Normalize line endings and whitespace in source files
diff --git a/portable/GCC/ARM7_AT91FR40008/port.c b/portable/GCC/ARM7_AT91FR40008/port.c
index 69376d5..d85e476 100644
--- a/portable/GCC/ARM7_AT91FR40008/port.c
+++ b/portable/GCC/ARM7_AT91FR40008/port.c
@@ -1,239 +1,238 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the Atmel AT91R40008
- * port.
- *
- * Components that can be compiled to either ARM or THUMB mode are
- * contained in this file. The ISR routines, which can only be compiled
- * to ARM mode are contained in portISR.c.
- *----------------------------------------------------------*/
-
-/* Standard includes. */
-#include <stdlib.h>
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Hardware specific definitions. */
-#include "AT91R40008.h"
-#include "pio.h"
-#include "aic.h"
-#include "tc.h"
-
-/* Constants required to setup the task context. */
-#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
-#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
-#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 )
-#define portTICK_PRIORITY_6 ( 6 )
-/*-----------------------------------------------------------*/
-
-/* Setup the timer to generate the tick interrupts. */
-static void prvSetupTimerInterrupt( void );
-
-/*
- * The scheduler can only be started from ARM mode, so
- * vPortISRStartFirstSTask() is defined in portISR.c.
- */
-extern void vPortISRStartFirstTask( void );
-
-/*-----------------------------------------------------------*/
-
-/*
- * Initialise the stack of a task to look exactly as if a call to
- * portSAVE_CONTEXT had been called.
- *
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-StackType_t *pxOriginalTOS;
-
- pxOriginalTOS = pxTopOfStack;
-
- /* To ensure asserts in tasks.c don't fail, although in this case the assert
- is not really required. */
- pxTopOfStack--;
-
- /* Setup the initial stack of the task. The stack is set exactly as
- expected by the portRESTORE_CONTEXT() macro. */
-
- /* First on the stack is the return address - which in this case is the
- start of the task. The offset is added to make the return address appear
- as it would within an IRQ ISR. */
- *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
- pxTopOfStack--;
-
- *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
- pxTopOfStack--;
-
- /* When the task starts is will expect to find the function parameter in
- R0. */
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack--;
-
- /* The last thing onto the stack is the status register, which is set for
- system mode, with interrupts enabled. */
- *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
-
- #ifdef THUMB_INTERWORK
- {
- /* We want the task to start in thumb mode. */
- *pxTopOfStack |= portTHUMB_MODE_BIT;
- }
- #endif
-
- pxTopOfStack--;
-
- /* Some optimisation levels use the stack differently to others. This
- means the interrupt flags cannot always be stored on the stack and will
- instead be stored in a variable, which is then saved as part of the
- tasks context. */
- *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
-
- return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
- /* Start the timer that generates the tick ISR. Interrupts are disabled
- here already. */
- prvSetupTimerInterrupt();
-
- /* Start the first task. */
- vPortISRStartFirstTask();
-
- /* Should not get here! */
- return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
- /* It is unlikely that the ARM port will require this function as there
- is nothing to return to. */
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the tick timer to generate the tick interrupts at the required frequency.
- */
-static void prvSetupTimerInterrupt( void )
-{
-volatile uint32_t ulDummy;
-
- /* Enable clock to the tick timer... */
- AT91C_BASE_PS->PS_PCER = portTIMER_CLK_ENABLE_BIT;
-
- /* Stop the tick timer... */
- portTIMER_REG_BASE_PTR->TC_CCR = TC_CLKDIS;
-
- /* Start with tick timer interrupts disabled... */
- portTIMER_REG_BASE_PTR->TC_IDR = 0xFFFFFFFF;
-
- /* Clear any pending tick timer interrupts... */
- ulDummy = portTIMER_REG_BASE_PTR->TC_SR;
-
- /* Store interrupt handler function address in tick timer vector register...
- The ISR installed depends on whether the preemptive or cooperative
- scheduler is being used. */
- #if configUSE_PREEMPTION == 1
- {
- extern void ( vPreemptiveTick )( void );
- AT91C_BASE_AIC->AIC_SVR[portTIMER_AIC_CHANNEL] = ( uint32_t ) vPreemptiveTick;
- }
- #else // else use cooperative scheduler
- {
- extern void ( vNonPreemptiveTick )( void );
- AT91C_BASE_AIC->AIC_SVR[portTIMER_AIC_CHANNEL] = ( uint32_t ) vNonPreemptiveTick;
- }
- #endif
-
- /* Tick timer interrupt level-sensitive, priority 6... */
- AT91C_BASE_AIC->AIC_SMR[ portTIMER_AIC_CHANNEL ] = AIC_SRCTYPE_INT_LEVEL_SENSITIVE | portTICK_PRIORITY_6;
-
- /* Enable the tick timer interrupt...
-
- First at timer level */
- portTIMER_REG_BASE_PTR->TC_IER = TC_CPCS;
-
- /* Then at the AIC level. */
- AT91C_BASE_AIC->AIC_IECR = (1 << portTIMER_AIC_CHANNEL);
-
- /* Calculate timer compare value to achieve the desired tick rate... */
- if( (configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 2) ) <= 0xFFFF )
- {
- /* The tick rate is fast enough for us to use the faster timer input
- clock (main clock / 2). */
- portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK2 | TC_BURST_NONE | TC_CPCTRG;
- portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 2);
- }
- else
- {
- /* We must use a slower timer input clock (main clock / 8) because the
- tick rate is too slow for the faster input clock. */
- portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK8 | TC_BURST_NONE | TC_CPCTRG;
- portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 8);
- }
-
- /* Start tick timer... */
- portTIMER_REG_BASE_PTR->TC_CCR = TC_SWTRG | TC_CLKEN;
-}
-/*-----------------------------------------------------------*/
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the Atmel AT91R40008
+ * port.
+ *
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in this file. The ISR routines, which can only be compiled
+ * to ARM mode are contained in portISR.c.
+ *----------------------------------------------------------*/
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Hardware specific definitions. */
+#include "AT91R40008.h"
+#include "pio.h"
+#include "aic.h"
+#include "tc.h"
+
+/* Constants required to setup the task context. */
+#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
+#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 )
+#define portTICK_PRIORITY_6 ( 6 )
+/*-----------------------------------------------------------*/
+
+/* Setup the timer to generate the tick interrupts. */
+static void prvSetupTimerInterrupt( void );
+
+/*
+ * The scheduler can only be started from ARM mode, so
+ * vPortISRStartFirstSTask() is defined in portISR.c.
+ */
+extern void vPortISRStartFirstTask( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been called.
+ *
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+StackType_t *pxOriginalTOS;
+
+ pxOriginalTOS = pxTopOfStack;
+
+ /* To ensure asserts in tasks.c don't fail, although in this case the assert
+ is not really required. */
+ pxTopOfStack--;
+
+ /* Setup the initial stack of the task. The stack is set exactly as
+ expected by the portRESTORE_CONTEXT() macro. */
+
+ /* First on the stack is the return address - which in this case is the
+ start of the task. The offset is added to make the return address appear
+ as it would within an IRQ ISR. */
+ *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
+ pxTopOfStack--;
+
+ *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+ pxTopOfStack--;
+
+ /* When the task starts is will expect to find the function parameter in
+ R0. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
+
+ /* The last thing onto the stack is the status register, which is set for
+ system mode, with interrupts enabled. */
+ *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+
+ #ifdef THUMB_INTERWORK
+ {
+ /* We want the task to start in thumb mode. */
+ *pxTopOfStack |= portTHUMB_MODE_BIT;
+ }
+ #endif
+
+ pxTopOfStack--;
+
+ /* Some optimisation levels use the stack differently to others. This
+ means the interrupt flags cannot always be stored on the stack and will
+ instead be stored in a variable, which is then saved as part of the
+ tasks context. */
+ *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
+
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ here already. */
+ prvSetupTimerInterrupt();
+
+ /* Start the first task. */
+ vPortISRStartFirstTask();
+
+ /* Should not get here! */
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+ /* It is unlikely that the ARM port will require this function as there
+ is nothing to return to. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the tick timer to generate the tick interrupts at the required frequency.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+volatile uint32_t ulDummy;
+
+ /* Enable clock to the tick timer... */
+ AT91C_BASE_PS->PS_PCER = portTIMER_CLK_ENABLE_BIT;
+
+ /* Stop the tick timer... */
+ portTIMER_REG_BASE_PTR->TC_CCR = TC_CLKDIS;
+
+ /* Start with tick timer interrupts disabled... */
+ portTIMER_REG_BASE_PTR->TC_IDR = 0xFFFFFFFF;
+
+ /* Clear any pending tick timer interrupts... */
+ ulDummy = portTIMER_REG_BASE_PTR->TC_SR;
+
+ /* Store interrupt handler function address in tick timer vector register...
+ The ISR installed depends on whether the preemptive or cooperative
+ scheduler is being used. */
+ #if configUSE_PREEMPTION == 1
+ {
+ extern void ( vPreemptiveTick )( void );
+ AT91C_BASE_AIC->AIC_SVR[portTIMER_AIC_CHANNEL] = ( uint32_t ) vPreemptiveTick;
+ }
+ #else // else use cooperative scheduler
+ {
+ extern void ( vNonPreemptiveTick )( void );
+ AT91C_BASE_AIC->AIC_SVR[portTIMER_AIC_CHANNEL] = ( uint32_t ) vNonPreemptiveTick;
+ }
+ #endif
+
+ /* Tick timer interrupt level-sensitive, priority 6... */
+ AT91C_BASE_AIC->AIC_SMR[ portTIMER_AIC_CHANNEL ] = AIC_SRCTYPE_INT_LEVEL_SENSITIVE | portTICK_PRIORITY_6;
+
+ /* Enable the tick timer interrupt...
+
+ First at timer level */
+ portTIMER_REG_BASE_PTR->TC_IER = TC_CPCS;
+
+ /* Then at the AIC level. */
+ AT91C_BASE_AIC->AIC_IECR = (1 << portTIMER_AIC_CHANNEL);
+
+ /* Calculate timer compare value to achieve the desired tick rate... */
+ if( (configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 2) ) <= 0xFFFF )
+ {
+ /* The tick rate is fast enough for us to use the faster timer input
+ clock (main clock / 2). */
+ portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK2 | TC_BURST_NONE | TC_CPCTRG;
+ portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 2);
+ }
+ else
+ {
+ /* We must use a slower timer input clock (main clock / 8) because the
+ tick rate is too slow for the faster input clock. */
+ portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK8 | TC_BURST_NONE | TC_CPCTRG;
+ portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 8);
+ }
+
+ /* Start tick timer... */
+ portTIMER_REG_BASE_PTR->TC_CCR = TC_SWTRG | TC_CLKEN;
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM7_AT91FR40008/portISR.c b/portable/GCC/ARM7_AT91FR40008/portISR.c
index e06fc57..15eba67 100644
--- a/portable/GCC/ARM7_AT91FR40008/portISR.c
+++ b/portable/GCC/ARM7_AT91FR40008/portISR.c
@@ -1,234 +1,233 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-
-/*-----------------------------------------------------------
- * Components that can be compiled to either ARM or THUMB mode are
- * contained in port.c The ISR routines, which can only be compiled
- * to ARM mode, are contained in this file.
- *----------------------------------------------------------*/
-
-/*
- Changes from V3.2.4
-
- + The assembler statements are now included in a single asm block rather
- than each line having its own asm block.
-*/
-
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Constants required to handle interrupts. */
-#define portCLEAR_AIC_INTERRUPT ( ( uint32_t ) 0 )
-
-/* Constants required to handle critical sections. */
-#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
-volatile uint32_t ulCriticalNesting = 9999UL;
-
-/*-----------------------------------------------------------*/
-
-/* ISR to handle manual context switches (from a call to taskYIELD()). */
-void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
-
-/*
- * The scheduler can only be started from ARM mode, hence the inclusion of this
- * function here.
- */
-void vPortISRStartFirstTask( void );
-/*-----------------------------------------------------------*/
-
-void vPortISRStartFirstTask( void )
-{
- /* Simply start the scheduler. This is included here as it can only be
- called from ARM mode. */
- portRESTORE_CONTEXT();
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Called by portYIELD() or taskYIELD() to manually force a context switch.
- *
- * When a context switch is performed from the task level the saved task
- * context is made to look as if it occurred from within the tick ISR. This
- * way the same restore context function can be used when restoring the context
- * saved from the ISR or that saved from a call to vPortYieldProcessor.
- */
-void vPortYieldProcessor( void )
-{
- /* Within an IRQ ISR the link register has an offset from the true return
- address, but an SWI ISR does not. Add the offset manually so the same
- ISR return code can be used in both cases. */
- asm volatile ( "ADD LR, LR, #4" );
-
- /* Perform the context switch. First save the context of the current task. */
- portSAVE_CONTEXT();
-
- /* Find the highest priority task that is ready to run. */
- vTaskSwitchContext();
-
- /* Restore the context of the new task. */
- portRESTORE_CONTEXT();
-}
-/*-----------------------------------------------------------*/
-
-/*
- * The ISR used for the scheduler tick depends on whether the cooperative or
- * the preemptive scheduler is being used.
- */
-
-#if configUSE_PREEMPTION == 0
-
- /* The cooperative scheduler requires a normal IRQ service routine to
- simply increment the system tick. */
- void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ")));
- void vNonPreemptiveTick( void )
- {
- static volatile uint32_t ulDummy;
-
- /* Clear tick timer interrupt indication. */
- ulDummy = portTIMER_REG_BASE_PTR->TC_SR;
-
- xTaskIncrementTick();
-
- /* Acknowledge the interrupt at AIC level... */
- AT91C_BASE_AIC->AIC_EOICR = portCLEAR_AIC_INTERRUPT;
- }
-
-#else /* else preemption is turned on */
-
- /* The preemptive scheduler is defined as "naked" as the full context is
- saved on entry as part of the context switch. */
- void vPreemptiveTick( void ) __attribute__((naked));
- void vPreemptiveTick( void )
- {
- /* Save the context of the interrupted task. */
- portSAVE_CONTEXT();
-
- /* WARNING - Do not use local (stack) variables here. Use globals
- if you must! */
- static volatile uint32_t ulDummy;
-
- /* Clear tick timer interrupt indication. */
- ulDummy = portTIMER_REG_BASE_PTR->TC_SR;
-
- /* Increment the RTOS tick count, then look for the highest priority
- task that is ready to run. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- vTaskSwitchContext();
- }
-
- /* Acknowledge the interrupt at AIC level... */
- AT91C_BASE_AIC->AIC_EOICR = portCLEAR_AIC_INTERRUPT;
-
- /* Restore the context of the new task. */
- portRESTORE_CONTEXT();
- }
-
-#endif
-/*-----------------------------------------------------------*/
-
-/*
- * The interrupt management utilities can only be called from ARM mode. When
- * THUMB_INTERWORK is defined the utilities are defined as functions here to
- * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then
- * the utilities are defined as macros in portmacro.h - as per other ports.
- */
-#ifdef THUMB_INTERWORK
-
- void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
- void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
-
- void vPortDisableInterruptsFromThumb( void )
- {
- asm volatile (
- "STMDB SP!, {R0} \n\t" /* Push R0. */
- "MRS R0, CPSR \n\t" /* Get CPSR. */
- "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
- "MSR CPSR, R0 \n\t" /* Write back modified value. */
- "LDMIA SP!, {R0} \n\t" /* Pop R0. */
- "BX R14" ); /* Return back to thumb. */
- }
-
- void vPortEnableInterruptsFromThumb( void )
- {
- asm volatile (
- "STMDB SP!, {R0} \n\t" /* Push R0. */
- "MRS R0, CPSR \n\t" /* Get CPSR. */
- "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
- "MSR CPSR, R0 \n\t" /* Write back modified value. */
- "LDMIA SP!, {R0} \n\t" /* Pop R0. */
- "BX R14" ); /* Return back to thumb. */
- }
-
-#endif /* THUMB_INTERWORK */
-
-/* The code generated by the GCC compiler uses the stack in different ways at
-different optimisation levels. The interrupt flags can therefore not always
-be saved to the stack. Instead the critical section nesting level is stored
-in a variable, which is then saved as part of the stack context. */
-void vPortEnterCritical( void )
-{
- /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
- asm volatile (
- "STMDB SP!, {R0} \n\t" /* Push R0. */
- "MRS R0, CPSR \n\t" /* Get CPSR. */
- "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
- "MSR CPSR, R0 \n\t" /* Write back modified value. */
- "LDMIA SP!, {R0}" ); /* Pop R0. */
-
- /* Now interrupts are disabled ulCriticalNesting can be accessed
- directly. Increment ulCriticalNesting to keep a count of how many times
- portENTER_CRITICAL() has been called. */
- ulCriticalNesting++;
-}
-
-void vPortExitCritical( void )
-{
- if( ulCriticalNesting > portNO_CRITICAL_NESTING )
- {
- /* Decrement the nesting count as we are leaving a critical section. */
- ulCriticalNesting--;
-
- /* If the nesting level has reached zero then interrupts should be
- re-enabled. */
- if( ulCriticalNesting == portNO_CRITICAL_NESTING )
- {
- /* Enable interrupts as per portEXIT_CRITICAL(). */
- asm volatile (
- "STMDB SP!, {R0} \n\t" /* Push R0. */
- "MRS R0, CPSR \n\t" /* Get CPSR. */
- "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
- "MSR CPSR, R0 \n\t" /* Write back modified value. */
- "LDMIA SP!, {R0}" ); /* Pop R0. */
- }
- }
-}
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+/*-----------------------------------------------------------
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in port.c The ISR routines, which can only be compiled
+ * to ARM mode, are contained in this file.
+ *----------------------------------------------------------*/
+
+/*
+ Changes from V3.2.4
+
+ + The assembler statements are now included in a single asm block rather
+ than each line having its own asm block.
+*/
+
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to handle interrupts. */
+#define portCLEAR_AIC_INTERRUPT ( ( uint32_t ) 0 )
+
+/* Constants required to handle critical sections. */
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
+volatile uint32_t ulCriticalNesting = 9999UL;
+
+/*-----------------------------------------------------------*/
+
+/* ISR to handle manual context switches (from a call to taskYIELD()). */
+void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
+
+/*
+ * The scheduler can only be started from ARM mode, hence the inclusion of this
+ * function here.
+ */
+void vPortISRStartFirstTask( void );
+/*-----------------------------------------------------------*/
+
+void vPortISRStartFirstTask( void )
+{
+ /* Simply start the scheduler. This is included here as it can only be
+ called from ARM mode. */
+ portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Called by portYIELD() or taskYIELD() to manually force a context switch.
+ *
+ * When a context switch is performed from the task level the saved task
+ * context is made to look as if it occurred from within the tick ISR. This
+ * way the same restore context function can be used when restoring the context
+ * saved from the ISR or that saved from a call to vPortYieldProcessor.
+ */
+void vPortYieldProcessor( void )
+{
+ /* Within an IRQ ISR the link register has an offset from the true return
+ address, but an SWI ISR does not. Add the offset manually so the same
+ ISR return code can be used in both cases. */
+ asm volatile ( "ADD LR, LR, #4" );
+
+ /* Perform the context switch. First save the context of the current task. */
+ portSAVE_CONTEXT();
+
+ /* Find the highest priority task that is ready to run. */
+ vTaskSwitchContext();
+
+ /* Restore the context of the new task. */
+ portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * The ISR used for the scheduler tick depends on whether the cooperative or
+ * the preemptive scheduler is being used.
+ */
+
+#if configUSE_PREEMPTION == 0
+
+ /* The cooperative scheduler requires a normal IRQ service routine to
+ simply increment the system tick. */
+ void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ")));
+ void vNonPreemptiveTick( void )
+ {
+ static volatile uint32_t ulDummy;
+
+ /* Clear tick timer interrupt indication. */
+ ulDummy = portTIMER_REG_BASE_PTR->TC_SR;
+
+ xTaskIncrementTick();
+
+ /* Acknowledge the interrupt at AIC level... */
+ AT91C_BASE_AIC->AIC_EOICR = portCLEAR_AIC_INTERRUPT;
+ }
+
+#else /* else preemption is turned on */
+
+ /* The preemptive scheduler is defined as "naked" as the full context is
+ saved on entry as part of the context switch. */
+ void vPreemptiveTick( void ) __attribute__((naked));
+ void vPreemptiveTick( void )
+ {
+ /* Save the context of the interrupted task. */
+ portSAVE_CONTEXT();
+
+ /* WARNING - Do not use local (stack) variables here. Use globals
+ if you must! */
+ static volatile uint32_t ulDummy;
+
+ /* Clear tick timer interrupt indication. */
+ ulDummy = portTIMER_REG_BASE_PTR->TC_SR;
+
+ /* Increment the RTOS tick count, then look for the highest priority
+ task that is ready to run. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ vTaskSwitchContext();
+ }
+
+ /* Acknowledge the interrupt at AIC level... */
+ AT91C_BASE_AIC->AIC_EOICR = portCLEAR_AIC_INTERRUPT;
+
+ /* Restore the context of the new task. */
+ portRESTORE_CONTEXT();
+ }
+
+#endif
+/*-----------------------------------------------------------*/
+
+/*
+ * The interrupt management utilities can only be called from ARM mode. When
+ * THUMB_INTERWORK is defined the utilities are defined as functions here to
+ * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then
+ * the utilities are defined as macros in portmacro.h - as per other ports.
+ */
+#ifdef THUMB_INTERWORK
+
+ void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+ void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+
+ void vPortDisableInterruptsFromThumb( void )
+ {
+ asm volatile (
+ "STMDB SP!, {R0} \n\t" /* Push R0. */
+ "MRS R0, CPSR \n\t" /* Get CPSR. */
+ "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */
+ "LDMIA SP!, {R0} \n\t" /* Pop R0. */
+ "BX R14" ); /* Return back to thumb. */
+ }
+
+ void vPortEnableInterruptsFromThumb( void )
+ {
+ asm volatile (
+ "STMDB SP!, {R0} \n\t" /* Push R0. */
+ "MRS R0, CPSR \n\t" /* Get CPSR. */
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */
+ "LDMIA SP!, {R0} \n\t" /* Pop R0. */
+ "BX R14" ); /* Return back to thumb. */
+ }
+
+#endif /* THUMB_INTERWORK */
+
+/* The code generated by the GCC compiler uses the stack in different ways at
+different optimisation levels. The interrupt flags can therefore not always
+be saved to the stack. Instead the critical section nesting level is stored
+in a variable, which is then saved as part of the stack context. */
+void vPortEnterCritical( void )
+{
+ /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
+ asm volatile (
+ "STMDB SP!, {R0} \n\t" /* Push R0. */
+ "MRS R0, CPSR \n\t" /* Get CPSR. */
+ "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */
+ "LDMIA SP!, {R0}" ); /* Pop R0. */
+
+ /* Now interrupts are disabled ulCriticalNesting can be accessed
+ directly. Increment ulCriticalNesting to keep a count of how many times
+ portENTER_CRITICAL() has been called. */
+ ulCriticalNesting++;
+}
+
+void vPortExitCritical( void )
+{
+ if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+ {
+ /* Decrement the nesting count as we are leaving a critical section. */
+ ulCriticalNesting--;
+
+ /* If the nesting level has reached zero then interrupts should be
+ re-enabled. */
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+ {
+ /* Enable interrupts as per portEXIT_CRITICAL(). */
+ asm volatile (
+ "STMDB SP!, {R0} \n\t" /* Push R0. */
+ "MRS R0, CPSR \n\t" /* Get CPSR. */
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */
+ "LDMIA SP!, {R0}" ); /* Pop R0. */
+ }
+ }
+}
diff --git a/portable/GCC/ARM7_AT91FR40008/portmacro.h b/portable/GCC/ARM7_AT91FR40008/portmacro.h
index 50d20ac..8a1666e 100644
--- a/portable/GCC/ARM7_AT91FR40008/portmacro.h
+++ b/portable/GCC/ARM7_AT91FR40008/portmacro.h
@@ -1,256 +1,255 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*
- Changes from V3.2.3
-
- + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
-
- Changes from V3.2.4
-
- + Removed the use of the %0 parameter within the assembler macros and
- replaced them with hard coded registers. This will ensure the
- assembler does not select the link register as the temp register as
- was occasionally happening previously.
-
- + The assembler statements are now included in a single asm block rather
- than each line having its own asm block.
-
- Changes from V4.5.0
-
- + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
- and replaced them with portYIELD_FROM_ISR() macro. Application code
- should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
- macros as per the V4.5.1 demo code.
-*/
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT short
-#define portSTACK_TYPE uint32_t
-#define portBASE_TYPE long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
-#else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portSTACK_GROWTH ( -1 )
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT 8
-#define portYIELD() asm volatile ( "SWI 0" )
-#define portNOP() asm volatile ( "NOP" )
-
-/*
- * These define the timer to use for generating the tick interrupt.
- * They are put in this file so they can be shared between "port.c"
- * and "portisr.c".
- */
-#define portTIMER_REG_BASE_PTR AT91C_BASE_TC0
-#define portTIMER_CLK_ENABLE_BIT AT91C_PS_TC0
-#define portTIMER_AIC_CHANNEL ( ( uint32_t ) 4 )
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-
-/*
- * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR
- * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but
- * are included here for efficiency. An attempt to call one from
- * THUMB mode code will result in a compile time error.
- */
-
-#define portRESTORE_CONTEXT() \
-{ \
-extern volatile void * volatile pxCurrentTCB; \
-extern volatile uint32_t ulCriticalNesting; \
- \
- /* Set the LR to the task stack. */ \
- asm volatile ( \
- "LDR R0, =pxCurrentTCB \n\t" \
- "LDR R0, [R0] \n\t" \
- "LDR LR, [R0] \n\t" \
- \
- /* The critical nesting depth is the first item on the stack. */ \
- /* Load it into the ulCriticalNesting variable. */ \
- "LDR R0, =ulCriticalNesting \n\t" \
- "LDMFD LR!, {R1} \n\t" \
- "STR R1, [R0] \n\t" \
- \
- /* Get the SPSR from the stack. */ \
- "LDMFD LR!, {R0} \n\t" \
- "MSR SPSR, R0 \n\t" \
- \
- /* Restore all system mode registers for the task. */ \
- "LDMFD LR, {R0-R14}^ \n\t" \
- "NOP \n\t" \
- \
- /* Restore the return address. */ \
- "LDR LR, [LR, #+60] \n\t" \
- \
- /* And return - correcting the offset in the LR to obtain the */ \
- /* correct address. */ \
- "SUBS PC, LR, #4 \n\t" \
- ); \
- ( void ) ulCriticalNesting; \
- ( void ) pxCurrentTCB; \
-}
-/*-----------------------------------------------------------*/
-
-#define portSAVE_CONTEXT() \
-{ \
-extern volatile void * volatile pxCurrentTCB; \
-extern volatile uint32_t ulCriticalNesting; \
- \
- /* Push R0 as we are going to use the register. */ \
- asm volatile ( \
- "STMDB SP!, {R0} \n\t" \
- \
- /* Set R0 to point to the task stack pointer. */ \
- "STMDB SP,{SP}^ \n\t" \
- "NOP \n\t" \
- "SUB SP, SP, #4 \n\t" \
- "LDMIA SP!,{R0} \n\t" \
- \
- /* Push the return address onto the stack. */ \
- "STMDB R0!, {LR} \n\t" \
- \
- /* Now we have saved LR we can use it instead of R0. */ \
- "MOV LR, R0 \n\t" \
- \
- /* Pop R0 so we can save it onto the system mode stack. */ \
- "LDMIA SP!, {R0} \n\t" \
- \
- /* Push all the system mode registers onto the task stack. */ \
- "STMDB LR,{R0-LR}^ \n\t" \
- "NOP \n\t" \
- "SUB LR, LR, #60 \n\t" \
- \
- /* Push the SPSR onto the task stack. */ \
- "MRS R0, SPSR \n\t" \
- "STMDB LR!, {R0} \n\t" \
- \
- "LDR R0, =ulCriticalNesting \n\t" \
- "LDR R0, [R0] \n\t" \
- "STMDB LR!, {R0} \n\t" \
- \
- /* Store the new top of stack for the task. */ \
- "LDR R0, =pxCurrentTCB \n\t" \
- "LDR R0, [R0] \n\t" \
- "STR LR, [R0] \n\t" \
- ); \
- ( void ) ulCriticalNesting; \
- ( void ) pxCurrentTCB; \
-}
-
-#define portYIELD_FROM_ISR() vTaskSwitchContext()
-
-/* Critical section handling. */
-
-/*
- * The interrupt management utilities can only be called from ARM mode. When
- * THUMB_INTERWORK is defined the utilities are defined as functions in
- * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not
- * defined then the utilities are defined as macros here - as per other ports.
- */
-
-#ifdef THUMB_INTERWORK
-
- extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
- extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
-
- #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb()
- #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb()
-
-#else
-
- #define portDISABLE_INTERRUPTS() \
- asm volatile ( \
- "STMDB SP!, {R0} \n\t" /* Push R0. */ \
- "MRS R0, CPSR \n\t" /* Get CPSR. */ \
- "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \
- "MSR CPSR, R0 \n\t" /* Write back modified value. */ \
- "LDMIA SP!, {R0} " ) /* Pop R0. */
-
- #define portENABLE_INTERRUPTS() \
- asm volatile ( \
- "STMDB SP!, {R0} \n\t" /* Push R0. */ \
- "MRS R0, CPSR \n\t" /* Get CPSR. */ \
- "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \
- "MSR CPSR, R0 \n\t" /* Write back modified value. */ \
- "LDMIA SP!, {R0} " ) /* Pop R0. */
-
-#endif /* THUMB_INTERWORK */
-
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-
-#define portENTER_CRITICAL() vPortEnterCritical();
-#define portEXIT_CRITICAL() vPortExitCritical();
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*
+ Changes from V3.2.3
+
+ + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
+
+ Changes from V3.2.4
+
+ + Removed the use of the %0 parameter within the assembler macros and
+ replaced them with hard coded registers. This will ensure the
+ assembler does not select the link register as the temp register as
+ was occasionally happening previously.
+
+ + The assembler statements are now included in a single asm block rather
+ than each line having its own asm block.
+
+ Changes from V4.5.0
+
+ + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
+ and replaced them with portYIELD_FROM_ISR() macro. Application code
+ should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
+ macros as per the V4.5.1 demo code.
+*/
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portYIELD() asm volatile ( "SWI 0" )
+#define portNOP() asm volatile ( "NOP" )
+
+/*
+ * These define the timer to use for generating the tick interrupt.
+ * They are put in this file so they can be shared between "port.c"
+ * and "portisr.c".
+ */
+#define portTIMER_REG_BASE_PTR AT91C_BASE_TC0
+#define portTIMER_CLK_ENABLE_BIT AT91C_PS_TC0
+#define portTIMER_AIC_CHANNEL ( ( uint32_t ) 4 )
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+/*
+ * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR
+ * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but
+ * are included here for efficiency. An attempt to call one from
+ * THUMB mode code will result in a compile time error.
+ */
+
+#define portRESTORE_CONTEXT() \
+{ \
+extern volatile void * volatile pxCurrentTCB; \
+extern volatile uint32_t ulCriticalNesting; \
+ \
+ /* Set the LR to the task stack. */ \
+ asm volatile ( \
+ "LDR R0, =pxCurrentTCB \n\t" \
+ "LDR R0, [R0] \n\t" \
+ "LDR LR, [R0] \n\t" \
+ \
+ /* The critical nesting depth is the first item on the stack. */ \
+ /* Load it into the ulCriticalNesting variable. */ \
+ "LDR R0, =ulCriticalNesting \n\t" \
+ "LDMFD LR!, {R1} \n\t" \
+ "STR R1, [R0] \n\t" \
+ \
+ /* Get the SPSR from the stack. */ \
+ "LDMFD LR!, {R0} \n\t" \
+ "MSR SPSR, R0 \n\t" \
+ \
+ /* Restore all system mode registers for the task. */ \
+ "LDMFD LR, {R0-R14}^ \n\t" \
+ "NOP \n\t" \
+ \
+ /* Restore the return address. */ \
+ "LDR LR, [LR, #+60] \n\t" \
+ \
+ /* And return - correcting the offset in the LR to obtain the */ \
+ /* correct address. */ \
+ "SUBS PC, LR, #4 \n\t" \
+ ); \
+ ( void ) ulCriticalNesting; \
+ ( void ) pxCurrentTCB; \
+}
+/*-----------------------------------------------------------*/
+
+#define portSAVE_CONTEXT() \
+{ \
+extern volatile void * volatile pxCurrentTCB; \
+extern volatile uint32_t ulCriticalNesting; \
+ \
+ /* Push R0 as we are going to use the register. */ \
+ asm volatile ( \
+ "STMDB SP!, {R0} \n\t" \
+ \
+ /* Set R0 to point to the task stack pointer. */ \
+ "STMDB SP,{SP}^ \n\t" \
+ "NOP \n\t" \
+ "SUB SP, SP, #4 \n\t" \
+ "LDMIA SP!,{R0} \n\t" \
+ \
+ /* Push the return address onto the stack. */ \
+ "STMDB R0!, {LR} \n\t" \
+ \
+ /* Now we have saved LR we can use it instead of R0. */ \
+ "MOV LR, R0 \n\t" \
+ \
+ /* Pop R0 so we can save it onto the system mode stack. */ \
+ "LDMIA SP!, {R0} \n\t" \
+ \
+ /* Push all the system mode registers onto the task stack. */ \
+ "STMDB LR,{R0-LR}^ \n\t" \
+ "NOP \n\t" \
+ "SUB LR, LR, #60 \n\t" \
+ \
+ /* Push the SPSR onto the task stack. */ \
+ "MRS R0, SPSR \n\t" \
+ "STMDB LR!, {R0} \n\t" \
+ \
+ "LDR R0, =ulCriticalNesting \n\t" \
+ "LDR R0, [R0] \n\t" \
+ "STMDB LR!, {R0} \n\t" \
+ \
+ /* Store the new top of stack for the task. */ \
+ "LDR R0, =pxCurrentTCB \n\t" \
+ "LDR R0, [R0] \n\t" \
+ "STR LR, [R0] \n\t" \
+ ); \
+ ( void ) ulCriticalNesting; \
+ ( void ) pxCurrentTCB; \
+}
+
+#define portYIELD_FROM_ISR() vTaskSwitchContext()
+
+/* Critical section handling. */
+
+/*
+ * The interrupt management utilities can only be called from ARM mode. When
+ * THUMB_INTERWORK is defined the utilities are defined as functions in
+ * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not
+ * defined then the utilities are defined as macros here - as per other ports.
+ */
+
+#ifdef THUMB_INTERWORK
+
+ extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+ extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+
+ #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb()
+ #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb()
+
+#else
+
+ #define portDISABLE_INTERRUPTS() \
+ asm volatile ( \
+ "STMDB SP!, {R0} \n\t" /* Push R0. */ \
+ "MRS R0, CPSR \n\t" /* Get CPSR. */ \
+ "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */ \
+ "LDMIA SP!, {R0} " ) /* Pop R0. */
+
+ #define portENABLE_INTERRUPTS() \
+ asm volatile ( \
+ "STMDB SP!, {R0} \n\t" /* Push R0. */ \
+ "MRS R0, CPSR \n\t" /* Get CPSR. */ \
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */ \
+ "LDMIA SP!, {R0} " ) /* Pop R0. */
+
+#endif /* THUMB_INTERWORK */
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portENTER_CRITICAL() vPortEnterCritical();
+#define portEXIT_CRITICAL() vPortExitCritical();
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h b/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h
index a14279e..d44cb28 100644
--- a/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h
+++ b/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h
@@ -1,2731 +1,2731 @@
-// ----------------------------------------------------------------------------
-// ATMEL Microcontroller Software Support - ROUSSET -
-// ----------------------------------------------------------------------------
-// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// ----------------------------------------------------------------------------
-// File Name : AT91SAM7X256.h
-// Object : AT91SAM7X256 definitions
-// Generated : AT91 SW Application Group 05/20/2005 (16:22:29)
-//
-// CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005//
-// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005//
-// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
-// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005//
-// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005//
-// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
-// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
-// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
-// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005//
-// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004//
-// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004//
-// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004//
-// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005//
-// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005//
-// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
-// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
-// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
-// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
-// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
-// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
-// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005//
-// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005//
-// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
-// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005//
-// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
-// ----------------------------------------------------------------------------
-
-#ifndef AT91SAM7X256_H
-#define AT91SAM7X256_H
-
-typedef volatile unsigned int AT91_REG;// Hardware register definition
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR System Peripherals
-// *****************************************************************************
-typedef struct _AT91S_SYS {
- AT91_REG AIC_SMR[32]; // Source Mode Register
- AT91_REG AIC_SVR[32]; // Source Vector Register
- AT91_REG AIC_IVR; // IRQ Vector Register
- AT91_REG AIC_FVR; // FIQ Vector Register
- AT91_REG AIC_ISR; // Interrupt Status Register
- AT91_REG AIC_IPR; // Interrupt Pending Register
- AT91_REG AIC_IMR; // Interrupt Mask Register
- AT91_REG AIC_CISR; // Core Interrupt Status Register
- AT91_REG Reserved0[2]; //
- AT91_REG AIC_IECR; // Interrupt Enable Command Register
- AT91_REG AIC_IDCR; // Interrupt Disable Command Register
- AT91_REG AIC_ICCR; // Interrupt Clear Command Register
- AT91_REG AIC_ISCR; // Interrupt Set Command Register
- AT91_REG AIC_EOICR; // End of Interrupt Command Register
- AT91_REG AIC_SPU; // Spurious Vector Register
- AT91_REG AIC_DCR; // Debug Control Register (Protect)
- AT91_REG Reserved1[1]; //
- AT91_REG AIC_FFER; // Fast Forcing Enable Register
- AT91_REG AIC_FFDR; // Fast Forcing Disable Register
- AT91_REG AIC_FFSR; // Fast Forcing Status Register
- AT91_REG Reserved2[45]; //
- AT91_REG DBGU_CR; // Control Register
- AT91_REG DBGU_MR; // Mode Register
- AT91_REG DBGU_IER; // Interrupt Enable Register
- AT91_REG DBGU_IDR; // Interrupt Disable Register
- AT91_REG DBGU_IMR; // Interrupt Mask Register
- AT91_REG DBGU_CSR; // Channel Status Register
- AT91_REG DBGU_RHR; // Receiver Holding Register
- AT91_REG DBGU_THR; // Transmitter Holding Register
- AT91_REG DBGU_BRGR; // Baud Rate Generator Register
- AT91_REG Reserved3[7]; //
- AT91_REG DBGU_CIDR; // Chip ID Register
- AT91_REG DBGU_EXID; // Chip ID Extension Register
- AT91_REG DBGU_FNTR; // Force NTRST Register
- AT91_REG Reserved4[45]; //
- AT91_REG DBGU_RPR; // Receive Pointer Register
- AT91_REG DBGU_RCR; // Receive Counter Register
- AT91_REG DBGU_TPR; // Transmit Pointer Register
- AT91_REG DBGU_TCR; // Transmit Counter Register
- AT91_REG DBGU_RNPR; // Receive Next Pointer Register
- AT91_REG DBGU_RNCR; // Receive Next Counter Register
- AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
- AT91_REG DBGU_TNCR; // Transmit Next Counter Register
- AT91_REG DBGU_PTCR; // PDC Transfer Control Register
- AT91_REG DBGU_PTSR; // PDC Transfer Status Register
- AT91_REG Reserved5[54]; //
- AT91_REG PIOA_PER; // PIO Enable Register
- AT91_REG PIOA_PDR; // PIO Disable Register
- AT91_REG PIOA_PSR; // PIO Status Register
- AT91_REG Reserved6[1]; //
- AT91_REG PIOA_OER; // Output Enable Register
- AT91_REG PIOA_ODR; // Output Disable Registerr
- AT91_REG PIOA_OSR; // Output Status Register
- AT91_REG Reserved7[1]; //
- AT91_REG PIOA_IFER; // Input Filter Enable Register
- AT91_REG PIOA_IFDR; // Input Filter Disable Register
- AT91_REG PIOA_IFSR; // Input Filter Status Register
- AT91_REG Reserved8[1]; //
- AT91_REG PIOA_SODR; // Set Output Data Register
- AT91_REG PIOA_CODR; // Clear Output Data Register
- AT91_REG PIOA_ODSR; // Output Data Status Register
- AT91_REG PIOA_PDSR; // Pin Data Status Register
- AT91_REG PIOA_IER; // Interrupt Enable Register
- AT91_REG PIOA_IDR; // Interrupt Disable Register
- AT91_REG PIOA_IMR; // Interrupt Mask Register
- AT91_REG PIOA_ISR; // Interrupt Status Register
- AT91_REG PIOA_MDER; // Multi-driver Enable Register
- AT91_REG PIOA_MDDR; // Multi-driver Disable Register
- AT91_REG PIOA_MDSR; // Multi-driver Status Register
- AT91_REG Reserved9[1]; //
- AT91_REG PIOA_PPUDR; // Pull-up Disable Register
- AT91_REG PIOA_PPUER; // Pull-up Enable Register
- AT91_REG PIOA_PPUSR; // Pull-up Status Register
- AT91_REG Reserved10[1]; //
- AT91_REG PIOA_ASR; // Select A Register
- AT91_REG PIOA_BSR; // Select B Register
- AT91_REG PIOA_ABSR; // AB Select Status Register
- AT91_REG Reserved11[9]; //
- AT91_REG PIOA_OWER; // Output Write Enable Register
- AT91_REG PIOA_OWDR; // Output Write Disable Register
- AT91_REG PIOA_OWSR; // Output Write Status Register
- AT91_REG Reserved12[85]; //
- AT91_REG PIOB_PER; // PIO Enable Register
- AT91_REG PIOB_PDR; // PIO Disable Register
- AT91_REG PIOB_PSR; // PIO Status Register
- AT91_REG Reserved13[1]; //
- AT91_REG PIOB_OER; // Output Enable Register
- AT91_REG PIOB_ODR; // Output Disable Registerr
- AT91_REG PIOB_OSR; // Output Status Register
- AT91_REG Reserved14[1]; //
- AT91_REG PIOB_IFER; // Input Filter Enable Register
- AT91_REG PIOB_IFDR; // Input Filter Disable Register
- AT91_REG PIOB_IFSR; // Input Filter Status Register
- AT91_REG Reserved15[1]; //
- AT91_REG PIOB_SODR; // Set Output Data Register
- AT91_REG PIOB_CODR; // Clear Output Data Register
- AT91_REG PIOB_ODSR; // Output Data Status Register
- AT91_REG PIOB_PDSR; // Pin Data Status Register
- AT91_REG PIOB_IER; // Interrupt Enable Register
- AT91_REG PIOB_IDR; // Interrupt Disable Register
- AT91_REG PIOB_IMR; // Interrupt Mask Register
- AT91_REG PIOB_ISR; // Interrupt Status Register
- AT91_REG PIOB_MDER; // Multi-driver Enable Register
- AT91_REG PIOB_MDDR; // Multi-driver Disable Register
- AT91_REG PIOB_MDSR; // Multi-driver Status Register
- AT91_REG Reserved16[1]; //
- AT91_REG PIOB_PPUDR; // Pull-up Disable Register
- AT91_REG PIOB_PPUER; // Pull-up Enable Register
- AT91_REG PIOB_PPUSR; // Pull-up Status Register
- AT91_REG Reserved17[1]; //
- AT91_REG PIOB_ASR; // Select A Register
- AT91_REG PIOB_BSR; // Select B Register
- AT91_REG PIOB_ABSR; // AB Select Status Register
- AT91_REG Reserved18[9]; //
- AT91_REG PIOB_OWER; // Output Write Enable Register
- AT91_REG PIOB_OWDR; // Output Write Disable Register
- AT91_REG PIOB_OWSR; // Output Write Status Register
- AT91_REG Reserved19[341]; //
- AT91_REG PMC_SCER; // System Clock Enable Register
- AT91_REG PMC_SCDR; // System Clock Disable Register
- AT91_REG PMC_SCSR; // System Clock Status Register
- AT91_REG Reserved20[1]; //
- AT91_REG PMC_PCER; // Peripheral Clock Enable Register
- AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
- AT91_REG PMC_PCSR; // Peripheral Clock Status Register
- AT91_REG Reserved21[1]; //
- AT91_REG PMC_MOR; // Main Oscillator Register
- AT91_REG PMC_MCFR; // Main Clock Frequency Register
- AT91_REG Reserved22[1]; //
- AT91_REG PMC_PLLR; // PLL Register
- AT91_REG PMC_MCKR; // Master Clock Register
- AT91_REG Reserved23[3]; //
- AT91_REG PMC_PCKR[4]; // Programmable Clock Register
- AT91_REG Reserved24[4]; //
- AT91_REG PMC_IER; // Interrupt Enable Register
- AT91_REG PMC_IDR; // Interrupt Disable Register
- AT91_REG PMC_SR; // Status Register
- AT91_REG PMC_IMR; // Interrupt Mask Register
- AT91_REG Reserved25[36]; //
- AT91_REG RSTC_RCR; // Reset Control Register
- AT91_REG RSTC_RSR; // Reset Status Register
- AT91_REG RSTC_RMR; // Reset Mode Register
- AT91_REG Reserved26[5]; //
- AT91_REG RTTC_RTMR; // Real-time Mode Register
- AT91_REG RTTC_RTAR; // Real-time Alarm Register
- AT91_REG RTTC_RTVR; // Real-time Value Register
- AT91_REG RTTC_RTSR; // Real-time Status Register
- AT91_REG PITC_PIMR; // Period Interval Mode Register
- AT91_REG PITC_PISR; // Period Interval Status Register
- AT91_REG PITC_PIVR; // Period Interval Value Register
- AT91_REG PITC_PIIR; // Period Interval Image Register
- AT91_REG WDTC_WDCR; // Watchdog Control Register
- AT91_REG WDTC_WDMR; // Watchdog Mode Register
- AT91_REG WDTC_WDSR; // Watchdog Status Register
- AT91_REG Reserved27[5]; //
- AT91_REG VREG_MR; // Voltage Regulator Mode Register
-} AT91S_SYS, *AT91PS_SYS;
-
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
-// *****************************************************************************
-typedef struct _AT91S_AIC {
- AT91_REG AIC_SMR[32]; // Source Mode Register
- AT91_REG AIC_SVR[32]; // Source Vector Register
- AT91_REG AIC_IVR; // IRQ Vector Register
- AT91_REG AIC_FVR; // FIQ Vector Register
- AT91_REG AIC_ISR; // Interrupt Status Register
- AT91_REG AIC_IPR; // Interrupt Pending Register
- AT91_REG AIC_IMR; // Interrupt Mask Register
- AT91_REG AIC_CISR; // Core Interrupt Status Register
- AT91_REG Reserved0[2]; //
- AT91_REG AIC_IECR; // Interrupt Enable Command Register
- AT91_REG AIC_IDCR; // Interrupt Disable Command Register
- AT91_REG AIC_ICCR; // Interrupt Clear Command Register
- AT91_REG AIC_ISCR; // Interrupt Set Command Register
- AT91_REG AIC_EOICR; // End of Interrupt Command Register
- AT91_REG AIC_SPU; // Spurious Vector Register
- AT91_REG AIC_DCR; // Debug Control Register (Protect)
- AT91_REG Reserved1[1]; //
- AT91_REG AIC_FFER; // Fast Forcing Enable Register
- AT91_REG AIC_FFDR; // Fast Forcing Disable Register
- AT91_REG AIC_FFSR; // Fast Forcing Status Register
-} AT91S_AIC, *AT91PS_AIC;
-
-// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
-#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level
-#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level
-#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level
-#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type
-#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive
-#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive
-#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered
-#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered
-#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
-#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
-// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
-#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status
-#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status
-// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
-#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode
-#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Peripheral DMA Controller
-// *****************************************************************************
-typedef struct _AT91S_PDC {
- AT91_REG PDC_RPR; // Receive Pointer Register
- AT91_REG PDC_RCR; // Receive Counter Register
- AT91_REG PDC_TPR; // Transmit Pointer Register
- AT91_REG PDC_TCR; // Transmit Counter Register
- AT91_REG PDC_RNPR; // Receive Next Pointer Register
- AT91_REG PDC_RNCR; // Receive Next Counter Register
- AT91_REG PDC_TNPR; // Transmit Next Pointer Register
- AT91_REG PDC_TNCR; // Transmit Next Counter Register
- AT91_REG PDC_PTCR; // PDC Transfer Control Register
- AT91_REG PDC_PTSR; // PDC Transfer Status Register
-} AT91S_PDC, *AT91PS_PDC;
-
-// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
-#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable
-#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable
-#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable
-#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable
-// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Debug Unit
-// *****************************************************************************
-typedef struct _AT91S_DBGU {
- AT91_REG DBGU_CR; // Control Register
- AT91_REG DBGU_MR; // Mode Register
- AT91_REG DBGU_IER; // Interrupt Enable Register
- AT91_REG DBGU_IDR; // Interrupt Disable Register
- AT91_REG DBGU_IMR; // Interrupt Mask Register
- AT91_REG DBGU_CSR; // Channel Status Register
- AT91_REG DBGU_RHR; // Receiver Holding Register
- AT91_REG DBGU_THR; // Transmitter Holding Register
- AT91_REG DBGU_BRGR; // Baud Rate Generator Register
- AT91_REG Reserved0[7]; //
- AT91_REG DBGU_CIDR; // Chip ID Register
- AT91_REG DBGU_EXID; // Chip ID Extension Register
- AT91_REG DBGU_FNTR; // Force NTRST Register
- AT91_REG Reserved1[45]; //
- AT91_REG DBGU_RPR; // Receive Pointer Register
- AT91_REG DBGU_RCR; // Receive Counter Register
- AT91_REG DBGU_TPR; // Transmit Pointer Register
- AT91_REG DBGU_TCR; // Transmit Counter Register
- AT91_REG DBGU_RNPR; // Receive Next Pointer Register
- AT91_REG DBGU_RNCR; // Receive Next Counter Register
- AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
- AT91_REG DBGU_TNCR; // Transmit Next Counter Register
- AT91_REG DBGU_PTCR; // PDC Transfer Control Register
- AT91_REG DBGU_PTSR; // PDC Transfer Status Register
-} AT91S_DBGU, *AT91PS_DBGU;
-
-// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver
-#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter
-#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable
-#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable
-#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable
-#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable
-#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits
-// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type
-#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity
-#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity
-#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space)
-#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
-#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity
-#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode
-#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
-#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt
-#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt
-#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
-#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt
-#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt
-#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt
-#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt
-#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt
-#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
-#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
-#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
-#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
-// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
-// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
-#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
-// *****************************************************************************
-typedef struct _AT91S_PIO {
- AT91_REG PIO_PER; // PIO Enable Register
- AT91_REG PIO_PDR; // PIO Disable Register
- AT91_REG PIO_PSR; // PIO Status Register
- AT91_REG Reserved0[1]; //
- AT91_REG PIO_OER; // Output Enable Register
- AT91_REG PIO_ODR; // Output Disable Registerr
- AT91_REG PIO_OSR; // Output Status Register
- AT91_REG Reserved1[1]; //
- AT91_REG PIO_IFER; // Input Filter Enable Register
- AT91_REG PIO_IFDR; // Input Filter Disable Register
- AT91_REG PIO_IFSR; // Input Filter Status Register
- AT91_REG Reserved2[1]; //
- AT91_REG PIO_SODR; // Set Output Data Register
- AT91_REG PIO_CODR; // Clear Output Data Register
- AT91_REG PIO_ODSR; // Output Data Status Register
- AT91_REG PIO_PDSR; // Pin Data Status Register
- AT91_REG PIO_IER; // Interrupt Enable Register
- AT91_REG PIO_IDR; // Interrupt Disable Register
- AT91_REG PIO_IMR; // Interrupt Mask Register
- AT91_REG PIO_ISR; // Interrupt Status Register
- AT91_REG PIO_MDER; // Multi-driver Enable Register
- AT91_REG PIO_MDDR; // Multi-driver Disable Register
- AT91_REG PIO_MDSR; // Multi-driver Status Register
- AT91_REG Reserved3[1]; //
- AT91_REG PIO_PPUDR; // Pull-up Disable Register
- AT91_REG PIO_PPUER; // Pull-up Enable Register
- AT91_REG PIO_PPUSR; // Pull-up Status Register
- AT91_REG Reserved4[1]; //
- AT91_REG PIO_ASR; // Select A Register
- AT91_REG PIO_BSR; // Select B Register
- AT91_REG PIO_ABSR; // AB Select Status Register
- AT91_REG Reserved5[9]; //
- AT91_REG PIO_OWER; // Output Write Enable Register
- AT91_REG PIO_OWDR; // Output Write Disable Register
- AT91_REG PIO_OWSR; // Output Write Status Register
-} AT91S_PIO, *AT91PS_PIO;
-
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Clock Generator Controler
-// *****************************************************************************
-typedef struct _AT91S_CKGR {
- AT91_REG CKGR_MOR; // Main Oscillator Register
- AT91_REG CKGR_MCFR; // Main Clock Frequency Register
- AT91_REG Reserved0[1]; //
- AT91_REG CKGR_PLLR; // PLL Register
-} AT91S_CKGR, *AT91PS_CKGR;
-
-// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
-#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable
-#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass
-#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time
-// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
-#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency
-#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
-// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
-#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected
-#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0
-#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed
-#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter
-#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
-#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
-#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
-#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
-#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
-#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Power Management Controler
-// *****************************************************************************
-typedef struct _AT91S_PMC {
- AT91_REG PMC_SCER; // System Clock Enable Register
- AT91_REG PMC_SCDR; // System Clock Disable Register
- AT91_REG PMC_SCSR; // System Clock Status Register
- AT91_REG Reserved0[1]; //
- AT91_REG PMC_PCER; // Peripheral Clock Enable Register
- AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
- AT91_REG PMC_PCSR; // Peripheral Clock Status Register
- AT91_REG Reserved1[1]; //
- AT91_REG PMC_MOR; // Main Oscillator Register
- AT91_REG PMC_MCFR; // Main Clock Frequency Register
- AT91_REG Reserved2[1]; //
- AT91_REG PMC_PLLR; // PLL Register
- AT91_REG PMC_MCKR; // Master Clock Register
- AT91_REG Reserved3[3]; //
- AT91_REG PMC_PCKR[4]; // Programmable Clock Register
- AT91_REG Reserved4[4]; //
- AT91_REG PMC_IER; // Interrupt Enable Register
- AT91_REG PMC_IDR; // Interrupt Disable Register
- AT91_REG PMC_SR; // Status Register
- AT91_REG PMC_IMR; // Interrupt Mask Register
-} AT91S_PMC, *AT91PS_PMC;
-
-// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
-#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock
-#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock
-#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
-// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
-// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
-// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
-// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
-// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
-// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
-#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection
-#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected
-#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected
-#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
-#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler
-#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock
-#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2
-#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4
-#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8
-#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16
-#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32
-#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64
-// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
-// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
-#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
-#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask
-#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
-// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
-// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
-// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Reset Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_RSTC {
- AT91_REG RSTC_RCR; // Reset Control Register
- AT91_REG RSTC_RSR; // Reset Status Register
- AT91_REG RSTC_RMR; // Reset Mode Register
-} AT91S_RSTC, *AT91PS_RSTC;
-
-// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
-#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset
-#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset
-#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset
-#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password
-// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
-#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status
-#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status
-#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type
-#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.
-#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.
-#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
-#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
-#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
-#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured.
-#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
-#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
-// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
-#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable
-#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable
-#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable
-#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_RTTC {
- AT91_REG RTTC_RTMR; // Real-time Mode Register
- AT91_REG RTTC_RTAR; // Real-time Alarm Register
- AT91_REG RTTC_RTVR; // Real-time Value Register
- AT91_REG RTTC_RTSR; // Real-time Status Register
-} AT91S_RTTC, *AT91PS_RTTC;
-
-// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
-#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
-#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
-#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
-#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
-// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
-#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value
-// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
-#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value
-// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
-#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status
-#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_PITC {
- AT91_REG PITC_PIMR; // Period Interval Mode Register
- AT91_REG PITC_PISR; // Period Interval Status Register
- AT91_REG PITC_PIVR; // Period Interval Value Register
- AT91_REG PITC_PIIR; // Period Interval Image Register
-} AT91S_PITC, *AT91PS_PITC;
-
-// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
-#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value
-#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
-#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
-// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
-#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status
-// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
-#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value
-#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
-// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_WDTC {
- AT91_REG WDTC_WDCR; // Watchdog Control Register
- AT91_REG WDTC_WDMR; // Watchdog Mode Register
- AT91_REG WDTC_WDSR; // Watchdog Status Register
-} AT91S_WDTC, *AT91PS_WDTC;
-
-// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
-#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart
-#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password
-// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
-#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
-#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
-#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
-#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
-#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
-#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
-// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
-#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow
-#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_VREG {
- AT91_REG VREG_MR; // Voltage Regulator Mode Register
-} AT91S_VREG, *AT91PS_VREG;
-
-// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
-#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Memory Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_MC {
- AT91_REG MC_RCR; // MC Remap Control Register
- AT91_REG MC_ASR; // MC Abort Status Register
- AT91_REG MC_AASR; // MC Abort Address Status Register
- AT91_REG Reserved0[21]; //
- AT91_REG MC_FMR; // MC Flash Mode Register
- AT91_REG MC_FCR; // MC Flash Command Register
- AT91_REG MC_FSR; // MC Flash Status Register
-} AT91S_MC, *AT91PS_MC;
-
-// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
-#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit
-// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
-#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status
-#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status
-#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status
-#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte
-#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word
-#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word
-#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
-#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read
-#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write
-#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch
-#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
-#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
-#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
-#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
-// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
-#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready
-#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error
-#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error
-#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming
-#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State
-#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations
-#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations
-#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations
-#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations
-#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
-// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
-#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command
-#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
-#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
-#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
-#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
-#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
-#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit.
-#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number
-#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
-// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
-#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status
-#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status
-#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status
-#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
-#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
-#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
-#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
-#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
-#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
-#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
-#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
-#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
-#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
-#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
-#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
-#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
-#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
-#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
-#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
-#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
-#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
-#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
-#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Serial Parallel Interface
-// *****************************************************************************
-typedef struct _AT91S_SPI {
- AT91_REG SPI_CR; // Control Register
- AT91_REG SPI_MR; // Mode Register
- AT91_REG SPI_RDR; // Receive Data Register
- AT91_REG SPI_TDR; // Transmit Data Register
- AT91_REG SPI_SR; // Status Register
- AT91_REG SPI_IER; // Interrupt Enable Register
- AT91_REG SPI_IDR; // Interrupt Disable Register
- AT91_REG SPI_IMR; // Interrupt Mask Register
- AT91_REG Reserved0[4]; //
- AT91_REG SPI_CSR[4]; // Chip Select Register
- AT91_REG Reserved1[48]; //
- AT91_REG SPI_RPR; // Receive Pointer Register
- AT91_REG SPI_RCR; // Receive Counter Register
- AT91_REG SPI_TPR; // Transmit Pointer Register
- AT91_REG SPI_TCR; // Transmit Counter Register
- AT91_REG SPI_RNPR; // Receive Next Pointer Register
- AT91_REG SPI_RNCR; // Receive Next Counter Register
- AT91_REG SPI_TNPR; // Transmit Next Pointer Register
- AT91_REG SPI_TNCR; // Transmit Next Counter Register
- AT91_REG SPI_PTCR; // PDC Transfer Control Register
- AT91_REG SPI_PTSR; // PDC Transfer Status Register
-} AT91S_SPI, *AT91PS_SPI;
-
-// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
-#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable
-#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable
-#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset
-#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
-// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
-#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode
-#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select
-#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select
-#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select
-#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode
-#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection
-#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection
-#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection
-#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
-#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
-// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
-#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data
-#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
-#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data
-#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
-#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full
-#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty
-#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error
-#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status
-#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt
-#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt
-#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt
-#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt
-#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status
-// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
-// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
-// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
-// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
-#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity
-#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase
-#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer
-#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer
-#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer
-#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer
-#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer
-#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer
-#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer
-#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer
-#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer
-#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer
-#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer
-#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK
-#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Usart
-// *****************************************************************************
-typedef struct _AT91S_USART {
- AT91_REG US_CR; // Control Register
- AT91_REG US_MR; // Mode Register
- AT91_REG US_IER; // Interrupt Enable Register
- AT91_REG US_IDR; // Interrupt Disable Register
- AT91_REG US_IMR; // Interrupt Mask Register
- AT91_REG US_CSR; // Channel Status Register
- AT91_REG US_RHR; // Receiver Holding Register
- AT91_REG US_THR; // Transmitter Holding Register
- AT91_REG US_BRGR; // Baud Rate Generator Register
- AT91_REG US_RTOR; // Receiver Time-out Register
- AT91_REG US_TTGR; // Transmitter Time-guard Register
- AT91_REG Reserved0[5]; //
- AT91_REG US_FIDI; // FI_DI_Ratio Register
- AT91_REG US_NER; // Nb Errors Register
- AT91_REG Reserved1[1]; //
- AT91_REG US_IF; // IRDA_FILTER Register
- AT91_REG Reserved2[44]; //
- AT91_REG US_RPR; // Receive Pointer Register
- AT91_REG US_RCR; // Receive Counter Register
- AT91_REG US_TPR; // Transmit Pointer Register
- AT91_REG US_TCR; // Transmit Counter Register
- AT91_REG US_RNPR; // Receive Next Pointer Register
- AT91_REG US_RNCR; // Receive Next Counter Register
- AT91_REG US_TNPR; // Transmit Next Pointer Register
- AT91_REG US_TNCR; // Transmit Next Counter Register
- AT91_REG US_PTCR; // PDC Transfer Control Register
- AT91_REG US_PTSR; // PDC Transfer Status Register
-} AT91S_USART, *AT91PS_USART;
-
-// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break
-#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break
-#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out
-#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address
-#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
-#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
-#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
-#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
-#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
-#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
-#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
-// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode
-#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal
-#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485
-#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking
-#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem
-#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
-#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
-#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA
-#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking
-#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock
-#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1
-#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM)
-#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK)
-#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits
-#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits
-#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits
-#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits
-#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select
-#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
-#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
-#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
-#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order
-#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
-#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
-#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
-#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
-#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
-#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
-#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
-// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break
-#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out
-#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
-#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
-#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
-#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
-#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
-#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
-// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
-#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
-#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
-#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
-#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_SSC {
- AT91_REG SSC_CR; // Control Register
- AT91_REG SSC_CMR; // Clock Mode Register
- AT91_REG Reserved0[2]; //
- AT91_REG SSC_RCMR; // Receive Clock ModeRegister
- AT91_REG SSC_RFMR; // Receive Frame Mode Register
- AT91_REG SSC_TCMR; // Transmit Clock Mode Register
- AT91_REG SSC_TFMR; // Transmit Frame Mode Register
- AT91_REG SSC_RHR; // Receive Holding Register
- AT91_REG SSC_THR; // Transmit Holding Register
- AT91_REG Reserved1[2]; //
- AT91_REG SSC_RSHR; // Receive Sync Holding Register
- AT91_REG SSC_TSHR; // Transmit Sync Holding Register
- AT91_REG Reserved2[2]; //
- AT91_REG SSC_SR; // Status Register
- AT91_REG SSC_IER; // Interrupt Enable Register
- AT91_REG SSC_IDR; // Interrupt Disable Register
- AT91_REG SSC_IMR; // Interrupt Mask Register
- AT91_REG Reserved3[44]; //
- AT91_REG SSC_RPR; // Receive Pointer Register
- AT91_REG SSC_RCR; // Receive Counter Register
- AT91_REG SSC_TPR; // Transmit Pointer Register
- AT91_REG SSC_TCR; // Transmit Counter Register
- AT91_REG SSC_RNPR; // Receive Next Pointer Register
- AT91_REG SSC_RNCR; // Receive Next Counter Register
- AT91_REG SSC_TNPR; // Transmit Next Pointer Register
- AT91_REG SSC_TNCR; // Transmit Next Counter Register
- AT91_REG SSC_PTCR; // PDC Transfer Control Register
- AT91_REG SSC_PTSR; // PDC Transfer Status Register
-} AT91S_SSC, *AT91PS_SSC;
-
-// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
-#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable
-#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable
-#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable
-#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable
-#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset
-// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
-#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection
-#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock
-#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal
-#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin
-#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
-#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
-#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
-#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection
-#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start
-#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input
-#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input
-#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input
-#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input
-#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input
-#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input
-#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0
-#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
-#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
-// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
-#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length
-#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode
-#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First
-#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame
-#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
-#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
-#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
-// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
-// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
-#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value
-#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
-// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
-#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready
-#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty
-#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission
-#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty
-#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready
-#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun
-#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception
-#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full
-#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
-#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
-#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
-#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
-// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
-// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
-// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Two-wire Interface
-// *****************************************************************************
-typedef struct _AT91S_TWI {
- AT91_REG TWI_CR; // Control Register
- AT91_REG TWI_MMR; // Master Mode Register
- AT91_REG Reserved0[1]; //
- AT91_REG TWI_IADR; // Internal Address Register
- AT91_REG TWI_CWGR; // Clock Waveform Generator Register
- AT91_REG Reserved1[3]; //
- AT91_REG TWI_SR; // Status Register
- AT91_REG TWI_IER; // Interrupt Enable Register
- AT91_REG TWI_IDR; // Interrupt Disable Register
- AT91_REG TWI_IMR; // Interrupt Mask Register
- AT91_REG TWI_RHR; // Receive Holding Register
- AT91_REG TWI_THR; // Transmit Holding Register
-} AT91S_TWI, *AT91PS_TWI;
-
-// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
-#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition
-#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition
-#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled
-#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled
-#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset
-// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
-#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size
-#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address
-#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address
-#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address
-#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address
-#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
-#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address
-// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
-#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider
-#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider
-#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
-// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
-#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed
-#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY
-#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY
-#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error
-#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error
-#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged
-// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
-// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
-// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR PWMC Channel Interface
-// *****************************************************************************
-typedef struct _AT91S_PWMC_CH {
- AT91_REG PWMC_CMR; // Channel Mode Register
- AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register
- AT91_REG PWMC_CPRDR; // Channel Period Register
- AT91_REG PWMC_CCNTR; // Channel Counter Register
- AT91_REG PWMC_CUPDR; // Channel Update Register
- AT91_REG PWMC_Reserved[3]; // Reserved
-} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
-
-// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
-#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
-#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH)
-#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH)
-#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH)
-#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment
-#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity
-#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
-// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
-#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle
-// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
-#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period
-// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
-#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter
-// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
-#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_PWMC {
- AT91_REG PWMC_MR; // PWMC Mode Register
- AT91_REG PWMC_ENA; // PWMC Enable Register
- AT91_REG PWMC_DIS; // PWMC Disable Register
- AT91_REG PWMC_SR; // PWMC Status Register
- AT91_REG PWMC_IER; // PWMC Interrupt Enable Register
- AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register
- AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register
- AT91_REG PWMC_ISR; // PWMC Interrupt Status Register
- AT91_REG Reserved0[55]; //
- AT91_REG PWMC_VR; // PWMC Version Register
- AT91_REG Reserved1[64]; //
- AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel
-} AT91S_PWMC, *AT91PS_PWMC;
-
-// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
-#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor.
-#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A
-#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC)
-#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
-#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
-#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC)
-// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
-#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0
-#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1
-#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2
-#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3
-// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
-// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
-// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
-// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
-// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
-// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR USB Device Interface
-// *****************************************************************************
-typedef struct _AT91S_UDP {
- AT91_REG UDP_NUM; // Frame Number Register
- AT91_REG UDP_GLBSTATE; // Global State Register
- AT91_REG UDP_FADDR; // Function Address Register
- AT91_REG Reserved0[1]; //
- AT91_REG UDP_IER; // Interrupt Enable Register
- AT91_REG UDP_IDR; // Interrupt Disable Register
- AT91_REG UDP_IMR; // Interrupt Mask Register
- AT91_REG UDP_ISR; // Interrupt Status Register
- AT91_REG UDP_ICR; // Interrupt Clear Register
- AT91_REG Reserved1[1]; //
- AT91_REG UDP_RSTEP; // Reset Endpoint Register
- AT91_REG Reserved2[1]; //
- AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register
- AT91_REG Reserved3[2]; //
- AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register
- AT91_REG Reserved4[3]; //
- AT91_REG UDP_TXVC; // Transceiver Control Register
-} AT91S_UDP, *AT91PS_UDP;
-
-// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
-#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
-#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error
-#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK
-// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
-#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable
-#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured
-#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume
-#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
-#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable
-// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
-#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value
-#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable
-// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
-#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt
-#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt
-#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt
-#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt
-#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt
-#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt
-#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
-#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
-#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
-// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
-// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
-// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
-#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
-// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
-// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
-#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0
-#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1
-#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2
-#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3
-#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4
-#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5
-// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
-#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
-#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0
-#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
-#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
-#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready
-#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction
-#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type
-#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control
-#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT
-#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT
-#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT
-#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN
-#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN
-#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN
-#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
-#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
-#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
-// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
-#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP)
-#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
-// *****************************************************************************
-typedef struct _AT91S_TC {
- AT91_REG TC_CCR; // Channel Control Register
- AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)
- AT91_REG Reserved0[2]; //
- AT91_REG TC_CV; // Counter Value
- AT91_REG TC_RA; // Register A
- AT91_REG TC_RB; // Register B
- AT91_REG TC_RC; // Register C
- AT91_REG TC_SR; // Status Register
- AT91_REG TC_IER; // Interrupt Enable Register
- AT91_REG TC_IDR; // Interrupt Disable Register
- AT91_REG TC_IMR; // Interrupt Mask Register
-} AT91S_TC, *AT91PS_TC;
-
-// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
-#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command
-#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command
-#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command
-// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
-#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection
-#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
-#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
-#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
-#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
-#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
-#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0
-#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1
-#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2
-#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert
-#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection
-#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal
-#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock
-#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock
-#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock
-#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
-#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
-#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare
-#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
-#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection
-#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
-#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
-#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
-#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
-#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection
-#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
-#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
-#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
-#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
-#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection
-#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
-#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
-#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
-#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
-#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
-#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
-#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection
-#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
-#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
-#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
-#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
-#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
-#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC)
-#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
-#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none
-#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set
-#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear
-#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
-#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
-#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None
-#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
-#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
-#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
-#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none
-#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set
-#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear
-#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
-#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
-#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None
-#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
-#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
-#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
-#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none
-#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set
-#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear
-#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
-#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
-#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none
-#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set
-#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear
-#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
-#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
-#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none
-#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set
-#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear
-#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
-#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
-#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none
-#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set
-#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear
-#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
-#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
-#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none
-#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set
-#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear
-#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
-#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
-#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none
-#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set
-#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear
-#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
-// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
-#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow
-#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun
-#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare
-#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare
-#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare
-#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading
-#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading
-#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger
-#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
-#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
-#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
-// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
-// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
-// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Timer Counter Interface
-// *****************************************************************************
-typedef struct _AT91S_TCB {
- AT91S_TC TCB_TC0; // TC Channel 0
- AT91_REG Reserved0[4]; //
- AT91S_TC TCB_TC1; // TC Channel 1
- AT91_REG Reserved1[4]; //
- AT91S_TC TCB_TC2; // TC Channel 2
- AT91_REG Reserved2[4]; //
- AT91_REG TCB_BCR; // TC Block Control Register
- AT91_REG TCB_BMR; // TC Block Mode Register
-} AT91S_TCB, *AT91PS_TCB;
-
-// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
-#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command
-// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
-#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection
-#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
-#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0
-#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
-#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
-#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection
-#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1
-#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1
-#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1
-#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1
-#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection
-#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2
-#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2
-#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2
-#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface
-// *****************************************************************************
-typedef struct _AT91S_CAN_MB {
- AT91_REG CAN_MB_MMR; // MailBox Mode Register
- AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register
- AT91_REG CAN_MB_MID; // MailBox ID Register
- AT91_REG CAN_MB_MFID; // MailBox Family ID Register
- AT91_REG CAN_MB_MSR; // MailBox Status Register
- AT91_REG CAN_MB_MDL; // MailBox Data Low Register
- AT91_REG CAN_MB_MDH; // MailBox Data High Register
- AT91_REG CAN_MB_MCR; // MailBox Control Register
-} AT91S_CAN_MB, *AT91PS_CAN_MB;
-
-// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register --------
-#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark
-#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority
-#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type
-#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB)
-#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB)
-#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB)
-#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB)
-#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB)
-#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB)
-// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register --------
-#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode
-#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
-#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version
-// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register --------
-// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register --------
-// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register --------
-#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value
-#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code
-#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
-#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort
-#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready
-#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored
-// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register --------
-// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register --------
-// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register --------
-#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox
-#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Control Area Network Interface
-// *****************************************************************************
-typedef struct _AT91S_CAN {
- AT91_REG CAN_MR; // Mode Register
- AT91_REG CAN_IER; // Interrupt Enable Register
- AT91_REG CAN_IDR; // Interrupt Disable Register
- AT91_REG CAN_IMR; // Interrupt Mask Register
- AT91_REG CAN_SR; // Status Register
- AT91_REG CAN_BR; // Baudrate Register
- AT91_REG CAN_TIM; // Timer Register
- AT91_REG CAN_TIMESTP; // Time Stamp Register
- AT91_REG CAN_ECR; // Error Counter Register
- AT91_REG CAN_TCR; // Transfer Command Register
- AT91_REG CAN_ACR; // Abort Command Register
- AT91_REG Reserved0[52]; //
- AT91_REG CAN_VR; // Version Register
- AT91_REG Reserved1[64]; //
- AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0
- AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1
- AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2
- AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3
- AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4
- AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5
- AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6
- AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7
- AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8
- AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9
- AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10
- AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11
- AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12
- AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13
- AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14
- AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15
-} AT91S_CAN, *AT91PS_CAN;
-
-// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register --------
-#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable
-#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode
-#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode
-#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame
-#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame
-#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode
-#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze
-#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat
-// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register --------
-#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag
-#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag
-#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag
-#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag
-#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag
-#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag
-#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag
-#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag
-#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag
-#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag
-#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag
-#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag
-#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag
-#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag
-#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag
-#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag
-#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag
-#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag
-#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag
-#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag
-#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag
-#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag
-#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag
-#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag
-#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error
-#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error
-#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error
-#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error
-#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error
-// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register --------
-// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register --------
-// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register --------
-#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy
-#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy
-#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy
-// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register --------
-#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment
-#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment
-#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment
-#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment
-#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler
-#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode
-// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register --------
-#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field
-// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register --------
-// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register --------
-#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter
-#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter
-// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register --------
-#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field
-// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100
-// *****************************************************************************
-typedef struct _AT91S_EMAC {
- AT91_REG EMAC_NCR; // Network Control Register
- AT91_REG EMAC_NCFGR; // Network Configuration Register
- AT91_REG EMAC_NSR; // Network Status Register
- AT91_REG Reserved0[2]; //
- AT91_REG EMAC_TSR; // Transmit Status Register
- AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer
- AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer
- AT91_REG EMAC_RSR; // Receive Status Register
- AT91_REG EMAC_ISR; // Interrupt Status Register
- AT91_REG EMAC_IER; // Interrupt Enable Register
- AT91_REG EMAC_IDR; // Interrupt Disable Register
- AT91_REG EMAC_IMR; // Interrupt Mask Register
- AT91_REG EMAC_MAN; // PHY Maintenance Register
- AT91_REG EMAC_PTR; // Pause Time Register
- AT91_REG EMAC_PFR; // Pause Frames received Register
- AT91_REG EMAC_FTO; // Frames Transmitted OK Register
- AT91_REG EMAC_SCF; // Single Collision Frame Register
- AT91_REG EMAC_MCF; // Multiple Collision Frame Register
- AT91_REG EMAC_FRO; // Frames Received OK Register
- AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register
- AT91_REG EMAC_ALE; // Alignment Error Register
- AT91_REG EMAC_DTF; // Deferred Transmission Frame Register
- AT91_REG EMAC_LCOL; // Late Collision Register
- AT91_REG EMAC_ECOL; // Excessive Collision Register
- AT91_REG EMAC_TUND; // Transmit Underrun Error Register
- AT91_REG EMAC_CSE; // Carrier Sense Error Register
- AT91_REG EMAC_RRE; // Receive Ressource Error Register
- AT91_REG EMAC_ROV; // Receive Overrun Errors Register
- AT91_REG EMAC_RSE; // Receive Symbol Errors Register
- AT91_REG EMAC_ELE; // Excessive Length Errors Register
- AT91_REG EMAC_RJA; // Receive Jabbers Register
- AT91_REG EMAC_USF; // Undersize Frames Register
- AT91_REG EMAC_STE; // SQE Test Error Register
- AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register
- AT91_REG EMAC_TPF; // Transmitted Pause Frames Register
- AT91_REG EMAC_HRB; // Hash Address Bottom[31:0]
- AT91_REG EMAC_HRT; // Hash Address Top[63:32]
- AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes
- AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes
- AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes
- AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes
- AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes
- AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes
- AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes
- AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes
- AT91_REG EMAC_TID; // Type ID Checking Register
- AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register
- AT91_REG EMAC_USRIO; // USER Input/Output Register
- AT91_REG EMAC_WOL; // Wake On LAN Register
- AT91_REG Reserved1[13]; //
- AT91_REG EMAC_REV; // Revision Register
-} AT91S_EMAC, *AT91PS_EMAC;
-
-// -------- EMAC_NCR : (EMAC Offset: 0x0) --------
-#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
-#define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local.
-#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable.
-#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable.
-#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable.
-#define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers.
-#define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers.
-#define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers.
-#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure.
-#define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission.
-#define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt.
-#define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame
-#define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame
-// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register --------
-#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed.
-#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex.
-#define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames.
-#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames.
-#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast.
-#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable
-#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable.
-#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes.
-#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable.
-#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC)
-#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8
-#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16
-#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32
-#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64
-#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC)
-#define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC)
-#define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC)
-#define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer
-#define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer
-#define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
-#define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
-#define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable
-#define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS
-#define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC)
-#define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS
-// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register --------
-#define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC)
-#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC)
-#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC)
-// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register --------
-#define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC)
-#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC)
-#define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC)
-#define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go
-#define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame
-#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC)
-#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC)
-// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
-#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC)
-#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC)
-#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC)
-// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
-#define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC)
-#define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC)
-#define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC)
-#define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC)
-#define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC)
-#define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC)
-#define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC)
-#define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC)
-#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC)
-#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC)
-#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC)
-#define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC)
-#define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC)
-// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
-// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
-// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
-// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
-#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC)
-#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC)
-#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC)
-#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC)
-#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC)
-#define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC)
-// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register --------
-#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII
-// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register --------
-#define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address
-#define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable
-#define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable
-#define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable
-// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register --------
-#define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC)
-#define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC)
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Analog to Digital Convertor
-// *****************************************************************************
-typedef struct _AT91S_ADC {
- AT91_REG ADC_CR; // ADC Control Register
- AT91_REG ADC_MR; // ADC Mode Register
- AT91_REG Reserved0[2]; //
- AT91_REG ADC_CHER; // ADC Channel Enable Register
- AT91_REG ADC_CHDR; // ADC Channel Disable Register
- AT91_REG ADC_CHSR; // ADC Channel Status Register
- AT91_REG ADC_SR; // ADC Status Register
- AT91_REG ADC_LCDR; // ADC Last Converted Data Register
- AT91_REG ADC_IER; // ADC Interrupt Enable Register
- AT91_REG ADC_IDR; // ADC Interrupt Disable Register
- AT91_REG ADC_IMR; // ADC Interrupt Mask Register
- AT91_REG ADC_CDR0; // ADC Channel Data Register 0
- AT91_REG ADC_CDR1; // ADC Channel Data Register 1
- AT91_REG ADC_CDR2; // ADC Channel Data Register 2
- AT91_REG ADC_CDR3; // ADC Channel Data Register 3
- AT91_REG ADC_CDR4; // ADC Channel Data Register 4
- AT91_REG ADC_CDR5; // ADC Channel Data Register 5
- AT91_REG ADC_CDR6; // ADC Channel Data Register 6
- AT91_REG ADC_CDR7; // ADC Channel Data Register 7
- AT91_REG Reserved1[44]; //
- AT91_REG ADC_RPR; // Receive Pointer Register
- AT91_REG ADC_RCR; // Receive Counter Register
- AT91_REG ADC_TPR; // Transmit Pointer Register
- AT91_REG ADC_TCR; // Transmit Counter Register
- AT91_REG ADC_RNPR; // Receive Next Pointer Register
- AT91_REG ADC_RNCR; // Receive Next Counter Register
- AT91_REG ADC_TNPR; // Transmit Next Pointer Register
- AT91_REG ADC_TNCR; // Transmit Next Counter Register
- AT91_REG ADC_PTCR; // PDC Transfer Control Register
- AT91_REG ADC_PTSR; // PDC Transfer Status Register
-} AT91S_ADC, *AT91PS_ADC;
-
-// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
-#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset
-#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion
-// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
-#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable
-#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
-#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
-#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection
-#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
-#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
-#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
-#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
-#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
-#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
-#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
-#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution.
-#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution
-#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution
-#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
-#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode
-#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
-#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection
-#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time
-#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
-// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
-#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0
-#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1
-#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2
-#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3
-#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4
-#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5
-#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6
-#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7
-// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
-// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
-// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
-#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion
-#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion
-#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion
-#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion
-#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion
-#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion
-#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion
-#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion
-#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
-#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready
-#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun
-#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
-#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
-// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
-#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted
-// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
-// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
-// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
-// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
-#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data
-// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
-// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
-// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
-// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
-// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
-// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
-// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Advanced Encryption Standard
-// *****************************************************************************
-typedef struct _AT91S_AES {
- AT91_REG AES_CR; // Control Register
- AT91_REG AES_MR; // Mode Register
- AT91_REG Reserved0[2]; //
- AT91_REG AES_IER; // Interrupt Enable Register
- AT91_REG AES_IDR; // Interrupt Disable Register
- AT91_REG AES_IMR; // Interrupt Mask Register
- AT91_REG AES_ISR; // Interrupt Status Register
- AT91_REG AES_KEYWxR[4]; // Key Word x Register
- AT91_REG Reserved1[4]; //
- AT91_REG AES_IDATAxR[4]; // Input Data x Register
- AT91_REG AES_ODATAxR[4]; // Output Data x Register
- AT91_REG AES_IVxR[4]; // Initialization Vector x Register
- AT91_REG Reserved2[35]; //
- AT91_REG AES_VR; // AES Version Register
- AT91_REG AES_RPR; // Receive Pointer Register
- AT91_REG AES_RCR; // Receive Counter Register
- AT91_REG AES_TPR; // Transmit Pointer Register
- AT91_REG AES_TCR; // Transmit Counter Register
- AT91_REG AES_RNPR; // Receive Next Pointer Register
- AT91_REG AES_RNCR; // Receive Next Counter Register
- AT91_REG AES_TNPR; // Transmit Next Pointer Register
- AT91_REG AES_TNCR; // Transmit Next Counter Register
- AT91_REG AES_PTCR; // PDC Transfer Control Register
- AT91_REG AES_PTSR; // PDC Transfer Status Register
-} AT91S_AES, *AT91PS_AES;
-
-// -------- AES_CR : (AES Offset: 0x0) Control Register --------
-#define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing
-#define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset
-#define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading
-// -------- AES_MR : (AES Offset: 0x4) Mode Register --------
-#define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode
-#define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay
-#define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode
-#define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
-#define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
-#define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet).
-#define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode
-#define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode.
-#define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
-#define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode.
-#define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode.
-#define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode.
-#define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode
-#define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size
-#define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit.
-#define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit.
-#define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit.
-#define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit.
-#define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit.
-#define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key
-#define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type
-#define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled.
-#define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled.
-#define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled.
-#define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled.
-#define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled.
-// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register --------
-#define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY
-#define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End
-#define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End
-#define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full
-#define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty
-#define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection
-// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register --------
-// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register --------
-// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register --------
-#define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status
-#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
-#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing.
-#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing.
-#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation.
-#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation.
-#define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access.
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard
-// *****************************************************************************
-typedef struct _AT91S_TDES {
- AT91_REG TDES_CR; // Control Register
- AT91_REG TDES_MR; // Mode Register
- AT91_REG Reserved0[2]; //
- AT91_REG TDES_IER; // Interrupt Enable Register
- AT91_REG TDES_IDR; // Interrupt Disable Register
- AT91_REG TDES_IMR; // Interrupt Mask Register
- AT91_REG TDES_ISR; // Interrupt Status Register
- AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register
- AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register
- AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register
- AT91_REG Reserved1[2]; //
- AT91_REG TDES_IDATAxR[2]; // Input Data x Register
- AT91_REG Reserved2[2]; //
- AT91_REG TDES_ODATAxR[2]; // Output Data x Register
- AT91_REG Reserved3[2]; //
- AT91_REG TDES_IVxR[2]; // Initialization Vector x Register
- AT91_REG Reserved4[37]; //
- AT91_REG TDES_VR; // TDES Version Register
- AT91_REG TDES_RPR; // Receive Pointer Register
- AT91_REG TDES_RCR; // Receive Counter Register
- AT91_REG TDES_TPR; // Transmit Pointer Register
- AT91_REG TDES_TCR; // Transmit Counter Register
- AT91_REG TDES_RNPR; // Receive Next Pointer Register
- AT91_REG TDES_RNCR; // Receive Next Counter Register
- AT91_REG TDES_TNPR; // Transmit Next Pointer Register
- AT91_REG TDES_TNCR; // Transmit Next Counter Register
- AT91_REG TDES_PTCR; // PDC Transfer Control Register
- AT91_REG TDES_PTSR; // PDC Transfer Status Register
-} AT91S_TDES, *AT91PS_TDES;
-
-// -------- TDES_CR : (TDES Offset: 0x0) Control Register --------
-#define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing
-#define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset
-// -------- TDES_MR : (TDES Offset: 0x4) Mode Register --------
-#define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode
-#define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode
-#define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode
-#define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode
-#define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
-#define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
-#define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet).
-#define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode
-#define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
-#define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
-#define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode.
-#define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode.
-#define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode
-#define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size
-#define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit.
-#define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit.
-#define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit.
-#define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit.
-// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register --------
-#define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY
-#define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End
-#define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End
-#define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full
-#define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty
-#define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection
-// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register --------
-// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register --------
-// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register --------
-#define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status
-#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
-#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing.
-#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing.
-#define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access.
-
-// *****************************************************************************
-// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
-// *****************************************************************************
-// ========== Register definition for SYS peripheral ==========
-// ========== Register definition for AIC peripheral ==========
-#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register
-#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register
-#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register
-#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)
-#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register
-#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register
-#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register
-#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register
-#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register
-#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register
-#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register
-#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register
-#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register
-#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register
-#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register
-#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register
-#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register
-#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register
-// ========== Register definition for PDC_DBGU peripheral ==========
-#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
-#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
-#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
-#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
-#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
-#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register
-#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
-#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
-#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
-#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
-// ========== Register definition for DBGU peripheral ==========
-#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register
-#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register
-#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register
-#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register
-#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register
-#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register
-#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register
-#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register
-#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register
-#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register
-#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register
-#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register
-// ========== Register definition for PIOA peripheral ==========
-#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr
-#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register
-#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register
-#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register
-#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register
-#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register
-#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register
-#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register
-#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register
-#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register
-#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register
-#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register
-#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register
-#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register
-#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register
-#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register
-#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register
-#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register
-#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register
-#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register
-#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register
-#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register
-#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register
-#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register
-#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register
-#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register
-#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register
-#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register
-#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register
-// ========== Register definition for PIOB peripheral ==========
-#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register
-#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register
-#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register
-#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register
-#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register
-#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register
-#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register
-#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register
-#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register
-#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register
-#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register
-#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register
-#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register
-#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register
-#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register
-#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register
-#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr
-#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register
-#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register
-#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register
-#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register
-#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register
-#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register
-#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register
-#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register
-#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register
-#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register
-#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register
-#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register
-// ========== Register definition for CKGR peripheral ==========
-#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register
-#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register
-#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register
-// ========== Register definition for PMC peripheral ==========
-#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register
-#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
-#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register
-#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
-#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register
-#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
-#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register
-#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
-#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register
-#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register
-#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register
-#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register
-#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register
-#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register
-#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register
-// ========== Register definition for RSTC peripheral ==========
-#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register
-#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register
-#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register
-// ========== Register definition for RTTC peripheral ==========
-#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register
-#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register
-#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register
-#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register
-// ========== Register definition for PITC peripheral ==========
-#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register
-#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register
-#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register
-#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register
-// ========== Register definition for WDTC peripheral ==========
-#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register
-#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register
-#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register
-// ========== Register definition for VREG peripheral ==========
-#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
-// ========== Register definition for MC peripheral ==========
-#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register
-#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register
-#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register
-#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register
-#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register
-#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register
-// ========== Register definition for PDC_SPI1 peripheral ==========
-#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
-#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
-#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
-#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
-#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
-#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
-#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register
-#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
-#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
-#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
-// ========== Register definition for SPI1 peripheral ==========
-#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register
-#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register
-#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register
-#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register
-#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register
-#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register
-#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register
-#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register
-#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register
-// ========== Register definition for PDC_SPI0 peripheral ==========
-#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
-#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
-#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
-#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register
-#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
-#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
-#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
-#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
-#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
-#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
-// ========== Register definition for SPI0 peripheral ==========
-#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register
-#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register
-#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register
-#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register
-#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register
-#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register
-#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register
-#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register
-#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register
-// ========== Register definition for PDC_US1 peripheral ==========
-#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register
-#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
-#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register
-#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
-#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
-#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register
-#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
-#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register
-#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
-#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register
-// ========== Register definition for US1 peripheral ==========
-#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register
-#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register
-#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register
-#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register
-#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register
-#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register
-#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register
-#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register
-#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register
-#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register
-#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register
-#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register
-#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register
-#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register
-// ========== Register definition for PDC_US0 peripheral ==========
-#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
-#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
-#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register
-#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
-#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
-#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
-#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register
-#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register
-#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register
-#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register
-// ========== Register definition for US0 peripheral ==========
-#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register
-#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register
-#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register
-#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register
-#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register
-#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register
-#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register
-#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register
-#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register
-#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register
-#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register
-#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register
-#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register
-#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register
-// ========== Register definition for PDC_SSC peripheral ==========
-#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
-#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register
-#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
-#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
-#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
-#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register
-#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register
-#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
-#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
-#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
-// ========== Register definition for SSC peripheral ==========
-#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register
-#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register
-#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register
-#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register
-#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register
-#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister
-#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register
-#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register
-#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register
-#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register
-#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register
-#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register
-#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register
-#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register
-// ========== Register definition for TWI peripheral ==========
-#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register
-#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register
-#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register
-#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register
-#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register
-#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register
-#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register
-#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register
-#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register
-#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register
-// ========== Register definition for PWMC_CH3 peripheral ==========
-#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register
-#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved
-#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register
-#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
-#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
-#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register
-// ========== Register definition for PWMC_CH2 peripheral ==========
-#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved
-#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register
-#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
-#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register
-#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register
-#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH1 peripheral ==========
-#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved
-#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register
-#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register
-#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
-#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
-#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register
-// ========== Register definition for PWMC_CH0 peripheral ==========
-#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved
-#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register
-#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
-#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register
-#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register
-#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
-// ========== Register definition for PWMC peripheral ==========
-#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
-#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register
-#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
-#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register
-#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
-#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register
-#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
-#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register
-#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register
-// ========== Register definition for UDP peripheral ==========
-#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register
-#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register
-#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register
-#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register
-#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register
-#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register
-#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register
-#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register
-#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register
-#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register
-#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register
-#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register
-// ========== Register definition for TC0 peripheral ==========
-#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register
-#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C
-#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B
-#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register
-#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register
-#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A
-#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register
-#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value
-#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register
-// ========== Register definition for TC1 peripheral ==========
-#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B
-#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register
-#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register
-#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register
-#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register
-#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A
-#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C
-#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register
-#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value
-// ========== Register definition for TC2 peripheral ==========
-#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register
-#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value
-#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A
-#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B
-#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register
-#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register
-#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C
-#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register
-#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
-// ========== Register definition for TCB peripheral ==========
-#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register
-#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register
-// ========== Register definition for CAN_MB0 peripheral ==========
-#define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
-#define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register
-#define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register
-#define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register
-#define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
-#define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register
-#define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register
-// ========== Register definition for CAN_MB1 peripheral ==========
-#define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
-#define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register
-#define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register
-#define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register
-#define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register
-#define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register
-#define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
-// ========== Register definition for CAN_MB2 peripheral ==========
-#define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register
-#define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register
-#define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register
-#define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
-#define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register
-#define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
-#define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register
-// ========== Register definition for CAN_MB3 peripheral ==========
-#define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
-#define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register
-#define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register
-#define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register
-#define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register
-#define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
-#define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register
-// ========== Register definition for CAN_MB4 peripheral ==========
-#define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register
-#define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register
-#define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register
-#define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
-#define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register
-#define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register
-#define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
-#define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
-// ========== Register definition for CAN_MB5 peripheral ==========
-#define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register
-#define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register
-#define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
-#define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
-#define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register
-#define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
-#define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
-#define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
-// ========== Register definition for CAN_MB6 peripheral ==========
-#define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
-#define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register
-#define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register
-#define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
-#define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register
-#define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
-#define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
-// ========== Register definition for CAN_MB7 peripheral ==========
-#define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register
-#define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
-#define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
-#define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
-#define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register
-#define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
-#define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register
-// ========== Register definition for CAN peripheral ==========
-#define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register
-#define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register
-#define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register
-#define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register
-#define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register
-#define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register
-#define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register
-#define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register
-#define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register
-#define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register
-#define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register
-#define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register
-// ========== Register definition for EMAC peripheral ==========
-#define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register
-#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
-#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
-#define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register
-#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register
-#define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
-#define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register
-#define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
-#define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register
-#define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register
-#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
-#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register
-#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
-#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register
-#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register
-#define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register
-#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register
-#define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register
-#define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
-#define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
-#define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register
-#define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register
-#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
-#define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register
-#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register
-#define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register
-#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
-#define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
-#define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register
-#define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32]
-#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register
-#define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
-#define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
-#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register
-#define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register
-#define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register
-#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register
-#define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register
-#define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register
-#define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register
-#define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register
-#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
-#define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register
-#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register
-#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
-#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register
-#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
-#define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register
-#define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register
-// ========== Register definition for PDC_ADC peripheral ==========
-#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
-#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
-#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
-#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
-#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
-#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
-#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register
-#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register
-#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
-#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register
-// ========== Register definition for ADC peripheral ==========
-#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2
-#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3
-#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0
-#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5
-#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register
-#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register
-#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4
-#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1
-#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register
-#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register
-#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register
-#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7
-#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6
-#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register
-#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register
-#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register
-#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register
-#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register
-// ========== Register definition for PDC_AES peripheral ==========
-#define AT91C_AES_TPR ((AT91_REG *) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register
-#define AT91C_AES_PTCR ((AT91_REG *) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
-#define AT91C_AES_RNPR ((AT91_REG *) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
-#define AT91C_AES_TNCR ((AT91_REG *) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
-#define AT91C_AES_TCR ((AT91_REG *) 0xFFFA410C) // (PDC_AES) Transmit Counter Register
-#define AT91C_AES_RCR ((AT91_REG *) 0xFFFA4104) // (PDC_AES) Receive Counter Register
-#define AT91C_AES_RNCR ((AT91_REG *) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register
-#define AT91C_AES_TNPR ((AT91_REG *) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
-#define AT91C_AES_RPR ((AT91_REG *) 0xFFFA4100) // (PDC_AES) Receive Pointer Register
-#define AT91C_AES_PTSR ((AT91_REG *) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
-// ========== Register definition for AES peripheral ==========
-#define AT91C_AES_IVxR ((AT91_REG *) 0xFFFA4060) // (AES) Initialization Vector x Register
-#define AT91C_AES_MR ((AT91_REG *) 0xFFFA4004) // (AES) Mode Register
-#define AT91C_AES_VR ((AT91_REG *) 0xFFFA40FC) // (AES) AES Version Register
-#define AT91C_AES_ODATAxR ((AT91_REG *) 0xFFFA4050) // (AES) Output Data x Register
-#define AT91C_AES_IDATAxR ((AT91_REG *) 0xFFFA4040) // (AES) Input Data x Register
-#define AT91C_AES_CR ((AT91_REG *) 0xFFFA4000) // (AES) Control Register
-#define AT91C_AES_IDR ((AT91_REG *) 0xFFFA4014) // (AES) Interrupt Disable Register
-#define AT91C_AES_IMR ((AT91_REG *) 0xFFFA4018) // (AES) Interrupt Mask Register
-#define AT91C_AES_IER ((AT91_REG *) 0xFFFA4010) // (AES) Interrupt Enable Register
-#define AT91C_AES_KEYWxR ((AT91_REG *) 0xFFFA4020) // (AES) Key Word x Register
-#define AT91C_AES_ISR ((AT91_REG *) 0xFFFA401C) // (AES) Interrupt Status Register
-// ========== Register definition for PDC_TDES peripheral ==========
-#define AT91C_TDES_RNCR ((AT91_REG *) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
-#define AT91C_TDES_TCR ((AT91_REG *) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register
-#define AT91C_TDES_RCR ((AT91_REG *) 0xFFFA8104) // (PDC_TDES) Receive Counter Register
-#define AT91C_TDES_TNPR ((AT91_REG *) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
-#define AT91C_TDES_RNPR ((AT91_REG *) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
-#define AT91C_TDES_RPR ((AT91_REG *) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register
-#define AT91C_TDES_TNCR ((AT91_REG *) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
-#define AT91C_TDES_TPR ((AT91_REG *) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
-#define AT91C_TDES_PTSR ((AT91_REG *) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
-#define AT91C_TDES_PTCR ((AT91_REG *) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
-// ========== Register definition for TDES peripheral ==========
-#define AT91C_TDES_KEY2WxR ((AT91_REG *) 0xFFFA8028) // (TDES) Key 2 Word x Register
-#define AT91C_TDES_KEY3WxR ((AT91_REG *) 0xFFFA8030) // (TDES) Key 3 Word x Register
-#define AT91C_TDES_IDR ((AT91_REG *) 0xFFFA8014) // (TDES) Interrupt Disable Register
-#define AT91C_TDES_VR ((AT91_REG *) 0xFFFA80FC) // (TDES) TDES Version Register
-#define AT91C_TDES_IVxR ((AT91_REG *) 0xFFFA8060) // (TDES) Initialization Vector x Register
-#define AT91C_TDES_ODATAxR ((AT91_REG *) 0xFFFA8050) // (TDES) Output Data x Register
-#define AT91C_TDES_IMR ((AT91_REG *) 0xFFFA8018) // (TDES) Interrupt Mask Register
-#define AT91C_TDES_MR ((AT91_REG *) 0xFFFA8004) // (TDES) Mode Register
-#define AT91C_TDES_CR ((AT91_REG *) 0xFFFA8000) // (TDES) Control Register
-#define AT91C_TDES_IER ((AT91_REG *) 0xFFFA8010) // (TDES) Interrupt Enable Register
-#define AT91C_TDES_ISR ((AT91_REG *) 0xFFFA801C) // (TDES) Interrupt Status Register
-#define AT91C_TDES_IDATAxR ((AT91_REG *) 0xFFFA8040) // (TDES) Input Data x Register
-#define AT91C_TDES_KEY1WxR ((AT91_REG *) 0xFFFA8020) // (TDES) Key 1 Word x Register
-
-// *****************************************************************************
-// PIO DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0
-#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data
-#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1
-#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data
-#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10
-#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data
-#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11
-#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock
-#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12
-#define AT91C_PA12_NPCS00 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0
-#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13
-#define AT91C_PA13_NPCS01 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1
-#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1
-#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14
-#define AT91C_PA14_NPCS02 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2
-#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1
-#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15
-#define AT91C_PA15_NPCS03 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3
-#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input
-#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16
-#define AT91C_PA16_MISO0 ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave
-#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17
-#define AT91C_PA17_MOSI0 ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave
-#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18
-#define AT91C_PA18_SPCK0 ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock
-#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19
-#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive
-#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2
-#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock
-#define AT91C_PA2_NPCS11 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20
-#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit
-#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21
-#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync
-#define AT91C_PA21_NPCS10 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0
-#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22
-#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock
-#define AT91C_PA22_SPCK1 ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock
-#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23
-#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data
-#define AT91C_PA23_MOSI1 ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave
-#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24
-#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data
-#define AT91C_PA24_MISO1 ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave
-#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25
-#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock
-#define AT91C_PA25_NPCS11 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26
-#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync
-#define AT91C_PA26_NPCS12 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27
-#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data
-#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3
-#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28
-#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data
-#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29
-#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input
-#define AT91C_PA29_NPCS13 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3
-#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send
-#define AT91C_PA3_NPCS12 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30
-#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0
-#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2
-#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4
-#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send
-#define AT91C_PA4_NPCS13 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5
-#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data
-#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6
-#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data
-#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7
-#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock
-#define AT91C_PA7_NPCS01 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8
-#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send
-#define AT91C_PA8_NPCS02 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9
-#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send
-#define AT91C_PA9_NPCS03 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0
-#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock
-#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0
-#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1
-#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable
-#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10
-#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2
-#define AT91C_PB10_NPCS11 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11
-#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3
-#define AT91C_PB11_NPCS12 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12
-#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error
-#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input
-#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13
-#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2
-#define AT91C_PB13_NPCS01 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14
-#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3
-#define AT91C_PB14_NPCS02 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15
-#define AT91C_PB15_ERXDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid
-#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16
-#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected
-#define AT91C_PB16_NPCS13 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17
-#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock
-#define AT91C_PB17_NPCS03 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18
-#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec
-#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger
-#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19
-#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0
-#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input
-#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2
-#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0
-#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20
-#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1
-#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0
-#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21
-#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2
-#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1
-#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22
-#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3
-#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2
-#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23
-#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A
-#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect
-#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24
-#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B
-#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready
-#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25
-#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A
-#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready
-#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26
-#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B
-#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator
-#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27
-#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A
-#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0
-#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28
-#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B
-#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1
-#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29
-#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1
-#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2
-#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3
-#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1
-#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30
-#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2
-#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3
-#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4
-#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
-#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5
-#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0
-#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6
-#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1
-#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7
-#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error
-#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8
-#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock
-#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9
-#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output
-
-// *****************************************************************************
-// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ)
-#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral
-#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A
-#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B
-#define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0
-#define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1
-#define AT91C_ID_US0 ((unsigned int) 6) // USART 0
-#define AT91C_ID_US1 ((unsigned int) 7) // USART 1
-#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller
-#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface
-#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller
-#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port
-#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0
-#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1
-#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2
-#define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller
-#define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC
-#define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter
-#define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit
-#define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard
-#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
-#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
-#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
-#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
-#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
-#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
-#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
-#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
-#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
-#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
-#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
-#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
-
-// *****************************************************************************
-// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address
-#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address
-#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address
-#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address
-#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address
-#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address
-#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address
-#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address
-#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address
-#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address
-#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address
-#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address
-#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address
-#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address
-#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address
-#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address
-#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address
-#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address
-#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address
-#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address
-#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address
-#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address
-#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address
-#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address
-#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address
-#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address
-#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address
-#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address
-#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address
-#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address
-#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address
-#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address
-#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address
-#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address
-#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address
-#define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address
-#define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address
-#define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address
-#define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address
-#define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address
-#define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address
-#define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address
-#define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address
-#define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address
-#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address
-#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address
-#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address
-#define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address
-#define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address
-#define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address
-#define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address
-
-// *****************************************************************************
-// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address
-#define AT91C_ISRAM_SIZE ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte)
-#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address
-#define AT91C_IFLASH_SIZE ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte)
-
-#define AT91F_AIC_ConfigureIt( irq_id, priority, src_type, newHandler ) \
-{ \
- unsigned int mask ; \
- \
- mask = 0x1 << irq_id; \
- /* Disable the interrupt on the interrupt controller */ \
- AT91C_BASE_AIC->AIC_IDCR = mask ; \
- /* Save the interrupt handler routine pointer and the interrupt priority */ \
- AT91C_BASE_AIC->AIC_SVR[irq_id] = (unsigned int) newHandler ; \
- /* Store the Source Mode Register */ \
- AT91C_BASE_AIC->AIC_SMR[irq_id] = src_type | priority ; \
- /* Clear the interrupt on the interrupt controller */ \
- AT91C_BASE_AIC->AIC_ICCR = mask ; \
-}
-
-
-#endif
+// ----------------------------------------------------------------------------
+// ATMEL Microcontroller Software Support - ROUSSET -
+// ----------------------------------------------------------------------------
+// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ----------------------------------------------------------------------------
+// File Name : AT91SAM7X256.h
+// Object : AT91SAM7X256 definitions
+// Generated : AT91 SW Application Group 05/20/2005 (16:22:29)
+//
+// CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005//
+// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005//
+// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
+// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005//
+// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005//
+// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
+// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
+// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
+// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005//
+// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004//
+// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004//
+// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004//
+// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005//
+// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005//
+// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
+// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
+// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
+// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
+// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
+// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
+// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005//
+// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005//
+// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
+// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005//
+// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
+// ----------------------------------------------------------------------------
+
+#ifndef AT91SAM7X256_H
+#define AT91SAM7X256_H
+
+typedef volatile unsigned int AT91_REG;// Hardware register definition
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR System Peripherals
+// *****************************************************************************
+typedef struct _AT91S_SYS {
+ AT91_REG AIC_SMR[32]; // Source Mode Register
+ AT91_REG AIC_SVR[32]; // Source Vector Register
+ AT91_REG AIC_IVR; // IRQ Vector Register
+ AT91_REG AIC_FVR; // FIQ Vector Register
+ AT91_REG AIC_ISR; // Interrupt Status Register
+ AT91_REG AIC_IPR; // Interrupt Pending Register
+ AT91_REG AIC_IMR; // Interrupt Mask Register
+ AT91_REG AIC_CISR; // Core Interrupt Status Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register
+ AT91_REG AIC_SPU; // Spurious Vector Register
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)
+ AT91_REG Reserved1[1]; //
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register
+ AT91_REG Reserved2[45]; //
+ AT91_REG DBGU_CR; // Control Register
+ AT91_REG DBGU_MR; // Mode Register
+ AT91_REG DBGU_IER; // Interrupt Enable Register
+ AT91_REG DBGU_IDR; // Interrupt Disable Register
+ AT91_REG DBGU_IMR; // Interrupt Mask Register
+ AT91_REG DBGU_CSR; // Channel Status Register
+ AT91_REG DBGU_RHR; // Receiver Holding Register
+ AT91_REG DBGU_THR; // Transmitter Holding Register
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register
+ AT91_REG Reserved3[7]; //
+ AT91_REG DBGU_CIDR; // Chip ID Register
+ AT91_REG DBGU_EXID; // Chip ID Extension Register
+ AT91_REG DBGU_FNTR; // Force NTRST Register
+ AT91_REG Reserved4[45]; //
+ AT91_REG DBGU_RPR; // Receive Pointer Register
+ AT91_REG DBGU_RCR; // Receive Counter Register
+ AT91_REG DBGU_TPR; // Transmit Pointer Register
+ AT91_REG DBGU_TCR; // Transmit Counter Register
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register
+ AT91_REG Reserved5[54]; //
+ AT91_REG PIOA_PER; // PIO Enable Register
+ AT91_REG PIOA_PDR; // PIO Disable Register
+ AT91_REG PIOA_PSR; // PIO Status Register
+ AT91_REG Reserved6[1]; //
+ AT91_REG PIOA_OER; // Output Enable Register
+ AT91_REG PIOA_ODR; // Output Disable Registerr
+ AT91_REG PIOA_OSR; // Output Status Register
+ AT91_REG Reserved7[1]; //
+ AT91_REG PIOA_IFER; // Input Filter Enable Register
+ AT91_REG PIOA_IFDR; // Input Filter Disable Register
+ AT91_REG PIOA_IFSR; // Input Filter Status Register
+ AT91_REG Reserved8[1]; //
+ AT91_REG PIOA_SODR; // Set Output Data Register
+ AT91_REG PIOA_CODR; // Clear Output Data Register
+ AT91_REG PIOA_ODSR; // Output Data Status Register
+ AT91_REG PIOA_PDSR; // Pin Data Status Register
+ AT91_REG PIOA_IER; // Interrupt Enable Register
+ AT91_REG PIOA_IDR; // Interrupt Disable Register
+ AT91_REG PIOA_IMR; // Interrupt Mask Register
+ AT91_REG PIOA_ISR; // Interrupt Status Register
+ AT91_REG PIOA_MDER; // Multi-driver Enable Register
+ AT91_REG PIOA_MDDR; // Multi-driver Disable Register
+ AT91_REG PIOA_MDSR; // Multi-driver Status Register
+ AT91_REG Reserved9[1]; //
+ AT91_REG PIOA_PPUDR; // Pull-up Disable Register
+ AT91_REG PIOA_PPUER; // Pull-up Enable Register
+ AT91_REG PIOA_PPUSR; // Pull-up Status Register
+ AT91_REG Reserved10[1]; //
+ AT91_REG PIOA_ASR; // Select A Register
+ AT91_REG PIOA_BSR; // Select B Register
+ AT91_REG PIOA_ABSR; // AB Select Status Register
+ AT91_REG Reserved11[9]; //
+ AT91_REG PIOA_OWER; // Output Write Enable Register
+ AT91_REG PIOA_OWDR; // Output Write Disable Register
+ AT91_REG PIOA_OWSR; // Output Write Status Register
+ AT91_REG Reserved12[85]; //
+ AT91_REG PIOB_PER; // PIO Enable Register
+ AT91_REG PIOB_PDR; // PIO Disable Register
+ AT91_REG PIOB_PSR; // PIO Status Register
+ AT91_REG Reserved13[1]; //
+ AT91_REG PIOB_OER; // Output Enable Register
+ AT91_REG PIOB_ODR; // Output Disable Registerr
+ AT91_REG PIOB_OSR; // Output Status Register
+ AT91_REG Reserved14[1]; //
+ AT91_REG PIOB_IFER; // Input Filter Enable Register
+ AT91_REG PIOB_IFDR; // Input Filter Disable Register
+ AT91_REG PIOB_IFSR; // Input Filter Status Register
+ AT91_REG Reserved15[1]; //
+ AT91_REG PIOB_SODR; // Set Output Data Register
+ AT91_REG PIOB_CODR; // Clear Output Data Register
+ AT91_REG PIOB_ODSR; // Output Data Status Register
+ AT91_REG PIOB_PDSR; // Pin Data Status Register
+ AT91_REG PIOB_IER; // Interrupt Enable Register
+ AT91_REG PIOB_IDR; // Interrupt Disable Register
+ AT91_REG PIOB_IMR; // Interrupt Mask Register
+ AT91_REG PIOB_ISR; // Interrupt Status Register
+ AT91_REG PIOB_MDER; // Multi-driver Enable Register
+ AT91_REG PIOB_MDDR; // Multi-driver Disable Register
+ AT91_REG PIOB_MDSR; // Multi-driver Status Register
+ AT91_REG Reserved16[1]; //
+ AT91_REG PIOB_PPUDR; // Pull-up Disable Register
+ AT91_REG PIOB_PPUER; // Pull-up Enable Register
+ AT91_REG PIOB_PPUSR; // Pull-up Status Register
+ AT91_REG Reserved17[1]; //
+ AT91_REG PIOB_ASR; // Select A Register
+ AT91_REG PIOB_BSR; // Select B Register
+ AT91_REG PIOB_ABSR; // AB Select Status Register
+ AT91_REG Reserved18[9]; //
+ AT91_REG PIOB_OWER; // Output Write Enable Register
+ AT91_REG PIOB_OWDR; // Output Write Disable Register
+ AT91_REG PIOB_OWSR; // Output Write Status Register
+ AT91_REG Reserved19[341]; //
+ AT91_REG PMC_SCER; // System Clock Enable Register
+ AT91_REG PMC_SCDR; // System Clock Disable Register
+ AT91_REG PMC_SCSR; // System Clock Status Register
+ AT91_REG Reserved20[1]; //
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register
+ AT91_REG Reserved21[1]; //
+ AT91_REG PMC_MOR; // Main Oscillator Register
+ AT91_REG PMC_MCFR; // Main Clock Frequency Register
+ AT91_REG Reserved22[1]; //
+ AT91_REG PMC_PLLR; // PLL Register
+ AT91_REG PMC_MCKR; // Master Clock Register
+ AT91_REG Reserved23[3]; //
+ AT91_REG PMC_PCKR[4]; // Programmable Clock Register
+ AT91_REG Reserved24[4]; //
+ AT91_REG PMC_IER; // Interrupt Enable Register
+ AT91_REG PMC_IDR; // Interrupt Disable Register
+ AT91_REG PMC_SR; // Status Register
+ AT91_REG PMC_IMR; // Interrupt Mask Register
+ AT91_REG Reserved25[36]; //
+ AT91_REG RSTC_RCR; // Reset Control Register
+ AT91_REG RSTC_RSR; // Reset Status Register
+ AT91_REG RSTC_RMR; // Reset Mode Register
+ AT91_REG Reserved26[5]; //
+ AT91_REG RTTC_RTMR; // Real-time Mode Register
+ AT91_REG RTTC_RTAR; // Real-time Alarm Register
+ AT91_REG RTTC_RTVR; // Real-time Value Register
+ AT91_REG RTTC_RTSR; // Real-time Status Register
+ AT91_REG PITC_PIMR; // Period Interval Mode Register
+ AT91_REG PITC_PISR; // Period Interval Status Register
+ AT91_REG PITC_PIVR; // Period Interval Value Register
+ AT91_REG PITC_PIIR; // Period Interval Image Register
+ AT91_REG WDTC_WDCR; // Watchdog Control Register
+ AT91_REG WDTC_WDMR; // Watchdog Mode Register
+ AT91_REG WDTC_WDSR; // Watchdog Status Register
+ AT91_REG Reserved27[5]; //
+ AT91_REG VREG_MR; // Voltage Regulator Mode Register
+} AT91S_SYS, *AT91PS_SYS;
+
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
+// *****************************************************************************
+typedef struct _AT91S_AIC {
+ AT91_REG AIC_SMR[32]; // Source Mode Register
+ AT91_REG AIC_SVR[32]; // Source Vector Register
+ AT91_REG AIC_IVR; // IRQ Vector Register
+ AT91_REG AIC_FVR; // FIQ Vector Register
+ AT91_REG AIC_ISR; // Interrupt Status Register
+ AT91_REG AIC_IPR; // Interrupt Pending Register
+ AT91_REG AIC_IMR; // Interrupt Mask Register
+ AT91_REG AIC_CISR; // Core Interrupt Status Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register
+ AT91_REG AIC_SPU; // Spurious Vector Register
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)
+ AT91_REG Reserved1[1]; //
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register
+} AT91S_AIC, *AT91PS_AIC;
+
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
+#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level
+#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level
+#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level
+#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type
+#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive
+#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive
+#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered
+#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered
+#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
+#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
+#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status
+#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
+#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode
+#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Peripheral DMA Controller
+// *****************************************************************************
+typedef struct _AT91S_PDC {
+ AT91_REG PDC_RPR; // Receive Pointer Register
+ AT91_REG PDC_RCR; // Receive Counter Register
+ AT91_REG PDC_TPR; // Transmit Pointer Register
+ AT91_REG PDC_TCR; // Transmit Counter Register
+ AT91_REG PDC_RNPR; // Receive Next Pointer Register
+ AT91_REG PDC_RNCR; // Receive Next Counter Register
+ AT91_REG PDC_TNPR; // Transmit Next Pointer Register
+ AT91_REG PDC_TNCR; // Transmit Next Counter Register
+ AT91_REG PDC_PTCR; // PDC Transfer Control Register
+ AT91_REG PDC_PTSR; // PDC Transfer Status Register
+} AT91S_PDC, *AT91PS_PDC;
+
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
+#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable
+#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable
+#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable
+#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Debug Unit
+// *****************************************************************************
+typedef struct _AT91S_DBGU {
+ AT91_REG DBGU_CR; // Control Register
+ AT91_REG DBGU_MR; // Mode Register
+ AT91_REG DBGU_IER; // Interrupt Enable Register
+ AT91_REG DBGU_IDR; // Interrupt Disable Register
+ AT91_REG DBGU_IMR; // Interrupt Mask Register
+ AT91_REG DBGU_CSR; // Channel Status Register
+ AT91_REG DBGU_RHR; // Receiver Holding Register
+ AT91_REG DBGU_THR; // Transmitter Holding Register
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register
+ AT91_REG Reserved0[7]; //
+ AT91_REG DBGU_CIDR; // Chip ID Register
+ AT91_REG DBGU_EXID; // Chip ID Extension Register
+ AT91_REG DBGU_FNTR; // Force NTRST Register
+ AT91_REG Reserved1[45]; //
+ AT91_REG DBGU_RPR; // Receive Pointer Register
+ AT91_REG DBGU_RCR; // Receive Counter Register
+ AT91_REG DBGU_TPR; // Transmit Pointer Register
+ AT91_REG DBGU_TCR; // Transmit Counter Register
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register
+} AT91S_DBGU, *AT91PS_DBGU;
+
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
+#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver
+#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter
+#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable
+#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable
+#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable
+#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable
+#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
+#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type
+#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity
+#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity
+#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space)
+#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
+#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity
+#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode
+#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
+#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
+#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt
+#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt
+#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
+#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt
+#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt
+#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt
+#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt
+#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt
+#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
+#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
+#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
+#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
+#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
+// *****************************************************************************
+typedef struct _AT91S_PIO {
+ AT91_REG PIO_PER; // PIO Enable Register
+ AT91_REG PIO_PDR; // PIO Disable Register
+ AT91_REG PIO_PSR; // PIO Status Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG PIO_OER; // Output Enable Register
+ AT91_REG PIO_ODR; // Output Disable Registerr
+ AT91_REG PIO_OSR; // Output Status Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG PIO_IFER; // Input Filter Enable Register
+ AT91_REG PIO_IFDR; // Input Filter Disable Register
+ AT91_REG PIO_IFSR; // Input Filter Status Register
+ AT91_REG Reserved2[1]; //
+ AT91_REG PIO_SODR; // Set Output Data Register
+ AT91_REG PIO_CODR; // Clear Output Data Register
+ AT91_REG PIO_ODSR; // Output Data Status Register
+ AT91_REG PIO_PDSR; // Pin Data Status Register
+ AT91_REG PIO_IER; // Interrupt Enable Register
+ AT91_REG PIO_IDR; // Interrupt Disable Register
+ AT91_REG PIO_IMR; // Interrupt Mask Register
+ AT91_REG PIO_ISR; // Interrupt Status Register
+ AT91_REG PIO_MDER; // Multi-driver Enable Register
+ AT91_REG PIO_MDDR; // Multi-driver Disable Register
+ AT91_REG PIO_MDSR; // Multi-driver Status Register
+ AT91_REG Reserved3[1]; //
+ AT91_REG PIO_PPUDR; // Pull-up Disable Register
+ AT91_REG PIO_PPUER; // Pull-up Enable Register
+ AT91_REG PIO_PPUSR; // Pull-up Status Register
+ AT91_REG Reserved4[1]; //
+ AT91_REG PIO_ASR; // Select A Register
+ AT91_REG PIO_BSR; // Select B Register
+ AT91_REG PIO_ABSR; // AB Select Status Register
+ AT91_REG Reserved5[9]; //
+ AT91_REG PIO_OWER; // Output Write Enable Register
+ AT91_REG PIO_OWDR; // Output Write Disable Register
+ AT91_REG PIO_OWSR; // Output Write Status Register
+} AT91S_PIO, *AT91PS_PIO;
+
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Clock Generator Controler
+// *****************************************************************************
+typedef struct _AT91S_CKGR {
+ AT91_REG CKGR_MOR; // Main Oscillator Register
+ AT91_REG CKGR_MCFR; // Main Clock Frequency Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG CKGR_PLLR; // PLL Register
+} AT91S_CKGR, *AT91PS_CKGR;
+
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
+#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable
+#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass
+#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
+#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency
+#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
+// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
+#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected
+#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0
+#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed
+#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter
+#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
+#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
+#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
+#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
+#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
+#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Power Management Controler
+// *****************************************************************************
+typedef struct _AT91S_PMC {
+ AT91_REG PMC_SCER; // System Clock Enable Register
+ AT91_REG PMC_SCDR; // System Clock Disable Register
+ AT91_REG PMC_SCSR; // System Clock Status Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG PMC_MOR; // Main Oscillator Register
+ AT91_REG PMC_MCFR; // Main Clock Frequency Register
+ AT91_REG Reserved2[1]; //
+ AT91_REG PMC_PLLR; // PLL Register
+ AT91_REG PMC_MCKR; // Master Clock Register
+ AT91_REG Reserved3[3]; //
+ AT91_REG PMC_PCKR[4]; // Programmable Clock Register
+ AT91_REG Reserved4[4]; //
+ AT91_REG PMC_IER; // Interrupt Enable Register
+ AT91_REG PMC_IDR; // Interrupt Disable Register
+ AT91_REG PMC_SR; // Status Register
+ AT91_REG PMC_IMR; // Interrupt Mask Register
+} AT91S_PMC, *AT91PS_PMC;
+
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
+#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock
+#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock
+#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
+// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
+#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection
+#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected
+#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected
+#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
+#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler
+#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock
+#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2
+#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4
+#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8
+#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16
+#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32
+#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
+#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask
+#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Reset Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RSTC {
+ AT91_REG RSTC_RCR; // Reset Control Register
+ AT91_REG RSTC_RSR; // Reset Status Register
+ AT91_REG RSTC_RMR; // Reset Mode Register
+} AT91S_RSTC, *AT91PS_RSTC;
+
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
+#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset
+#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset
+#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset
+#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
+#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status
+#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status
+#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type
+#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.
+#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.
+#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
+#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
+#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
+#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured.
+#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
+#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
+#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable
+#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable
+#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable
+#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RTTC {
+ AT91_REG RTTC_RTMR; // Real-time Mode Register
+ AT91_REG RTTC_RTAR; // Real-time Alarm Register
+ AT91_REG RTTC_RTVR; // Real-time Value Register
+ AT91_REG RTTC_RTSR; // Real-time Status Register
+} AT91S_RTTC, *AT91PS_RTTC;
+
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
+#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
+#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
+#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
+#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
+#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
+#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
+#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status
+#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PITC {
+ AT91_REG PITC_PIMR; // Period Interval Mode Register
+ AT91_REG PITC_PISR; // Period Interval Status Register
+ AT91_REG PITC_PIVR; // Period Interval Value Register
+ AT91_REG PITC_PIIR; // Period Interval Image Register
+} AT91S_PITC, *AT91PS_PITC;
+
+// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
+#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value
+#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
+#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
+// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
+#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status
+// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
+#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value
+#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
+// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_WDTC {
+ AT91_REG WDTC_WDCR; // Watchdog Control Register
+ AT91_REG WDTC_WDMR; // Watchdog Mode Register
+ AT91_REG WDTC_WDSR; // Watchdog Status Register
+} AT91S_WDTC, *AT91PS_WDTC;
+
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
+#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart
+#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
+#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
+#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
+#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
+#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
+#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
+#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
+#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow
+#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_VREG {
+ AT91_REG VREG_MR; // Voltage Regulator Mode Register
+} AT91S_VREG, *AT91PS_VREG;
+
+// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
+#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Memory Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_MC {
+ AT91_REG MC_RCR; // MC Remap Control Register
+ AT91_REG MC_ASR; // MC Abort Status Register
+ AT91_REG MC_AASR; // MC Abort Address Status Register
+ AT91_REG Reserved0[21]; //
+ AT91_REG MC_FMR; // MC Flash Mode Register
+ AT91_REG MC_FCR; // MC Flash Command Register
+ AT91_REG MC_FSR; // MC Flash Status Register
+} AT91S_MC, *AT91PS_MC;
+
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
+#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
+#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status
+#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status
+#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status
+#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte
+#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word
+#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word
+#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
+#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read
+#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write
+#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch
+#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
+#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
+#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
+#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
+// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
+#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready
+#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error
+#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error
+#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming
+#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State
+#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations
+#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations
+#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations
+#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations
+#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
+// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
+#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command
+#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
+#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
+#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
+#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
+#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
+#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit.
+#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number
+#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
+// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
+#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status
+#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status
+#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status
+#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
+#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
+#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
+#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
+#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
+#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
+#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
+#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
+#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
+#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
+#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
+#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
+#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
+#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
+#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
+#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
+#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
+#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
+#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
+#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Serial Parallel Interface
+// *****************************************************************************
+typedef struct _AT91S_SPI {
+ AT91_REG SPI_CR; // Control Register
+ AT91_REG SPI_MR; // Mode Register
+ AT91_REG SPI_RDR; // Receive Data Register
+ AT91_REG SPI_TDR; // Transmit Data Register
+ AT91_REG SPI_SR; // Status Register
+ AT91_REG SPI_IER; // Interrupt Enable Register
+ AT91_REG SPI_IDR; // Interrupt Disable Register
+ AT91_REG SPI_IMR; // Interrupt Mask Register
+ AT91_REG Reserved0[4]; //
+ AT91_REG SPI_CSR[4]; // Chip Select Register
+ AT91_REG Reserved1[48]; //
+ AT91_REG SPI_RPR; // Receive Pointer Register
+ AT91_REG SPI_RCR; // Receive Counter Register
+ AT91_REG SPI_TPR; // Transmit Pointer Register
+ AT91_REG SPI_TCR; // Transmit Counter Register
+ AT91_REG SPI_RNPR; // Receive Next Pointer Register
+ AT91_REG SPI_RNCR; // Receive Next Counter Register
+ AT91_REG SPI_TNPR; // Transmit Next Pointer Register
+ AT91_REG SPI_TNCR; // Transmit Next Counter Register
+ AT91_REG SPI_PTCR; // PDC Transfer Control Register
+ AT91_REG SPI_PTSR; // PDC Transfer Status Register
+} AT91S_SPI, *AT91PS_SPI;
+
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
+#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable
+#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable
+#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset
+#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
+#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode
+#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select
+#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select
+#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select
+#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode
+#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection
+#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection
+#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection
+#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
+#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
+#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data
+#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
+#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data
+#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
+#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full
+#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty
+#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error
+#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status
+#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt
+#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt
+#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt
+#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt
+#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
+#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity
+#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase
+#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer
+#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer
+#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer
+#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer
+#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer
+#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer
+#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer
+#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer
+#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer
+#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer
+#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer
+#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK
+#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Usart
+// *****************************************************************************
+typedef struct _AT91S_USART {
+ AT91_REG US_CR; // Control Register
+ AT91_REG US_MR; // Mode Register
+ AT91_REG US_IER; // Interrupt Enable Register
+ AT91_REG US_IDR; // Interrupt Disable Register
+ AT91_REG US_IMR; // Interrupt Mask Register
+ AT91_REG US_CSR; // Channel Status Register
+ AT91_REG US_RHR; // Receiver Holding Register
+ AT91_REG US_THR; // Transmitter Holding Register
+ AT91_REG US_BRGR; // Baud Rate Generator Register
+ AT91_REG US_RTOR; // Receiver Time-out Register
+ AT91_REG US_TTGR; // Transmitter Time-guard Register
+ AT91_REG Reserved0[5]; //
+ AT91_REG US_FIDI; // FI_DI_Ratio Register
+ AT91_REG US_NER; // Nb Errors Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG US_IF; // IRDA_FILTER Register
+ AT91_REG Reserved2[44]; //
+ AT91_REG US_RPR; // Receive Pointer Register
+ AT91_REG US_RCR; // Receive Counter Register
+ AT91_REG US_TPR; // Transmit Pointer Register
+ AT91_REG US_TCR; // Transmit Counter Register
+ AT91_REG US_RNPR; // Receive Next Pointer Register
+ AT91_REG US_RNCR; // Receive Next Counter Register
+ AT91_REG US_TNPR; // Transmit Next Pointer Register
+ AT91_REG US_TNCR; // Transmit Next Counter Register
+ AT91_REG US_PTCR; // PDC Transfer Control Register
+ AT91_REG US_PTSR; // PDC Transfer Status Register
+} AT91S_USART, *AT91PS_USART;
+
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
+#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break
+#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break
+#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out
+#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address
+#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
+#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
+#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
+#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
+#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
+#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
+#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
+#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode
+#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal
+#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485
+#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking
+#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem
+#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
+#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
+#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA
+#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking
+#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock
+#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1
+#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM)
+#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK)
+#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits
+#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits
+#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits
+#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits
+#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select
+#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
+#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
+#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
+#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order
+#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
+#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
+#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
+#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
+#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
+#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
+#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
+#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break
+#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out
+#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
+#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
+#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
+#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
+#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
+#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
+#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
+#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
+#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
+#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_SSC {
+ AT91_REG SSC_CR; // Control Register
+ AT91_REG SSC_CMR; // Clock Mode Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG SSC_RCMR; // Receive Clock ModeRegister
+ AT91_REG SSC_RFMR; // Receive Frame Mode Register
+ AT91_REG SSC_TCMR; // Transmit Clock Mode Register
+ AT91_REG SSC_TFMR; // Transmit Frame Mode Register
+ AT91_REG SSC_RHR; // Receive Holding Register
+ AT91_REG SSC_THR; // Transmit Holding Register
+ AT91_REG Reserved1[2]; //
+ AT91_REG SSC_RSHR; // Receive Sync Holding Register
+ AT91_REG SSC_TSHR; // Transmit Sync Holding Register
+ AT91_REG Reserved2[2]; //
+ AT91_REG SSC_SR; // Status Register
+ AT91_REG SSC_IER; // Interrupt Enable Register
+ AT91_REG SSC_IDR; // Interrupt Disable Register
+ AT91_REG SSC_IMR; // Interrupt Mask Register
+ AT91_REG Reserved3[44]; //
+ AT91_REG SSC_RPR; // Receive Pointer Register
+ AT91_REG SSC_RCR; // Receive Counter Register
+ AT91_REG SSC_TPR; // Transmit Pointer Register
+ AT91_REG SSC_TCR; // Transmit Counter Register
+ AT91_REG SSC_RNPR; // Receive Next Pointer Register
+ AT91_REG SSC_RNCR; // Receive Next Counter Register
+ AT91_REG SSC_TNPR; // Transmit Next Pointer Register
+ AT91_REG SSC_TNCR; // Transmit Next Counter Register
+ AT91_REG SSC_PTCR; // PDC Transfer Control Register
+ AT91_REG SSC_PTSR; // PDC Transfer Status Register
+} AT91S_SSC, *AT91PS_SSC;
+
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
+#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable
+#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable
+#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable
+#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable
+#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
+#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection
+#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock
+#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal
+#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin
+#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
+#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
+#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
+#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection
+#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start
+#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input
+#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input
+#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input
+#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input
+#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input
+#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input
+#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0
+#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
+#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
+#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length
+#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode
+#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First
+#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame
+#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
+#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
+#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
+#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value
+#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
+#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready
+#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty
+#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission
+#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty
+#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready
+#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun
+#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception
+#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full
+#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
+#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
+#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
+#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Two-wire Interface
+// *****************************************************************************
+typedef struct _AT91S_TWI {
+ AT91_REG TWI_CR; // Control Register
+ AT91_REG TWI_MMR; // Master Mode Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG TWI_IADR; // Internal Address Register
+ AT91_REG TWI_CWGR; // Clock Waveform Generator Register
+ AT91_REG Reserved1[3]; //
+ AT91_REG TWI_SR; // Status Register
+ AT91_REG TWI_IER; // Interrupt Enable Register
+ AT91_REG TWI_IDR; // Interrupt Disable Register
+ AT91_REG TWI_IMR; // Interrupt Mask Register
+ AT91_REG TWI_RHR; // Receive Holding Register
+ AT91_REG TWI_THR; // Transmit Holding Register
+} AT91S_TWI, *AT91PS_TWI;
+
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
+#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition
+#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition
+#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled
+#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled
+#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
+#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size
+#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address
+#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address
+#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address
+#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address
+#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
+#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
+#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider
+#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider
+#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
+#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed
+#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY
+#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error
+#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error
+#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR PWMC Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC_CH {
+ AT91_REG PWMC_CMR; // Channel Mode Register
+ AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register
+ AT91_REG PWMC_CPRDR; // Channel Period Register
+ AT91_REG PWMC_CCNTR; // Channel Counter Register
+ AT91_REG PWMC_CUPDR; // Channel Update Register
+ AT91_REG PWMC_Reserved[3]; // Reserved
+} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
+
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
+#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
+#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH)
+#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH)
+#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH)
+#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment
+#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity
+#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
+#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
+#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
+#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter
+// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
+#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC {
+ AT91_REG PWMC_MR; // PWMC Mode Register
+ AT91_REG PWMC_ENA; // PWMC Enable Register
+ AT91_REG PWMC_DIS; // PWMC Disable Register
+ AT91_REG PWMC_SR; // PWMC Status Register
+ AT91_REG PWMC_IER; // PWMC Interrupt Enable Register
+ AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register
+ AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register
+ AT91_REG PWMC_ISR; // PWMC Interrupt Status Register
+ AT91_REG Reserved0[55]; //
+ AT91_REG PWMC_VR; // PWMC Version Register
+ AT91_REG Reserved1[64]; //
+ AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel
+} AT91S_PWMC, *AT91PS_PWMC;
+
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
+#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor.
+#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A
+#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC)
+#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
+#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
+#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC)
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
+#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0
+#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1
+#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2
+#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
+// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
+// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
+// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
+// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR USB Device Interface
+// *****************************************************************************
+typedef struct _AT91S_UDP {
+ AT91_REG UDP_NUM; // Frame Number Register
+ AT91_REG UDP_GLBSTATE; // Global State Register
+ AT91_REG UDP_FADDR; // Function Address Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG UDP_IER; // Interrupt Enable Register
+ AT91_REG UDP_IDR; // Interrupt Disable Register
+ AT91_REG UDP_IMR; // Interrupt Mask Register
+ AT91_REG UDP_ISR; // Interrupt Status Register
+ AT91_REG UDP_ICR; // Interrupt Clear Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG UDP_RSTEP; // Reset Endpoint Register
+ AT91_REG Reserved2[1]; //
+ AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register
+ AT91_REG Reserved3[2]; //
+ AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register
+ AT91_REG Reserved4[3]; //
+ AT91_REG UDP_TXVC; // Transceiver Control Register
+} AT91S_UDP, *AT91PS_UDP;
+
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
+#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
+#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error
+#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
+#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable
+#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured
+#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume
+#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
+#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
+#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value
+#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
+#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt
+#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt
+#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt
+#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt
+#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt
+#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt
+#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
+#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
+#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
+#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
+#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0
+#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1
+#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2
+#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3
+#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4
+#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
+#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
+#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0
+#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
+#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
+#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready
+#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction
+#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type
+#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control
+#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT
+#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT
+#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT
+#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN
+#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN
+#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN
+#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
+#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
+#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
+// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
+#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP)
+#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_TC {
+ AT91_REG TC_CCR; // Channel Control Register
+ AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)
+ AT91_REG Reserved0[2]; //
+ AT91_REG TC_CV; // Counter Value
+ AT91_REG TC_RA; // Register A
+ AT91_REG TC_RB; // Register B
+ AT91_REG TC_RC; // Register C
+ AT91_REG TC_SR; // Status Register
+ AT91_REG TC_IER; // Interrupt Enable Register
+ AT91_REG TC_IDR; // Interrupt Disable Register
+ AT91_REG TC_IMR; // Interrupt Mask Register
+} AT91S_TC, *AT91PS_TC;
+
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
+#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command
+#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command
+#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
+#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection
+#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
+#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0
+#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1
+#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2
+#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert
+#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection
+#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal
+#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock
+#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock
+#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock
+#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
+#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
+#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare
+#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
+#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection
+#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
+#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
+#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
+#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
+#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection
+#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
+#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
+#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
+#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
+#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection
+#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
+#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
+#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
+#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
+#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
+#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
+#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection
+#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
+#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
+#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC)
+#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
+#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none
+#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set
+#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear
+#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
+#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
+#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None
+#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
+#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
+#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
+#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none
+#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set
+#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear
+#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
+#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
+#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None
+#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
+#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
+#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
+#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none
+#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set
+#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear
+#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
+#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
+#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none
+#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set
+#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear
+#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
+#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
+#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none
+#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set
+#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear
+#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
+#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
+#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none
+#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set
+#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear
+#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
+#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
+#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none
+#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set
+#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear
+#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
+#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
+#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none
+#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set
+#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear
+#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
+#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow
+#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun
+#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare
+#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare
+#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare
+#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading
+#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading
+#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger
+#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
+#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
+#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Timer Counter Interface
+// *****************************************************************************
+typedef struct _AT91S_TCB {
+ AT91S_TC TCB_TC0; // TC Channel 0
+ AT91_REG Reserved0[4]; //
+ AT91S_TC TCB_TC1; // TC Channel 1
+ AT91_REG Reserved1[4]; //
+ AT91S_TC TCB_TC2; // TC Channel 2
+ AT91_REG Reserved2[4]; //
+ AT91_REG TCB_BCR; // TC Block Control Register
+ AT91_REG TCB_BMR; // TC Block Mode Register
+} AT91S_TCB, *AT91PS_TCB;
+
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
+#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
+#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection
+#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
+#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0
+#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
+#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
+#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection
+#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1
+#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1
+#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1
+#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1
+#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection
+#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2
+#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2
+#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2
+#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface
+// *****************************************************************************
+typedef struct _AT91S_CAN_MB {
+ AT91_REG CAN_MB_MMR; // MailBox Mode Register
+ AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register
+ AT91_REG CAN_MB_MID; // MailBox ID Register
+ AT91_REG CAN_MB_MFID; // MailBox Family ID Register
+ AT91_REG CAN_MB_MSR; // MailBox Status Register
+ AT91_REG CAN_MB_MDL; // MailBox Data Low Register
+ AT91_REG CAN_MB_MDH; // MailBox Data High Register
+ AT91_REG CAN_MB_MCR; // MailBox Control Register
+} AT91S_CAN_MB, *AT91PS_CAN_MB;
+
+// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register --------
+#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark
+#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority
+#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type
+#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB)
+#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB)
+#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB)
+#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB)
+#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB)
+#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB)
+// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register --------
+#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode
+#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
+#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version
+// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register --------
+// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register --------
+// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register --------
+#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value
+#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code
+#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
+#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort
+#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready
+#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored
+// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register --------
+// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register --------
+// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register --------
+#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox
+#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Control Area Network Interface
+// *****************************************************************************
+typedef struct _AT91S_CAN {
+ AT91_REG CAN_MR; // Mode Register
+ AT91_REG CAN_IER; // Interrupt Enable Register
+ AT91_REG CAN_IDR; // Interrupt Disable Register
+ AT91_REG CAN_IMR; // Interrupt Mask Register
+ AT91_REG CAN_SR; // Status Register
+ AT91_REG CAN_BR; // Baudrate Register
+ AT91_REG CAN_TIM; // Timer Register
+ AT91_REG CAN_TIMESTP; // Time Stamp Register
+ AT91_REG CAN_ECR; // Error Counter Register
+ AT91_REG CAN_TCR; // Transfer Command Register
+ AT91_REG CAN_ACR; // Abort Command Register
+ AT91_REG Reserved0[52]; //
+ AT91_REG CAN_VR; // Version Register
+ AT91_REG Reserved1[64]; //
+ AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0
+ AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1
+ AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2
+ AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3
+ AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4
+ AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5
+ AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6
+ AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7
+ AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8
+ AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9
+ AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10
+ AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11
+ AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12
+ AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13
+ AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14
+ AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15
+} AT91S_CAN, *AT91PS_CAN;
+
+// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register --------
+#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable
+#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode
+#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode
+#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame
+#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame
+#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode
+#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze
+#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat
+// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register --------
+#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag
+#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag
+#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag
+#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag
+#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag
+#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag
+#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag
+#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag
+#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag
+#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag
+#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag
+#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag
+#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag
+#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag
+#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag
+#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag
+#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag
+#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag
+#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag
+#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag
+#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag
+#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag
+#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag
+#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag
+#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error
+#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error
+#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error
+#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error
+#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error
+// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register --------
+// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register --------
+// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register --------
+#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy
+#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy
+#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy
+// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register --------
+#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment
+#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment
+#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment
+#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment
+#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler
+#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode
+// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register --------
+#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field
+// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register --------
+// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register --------
+#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter
+#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter
+// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register --------
+#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field
+// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100
+// *****************************************************************************
+typedef struct _AT91S_EMAC {
+ AT91_REG EMAC_NCR; // Network Control Register
+ AT91_REG EMAC_NCFGR; // Network Configuration Register
+ AT91_REG EMAC_NSR; // Network Status Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG EMAC_TSR; // Transmit Status Register
+ AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer
+ AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer
+ AT91_REG EMAC_RSR; // Receive Status Register
+ AT91_REG EMAC_ISR; // Interrupt Status Register
+ AT91_REG EMAC_IER; // Interrupt Enable Register
+ AT91_REG EMAC_IDR; // Interrupt Disable Register
+ AT91_REG EMAC_IMR; // Interrupt Mask Register
+ AT91_REG EMAC_MAN; // PHY Maintenance Register
+ AT91_REG EMAC_PTR; // Pause Time Register
+ AT91_REG EMAC_PFR; // Pause Frames received Register
+ AT91_REG EMAC_FTO; // Frames Transmitted OK Register
+ AT91_REG EMAC_SCF; // Single Collision Frame Register
+ AT91_REG EMAC_MCF; // Multiple Collision Frame Register
+ AT91_REG EMAC_FRO; // Frames Received OK Register
+ AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register
+ AT91_REG EMAC_ALE; // Alignment Error Register
+ AT91_REG EMAC_DTF; // Deferred Transmission Frame Register
+ AT91_REG EMAC_LCOL; // Late Collision Register
+ AT91_REG EMAC_ECOL; // Excessive Collision Register
+ AT91_REG EMAC_TUND; // Transmit Underrun Error Register
+ AT91_REG EMAC_CSE; // Carrier Sense Error Register
+ AT91_REG EMAC_RRE; // Receive Ressource Error Register
+ AT91_REG EMAC_ROV; // Receive Overrun Errors Register
+ AT91_REG EMAC_RSE; // Receive Symbol Errors Register
+ AT91_REG EMAC_ELE; // Excessive Length Errors Register
+ AT91_REG EMAC_RJA; // Receive Jabbers Register
+ AT91_REG EMAC_USF; // Undersize Frames Register
+ AT91_REG EMAC_STE; // SQE Test Error Register
+ AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register
+ AT91_REG EMAC_TPF; // Transmitted Pause Frames Register
+ AT91_REG EMAC_HRB; // Hash Address Bottom[31:0]
+ AT91_REG EMAC_HRT; // Hash Address Top[63:32]
+ AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes
+ AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes
+ AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes
+ AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes
+ AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes
+ AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes
+ AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes
+ AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes
+ AT91_REG EMAC_TID; // Type ID Checking Register
+ AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register
+ AT91_REG EMAC_USRIO; // USER Input/Output Register
+ AT91_REG EMAC_WOL; // Wake On LAN Register
+ AT91_REG Reserved1[13]; //
+ AT91_REG EMAC_REV; // Revision Register
+} AT91S_EMAC, *AT91PS_EMAC;
+
+// -------- EMAC_NCR : (EMAC Offset: 0x0) --------
+#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
+#define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local.
+#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable.
+#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable.
+#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable.
+#define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers.
+#define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers.
+#define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers.
+#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure.
+#define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission.
+#define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt.
+#define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame
+#define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame
+// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register --------
+#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed.
+#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex.
+#define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames.
+#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames.
+#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast.
+#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable
+#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable.
+#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes.
+#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable.
+#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC)
+#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8
+#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16
+#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32
+#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64
+#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC)
+#define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC)
+#define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC)
+#define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer
+#define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer
+#define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
+#define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
+#define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable
+#define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS
+#define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC)
+#define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS
+// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register --------
+#define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC)
+#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC)
+#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC)
+// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register --------
+#define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC)
+#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC)
+#define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC)
+#define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go
+#define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame
+#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC)
+#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC)
+// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
+#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC)
+#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC)
+#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC)
+// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
+#define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC)
+#define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC)
+#define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC)
+#define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC)
+#define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC)
+#define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC)
+#define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC)
+#define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC)
+#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC)
+#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC)
+#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC)
+#define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC)
+#define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC)
+// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
+// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
+// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
+// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
+#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC)
+#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC)
+#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC)
+#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC)
+#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC)
+#define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC)
+// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register --------
+#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII
+// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register --------
+#define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address
+#define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable
+#define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable
+#define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable
+// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register --------
+#define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC)
+#define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC)
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Analog to Digital Convertor
+// *****************************************************************************
+typedef struct _AT91S_ADC {
+ AT91_REG ADC_CR; // ADC Control Register
+ AT91_REG ADC_MR; // ADC Mode Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG ADC_CHER; // ADC Channel Enable Register
+ AT91_REG ADC_CHDR; // ADC Channel Disable Register
+ AT91_REG ADC_CHSR; // ADC Channel Status Register
+ AT91_REG ADC_SR; // ADC Status Register
+ AT91_REG ADC_LCDR; // ADC Last Converted Data Register
+ AT91_REG ADC_IER; // ADC Interrupt Enable Register
+ AT91_REG ADC_IDR; // ADC Interrupt Disable Register
+ AT91_REG ADC_IMR; // ADC Interrupt Mask Register
+ AT91_REG ADC_CDR0; // ADC Channel Data Register 0
+ AT91_REG ADC_CDR1; // ADC Channel Data Register 1
+ AT91_REG ADC_CDR2; // ADC Channel Data Register 2
+ AT91_REG ADC_CDR3; // ADC Channel Data Register 3
+ AT91_REG ADC_CDR4; // ADC Channel Data Register 4
+ AT91_REG ADC_CDR5; // ADC Channel Data Register 5
+ AT91_REG ADC_CDR6; // ADC Channel Data Register 6
+ AT91_REG ADC_CDR7; // ADC Channel Data Register 7
+ AT91_REG Reserved1[44]; //
+ AT91_REG ADC_RPR; // Receive Pointer Register
+ AT91_REG ADC_RCR; // Receive Counter Register
+ AT91_REG ADC_TPR; // Transmit Pointer Register
+ AT91_REG ADC_TCR; // Transmit Counter Register
+ AT91_REG ADC_RNPR; // Receive Next Pointer Register
+ AT91_REG ADC_RNCR; // Receive Next Counter Register
+ AT91_REG ADC_TNPR; // Transmit Next Pointer Register
+ AT91_REG ADC_TNCR; // Transmit Next Counter Register
+ AT91_REG ADC_PTCR; // PDC Transfer Control Register
+ AT91_REG ADC_PTSR; // PDC Transfer Status Register
+} AT91S_ADC, *AT91PS_ADC;
+
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
+#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset
+#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
+#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable
+#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
+#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection
+#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
+#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
+#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
+#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
+#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
+#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
+#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
+#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution.
+#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution
+#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution
+#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
+#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode
+#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
+#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection
+#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time
+#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
+// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
+#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0
+#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1
+#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2
+#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3
+#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4
+#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5
+#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6
+#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7
+// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
+// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
+#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion
+#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion
+#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion
+#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion
+#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion
+#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion
+#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion
+#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion
+#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
+#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready
+#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun
+#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
+#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
+#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
+#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Advanced Encryption Standard
+// *****************************************************************************
+typedef struct _AT91S_AES {
+ AT91_REG AES_CR; // Control Register
+ AT91_REG AES_MR; // Mode Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG AES_IER; // Interrupt Enable Register
+ AT91_REG AES_IDR; // Interrupt Disable Register
+ AT91_REG AES_IMR; // Interrupt Mask Register
+ AT91_REG AES_ISR; // Interrupt Status Register
+ AT91_REG AES_KEYWxR[4]; // Key Word x Register
+ AT91_REG Reserved1[4]; //
+ AT91_REG AES_IDATAxR[4]; // Input Data x Register
+ AT91_REG AES_ODATAxR[4]; // Output Data x Register
+ AT91_REG AES_IVxR[4]; // Initialization Vector x Register
+ AT91_REG Reserved2[35]; //
+ AT91_REG AES_VR; // AES Version Register
+ AT91_REG AES_RPR; // Receive Pointer Register
+ AT91_REG AES_RCR; // Receive Counter Register
+ AT91_REG AES_TPR; // Transmit Pointer Register
+ AT91_REG AES_TCR; // Transmit Counter Register
+ AT91_REG AES_RNPR; // Receive Next Pointer Register
+ AT91_REG AES_RNCR; // Receive Next Counter Register
+ AT91_REG AES_TNPR; // Transmit Next Pointer Register
+ AT91_REG AES_TNCR; // Transmit Next Counter Register
+ AT91_REG AES_PTCR; // PDC Transfer Control Register
+ AT91_REG AES_PTSR; // PDC Transfer Status Register
+} AT91S_AES, *AT91PS_AES;
+
+// -------- AES_CR : (AES Offset: 0x0) Control Register --------
+#define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing
+#define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset
+#define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading
+// -------- AES_MR : (AES Offset: 0x4) Mode Register --------
+#define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode
+#define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay
+#define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode
+#define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
+#define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
+#define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet).
+#define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode
+#define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode.
+#define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
+#define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode.
+#define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode.
+#define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode.
+#define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode
+#define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size
+#define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit.
+#define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit.
+#define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit.
+#define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit.
+#define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit.
+#define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key
+#define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type
+#define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled.
+#define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled.
+#define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled.
+#define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled.
+#define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled.
+// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register --------
+#define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY
+#define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End
+#define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End
+#define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full
+#define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty
+#define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection
+// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register --------
+// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register --------
+// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register --------
+#define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status
+#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
+#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing.
+#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing.
+#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation.
+#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation.
+#define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access.
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard
+// *****************************************************************************
+typedef struct _AT91S_TDES {
+ AT91_REG TDES_CR; // Control Register
+ AT91_REG TDES_MR; // Mode Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG TDES_IER; // Interrupt Enable Register
+ AT91_REG TDES_IDR; // Interrupt Disable Register
+ AT91_REG TDES_IMR; // Interrupt Mask Register
+ AT91_REG TDES_ISR; // Interrupt Status Register
+ AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register
+ AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register
+ AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register
+ AT91_REG Reserved1[2]; //
+ AT91_REG TDES_IDATAxR[2]; // Input Data x Register
+ AT91_REG Reserved2[2]; //
+ AT91_REG TDES_ODATAxR[2]; // Output Data x Register
+ AT91_REG Reserved3[2]; //
+ AT91_REG TDES_IVxR[2]; // Initialization Vector x Register
+ AT91_REG Reserved4[37]; //
+ AT91_REG TDES_VR; // TDES Version Register
+ AT91_REG TDES_RPR; // Receive Pointer Register
+ AT91_REG TDES_RCR; // Receive Counter Register
+ AT91_REG TDES_TPR; // Transmit Pointer Register
+ AT91_REG TDES_TCR; // Transmit Counter Register
+ AT91_REG TDES_RNPR; // Receive Next Pointer Register
+ AT91_REG TDES_RNCR; // Receive Next Counter Register
+ AT91_REG TDES_TNPR; // Transmit Next Pointer Register
+ AT91_REG TDES_TNCR; // Transmit Next Counter Register
+ AT91_REG TDES_PTCR; // PDC Transfer Control Register
+ AT91_REG TDES_PTSR; // PDC Transfer Status Register
+} AT91S_TDES, *AT91PS_TDES;
+
+// -------- TDES_CR : (TDES Offset: 0x0) Control Register --------
+#define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing
+#define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset
+// -------- TDES_MR : (TDES Offset: 0x4) Mode Register --------
+#define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode
+#define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode
+#define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode
+#define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode
+#define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
+#define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
+#define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet).
+#define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode
+#define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
+#define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
+#define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode.
+#define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode.
+#define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode
+#define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size
+#define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit.
+#define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit.
+#define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit.
+#define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit.
+// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register --------
+#define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY
+#define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End
+#define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End
+#define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full
+#define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty
+#define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection
+// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register --------
+// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register --------
+// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register --------
+#define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status
+#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
+#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing.
+#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing.
+#define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access.
+
+// *****************************************************************************
+// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
+// *****************************************************************************
+// ========== Register definition for SYS peripheral ==========
+// ========== Register definition for AIC peripheral ==========
+#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register
+#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register
+#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register
+#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)
+#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register
+#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register
+#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register
+#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register
+#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register
+#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register
+#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register
+#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register
+#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register
+#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register
+#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register
+#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register
+#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register
+#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register
+// ========== Register definition for PDC_DBGU peripheral ==========
+#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
+#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
+#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
+#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
+#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
+#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register
+#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
+#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
+#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
+#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
+// ========== Register definition for DBGU peripheral ==========
+#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register
+#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register
+#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register
+#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register
+#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register
+#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register
+#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register
+#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register
+#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register
+#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register
+#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register
+#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register
+// ========== Register definition for PIOA peripheral ==========
+#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr
+#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register
+#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register
+#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register
+#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register
+#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register
+#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register
+#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register
+#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register
+#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register
+#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register
+#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register
+#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register
+#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register
+#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register
+#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register
+#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register
+#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register
+#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register
+#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register
+#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register
+#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register
+#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register
+#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register
+#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register
+#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register
+#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register
+#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register
+#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register
+// ========== Register definition for PIOB peripheral ==========
+#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register
+#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register
+#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register
+#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register
+#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register
+#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register
+#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register
+#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register
+#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register
+#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register
+#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register
+#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register
+#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register
+#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register
+#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register
+#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register
+#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr
+#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register
+#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register
+#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register
+#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register
+#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register
+#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register
+#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register
+#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register
+#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register
+#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register
+#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register
+#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register
+// ========== Register definition for CKGR peripheral ==========
+#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register
+#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register
+#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register
+// ========== Register definition for PMC peripheral ==========
+#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register
+#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
+#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register
+#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
+#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register
+#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
+#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register
+#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
+#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register
+#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register
+#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register
+#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register
+#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register
+#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register
+#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register
+// ========== Register definition for RSTC peripheral ==========
+#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register
+#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register
+#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register
+// ========== Register definition for RTTC peripheral ==========
+#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register
+#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register
+#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register
+#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register
+// ========== Register definition for PITC peripheral ==========
+#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register
+#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register
+#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register
+#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register
+// ========== Register definition for WDTC peripheral ==========
+#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register
+#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register
+#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register
+// ========== Register definition for VREG peripheral ==========
+#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
+// ========== Register definition for MC peripheral ==========
+#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register
+#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register
+#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register
+#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register
+#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register
+#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register
+// ========== Register definition for PDC_SPI1 peripheral ==========
+#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
+#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
+#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
+#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
+#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
+#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
+#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register
+#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
+#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
+#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
+// ========== Register definition for SPI1 peripheral ==========
+#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register
+#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register
+#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register
+#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register
+#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register
+#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register
+#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register
+#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register
+#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register
+// ========== Register definition for PDC_SPI0 peripheral ==========
+#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
+#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
+#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
+#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register
+#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
+#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
+#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
+#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
+#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
+#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
+// ========== Register definition for SPI0 peripheral ==========
+#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register
+#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register
+#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register
+#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register
+#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register
+#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register
+#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register
+#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register
+#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register
+// ========== Register definition for PDC_US1 peripheral ==========
+#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register
+#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
+#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register
+#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
+#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
+#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register
+#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
+#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register
+#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
+#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register
+// ========== Register definition for US1 peripheral ==========
+#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register
+#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register
+#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register
+#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register
+#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register
+#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register
+#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register
+#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register
+#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register
+#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register
+#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register
+#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register
+#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register
+#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register
+// ========== Register definition for PDC_US0 peripheral ==========
+#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
+#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
+#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register
+#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
+#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
+#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
+#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register
+#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register
+#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register
+#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register
+// ========== Register definition for US0 peripheral ==========
+#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register
+#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register
+#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register
+#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register
+#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register
+#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register
+#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register
+#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register
+#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register
+#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register
+#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register
+#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register
+#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register
+#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register
+// ========== Register definition for PDC_SSC peripheral ==========
+#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
+#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register
+#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
+#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
+#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
+#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register
+#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register
+#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
+#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
+#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
+// ========== Register definition for SSC peripheral ==========
+#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register
+#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register
+#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register
+#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register
+#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register
+#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister
+#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register
+#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register
+#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register
+#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register
+#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register
+#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register
+#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register
+#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register
+// ========== Register definition for TWI peripheral ==========
+#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register
+#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register
+#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register
+#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register
+#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register
+#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register
+#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register
+#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register
+#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register
+#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register
+// ========== Register definition for PWMC_CH3 peripheral ==========
+#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register
+#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved
+#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register
+#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
+#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
+#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register
+// ========== Register definition for PWMC_CH2 peripheral ==========
+#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved
+#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register
+#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
+#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register
+#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register
+#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH1 peripheral ==========
+#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved
+#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register
+#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register
+#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
+#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
+#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register
+// ========== Register definition for PWMC_CH0 peripheral ==========
+#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved
+#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register
+#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
+#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register
+#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register
+#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
+// ========== Register definition for PWMC peripheral ==========
+#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
+#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register
+#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
+#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register
+#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
+#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register
+#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
+#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register
+#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register
+// ========== Register definition for UDP peripheral ==========
+#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register
+#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register
+#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register
+#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register
+#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register
+#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register
+#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register
+#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register
+#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register
+#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register
+#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register
+#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register
+// ========== Register definition for TC0 peripheral ==========
+#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register
+#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C
+#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B
+#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register
+#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register
+#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A
+#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register
+#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value
+#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register
+// ========== Register definition for TC1 peripheral ==========
+#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B
+#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register
+#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register
+#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register
+#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register
+#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A
+#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C
+#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register
+#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value
+// ========== Register definition for TC2 peripheral ==========
+#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register
+#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value
+#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A
+#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B
+#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register
+#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register
+#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C
+#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register
+#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
+// ========== Register definition for TCB peripheral ==========
+#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register
+#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register
+// ========== Register definition for CAN_MB0 peripheral ==========
+#define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
+#define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register
+#define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register
+#define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register
+#define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
+#define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register
+#define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register
+// ========== Register definition for CAN_MB1 peripheral ==========
+#define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
+#define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register
+#define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register
+#define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register
+#define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register
+#define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register
+#define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
+// ========== Register definition for CAN_MB2 peripheral ==========
+#define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register
+#define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register
+#define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register
+#define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
+#define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register
+#define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
+#define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register
+// ========== Register definition for CAN_MB3 peripheral ==========
+#define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
+#define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register
+#define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register
+#define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register
+#define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register
+#define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
+#define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register
+// ========== Register definition for CAN_MB4 peripheral ==========
+#define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register
+#define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register
+#define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register
+#define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
+#define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register
+#define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register
+#define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
+#define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB5 peripheral ==========
+#define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register
+#define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register
+#define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
+#define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
+#define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register
+#define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
+#define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
+#define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB6 peripheral ==========
+#define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
+#define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register
+#define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register
+#define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
+#define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register
+#define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
+#define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
+// ========== Register definition for CAN_MB7 peripheral ==========
+#define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register
+#define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
+#define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
+#define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
+#define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register
+#define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
+#define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register
+// ========== Register definition for CAN peripheral ==========
+#define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register
+#define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register
+#define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register
+#define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register
+#define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register
+#define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register
+#define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register
+#define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register
+#define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register
+#define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register
+#define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register
+#define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register
+// ========== Register definition for EMAC peripheral ==========
+#define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register
+#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
+#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
+#define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register
+#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register
+#define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
+#define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register
+#define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
+#define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register
+#define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register
+#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
+#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register
+#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
+#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register
+#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register
+#define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register
+#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register
+#define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register
+#define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
+#define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
+#define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register
+#define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register
+#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
+#define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register
+#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register
+#define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register
+#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
+#define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
+#define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register
+#define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32]
+#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register
+#define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
+#define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
+#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register
+#define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register
+#define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register
+#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register
+#define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register
+#define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register
+#define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register
+#define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register
+#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
+#define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register
+#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register
+#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
+#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register
+#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
+#define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register
+#define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register
+// ========== Register definition for PDC_ADC peripheral ==========
+#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
+#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
+#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
+#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
+#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
+#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
+#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register
+#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register
+#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
+#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register
+// ========== Register definition for ADC peripheral ==========
+#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2
+#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3
+#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0
+#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5
+#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register
+#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register
+#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4
+#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1
+#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register
+#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register
+#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register
+#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7
+#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6
+#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register
+#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register
+#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register
+#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register
+#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register
+// ========== Register definition for PDC_AES peripheral ==========
+#define AT91C_AES_TPR ((AT91_REG *) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register
+#define AT91C_AES_PTCR ((AT91_REG *) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
+#define AT91C_AES_RNPR ((AT91_REG *) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
+#define AT91C_AES_TNCR ((AT91_REG *) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
+#define AT91C_AES_TCR ((AT91_REG *) 0xFFFA410C) // (PDC_AES) Transmit Counter Register
+#define AT91C_AES_RCR ((AT91_REG *) 0xFFFA4104) // (PDC_AES) Receive Counter Register
+#define AT91C_AES_RNCR ((AT91_REG *) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register
+#define AT91C_AES_TNPR ((AT91_REG *) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
+#define AT91C_AES_RPR ((AT91_REG *) 0xFFFA4100) // (PDC_AES) Receive Pointer Register
+#define AT91C_AES_PTSR ((AT91_REG *) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
+// ========== Register definition for AES peripheral ==========
+#define AT91C_AES_IVxR ((AT91_REG *) 0xFFFA4060) // (AES) Initialization Vector x Register
+#define AT91C_AES_MR ((AT91_REG *) 0xFFFA4004) // (AES) Mode Register
+#define AT91C_AES_VR ((AT91_REG *) 0xFFFA40FC) // (AES) AES Version Register
+#define AT91C_AES_ODATAxR ((AT91_REG *) 0xFFFA4050) // (AES) Output Data x Register
+#define AT91C_AES_IDATAxR ((AT91_REG *) 0xFFFA4040) // (AES) Input Data x Register
+#define AT91C_AES_CR ((AT91_REG *) 0xFFFA4000) // (AES) Control Register
+#define AT91C_AES_IDR ((AT91_REG *) 0xFFFA4014) // (AES) Interrupt Disable Register
+#define AT91C_AES_IMR ((AT91_REG *) 0xFFFA4018) // (AES) Interrupt Mask Register
+#define AT91C_AES_IER ((AT91_REG *) 0xFFFA4010) // (AES) Interrupt Enable Register
+#define AT91C_AES_KEYWxR ((AT91_REG *) 0xFFFA4020) // (AES) Key Word x Register
+#define AT91C_AES_ISR ((AT91_REG *) 0xFFFA401C) // (AES) Interrupt Status Register
+// ========== Register definition for PDC_TDES peripheral ==========
+#define AT91C_TDES_RNCR ((AT91_REG *) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
+#define AT91C_TDES_TCR ((AT91_REG *) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register
+#define AT91C_TDES_RCR ((AT91_REG *) 0xFFFA8104) // (PDC_TDES) Receive Counter Register
+#define AT91C_TDES_TNPR ((AT91_REG *) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
+#define AT91C_TDES_RNPR ((AT91_REG *) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
+#define AT91C_TDES_RPR ((AT91_REG *) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register
+#define AT91C_TDES_TNCR ((AT91_REG *) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
+#define AT91C_TDES_TPR ((AT91_REG *) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
+#define AT91C_TDES_PTSR ((AT91_REG *) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
+#define AT91C_TDES_PTCR ((AT91_REG *) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
+// ========== Register definition for TDES peripheral ==========
+#define AT91C_TDES_KEY2WxR ((AT91_REG *) 0xFFFA8028) // (TDES) Key 2 Word x Register
+#define AT91C_TDES_KEY3WxR ((AT91_REG *) 0xFFFA8030) // (TDES) Key 3 Word x Register
+#define AT91C_TDES_IDR ((AT91_REG *) 0xFFFA8014) // (TDES) Interrupt Disable Register
+#define AT91C_TDES_VR ((AT91_REG *) 0xFFFA80FC) // (TDES) TDES Version Register
+#define AT91C_TDES_IVxR ((AT91_REG *) 0xFFFA8060) // (TDES) Initialization Vector x Register
+#define AT91C_TDES_ODATAxR ((AT91_REG *) 0xFFFA8050) // (TDES) Output Data x Register
+#define AT91C_TDES_IMR ((AT91_REG *) 0xFFFA8018) // (TDES) Interrupt Mask Register
+#define AT91C_TDES_MR ((AT91_REG *) 0xFFFA8004) // (TDES) Mode Register
+#define AT91C_TDES_CR ((AT91_REG *) 0xFFFA8000) // (TDES) Control Register
+#define AT91C_TDES_IER ((AT91_REG *) 0xFFFA8010) // (TDES) Interrupt Enable Register
+#define AT91C_TDES_ISR ((AT91_REG *) 0xFFFA801C) // (TDES) Interrupt Status Register
+#define AT91C_TDES_IDATAxR ((AT91_REG *) 0xFFFA8040) // (TDES) Input Data x Register
+#define AT91C_TDES_KEY1WxR ((AT91_REG *) 0xFFFA8020) // (TDES) Key 1 Word x Register
+
+// *****************************************************************************
+// PIO DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0
+#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data
+#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1
+#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data
+#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10
+#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data
+#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11
+#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock
+#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12
+#define AT91C_PA12_NPCS00 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0
+#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13
+#define AT91C_PA13_NPCS01 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1
+#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1
+#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14
+#define AT91C_PA14_NPCS02 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2
+#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1
+#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15
+#define AT91C_PA15_NPCS03 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3
+#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input
+#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16
+#define AT91C_PA16_MISO0 ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave
+#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17
+#define AT91C_PA17_MOSI0 ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave
+#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18
+#define AT91C_PA18_SPCK0 ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock
+#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19
+#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive
+#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2
+#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock
+#define AT91C_PA2_NPCS11 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20
+#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit
+#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21
+#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync
+#define AT91C_PA21_NPCS10 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0
+#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22
+#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock
+#define AT91C_PA22_SPCK1 ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock
+#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23
+#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data
+#define AT91C_PA23_MOSI1 ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave
+#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24
+#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data
+#define AT91C_PA24_MISO1 ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave
+#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25
+#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock
+#define AT91C_PA25_NPCS11 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26
+#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync
+#define AT91C_PA26_NPCS12 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27
+#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data
+#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3
+#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28
+#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data
+#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29
+#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input
+#define AT91C_PA29_NPCS13 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3
+#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send
+#define AT91C_PA3_NPCS12 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30
+#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0
+#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2
+#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4
+#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send
+#define AT91C_PA4_NPCS13 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5
+#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data
+#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6
+#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data
+#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7
+#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock
+#define AT91C_PA7_NPCS01 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8
+#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send
+#define AT91C_PA8_NPCS02 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9
+#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send
+#define AT91C_PA9_NPCS03 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0
+#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock
+#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0
+#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1
+#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable
+#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10
+#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2
+#define AT91C_PB10_NPCS11 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11
+#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3
+#define AT91C_PB11_NPCS12 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12
+#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error
+#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input
+#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13
+#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2
+#define AT91C_PB13_NPCS01 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14
+#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3
+#define AT91C_PB14_NPCS02 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15
+#define AT91C_PB15_ERXDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid
+#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16
+#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected
+#define AT91C_PB16_NPCS13 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17
+#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock
+#define AT91C_PB17_NPCS03 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18
+#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec
+#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger
+#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19
+#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0
+#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input
+#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2
+#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0
+#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20
+#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1
+#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0
+#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21
+#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2
+#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1
+#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22
+#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3
+#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2
+#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23
+#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A
+#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect
+#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24
+#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B
+#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready
+#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25
+#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A
+#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready
+#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26
+#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B
+#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator
+#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27
+#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A
+#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0
+#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28
+#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B
+#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1
+#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29
+#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1
+#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2
+#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3
+#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1
+#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30
+#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2
+#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3
+#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4
+#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
+#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5
+#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0
+#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6
+#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1
+#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7
+#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error
+#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8
+#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock
+#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9
+#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output
+
+// *****************************************************************************
+// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ)
+#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral
+#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A
+#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B
+#define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0
+#define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1
+#define AT91C_ID_US0 ((unsigned int) 6) // USART 0
+#define AT91C_ID_US1 ((unsigned int) 7) // USART 1
+#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller
+#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface
+#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller
+#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port
+#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0
+#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1
+#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2
+#define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller
+#define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC
+#define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter
+#define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit
+#define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard
+#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
+#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
+#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
+#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
+#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
+#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
+#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
+#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
+#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
+#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
+#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
+#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
+
+// *****************************************************************************
+// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address
+#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address
+#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address
+#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address
+#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address
+#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address
+#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address
+#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address
+#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address
+#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address
+#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address
+#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address
+#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address
+#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address
+#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address
+#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address
+#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address
+#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address
+#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address
+#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address
+#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address
+#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address
+#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address
+#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address
+#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address
+#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address
+#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address
+#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address
+#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address
+#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address
+#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address
+#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address
+#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address
+#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address
+#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address
+#define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address
+#define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address
+#define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address
+#define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address
+#define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address
+#define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address
+#define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address
+#define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address
+#define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address
+#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address
+#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address
+#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address
+#define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address
+#define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address
+#define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address
+#define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address
+
+// *****************************************************************************
+// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address
+#define AT91C_ISRAM_SIZE ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte)
+#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address
+#define AT91C_IFLASH_SIZE ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte)
+
+#define AT91F_AIC_ConfigureIt( irq_id, priority, src_type, newHandler ) \
+{ \
+ unsigned int mask ; \
+ \
+ mask = 0x1 << irq_id; \
+ /* Disable the interrupt on the interrupt controller */ \
+ AT91C_BASE_AIC->AIC_IDCR = mask ; \
+ /* Save the interrupt handler routine pointer and the interrupt priority */ \
+ AT91C_BASE_AIC->AIC_SVR[irq_id] = (unsigned int) newHandler ; \
+ /* Store the Source Mode Register */ \
+ AT91C_BASE_AIC->AIC_SMR[irq_id] = src_type | priority ; \
+ /* Clear the interrupt on the interrupt controller */ \
+ AT91C_BASE_AIC->AIC_ICCR = mask ; \
+}
+
+
+#endif
diff --git a/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h b/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h
index 8ea721e..d4c43e8 100644
--- a/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h
+++ b/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h
@@ -1,4698 +1,4698 @@
-// - ----------------------------------------------------------------------------
-// - ATMEL Microcontroller Software Support - ROUSSET -
-// - ----------------------------------------------------------------------------
-// - DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-// - IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-// - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-// - DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-// - INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// - LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-// - OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-// - LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-// - NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-// - EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// - ----------------------------------------------------------------------------
-// - File Name : AT91SAM7X256.h
-// - Object : AT91SAM7X256 definitions
-// - Generated : AT91 SW Application Group 05/20/2005 (16:22:29)
-// -
-// - CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005//
-// - CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005//
-// - CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
-// - CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005//
-// - CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005//
-// - CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
-// - CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
-// - CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
-// - CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005//
-// - CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004//
-// - CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004//
-// - CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004//
-// - CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005//
-// - CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005//
-// - CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
-// - CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
-// - CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
-// - CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
-// - CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
-// - CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
-// - CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005//
-// - CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005//
-// - CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
-// - CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005//
-// - CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
-// - ----------------------------------------------------------------------------
-
-#ifndef AT91SAM7X256_H
-#define AT91SAM7X256_H
-
-typedef volatile unsigned int AT91_REG;// Hardware register definition
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR System Peripherals
-// *****************************************************************************
-typedef struct _AT91S_SYS {
- AT91_REG AIC_SMR[32]; // Source Mode Register
- AT91_REG AIC_SVR[32]; // Source Vector Register
- AT91_REG AIC_IVR; // IRQ Vector Register
- AT91_REG AIC_FVR; // FIQ Vector Register
- AT91_REG AIC_ISR; // Interrupt Status Register
- AT91_REG AIC_IPR; // Interrupt Pending Register
- AT91_REG AIC_IMR; // Interrupt Mask Register
- AT91_REG AIC_CISR; // Core Interrupt Status Register
- AT91_REG Reserved0[2]; //
- AT91_REG AIC_IECR; // Interrupt Enable Command Register
- AT91_REG AIC_IDCR; // Interrupt Disable Command Register
- AT91_REG AIC_ICCR; // Interrupt Clear Command Register
- AT91_REG AIC_ISCR; // Interrupt Set Command Register
- AT91_REG AIC_EOICR; // End of Interrupt Command Register
- AT91_REG AIC_SPU; // Spurious Vector Register
- AT91_REG AIC_DCR; // Debug Control Register (Protect)
- AT91_REG Reserved1[1]; //
- AT91_REG AIC_FFER; // Fast Forcing Enable Register
- AT91_REG AIC_FFDR; // Fast Forcing Disable Register
- AT91_REG AIC_FFSR; // Fast Forcing Status Register
- AT91_REG Reserved2[45]; //
- AT91_REG DBGU_CR; // Control Register
- AT91_REG DBGU_MR; // Mode Register
- AT91_REG DBGU_IER; // Interrupt Enable Register
- AT91_REG DBGU_IDR; // Interrupt Disable Register
- AT91_REG DBGU_IMR; // Interrupt Mask Register
- AT91_REG DBGU_CSR; // Channel Status Register
- AT91_REG DBGU_RHR; // Receiver Holding Register
- AT91_REG DBGU_THR; // Transmitter Holding Register
- AT91_REG DBGU_BRGR; // Baud Rate Generator Register
- AT91_REG Reserved3[7]; //
- AT91_REG DBGU_CIDR; // Chip ID Register
- AT91_REG DBGU_EXID; // Chip ID Extension Register
- AT91_REG DBGU_FNTR; // Force NTRST Register
- AT91_REG Reserved4[45]; //
- AT91_REG DBGU_RPR; // Receive Pointer Register
- AT91_REG DBGU_RCR; // Receive Counter Register
- AT91_REG DBGU_TPR; // Transmit Pointer Register
- AT91_REG DBGU_TCR; // Transmit Counter Register
- AT91_REG DBGU_RNPR; // Receive Next Pointer Register
- AT91_REG DBGU_RNCR; // Receive Next Counter Register
- AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
- AT91_REG DBGU_TNCR; // Transmit Next Counter Register
- AT91_REG DBGU_PTCR; // PDC Transfer Control Register
- AT91_REG DBGU_PTSR; // PDC Transfer Status Register
- AT91_REG Reserved5[54]; //
- AT91_REG PIOA_PER; // PIO Enable Register
- AT91_REG PIOA_PDR; // PIO Disable Register
- AT91_REG PIOA_PSR; // PIO Status Register
- AT91_REG Reserved6[1]; //
- AT91_REG PIOA_OER; // Output Enable Register
- AT91_REG PIOA_ODR; // Output Disable Registerr
- AT91_REG PIOA_OSR; // Output Status Register
- AT91_REG Reserved7[1]; //
- AT91_REG PIOA_IFER; // Input Filter Enable Register
- AT91_REG PIOA_IFDR; // Input Filter Disable Register
- AT91_REG PIOA_IFSR; // Input Filter Status Register
- AT91_REG Reserved8[1]; //
- AT91_REG PIOA_SODR; // Set Output Data Register
- AT91_REG PIOA_CODR; // Clear Output Data Register
- AT91_REG PIOA_ODSR; // Output Data Status Register
- AT91_REG PIOA_PDSR; // Pin Data Status Register
- AT91_REG PIOA_IER; // Interrupt Enable Register
- AT91_REG PIOA_IDR; // Interrupt Disable Register
- AT91_REG PIOA_IMR; // Interrupt Mask Register
- AT91_REG PIOA_ISR; // Interrupt Status Register
- AT91_REG PIOA_MDER; // Multi-driver Enable Register
- AT91_REG PIOA_MDDR; // Multi-driver Disable Register
- AT91_REG PIOA_MDSR; // Multi-driver Status Register
- AT91_REG Reserved9[1]; //
- AT91_REG PIOA_PPUDR; // Pull-up Disable Register
- AT91_REG PIOA_PPUER; // Pull-up Enable Register
- AT91_REG PIOA_PPUSR; // Pull-up Status Register
- AT91_REG Reserved10[1]; //
- AT91_REG PIOA_ASR; // Select A Register
- AT91_REG PIOA_BSR; // Select B Register
- AT91_REG PIOA_ABSR; // AB Select Status Register
- AT91_REG Reserved11[9]; //
- AT91_REG PIOA_OWER; // Output Write Enable Register
- AT91_REG PIOA_OWDR; // Output Write Disable Register
- AT91_REG PIOA_OWSR; // Output Write Status Register
- AT91_REG Reserved12[85]; //
- AT91_REG PIOB_PER; // PIO Enable Register
- AT91_REG PIOB_PDR; // PIO Disable Register
- AT91_REG PIOB_PSR; // PIO Status Register
- AT91_REG Reserved13[1]; //
- AT91_REG PIOB_OER; // Output Enable Register
- AT91_REG PIOB_ODR; // Output Disable Registerr
- AT91_REG PIOB_OSR; // Output Status Register
- AT91_REG Reserved14[1]; //
- AT91_REG PIOB_IFER; // Input Filter Enable Register
- AT91_REG PIOB_IFDR; // Input Filter Disable Register
- AT91_REG PIOB_IFSR; // Input Filter Status Register
- AT91_REG Reserved15[1]; //
- AT91_REG PIOB_SODR; // Set Output Data Register
- AT91_REG PIOB_CODR; // Clear Output Data Register
- AT91_REG PIOB_ODSR; // Output Data Status Register
- AT91_REG PIOB_PDSR; // Pin Data Status Register
- AT91_REG PIOB_IER; // Interrupt Enable Register
- AT91_REG PIOB_IDR; // Interrupt Disable Register
- AT91_REG PIOB_IMR; // Interrupt Mask Register
- AT91_REG PIOB_ISR; // Interrupt Status Register
- AT91_REG PIOB_MDER; // Multi-driver Enable Register
- AT91_REG PIOB_MDDR; // Multi-driver Disable Register
- AT91_REG PIOB_MDSR; // Multi-driver Status Register
- AT91_REG Reserved16[1]; //
- AT91_REG PIOB_PPUDR; // Pull-up Disable Register
- AT91_REG PIOB_PPUER; // Pull-up Enable Register
- AT91_REG PIOB_PPUSR; // Pull-up Status Register
- AT91_REG Reserved17[1]; //
- AT91_REG PIOB_ASR; // Select A Register
- AT91_REG PIOB_BSR; // Select B Register
- AT91_REG PIOB_ABSR; // AB Select Status Register
- AT91_REG Reserved18[9]; //
- AT91_REG PIOB_OWER; // Output Write Enable Register
- AT91_REG PIOB_OWDR; // Output Write Disable Register
- AT91_REG PIOB_OWSR; // Output Write Status Register
- AT91_REG Reserved19[341]; //
- AT91_REG PMC_SCER; // System Clock Enable Register
- AT91_REG PMC_SCDR; // System Clock Disable Register
- AT91_REG PMC_SCSR; // System Clock Status Register
- AT91_REG Reserved20[1]; //
- AT91_REG PMC_PCER; // Peripheral Clock Enable Register
- AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
- AT91_REG PMC_PCSR; // Peripheral Clock Status Register
- AT91_REG Reserved21[1]; //
- AT91_REG PMC_MOR; // Main Oscillator Register
- AT91_REG PMC_MCFR; // Main Clock Frequency Register
- AT91_REG Reserved22[1]; //
- AT91_REG PMC_PLLR; // PLL Register
- AT91_REG PMC_MCKR; // Master Clock Register
- AT91_REG Reserved23[3]; //
- AT91_REG PMC_PCKR[4]; // Programmable Clock Register
- AT91_REG Reserved24[4]; //
- AT91_REG PMC_IER; // Interrupt Enable Register
- AT91_REG PMC_IDR; // Interrupt Disable Register
- AT91_REG PMC_SR; // Status Register
- AT91_REG PMC_IMR; // Interrupt Mask Register
- AT91_REG Reserved25[36]; //
- AT91_REG RSTC_RCR; // Reset Control Register
- AT91_REG RSTC_RSR; // Reset Status Register
- AT91_REG RSTC_RMR; // Reset Mode Register
- AT91_REG Reserved26[5]; //
- AT91_REG RTTC_RTMR; // Real-time Mode Register
- AT91_REG RTTC_RTAR; // Real-time Alarm Register
- AT91_REG RTTC_RTVR; // Real-time Value Register
- AT91_REG RTTC_RTSR; // Real-time Status Register
- AT91_REG PITC_PIMR; // Period Interval Mode Register
- AT91_REG PITC_PISR; // Period Interval Status Register
- AT91_REG PITC_PIVR; // Period Interval Value Register
- AT91_REG PITC_PIIR; // Period Interval Image Register
- AT91_REG WDTC_WDCR; // Watchdog Control Register
- AT91_REG WDTC_WDMR; // Watchdog Mode Register
- AT91_REG WDTC_WDSR; // Watchdog Status Register
- AT91_REG Reserved27[5]; //
- AT91_REG VREG_MR; // Voltage Regulator Mode Register
-} AT91S_SYS, *AT91PS_SYS;
-
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
-// *****************************************************************************
-typedef struct _AT91S_AIC {
- AT91_REG AIC_SMR[32]; // Source Mode Register
- AT91_REG AIC_SVR[32]; // Source Vector Register
- AT91_REG AIC_IVR; // IRQ Vector Register
- AT91_REG AIC_FVR; // FIQ Vector Register
- AT91_REG AIC_ISR; // Interrupt Status Register
- AT91_REG AIC_IPR; // Interrupt Pending Register
- AT91_REG AIC_IMR; // Interrupt Mask Register
- AT91_REG AIC_CISR; // Core Interrupt Status Register
- AT91_REG Reserved0[2]; //
- AT91_REG AIC_IECR; // Interrupt Enable Command Register
- AT91_REG AIC_IDCR; // Interrupt Disable Command Register
- AT91_REG AIC_ICCR; // Interrupt Clear Command Register
- AT91_REG AIC_ISCR; // Interrupt Set Command Register
- AT91_REG AIC_EOICR; // End of Interrupt Command Register
- AT91_REG AIC_SPU; // Spurious Vector Register
- AT91_REG AIC_DCR; // Debug Control Register (Protect)
- AT91_REG Reserved1[1]; //
- AT91_REG AIC_FFER; // Fast Forcing Enable Register
- AT91_REG AIC_FFDR; // Fast Forcing Disable Register
- AT91_REG AIC_FFSR; // Fast Forcing Status Register
-} AT91S_AIC, *AT91PS_AIC;
-
-// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
-#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level
-#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level
-#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level
-#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type
-#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive
-#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive
-#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered
-#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered
-#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
-#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
-// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
-#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status
-#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status
-// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
-#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode
-#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Peripheral DMA Controller
-// *****************************************************************************
-typedef struct _AT91S_PDC {
- AT91_REG PDC_RPR; // Receive Pointer Register
- AT91_REG PDC_RCR; // Receive Counter Register
- AT91_REG PDC_TPR; // Transmit Pointer Register
- AT91_REG PDC_TCR; // Transmit Counter Register
- AT91_REG PDC_RNPR; // Receive Next Pointer Register
- AT91_REG PDC_RNCR; // Receive Next Counter Register
- AT91_REG PDC_TNPR; // Transmit Next Pointer Register
- AT91_REG PDC_TNCR; // Transmit Next Counter Register
- AT91_REG PDC_PTCR; // PDC Transfer Control Register
- AT91_REG PDC_PTSR; // PDC Transfer Status Register
-} AT91S_PDC, *AT91PS_PDC;
-
-// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
-#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable
-#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable
-#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable
-#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable
-// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Debug Unit
-// *****************************************************************************
-typedef struct _AT91S_DBGU {
- AT91_REG DBGU_CR; // Control Register
- AT91_REG DBGU_MR; // Mode Register
- AT91_REG DBGU_IER; // Interrupt Enable Register
- AT91_REG DBGU_IDR; // Interrupt Disable Register
- AT91_REG DBGU_IMR; // Interrupt Mask Register
- AT91_REG DBGU_CSR; // Channel Status Register
- AT91_REG DBGU_RHR; // Receiver Holding Register
- AT91_REG DBGU_THR; // Transmitter Holding Register
- AT91_REG DBGU_BRGR; // Baud Rate Generator Register
- AT91_REG Reserved0[7]; //
- AT91_REG DBGU_CIDR; // Chip ID Register
- AT91_REG DBGU_EXID; // Chip ID Extension Register
- AT91_REG DBGU_FNTR; // Force NTRST Register
- AT91_REG Reserved1[45]; //
- AT91_REG DBGU_RPR; // Receive Pointer Register
- AT91_REG DBGU_RCR; // Receive Counter Register
- AT91_REG DBGU_TPR; // Transmit Pointer Register
- AT91_REG DBGU_TCR; // Transmit Counter Register
- AT91_REG DBGU_RNPR; // Receive Next Pointer Register
- AT91_REG DBGU_RNCR; // Receive Next Counter Register
- AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
- AT91_REG DBGU_TNCR; // Transmit Next Counter Register
- AT91_REG DBGU_PTCR; // PDC Transfer Control Register
- AT91_REG DBGU_PTSR; // PDC Transfer Status Register
-} AT91S_DBGU, *AT91PS_DBGU;
-
-// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver
-#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter
-#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable
-#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable
-#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable
-#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable
-#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits
-// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type
-#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity
-#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity
-#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space)
-#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
-#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity
-#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode
-#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
-#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt
-#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt
-#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
-#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt
-#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt
-#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt
-#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt
-#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt
-#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
-#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
-#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
-#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
-// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
-// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
-#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
-// *****************************************************************************
-typedef struct _AT91S_PIO {
- AT91_REG PIO_PER; // PIO Enable Register
- AT91_REG PIO_PDR; // PIO Disable Register
- AT91_REG PIO_PSR; // PIO Status Register
- AT91_REG Reserved0[1]; //
- AT91_REG PIO_OER; // Output Enable Register
- AT91_REG PIO_ODR; // Output Disable Registerr
- AT91_REG PIO_OSR; // Output Status Register
- AT91_REG Reserved1[1]; //
- AT91_REG PIO_IFER; // Input Filter Enable Register
- AT91_REG PIO_IFDR; // Input Filter Disable Register
- AT91_REG PIO_IFSR; // Input Filter Status Register
- AT91_REG Reserved2[1]; //
- AT91_REG PIO_SODR; // Set Output Data Register
- AT91_REG PIO_CODR; // Clear Output Data Register
- AT91_REG PIO_ODSR; // Output Data Status Register
- AT91_REG PIO_PDSR; // Pin Data Status Register
- AT91_REG PIO_IER; // Interrupt Enable Register
- AT91_REG PIO_IDR; // Interrupt Disable Register
- AT91_REG PIO_IMR; // Interrupt Mask Register
- AT91_REG PIO_ISR; // Interrupt Status Register
- AT91_REG PIO_MDER; // Multi-driver Enable Register
- AT91_REG PIO_MDDR; // Multi-driver Disable Register
- AT91_REG PIO_MDSR; // Multi-driver Status Register
- AT91_REG Reserved3[1]; //
- AT91_REG PIO_PPUDR; // Pull-up Disable Register
- AT91_REG PIO_PPUER; // Pull-up Enable Register
- AT91_REG PIO_PPUSR; // Pull-up Status Register
- AT91_REG Reserved4[1]; //
- AT91_REG PIO_ASR; // Select A Register
- AT91_REG PIO_BSR; // Select B Register
- AT91_REG PIO_ABSR; // AB Select Status Register
- AT91_REG Reserved5[9]; //
- AT91_REG PIO_OWER; // Output Write Enable Register
- AT91_REG PIO_OWDR; // Output Write Disable Register
- AT91_REG PIO_OWSR; // Output Write Status Register
-} AT91S_PIO, *AT91PS_PIO;
-
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Clock Generator Controler
-// *****************************************************************************
-typedef struct _AT91S_CKGR {
- AT91_REG CKGR_MOR; // Main Oscillator Register
- AT91_REG CKGR_MCFR; // Main Clock Frequency Register
- AT91_REG Reserved0[1]; //
- AT91_REG CKGR_PLLR; // PLL Register
-} AT91S_CKGR, *AT91PS_CKGR;
-
-// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
-#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable
-#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass
-#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time
-// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
-#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency
-#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
-// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
-#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected
-#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0
-#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed
-#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter
-#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
-#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
-#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
-#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
-#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
-#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Power Management Controler
-// *****************************************************************************
-typedef struct _AT91S_PMC {
- AT91_REG PMC_SCER; // System Clock Enable Register
- AT91_REG PMC_SCDR; // System Clock Disable Register
- AT91_REG PMC_SCSR; // System Clock Status Register
- AT91_REG Reserved0[1]; //
- AT91_REG PMC_PCER; // Peripheral Clock Enable Register
- AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
- AT91_REG PMC_PCSR; // Peripheral Clock Status Register
- AT91_REG Reserved1[1]; //
- AT91_REG PMC_MOR; // Main Oscillator Register
- AT91_REG PMC_MCFR; // Main Clock Frequency Register
- AT91_REG Reserved2[1]; //
- AT91_REG PMC_PLLR; // PLL Register
- AT91_REG PMC_MCKR; // Master Clock Register
- AT91_REG Reserved3[3]; //
- AT91_REG PMC_PCKR[4]; // Programmable Clock Register
- AT91_REG Reserved4[4]; //
- AT91_REG PMC_IER; // Interrupt Enable Register
- AT91_REG PMC_IDR; // Interrupt Disable Register
- AT91_REG PMC_SR; // Status Register
- AT91_REG PMC_IMR; // Interrupt Mask Register
-} AT91S_PMC, *AT91PS_PMC;
-
-// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
-#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock
-#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock
-#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
-// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
-// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
-// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
-// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
-// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
-// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
-#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection
-#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected
-#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected
-#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
-#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler
-#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock
-#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2
-#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4
-#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8
-#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16
-#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32
-#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64
-// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
-// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
-#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
-#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask
-#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
-// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
-// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
-// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Reset Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_RSTC {
- AT91_REG RSTC_RCR; // Reset Control Register
- AT91_REG RSTC_RSR; // Reset Status Register
- AT91_REG RSTC_RMR; // Reset Mode Register
-} AT91S_RSTC, *AT91PS_RSTC;
-
-// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
-#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset
-#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset
-#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset
-#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password
-// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
-#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status
-#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status
-#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type
-#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.
-#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.
-#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
-#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
-#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
-#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured.
-#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
-#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
-// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
-#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable
-#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable
-#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable
-#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_RTTC {
- AT91_REG RTTC_RTMR; // Real-time Mode Register
- AT91_REG RTTC_RTAR; // Real-time Alarm Register
- AT91_REG RTTC_RTVR; // Real-time Value Register
- AT91_REG RTTC_RTSR; // Real-time Status Register
-} AT91S_RTTC, *AT91PS_RTTC;
-
-// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
-#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
-#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
-#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
-#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
-// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
-#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value
-// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
-#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value
-// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
-#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status
-#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_PITC {
- AT91_REG PITC_PIMR; // Period Interval Mode Register
- AT91_REG PITC_PISR; // Period Interval Status Register
- AT91_REG PITC_PIVR; // Period Interval Value Register
- AT91_REG PITC_PIIR; // Period Interval Image Register
-} AT91S_PITC, *AT91PS_PITC;
-
-// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
-#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value
-#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
-#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
-// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
-#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status
-// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
-#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value
-#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
-// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_WDTC {
- AT91_REG WDTC_WDCR; // Watchdog Control Register
- AT91_REG WDTC_WDMR; // Watchdog Mode Register
- AT91_REG WDTC_WDSR; // Watchdog Status Register
-} AT91S_WDTC, *AT91PS_WDTC;
-
-// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
-#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart
-#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password
-// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
-#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
-#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
-#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
-#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
-#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
-#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
-// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
-#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow
-#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_VREG {
- AT91_REG VREG_MR; // Voltage Regulator Mode Register
-} AT91S_VREG, *AT91PS_VREG;
-
-// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
-#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Memory Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_MC {
- AT91_REG MC_RCR; // MC Remap Control Register
- AT91_REG MC_ASR; // MC Abort Status Register
- AT91_REG MC_AASR; // MC Abort Address Status Register
- AT91_REG Reserved0[21]; //
- AT91_REG MC_FMR; // MC Flash Mode Register
- AT91_REG MC_FCR; // MC Flash Command Register
- AT91_REG MC_FSR; // MC Flash Status Register
-} AT91S_MC, *AT91PS_MC;
-
-// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
-#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit
-// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
-#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status
-#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status
-#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status
-#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte
-#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word
-#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word
-#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
-#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read
-#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write
-#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch
-#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
-#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
-#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
-#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
-// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
-#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready
-#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error
-#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error
-#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming
-#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State
-#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations
-#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations
-#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations
-#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations
-#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
-// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
-#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command
-#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
-#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
-#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
-#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
-#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
-#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit.
-#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number
-#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
-// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
-#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status
-#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status
-#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status
-#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
-#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
-#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
-#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
-#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
-#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
-#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
-#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
-#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
-#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
-#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
-#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
-#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
-#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
-#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
-#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
-#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
-#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
-#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
-#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Serial Parallel Interface
-// *****************************************************************************
-typedef struct _AT91S_SPI {
- AT91_REG SPI_CR; // Control Register
- AT91_REG SPI_MR; // Mode Register
- AT91_REG SPI_RDR; // Receive Data Register
- AT91_REG SPI_TDR; // Transmit Data Register
- AT91_REG SPI_SR; // Status Register
- AT91_REG SPI_IER; // Interrupt Enable Register
- AT91_REG SPI_IDR; // Interrupt Disable Register
- AT91_REG SPI_IMR; // Interrupt Mask Register
- AT91_REG Reserved0[4]; //
- AT91_REG SPI_CSR[4]; // Chip Select Register
- AT91_REG Reserved1[48]; //
- AT91_REG SPI_RPR; // Receive Pointer Register
- AT91_REG SPI_RCR; // Receive Counter Register
- AT91_REG SPI_TPR; // Transmit Pointer Register
- AT91_REG SPI_TCR; // Transmit Counter Register
- AT91_REG SPI_RNPR; // Receive Next Pointer Register
- AT91_REG SPI_RNCR; // Receive Next Counter Register
- AT91_REG SPI_TNPR; // Transmit Next Pointer Register
- AT91_REG SPI_TNCR; // Transmit Next Counter Register
- AT91_REG SPI_PTCR; // PDC Transfer Control Register
- AT91_REG SPI_PTSR; // PDC Transfer Status Register
-} AT91S_SPI, *AT91PS_SPI;
-
-// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
-#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable
-#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable
-#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset
-#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
-// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
-#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode
-#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select
-#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select
-#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select
-#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode
-#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection
-#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection
-#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection
-#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
-#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
-// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
-#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data
-#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
-#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data
-#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
-#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full
-#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty
-#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error
-#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status
-#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt
-#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt
-#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt
-#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt
-#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status
-// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
-// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
-// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
-// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
-#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity
-#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase
-#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer
-#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer
-#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer
-#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer
-#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer
-#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer
-#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer
-#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer
-#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer
-#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer
-#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer
-#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK
-#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Usart
-// *****************************************************************************
-typedef struct _AT91S_USART {
- AT91_REG US_CR; // Control Register
- AT91_REG US_MR; // Mode Register
- AT91_REG US_IER; // Interrupt Enable Register
- AT91_REG US_IDR; // Interrupt Disable Register
- AT91_REG US_IMR; // Interrupt Mask Register
- AT91_REG US_CSR; // Channel Status Register
- AT91_REG US_RHR; // Receiver Holding Register
- AT91_REG US_THR; // Transmitter Holding Register
- AT91_REG US_BRGR; // Baud Rate Generator Register
- AT91_REG US_RTOR; // Receiver Time-out Register
- AT91_REG US_TTGR; // Transmitter Time-guard Register
- AT91_REG Reserved0[5]; //
- AT91_REG US_FIDI; // FI_DI_Ratio Register
- AT91_REG US_NER; // Nb Errors Register
- AT91_REG Reserved1[1]; //
- AT91_REG US_IF; // IRDA_FILTER Register
- AT91_REG Reserved2[44]; //
- AT91_REG US_RPR; // Receive Pointer Register
- AT91_REG US_RCR; // Receive Counter Register
- AT91_REG US_TPR; // Transmit Pointer Register
- AT91_REG US_TCR; // Transmit Counter Register
- AT91_REG US_RNPR; // Receive Next Pointer Register
- AT91_REG US_RNCR; // Receive Next Counter Register
- AT91_REG US_TNPR; // Transmit Next Pointer Register
- AT91_REG US_TNCR; // Transmit Next Counter Register
- AT91_REG US_PTCR; // PDC Transfer Control Register
- AT91_REG US_PTSR; // PDC Transfer Status Register
-} AT91S_USART, *AT91PS_USART;
-
-// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break
-#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break
-#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out
-#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address
-#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
-#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
-#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
-#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
-#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
-#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
-#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
-// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode
-#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal
-#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485
-#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking
-#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem
-#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
-#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
-#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA
-#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking
-#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock
-#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1
-#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM)
-#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK)
-#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits
-#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits
-#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits
-#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits
-#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select
-#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
-#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
-#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
-#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order
-#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
-#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
-#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
-#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
-#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
-#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
-#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
-// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break
-#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out
-#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
-#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
-#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
-#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
-#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
-#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
-// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
-#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
-#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
-#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
-#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_SSC {
- AT91_REG SSC_CR; // Control Register
- AT91_REG SSC_CMR; // Clock Mode Register
- AT91_REG Reserved0[2]; //
- AT91_REG SSC_RCMR; // Receive Clock ModeRegister
- AT91_REG SSC_RFMR; // Receive Frame Mode Register
- AT91_REG SSC_TCMR; // Transmit Clock Mode Register
- AT91_REG SSC_TFMR; // Transmit Frame Mode Register
- AT91_REG SSC_RHR; // Receive Holding Register
- AT91_REG SSC_THR; // Transmit Holding Register
- AT91_REG Reserved1[2]; //
- AT91_REG SSC_RSHR; // Receive Sync Holding Register
- AT91_REG SSC_TSHR; // Transmit Sync Holding Register
- AT91_REG Reserved2[2]; //
- AT91_REG SSC_SR; // Status Register
- AT91_REG SSC_IER; // Interrupt Enable Register
- AT91_REG SSC_IDR; // Interrupt Disable Register
- AT91_REG SSC_IMR; // Interrupt Mask Register
- AT91_REG Reserved3[44]; //
- AT91_REG SSC_RPR; // Receive Pointer Register
- AT91_REG SSC_RCR; // Receive Counter Register
- AT91_REG SSC_TPR; // Transmit Pointer Register
- AT91_REG SSC_TCR; // Transmit Counter Register
- AT91_REG SSC_RNPR; // Receive Next Pointer Register
- AT91_REG SSC_RNCR; // Receive Next Counter Register
- AT91_REG SSC_TNPR; // Transmit Next Pointer Register
- AT91_REG SSC_TNCR; // Transmit Next Counter Register
- AT91_REG SSC_PTCR; // PDC Transfer Control Register
- AT91_REG SSC_PTSR; // PDC Transfer Status Register
-} AT91S_SSC, *AT91PS_SSC;
-
-// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
-#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable
-#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable
-#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable
-#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable
-#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset
-// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
-#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection
-#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock
-#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal
-#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin
-#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
-#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
-#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
-#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection
-#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start
-#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input
-#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input
-#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input
-#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input
-#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input
-#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input
-#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0
-#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
-#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
-// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
-#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length
-#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode
-#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First
-#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame
-#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
-#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
-#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
-// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
-// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
-#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value
-#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
-// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
-#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready
-#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty
-#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission
-#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty
-#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready
-#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun
-#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception
-#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full
-#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
-#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
-#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
-#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
-// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
-// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
-// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Two-wire Interface
-// *****************************************************************************
-typedef struct _AT91S_TWI {
- AT91_REG TWI_CR; // Control Register
- AT91_REG TWI_MMR; // Master Mode Register
- AT91_REG Reserved0[1]; //
- AT91_REG TWI_IADR; // Internal Address Register
- AT91_REG TWI_CWGR; // Clock Waveform Generator Register
- AT91_REG Reserved1[3]; //
- AT91_REG TWI_SR; // Status Register
- AT91_REG TWI_IER; // Interrupt Enable Register
- AT91_REG TWI_IDR; // Interrupt Disable Register
- AT91_REG TWI_IMR; // Interrupt Mask Register
- AT91_REG TWI_RHR; // Receive Holding Register
- AT91_REG TWI_THR; // Transmit Holding Register
-} AT91S_TWI, *AT91PS_TWI;
-
-// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
-#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition
-#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition
-#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled
-#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled
-#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset
-// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
-#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size
-#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address
-#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address
-#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address
-#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address
-#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
-#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address
-// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
-#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider
-#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider
-#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
-// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
-#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed
-#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY
-#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY
-#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error
-#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error
-#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged
-// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
-// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
-// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR PWMC Channel Interface
-// *****************************************************************************
-typedef struct _AT91S_PWMC_CH {
- AT91_REG PWMC_CMR; // Channel Mode Register
- AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register
- AT91_REG PWMC_CPRDR; // Channel Period Register
- AT91_REG PWMC_CCNTR; // Channel Counter Register
- AT91_REG PWMC_CUPDR; // Channel Update Register
- AT91_REG PWMC_Reserved[3]; // Reserved
-} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
-
-// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
-#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
-#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH)
-#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH)
-#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH)
-#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment
-#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity
-#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
-// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
-#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle
-// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
-#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period
-// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
-#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter
-// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
-#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_PWMC {
- AT91_REG PWMC_MR; // PWMC Mode Register
- AT91_REG PWMC_ENA; // PWMC Enable Register
- AT91_REG PWMC_DIS; // PWMC Disable Register
- AT91_REG PWMC_SR; // PWMC Status Register
- AT91_REG PWMC_IER; // PWMC Interrupt Enable Register
- AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register
- AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register
- AT91_REG PWMC_ISR; // PWMC Interrupt Status Register
- AT91_REG Reserved0[55]; //
- AT91_REG PWMC_VR; // PWMC Version Register
- AT91_REG Reserved1[64]; //
- AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel
-} AT91S_PWMC, *AT91PS_PWMC;
-
-// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
-#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor.
-#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A
-#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC)
-#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
-#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
-#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC)
-// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
-#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0
-#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1
-#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2
-#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3
-// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
-// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
-// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
-// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
-// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
-// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR USB Device Interface
-// *****************************************************************************
-typedef struct _AT91S_UDP {
- AT91_REG UDP_NUM; // Frame Number Register
- AT91_REG UDP_GLBSTATE; // Global State Register
- AT91_REG UDP_FADDR; // Function Address Register
- AT91_REG Reserved0[1]; //
- AT91_REG UDP_IER; // Interrupt Enable Register
- AT91_REG UDP_IDR; // Interrupt Disable Register
- AT91_REG UDP_IMR; // Interrupt Mask Register
- AT91_REG UDP_ISR; // Interrupt Status Register
- AT91_REG UDP_ICR; // Interrupt Clear Register
- AT91_REG Reserved1[1]; //
- AT91_REG UDP_RSTEP; // Reset Endpoint Register
- AT91_REG Reserved2[1]; //
- AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register
- AT91_REG Reserved3[2]; //
- AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register
- AT91_REG Reserved4[3]; //
- AT91_REG UDP_TXVC; // Transceiver Control Register
-} AT91S_UDP, *AT91PS_UDP;
-
-// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
-#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
-#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error
-#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK
-// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
-#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable
-#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured
-#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume
-#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
-#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable
-// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
-#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value
-#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable
-// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
-#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt
-#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt
-#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt
-#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt
-#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt
-#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt
-#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
-#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
-#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
-// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
-// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
-// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
-#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
-// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
-// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
-#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0
-#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1
-#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2
-#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3
-#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4
-#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5
-// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
-#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
-#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0
-#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
-#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
-#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready
-#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction
-#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type
-#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control
-#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT
-#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT
-#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT
-#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN
-#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN
-#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN
-#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
-#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
-#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
-// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
-#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP)
-#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
-// *****************************************************************************
-typedef struct _AT91S_TC {
- AT91_REG TC_CCR; // Channel Control Register
- AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)
- AT91_REG Reserved0[2]; //
- AT91_REG TC_CV; // Counter Value
- AT91_REG TC_RA; // Register A
- AT91_REG TC_RB; // Register B
- AT91_REG TC_RC; // Register C
- AT91_REG TC_SR; // Status Register
- AT91_REG TC_IER; // Interrupt Enable Register
- AT91_REG TC_IDR; // Interrupt Disable Register
- AT91_REG TC_IMR; // Interrupt Mask Register
-} AT91S_TC, *AT91PS_TC;
-
-// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
-#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command
-#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command
-#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command
-// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
-#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection
-#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
-#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
-#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
-#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
-#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
-#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0
-#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1
-#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2
-#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert
-#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection
-#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal
-#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock
-#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock
-#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock
-#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
-#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
-#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare
-#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
-#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection
-#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
-#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
-#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
-#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
-#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection
-#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
-#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
-#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
-#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
-#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection
-#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
-#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
-#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
-#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
-#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
-#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
-#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection
-#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
-#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
-#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
-#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
-#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
-#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC)
-#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
-#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none
-#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set
-#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear
-#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
-#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
-#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None
-#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
-#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
-#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
-#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none
-#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set
-#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear
-#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
-#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
-#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None
-#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
-#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
-#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
-#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none
-#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set
-#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear
-#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
-#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
-#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none
-#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set
-#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear
-#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
-#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
-#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none
-#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set
-#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear
-#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
-#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
-#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none
-#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set
-#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear
-#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
-#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
-#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none
-#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set
-#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear
-#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
-#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
-#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none
-#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set
-#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear
-#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
-// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
-#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow
-#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun
-#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare
-#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare
-#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare
-#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading
-#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading
-#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger
-#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
-#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
-#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
-// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
-// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
-// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Timer Counter Interface
-// *****************************************************************************
-typedef struct _AT91S_TCB {
- AT91S_TC TCB_TC0; // TC Channel 0
- AT91_REG Reserved0[4]; //
- AT91S_TC TCB_TC1; // TC Channel 1
- AT91_REG Reserved1[4]; //
- AT91S_TC TCB_TC2; // TC Channel 2
- AT91_REG Reserved2[4]; //
- AT91_REG TCB_BCR; // TC Block Control Register
- AT91_REG TCB_BMR; // TC Block Mode Register
-} AT91S_TCB, *AT91PS_TCB;
-
-// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
-#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command
-// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
-#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection
-#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
-#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0
-#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
-#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
-#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection
-#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1
-#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1
-#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1
-#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1
-#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection
-#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2
-#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2
-#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2
-#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface
-// *****************************************************************************
-typedef struct _AT91S_CAN_MB {
- AT91_REG CAN_MB_MMR; // MailBox Mode Register
- AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register
- AT91_REG CAN_MB_MID; // MailBox ID Register
- AT91_REG CAN_MB_MFID; // MailBox Family ID Register
- AT91_REG CAN_MB_MSR; // MailBox Status Register
- AT91_REG CAN_MB_MDL; // MailBox Data Low Register
- AT91_REG CAN_MB_MDH; // MailBox Data High Register
- AT91_REG CAN_MB_MCR; // MailBox Control Register
-} AT91S_CAN_MB, *AT91PS_CAN_MB;
-
-// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register --------
-#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark
-#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority
-#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type
-#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB)
-#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB)
-#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB)
-#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB)
-#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB)
-#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB)
-// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register --------
-#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode
-#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
-#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version
-// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register --------
-// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register --------
-// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register --------
-#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value
-#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code
-#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
-#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort
-#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready
-#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored
-// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register --------
-// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register --------
-// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register --------
-#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox
-#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Control Area Network Interface
-// *****************************************************************************
-typedef struct _AT91S_CAN {
- AT91_REG CAN_MR; // Mode Register
- AT91_REG CAN_IER; // Interrupt Enable Register
- AT91_REG CAN_IDR; // Interrupt Disable Register
- AT91_REG CAN_IMR; // Interrupt Mask Register
- AT91_REG CAN_SR; // Status Register
- AT91_REG CAN_BR; // Baudrate Register
- AT91_REG CAN_TIM; // Timer Register
- AT91_REG CAN_TIMESTP; // Time Stamp Register
- AT91_REG CAN_ECR; // Error Counter Register
- AT91_REG CAN_TCR; // Transfer Command Register
- AT91_REG CAN_ACR; // Abort Command Register
- AT91_REG Reserved0[52]; //
- AT91_REG CAN_VR; // Version Register
- AT91_REG Reserved1[64]; //
- AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0
- AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1
- AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2
- AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3
- AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4
- AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5
- AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6
- AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7
- AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8
- AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9
- AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10
- AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11
- AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12
- AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13
- AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14
- AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15
-} AT91S_CAN, *AT91PS_CAN;
-
-// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register --------
-#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable
-#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode
-#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode
-#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame
-#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame
-#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode
-#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze
-#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat
-// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register --------
-#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag
-#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag
-#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag
-#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag
-#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag
-#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag
-#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag
-#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag
-#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag
-#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag
-#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag
-#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag
-#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag
-#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag
-#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag
-#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag
-#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag
-#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag
-#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag
-#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag
-#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag
-#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag
-#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag
-#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag
-#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error
-#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error
-#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error
-#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error
-#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error
-// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register --------
-// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register --------
-// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register --------
-#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy
-#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy
-#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy
-// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register --------
-#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment
-#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment
-#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment
-#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment
-#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler
-#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode
-// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register --------
-#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field
-// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register --------
-// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register --------
-#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter
-#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter
-// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register --------
-#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field
-// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100
-// *****************************************************************************
-typedef struct _AT91S_EMAC {
- AT91_REG EMAC_NCR; // Network Control Register
- AT91_REG EMAC_NCFGR; // Network Configuration Register
- AT91_REG EMAC_NSR; // Network Status Register
- AT91_REG Reserved0[2]; //
- AT91_REG EMAC_TSR; // Transmit Status Register
- AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer
- AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer
- AT91_REG EMAC_RSR; // Receive Status Register
- AT91_REG EMAC_ISR; // Interrupt Status Register
- AT91_REG EMAC_IER; // Interrupt Enable Register
- AT91_REG EMAC_IDR; // Interrupt Disable Register
- AT91_REG EMAC_IMR; // Interrupt Mask Register
- AT91_REG EMAC_MAN; // PHY Maintenance Register
- AT91_REG EMAC_PTR; // Pause Time Register
- AT91_REG EMAC_PFR; // Pause Frames received Register
- AT91_REG EMAC_FTO; // Frames Transmitted OK Register
- AT91_REG EMAC_SCF; // Single Collision Frame Register
- AT91_REG EMAC_MCF; // Multiple Collision Frame Register
- AT91_REG EMAC_FRO; // Frames Received OK Register
- AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register
- AT91_REG EMAC_ALE; // Alignment Error Register
- AT91_REG EMAC_DTF; // Deferred Transmission Frame Register
- AT91_REG EMAC_LCOL; // Late Collision Register
- AT91_REG EMAC_ECOL; // Excessive Collision Register
- AT91_REG EMAC_TUND; // Transmit Underrun Error Register
- AT91_REG EMAC_CSE; // Carrier Sense Error Register
- AT91_REG EMAC_RRE; // Receive Ressource Error Register
- AT91_REG EMAC_ROV; // Receive Overrun Errors Register
- AT91_REG EMAC_RSE; // Receive Symbol Errors Register
- AT91_REG EMAC_ELE; // Excessive Length Errors Register
- AT91_REG EMAC_RJA; // Receive Jabbers Register
- AT91_REG EMAC_USF; // Undersize Frames Register
- AT91_REG EMAC_STE; // SQE Test Error Register
- AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register
- AT91_REG EMAC_TPF; // Transmitted Pause Frames Register
- AT91_REG EMAC_HRB; // Hash Address Bottom[31:0]
- AT91_REG EMAC_HRT; // Hash Address Top[63:32]
- AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes
- AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes
- AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes
- AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes
- AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes
- AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes
- AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes
- AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes
- AT91_REG EMAC_TID; // Type ID Checking Register
- AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register
- AT91_REG EMAC_USRIO; // USER Input/Output Register
- AT91_REG EMAC_WOL; // Wake On LAN Register
- AT91_REG Reserved1[13]; //
- AT91_REG EMAC_REV; // Revision Register
-} AT91S_EMAC, *AT91PS_EMAC;
-
-// -------- EMAC_NCR : (EMAC Offset: 0x0) --------
-#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
-#define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local.
-#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable.
-#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable.
-#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable.
-#define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers.
-#define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers.
-#define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers.
-#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure.
-#define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission.
-#define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt.
-#define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame
-#define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame
-// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register --------
-#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed.
-#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex.
-#define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames.
-#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames.
-#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast.
-#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable
-#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable.
-#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes.
-#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable.
-#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC)
-#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8
-#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16
-#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32
-#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64
-#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC)
-#define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC)
-#define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC)
-#define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer
-#define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer
-#define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
-#define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
-#define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable
-#define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS
-#define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC)
-#define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS
-// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register --------
-#define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC)
-#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC)
-#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC)
-// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register --------
-#define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC)
-#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC)
-#define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC)
-#define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go
-#define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame
-#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC)
-#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC)
-// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
-#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC)
-#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC)
-#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC)
-// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
-#define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC)
-#define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC)
-#define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC)
-#define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC)
-#define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC)
-#define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC)
-#define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC)
-#define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC)
-#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC)
-#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC)
-#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC)
-#define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC)
-#define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC)
-// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
-// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
-// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
-// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
-#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC)
-#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC)
-#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC)
-#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC)
-#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC)
-#define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC)
-// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register --------
-#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII
-// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register --------
-#define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address
-#define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable
-#define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable
-#define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable
-// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register --------
-#define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC)
-#define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC)
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Analog to Digital Convertor
-// *****************************************************************************
-typedef struct _AT91S_ADC {
- AT91_REG ADC_CR; // ADC Control Register
- AT91_REG ADC_MR; // ADC Mode Register
- AT91_REG Reserved0[2]; //
- AT91_REG ADC_CHER; // ADC Channel Enable Register
- AT91_REG ADC_CHDR; // ADC Channel Disable Register
- AT91_REG ADC_CHSR; // ADC Channel Status Register
- AT91_REG ADC_SR; // ADC Status Register
- AT91_REG ADC_LCDR; // ADC Last Converted Data Register
- AT91_REG ADC_IER; // ADC Interrupt Enable Register
- AT91_REG ADC_IDR; // ADC Interrupt Disable Register
- AT91_REG ADC_IMR; // ADC Interrupt Mask Register
- AT91_REG ADC_CDR0; // ADC Channel Data Register 0
- AT91_REG ADC_CDR1; // ADC Channel Data Register 1
- AT91_REG ADC_CDR2; // ADC Channel Data Register 2
- AT91_REG ADC_CDR3; // ADC Channel Data Register 3
- AT91_REG ADC_CDR4; // ADC Channel Data Register 4
- AT91_REG ADC_CDR5; // ADC Channel Data Register 5
- AT91_REG ADC_CDR6; // ADC Channel Data Register 6
- AT91_REG ADC_CDR7; // ADC Channel Data Register 7
- AT91_REG Reserved1[44]; //
- AT91_REG ADC_RPR; // Receive Pointer Register
- AT91_REG ADC_RCR; // Receive Counter Register
- AT91_REG ADC_TPR; // Transmit Pointer Register
- AT91_REG ADC_TCR; // Transmit Counter Register
- AT91_REG ADC_RNPR; // Receive Next Pointer Register
- AT91_REG ADC_RNCR; // Receive Next Counter Register
- AT91_REG ADC_TNPR; // Transmit Next Pointer Register
- AT91_REG ADC_TNCR; // Transmit Next Counter Register
- AT91_REG ADC_PTCR; // PDC Transfer Control Register
- AT91_REG ADC_PTSR; // PDC Transfer Status Register
-} AT91S_ADC, *AT91PS_ADC;
-
-// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
-#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset
-#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion
-// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
-#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable
-#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
-#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
-#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection
-#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
-#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
-#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
-#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
-#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
-#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
-#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
-#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution.
-#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution
-#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution
-#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
-#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode
-#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
-#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection
-#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time
-#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
-// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
-#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0
-#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1
-#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2
-#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3
-#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4
-#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5
-#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6
-#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7
-// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
-// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
-// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
-#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion
-#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion
-#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion
-#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion
-#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion
-#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion
-#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion
-#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion
-#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
-#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready
-#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun
-#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
-#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
-// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
-#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted
-// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
-// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
-// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
-// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
-#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data
-// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
-// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
-// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
-// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
-// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
-// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
-// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Advanced Encryption Standard
-// *****************************************************************************
-typedef struct _AT91S_AES {
- AT91_REG AES_CR; // Control Register
- AT91_REG AES_MR; // Mode Register
- AT91_REG Reserved0[2]; //
- AT91_REG AES_IER; // Interrupt Enable Register
- AT91_REG AES_IDR; // Interrupt Disable Register
- AT91_REG AES_IMR; // Interrupt Mask Register
- AT91_REG AES_ISR; // Interrupt Status Register
- AT91_REG AES_KEYWxR[4]; // Key Word x Register
- AT91_REG Reserved1[4]; //
- AT91_REG AES_IDATAxR[4]; // Input Data x Register
- AT91_REG AES_ODATAxR[4]; // Output Data x Register
- AT91_REG AES_IVxR[4]; // Initialization Vector x Register
- AT91_REG Reserved2[35]; //
- AT91_REG AES_VR; // AES Version Register
- AT91_REG AES_RPR; // Receive Pointer Register
- AT91_REG AES_RCR; // Receive Counter Register
- AT91_REG AES_TPR; // Transmit Pointer Register
- AT91_REG AES_TCR; // Transmit Counter Register
- AT91_REG AES_RNPR; // Receive Next Pointer Register
- AT91_REG AES_RNCR; // Receive Next Counter Register
- AT91_REG AES_TNPR; // Transmit Next Pointer Register
- AT91_REG AES_TNCR; // Transmit Next Counter Register
- AT91_REG AES_PTCR; // PDC Transfer Control Register
- AT91_REG AES_PTSR; // PDC Transfer Status Register
-} AT91S_AES, *AT91PS_AES;
-
-// -------- AES_CR : (AES Offset: 0x0) Control Register --------
-#define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing
-#define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset
-#define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading
-// -------- AES_MR : (AES Offset: 0x4) Mode Register --------
-#define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode
-#define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay
-#define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode
-#define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
-#define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
-#define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet).
-#define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode
-#define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode.
-#define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
-#define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode.
-#define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode.
-#define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode.
-#define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode
-#define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size
-#define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit.
-#define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit.
-#define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit.
-#define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit.
-#define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit.
-#define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key
-#define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type
-#define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled.
-#define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled.
-#define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled.
-#define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled.
-#define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled.
-// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register --------
-#define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY
-#define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End
-#define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End
-#define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full
-#define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty
-#define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection
-// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register --------
-// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register --------
-// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register --------
-#define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status
-#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
-#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing.
-#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing.
-#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation.
-#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation.
-#define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access.
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard
-// *****************************************************************************
-typedef struct _AT91S_TDES {
- AT91_REG TDES_CR; // Control Register
- AT91_REG TDES_MR; // Mode Register
- AT91_REG Reserved0[2]; //
- AT91_REG TDES_IER; // Interrupt Enable Register
- AT91_REG TDES_IDR; // Interrupt Disable Register
- AT91_REG TDES_IMR; // Interrupt Mask Register
- AT91_REG TDES_ISR; // Interrupt Status Register
- AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register
- AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register
- AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register
- AT91_REG Reserved1[2]; //
- AT91_REG TDES_IDATAxR[2]; // Input Data x Register
- AT91_REG Reserved2[2]; //
- AT91_REG TDES_ODATAxR[2]; // Output Data x Register
- AT91_REG Reserved3[2]; //
- AT91_REG TDES_IVxR[2]; // Initialization Vector x Register
- AT91_REG Reserved4[37]; //
- AT91_REG TDES_VR; // TDES Version Register
- AT91_REG TDES_RPR; // Receive Pointer Register
- AT91_REG TDES_RCR; // Receive Counter Register
- AT91_REG TDES_TPR; // Transmit Pointer Register
- AT91_REG TDES_TCR; // Transmit Counter Register
- AT91_REG TDES_RNPR; // Receive Next Pointer Register
- AT91_REG TDES_RNCR; // Receive Next Counter Register
- AT91_REG TDES_TNPR; // Transmit Next Pointer Register
- AT91_REG TDES_TNCR; // Transmit Next Counter Register
- AT91_REG TDES_PTCR; // PDC Transfer Control Register
- AT91_REG TDES_PTSR; // PDC Transfer Status Register
-} AT91S_TDES, *AT91PS_TDES;
-
-// -------- TDES_CR : (TDES Offset: 0x0) Control Register --------
-#define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing
-#define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset
-// -------- TDES_MR : (TDES Offset: 0x4) Mode Register --------
-#define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode
-#define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode
-#define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode
-#define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode
-#define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
-#define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
-#define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet).
-#define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode
-#define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
-#define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
-#define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode.
-#define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode.
-#define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode
-#define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size
-#define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit.
-#define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit.
-#define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit.
-#define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit.
-// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register --------
-#define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY
-#define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End
-#define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End
-#define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full
-#define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty
-#define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection
-// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register --------
-// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register --------
-// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register --------
-#define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status
-#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
-#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing.
-#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing.
-#define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access.
-
-// *****************************************************************************
-// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
-// *****************************************************************************
-// ========== Register definition for SYS peripheral ==========
-// ========== Register definition for AIC peripheral ==========
-#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register
-#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register
-#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register
-#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)
-#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register
-#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register
-#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register
-#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register
-#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register
-#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register
-#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register
-#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register
-#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register
-#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register
-#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register
-#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register
-#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register
-#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register
-// ========== Register definition for PDC_DBGU peripheral ==========
-#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
-#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
-#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
-#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
-#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
-#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register
-#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
-#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
-#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
-#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
-// ========== Register definition for DBGU peripheral ==========
-#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register
-#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register
-#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register
-#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register
-#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register
-#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register
-#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register
-#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register
-#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register
-#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register
-#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register
-#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register
-// ========== Register definition for PIOA peripheral ==========
-#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr
-#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register
-#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register
-#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register
-#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register
-#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register
-#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register
-#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register
-#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register
-#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register
-#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register
-#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register
-#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register
-#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register
-#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register
-#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register
-#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register
-#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register
-#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register
-#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register
-#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register
-#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register
-#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register
-#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register
-#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register
-#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register
-#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register
-#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register
-#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register
-// ========== Register definition for PIOB peripheral ==========
-#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register
-#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register
-#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register
-#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register
-#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register
-#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register
-#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register
-#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register
-#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register
-#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register
-#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register
-#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register
-#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register
-#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register
-#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register
-#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register
-#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr
-#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register
-#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register
-#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register
-#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register
-#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register
-#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register
-#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register
-#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register
-#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register
-#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register
-#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register
-#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register
-// ========== Register definition for CKGR peripheral ==========
-#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register
-#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register
-#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register
-// ========== Register definition for PMC peripheral ==========
-#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register
-#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
-#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register
-#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
-#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register
-#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
-#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register
-#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
-#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register
-#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register
-#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register
-#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register
-#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register
-#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register
-#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register
-// ========== Register definition for RSTC peripheral ==========
-#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register
-#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register
-#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register
-// ========== Register definition for RTTC peripheral ==========
-#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register
-#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register
-#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register
-#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register
-// ========== Register definition for PITC peripheral ==========
-#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register
-#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register
-#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register
-#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register
-// ========== Register definition for WDTC peripheral ==========
-#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register
-#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register
-#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register
-// ========== Register definition for VREG peripheral ==========
-#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
-// ========== Register definition for MC peripheral ==========
-#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register
-#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register
-#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register
-#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register
-#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register
-#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register
-// ========== Register definition for PDC_SPI1 peripheral ==========
-#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
-#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
-#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
-#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
-#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
-#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
-#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register
-#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
-#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
-#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
-// ========== Register definition for SPI1 peripheral ==========
-#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register
-#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register
-#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register
-#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register
-#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register
-#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register
-#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register
-#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register
-#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register
-// ========== Register definition for PDC_SPI0 peripheral ==========
-#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
-#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
-#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
-#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register
-#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
-#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
-#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
-#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
-#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
-#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
-// ========== Register definition for SPI0 peripheral ==========
-#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register
-#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register
-#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register
-#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register
-#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register
-#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register
-#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register
-#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register
-#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register
-// ========== Register definition for PDC_US1 peripheral ==========
-#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register
-#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
-#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register
-#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
-#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
-#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register
-#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
-#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register
-#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
-#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register
-// ========== Register definition for US1 peripheral ==========
-#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register
-#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register
-#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register
-#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register
-#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register
-#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register
-#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register
-#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register
-#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register
-#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register
-#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register
-#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register
-#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register
-#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register
-// ========== Register definition for PDC_US0 peripheral ==========
-#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
-#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
-#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register
-#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
-#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
-#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
-#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register
-#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register
-#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register
-#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register
-// ========== Register definition for US0 peripheral ==========
-#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register
-#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register
-#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register
-#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register
-#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register
-#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register
-#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register
-#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register
-#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register
-#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register
-#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register
-#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register
-#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register
-#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register
-// ========== Register definition for PDC_SSC peripheral ==========
-#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
-#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register
-#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
-#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
-#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
-#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register
-#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register
-#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
-#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
-#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
-// ========== Register definition for SSC peripheral ==========
-#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register
-#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register
-#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register
-#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register
-#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register
-#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister
-#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register
-#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register
-#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register
-#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register
-#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register
-#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register
-#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register
-#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register
-// ========== Register definition for TWI peripheral ==========
-#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register
-#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register
-#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register
-#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register
-#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register
-#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register
-#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register
-#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register
-#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register
-#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register
-// ========== Register definition for PWMC_CH3 peripheral ==========
-#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register
-#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved
-#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register
-#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
-#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
-#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register
-// ========== Register definition for PWMC_CH2 peripheral ==========
-#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved
-#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register
-#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
-#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register
-#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register
-#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH1 peripheral ==========
-#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved
-#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register
-#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register
-#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
-#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
-#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register
-// ========== Register definition for PWMC_CH0 peripheral ==========
-#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved
-#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register
-#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
-#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register
-#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register
-#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
-// ========== Register definition for PWMC peripheral ==========
-#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
-#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register
-#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
-#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register
-#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
-#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register
-#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
-#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register
-#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register
-// ========== Register definition for UDP peripheral ==========
-#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register
-#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register
-#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register
-#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register
-#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register
-#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register
-#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register
-#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register
-#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register
-#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register
-#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register
-#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register
-// ========== Register definition for TC0 peripheral ==========
-#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register
-#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C
-#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B
-#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register
-#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register
-#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A
-#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register
-#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value
-#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register
-// ========== Register definition for TC1 peripheral ==========
-#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B
-#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register
-#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register
-#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register
-#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register
-#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A
-#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C
-#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register
-#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value
-// ========== Register definition for TC2 peripheral ==========
-#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register
-#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value
-#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A
-#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B
-#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register
-#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register
-#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C
-#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register
-#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
-// ========== Register definition for TCB peripheral ==========
-#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register
-#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register
-// ========== Register definition for CAN_MB0 peripheral ==========
-#define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
-#define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register
-#define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register
-#define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register
-#define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
-#define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register
-#define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register
-// ========== Register definition for CAN_MB1 peripheral ==========
-#define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
-#define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register
-#define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register
-#define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register
-#define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register
-#define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register
-#define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
-// ========== Register definition for CAN_MB2 peripheral ==========
-#define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register
-#define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register
-#define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register
-#define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
-#define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register
-#define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
-#define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register
-// ========== Register definition for CAN_MB3 peripheral ==========
-#define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
-#define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register
-#define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register
-#define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register
-#define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register
-#define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
-#define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register
-// ========== Register definition for CAN_MB4 peripheral ==========
-#define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register
-#define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register
-#define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register
-#define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
-#define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register
-#define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register
-#define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
-#define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
-// ========== Register definition for CAN_MB5 peripheral ==========
-#define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register
-#define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register
-#define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
-#define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
-#define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register
-#define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
-#define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
-#define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
-// ========== Register definition for CAN_MB6 peripheral ==========
-#define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
-#define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register
-#define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register
-#define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
-#define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register
-#define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
-#define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
-// ========== Register definition for CAN_MB7 peripheral ==========
-#define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register
-#define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
-#define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
-#define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
-#define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register
-#define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
-#define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register
-// ========== Register definition for CAN peripheral ==========
-#define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register
-#define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register
-#define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register
-#define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register
-#define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register
-#define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register
-#define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register
-#define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register
-#define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register
-#define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register
-#define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register
-#define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register
-// ========== Register definition for EMAC peripheral ==========
-#define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register
-#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
-#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
-#define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register
-#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register
-#define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
-#define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register
-#define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
-#define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register
-#define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register
-#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
-#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register
-#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
-#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register
-#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register
-#define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register
-#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register
-#define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register
-#define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
-#define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
-#define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register
-#define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register
-#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
-#define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register
-#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register
-#define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register
-#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
-#define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
-#define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register
-#define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32]
-#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register
-#define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
-#define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
-#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register
-#define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register
-#define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register
-#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register
-#define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register
-#define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register
-#define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register
-#define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register
-#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
-#define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register
-#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register
-#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
-#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register
-#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
-#define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register
-#define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register
-// ========== Register definition for PDC_ADC peripheral ==========
-#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
-#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
-#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
-#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
-#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
-#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
-#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register
-#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register
-#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
-#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register
-// ========== Register definition for ADC peripheral ==========
-#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2
-#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3
-#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0
-#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5
-#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register
-#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register
-#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4
-#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1
-#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register
-#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register
-#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register
-#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7
-#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6
-#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register
-#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register
-#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register
-#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register
-#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register
-// ========== Register definition for PDC_AES peripheral ==========
-#define AT91C_AES_TPR ((AT91_REG *) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register
-#define AT91C_AES_PTCR ((AT91_REG *) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
-#define AT91C_AES_RNPR ((AT91_REG *) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
-#define AT91C_AES_TNCR ((AT91_REG *) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
-#define AT91C_AES_TCR ((AT91_REG *) 0xFFFA410C) // (PDC_AES) Transmit Counter Register
-#define AT91C_AES_RCR ((AT91_REG *) 0xFFFA4104) // (PDC_AES) Receive Counter Register
-#define AT91C_AES_RNCR ((AT91_REG *) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register
-#define AT91C_AES_TNPR ((AT91_REG *) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
-#define AT91C_AES_RPR ((AT91_REG *) 0xFFFA4100) // (PDC_AES) Receive Pointer Register
-#define AT91C_AES_PTSR ((AT91_REG *) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
-// ========== Register definition for AES peripheral ==========
-#define AT91C_AES_IVxR ((AT91_REG *) 0xFFFA4060) // (AES) Initialization Vector x Register
-#define AT91C_AES_MR ((AT91_REG *) 0xFFFA4004) // (AES) Mode Register
-#define AT91C_AES_VR ((AT91_REG *) 0xFFFA40FC) // (AES) AES Version Register
-#define AT91C_AES_ODATAxR ((AT91_REG *) 0xFFFA4050) // (AES) Output Data x Register
-#define AT91C_AES_IDATAxR ((AT91_REG *) 0xFFFA4040) // (AES) Input Data x Register
-#define AT91C_AES_CR ((AT91_REG *) 0xFFFA4000) // (AES) Control Register
-#define AT91C_AES_IDR ((AT91_REG *) 0xFFFA4014) // (AES) Interrupt Disable Register
-#define AT91C_AES_IMR ((AT91_REG *) 0xFFFA4018) // (AES) Interrupt Mask Register
-#define AT91C_AES_IER ((AT91_REG *) 0xFFFA4010) // (AES) Interrupt Enable Register
-#define AT91C_AES_KEYWxR ((AT91_REG *) 0xFFFA4020) // (AES) Key Word x Register
-#define AT91C_AES_ISR ((AT91_REG *) 0xFFFA401C) // (AES) Interrupt Status Register
-// ========== Register definition for PDC_TDES peripheral ==========
-#define AT91C_TDES_RNCR ((AT91_REG *) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
-#define AT91C_TDES_TCR ((AT91_REG *) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register
-#define AT91C_TDES_RCR ((AT91_REG *) 0xFFFA8104) // (PDC_TDES) Receive Counter Register
-#define AT91C_TDES_TNPR ((AT91_REG *) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
-#define AT91C_TDES_RNPR ((AT91_REG *) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
-#define AT91C_TDES_RPR ((AT91_REG *) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register
-#define AT91C_TDES_TNCR ((AT91_REG *) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
-#define AT91C_TDES_TPR ((AT91_REG *) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
-#define AT91C_TDES_PTSR ((AT91_REG *) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
-#define AT91C_TDES_PTCR ((AT91_REG *) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
-// ========== Register definition for TDES peripheral ==========
-#define AT91C_TDES_KEY2WxR ((AT91_REG *) 0xFFFA8028) // (TDES) Key 2 Word x Register
-#define AT91C_TDES_KEY3WxR ((AT91_REG *) 0xFFFA8030) // (TDES) Key 3 Word x Register
-#define AT91C_TDES_IDR ((AT91_REG *) 0xFFFA8014) // (TDES) Interrupt Disable Register
-#define AT91C_TDES_VR ((AT91_REG *) 0xFFFA80FC) // (TDES) TDES Version Register
-#define AT91C_TDES_IVxR ((AT91_REG *) 0xFFFA8060) // (TDES) Initialization Vector x Register
-#define AT91C_TDES_ODATAxR ((AT91_REG *) 0xFFFA8050) // (TDES) Output Data x Register
-#define AT91C_TDES_IMR ((AT91_REG *) 0xFFFA8018) // (TDES) Interrupt Mask Register
-#define AT91C_TDES_MR ((AT91_REG *) 0xFFFA8004) // (TDES) Mode Register
-#define AT91C_TDES_CR ((AT91_REG *) 0xFFFA8000) // (TDES) Control Register
-#define AT91C_TDES_IER ((AT91_REG *) 0xFFFA8010) // (TDES) Interrupt Enable Register
-#define AT91C_TDES_ISR ((AT91_REG *) 0xFFFA801C) // (TDES) Interrupt Status Register
-#define AT91C_TDES_IDATAxR ((AT91_REG *) 0xFFFA8040) // (TDES) Input Data x Register
-#define AT91C_TDES_KEY1WxR ((AT91_REG *) 0xFFFA8020) // (TDES) Key 1 Word x Register
-
-// *****************************************************************************
-// PIO DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0
-#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data
-#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1
-#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data
-#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10
-#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data
-#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11
-#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock
-#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12
-#define AT91C_PA12_NPCS00 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0
-#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13
-#define AT91C_PA13_NPCS01 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1
-#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1
-#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14
-#define AT91C_PA14_NPCS02 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2
-#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1
-#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15
-#define AT91C_PA15_NPCS03 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3
-#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input
-#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16
-#define AT91C_PA16_MISO0 ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave
-#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17
-#define AT91C_PA17_MOSI0 ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave
-#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18
-#define AT91C_PA18_SPCK0 ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock
-#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19
-#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive
-#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2
-#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock
-#define AT91C_PA2_NPCS11 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20
-#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit
-#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21
-#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync
-#define AT91C_PA21_NPCS10 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0
-#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22
-#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock
-#define AT91C_PA22_SPCK1 ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock
-#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23
-#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data
-#define AT91C_PA23_MOSI1 ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave
-#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24
-#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data
-#define AT91C_PA24_MISO1 ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave
-#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25
-#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock
-#define AT91C_PA25_NPCS11 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26
-#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync
-#define AT91C_PA26_NPCS12 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27
-#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data
-#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3
-#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28
-#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data
-#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29
-#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input
-#define AT91C_PA29_NPCS13 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3
-#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send
-#define AT91C_PA3_NPCS12 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30
-#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0
-#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2
-#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4
-#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send
-#define AT91C_PA4_NPCS13 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5
-#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data
-#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6
-#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data
-#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7
-#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock
-#define AT91C_PA7_NPCS01 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8
-#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send
-#define AT91C_PA8_NPCS02 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9
-#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send
-#define AT91C_PA9_NPCS03 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0
-#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock
-#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0
-#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1
-#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable
-#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10
-#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2
-#define AT91C_PB10_NPCS11 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11
-#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3
-#define AT91C_PB11_NPCS12 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12
-#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error
-#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input
-#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13
-#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2
-#define AT91C_PB13_NPCS01 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14
-#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3
-#define AT91C_PB14_NPCS02 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15
-#define AT91C_PB15_ERXDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid
-#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16
-#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected
-#define AT91C_PB16_NPCS13 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17
-#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock
-#define AT91C_PB17_NPCS03 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18
-#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec
-#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger
-#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19
-#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0
-#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input
-#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2
-#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0
-#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20
-#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1
-#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0
-#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21
-#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2
-#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1
-#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22
-#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3
-#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2
-#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23
-#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A
-#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect
-#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24
-#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B
-#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready
-#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25
-#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A
-#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready
-#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26
-#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B
-#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator
-#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27
-#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A
-#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0
-#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28
-#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B
-#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1
-#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29
-#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1
-#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2
-#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3
-#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1
-#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30
-#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2
-#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3
-#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4
-#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
-#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5
-#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0
-#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6
-#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1
-#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7
-#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error
-#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8
-#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock
-#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9
-#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output
-
-// *****************************************************************************
-// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ)
-#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral
-#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A
-#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B
-#define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0
-#define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1
-#define AT91C_ID_US0 ((unsigned int) 6) // USART 0
-#define AT91C_ID_US1 ((unsigned int) 7) // USART 1
-#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller
-#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface
-#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller
-#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port
-#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0
-#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1
-#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2
-#define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller
-#define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC
-#define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter
-#define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit
-#define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard
-#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
-#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
-#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
-#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
-#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
-#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
-#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
-#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
-#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
-#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
-#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
-#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
-
-// *****************************************************************************
-// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address
-#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address
-#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address
-#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address
-#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address
-#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address
-#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address
-#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address
-#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address
-#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address
-#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address
-#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address
-#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address
-#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address
-#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address
-#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address
-#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address
-#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address
-#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address
-#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address
-#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address
-#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address
-#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address
-#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address
-#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address
-#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address
-#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address
-#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address
-#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address
-#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address
-#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address
-#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address
-#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address
-#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address
-#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address
-#define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address
-#define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address
-#define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address
-#define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address
-#define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address
-#define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address
-#define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address
-#define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address
-#define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address
-#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address
-#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address
-#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address
-#define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address
-#define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address
-#define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address
-#define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address
-
-// *****************************************************************************
-// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address
-#define AT91C_ISRAM_SIZE ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte)
-#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address
-#define AT91C_IFLASH_SIZE ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte)
-
-
-
-// - Hardware register definition
-
-// - *****************************************************************************
-// - SOFTWARE API DEFINITION FOR System Peripherals
-// - *****************************************************************************
-
-// - *****************************************************************************
-// - SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
-// - *****************************************************************************
-// - -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
-#if 0 /*_RB_*/
-AT91C_AIC_PRIOR EQU (0x7 << 0) ;- (AIC) Priority Level
-AT91C_AIC_PRIOR_LOWEST EQU (0x0) ;- (AIC) Lowest priority level
-AT91C_AIC_PRIOR_HIGHEST EQU (0x7) ;- (AIC) Highest priority level
-AT91C_AIC_SRCTYPE EQU (0x3 << 5) ;- (AIC) Interrupt Source Type
-AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL EQU (0x0 << 5) ;- (AIC) Internal Sources Code Label High-level Sensitive
-AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL EQU (0x0 << 5) ;- (AIC) External Sources Code Label Low-level Sensitive
-AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE EQU (0x1 << 5) ;- (AIC) Internal Sources Code Label Positive Edge triggered
-AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE EQU (0x1 << 5) ;- (AIC) External Sources Code Label Negative Edge triggered
-AT91C_AIC_SRCTYPE_HIGH_LEVEL EQU (0x2 << 5) ;- (AIC) Internal Or External Sources Code Label High-level Sensitive
-AT91C_AIC_SRCTYPE_POSITIVE_EDGE EQU (0x3 << 5) ;- (AIC) Internal Or External Sources Code Label Positive Edge triggered
-// - -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
-AT91C_AIC_NFIQ EQU (0x1 << 0) ;- (AIC) NFIQ Status
-AT91C_AIC_NIRQ EQU (0x1 << 1) ;- (AIC) NIRQ Status
-// - -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
-AT91C_AIC_DCR_PROT EQU (0x1 << 0) ;- (AIC) Protection Mode
-AT91C_AIC_DCR_GMSK EQU (0x1 << 1) ;- (AIC) General Mask
-#endif
-// - *****************************************************************************
-// - SOFTWARE API DEFINITION FOR Peripheral DMA Controller
-// - *****************************************************************************
-// - -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
-AT91C_PDC_RXTEN EQU (0x1 << 0) ;- (PDC) Receiver Transfer Enable
-AT91C_PDC_RXTDIS EQU (0x1 << 1) ;- (PDC) Receiver Transfer Disable
-AT91C_PDC_TXTEN EQU (0x1 << 8) ;- (PDC) Transmitter Transfer Enable
-AT91C_PDC_TXTDIS EQU (0x1 << 9) ;- (PDC) Transmitter Transfer Disable
-// - -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
-
-// - *****************************************************************************
-// - SOFTWARE API DEFINITION FOR Debug Unit
-// - *****************************************************************************
-// - -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
-AT91C_US_RSTRX EQU (0x1 << 2) ;- (DBGU) Reset Receiver
-AT91C_US_RSTTX EQU (0x1 << 3) ;- (DBGU) Reset Transmitter
-AT91C_US_RXEN EQU (0x1 << 4) ;- (DBGU) Receiver Enable
-AT91C_US_RXDIS EQU (0x1 << 5) ;- (DBGU) Receiver Disable
-AT91C_US_TXEN EQU (0x1 << 6) ;- (DBGU) Transmitter Enable
-AT91C_US_TXDIS EQU (0x1 << 7) ;- (DBGU) Transmitter Disable
-AT91C_US_RSTSTA EQU (0x1 << 8) ;- (DBGU) Reset Status Bits
-// - -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
-AT91C_US_PAR EQU (0x7 << 9) ;- (DBGU) Parity type
-AT91C_US_PAR_EVEN EQU (0x0 << 9) ;- (DBGU) Even Parity
-AT91C_US_PAR_ODD EQU (0x1 << 9) ;- (DBGU) Odd Parity
-AT91C_US_PAR_SPACE EQU (0x2 << 9) ;- (DBGU) Parity forced to 0 (Space)
-AT91C_US_PAR_MARK EQU (0x3 << 9) ;- (DBGU) Parity forced to 1 (Mark)
-AT91C_US_PAR_NONE EQU (0x4 << 9) ;- (DBGU) No Parity
-AT91C_US_PAR_MULTI_DROP EQU (0x6 << 9) ;- (DBGU) Multi-drop mode
-AT91C_US_CHMODE EQU (0x3 << 14) ;- (DBGU) Channel Mode
-AT91C_US_CHMODE_NORMAL EQU (0x0 << 14) ;- (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-AT91C_US_CHMODE_AUTO EQU (0x1 << 14) ;- (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-AT91C_US_CHMODE_LOCAL EQU (0x2 << 14) ;- (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-AT91C_US_CHMODE_REMOTE EQU (0x3 << 14) ;- (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-// - -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
-AT91C_US_RXRDY EQU (0x1 << 0) ;- (DBGU) RXRDY Interrupt
-AT91C_US_TXRDY EQU (0x1 << 1) ;- (DBGU) TXRDY Interrupt
-AT91C_US_ENDRX EQU (0x1 << 3) ;- (DBGU) End of Receive Transfer Interrupt
-AT91C_US_ENDTX EQU (0x1 << 4) ;- (DBGU) End of Transmit Interrupt
-AT91C_US_OVRE EQU (0x1 << 5) ;- (DBGU) Overrun Interrupt
-AT91C_US_FRAME EQU (0x1 << 6) ;- (DBGU) Framing Error Interrupt
-AT91C_US_PARE EQU (0x1 << 7) ;- (DBGU) Parity Error Interrupt
-AT91C_US_TXEMPTY EQU (0x1 << 9) ;- (DBGU) TXEMPTY Interrupt
-AT91C_US_TXBUFE EQU (0x1 << 11) ;- (DBGU) TXBUFE Interrupt
-AT91C_US_RXBUFF EQU (0x1 << 12) ;- (DBGU) RXBUFF Interrupt
-AT91C_US_COMM_TX EQU (0x1 << 30) ;- (DBGU) COMM_TX Interrupt
-AT91C_US_COMM_RX EQU (0x1 << 31) ;- (DBGU) COMM_RX Interrupt
-// - -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// - -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// - -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
-// - -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
-AT91C_US_FORCE_NTRST EQU (0x1 << 0) ;- (DBGU) Force NTRST in JTAG
-
-// - *****************************************************************************
-// - SOFTWARE API DEFINITION FOR Parallel Input Output Controler
-// - *****************************************************************************
-
-// - *****************************************************************************
-// - SOFTWARE API DEFINITION FOR Clock Generator Controler
-// - *****************************************************************************
-// - -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
-AT91C_CKGR_MOSCEN EQU (0x1 << 0) ;- (CKGR) Main Oscillator Enable
-AT91C_CKGR_OSCBYPASS EQU (0x1 << 1) ;- (CKGR) Main Oscillator Bypass
-AT91C_CKGR_OSCOUNT EQU (0xFF << 8) ;- (CKGR) Main Oscillator Start-up Time
-// - -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
-AT91C_CKGR_MAINF EQU (0xFFFF << 0) ;- (CKGR) Main Clock Frequency
-AT91C_CKGR_MAINRDY EQU (0x1 << 16) ;- (CKGR) Main Clock Ready
-// - -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
-AT91C_CKGR_DIV EQU (0xFF << 0) ;- (CKGR) Divider Selected
-AT91C_CKGR_DIV_0 EQU (0x0) ;- (CKGR) Divider output is 0
-AT91C_CKGR_DIV_BYPASS EQU (0x1) ;- (CKGR) Divider is bypassed
-AT91C_CKGR_PLLCOUNT EQU (0x3F << 8) ;- (CKGR) PLL Counter
-AT91C_CKGR_OUT EQU (0x3 << 14) ;- (CKGR) PLL Output Frequency Range
-AT91C_CKGR_OUT_0 EQU (0x0 << 14) ;- (CKGR) Please refer to the PLL datasheet
-AT91C_CKGR_OUT_1 EQU (0x1 << 14) ;- (CKGR) Please refer to the PLL datasheet
-AT91C_CKGR_OUT_2 EQU (0x2 << 14) ;- (CKGR) Please refer to the PLL datasheet
-AT91C_CKGR_OUT_3 EQU (0x3 << 14) ;- (CKGR) Please refer to the PLL datasheet
-AT91C_CKGR_MUL EQU (0x7FF << 16) ;- (CKGR) PLL Multiplier
-AT91C_CKGR_USBDIV EQU (0x3 << 28) ;- (CKGR) Divider for USB Clocks
-AT91C_CKGR_USBDIV_0 EQU (0x0 << 28) ;- (CKGR) Divider output is PLL clock output
-AT91C_CKGR_USBDIV_1 EQU (0x1 << 28) ;- (CKGR) Divider output is PLL clock output divided by 2
-AT91C_CKGR_USBDIV_2 EQU (0x2 << 28) ;- (CKGR) Divider output is PLL clock output divided by 4
-
-// - *****************************************************************************
-// - SOFTWARE API DEFINITION FOR Power Management Controler
-// - *****************************************************************************
-// - -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
-AT91C_PMC_PCK EQU (0x1 << 0) ;- (PMC) Processor Clock
-AT91C_PMC_UDP EQU (0x1 << 7) ;- (PMC) USB Device Port Clock
-AT91C_PMC_PCK0 EQU (0x1 << 8) ;- (PMC) Programmable Clock Output
-AT91C_PMC_PCK1 EQU (0x1 << 9) ;- (PMC) Programmable Clock Output
-AT91C_PMC_PCK2 EQU (0x1 << 10) ;- (PMC) Programmable Clock Output
-AT91C_PMC_PCK3 EQU (0x1 << 11) ;- (PMC) Programmable Clock Output
-// - -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
-// - -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
-// - -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
-// - -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
-// - -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
-// - -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
-AT91C_PMC_CSS EQU (0x3 << 0) ;- (PMC) Programmable Clock Selection
-AT91C_PMC_CSS_SLOW_CLK EQU (0x0) ;- (PMC) Slow Clock is selected
-AT91C_PMC_CSS_MAIN_CLK EQU (0x1) ;- (PMC) Main Clock is selected
-AT91C_PMC_CSS_PLL_CLK EQU (0x3) ;- (PMC) Clock from PLL is selected
-AT91C_PMC_PRES EQU (0x7 << 2) ;- (PMC) Programmable Clock Prescaler
-AT91C_PMC_PRES_CLK EQU (0x0 << 2) ;- (PMC) Selected clock
-AT91C_PMC_PRES_CLK_2 EQU (0x1 << 2) ;- (PMC) Selected clock divided by 2
-AT91C_PMC_PRES_CLK_4 EQU (0x2 << 2) ;- (PMC) Selected clock divided by 4
-AT91C_PMC_PRES_CLK_8 EQU (0x3 << 2) ;- (PMC) Selected clock divided by 8
-AT91C_PMC_PRES_CLK_16 EQU (0x4 << 2) ;- (PMC) Selected clock divided by 16
-AT91C_PMC_PRES_CLK_32 EQU (0x5 << 2) ;- (PMC) Selected clock divided by 32
-AT91C_PMC_PRES_CLK_64 EQU (0x6 << 2) ;- (PMC) Selected clock divided by 64
-// - -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
-// - -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
-AT91C_PMC_MOSCS EQU (0x1 << 0) ;- (PMC) MOSC Status/Enable/Disable/Mask
-AT91C_PMC_LOCK EQU (0x1 << 2) ;- (PMC) PLL Status/Enable/Disable/Mask
-AT91C_PMC_MCKRDY EQU (0x1 << 3) ;- (PMC) MCK_RDY Status/Enable/Disable/Mask
-AT91C_PMC_PCK0RDY EQU (0x1 << 8) ;- (PMC) PCK0_RDY Status/Enable/Disable/Mask
-AT91C_PMC_PCK1RDY EQU (0x1 << 9) ;- (PMC) PCK1_RDY Status/Enable/Disable/Mask
-AT91C_PMC_PCK2RDY EQU (0x1 << 10) ;- (PMC) PCK2_RDY Status/Enable/Disable/Mask
-AT91C_PMC_PCK3RDY EQU (0x1 << 11) ;- (PMC) PCK3_RDY Status/Enable/Disable/Mask
-// - -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
-// - -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
-// - -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
-
-// - *****************************************************************************
-// - SOFTWARE API DEFINITION FOR Reset Controller Interface
-// - *****************************************************************************
-// - -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
-AT91C_RSTC_PROCRST EQU (0x1 << 0) ;- (RSTC) Processor Reset
-AT91C_RSTC_PERRST EQU (0x1 << 2) ;- (RSTC) Peripheral Reset
-AT91C_RSTC_EXTRST EQU (0x1 << 3) ;- (RSTC) External Reset
-AT91C_RSTC_KEY EQU (0xFF << 24) ;- (RSTC) Password
-// - -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
-AT91C_RSTC_URSTS EQU (0x1 << 0) ;- (RSTC) User Reset Status
-AT91C_RSTC_BODSTS EQU (0x1 << 1) ;- (RSTC) Brownout Detection Status
-AT91C_RSTC_RSTTYP EQU (0x7 << 8) ;- (RSTC) Reset Type
-AT91C_RSTC_RSTTYP_POWERUP EQU (0x0 << 8) ;- (RSTC) Power-up Reset. VDDCORE rising.
-AT91C_RSTC_RSTTYP_WAKEUP EQU (0x1 << 8) ;- (RSTC) WakeUp Reset. VDDCORE rising.
-AT91C_RSTC_RSTTYP_WATCHDOG EQU (0x2 << 8) ;- (RSTC) Watchdog Reset. Watchdog overflow occured.
-AT91C_RSTC_RSTTYP_SOFTWARE EQU (0x3 << 8) ;- (RSTC) Software Reset. Processor reset required by the software.
-AT91C_RSTC_RSTTYP_USER EQU (0x4 << 8) ;- (RSTC) User Reset. NRST pin detected low.
-AT91C_RSTC_RSTTYP_BROWNOUT EQU (0x5 << 8) ;- (RSTC) Brownout Reset occured.
-AT91C_RSTC_NRSTL EQU (0x1 << 16) ;- (RSTC) NRST pin level
-AT91C_RSTC_SRCMP EQU (0x1 << 17) ;- (RSTC) Software Reset Command in Progress.
-// - -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
-AT91C_RSTC_URSTEN EQU (0x1 << 0) ;- (RSTC) User Reset Enable
-AT91C_RSTC_URSTIEN EQU (0x1 << 4) ;- (RSTC) User Reset Interrupt Enable
-AT91C_RSTC_ERSTL EQU (0xF << 8) ;- (RSTC) User Reset Enable
-AT91C_RSTC_BODIEN EQU (0x1 << 16) ;- (RSTC) Brownout Detection Interrupt Enable
-
-// - *****************************************************************************
-// - SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
-// - *****************************************************************************
-// - -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
-AT91C_RTTC_RTPRES EQU (0xFFFF << 0) ;- (RTTC) Real-time Timer Prescaler Value
-AT91C_RTTC_ALMIEN EQU (0x1 << 16) ;- (RTTC) Alarm Interrupt Enable
-AT91C_RTTC_RTTINCIEN EQU (0x1 << 17) ;- (RTTC) Real Time Timer Increment Interrupt Enable
-AT91C_RTTC_RTTRST EQU (0x1 << 18) ;- (RTTC) Real Time Timer Restart
-// - -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
-AT91C_RTTC_ALMV EQU (0x0 << 0) ;- (RTTC) Alarm Value
-// - -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
-AT91C_RTTC_CRTV EQU (0x0 << 0) ;- (RTTC) Current Real-time Value
-// - -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
-AT91C_RTTC_ALMS EQU (0x1 << 0) ;- (RTTC) Real-time Alarm Status
-AT91C_RTTC_RTTINC EQU (0x1 << 1) ;- (RTTC) Real-time Timer Increment
-
-// - *****************************************************************************
-// - SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
-// - *****************************************************************************
-// - -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
-AT91C_PITC_PIV EQU (0xFFFFF << 0) ;- (PITC) Periodic Interval Value
-AT91C_PITC_PITEN EQU (0x1 << 24) ;- (PITC) Periodic Interval Timer Enabled
-AT91C_PITC_PITIEN EQU (0x1 << 25) ;- (PITC) Periodic Interval Timer Interrupt Enable
-// - -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
-AT91C_PITC_PITS EQU (0x1 << 0) ;- (PITC) Periodic Interval Timer Status
-// - -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
-AT91C_PITC_CPIV EQU (0xFFFFF << 0) ;- (PITC) Current Periodic Interval Value
-AT91C_PITC_PICNT EQU (0xFFF << 20) ;- (PITC) Periodic Interval Counter
-// - -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
-
-// - *****************************************************************************
-// - SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
-// - *****************************************************************************
-// - -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
-AT91C_WDTC_WDRSTT EQU (0x1 << 0) ;- (WDTC) Watchdog Restart
-AT91C_WDTC_KEY EQU (0xFF << 24) ;- (WDTC) Watchdog KEY Password
-// - -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
-AT91C_WDTC_WDV EQU (0xFFF << 0) ;- (WDTC) Watchdog Timer Restart
-AT91C_WDTC_WDFIEN EQU (0x1 << 12) ;- (WDTC) Watchdog Fault Interrupt Enable
-AT91C_WDTC_WDRSTEN EQU (0x1 << 13) ;- (WDTC) Watchdog Reset Enable
-AT91C_WDTC_WDRPROC EQU (0x1 << 14) ;- (WDTC) Watchdog Timer Restart
-AT91C_WDTC_WDDIS EQU (0x1 << 15) ;- (WDTC) Watchdog Disable
-AT91C_WDTC_WDD EQU (0xFFF << 16) ;- (WDTC) Watchdog Delta Value
-AT91C_WDTC_WDDBGHLT EQU (0x1 << 28) ;- (WDTC) Watchdog Debug Halt
-AT91C_WDTC_WDIDLEHLT EQU (0x1 << 29) ;- (WDTC) Watchdog Idle Halt
-// - -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
-AT91C_WDTC_WDUNF EQU (0x1 << 0) ;- (WDTC) Watchdog Underflow
-AT91C_WDTC_WDERR EQU (0x1 << 1) ;- (WDTC) Watchdog Error
-
-// - *****************************************************************************
-// - SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface
-// - *****************************************************************************
-// - -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
-AT91C_VREG_PSTDBY EQU (0x1 << 0) ;- (VREG) Voltage Regulator Power Standby Mode
-
-// - *****************************************************************************
-// - SOFTWARE API DEFINITION FOR Memory Controller Interface
-// - *****************************************************************************
-// - -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
-AT91C_MC_RCB EQU (0x1 << 0) ;- (MC) Remap Command Bit
-// - -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
-AT91C_MC_UNDADD EQU (0x1 << 0) ;- (MC) Undefined Addess Abort Status
-AT91C_MC_MISADD EQU (0x1 << 1) ;- (MC) Misaligned Addess Abort Status
-AT91C_MC_ABTSZ EQU (0x3 << 8) ;- (MC) Abort Size Status
-AT91C_MC_ABTSZ_BYTE EQU (0x0 << 8) ;- (MC) Byte
-AT91C_MC_ABTSZ_HWORD EQU (0x1 << 8) ;- (MC) Half-word
-AT91C_MC_ABTSZ_WORD EQU (0x2 << 8) ;- (MC) Word
-AT91C_MC_ABTTYP EQU (0x3 << 10) ;- (MC) Abort Type Status
-AT91C_MC_ABTTYP_DATAR EQU (0x0 << 10) ;- (MC) Data Read
-AT91C_MC_ABTTYP_DATAW EQU (0x1 << 10) ;- (MC) Data Write
-AT91C_MC_ABTTYP_FETCH EQU (0x2 << 10) ;- (MC) Code Fetch
-AT91C_MC_MST0 EQU (0x1 << 16) ;- (MC) Master 0 Abort Source
-AT91C_MC_MST1 EQU (0x1 << 17) ;- (MC) Master 1 Abort Source
-AT91C_MC_SVMST0 EQU (0x1 << 24) ;- (MC) Saved Master 0 Abort Source
-AT91C_MC_SVMST1 EQU (0x1 << 25) ;- (MC) Saved Master 1 Abort Source
-// - -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
-AT91C_MC_FRDY EQU (0x1 << 0) ;- (MC) Flash Ready
-AT91C_MC_LOCKE EQU (0x1 << 2) ;- (MC) Lock Error
-AT91C_MC_PROGE EQU (0x1 << 3) ;- (MC) Programming Error
-AT91C_MC_NEBP EQU (0x1 << 7) ;- (MC) No Erase Before Programming
-AT91C_MC_FWS EQU (0x3 << 8) ;- (MC) Flash Wait State
-AT91C_MC_FWS_0FWS EQU (0x0 << 8) ;- (MC) 1 cycle for Read, 2 for Write operations
-AT91C_MC_FWS_1FWS EQU (0x1 << 8) ;- (MC) 2 cycles for Read, 3 for Write operations
-AT91C_MC_FWS_2FWS EQU (0x2 << 8) ;- (MC) 3 cycles for Read, 4 for Write operations
-AT91C_MC_FWS_3FWS EQU (0x3 << 8) ;- (MC) 4 cycles for Read, 4 for Write operations
-AT91C_MC_FMCN EQU (0xFF << 16) ;- (MC) Flash Microsecond Cycle Number
-// - -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
-AT91C_MC_FCMD EQU (0xF << 0) ;- (MC) Flash Command
-AT91C_MC_FCMD_START_PROG EQU (0x1) ;- (MC) Starts the programming of th epage specified by PAGEN.
-AT91C_MC_FCMD_LOCK EQU (0x2) ;- (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-AT91C_MC_FCMD_PROG_AND_LOCK EQU (0x3) ;- (MC) The lock sequence automatically happens after the programming sequence is completed.
-AT91C_MC_FCMD_UNLOCK EQU (0x4) ;- (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-AT91C_MC_FCMD_ERASE_ALL EQU (0x8) ;- (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
-AT91C_MC_FCMD_SET_GP_NVM EQU (0xB) ;- (MC) Set General Purpose NVM bits.
-AT91C_MC_FCMD_CLR_GP_NVM EQU (0xD) ;- (MC) Clear General Purpose NVM bits.
-AT91C_MC_FCMD_SET_SECURITY EQU (0xF) ;- (MC) Set Security Bit.
-AT91C_MC_PAGEN EQU (0x3FF << 8) ;- (MC) Page Number
-AT91C_MC_KEY EQU (0xFF << 24) ;- (MC) Writing Protect Key
-// - -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
-AT91C_MC_SECURITY EQU (0x1 << 4) ;- (MC) Security Bit Status
-AT91C_MC_GPNVM0 EQU (0x1 << 8) ;- (MC) Sector 0 Lock Status
-AT91C_MC_GPNVM1 EQU (0x1 << 9) ;- (MC) Sector 1 Lock Status
-AT91C_MC_GPNVM2 EQU (0x1 << 10) ;- (MC) Sector 2 Lock Status
-AT91C_MC_GPNVM3 EQU (0x1 << 11) ;- (MC) Sector 3 Lock Status
-AT91C_MC_GPNVM4 EQU (0x1 << 12) ;- (MC) Sector 4 Lock Status
-AT91C_MC_GPNVM5 EQU (0x1 << 13) ;- (MC) Sector 5 Lock Status
-AT91C_MC_GPNVM6 EQU (0x1 << 14) ;- (MC) Sector 6 Lock Status
-AT91C_MC_GPNVM7 EQU (0x1 << 15) ;- (MC) Sector 7 Lock Status
-AT91C_MC_LOCKS0 EQU (0x1 << 16) ;- (MC) Sector 0 Lock Status
-AT91C_MC_LOCKS1 EQU (0x1 << 17) ;- (MC) Sector 1 Lock Status
-AT91C_MC_LOCKS2 EQU (0x1 << 18) ;- (MC) Sector 2 Lock Status
-AT91C_MC_LOCKS3 EQU (0x1 << 19) ;- (MC) Sector 3 Lock Status
-AT91C_MC_LOCKS4 EQU (0x1 << 20) ;- (MC) Sector 4 Lock Status
-AT91C_MC_LOCKS5 EQU (0x1 << 21) ;- (MC) Sector 5 Lock Status
-AT91C_MC_LOCKS6 EQU (0x1 << 22) ;- (MC) Sector 6 Lock Status
-AT91C_MC_LOCKS7 EQU (0x1 << 23) ;- (MC) Sector 7 Lock Status
-AT91C_MC_LOCKS8 EQU (0x1 << 24) ;- (MC) Sector 8 Lock Status
-AT91C_MC_LOCKS9 EQU (0x1 << 25) ;- (MC) Sector 9 Lock Status
-AT91C_MC_LOCKS10 EQU (0x1 << 26) ;- (MC) Sector 10 Lock Status
-AT91C_MC_LOCKS11 EQU (0x1 << 27) ;- (MC) Sector 11 Lock Status
-AT91C_MC_LOCKS12 EQU (0x1 << 28) ;- (MC) Sector 12 Lock Status
-AT91C_MC_LOCKS13 EQU (0x1 << 29) ;- (MC) Sector 13 Lock Status
-AT91C_MC_LOCKS14 EQU (0x1 << 30) ;- (MC) Sector 14 Lock Status
-AT91C_MC_LOCKS15 EQU (0x1 << 31) ;- (MC) Sector 15 Lock Status
-
-// - *****************************************************************************
-// - SOFTWARE API DEFINITION FOR Serial Parallel Interface
-// - *****************************************************************************
-// - -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
-AT91C_SPI_SPIEN EQU (0x1 << 0) ;- (SPI) SPI Enable
-AT91C_SPI_SPIDIS EQU (0x1 << 1) ;- (SPI) SPI Disable
-AT91C_SPI_SWRST EQU (0x1 << 7) ;- (SPI) SPI Software reset
-AT91C_SPI_LASTXFER EQU (0x1 << 24) ;- (SPI) SPI Last Transfer
-// - -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
-AT91C_SPI_MSTR EQU (0x1 << 0) ;- (SPI) Master/Slave Mode
-AT91C_SPI_PS EQU (0x1 << 1) ;- (SPI) Peripheral Select
-AT91C_SPI_PS_FIXED EQU (0x0 << 1) ;- (SPI) Fixed Peripheral Select
-AT91C_SPI_PS_VARIABLE EQU (0x1 << 1) ;- (SPI) Variable Peripheral Select
-AT91C_SPI_PCSDEC EQU (0x1 << 2) ;- (SPI) Chip Select Decode
-AT91C_SPI_FDIV EQU (0x1 << 3) ;- (SPI) Clock Selection
-AT91C_SPI_MODFDIS EQU (0x1 << 4) ;- (SPI) Mode Fault Detection
-AT91C_SPI_LLB EQU (0x1 << 7) ;- (SPI) Clock Selection
-AT91C_SPI_PCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select
-AT91C_SPI_DLYBCS EQU (0xFF << 24) ;- (SPI) Delay Between Chip Selects
-// - -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
-AT91C_SPI_RD EQU (0xFFFF << 0) ;- (SPI) Receive Data
-AT91C_SPI_RPCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status
-// - -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
-AT91C_SPI_TD EQU (0xFFFF << 0) ;- (SPI) Transmit Data
-AT91C_SPI_TPCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status
-// - -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
-AT91C_SPI_RDRF EQU (0x1 << 0) ;- (SPI) Receive Data Register Full
-AT91C_SPI_TDRE EQU (0x1 << 1) ;- (SPI) Transmit Data Register Empty
-AT91C_SPI_MODF EQU (0x1 << 2) ;- (SPI) Mode Fault Error
-AT91C_SPI_OVRES EQU (0x1 << 3) ;- (SPI) Overrun Error Status
-AT91C_SPI_ENDRX EQU (0x1 << 4) ;- (SPI) End of Receiver Transfer
-AT91C_SPI_ENDTX EQU (0x1 << 5) ;- (SPI) End of Receiver Transfer
-AT91C_SPI_RXBUFF EQU (0x1 << 6) ;- (SPI) RXBUFF Interrupt
-AT91C_SPI_TXBUFE EQU (0x1 << 7) ;- (SPI) TXBUFE Interrupt
-AT91C_SPI_NSSR EQU (0x1 << 8) ;- (SPI) NSSR Interrupt
-AT91C_SPI_TXEMPTY EQU (0x1 << 9) ;- (SPI) TXEMPTY Interrupt
-AT91C_SPI_SPIENS EQU (0x1 << 16) ;- (SPI) Enable Status
-// - -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
-// - -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
-// - -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
-// - -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
-AT91C_SPI_CPOL EQU (0x1 << 0) ;- (SPI) Clock Polarity
-AT91C_SPI_NCPHA EQU (0x1 << 1) ;- (SPI) Clock Phase
-AT91C_SPI_CSAAT EQU (0x1 << 3) ;- (SPI) Chip Select Active After Transfer
-AT91C_SPI_BITS EQU (0xF << 4) ;- (SPI) Bits Per Transfer
-AT91C_SPI_BITS_8 EQU (0x0 << 4) ;- (SPI) 8 Bits Per transfer
-AT91C_SPI_BITS_9 EQU (0x1 << 4) ;- (SPI) 9 Bits Per transfer
-AT91C_SPI_BITS_10 EQU (0x2 << 4) ;- (SPI) 10 Bits Per transfer
-AT91C_SPI_BITS_11 EQU (0x3 << 4) ;- (SPI) 11 Bits Per transfer
-AT91C_SPI_BITS_12 EQU (0x4 << 4) ;- (SPI) 12 Bits Per transfer
-AT91C_SPI_BITS_13 EQU (0x5 << 4) ;- (SPI) 13 Bits Per transfer
-AT91C_SPI_BITS_14 EQU (0x6 << 4) ;- (SPI) 14 Bits Per transfer
-AT91C_SPI_BITS_15 EQU (0x7 << 4) ;- (SPI) 15 Bits Per transfer
-AT91C_SPI_BITS_16 EQU (0x8 << 4) ;- (SPI) 16 Bits Per transfer
-AT91C_SPI_SCBR EQU (0xFF << 8) ;- (SPI) Serial Clock Baud Rate
-AT91C_SPI_DLYBS EQU (0xFF << 16) ;- (SPI) Delay Before SPCK
-AT91C_SPI_DLYBCT EQU (0xFF << 24) ;- (SPI) Delay Between Consecutive Transfers
-
-// - *****************************************************************************
-// - SOFTWARE API DEFINITION FOR Usart
-// - *****************************************************************************
-// - -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
-AT91C_US_STTBRK EQU (0x1 << 9) ;- (USART) Start Break
-AT91C_US_STPBRK EQU (0x1 << 10) ;- (USART) Stop Break
-AT91C_US_STTTO EQU (0x1 << 11) ;- (USART) Start Time-out
-AT91C_US_SENDA EQU (0x1 << 12) ;- (USART) Send Address
-AT91C_US_RSTIT EQU (0x1 << 13) ;- (USART) Reset Iterations
-AT91C_US_RSTNACK EQU (0x1 << 14) ;- (USART) Reset Non Acknowledge
-AT91C_US_RETTO EQU (0x1 << 15) ;- (USART) Rearm Time-out
-AT91C_US_DTREN EQU (0x1 << 16) ;- (USART) Data Terminal ready Enable
-AT91C_US_DTRDIS EQU (0x1 << 17) ;- (USART) Data Terminal ready Disable
-AT91C_US_RTSEN EQU (0x1 << 18) ;- (USART) Request to Send enable
-AT91C_US_RTSDIS EQU (0x1 << 19) ;- (USART) Request to Send Disable
-// - -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
-AT91C_US_USMODE EQU (0xF << 0) ;- (USART) Usart mode
-AT91C_US_USMODE_NORMAL EQU (0x0) ;- (USART) Normal
-AT91C_US_USMODE_RS485 EQU (0x1) ;- (USART) RS485
-AT91C_US_USMODE_HWHSH EQU (0x2) ;- (USART) Hardware Handshaking
-AT91C_US_USMODE_MODEM EQU (0x3) ;- (USART) Modem
-AT91C_US_USMODE_ISO7816_0 EQU (0x4) ;- (USART) ISO7816 protocol: T = 0
-AT91C_US_USMODE_ISO7816_1 EQU (0x6) ;- (USART) ISO7816 protocol: T = 1
-AT91C_US_USMODE_IRDA EQU (0x8) ;- (USART) IrDA
-AT91C_US_USMODE_SWHSH EQU (0xC) ;- (USART) Software Handshaking
-AT91C_US_CLKS EQU (0x3 << 4) ;- (USART) Clock Selection (Baud Rate generator Input Clock
-AT91C_US_CLKS_CLOCK EQU (0x0 << 4) ;- (USART) Clock
-AT91C_US_CLKS_FDIV1 EQU (0x1 << 4) ;- (USART) fdiv1
-AT91C_US_CLKS_SLOW EQU (0x2 << 4) ;- (USART) slow_clock (ARM)
-AT91C_US_CLKS_EXT EQU (0x3 << 4) ;- (USART) External (SCK)
-AT91C_US_CHRL EQU (0x3 << 6) ;- (USART) Clock Selection (Baud Rate generator Input Clock
-AT91C_US_CHRL_5_BITS EQU (0x0 << 6) ;- (USART) Character Length: 5 bits
-AT91C_US_CHRL_6_BITS EQU (0x1 << 6) ;- (USART) Character Length: 6 bits
-AT91C_US_CHRL_7_BITS EQU (0x2 << 6) ;- (USART) Character Length: 7 bits
-AT91C_US_CHRL_8_BITS EQU (0x3 << 6) ;- (USART) Character Length: 8 bits
-AT91C_US_SYNC EQU (0x1 << 8) ;- (USART) Synchronous Mode Select
-AT91C_US_NBSTOP EQU (0x3 << 12) ;- (USART) Number of Stop bits
-AT91C_US_NBSTOP_1_BIT EQU (0x0 << 12) ;- (USART) 1 stop bit
-AT91C_US_NBSTOP_15_BIT EQU (0x1 << 12) ;- (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-AT91C_US_NBSTOP_2_BIT EQU (0x2 << 12) ;- (USART) 2 stop bits
-AT91C_US_MSBF EQU (0x1 << 16) ;- (USART) Bit Order
-AT91C_US_MODE9 EQU (0x1 << 17) ;- (USART) 9-bit Character length
-AT91C_US_CKLO EQU (0x1 << 18) ;- (USART) Clock Output Select
-AT91C_US_OVER EQU (0x1 << 19) ;- (USART) Over Sampling Mode
-AT91C_US_INACK EQU (0x1 << 20) ;- (USART) Inhibit Non Acknowledge
-AT91C_US_DSNACK EQU (0x1 << 21) ;- (USART) Disable Successive NACK
-AT91C_US_MAX_ITER EQU (0x1 << 24) ;- (USART) Number of Repetitions
-AT91C_US_FILTER EQU (0x1 << 28) ;- (USART) Receive Line Filter
-// - -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
-AT91C_US_RXBRK EQU (0x1 << 2) ;- (USART) Break Received/End of Break
-AT91C_US_TIMEOUT EQU (0x1 << 8) ;- (USART) Receiver Time-out
-AT91C_US_ITERATION EQU (0x1 << 10) ;- (USART) Max number of Repetitions Reached
-AT91C_US_NACK EQU (0x1 << 13) ;- (USART) Non Acknowledge
-AT91C_US_RIIC EQU (0x1 << 16) ;- (USART) Ring INdicator Input Change Flag
-AT91C_US_DSRIC EQU (0x1 << 17) ;- (USART) Data Set Ready Input Change Flag
-AT91C_US_DCDIC EQU (0x1 << 18) ;- (USART) Data Carrier Flag
-AT91C_US_CTSIC EQU (0x1 << 19) ;- (USART) Clear To Send Input Change Flag
-// - -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// - -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// - -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
-AT91C_US_RI EQU (0x1 << 20) ;- (USART) Image of RI Input
-AT91C_US_DSR EQU (0x1 << 21) ;- (USART) Image of DSR Input
-AT91C_US_DCD EQU (0x1 << 22) ;- (USART) Image of DCD Input
-AT91C_US_CTS EQU (0x1 << 23) ;- (USART) Image of CTS Input
-
-// - *****************************************************************************
-// - SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
-// - *****************************************************************************
-// - -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
-AT91C_SSC_RXEN EQU (0x1 << 0) ;- (SSC) Receive Enable
-AT91C_SSC_RXDIS EQU (0x1 << 1) ;- (SSC) Receive Disable
-AT91C_SSC_TXEN EQU (0x1 << 8) ;- (SSC) Transmit Enable
-AT91C_SSC_TXDIS EQU (0x1 << 9) ;- (SSC) Transmit Disable
-AT91C_SSC_SWRST EQU (0x1 << 15) ;- (SSC) Software Reset
-// - -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
-AT91C_SSC_CKS EQU (0x3 << 0) ;- (SSC) Receive/Transmit Clock Selection
-AT91C_SSC_CKS_DIV EQU (0x0) ;- (SSC) Divided Clock
-AT91C_SSC_CKS_TK EQU (0x1) ;- (SSC) TK Clock signal
-AT91C_SSC_CKS_RK EQU (0x2) ;- (SSC) RK pin
-AT91C_SSC_CKO EQU (0x7 << 2) ;- (SSC) Receive/Transmit Clock Output Mode Selection
-AT91C_SSC_CKO_NONE EQU (0x0 << 2) ;- (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-AT91C_SSC_CKO_CONTINOUS EQU (0x1 << 2) ;- (SSC) Continuous Receive/Transmit Clock RK pin: Output
-AT91C_SSC_CKO_DATA_TX EQU (0x2 << 2) ;- (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-AT91C_SSC_CKI EQU (0x1 << 5) ;- (SSC) Receive/Transmit Clock Inversion
-AT91C_SSC_START EQU (0xF << 8) ;- (SSC) Receive/Transmit Start Selection
-AT91C_SSC_START_CONTINOUS EQU (0x0 << 8) ;- (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-AT91C_SSC_START_TX EQU (0x1 << 8) ;- (SSC) Transmit/Receive start
-AT91C_SSC_START_LOW_RF EQU (0x2 << 8) ;- (SSC) Detection of a low level on RF input
-AT91C_SSC_START_HIGH_RF EQU (0x3 << 8) ;- (SSC) Detection of a high level on RF input
-AT91C_SSC_START_FALL_RF EQU (0x4 << 8) ;- (SSC) Detection of a falling edge on RF input
-AT91C_SSC_START_RISE_RF EQU (0x5 << 8) ;- (SSC) Detection of a rising edge on RF input
-AT91C_SSC_START_LEVEL_RF EQU (0x6 << 8) ;- (SSC) Detection of any level change on RF input
-AT91C_SSC_START_EDGE_RF EQU (0x7 << 8) ;- (SSC) Detection of any edge on RF input
-AT91C_SSC_START_0 EQU (0x8 << 8) ;- (SSC) Compare 0
-AT91C_SSC_STTDLY EQU (0xFF << 16) ;- (SSC) Receive/Transmit Start Delay
-AT91C_SSC_PERIOD EQU (0xFF << 24) ;- (SSC) Receive/Transmit Period Divider Selection
-// - -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
-AT91C_SSC_DATLEN EQU (0x1F << 0) ;- (SSC) Data Length
-AT91C_SSC_LOOP EQU (0x1 << 5) ;- (SSC) Loop Mode
-AT91C_SSC_MSBF EQU (0x1 << 7) ;- (SSC) Most Significant Bit First
-AT91C_SSC_DATNB EQU (0xF << 8) ;- (SSC) Data Number per Frame
-AT91C_SSC_FSLEN EQU (0xF << 16) ;- (SSC) Receive/Transmit Frame Sync length
-AT91C_SSC_FSOS EQU (0x7 << 20) ;- (SSC) Receive/Transmit Frame Sync Output Selection
-AT91C_SSC_FSOS_NONE EQU (0x0 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-AT91C_SSC_FSOS_NEGATIVE EQU (0x1 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-AT91C_SSC_FSOS_POSITIVE EQU (0x2 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-AT91C_SSC_FSOS_LOW EQU (0x3 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-AT91C_SSC_FSOS_HIGH EQU (0x4 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-AT91C_SSC_FSOS_TOGGLE EQU (0x5 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-AT91C_SSC_FSEDGE EQU (0x1 << 24) ;- (SSC) Frame Sync Edge Detection
-// - -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
-// - -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
-AT91C_SSC_DATDEF EQU (0x1 << 5) ;- (SSC) Data Default Value
-AT91C_SSC_FSDEN EQU (0x1 << 23) ;- (SSC) Frame Sync Data Enable
-// - -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
-AT91C_SSC_TXRDY EQU (0x1 << 0) ;- (SSC) Transmit Ready
-AT91C_SSC_TXEMPTY EQU (0x1 << 1) ;- (SSC) Transmit Empty
-AT91C_SSC_ENDTX EQU (0x1 << 2) ;- (SSC) End Of Transmission
-AT91C_SSC_TXBUFE EQU (0x1 << 3) ;- (SSC) Transmit Buffer Empty
-AT91C_SSC_RXRDY EQU (0x1 << 4) ;- (SSC) Receive Ready
-AT91C_SSC_OVRUN EQU (0x1 << 5) ;- (SSC) Receive Overrun
-AT91C_SSC_ENDRX EQU (0x1 << 6) ;- (SSC) End of Reception
-AT91C_SSC_RXBUFF EQU (0x1 << 7) ;- (SSC) Receive Buffer Full
-AT91C_SSC_TXSYN EQU (0x1 << 10) ;- (SSC) Transmit Sync
-AT91C_SSC_RXSYN EQU (0x1 << 11) ;- (SSC) Receive Sync
-AT91C_SSC_TXENA EQU (0x1 << 16) ;- (SSC) Transmit Enable
-AT91C_SSC_RXENA EQU (0x1 << 17) ;- (SSC) Receive Enable
-// - -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
-// - -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
-// - -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
-
-// - *****************************************************************************
-// - SOFTWARE API DEFINITION FOR Two-wire Interface
-// - *****************************************************************************
-// - -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
-AT91C_TWI_START EQU (0x1 << 0) ;- (TWI) Send a START Condition
-AT91C_TWI_STOP EQU (0x1 << 1) ;- (TWI) Send a STOP Condition
-AT91C_TWI_MSEN EQU (0x1 << 2) ;- (TWI) TWI Master Transfer Enabled
-AT91C_TWI_MSDIS EQU (0x1 << 3) ;- (TWI) TWI Master Transfer Disabled
-AT91C_TWI_SWRST EQU (0x1 << 7) ;- (TWI) Software Reset
-// - -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
-AT91C_TWI_IADRSZ EQU (0x3 << 8) ;- (TWI) Internal Device Address Size
-AT91C_TWI_IADRSZ_NO EQU (0x0 << 8) ;- (TWI) No internal device address
-AT91C_TWI_IADRSZ_1_BYTE EQU (0x1 << 8) ;- (TWI) One-byte internal device address
-AT91C_TWI_IADRSZ_2_BYTE EQU (0x2 << 8) ;- (TWI) Two-byte internal device address
-AT91C_TWI_IADRSZ_3_BYTE EQU (0x3 << 8) ;- (TWI) Three-byte internal device address
-AT91C_TWI_MREAD EQU (0x1 << 12) ;- (TWI) Master Read Direction
-AT91C_TWI_DADR EQU (0x7F << 16) ;- (TWI) Device Address
-// - -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
-AT91C_TWI_CLDIV EQU (0xFF << 0) ;- (TWI) Clock Low Divider
-AT91C_TWI_CHDIV EQU (0xFF << 8) ;- (TWI) Clock High Divider
-AT91C_TWI_CKDIV EQU (0x7 << 16) ;- (TWI) Clock Divider
-// - -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
-AT91C_TWI_TXCOMP EQU (0x1 << 0) ;- (TWI) Transmission Completed
-AT91C_TWI_RXRDY EQU (0x1 << 1) ;- (TWI) Receive holding register ReaDY
-AT91C_TWI_TXRDY EQU (0x1 << 2) ;- (TWI) Transmit holding register ReaDY
-AT91C_TWI_OVRE EQU (0x1 << 6) ;- (TWI) Overrun Error
-AT91C_TWI_UNRE EQU (0x1 << 7) ;- (TWI) Underrun Error
-AT91C_TWI_NACK EQU (0x1 << 8) ;- (TWI) Not Acknowledged
-// - -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
-// - -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
-// - -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
-
-// - *****************************************************************************
-// - SOFTWARE API DEFINITION FOR PWMC Channel Interface
-// - *****************************************************************************
-// - -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
-AT91C_PWMC_CPRE EQU (0xF << 0) ;- (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
-AT91C_PWMC_CPRE_MCK EQU (0x0) ;- (PWMC_CH)
-AT91C_PWMC_CPRE_MCKA EQU (0xB) ;- (PWMC_CH)
-AT91C_PWMC_CPRE_MCKB EQU (0xC) ;- (PWMC_CH)
-AT91C_PWMC_CALG EQU (0x1 << 8) ;- (PWMC_CH) Channel Alignment
-AT91C_PWMC_CPOL EQU (0x1 << 9) ;- (PWMC_CH) Channel Polarity
-AT91C_PWMC_CPD EQU (0x1 << 10) ;- (PWMC_CH) Channel Update Period
-// - -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
-AT91C_PWMC_CDTY EQU (0x0 << 0) ;- (PWMC_CH) Channel Duty Cycle
-// - -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
-AT91C_PWMC_CPRD EQU (0x0 << 0) ;- (PWMC_CH) Channel Period
-// - -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
-AT91C_PWMC_CCNT EQU (0x0 << 0) ;- (PWMC_CH) Channel Counter
-// - -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
-AT91C_PWMC_CUPD EQU (0x0 << 0) ;- (PWMC_CH) Channel Update
-
-// - *****************************************************************************
-// - SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
-// - *****************************************************************************
-// - -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
-AT91C_PWMC_DIVA EQU (0xFF << 0) ;- (PWMC) CLKA divide factor.
-AT91C_PWMC_PREA EQU (0xF << 8) ;- (PWMC) Divider Input Clock Prescaler A
-AT91C_PWMC_PREA_MCK EQU (0x0 << 8) ;- (PWMC)
-AT91C_PWMC_DIVB EQU (0xFF << 16) ;- (PWMC) CLKB divide factor.
-AT91C_PWMC_PREB EQU (0xF << 24) ;- (PWMC) Divider Input Clock Prescaler B
-AT91C_PWMC_PREB_MCK EQU (0x0 << 24) ;- (PWMC)
-// - -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
-AT91C_PWMC_CHID0 EQU (0x1 << 0) ;- (PWMC) Channel ID 0
-AT91C_PWMC_CHID1 EQU (0x1 << 1) ;- (PWMC) Channel ID 1
-AT91C_PWMC_CHID2 EQU (0x1 << 2) ;- (PWMC) Channel ID 2
-AT91C_PWMC_CHID3 EQU (0x1 << 3) ;- (PWMC) Channel ID 3
-// - -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
-// - -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
-// - -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
-// - -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
-// - -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
-// - -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
-
-// - *****************************************************************************
-// - SOFTWARE API DEFINITION FOR USB Device Interface
-// - *****************************************************************************
-// - -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
-AT91C_UDP_FRM_NUM EQU (0x7FF << 0) ;- (UDP) Frame Number as Defined in the Packet Field Formats
-AT91C_UDP_FRM_ERR EQU (0x1 << 16) ;- (UDP) Frame Error
-AT91C_UDP_FRM_OK EQU (0x1 << 17) ;- (UDP) Frame OK
-// - -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
-AT91C_UDP_FADDEN EQU (0x1 << 0) ;- (UDP) Function Address Enable
-AT91C_UDP_CONFG EQU (0x1 << 1) ;- (UDP) Configured
-AT91C_UDP_ESR EQU (0x1 << 2) ;- (UDP) Enable Send Resume
-AT91C_UDP_RSMINPR EQU (0x1 << 3) ;- (UDP) A Resume Has Been Sent to the Host
-AT91C_UDP_RMWUPE EQU (0x1 << 4) ;- (UDP) Remote Wake Up Enable
-// - -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
-AT91C_UDP_FADD EQU (0xFF << 0) ;- (UDP) Function Address Value
-AT91C_UDP_FEN EQU (0x1 << 8) ;- (UDP) Function Enable
-// - -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
-AT91C_UDP_EPINT0 EQU (0x1 << 0) ;- (UDP) Endpoint 0 Interrupt
-AT91C_UDP_EPINT1 EQU (0x1 << 1) ;- (UDP) Endpoint 0 Interrupt
-AT91C_UDP_EPINT2 EQU (0x1 << 2) ;- (UDP) Endpoint 2 Interrupt
-AT91C_UDP_EPINT3 EQU (0x1 << 3) ;- (UDP) Endpoint 3 Interrupt
-AT91C_UDP_EPINT4 EQU (0x1 << 4) ;- (UDP) Endpoint 4 Interrupt
-AT91C_UDP_EPINT5 EQU (0x1 << 5) ;- (UDP) Endpoint 5 Interrupt
-AT91C_UDP_RXSUSP EQU (0x1 << 8) ;- (UDP) USB Suspend Interrupt
-AT91C_UDP_RXRSM EQU (0x1 << 9) ;- (UDP) USB Resume Interrupt
-AT91C_UDP_EXTRSM EQU (0x1 << 10) ;- (UDP) USB External Resume Interrupt
-AT91C_UDP_SOFINT EQU (0x1 << 11) ;- (UDP) USB Start Of frame Interrupt
-AT91C_UDP_WAKEUP EQU (0x1 << 13) ;- (UDP) USB Resume Interrupt
-// - -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
-// - -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
-// - -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
-AT91C_UDP_ENDBUSRES EQU (0x1 << 12) ;- (UDP) USB End Of Bus Reset Interrupt
-// - -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
-// - -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
-AT91C_UDP_EP0 EQU (0x1 << 0) ;- (UDP) Reset Endpoint 0
-AT91C_UDP_EP1 EQU (0x1 << 1) ;- (UDP) Reset Endpoint 1
-AT91C_UDP_EP2 EQU (0x1 << 2) ;- (UDP) Reset Endpoint 2
-AT91C_UDP_EP3 EQU (0x1 << 3) ;- (UDP) Reset Endpoint 3
-AT91C_UDP_EP4 EQU (0x1 << 4) ;- (UDP) Reset Endpoint 4
-AT91C_UDP_EP5 EQU (0x1 << 5) ;- (UDP) Reset Endpoint 5
-// - -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
-AT91C_UDP_TXCOMP EQU (0x1 << 0) ;- (UDP) Generates an IN packet with data previously written in the DPR
-AT91C_UDP_RX_DATA_BK0 EQU (0x1 << 1) ;- (UDP) Receive Data Bank 0
-AT91C_UDP_RXSETUP EQU (0x1 << 2) ;- (UDP) Sends STALL to the Host (Control endpoints)
-AT91C_UDP_ISOERROR EQU (0x1 << 3) ;- (UDP) Isochronous error (Isochronous endpoints)
-AT91C_UDP_TXPKTRDY EQU (0x1 << 4) ;- (UDP) Transmit Packet Ready
-AT91C_UDP_FORCESTALL EQU (0x1 << 5) ;- (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-AT91C_UDP_RX_DATA_BK1 EQU (0x1 << 6) ;- (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-AT91C_UDP_DIR EQU (0x1 << 7) ;- (UDP) Transfer Direction
-AT91C_UDP_EPTYPE EQU (0x7 << 8) ;- (UDP) Endpoint type
-AT91C_UDP_EPTYPE_CTRL EQU (0x0 << 8) ;- (UDP) Control
-AT91C_UDP_EPTYPE_ISO_OUT EQU (0x1 << 8) ;- (UDP) Isochronous OUT
-AT91C_UDP_EPTYPE_BULK_OUT EQU (0x2 << 8) ;- (UDP) Bulk OUT
-AT91C_UDP_EPTYPE_INT_OUT EQU (0x3 << 8) ;- (UDP) Interrupt OUT
-AT91C_UDP_EPTYPE_ISO_IN EQU (0x5 << 8) ;- (UDP) Isochronous IN
-AT91C_UDP_EPTYPE_BULK_IN EQU (0x6 << 8) ;- (UDP) Bulk IN
-AT91C_UDP_EPTYPE_INT_IN EQU (0x7 << 8) ;- (UDP) Interrupt IN
-AT91C_UDP_DTGLE EQU (0x1 << 11) ;- (UDP) Data Toggle
-AT91C_UDP_EPEDS EQU (0x1 << 15) ;- (UDP) Endpoint Enable Disable
-AT91C_UDP_RXBYTECNT EQU (0x7FF << 16) ;- (UDP) Number Of Bytes Available in the FIFO
-// - -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
-AT91C_UDP_TXVDIS EQU (0x1 << 8) ;- (UDP)
-AT91C_UDP_PUON EQU (0x1 << 9) ;- (UDP) Pull-up ON
-
-// - *****************************************************************************
-// - SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
-// - *****************************************************************************
-// - -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
-AT91C_TC_CLKEN EQU (0x1 << 0) ;- (TC) Counter Clock Enable Command
-AT91C_TC_CLKDIS EQU (0x1 << 1) ;- (TC) Counter Clock Disable Command
-AT91C_TC_SWTRG EQU (0x1 << 2) ;- (TC) Software Trigger Command
-// - -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
-AT91C_TC_CLKS EQU (0x7 << 0) ;- (TC) Clock Selection
-AT91C_TC_CLKS_TIMER_DIV1_CLOCK EQU (0x0) ;- (TC) Clock selected: TIMER_DIV1_CLOCK
-AT91C_TC_CLKS_TIMER_DIV2_CLOCK EQU (0x1) ;- (TC) Clock selected: TIMER_DIV2_CLOCK
-AT91C_TC_CLKS_TIMER_DIV3_CLOCK EQU (0x2) ;- (TC) Clock selected: TIMER_DIV3_CLOCK
-AT91C_TC_CLKS_TIMER_DIV4_CLOCK EQU (0x3) ;- (TC) Clock selected: TIMER_DIV4_CLOCK
-AT91C_TC_CLKS_TIMER_DIV5_CLOCK EQU (0x4) ;- (TC) Clock selected: TIMER_DIV5_CLOCK
-AT91C_TC_CLKS_XC0 EQU (0x5) ;- (TC) Clock selected: XC0
-AT91C_TC_CLKS_XC1 EQU (0x6) ;- (TC) Clock selected: XC1
-AT91C_TC_CLKS_XC2 EQU (0x7) ;- (TC) Clock selected: XC2
-AT91C_TC_CLKI EQU (0x1 << 3) ;- (TC) Clock Invert
-AT91C_TC_BURST EQU (0x3 << 4) ;- (TC) Burst Signal Selection
-AT91C_TC_BURST_NONE EQU (0x0 << 4) ;- (TC) The clock is not gated by an external signal
-AT91C_TC_BURST_XC0 EQU (0x1 << 4) ;- (TC) XC0 is ANDed with the selected clock
-AT91C_TC_BURST_XC1 EQU (0x2 << 4) ;- (TC) XC1 is ANDed with the selected clock
-AT91C_TC_BURST_XC2 EQU (0x3 << 4) ;- (TC) XC2 is ANDed with the selected clock
-AT91C_TC_CPCSTOP EQU (0x1 << 6) ;- (TC) Counter Clock Stopped with RC Compare
-AT91C_TC_LDBSTOP EQU (0x1 << 6) ;- (TC) Counter Clock Stopped with RB Loading
-AT91C_TC_CPCDIS EQU (0x1 << 7) ;- (TC) Counter Clock Disable with RC Compare
-AT91C_TC_LDBDIS EQU (0x1 << 7) ;- (TC) Counter Clock Disabled with RB Loading
-AT91C_TC_ETRGEDG EQU (0x3 << 8) ;- (TC) External Trigger Edge Selection
-AT91C_TC_ETRGEDG_NONE EQU (0x0 << 8) ;- (TC) Edge: None
-AT91C_TC_ETRGEDG_RISING EQU (0x1 << 8) ;- (TC) Edge: rising edge
-AT91C_TC_ETRGEDG_FALLING EQU (0x2 << 8) ;- (TC) Edge: falling edge
-AT91C_TC_ETRGEDG_BOTH EQU (0x3 << 8) ;- (TC) Edge: each edge
-AT91C_TC_EEVTEDG EQU (0x3 << 8) ;- (TC) External Event Edge Selection
-AT91C_TC_EEVTEDG_NONE EQU (0x0 << 8) ;- (TC) Edge: None
-AT91C_TC_EEVTEDG_RISING EQU (0x1 << 8) ;- (TC) Edge: rising edge
-AT91C_TC_EEVTEDG_FALLING EQU (0x2 << 8) ;- (TC) Edge: falling edge
-AT91C_TC_EEVTEDG_BOTH EQU (0x3 << 8) ;- (TC) Edge: each edge
-AT91C_TC_EEVT EQU (0x3 << 10) ;- (TC) External Event Selection
-AT91C_TC_EEVT_TIOB EQU (0x0 << 10) ;- (TC) Signal selected as external event: TIOB TIOB direction: input
-AT91C_TC_EEVT_XC0 EQU (0x1 << 10) ;- (TC) Signal selected as external event: XC0 TIOB direction: output
-AT91C_TC_EEVT_XC1 EQU (0x2 << 10) ;- (TC) Signal selected as external event: XC1 TIOB direction: output
-AT91C_TC_EEVT_XC2 EQU (0x3 << 10) ;- (TC) Signal selected as external event: XC2 TIOB direction: output
-AT91C_TC_ABETRG EQU (0x1 << 10) ;- (TC) TIOA or TIOB External Trigger Selection
-AT91C_TC_ENETRG EQU (0x1 << 12) ;- (TC) External Event Trigger enable
-AT91C_TC_WAVESEL EQU (0x3 << 13) ;- (TC) Waveform Selection
-AT91C_TC_WAVESEL_UP EQU (0x0 << 13) ;- (TC) UP mode without atomatic trigger on RC Compare
-AT91C_TC_WAVESEL_UPDOWN EQU (0x1 << 13) ;- (TC) UPDOWN mode without automatic trigger on RC Compare
-AT91C_TC_WAVESEL_UP_AUTO EQU (0x2 << 13) ;- (TC) UP mode with automatic trigger on RC Compare
-AT91C_TC_WAVESEL_UPDOWN_AUTO EQU (0x3 << 13) ;- (TC) UPDOWN mode with automatic trigger on RC Compare
-AT91C_TC_CPCTRG EQU (0x1 << 14) ;- (TC) RC Compare Trigger Enable
-AT91C_TC_WAVE EQU (0x1 << 15) ;- (TC)
-AT91C_TC_ACPA EQU (0x3 << 16) ;- (TC) RA Compare Effect on TIOA
-AT91C_TC_ACPA_NONE EQU (0x0 << 16) ;- (TC) Effect: none
-AT91C_TC_ACPA_SET EQU (0x1 << 16) ;- (TC) Effect: set
-AT91C_TC_ACPA_CLEAR EQU (0x2 << 16) ;- (TC) Effect: clear
-AT91C_TC_ACPA_TOGGLE EQU (0x3 << 16) ;- (TC) Effect: toggle
-AT91C_TC_LDRA EQU (0x3 << 16) ;- (TC) RA Loading Selection
-AT91C_TC_LDRA_NONE EQU (0x0 << 16) ;- (TC) Edge: None
-AT91C_TC_LDRA_RISING EQU (0x1 << 16) ;- (TC) Edge: rising edge of TIOA
-AT91C_TC_LDRA_FALLING EQU (0x2 << 16) ;- (TC) Edge: falling edge of TIOA
-AT91C_TC_LDRA_BOTH EQU (0x3 << 16) ;- (TC) Edge: each edge of TIOA
-AT91C_TC_ACPC EQU (0x3 << 18) ;- (TC) RC Compare Effect on TIOA
-AT91C_TC_ACPC_NONE EQU (0x0 << 18) ;- (TC) Effect: none
-AT91C_TC_ACPC_SET EQU (0x1 << 18) ;- (TC) Effect: set
-AT91C_TC_ACPC_CLEAR EQU (0x2 << 18) ;- (TC) Effect: clear
-AT91C_TC_ACPC_TOGGLE EQU (0x3 << 18) ;- (TC) Effect: toggle
-AT91C_TC_LDRB EQU (0x3 << 18) ;- (TC) RB Loading Selection
-AT91C_TC_LDRB_NONE EQU (0x0 << 18) ;- (TC) Edge: None
-AT91C_TC_LDRB_RISING EQU (0x1 << 18) ;- (TC) Edge: rising edge of TIOA
-AT91C_TC_LDRB_FALLING EQU (0x2 << 18) ;- (TC) Edge: falling edge of TIOA
-AT91C_TC_LDRB_BOTH EQU (0x3 << 18) ;- (TC) Edge: each edge of TIOA
-AT91C_TC_AEEVT EQU (0x3 << 20) ;- (TC) External Event Effect on TIOA
-AT91C_TC_AEEVT_NONE EQU (0x0 << 20) ;- (TC) Effect: none
-AT91C_TC_AEEVT_SET EQU (0x1 << 20) ;- (TC) Effect: set
-AT91C_TC_AEEVT_CLEAR EQU (0x2 << 20) ;- (TC) Effect: clear
-AT91C_TC_AEEVT_TOGGLE EQU (0x3 << 20) ;- (TC) Effect: toggle
-AT91C_TC_ASWTRG EQU (0x3 << 22) ;- (TC) Software Trigger Effect on TIOA
-AT91C_TC_ASWTRG_NONE EQU (0x0 << 22) ;- (TC) Effect: none
-AT91C_TC_ASWTRG_SET EQU (0x1 << 22) ;- (TC) Effect: set
-AT91C_TC_ASWTRG_CLEAR EQU (0x2 << 22) ;- (TC) Effect: clear
-AT91C_TC_ASWTRG_TOGGLE EQU (0x3 << 22) ;- (TC) Effect: toggle
-AT91C_TC_BCPB EQU (0x3 << 24) ;- (TC) RB Compare Effect on TIOB
-AT91C_TC_BCPB_NONE EQU (0x0 << 24) ;- (TC) Effect: none
-AT91C_TC_BCPB_SET EQU (0x1 << 24) ;- (TC) Effect: set
-AT91C_TC_BCPB_CLEAR EQU (0x2 << 24) ;- (TC) Effect: clear
-AT91C_TC_BCPB_TOGGLE EQU (0x3 << 24) ;- (TC) Effect: toggle
-AT91C_TC_BCPC EQU (0x3 << 26) ;- (TC) RC Compare Effect on TIOB
-AT91C_TC_BCPC_NONE EQU (0x0 << 26) ;- (TC) Effect: none
-AT91C_TC_BCPC_SET EQU (0x1 << 26) ;- (TC) Effect: set
-AT91C_TC_BCPC_CLEAR EQU (0x2 << 26) ;- (TC) Effect: clear
-AT91C_TC_BCPC_TOGGLE EQU (0x3 << 26) ;- (TC) Effect: toggle
-AT91C_TC_BEEVT EQU (0x3 << 28) ;- (TC) External Event Effect on TIOB
-AT91C_TC_BEEVT_NONE EQU (0x0 << 28) ;- (TC) Effect: none
-AT91C_TC_BEEVT_SET EQU (0x1 << 28) ;- (TC) Effect: set
-AT91C_TC_BEEVT_CLEAR EQU (0x2 << 28) ;- (TC) Effect: clear
-AT91C_TC_BEEVT_TOGGLE EQU (0x3 << 28) ;- (TC) Effect: toggle
-AT91C_TC_BSWTRG EQU (0x3 << 30) ;- (TC) Software Trigger Effect on TIOB
-AT91C_TC_BSWTRG_NONE EQU (0x0 << 30) ;- (TC) Effect: none
-AT91C_TC_BSWTRG_SET EQU (0x1 << 30) ;- (TC) Effect: set
-AT91C_TC_BSWTRG_CLEAR EQU (0x2 << 30) ;- (TC) Effect: clear
-AT91C_TC_BSWTRG_TOGGLE EQU (0x3 << 30) ;- (TC) Effect: toggle
-// - -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
-AT91C_TC_COVFS EQU (0x1 << 0) ;- (TC) Counter Overflow
-AT91C_TC_LOVRS EQU (0x1 << 1) ;- (TC) Load Overrun
-AT91C_TC_CPAS EQU (0x1 << 2) ;- (TC) RA Compare
-AT91C_TC_CPBS EQU (0x1 << 3) ;- (TC) RB Compare
-AT91C_TC_CPCS EQU (0x1 << 4) ;- (TC) RC Compare
-AT91C_TC_LDRAS EQU (0x1 << 5) ;- (TC) RA Loading
-AT91C_TC_LDRBS EQU (0x1 << 6) ;- (TC) RB Loading
-AT91C_TC_ETRGS EQU (0x1 << 7) ;- (TC) External Trigger
-AT91C_TC_CLKSTA EQU (0x1 << 16) ;- (TC) Clock Enabling
-AT91C_TC_MTIOA EQU (0x1 << 17) ;- (TC) TIOA Mirror
-AT91C_TC_MTIOB EQU (0x1 << 18) ;- (TC) TIOA Mirror
-// - -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
-// - -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
-// - -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
-
-// - *****************************************************************************
-// - SOFTWARE API DEFINITION FOR Timer Counter Interface
-// - *****************************************************************************
-// - -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
-AT91C_TCB_SYNC EQU (0x1 << 0) ;- (TCB) Synchro Command
-// - -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
-AT91C_TCB_TC0XC0S EQU (0x3 << 0) ;- (TCB) External Clock Signal 0 Selection
-AT91C_TCB_TC0XC0S_TCLK0 EQU (0x0) ;- (TCB) TCLK0 connected to XC0
-AT91C_TCB_TC0XC0S_NONE EQU (0x1) ;- (TCB) None signal connected to XC0
-AT91C_TCB_TC0XC0S_TIOA1 EQU (0x2) ;- (TCB) TIOA1 connected to XC0
-AT91C_TCB_TC0XC0S_TIOA2 EQU (0x3) ;- (TCB) TIOA2 connected to XC0
-AT91C_TCB_TC1XC1S EQU (0x3 << 2) ;- (TCB) External Clock Signal 1 Selection
-AT91C_TCB_TC1XC1S_TCLK1 EQU (0x0 << 2) ;- (TCB) TCLK1 connected to XC1
-AT91C_TCB_TC1XC1S_NONE EQU (0x1 << 2) ;- (TCB) None signal connected to XC1
-AT91C_TCB_TC1XC1S_TIOA0 EQU (0x2 << 2) ;- (TCB) TIOA0 connected to XC1
-AT91C_TCB_TC1XC1S_TIOA2 EQU (0x3 << 2) ;- (TCB) TIOA2 connected to XC1
-AT91C_TCB_TC2XC2S EQU (0x3 << 4) ;- (TCB) External Clock Signal 2 Selection
-AT91C_TCB_TC2XC2S_TCLK2 EQU (0x0 << 4) ;- (TCB) TCLK2 connected to XC2
-AT91C_TCB_TC2XC2S_NONE EQU (0x1 << 4) ;- (TCB) None signal connected to XC2
-AT91C_TCB_TC2XC2S_TIOA0 EQU (0x2 << 4) ;- (TCB) TIOA0 connected to XC2
-AT91C_TCB_TC2XC2S_TIOA1 EQU (0x3 << 4) ;- (TCB) TIOA2 connected to XC2
-
-// - *****************************************************************************
-// - SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface
-// - *****************************************************************************
-// - -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register --------
-AT91C_CAN_MTIMEMARK EQU (0xFFFF << 0) ;- (CAN_MB) Mailbox Timemark
-AT91C_CAN_PRIOR EQU (0xF << 16) ;- (CAN_MB) Mailbox Priority
-AT91C_CAN_MOT EQU (0x7 << 24) ;- (CAN_MB) Mailbox Object Type
-AT91C_CAN_MOT_DIS EQU (0x0 << 24) ;- (CAN_MB)
-AT91C_CAN_MOT_RX EQU (0x1 << 24) ;- (CAN_MB)
-AT91C_CAN_MOT_RXOVERWRITE EQU (0x2 << 24) ;- (CAN_MB)
-AT91C_CAN_MOT_TX EQU (0x3 << 24) ;- (CAN_MB)
-AT91C_CAN_MOT_CONSUMER EQU (0x4 << 24) ;- (CAN_MB)
-AT91C_CAN_MOT_PRODUCER EQU (0x5 << 24) ;- (CAN_MB)
-// - -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register --------
-AT91C_CAN_MIDvB EQU (0x3FFFF << 0) ;- (CAN_MB) Complementary bits for identifier in extended mode
-AT91C_CAN_MIDvA EQU (0x7FF << 18) ;- (CAN_MB) Identifier for standard frame mode
-AT91C_CAN_MIDE EQU (0x1 << 29) ;- (CAN_MB) Identifier Version
-// - -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register --------
-// - -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register --------
-// - -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register --------
-AT91C_CAN_MTIMESTAMP EQU (0xFFFF << 0) ;- (CAN_MB) Timer Value
-AT91C_CAN_MDLC EQU (0xF << 16) ;- (CAN_MB) Mailbox Data Length Code
-AT91C_CAN_MRTR EQU (0x1 << 20) ;- (CAN_MB) Mailbox Remote Transmission Request
-AT91C_CAN_MABT EQU (0x1 << 22) ;- (CAN_MB) Mailbox Message Abort
-AT91C_CAN_MRDY EQU (0x1 << 23) ;- (CAN_MB) Mailbox Ready
-AT91C_CAN_MMI EQU (0x1 << 24) ;- (CAN_MB) Mailbox Message Ignored
-// - -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register --------
-// - -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register --------
-// - -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register --------
-AT91C_CAN_MACR EQU (0x1 << 22) ;- (CAN_MB) Abort Request for Mailbox
-AT91C_CAN_MTCR EQU (0x1 << 23) ;- (CAN_MB) Mailbox Transfer Command
-
-// - *****************************************************************************
-// - SOFTWARE API DEFINITION FOR Control Area Network Interface
-// - *****************************************************************************
-// - -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register --------
-AT91C_CAN_CANEN EQU (0x1 << 0) ;- (CAN) CAN Controller Enable
-AT91C_CAN_LPM EQU (0x1 << 1) ;- (CAN) Disable/Enable Low Power Mode
-AT91C_CAN_ABM EQU (0x1 << 2) ;- (CAN) Disable/Enable Autobaud/Listen Mode
-AT91C_CAN_OVL EQU (0x1 << 3) ;- (CAN) Disable/Enable Overload Frame
-AT91C_CAN_TEOF EQU (0x1 << 4) ;- (CAN) Time Stamp messages at each end of Frame
-AT91C_CAN_TTM EQU (0x1 << 5) ;- (CAN) Disable/Enable Time Trigger Mode
-AT91C_CAN_TIMFRZ EQU (0x1 << 6) ;- (CAN) Enable Timer Freeze
-AT91C_CAN_DRPT EQU (0x1 << 7) ;- (CAN) Disable Repeat
-// - -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register --------
-AT91C_CAN_MB0 EQU (0x1 << 0) ;- (CAN) Mailbox 0 Flag
-AT91C_CAN_MB1 EQU (0x1 << 1) ;- (CAN) Mailbox 1 Flag
-AT91C_CAN_MB2 EQU (0x1 << 2) ;- (CAN) Mailbox 2 Flag
-AT91C_CAN_MB3 EQU (0x1 << 3) ;- (CAN) Mailbox 3 Flag
-AT91C_CAN_MB4 EQU (0x1 << 4) ;- (CAN) Mailbox 4 Flag
-AT91C_CAN_MB5 EQU (0x1 << 5) ;- (CAN) Mailbox 5 Flag
-AT91C_CAN_MB6 EQU (0x1 << 6) ;- (CAN) Mailbox 6 Flag
-AT91C_CAN_MB7 EQU (0x1 << 7) ;- (CAN) Mailbox 7 Flag
-AT91C_CAN_MB8 EQU (0x1 << 8) ;- (CAN) Mailbox 8 Flag
-AT91C_CAN_MB9 EQU (0x1 << 9) ;- (CAN) Mailbox 9 Flag
-AT91C_CAN_MB10 EQU (0x1 << 10) ;- (CAN) Mailbox 10 Flag
-AT91C_CAN_MB11 EQU (0x1 << 11) ;- (CAN) Mailbox 11 Flag
-AT91C_CAN_MB12 EQU (0x1 << 12) ;- (CAN) Mailbox 12 Flag
-AT91C_CAN_MB13 EQU (0x1 << 13) ;- (CAN) Mailbox 13 Flag
-AT91C_CAN_MB14 EQU (0x1 << 14) ;- (CAN) Mailbox 14 Flag
-AT91C_CAN_MB15 EQU (0x1 << 15) ;- (CAN) Mailbox 15 Flag
-AT91C_CAN_ERRA EQU (0x1 << 16) ;- (CAN) Error Active Mode Flag
-AT91C_CAN_WARN EQU (0x1 << 17) ;- (CAN) Warning Limit Flag
-AT91C_CAN_ERRP EQU (0x1 << 18) ;- (CAN) Error Passive Mode Flag
-AT91C_CAN_BOFF EQU (0x1 << 19) ;- (CAN) Bus Off Mode Flag
-AT91C_CAN_SLEEP EQU (0x1 << 20) ;- (CAN) Sleep Flag
-AT91C_CAN_WAKEUP EQU (0x1 << 21) ;- (CAN) Wakeup Flag
-AT91C_CAN_TOVF EQU (0x1 << 22) ;- (CAN) Timer Overflow Flag
-AT91C_CAN_TSTP EQU (0x1 << 23) ;- (CAN) Timestamp Flag
-AT91C_CAN_CERR EQU (0x1 << 24) ;- (CAN) CRC Error
-AT91C_CAN_SERR EQU (0x1 << 25) ;- (CAN) Stuffing Error
-AT91C_CAN_AERR EQU (0x1 << 26) ;- (CAN) Acknowledgment Error
-AT91C_CAN_FERR EQU (0x1 << 27) ;- (CAN) Form Error
-AT91C_CAN_BERR EQU (0x1 << 28) ;- (CAN) Bit Error
-// - -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register --------
-// - -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register --------
-// - -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register --------
-AT91C_CAN_RBSY EQU (0x1 << 29) ;- (CAN) Receiver Busy
-AT91C_CAN_TBSY EQU (0x1 << 30) ;- (CAN) Transmitter Busy
-AT91C_CAN_OVLY EQU (0x1 << 31) ;- (CAN) Overload Busy
-// - -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register --------
-AT91C_CAN_PHASE2 EQU (0x7 << 0) ;- (CAN) Phase 2 segment
-AT91C_CAN_PHASE1 EQU (0x7 << 4) ;- (CAN) Phase 1 segment
-AT91C_CAN_PROPAG EQU (0x7 << 8) ;- (CAN) Programmation time segment
-AT91C_CAN_SYNC EQU (0x3 << 12) ;- (CAN) Re-synchronization jump width segment
-AT91C_CAN_BRP EQU (0x7F << 16) ;- (CAN) Baudrate Prescaler
-AT91C_CAN_SMP EQU (0x1 << 24) ;- (CAN) Sampling mode
-// - -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register --------
-AT91C_CAN_TIMER EQU (0xFFFF << 0) ;- (CAN) Timer field
-// - -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register --------
-// - -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register --------
-AT91C_CAN_REC EQU (0xFF << 0) ;- (CAN) Receive Error Counter
-AT91C_CAN_TEC EQU (0xFF << 16) ;- (CAN) Transmit Error Counter
-// - -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register --------
-AT91C_CAN_TIMRST EQU (0x1 << 31) ;- (CAN) Timer Reset Field
-// - -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register --------
-
-// - *****************************************************************************
-// - SOFTWARE API DEFINITION FOR Ethernet MAC 10/100
-// - *****************************************************************************
-// - -------- EMAC_NCR : (EMAC Offset: 0x0) --------
-AT91C_EMAC_LB EQU (0x1 << 0) ;- (EMAC) Loopback. Optional. When set, loopback signal is at high level.
-AT91C_EMAC_LLB EQU (0x1 << 1) ;- (EMAC) Loopback local.
-AT91C_EMAC_RE EQU (0x1 << 2) ;- (EMAC) Receive enable.
-AT91C_EMAC_TE EQU (0x1 << 3) ;- (EMAC) Transmit enable.
-AT91C_EMAC_MPE EQU (0x1 << 4) ;- (EMAC) Management port enable.
-AT91C_EMAC_CLRSTAT EQU (0x1 << 5) ;- (EMAC) Clear statistics registers.
-AT91C_EMAC_INCSTAT EQU (0x1 << 6) ;- (EMAC) Increment statistics registers.
-AT91C_EMAC_WESTAT EQU (0x1 << 7) ;- (EMAC) Write enable for statistics registers.
-AT91C_EMAC_BP EQU (0x1 << 8) ;- (EMAC) Back pressure.
-AT91C_EMAC_TSTART EQU (0x1 << 9) ;- (EMAC) Start Transmission.
-AT91C_EMAC_THALT EQU (0x1 << 10) ;- (EMAC) Transmission Halt.
-AT91C_EMAC_TPFR EQU (0x1 << 11) ;- (EMAC) Transmit pause frame
-AT91C_EMAC_TZQ EQU (0x1 << 12) ;- (EMAC) Transmit zero quantum pause frame
-// - -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register --------
-AT91C_EMAC_SPD EQU (0x1 << 0) ;- (EMAC) Speed.
-AT91C_EMAC_FD EQU (0x1 << 1) ;- (EMAC) Full duplex.
-AT91C_EMAC_JFRAME EQU (0x1 << 3) ;- (EMAC) Jumbo Frames.
-AT91C_EMAC_CAF EQU (0x1 << 4) ;- (EMAC) Copy all frames.
-AT91C_EMAC_NBC EQU (0x1 << 5) ;- (EMAC) No broadcast.
-AT91C_EMAC_MTI EQU (0x1 << 6) ;- (EMAC) Multicast hash event enable
-AT91C_EMAC_UNI EQU (0x1 << 7) ;- (EMAC) Unicast hash enable.
-AT91C_EMAC_BIG EQU (0x1 << 8) ;- (EMAC) Receive 1522 bytes.
-AT91C_EMAC_EAE EQU (0x1 << 9) ;- (EMAC) External address match enable.
-AT91C_EMAC_CLK EQU (0x3 << 10) ;- (EMAC)
-AT91C_EMAC_CLK_HCLK_8 EQU (0x0 << 10) ;- (EMAC) HCLK divided by 8
-AT91C_EMAC_CLK_HCLK_16 EQU (0x1 << 10) ;- (EMAC) HCLK divided by 16
-AT91C_EMAC_CLK_HCLK_32 EQU (0x2 << 10) ;- (EMAC) HCLK divided by 32
-AT91C_EMAC_CLK_HCLK_64 EQU (0x3 << 10) ;- (EMAC) HCLK divided by 64
-AT91C_EMAC_RTY EQU (0x1 << 12) ;- (EMAC)
-AT91C_EMAC_PAE EQU (0x1 << 13) ;- (EMAC)
-AT91C_EMAC_RBOF EQU (0x3 << 14) ;- (EMAC)
-AT91C_EMAC_RBOF_OFFSET_0 EQU (0x0 << 14) ;- (EMAC) no offset from start of receive buffer
-AT91C_EMAC_RBOF_OFFSET_1 EQU (0x1 << 14) ;- (EMAC) one byte offset from start of receive buffer
-AT91C_EMAC_RBOF_OFFSET_2 EQU (0x2 << 14) ;- (EMAC) two bytes offset from start of receive buffer
-AT91C_EMAC_RBOF_OFFSET_3 EQU (0x3 << 14) ;- (EMAC) three bytes offset from start of receive buffer
-AT91C_EMAC_RLCE EQU (0x1 << 16) ;- (EMAC) Receive Length field Checking Enable
-AT91C_EMAC_DRFCS EQU (0x1 << 17) ;- (EMAC) Discard Receive FCS
-AT91C_EMAC_EFRHD EQU (0x1 << 18) ;- (EMAC)
-AT91C_EMAC_IRXFCS EQU (0x1 << 19) ;- (EMAC) Ignore RX FCS
-// - -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register --------
-AT91C_EMAC_LINKR EQU (0x1 << 0) ;- (EMAC)
-AT91C_EMAC_MDIO EQU (0x1 << 1) ;- (EMAC)
-AT91C_EMAC_IDLE EQU (0x1 << 2) ;- (EMAC)
-// - -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register --------
-AT91C_EMAC_UBR EQU (0x1 << 0) ;- (EMAC)
-AT91C_EMAC_COL EQU (0x1 << 1) ;- (EMAC)
-AT91C_EMAC_RLES EQU (0x1 << 2) ;- (EMAC)
-AT91C_EMAC_TGO EQU (0x1 << 3) ;- (EMAC) Transmit Go
-AT91C_EMAC_BEX EQU (0x1 << 4) ;- (EMAC) Buffers exhausted mid frame
-AT91C_EMAC_COMP EQU (0x1 << 5) ;- (EMAC)
-AT91C_EMAC_UND EQU (0x1 << 6) ;- (EMAC)
-// - -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
-AT91C_EMAC_BNA EQU (0x1 << 0) ;- (EMAC)
-AT91C_EMAC_REC EQU (0x1 << 1) ;- (EMAC)
-AT91C_EMAC_OVR EQU (0x1 << 2) ;- (EMAC)
-// - -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
-AT91C_EMAC_MFD EQU (0x1 << 0) ;- (EMAC)
-AT91C_EMAC_RCOMP EQU (0x1 << 1) ;- (EMAC)
-AT91C_EMAC_RXUBR EQU (0x1 << 2) ;- (EMAC)
-AT91C_EMAC_TXUBR EQU (0x1 << 3) ;- (EMAC)
-AT91C_EMAC_TUNDR EQU (0x1 << 4) ;- (EMAC)
-AT91C_EMAC_RLEX EQU (0x1 << 5) ;- (EMAC)
-AT91C_EMAC_TXERR EQU (0x1 << 6) ;- (EMAC)
-AT91C_EMAC_TCOMP EQU (0x1 << 7) ;- (EMAC)
-AT91C_EMAC_LINK EQU (0x1 << 9) ;- (EMAC)
-AT91C_EMAC_ROVR EQU (0x1 << 10) ;- (EMAC)
-AT91C_EMAC_HRESP EQU (0x1 << 11) ;- (EMAC)
-AT91C_EMAC_PFRE EQU (0x1 << 12) ;- (EMAC)
-AT91C_EMAC_PTZ EQU (0x1 << 13) ;- (EMAC)
-// - -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
-// - -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
-// - -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
-// - -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
-AT91C_EMAC_DATA EQU (0xFFFF << 0) ;- (EMAC)
-AT91C_EMAC_CODE EQU (0x3 << 16) ;- (EMAC)
-AT91C_EMAC_REGA EQU (0x1F << 18) ;- (EMAC)
-AT91C_EMAC_PHYA EQU (0x1F << 23) ;- (EMAC)
-AT91C_EMAC_RW EQU (0x3 << 28) ;- (EMAC)
-AT91C_EMAC_SOF EQU (0x3 << 30) ;- (EMAC)
-// - -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register --------
-AT91C_EMAC_RMII EQU (0x1 << 0) ;- (EMAC) Reduce MII
-// - -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register --------
-AT91C_EMAC_IP EQU (0xFFFF << 0) ;- (EMAC) ARP request IP address
-AT91C_EMAC_MAG EQU (0x1 << 16) ;- (EMAC) Magic packet event enable
-AT91C_EMAC_ARP EQU (0x1 << 17) ;- (EMAC) ARP request event enable
-AT91C_EMAC_SA1 EQU (0x1 << 18) ;- (EMAC) Specific address register 1 event enable
-// - -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register --------
-AT91C_EMAC_REVREF EQU (0xFFFF << 0) ;- (EMAC)
-AT91C_EMAC_PARTREF EQU (0xFFFF << 16) ;- (EMAC)
-
-// - *****************************************************************************
-// - SOFTWARE API DEFINITION FOR Analog to Digital Convertor
-// - *****************************************************************************
-// - -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
-AT91C_ADC_SWRST EQU (0x1 << 0) ;- (ADC) Software Reset
-AT91C_ADC_START EQU (0x1 << 1) ;- (ADC) Start Conversion
-// - -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
-AT91C_ADC_TRGEN EQU (0x1 << 0) ;- (ADC) Trigger Enable
-AT91C_ADC_TRGEN_DIS EQU (0x0) ;- (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
-AT91C_ADC_TRGEN_EN EQU (0x1) ;- (ADC) Hardware trigger selected by TRGSEL field is enabled.
-AT91C_ADC_TRGSEL EQU (0x7 << 1) ;- (ADC) Trigger Selection
-AT91C_ADC_TRGSEL_TIOA0 EQU (0x0 << 1) ;- (ADC) Selected TRGSEL = TIAO0
-AT91C_ADC_TRGSEL_TIOA1 EQU (0x1 << 1) ;- (ADC) Selected TRGSEL = TIAO1
-AT91C_ADC_TRGSEL_TIOA2 EQU (0x2 << 1) ;- (ADC) Selected TRGSEL = TIAO2
-AT91C_ADC_TRGSEL_TIOA3 EQU (0x3 << 1) ;- (ADC) Selected TRGSEL = TIAO3
-AT91C_ADC_TRGSEL_TIOA4 EQU (0x4 << 1) ;- (ADC) Selected TRGSEL = TIAO4
-AT91C_ADC_TRGSEL_TIOA5 EQU (0x5 << 1) ;- (ADC) Selected TRGSEL = TIAO5
-AT91C_ADC_TRGSEL_EXT EQU (0x6 << 1) ;- (ADC) Selected TRGSEL = External Trigger
-AT91C_ADC_LOWRES EQU (0x1 << 4) ;- (ADC) Resolution.
-AT91C_ADC_LOWRES_10_BIT EQU (0x0 << 4) ;- (ADC) 10-bit resolution
-AT91C_ADC_LOWRES_8_BIT EQU (0x1 << 4) ;- (ADC) 8-bit resolution
-AT91C_ADC_SLEEP EQU (0x1 << 5) ;- (ADC) Sleep Mode
-AT91C_ADC_SLEEP_NORMAL_MODE EQU (0x0 << 5) ;- (ADC) Normal Mode
-AT91C_ADC_SLEEP_MODE EQU (0x1 << 5) ;- (ADC) Sleep Mode
-AT91C_ADC_PRESCAL EQU (0x3F << 8) ;- (ADC) Prescaler rate selection
-AT91C_ADC_STARTUP EQU (0x1F << 16) ;- (ADC) Startup Time
-AT91C_ADC_SHTIM EQU (0xF << 24) ;- (ADC) Sample & Hold Time
-// - -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
-AT91C_ADC_CH0 EQU (0x1 << 0) ;- (ADC) Channel 0
-AT91C_ADC_CH1 EQU (0x1 << 1) ;- (ADC) Channel 1
-AT91C_ADC_CH2 EQU (0x1 << 2) ;- (ADC) Channel 2
-AT91C_ADC_CH3 EQU (0x1 << 3) ;- (ADC) Channel 3
-AT91C_ADC_CH4 EQU (0x1 << 4) ;- (ADC) Channel 4
-AT91C_ADC_CH5 EQU (0x1 << 5) ;- (ADC) Channel 5
-AT91C_ADC_CH6 EQU (0x1 << 6) ;- (ADC) Channel 6
-AT91C_ADC_CH7 EQU (0x1 << 7) ;- (ADC) Channel 7
-// - -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
-// - -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
-// - -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
-AT91C_ADC_EOC0 EQU (0x1 << 0) ;- (ADC) End of Conversion
-AT91C_ADC_EOC1 EQU (0x1 << 1) ;- (ADC) End of Conversion
-AT91C_ADC_EOC2 EQU (0x1 << 2) ;- (ADC) End of Conversion
-AT91C_ADC_EOC3 EQU (0x1 << 3) ;- (ADC) End of Conversion
-AT91C_ADC_EOC4 EQU (0x1 << 4) ;- (ADC) End of Conversion
-AT91C_ADC_EOC5 EQU (0x1 << 5) ;- (ADC) End of Conversion
-AT91C_ADC_EOC6 EQU (0x1 << 6) ;- (ADC) End of Conversion
-AT91C_ADC_EOC7 EQU (0x1 << 7) ;- (ADC) End of Conversion
-AT91C_ADC_OVRE0 EQU (0x1 << 8) ;- (ADC) Overrun Error
-AT91C_ADC_OVRE1 EQU (0x1 << 9) ;- (ADC) Overrun Error
-AT91C_ADC_OVRE2 EQU (0x1 << 10) ;- (ADC) Overrun Error
-AT91C_ADC_OVRE3 EQU (0x1 << 11) ;- (ADC) Overrun Error
-AT91C_ADC_OVRE4 EQU (0x1 << 12) ;- (ADC) Overrun Error
-AT91C_ADC_OVRE5 EQU (0x1 << 13) ;- (ADC) Overrun Error
-AT91C_ADC_OVRE6 EQU (0x1 << 14) ;- (ADC) Overrun Error
-AT91C_ADC_OVRE7 EQU (0x1 << 15) ;- (ADC) Overrun Error
-AT91C_ADC_DRDY EQU (0x1 << 16) ;- (ADC) Data Ready
-AT91C_ADC_GOVRE EQU (0x1 << 17) ;- (ADC) General Overrun
-AT91C_ADC_ENDRX EQU (0x1 << 18) ;- (ADC) End of Receiver Transfer
-AT91C_ADC_RXBUFF EQU (0x1 << 19) ;- (ADC) RXBUFF Interrupt
-// - -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
-AT91C_ADC_LDATA EQU (0x3FF << 0) ;- (ADC) Last Data Converted
-// - -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
-// - -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
-// - -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
-// - -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
-AT91C_ADC_DATA EQU (0x3FF << 0) ;- (ADC) Converted Data
-// - -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
-// - -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
-// - -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
-// - -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
-// - -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
-// - -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
-// - -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
-
-// - *****************************************************************************
-// - SOFTWARE API DEFINITION FOR Advanced Encryption Standard
-// - *****************************************************************************
-// - -------- AES_CR : (AES Offset: 0x0) Control Register --------
-AT91C_AES_START EQU (0x1 << 0) ;- (AES) Starts Processing
-AT91C_AES_SWRST EQU (0x1 << 8) ;- (AES) Software Reset
-AT91C_AES_LOADSEED EQU (0x1 << 16) ;- (AES) Random Number Generator Seed Loading
-// - -------- AES_MR : (AES Offset: 0x4) Mode Register --------
-AT91C_AES_CIPHER EQU (0x1 << 0) ;- (AES) Processing Mode
-AT91C_AES_PROCDLY EQU (0xF << 4) ;- (AES) Processing Delay
-AT91C_AES_SMOD EQU (0x3 << 8) ;- (AES) Start Mode
-AT91C_AES_SMOD_MANUAL EQU (0x0 << 8) ;- (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
-AT91C_AES_SMOD_AUTO EQU (0x1 << 8) ;- (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
-AT91C_AES_SMOD_PDC EQU (0x2 << 8) ;- (AES) PDC Mode (cf datasheet).
-AT91C_AES_OPMOD EQU (0x7 << 12) ;- (AES) Operation Mode
-AT91C_AES_OPMOD_ECB EQU (0x0 << 12) ;- (AES) ECB Electronic CodeBook mode.
-AT91C_AES_OPMOD_CBC EQU (0x1 << 12) ;- (AES) CBC Cipher Block Chaining mode.
-AT91C_AES_OPMOD_OFB EQU (0x2 << 12) ;- (AES) OFB Output Feedback mode.
-AT91C_AES_OPMOD_CFB EQU (0x3 << 12) ;- (AES) CFB Cipher Feedback mode.
-AT91C_AES_OPMOD_CTR EQU (0x4 << 12) ;- (AES) CTR Counter mode.
-AT91C_AES_LOD EQU (0x1 << 15) ;- (AES) Last Output Data Mode
-AT91C_AES_CFBS EQU (0x7 << 16) ;- (AES) Cipher Feedback Data Size
-AT91C_AES_CFBS_128_BIT EQU (0x0 << 16) ;- (AES) 128-bit.
-AT91C_AES_CFBS_64_BIT EQU (0x1 << 16) ;- (AES) 64-bit.
-AT91C_AES_CFBS_32_BIT EQU (0x2 << 16) ;- (AES) 32-bit.
-AT91C_AES_CFBS_16_BIT EQU (0x3 << 16) ;- (AES) 16-bit.
-AT91C_AES_CFBS_8_BIT EQU (0x4 << 16) ;- (AES) 8-bit.
-AT91C_AES_CKEY EQU (0xF << 20) ;- (AES) Countermeasure Key
-AT91C_AES_CTYPE EQU (0x1F << 24) ;- (AES) Countermeasure Type
-AT91C_AES_CTYPE_TYPE1_EN EQU (0x1 << 24) ;- (AES) Countermeasure type 1 is enabled.
-AT91C_AES_CTYPE_TYPE2_EN EQU (0x2 << 24) ;- (AES) Countermeasure type 2 is enabled.
-AT91C_AES_CTYPE_TYPE3_EN EQU (0x4 << 24) ;- (AES) Countermeasure type 3 is enabled.
-AT91C_AES_CTYPE_TYPE4_EN EQU (0x8 << 24) ;- (AES) Countermeasure type 4 is enabled.
-AT91C_AES_CTYPE_TYPE5_EN EQU (0x10 << 24) ;- (AES) Countermeasure type 5 is enabled.
-// - -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register --------
-AT91C_AES_DATRDY EQU (0x1 << 0) ;- (AES) DATRDY
-AT91C_AES_ENDRX EQU (0x1 << 1) ;- (AES) PDC Read Buffer End
-AT91C_AES_ENDTX EQU (0x1 << 2) ;- (AES) PDC Write Buffer End
-AT91C_AES_RXBUFF EQU (0x1 << 3) ;- (AES) PDC Read Buffer Full
-AT91C_AES_TXBUFE EQU (0x1 << 4) ;- (AES) PDC Write Buffer Empty
-AT91C_AES_URAD EQU (0x1 << 8) ;- (AES) Unspecified Register Access Detection
-// - -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register --------
-// - -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register --------
-// - -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register --------
-AT91C_AES_URAT EQU (0x7 << 12) ;- (AES) Unspecified Register Access Type Status
-AT91C_AES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (AES) Input data register written during the data processing in PDC mode.
-AT91C_AES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (AES) Output data register read during the data processing.
-AT91C_AES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (AES) Mode register written during the data processing.
-AT91C_AES_URAT_OUT_DAT_READ_SUBKEY EQU (0x3 << 12) ;- (AES) Output data register read during the sub-keys generation.
-AT91C_AES_URAT_MODEREG_WRITE_SUBKEY EQU (0x4 << 12) ;- (AES) Mode register written during the sub-keys generation.
-AT91C_AES_URAT_WO_REG_READ EQU (0x5 << 12) ;- (AES) Write-only register read access.
-
-// - *****************************************************************************
-// - SOFTWARE API DEFINITION FOR Triple Data Encryption Standard
-// - *****************************************************************************
-// - -------- TDES_CR : (TDES Offset: 0x0) Control Register --------
-AT91C_TDES_START EQU (0x1 << 0) ;- (TDES) Starts Processing
-AT91C_TDES_SWRST EQU (0x1 << 8) ;- (TDES) Software Reset
-// - -------- TDES_MR : (TDES Offset: 0x4) Mode Register --------
-AT91C_TDES_CIPHER EQU (0x1 << 0) ;- (TDES) Processing Mode
-AT91C_TDES_TDESMOD EQU (0x1 << 1) ;- (TDES) Single or Triple DES Mode
-AT91C_TDES_KEYMOD EQU (0x1 << 4) ;- (TDES) Key Mode
-AT91C_TDES_SMOD EQU (0x3 << 8) ;- (TDES) Start Mode
-AT91C_TDES_SMOD_MANUAL EQU (0x0 << 8) ;- (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
-AT91C_TDES_SMOD_AUTO EQU (0x1 << 8) ;- (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
-AT91C_TDES_SMOD_PDC EQU (0x2 << 8) ;- (TDES) PDC Mode (cf datasheet).
-AT91C_TDES_OPMOD EQU (0x3 << 12) ;- (TDES) Operation Mode
-AT91C_TDES_OPMOD_ECB EQU (0x0 << 12) ;- (TDES) ECB Electronic CodeBook mode.
-AT91C_TDES_OPMOD_CBC EQU (0x1 << 12) ;- (TDES) CBC Cipher Block Chaining mode.
-AT91C_TDES_OPMOD_OFB EQU (0x2 << 12) ;- (TDES) OFB Output Feedback mode.
-AT91C_TDES_OPMOD_CFB EQU (0x3 << 12) ;- (TDES) CFB Cipher Feedback mode.
-AT91C_TDES_LOD EQU (0x1 << 15) ;- (TDES) Last Output Data Mode
-AT91C_TDES_CFBS EQU (0x3 << 16) ;- (TDES) Cipher Feedback Data Size
-AT91C_TDES_CFBS_64_BIT EQU (0x0 << 16) ;- (TDES) 64-bit.
-AT91C_TDES_CFBS_32_BIT EQU (0x1 << 16) ;- (TDES) 32-bit.
-AT91C_TDES_CFBS_16_BIT EQU (0x2 << 16) ;- (TDES) 16-bit.
-AT91C_TDES_CFBS_8_BIT EQU (0x3 << 16) ;- (TDES) 8-bit.
-// - -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register --------
-AT91C_TDES_DATRDY EQU (0x1 << 0) ;- (TDES) DATRDY
-AT91C_TDES_ENDRX EQU (0x1 << 1) ;- (TDES) PDC Read Buffer End
-AT91C_TDES_ENDTX EQU (0x1 << 2) ;- (TDES) PDC Write Buffer End
-AT91C_TDES_RXBUFF EQU (0x1 << 3) ;- (TDES) PDC Read Buffer Full
-AT91C_TDES_TXBUFE EQU (0x1 << 4) ;- (TDES) PDC Write Buffer Empty
-AT91C_TDES_URAD EQU (0x1 << 8) ;- (TDES) Unspecified Register Access Detection
-// - -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register --------
-// - -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register --------
-// - -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register --------
-AT91C_TDES_URAT EQU (0x3 << 12) ;- (TDES) Unspecified Register Access Type Status
-AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (TDES) Input data register written during the data processing in PDC mode.
-AT91C_TDES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (TDES) Output data register read during the data processing.
-AT91C_TDES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (TDES) Mode register written during the data processing.
-AT91C_TDES_URAT_WO_REG_READ EQU (0x3 << 12) ;- (TDES) Write-only register read access.
-
-// - *****************************************************************************
-// - REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
-// - *****************************************************************************
-// - ========== Register definition for SYS peripheral ==========
-// - ========== Register definition for AIC peripheral ==========
-AT91C_AIC_IVR EQU (0xFFFFF100) ;- (AIC) IRQ Vector Register
-AT91C_AIC_SMR EQU (0xFFFFF000) ;- (AIC) Source Mode Register
-AT91C_AIC_FVR EQU (0xFFFFF104) ;- (AIC) FIQ Vector Register
-AT91C_AIC_DCR EQU (0xFFFFF138) ;- (AIC) Debug Control Register (Protect)
-AT91C_AIC_EOICR EQU (0xFFFFF130) ;- (AIC) End of Interrupt Command Register
-AT91C_AIC_SVR EQU (0xFFFFF080) ;- (AIC) Source Vector Register
-AT91C_AIC_FFSR EQU (0xFFFFF148) ;- (AIC) Fast Forcing Status Register
-AT91C_AIC_ICCR EQU (0xFFFFF128) ;- (AIC) Interrupt Clear Command Register
-AT91C_AIC_ISR EQU (0xFFFFF108) ;- (AIC) Interrupt Status Register
-AT91C_AIC_IMR EQU (0xFFFFF110) ;- (AIC) Interrupt Mask Register
-AT91C_AIC_IPR EQU (0xFFFFF10C) ;- (AIC) Interrupt Pending Register
-AT91C_AIC_FFER EQU (0xFFFFF140) ;- (AIC) Fast Forcing Enable Register
-AT91C_AIC_IECR EQU (0xFFFFF120) ;- (AIC) Interrupt Enable Command Register
-AT91C_AIC_ISCR EQU (0xFFFFF12C) ;- (AIC) Interrupt Set Command Register
-AT91C_AIC_FFDR EQU (0xFFFFF144) ;- (AIC) Fast Forcing Disable Register
-AT91C_AIC_CISR EQU (0xFFFFF114) ;- (AIC) Core Interrupt Status Register
-AT91C_AIC_IDCR EQU (0xFFFFF124) ;- (AIC) Interrupt Disable Command Register
-AT91C_AIC_SPU EQU (0xFFFFF134) ;- (AIC) Spurious Vector Register
-// - ========== Register definition for PDC_DBGU peripheral ==========
-AT91C_DBGU_TCR EQU (0xFFFFF30C) ;- (PDC_DBGU) Transmit Counter Register
-AT91C_DBGU_RNPR EQU (0xFFFFF310) ;- (PDC_DBGU) Receive Next Pointer Register
-AT91C_DBGU_TNPR EQU (0xFFFFF318) ;- (PDC_DBGU) Transmit Next Pointer Register
-AT91C_DBGU_TPR EQU (0xFFFFF308) ;- (PDC_DBGU) Transmit Pointer Register
-AT91C_DBGU_RPR EQU (0xFFFFF300) ;- (PDC_DBGU) Receive Pointer Register
-AT91C_DBGU_RCR EQU (0xFFFFF304) ;- (PDC_DBGU) Receive Counter Register
-AT91C_DBGU_RNCR EQU (0xFFFFF314) ;- (PDC_DBGU) Receive Next Counter Register
-AT91C_DBGU_PTCR EQU (0xFFFFF320) ;- (PDC_DBGU) PDC Transfer Control Register
-AT91C_DBGU_PTSR EQU (0xFFFFF324) ;- (PDC_DBGU) PDC Transfer Status Register
-AT91C_DBGU_TNCR EQU (0xFFFFF31C) ;- (PDC_DBGU) Transmit Next Counter Register
-// - ========== Register definition for DBGU peripheral ==========
-AT91C_DBGU_EXID EQU (0xFFFFF244) ;- (DBGU) Chip ID Extension Register
-AT91C_DBGU_BRGR EQU (0xFFFFF220) ;- (DBGU) Baud Rate Generator Register
-AT91C_DBGU_IDR EQU (0xFFFFF20C) ;- (DBGU) Interrupt Disable Register
-AT91C_DBGU_CSR EQU (0xFFFFF214) ;- (DBGU) Channel Status Register
-AT91C_DBGU_CIDR EQU (0xFFFFF240) ;- (DBGU) Chip ID Register
-AT91C_DBGU_MR EQU (0xFFFFF204) ;- (DBGU) Mode Register
-AT91C_DBGU_IMR EQU (0xFFFFF210) ;- (DBGU) Interrupt Mask Register
-AT91C_DBGU_CR EQU (0xFFFFF200) ;- (DBGU) Control Register
-AT91C_DBGU_FNTR EQU (0xFFFFF248) ;- (DBGU) Force NTRST Register
-AT91C_DBGU_THR EQU (0xFFFFF21C) ;- (DBGU) Transmitter Holding Register
-AT91C_DBGU_RHR EQU (0xFFFFF218) ;- (DBGU) Receiver Holding Register
-AT91C_DBGU_IER EQU (0xFFFFF208) ;- (DBGU) Interrupt Enable Register
-// - ========== Register definition for PIOA peripheral ==========
-AT91C_PIOA_ODR EQU (0xFFFFF414) ;- (PIOA) Output Disable Registerr
-AT91C_PIOA_SODR EQU (0xFFFFF430) ;- (PIOA) Set Output Data Register
-AT91C_PIOA_ISR EQU (0xFFFFF44C) ;- (PIOA) Interrupt Status Register
-AT91C_PIOA_ABSR EQU (0xFFFFF478) ;- (PIOA) AB Select Status Register
-AT91C_PIOA_IER EQU (0xFFFFF440) ;- (PIOA) Interrupt Enable Register
-AT91C_PIOA_PPUDR EQU (0xFFFFF460) ;- (PIOA) Pull-up Disable Register
-AT91C_PIOA_IMR EQU (0xFFFFF448) ;- (PIOA) Interrupt Mask Register
-AT91C_PIOA_PER EQU (0xFFFFF400) ;- (PIOA) PIO Enable Register
-AT91C_PIOA_IFDR EQU (0xFFFFF424) ;- (PIOA) Input Filter Disable Register
-AT91C_PIOA_OWDR EQU (0xFFFFF4A4) ;- (PIOA) Output Write Disable Register
-AT91C_PIOA_MDSR EQU (0xFFFFF458) ;- (PIOA) Multi-driver Status Register
-AT91C_PIOA_IDR EQU (0xFFFFF444) ;- (PIOA) Interrupt Disable Register
-AT91C_PIOA_ODSR EQU (0xFFFFF438) ;- (PIOA) Output Data Status Register
-AT91C_PIOA_PPUSR EQU (0xFFFFF468) ;- (PIOA) Pull-up Status Register
-AT91C_PIOA_OWSR EQU (0xFFFFF4A8) ;- (PIOA) Output Write Status Register
-AT91C_PIOA_BSR EQU (0xFFFFF474) ;- (PIOA) Select B Register
-AT91C_PIOA_OWER EQU (0xFFFFF4A0) ;- (PIOA) Output Write Enable Register
-AT91C_PIOA_IFER EQU (0xFFFFF420) ;- (PIOA) Input Filter Enable Register
-AT91C_PIOA_PDSR EQU (0xFFFFF43C) ;- (PIOA) Pin Data Status Register
-AT91C_PIOA_PPUER EQU (0xFFFFF464) ;- (PIOA) Pull-up Enable Register
-AT91C_PIOA_OSR EQU (0xFFFFF418) ;- (PIOA) Output Status Register
-AT91C_PIOA_ASR EQU (0xFFFFF470) ;- (PIOA) Select A Register
-AT91C_PIOA_MDDR EQU (0xFFFFF454) ;- (PIOA) Multi-driver Disable Register
-AT91C_PIOA_CODR EQU (0xFFFFF434) ;- (PIOA) Clear Output Data Register
-AT91C_PIOA_MDER EQU (0xFFFFF450) ;- (PIOA) Multi-driver Enable Register
-AT91C_PIOA_PDR EQU (0xFFFFF404) ;- (PIOA) PIO Disable Register
-AT91C_PIOA_IFSR EQU (0xFFFFF428) ;- (PIOA) Input Filter Status Register
-AT91C_PIOA_OER EQU (0xFFFFF410) ;- (PIOA) Output Enable Register
-AT91C_PIOA_PSR EQU (0xFFFFF408) ;- (PIOA) PIO Status Register
-// - ========== Register definition for PIOB peripheral ==========
-AT91C_PIOB_OWDR EQU (0xFFFFF6A4) ;- (PIOB) Output Write Disable Register
-AT91C_PIOB_MDER EQU (0xFFFFF650) ;- (PIOB) Multi-driver Enable Register
-AT91C_PIOB_PPUSR EQU (0xFFFFF668) ;- (PIOB) Pull-up Status Register
-AT91C_PIOB_IMR EQU (0xFFFFF648) ;- (PIOB) Interrupt Mask Register
-AT91C_PIOB_ASR EQU (0xFFFFF670) ;- (PIOB) Select A Register
-AT91C_PIOB_PPUDR EQU (0xFFFFF660) ;- (PIOB) Pull-up Disable Register
-AT91C_PIOB_PSR EQU (0xFFFFF608) ;- (PIOB) PIO Status Register
-AT91C_PIOB_IER EQU (0xFFFFF640) ;- (PIOB) Interrupt Enable Register
-AT91C_PIOB_CODR EQU (0xFFFFF634) ;- (PIOB) Clear Output Data Register
-AT91C_PIOB_OWER EQU (0xFFFFF6A0) ;- (PIOB) Output Write Enable Register
-AT91C_PIOB_ABSR EQU (0xFFFFF678) ;- (PIOB) AB Select Status Register
-AT91C_PIOB_IFDR EQU (0xFFFFF624) ;- (PIOB) Input Filter Disable Register
-AT91C_PIOB_PDSR EQU (0xFFFFF63C) ;- (PIOB) Pin Data Status Register
-AT91C_PIOB_IDR EQU (0xFFFFF644) ;- (PIOB) Interrupt Disable Register
-AT91C_PIOB_OWSR EQU (0xFFFFF6A8) ;- (PIOB) Output Write Status Register
-AT91C_PIOB_PDR EQU (0xFFFFF604) ;- (PIOB) PIO Disable Register
-AT91C_PIOB_ODR EQU (0xFFFFF614) ;- (PIOB) Output Disable Registerr
-AT91C_PIOB_IFSR EQU (0xFFFFF628) ;- (PIOB) Input Filter Status Register
-AT91C_PIOB_PPUER EQU (0xFFFFF664) ;- (PIOB) Pull-up Enable Register
-AT91C_PIOB_SODR EQU (0xFFFFF630) ;- (PIOB) Set Output Data Register
-AT91C_PIOB_ISR EQU (0xFFFFF64C) ;- (PIOB) Interrupt Status Register
-AT91C_PIOB_ODSR EQU (0xFFFFF638) ;- (PIOB) Output Data Status Register
-AT91C_PIOB_OSR EQU (0xFFFFF618) ;- (PIOB) Output Status Register
-AT91C_PIOB_MDSR EQU (0xFFFFF658) ;- (PIOB) Multi-driver Status Register
-AT91C_PIOB_IFER EQU (0xFFFFF620) ;- (PIOB) Input Filter Enable Register
-AT91C_PIOB_BSR EQU (0xFFFFF674) ;- (PIOB) Select B Register
-AT91C_PIOB_MDDR EQU (0xFFFFF654) ;- (PIOB) Multi-driver Disable Register
-AT91C_PIOB_OER EQU (0xFFFFF610) ;- (PIOB) Output Enable Register
-AT91C_PIOB_PER EQU (0xFFFFF600) ;- (PIOB) PIO Enable Register
-// - ========== Register definition for CKGR peripheral ==========
-AT91C_CKGR_MOR EQU (0xFFFFFC20) ;- (CKGR) Main Oscillator Register
-AT91C_CKGR_PLLR EQU (0xFFFFFC2C) ;- (CKGR) PLL Register
-AT91C_CKGR_MCFR EQU (0xFFFFFC24) ;- (CKGR) Main Clock Frequency Register
-// - ========== Register definition for PMC peripheral ==========
-AT91C_PMC_IDR EQU (0xFFFFFC64) ;- (PMC) Interrupt Disable Register
-AT91C_PMC_MOR EQU (0xFFFFFC20) ;- (PMC) Main Oscillator Register
-AT91C_PMC_PLLR EQU (0xFFFFFC2C) ;- (PMC) PLL Register
-AT91C_PMC_PCER EQU (0xFFFFFC10) ;- (PMC) Peripheral Clock Enable Register
-AT91C_PMC_PCKR EQU (0xFFFFFC40) ;- (PMC) Programmable Clock Register
-AT91C_PMC_MCKR EQU (0xFFFFFC30) ;- (PMC) Master Clock Register
-AT91C_PMC_SCDR EQU (0xFFFFFC04) ;- (PMC) System Clock Disable Register
-AT91C_PMC_PCDR EQU (0xFFFFFC14) ;- (PMC) Peripheral Clock Disable Register
-AT91C_PMC_SCSR EQU (0xFFFFFC08) ;- (PMC) System Clock Status Register
-AT91C_PMC_PCSR EQU (0xFFFFFC18) ;- (PMC) Peripheral Clock Status Register
-AT91C_PMC_MCFR EQU (0xFFFFFC24) ;- (PMC) Main Clock Frequency Register
-AT91C_PMC_SCER EQU (0xFFFFFC00) ;- (PMC) System Clock Enable Register
-AT91C_PMC_IMR EQU (0xFFFFFC6C) ;- (PMC) Interrupt Mask Register
-AT91C_PMC_IER EQU (0xFFFFFC60) ;- (PMC) Interrupt Enable Register
-AT91C_PMC_SR EQU (0xFFFFFC68) ;- (PMC) Status Register
-// - ========== Register definition for RSTC peripheral ==========
-AT91C_RSTC_RCR EQU (0xFFFFFD00) ;- (RSTC) Reset Control Register
-AT91C_RSTC_RMR EQU (0xFFFFFD08) ;- (RSTC) Reset Mode Register
-AT91C_RSTC_RSR EQU (0xFFFFFD04) ;- (RSTC) Reset Status Register
-// - ========== Register definition for RTTC peripheral ==========
-AT91C_RTTC_RTSR EQU (0xFFFFFD2C) ;- (RTTC) Real-time Status Register
-AT91C_RTTC_RTMR EQU (0xFFFFFD20) ;- (RTTC) Real-time Mode Register
-AT91C_RTTC_RTVR EQU (0xFFFFFD28) ;- (RTTC) Real-time Value Register
-AT91C_RTTC_RTAR EQU (0xFFFFFD24) ;- (RTTC) Real-time Alarm Register
-// - ========== Register definition for PITC peripheral ==========
-AT91C_PITC_PIVR EQU (0xFFFFFD38) ;- (PITC) Period Interval Value Register
-AT91C_PITC_PISR EQU (0xFFFFFD34) ;- (PITC) Period Interval Status Register
-AT91C_PITC_PIIR EQU (0xFFFFFD3C) ;- (PITC) Period Interval Image Register
-AT91C_PITC_PIMR EQU (0xFFFFFD30) ;- (PITC) Period Interval Mode Register
-// - ========== Register definition for WDTC peripheral ==========
-AT91C_WDTC_WDCR EQU (0xFFFFFD40) ;- (WDTC) Watchdog Control Register
-AT91C_WDTC_WDSR EQU (0xFFFFFD48) ;- (WDTC) Watchdog Status Register
-AT91C_WDTC_WDMR EQU (0xFFFFFD44) ;- (WDTC) Watchdog Mode Register
-// - ========== Register definition for VREG peripheral ==========
-AT91C_VREG_MR EQU (0xFFFFFD60) ;- (VREG) Voltage Regulator Mode Register
-// - ========== Register definition for MC peripheral ==========
-AT91C_MC_ASR EQU (0xFFFFFF04) ;- (MC) MC Abort Status Register
-AT91C_MC_RCR EQU (0xFFFFFF00) ;- (MC) MC Remap Control Register
-AT91C_MC_FCR EQU (0xFFFFFF64) ;- (MC) MC Flash Command Register
-AT91C_MC_AASR EQU (0xFFFFFF08) ;- (MC) MC Abort Address Status Register
-AT91C_MC_FSR EQU (0xFFFFFF68) ;- (MC) MC Flash Status Register
-AT91C_MC_FMR EQU (0xFFFFFF60) ;- (MC) MC Flash Mode Register
-// - ========== Register definition for PDC_SPI1 peripheral ==========
-AT91C_SPI1_PTCR EQU (0xFFFE4120) ;- (PDC_SPI1) PDC Transfer Control Register
-AT91C_SPI1_RPR EQU (0xFFFE4100) ;- (PDC_SPI1) Receive Pointer Register
-AT91C_SPI1_TNCR EQU (0xFFFE411C) ;- (PDC_SPI1) Transmit Next Counter Register
-AT91C_SPI1_TPR EQU (0xFFFE4108) ;- (PDC_SPI1) Transmit Pointer Register
-AT91C_SPI1_TNPR EQU (0xFFFE4118) ;- (PDC_SPI1) Transmit Next Pointer Register
-AT91C_SPI1_TCR EQU (0xFFFE410C) ;- (PDC_SPI1) Transmit Counter Register
-AT91C_SPI1_RCR EQU (0xFFFE4104) ;- (PDC_SPI1) Receive Counter Register
-AT91C_SPI1_RNPR EQU (0xFFFE4110) ;- (PDC_SPI1) Receive Next Pointer Register
-AT91C_SPI1_RNCR EQU (0xFFFE4114) ;- (PDC_SPI1) Receive Next Counter Register
-AT91C_SPI1_PTSR EQU (0xFFFE4124) ;- (PDC_SPI1) PDC Transfer Status Register
-// - ========== Register definition for SPI1 peripheral ==========
-AT91C_SPI1_IMR EQU (0xFFFE401C) ;- (SPI1) Interrupt Mask Register
-AT91C_SPI1_IER EQU (0xFFFE4014) ;- (SPI1) Interrupt Enable Register
-AT91C_SPI1_MR EQU (0xFFFE4004) ;- (SPI1) Mode Register
-AT91C_SPI1_RDR EQU (0xFFFE4008) ;- (SPI1) Receive Data Register
-AT91C_SPI1_IDR EQU (0xFFFE4018) ;- (SPI1) Interrupt Disable Register
-AT91C_SPI1_SR EQU (0xFFFE4010) ;- (SPI1) Status Register
-AT91C_SPI1_TDR EQU (0xFFFE400C) ;- (SPI1) Transmit Data Register
-AT91C_SPI1_CR EQU (0xFFFE4000) ;- (SPI1) Control Register
-AT91C_SPI1_CSR EQU (0xFFFE4030) ;- (SPI1) Chip Select Register
-// - ========== Register definition for PDC_SPI0 peripheral ==========
-AT91C_SPI0_PTCR EQU (0xFFFE0120) ;- (PDC_SPI0) PDC Transfer Control Register
-AT91C_SPI0_TPR EQU (0xFFFE0108) ;- (PDC_SPI0) Transmit Pointer Register
-AT91C_SPI0_TCR EQU (0xFFFE010C) ;- (PDC_SPI0) Transmit Counter Register
-AT91C_SPI0_RCR EQU (0xFFFE0104) ;- (PDC_SPI0) Receive Counter Register
-AT91C_SPI0_PTSR EQU (0xFFFE0124) ;- (PDC_SPI0) PDC Transfer Status Register
-AT91C_SPI0_RNPR EQU (0xFFFE0110) ;- (PDC_SPI0) Receive Next Pointer Register
-AT91C_SPI0_RPR EQU (0xFFFE0100) ;- (PDC_SPI0) Receive Pointer Register
-AT91C_SPI0_TNCR EQU (0xFFFE011C) ;- (PDC_SPI0) Transmit Next Counter Register
-AT91C_SPI0_RNCR EQU (0xFFFE0114) ;- (PDC_SPI0) Receive Next Counter Register
-AT91C_SPI0_TNPR EQU (0xFFFE0118) ;- (PDC_SPI0) Transmit Next Pointer Register
-// - ========== Register definition for SPI0 peripheral ==========
-AT91C_SPI0_IER EQU (0xFFFE0014) ;- (SPI0) Interrupt Enable Register
-AT91C_SPI0_SR EQU (0xFFFE0010) ;- (SPI0) Status Register
-AT91C_SPI0_IDR EQU (0xFFFE0018) ;- (SPI0) Interrupt Disable Register
-AT91C_SPI0_CR EQU (0xFFFE0000) ;- (SPI0) Control Register
-AT91C_SPI0_MR EQU (0xFFFE0004) ;- (SPI0) Mode Register
-AT91C_SPI0_IMR EQU (0xFFFE001C) ;- (SPI0) Interrupt Mask Register
-AT91C_SPI0_TDR EQU (0xFFFE000C) ;- (SPI0) Transmit Data Register
-AT91C_SPI0_RDR EQU (0xFFFE0008) ;- (SPI0) Receive Data Register
-AT91C_SPI0_CSR EQU (0xFFFE0030) ;- (SPI0) Chip Select Register
-// - ========== Register definition for PDC_US1 peripheral ==========
-AT91C_US1_RNCR EQU (0xFFFC4114) ;- (PDC_US1) Receive Next Counter Register
-AT91C_US1_PTCR EQU (0xFFFC4120) ;- (PDC_US1) PDC Transfer Control Register
-AT91C_US1_TCR EQU (0xFFFC410C) ;- (PDC_US1) Transmit Counter Register
-AT91C_US1_PTSR EQU (0xFFFC4124) ;- (PDC_US1) PDC Transfer Status Register
-AT91C_US1_TNPR EQU (0xFFFC4118) ;- (PDC_US1) Transmit Next Pointer Register
-AT91C_US1_RCR EQU (0xFFFC4104) ;- (PDC_US1) Receive Counter Register
-AT91C_US1_RNPR EQU (0xFFFC4110) ;- (PDC_US1) Receive Next Pointer Register
-AT91C_US1_RPR EQU (0xFFFC4100) ;- (PDC_US1) Receive Pointer Register
-AT91C_US1_TNCR EQU (0xFFFC411C) ;- (PDC_US1) Transmit Next Counter Register
-AT91C_US1_TPR EQU (0xFFFC4108) ;- (PDC_US1) Transmit Pointer Register
-// - ========== Register definition for US1 peripheral ==========
-AT91C_US1_IF EQU (0xFFFC404C) ;- (US1) IRDA_FILTER Register
-AT91C_US1_NER EQU (0xFFFC4044) ;- (US1) Nb Errors Register
-AT91C_US1_RTOR EQU (0xFFFC4024) ;- (US1) Receiver Time-out Register
-AT91C_US1_CSR EQU (0xFFFC4014) ;- (US1) Channel Status Register
-AT91C_US1_IDR EQU (0xFFFC400C) ;- (US1) Interrupt Disable Register
-AT91C_US1_IER EQU (0xFFFC4008) ;- (US1) Interrupt Enable Register
-AT91C_US1_THR EQU (0xFFFC401C) ;- (US1) Transmitter Holding Register
-AT91C_US1_TTGR EQU (0xFFFC4028) ;- (US1) Transmitter Time-guard Register
-AT91C_US1_RHR EQU (0xFFFC4018) ;- (US1) Receiver Holding Register
-AT91C_US1_BRGR EQU (0xFFFC4020) ;- (US1) Baud Rate Generator Register
-AT91C_US1_IMR EQU (0xFFFC4010) ;- (US1) Interrupt Mask Register
-AT91C_US1_FIDI EQU (0xFFFC4040) ;- (US1) FI_DI_Ratio Register
-AT91C_US1_CR EQU (0xFFFC4000) ;- (US1) Control Register
-AT91C_US1_MR EQU (0xFFFC4004) ;- (US1) Mode Register
-// - ========== Register definition for PDC_US0 peripheral ==========
-AT91C_US0_TNPR EQU (0xFFFC0118) ;- (PDC_US0) Transmit Next Pointer Register
-AT91C_US0_RNPR EQU (0xFFFC0110) ;- (PDC_US0) Receive Next Pointer Register
-AT91C_US0_TCR EQU (0xFFFC010C) ;- (PDC_US0) Transmit Counter Register
-AT91C_US0_PTCR EQU (0xFFFC0120) ;- (PDC_US0) PDC Transfer Control Register
-AT91C_US0_PTSR EQU (0xFFFC0124) ;- (PDC_US0) PDC Transfer Status Register
-AT91C_US0_TNCR EQU (0xFFFC011C) ;- (PDC_US0) Transmit Next Counter Register
-AT91C_US0_TPR EQU (0xFFFC0108) ;- (PDC_US0) Transmit Pointer Register
-AT91C_US0_RCR EQU (0xFFFC0104) ;- (PDC_US0) Receive Counter Register
-AT91C_US0_RPR EQU (0xFFFC0100) ;- (PDC_US0) Receive Pointer Register
-AT91C_US0_RNCR EQU (0xFFFC0114) ;- (PDC_US0) Receive Next Counter Register
-// - ========== Register definition for US0 peripheral ==========
-AT91C_US0_BRGR EQU (0xFFFC0020) ;- (US0) Baud Rate Generator Register
-AT91C_US0_NER EQU (0xFFFC0044) ;- (US0) Nb Errors Register
-AT91C_US0_CR EQU (0xFFFC0000) ;- (US0) Control Register
-AT91C_US0_IMR EQU (0xFFFC0010) ;- (US0) Interrupt Mask Register
-AT91C_US0_FIDI EQU (0xFFFC0040) ;- (US0) FI_DI_Ratio Register
-AT91C_US0_TTGR EQU (0xFFFC0028) ;- (US0) Transmitter Time-guard Register
-AT91C_US0_MR EQU (0xFFFC0004) ;- (US0) Mode Register
-AT91C_US0_RTOR EQU (0xFFFC0024) ;- (US0) Receiver Time-out Register
-AT91C_US0_CSR EQU (0xFFFC0014) ;- (US0) Channel Status Register
-AT91C_US0_RHR EQU (0xFFFC0018) ;- (US0) Receiver Holding Register
-AT91C_US0_IDR EQU (0xFFFC000C) ;- (US0) Interrupt Disable Register
-AT91C_US0_THR EQU (0xFFFC001C) ;- (US0) Transmitter Holding Register
-AT91C_US0_IF EQU (0xFFFC004C) ;- (US0) IRDA_FILTER Register
-AT91C_US0_IER EQU (0xFFFC0008) ;- (US0) Interrupt Enable Register
-// - ========== Register definition for PDC_SSC peripheral ==========
-AT91C_SSC_TNCR EQU (0xFFFD411C) ;- (PDC_SSC) Transmit Next Counter Register
-AT91C_SSC_RPR EQU (0xFFFD4100) ;- (PDC_SSC) Receive Pointer Register
-AT91C_SSC_RNCR EQU (0xFFFD4114) ;- (PDC_SSC) Receive Next Counter Register
-AT91C_SSC_TPR EQU (0xFFFD4108) ;- (PDC_SSC) Transmit Pointer Register
-AT91C_SSC_PTCR EQU (0xFFFD4120) ;- (PDC_SSC) PDC Transfer Control Register
-AT91C_SSC_TCR EQU (0xFFFD410C) ;- (PDC_SSC) Transmit Counter Register
-AT91C_SSC_RCR EQU (0xFFFD4104) ;- (PDC_SSC) Receive Counter Register
-AT91C_SSC_RNPR EQU (0xFFFD4110) ;- (PDC_SSC) Receive Next Pointer Register
-AT91C_SSC_TNPR EQU (0xFFFD4118) ;- (PDC_SSC) Transmit Next Pointer Register
-AT91C_SSC_PTSR EQU (0xFFFD4124) ;- (PDC_SSC) PDC Transfer Status Register
-// - ========== Register definition for SSC peripheral ==========
-AT91C_SSC_RHR EQU (0xFFFD4020) ;- (SSC) Receive Holding Register
-AT91C_SSC_RSHR EQU (0xFFFD4030) ;- (SSC) Receive Sync Holding Register
-AT91C_SSC_TFMR EQU (0xFFFD401C) ;- (SSC) Transmit Frame Mode Register
-AT91C_SSC_IDR EQU (0xFFFD4048) ;- (SSC) Interrupt Disable Register
-AT91C_SSC_THR EQU (0xFFFD4024) ;- (SSC) Transmit Holding Register
-AT91C_SSC_RCMR EQU (0xFFFD4010) ;- (SSC) Receive Clock ModeRegister
-AT91C_SSC_IER EQU (0xFFFD4044) ;- (SSC) Interrupt Enable Register
-AT91C_SSC_TSHR EQU (0xFFFD4034) ;- (SSC) Transmit Sync Holding Register
-AT91C_SSC_SR EQU (0xFFFD4040) ;- (SSC) Status Register
-AT91C_SSC_CMR EQU (0xFFFD4004) ;- (SSC) Clock Mode Register
-AT91C_SSC_TCMR EQU (0xFFFD4018) ;- (SSC) Transmit Clock Mode Register
-AT91C_SSC_CR EQU (0xFFFD4000) ;- (SSC) Control Register
-AT91C_SSC_IMR EQU (0xFFFD404C) ;- (SSC) Interrupt Mask Register
-AT91C_SSC_RFMR EQU (0xFFFD4014) ;- (SSC) Receive Frame Mode Register
-// - ========== Register definition for TWI peripheral ==========
-AT91C_TWI_IER EQU (0xFFFB8024) ;- (TWI) Interrupt Enable Register
-AT91C_TWI_CR EQU (0xFFFB8000) ;- (TWI) Control Register
-AT91C_TWI_SR EQU (0xFFFB8020) ;- (TWI) Status Register
-AT91C_TWI_IMR EQU (0xFFFB802C) ;- (TWI) Interrupt Mask Register
-AT91C_TWI_THR EQU (0xFFFB8034) ;- (TWI) Transmit Holding Register
-AT91C_TWI_IDR EQU (0xFFFB8028) ;- (TWI) Interrupt Disable Register
-AT91C_TWI_IADR EQU (0xFFFB800C) ;- (TWI) Internal Address Register
-AT91C_TWI_MMR EQU (0xFFFB8004) ;- (TWI) Master Mode Register
-AT91C_TWI_CWGR EQU (0xFFFB8010) ;- (TWI) Clock Waveform Generator Register
-AT91C_TWI_RHR EQU (0xFFFB8030) ;- (TWI) Receive Holding Register
-// - ========== Register definition for PWMC_CH3 peripheral ==========
-AT91C_PWMC_CH3_CUPDR EQU (0xFFFCC270) ;- (PWMC_CH3) Channel Update Register
-AT91C_PWMC_CH3_Reserved EQU (0xFFFCC274) ;- (PWMC_CH3) Reserved
-AT91C_PWMC_CH3_CPRDR EQU (0xFFFCC268) ;- (PWMC_CH3) Channel Period Register
-AT91C_PWMC_CH3_CDTYR EQU (0xFFFCC264) ;- (PWMC_CH3) Channel Duty Cycle Register
-AT91C_PWMC_CH3_CCNTR EQU (0xFFFCC26C) ;- (PWMC_CH3) Channel Counter Register
-AT91C_PWMC_CH3_CMR EQU (0xFFFCC260) ;- (PWMC_CH3) Channel Mode Register
-// - ========== Register definition for PWMC_CH2 peripheral ==========
-AT91C_PWMC_CH2_Reserved EQU (0xFFFCC254) ;- (PWMC_CH2) Reserved
-AT91C_PWMC_CH2_CMR EQU (0xFFFCC240) ;- (PWMC_CH2) Channel Mode Register
-AT91C_PWMC_CH2_CCNTR EQU (0xFFFCC24C) ;- (PWMC_CH2) Channel Counter Register
-AT91C_PWMC_CH2_CPRDR EQU (0xFFFCC248) ;- (PWMC_CH2) Channel Period Register
-AT91C_PWMC_CH2_CUPDR EQU (0xFFFCC250) ;- (PWMC_CH2) Channel Update Register
-AT91C_PWMC_CH2_CDTYR EQU (0xFFFCC244) ;- (PWMC_CH2) Channel Duty Cycle Register
-// - ========== Register definition for PWMC_CH1 peripheral ==========
-AT91C_PWMC_CH1_Reserved EQU (0xFFFCC234) ;- (PWMC_CH1) Reserved
-AT91C_PWMC_CH1_CUPDR EQU (0xFFFCC230) ;- (PWMC_CH1) Channel Update Register
-AT91C_PWMC_CH1_CPRDR EQU (0xFFFCC228) ;- (PWMC_CH1) Channel Period Register
-AT91C_PWMC_CH1_CCNTR EQU (0xFFFCC22C) ;- (PWMC_CH1) Channel Counter Register
-AT91C_PWMC_CH1_CDTYR EQU (0xFFFCC224) ;- (PWMC_CH1) Channel Duty Cycle Register
-AT91C_PWMC_CH1_CMR EQU (0xFFFCC220) ;- (PWMC_CH1) Channel Mode Register
-// - ========== Register definition for PWMC_CH0 peripheral ==========
-AT91C_PWMC_CH0_Reserved EQU (0xFFFCC214) ;- (PWMC_CH0) Reserved
-AT91C_PWMC_CH0_CPRDR EQU (0xFFFCC208) ;- (PWMC_CH0) Channel Period Register
-AT91C_PWMC_CH0_CDTYR EQU (0xFFFCC204) ;- (PWMC_CH0) Channel Duty Cycle Register
-AT91C_PWMC_CH0_CMR EQU (0xFFFCC200) ;- (PWMC_CH0) Channel Mode Register
-AT91C_PWMC_CH0_CUPDR EQU (0xFFFCC210) ;- (PWMC_CH0) Channel Update Register
-AT91C_PWMC_CH0_CCNTR EQU (0xFFFCC20C) ;- (PWMC_CH0) Channel Counter Register
-// - ========== Register definition for PWMC peripheral ==========
-AT91C_PWMC_IDR EQU (0xFFFCC014) ;- (PWMC) PWMC Interrupt Disable Register
-AT91C_PWMC_DIS EQU (0xFFFCC008) ;- (PWMC) PWMC Disable Register
-AT91C_PWMC_IER EQU (0xFFFCC010) ;- (PWMC) PWMC Interrupt Enable Register
-AT91C_PWMC_VR EQU (0xFFFCC0FC) ;- (PWMC) PWMC Version Register
-AT91C_PWMC_ISR EQU (0xFFFCC01C) ;- (PWMC) PWMC Interrupt Status Register
-AT91C_PWMC_SR EQU (0xFFFCC00C) ;- (PWMC) PWMC Status Register
-AT91C_PWMC_IMR EQU (0xFFFCC018) ;- (PWMC) PWMC Interrupt Mask Register
-AT91C_PWMC_MR EQU (0xFFFCC000) ;- (PWMC) PWMC Mode Register
-AT91C_PWMC_ENA EQU (0xFFFCC004) ;- (PWMC) PWMC Enable Register
-// - ========== Register definition for UDP peripheral ==========
-AT91C_UDP_IMR EQU (0xFFFB0018) ;- (UDP) Interrupt Mask Register
-AT91C_UDP_FADDR EQU (0xFFFB0008) ;- (UDP) Function Address Register
-AT91C_UDP_NUM EQU (0xFFFB0000) ;- (UDP) Frame Number Register
-AT91C_UDP_FDR EQU (0xFFFB0050) ;- (UDP) Endpoint FIFO Data Register
-AT91C_UDP_ISR EQU (0xFFFB001C) ;- (UDP) Interrupt Status Register
-AT91C_UDP_CSR EQU (0xFFFB0030) ;- (UDP) Endpoint Control and Status Register
-AT91C_UDP_IDR EQU (0xFFFB0014) ;- (UDP) Interrupt Disable Register
-AT91C_UDP_ICR EQU (0xFFFB0020) ;- (UDP) Interrupt Clear Register
-AT91C_UDP_RSTEP EQU (0xFFFB0028) ;- (UDP) Reset Endpoint Register
-AT91C_UDP_TXVC EQU (0xFFFB0074) ;- (UDP) Transceiver Control Register
-AT91C_UDP_GLBSTATE EQU (0xFFFB0004) ;- (UDP) Global State Register
-AT91C_UDP_IER EQU (0xFFFB0010) ;- (UDP) Interrupt Enable Register
-// - ========== Register definition for TC0 peripheral ==========
-AT91C_TC0_SR EQU (0xFFFA0020) ;- (TC0) Status Register
-AT91C_TC0_RC EQU (0xFFFA001C) ;- (TC0) Register C
-AT91C_TC0_RB EQU (0xFFFA0018) ;- (TC0) Register B
-AT91C_TC0_CCR EQU (0xFFFA0000) ;- (TC0) Channel Control Register
-AT91C_TC0_CMR EQU (0xFFFA0004) ;- (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
-AT91C_TC0_IER EQU (0xFFFA0024) ;- (TC0) Interrupt Enable Register
-AT91C_TC0_RA EQU (0xFFFA0014) ;- (TC0) Register A
-AT91C_TC0_IDR EQU (0xFFFA0028) ;- (TC0) Interrupt Disable Register
-AT91C_TC0_CV EQU (0xFFFA0010) ;- (TC0) Counter Value
-AT91C_TC0_IMR EQU (0xFFFA002C) ;- (TC0) Interrupt Mask Register
-// - ========== Register definition for TC1 peripheral ==========
-AT91C_TC1_RB EQU (0xFFFA0058) ;- (TC1) Register B
-AT91C_TC1_CCR EQU (0xFFFA0040) ;- (TC1) Channel Control Register
-AT91C_TC1_IER EQU (0xFFFA0064) ;- (TC1) Interrupt Enable Register
-AT91C_TC1_IDR EQU (0xFFFA0068) ;- (TC1) Interrupt Disable Register
-AT91C_TC1_SR EQU (0xFFFA0060) ;- (TC1) Status Register
-AT91C_TC1_CMR EQU (0xFFFA0044) ;- (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
-AT91C_TC1_RA EQU (0xFFFA0054) ;- (TC1) Register A
-AT91C_TC1_RC EQU (0xFFFA005C) ;- (TC1) Register C
-AT91C_TC1_IMR EQU (0xFFFA006C) ;- (TC1) Interrupt Mask Register
-AT91C_TC1_CV EQU (0xFFFA0050) ;- (TC1) Counter Value
-// - ========== Register definition for TC2 peripheral ==========
-AT91C_TC2_CMR EQU (0xFFFA0084) ;- (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
-AT91C_TC2_CCR EQU (0xFFFA0080) ;- (TC2) Channel Control Register
-AT91C_TC2_CV EQU (0xFFFA0090) ;- (TC2) Counter Value
-AT91C_TC2_RA EQU (0xFFFA0094) ;- (TC2) Register A
-AT91C_TC2_RB EQU (0xFFFA0098) ;- (TC2) Register B
-AT91C_TC2_IDR EQU (0xFFFA00A8) ;- (TC2) Interrupt Disable Register
-AT91C_TC2_IMR EQU (0xFFFA00AC) ;- (TC2) Interrupt Mask Register
-AT91C_TC2_RC EQU (0xFFFA009C) ;- (TC2) Register C
-AT91C_TC2_IER EQU (0xFFFA00A4) ;- (TC2) Interrupt Enable Register
-AT91C_TC2_SR EQU (0xFFFA00A0) ;- (TC2) Status Register
-// - ========== Register definition for TCB peripheral ==========
-AT91C_TCB_BMR EQU (0xFFFA00C4) ;- (TCB) TC Block Mode Register
-AT91C_TCB_BCR EQU (0xFFFA00C0) ;- (TCB) TC Block Control Register
-// - ========== Register definition for CAN_MB0 peripheral ==========
-AT91C_CAN_MB0_MDL EQU (0xFFFD0214) ;- (CAN_MB0) MailBox Data Low Register
-AT91C_CAN_MB0_MAM EQU (0xFFFD0204) ;- (CAN_MB0) MailBox Acceptance Mask Register
-AT91C_CAN_MB0_MCR EQU (0xFFFD021C) ;- (CAN_MB0) MailBox Control Register
-AT91C_CAN_MB0_MID EQU (0xFFFD0208) ;- (CAN_MB0) MailBox ID Register
-AT91C_CAN_MB0_MSR EQU (0xFFFD0210) ;- (CAN_MB0) MailBox Status Register
-AT91C_CAN_MB0_MFID EQU (0xFFFD020C) ;- (CAN_MB0) MailBox Family ID Register
-AT91C_CAN_MB0_MDH EQU (0xFFFD0218) ;- (CAN_MB0) MailBox Data High Register
-AT91C_CAN_MB0_MMR EQU (0xFFFD0200) ;- (CAN_MB0) MailBox Mode Register
-// - ========== Register definition for CAN_MB1 peripheral ==========
-AT91C_CAN_MB1_MDL EQU (0xFFFD0234) ;- (CAN_MB1) MailBox Data Low Register
-AT91C_CAN_MB1_MID EQU (0xFFFD0228) ;- (CAN_MB1) MailBox ID Register
-AT91C_CAN_MB1_MMR EQU (0xFFFD0220) ;- (CAN_MB1) MailBox Mode Register
-AT91C_CAN_MB1_MSR EQU (0xFFFD0230) ;- (CAN_MB1) MailBox Status Register
-AT91C_CAN_MB1_MAM EQU (0xFFFD0224) ;- (CAN_MB1) MailBox Acceptance Mask Register
-AT91C_CAN_MB1_MDH EQU (0xFFFD0238) ;- (CAN_MB1) MailBox Data High Register
-AT91C_CAN_MB1_MCR EQU (0xFFFD023C) ;- (CAN_MB1) MailBox Control Register
-AT91C_CAN_MB1_MFID EQU (0xFFFD022C) ;- (CAN_MB1) MailBox Family ID Register
-// - ========== Register definition for CAN_MB2 peripheral ==========
-AT91C_CAN_MB2_MCR EQU (0xFFFD025C) ;- (CAN_MB2) MailBox Control Register
-AT91C_CAN_MB2_MDH EQU (0xFFFD0258) ;- (CAN_MB2) MailBox Data High Register
-AT91C_CAN_MB2_MID EQU (0xFFFD0248) ;- (CAN_MB2) MailBox ID Register
-AT91C_CAN_MB2_MDL EQU (0xFFFD0254) ;- (CAN_MB2) MailBox Data Low Register
-AT91C_CAN_MB2_MMR EQU (0xFFFD0240) ;- (CAN_MB2) MailBox Mode Register
-AT91C_CAN_MB2_MAM EQU (0xFFFD0244) ;- (CAN_MB2) MailBox Acceptance Mask Register
-AT91C_CAN_MB2_MFID EQU (0xFFFD024C) ;- (CAN_MB2) MailBox Family ID Register
-AT91C_CAN_MB2_MSR EQU (0xFFFD0250) ;- (CAN_MB2) MailBox Status Register
-// - ========== Register definition for CAN_MB3 peripheral ==========
-AT91C_CAN_MB3_MFID EQU (0xFFFD026C) ;- (CAN_MB3) MailBox Family ID Register
-AT91C_CAN_MB3_MAM EQU (0xFFFD0264) ;- (CAN_MB3) MailBox Acceptance Mask Register
-AT91C_CAN_MB3_MID EQU (0xFFFD0268) ;- (CAN_MB3) MailBox ID Register
-AT91C_CAN_MB3_MCR EQU (0xFFFD027C) ;- (CAN_MB3) MailBox Control Register
-AT91C_CAN_MB3_MMR EQU (0xFFFD0260) ;- (CAN_MB3) MailBox Mode Register
-AT91C_CAN_MB3_MSR EQU (0xFFFD0270) ;- (CAN_MB3) MailBox Status Register
-AT91C_CAN_MB3_MDL EQU (0xFFFD0274) ;- (CAN_MB3) MailBox Data Low Register
-AT91C_CAN_MB3_MDH EQU (0xFFFD0278) ;- (CAN_MB3) MailBox Data High Register
-// - ========== Register definition for CAN_MB4 peripheral ==========
-AT91C_CAN_MB4_MID EQU (0xFFFD0288) ;- (CAN_MB4) MailBox ID Register
-AT91C_CAN_MB4_MMR EQU (0xFFFD0280) ;- (CAN_MB4) MailBox Mode Register
-AT91C_CAN_MB4_MDH EQU (0xFFFD0298) ;- (CAN_MB4) MailBox Data High Register
-AT91C_CAN_MB4_MFID EQU (0xFFFD028C) ;- (CAN_MB4) MailBox Family ID Register
-AT91C_CAN_MB4_MSR EQU (0xFFFD0290) ;- (CAN_MB4) MailBox Status Register
-AT91C_CAN_MB4_MCR EQU (0xFFFD029C) ;- (CAN_MB4) MailBox Control Register
-AT91C_CAN_MB4_MDL EQU (0xFFFD0294) ;- (CAN_MB4) MailBox Data Low Register
-AT91C_CAN_MB4_MAM EQU (0xFFFD0284) ;- (CAN_MB4) MailBox Acceptance Mask Register
-// - ========== Register definition for CAN_MB5 peripheral ==========
-AT91C_CAN_MB5_MSR EQU (0xFFFD02B0) ;- (CAN_MB5) MailBox Status Register
-AT91C_CAN_MB5_MCR EQU (0xFFFD02BC) ;- (CAN_MB5) MailBox Control Register
-AT91C_CAN_MB5_MFID EQU (0xFFFD02AC) ;- (CAN_MB5) MailBox Family ID Register
-AT91C_CAN_MB5_MDH EQU (0xFFFD02B8) ;- (CAN_MB5) MailBox Data High Register
-AT91C_CAN_MB5_MID EQU (0xFFFD02A8) ;- (CAN_MB5) MailBox ID Register
-AT91C_CAN_MB5_MMR EQU (0xFFFD02A0) ;- (CAN_MB5) MailBox Mode Register
-AT91C_CAN_MB5_MDL EQU (0xFFFD02B4) ;- (CAN_MB5) MailBox Data Low Register
-AT91C_CAN_MB5_MAM EQU (0xFFFD02A4) ;- (CAN_MB5) MailBox Acceptance Mask Register
-// - ========== Register definition for CAN_MB6 peripheral ==========
-AT91C_CAN_MB6_MFID EQU (0xFFFD02CC) ;- (CAN_MB6) MailBox Family ID Register
-AT91C_CAN_MB6_MID EQU (0xFFFD02C8) ;- (CAN_MB6) MailBox ID Register
-AT91C_CAN_MB6_MAM EQU (0xFFFD02C4) ;- (CAN_MB6) MailBox Acceptance Mask Register
-AT91C_CAN_MB6_MSR EQU (0xFFFD02D0) ;- (CAN_MB6) MailBox Status Register
-AT91C_CAN_MB6_MDL EQU (0xFFFD02D4) ;- (CAN_MB6) MailBox Data Low Register
-AT91C_CAN_MB6_MCR EQU (0xFFFD02DC) ;- (CAN_MB6) MailBox Control Register
-AT91C_CAN_MB6_MDH EQU (0xFFFD02D8) ;- (CAN_MB6) MailBox Data High Register
-AT91C_CAN_MB6_MMR EQU (0xFFFD02C0) ;- (CAN_MB6) MailBox Mode Register
-// - ========== Register definition for CAN_MB7 peripheral ==========
-AT91C_CAN_MB7_MCR EQU (0xFFFD02FC) ;- (CAN_MB7) MailBox Control Register
-AT91C_CAN_MB7_MDH EQU (0xFFFD02F8) ;- (CAN_MB7) MailBox Data High Register
-AT91C_CAN_MB7_MFID EQU (0xFFFD02EC) ;- (CAN_MB7) MailBox Family ID Register
-AT91C_CAN_MB7_MDL EQU (0xFFFD02F4) ;- (CAN_MB7) MailBox Data Low Register
-AT91C_CAN_MB7_MID EQU (0xFFFD02E8) ;- (CAN_MB7) MailBox ID Register
-AT91C_CAN_MB7_MMR EQU (0xFFFD02E0) ;- (CAN_MB7) MailBox Mode Register
-AT91C_CAN_MB7_MAM EQU (0xFFFD02E4) ;- (CAN_MB7) MailBox Acceptance Mask Register
-AT91C_CAN_MB7_MSR EQU (0xFFFD02F0) ;- (CAN_MB7) MailBox Status Register
-// - ========== Register definition for CAN peripheral ==========
-AT91C_CAN_TCR EQU (0xFFFD0024) ;- (CAN) Transfer Command Register
-AT91C_CAN_IMR EQU (0xFFFD000C) ;- (CAN) Interrupt Mask Register
-AT91C_CAN_IER EQU (0xFFFD0004) ;- (CAN) Interrupt Enable Register
-AT91C_CAN_ECR EQU (0xFFFD0020) ;- (CAN) Error Counter Register
-AT91C_CAN_TIMESTP EQU (0xFFFD001C) ;- (CAN) Time Stamp Register
-AT91C_CAN_MR EQU (0xFFFD0000) ;- (CAN) Mode Register
-AT91C_CAN_IDR EQU (0xFFFD0008) ;- (CAN) Interrupt Disable Register
-AT91C_CAN_ACR EQU (0xFFFD0028) ;- (CAN) Abort Command Register
-AT91C_CAN_TIM EQU (0xFFFD0018) ;- (CAN) Timer Register
-AT91C_CAN_SR EQU (0xFFFD0010) ;- (CAN) Status Register
-AT91C_CAN_BR EQU (0xFFFD0014) ;- (CAN) Baudrate Register
-AT91C_CAN_VR EQU (0xFFFD00FC) ;- (CAN) Version Register
-// - ========== Register definition for EMAC peripheral ==========
-AT91C_EMAC_ISR EQU (0xFFFDC024) ;- (EMAC) Interrupt Status Register
-AT91C_EMAC_SA4H EQU (0xFFFDC0B4) ;- (EMAC) Specific Address 4 Top, Last 2 bytes
-AT91C_EMAC_SA1L EQU (0xFFFDC098) ;- (EMAC) Specific Address 1 Bottom, First 4 bytes
-AT91C_EMAC_ELE EQU (0xFFFDC078) ;- (EMAC) Excessive Length Errors Register
-AT91C_EMAC_LCOL EQU (0xFFFDC05C) ;- (EMAC) Late Collision Register
-AT91C_EMAC_RLE EQU (0xFFFDC088) ;- (EMAC) Receive Length Field Mismatch Register
-AT91C_EMAC_WOL EQU (0xFFFDC0C4) ;- (EMAC) Wake On LAN Register
-AT91C_EMAC_DTF EQU (0xFFFDC058) ;- (EMAC) Deferred Transmission Frame Register
-AT91C_EMAC_TUND EQU (0xFFFDC064) ;- (EMAC) Transmit Underrun Error Register
-AT91C_EMAC_NCR EQU (0xFFFDC000) ;- (EMAC) Network Control Register
-AT91C_EMAC_SA4L EQU (0xFFFDC0B0) ;- (EMAC) Specific Address 4 Bottom, First 4 bytes
-AT91C_EMAC_RSR EQU (0xFFFDC020) ;- (EMAC) Receive Status Register
-AT91C_EMAC_SA3L EQU (0xFFFDC0A8) ;- (EMAC) Specific Address 3 Bottom, First 4 bytes
-AT91C_EMAC_TSR EQU (0xFFFDC014) ;- (EMAC) Transmit Status Register
-AT91C_EMAC_IDR EQU (0xFFFDC02C) ;- (EMAC) Interrupt Disable Register
-AT91C_EMAC_RSE EQU (0xFFFDC074) ;- (EMAC) Receive Symbol Errors Register
-AT91C_EMAC_ECOL EQU (0xFFFDC060) ;- (EMAC) Excessive Collision Register
-AT91C_EMAC_TID EQU (0xFFFDC0B8) ;- (EMAC) Type ID Checking Register
-AT91C_EMAC_HRB EQU (0xFFFDC090) ;- (EMAC) Hash Address Bottom[31:0]
-AT91C_EMAC_TBQP EQU (0xFFFDC01C) ;- (EMAC) Transmit Buffer Queue Pointer
-AT91C_EMAC_USRIO EQU (0xFFFDC0C0) ;- (EMAC) USER Input/Output Register
-AT91C_EMAC_PTR EQU (0xFFFDC038) ;- (EMAC) Pause Time Register
-AT91C_EMAC_SA2H EQU (0xFFFDC0A4) ;- (EMAC) Specific Address 2 Top, Last 2 bytes
-AT91C_EMAC_ROV EQU (0xFFFDC070) ;- (EMAC) Receive Overrun Errors Register
-AT91C_EMAC_ALE EQU (0xFFFDC054) ;- (EMAC) Alignment Error Register
-AT91C_EMAC_RJA EQU (0xFFFDC07C) ;- (EMAC) Receive Jabbers Register
-AT91C_EMAC_RBQP EQU (0xFFFDC018) ;- (EMAC) Receive Buffer Queue Pointer
-AT91C_EMAC_TPF EQU (0xFFFDC08C) ;- (EMAC) Transmitted Pause Frames Register
-AT91C_EMAC_NCFGR EQU (0xFFFDC004) ;- (EMAC) Network Configuration Register
-AT91C_EMAC_HRT EQU (0xFFFDC094) ;- (EMAC) Hash Address Top[63:32]
-AT91C_EMAC_USF EQU (0xFFFDC080) ;- (EMAC) Undersize Frames Register
-AT91C_EMAC_FCSE EQU (0xFFFDC050) ;- (EMAC) Frame Check Sequence Error Register
-AT91C_EMAC_TPQ EQU (0xFFFDC0BC) ;- (EMAC) Transmit Pause Quantum Register
-AT91C_EMAC_MAN EQU (0xFFFDC034) ;- (EMAC) PHY Maintenance Register
-AT91C_EMAC_FTO EQU (0xFFFDC040) ;- (EMAC) Frames Transmitted OK Register
-AT91C_EMAC_REV EQU (0xFFFDC0FC) ;- (EMAC) Revision Register
-AT91C_EMAC_IMR EQU (0xFFFDC030) ;- (EMAC) Interrupt Mask Register
-AT91C_EMAC_SCF EQU (0xFFFDC044) ;- (EMAC) Single Collision Frame Register
-AT91C_EMAC_PFR EQU (0xFFFDC03C) ;- (EMAC) Pause Frames received Register
-AT91C_EMAC_MCF EQU (0xFFFDC048) ;- (EMAC) Multiple Collision Frame Register
-AT91C_EMAC_NSR EQU (0xFFFDC008) ;- (EMAC) Network Status Register
-AT91C_EMAC_SA2L EQU (0xFFFDC0A0) ;- (EMAC) Specific Address 2 Bottom, First 4 bytes
-AT91C_EMAC_FRO EQU (0xFFFDC04C) ;- (EMAC) Frames Received OK Register
-AT91C_EMAC_IER EQU (0xFFFDC028) ;- (EMAC) Interrupt Enable Register
-AT91C_EMAC_SA1H EQU (0xFFFDC09C) ;- (EMAC) Specific Address 1 Top, Last 2 bytes
-AT91C_EMAC_CSE EQU (0xFFFDC068) ;- (EMAC) Carrier Sense Error Register
-AT91C_EMAC_SA3H EQU (0xFFFDC0AC) ;- (EMAC) Specific Address 3 Top, Last 2 bytes
-AT91C_EMAC_RRE EQU (0xFFFDC06C) ;- (EMAC) Receive Ressource Error Register
-AT91C_EMAC_STE EQU (0xFFFDC084) ;- (EMAC) SQE Test Error Register
-// - ========== Register definition for PDC_ADC peripheral ==========
-AT91C_ADC_PTSR EQU (0xFFFD8124) ;- (PDC_ADC) PDC Transfer Status Register
-AT91C_ADC_PTCR EQU (0xFFFD8120) ;- (PDC_ADC) PDC Transfer Control Register
-AT91C_ADC_TNPR EQU (0xFFFD8118) ;- (PDC_ADC) Transmit Next Pointer Register
-AT91C_ADC_TNCR EQU (0xFFFD811C) ;- (PDC_ADC) Transmit Next Counter Register
-AT91C_ADC_RNPR EQU (0xFFFD8110) ;- (PDC_ADC) Receive Next Pointer Register
-AT91C_ADC_RNCR EQU (0xFFFD8114) ;- (PDC_ADC) Receive Next Counter Register
-AT91C_ADC_RPR EQU (0xFFFD8100) ;- (PDC_ADC) Receive Pointer Register
-AT91C_ADC_TCR EQU (0xFFFD810C) ;- (PDC_ADC) Transmit Counter Register
-AT91C_ADC_TPR EQU (0xFFFD8108) ;- (PDC_ADC) Transmit Pointer Register
-AT91C_ADC_RCR EQU (0xFFFD8104) ;- (PDC_ADC) Receive Counter Register
-// - ========== Register definition for ADC peripheral ==========
-AT91C_ADC_CDR2 EQU (0xFFFD8038) ;- (ADC) ADC Channel Data Register 2
-AT91C_ADC_CDR3 EQU (0xFFFD803C) ;- (ADC) ADC Channel Data Register 3
-AT91C_ADC_CDR0 EQU (0xFFFD8030) ;- (ADC) ADC Channel Data Register 0
-AT91C_ADC_CDR5 EQU (0xFFFD8044) ;- (ADC) ADC Channel Data Register 5
-AT91C_ADC_CHDR EQU (0xFFFD8014) ;- (ADC) ADC Channel Disable Register
-AT91C_ADC_SR EQU (0xFFFD801C) ;- (ADC) ADC Status Register
-AT91C_ADC_CDR4 EQU (0xFFFD8040) ;- (ADC) ADC Channel Data Register 4
-AT91C_ADC_CDR1 EQU (0xFFFD8034) ;- (ADC) ADC Channel Data Register 1
-AT91C_ADC_LCDR EQU (0xFFFD8020) ;- (ADC) ADC Last Converted Data Register
-AT91C_ADC_IDR EQU (0xFFFD8028) ;- (ADC) ADC Interrupt Disable Register
-AT91C_ADC_CR EQU (0xFFFD8000) ;- (ADC) ADC Control Register
-AT91C_ADC_CDR7 EQU (0xFFFD804C) ;- (ADC) ADC Channel Data Register 7
-AT91C_ADC_CDR6 EQU (0xFFFD8048) ;- (ADC) ADC Channel Data Register 6
-AT91C_ADC_IER EQU (0xFFFD8024) ;- (ADC) ADC Interrupt Enable Register
-AT91C_ADC_CHER EQU (0xFFFD8010) ;- (ADC) ADC Channel Enable Register
-AT91C_ADC_CHSR EQU (0xFFFD8018) ;- (ADC) ADC Channel Status Register
-AT91C_ADC_MR EQU (0xFFFD8004) ;- (ADC) ADC Mode Register
-AT91C_ADC_IMR EQU (0xFFFD802C) ;- (ADC) ADC Interrupt Mask Register
-// - ========== Register definition for PDC_AES peripheral ==========
-AT91C_AES_TPR EQU (0xFFFA4108) ;- (PDC_AES) Transmit Pointer Register
-AT91C_AES_PTCR EQU (0xFFFA4120) ;- (PDC_AES) PDC Transfer Control Register
-AT91C_AES_RNPR EQU (0xFFFA4110) ;- (PDC_AES) Receive Next Pointer Register
-AT91C_AES_TNCR EQU (0xFFFA411C) ;- (PDC_AES) Transmit Next Counter Register
-AT91C_AES_TCR EQU (0xFFFA410C) ;- (PDC_AES) Transmit Counter Register
-AT91C_AES_RCR EQU (0xFFFA4104) ;- (PDC_AES) Receive Counter Register
-AT91C_AES_RNCR EQU (0xFFFA4114) ;- (PDC_AES) Receive Next Counter Register
-AT91C_AES_TNPR EQU (0xFFFA4118) ;- (PDC_AES) Transmit Next Pointer Register
-AT91C_AES_RPR EQU (0xFFFA4100) ;- (PDC_AES) Receive Pointer Register
-AT91C_AES_PTSR EQU (0xFFFA4124) ;- (PDC_AES) PDC Transfer Status Register
-// - ========== Register definition for AES peripheral ==========
-AT91C_AES_IVxR EQU (0xFFFA4060) ;- (AES) Initialization Vector x Register
-AT91C_AES_MR EQU (0xFFFA4004) ;- (AES) Mode Register
-AT91C_AES_VR EQU (0xFFFA40FC) ;- (AES) AES Version Register
-AT91C_AES_ODATAxR EQU (0xFFFA4050) ;- (AES) Output Data x Register
-AT91C_AES_IDATAxR EQU (0xFFFA4040) ;- (AES) Input Data x Register
-AT91C_AES_CR EQU (0xFFFA4000) ;- (AES) Control Register
-AT91C_AES_IDR EQU (0xFFFA4014) ;- (AES) Interrupt Disable Register
-AT91C_AES_IMR EQU (0xFFFA4018) ;- (AES) Interrupt Mask Register
-AT91C_AES_IER EQU (0xFFFA4010) ;- (AES) Interrupt Enable Register
-AT91C_AES_KEYWxR EQU (0xFFFA4020) ;- (AES) Key Word x Register
-AT91C_AES_ISR EQU (0xFFFA401C) ;- (AES) Interrupt Status Register
-// - ========== Register definition for PDC_TDES peripheral ==========
-AT91C_TDES_RNCR EQU (0xFFFA8114) ;- (PDC_TDES) Receive Next Counter Register
-AT91C_TDES_TCR EQU (0xFFFA810C) ;- (PDC_TDES) Transmit Counter Register
-AT91C_TDES_RCR EQU (0xFFFA8104) ;- (PDC_TDES) Receive Counter Register
-AT91C_TDES_TNPR EQU (0xFFFA8118) ;- (PDC_TDES) Transmit Next Pointer Register
-AT91C_TDES_RNPR EQU (0xFFFA8110) ;- (PDC_TDES) Receive Next Pointer Register
-AT91C_TDES_RPR EQU (0xFFFA8100) ;- (PDC_TDES) Receive Pointer Register
-AT91C_TDES_TNCR EQU (0xFFFA811C) ;- (PDC_TDES) Transmit Next Counter Register
-AT91C_TDES_TPR EQU (0xFFFA8108) ;- (PDC_TDES) Transmit Pointer Register
-AT91C_TDES_PTSR EQU (0xFFFA8124) ;- (PDC_TDES) PDC Transfer Status Register
-AT91C_TDES_PTCR EQU (0xFFFA8120) ;- (PDC_TDES) PDC Transfer Control Register
-// - ========== Register definition for TDES peripheral ==========
-AT91C_TDES_KEY2WxR EQU (0xFFFA8028) ;- (TDES) Key 2 Word x Register
-AT91C_TDES_KEY3WxR EQU (0xFFFA8030) ;- (TDES) Key 3 Word x Register
-AT91C_TDES_IDR EQU (0xFFFA8014) ;- (TDES) Interrupt Disable Register
-AT91C_TDES_VR EQU (0xFFFA80FC) ;- (TDES) TDES Version Register
-AT91C_TDES_IVxR EQU (0xFFFA8060) ;- (TDES) Initialization Vector x Register
-AT91C_TDES_ODATAxR EQU (0xFFFA8050) ;- (TDES) Output Data x Register
-AT91C_TDES_IMR EQU (0xFFFA8018) ;- (TDES) Interrupt Mask Register
-AT91C_TDES_MR EQU (0xFFFA8004) ;- (TDES) Mode Register
-AT91C_TDES_CR EQU (0xFFFA8000) ;- (TDES) Control Register
-AT91C_TDES_IER EQU (0xFFFA8010) ;- (TDES) Interrupt Enable Register
-AT91C_TDES_ISR EQU (0xFFFA801C) ;- (TDES) Interrupt Status Register
-AT91C_TDES_IDATAxR EQU (0xFFFA8040) ;- (TDES) Input Data x Register
-AT91C_TDES_KEY1WxR EQU (0xFFFA8020) ;- (TDES) Key 1 Word x Register
-
-// - *****************************************************************************
-// - PIO DEFINITIONS FOR AT91SAM7X256
-// - *****************************************************************************
-AT91C_PIO_PA0 EQU (1 << 0) ;- Pin Controlled by PA0
-AT91C_PA0_RXD0 EQU (AT91C_PIO_PA0) ;- USART 0 Receive Data
-AT91C_PIO_PA1 EQU (1 << 1) ;- Pin Controlled by PA1
-AT91C_PA1_TXD0 EQU (AT91C_PIO_PA1) ;- USART 0 Transmit Data
-AT91C_PIO_PA10 EQU (1 << 10) ;- Pin Controlled by PA10
-AT91C_PA10_TWD EQU (AT91C_PIO_PA10) ;- TWI Two-wire Serial Data
-AT91C_PIO_PA11 EQU (1 << 11) ;- Pin Controlled by PA11
-AT91C_PA11_TWCK EQU (AT91C_PIO_PA11) ;- TWI Two-wire Serial Clock
-AT91C_PIO_PA12 EQU (1 << 12) ;- Pin Controlled by PA12
-AT91C_PA12_NPCS00 EQU (AT91C_PIO_PA12) ;- SPI 0 Peripheral Chip Select 0
-AT91C_PIO_PA13 EQU (1 << 13) ;- Pin Controlled by PA13
-AT91C_PA13_NPCS01 EQU (AT91C_PIO_PA13) ;- SPI 0 Peripheral Chip Select 1
-AT91C_PA13_PCK1 EQU (AT91C_PIO_PA13) ;- PMC Programmable Clock Output 1
-AT91C_PIO_PA14 EQU (1 << 14) ;- Pin Controlled by PA14
-AT91C_PA14_NPCS02 EQU (AT91C_PIO_PA14) ;- SPI 0 Peripheral Chip Select 2
-AT91C_PA14_IRQ1 EQU (AT91C_PIO_PA14) ;- External Interrupt 1
-AT91C_PIO_PA15 EQU (1 << 15) ;- Pin Controlled by PA15
-AT91C_PA15_NPCS03 EQU (AT91C_PIO_PA15) ;- SPI 0 Peripheral Chip Select 3
-AT91C_PA15_TCLK2 EQU (AT91C_PIO_PA15) ;- Timer Counter 2 external clock input
-AT91C_PIO_PA16 EQU (1 << 16) ;- Pin Controlled by PA16
-AT91C_PA16_MISO0 EQU (AT91C_PIO_PA16) ;- SPI 0 Master In Slave
-AT91C_PIO_PA17 EQU (1 << 17) ;- Pin Controlled by PA17
-AT91C_PA17_MOSI0 EQU (AT91C_PIO_PA17) ;- SPI 0 Master Out Slave
-AT91C_PIO_PA18 EQU (1 << 18) ;- Pin Controlled by PA18
-AT91C_PA18_SPCK0 EQU (AT91C_PIO_PA18) ;- SPI 0 Serial Clock
-AT91C_PIO_PA19 EQU (1 << 19) ;- Pin Controlled by PA19
-AT91C_PA19_CANRX EQU (AT91C_PIO_PA19) ;- CAN Receive
-AT91C_PIO_PA2 EQU (1 << 2) ;- Pin Controlled by PA2
-AT91C_PA2_SCK0 EQU (AT91C_PIO_PA2) ;- USART 0 Serial Clock
-AT91C_PA2_NPCS11 EQU (AT91C_PIO_PA2) ;- SPI 1 Peripheral Chip Select 1
-AT91C_PIO_PA20 EQU (1 << 20) ;- Pin Controlled by PA20
-AT91C_PA20_CANTX EQU (AT91C_PIO_PA20) ;- CAN Transmit
-AT91C_PIO_PA21 EQU (1 << 21) ;- Pin Controlled by PA21
-AT91C_PA21_TF EQU (AT91C_PIO_PA21) ;- SSC Transmit Frame Sync
-AT91C_PA21_NPCS10 EQU (AT91C_PIO_PA21) ;- SPI 1 Peripheral Chip Select 0
-AT91C_PIO_PA22 EQU (1 << 22) ;- Pin Controlled by PA22
-AT91C_PA22_TK EQU (AT91C_PIO_PA22) ;- SSC Transmit Clock
-AT91C_PA22_SPCK1 EQU (AT91C_PIO_PA22) ;- SPI 1 Serial Clock
-AT91C_PIO_PA23 EQU (1 << 23) ;- Pin Controlled by PA23
-AT91C_PA23_TD EQU (AT91C_PIO_PA23) ;- SSC Transmit data
-AT91C_PA23_MOSI1 EQU (AT91C_PIO_PA23) ;- SPI 1 Master Out Slave
-AT91C_PIO_PA24 EQU (1 << 24) ;- Pin Controlled by PA24
-AT91C_PA24_RD EQU (AT91C_PIO_PA24) ;- SSC Receive Data
-AT91C_PA24_MISO1 EQU (AT91C_PIO_PA24) ;- SPI 1 Master In Slave
-AT91C_PIO_PA25 EQU (1 << 25) ;- Pin Controlled by PA25
-AT91C_PA25_RK EQU (AT91C_PIO_PA25) ;- SSC Receive Clock
-AT91C_PA25_NPCS11 EQU (AT91C_PIO_PA25) ;- SPI 1 Peripheral Chip Select 1
-AT91C_PIO_PA26 EQU (1 << 26) ;- Pin Controlled by PA26
-AT91C_PA26_RF EQU (AT91C_PIO_PA26) ;- SSC Receive Frame Sync
-AT91C_PA26_NPCS12 EQU (AT91C_PIO_PA26) ;- SPI 1 Peripheral Chip Select 2
-AT91C_PIO_PA27 EQU (1 << 27) ;- Pin Controlled by PA27
-AT91C_PA27_DRXD EQU (AT91C_PIO_PA27) ;- DBGU Debug Receive Data
-AT91C_PA27_PCK3 EQU (AT91C_PIO_PA27) ;- PMC Programmable Clock Output 3
-AT91C_PIO_PA28 EQU (1 << 28) ;- Pin Controlled by PA28
-AT91C_PA28_DTXD EQU (AT91C_PIO_PA28) ;- DBGU Debug Transmit Data
-AT91C_PIO_PA29 EQU (1 << 29) ;- Pin Controlled by PA29
-AT91C_PA29_FIQ EQU (AT91C_PIO_PA29) ;- AIC Fast Interrupt Input
-AT91C_PA29_NPCS13 EQU (AT91C_PIO_PA29) ;- SPI 1 Peripheral Chip Select 3
-AT91C_PIO_PA3 EQU (1 << 3) ;- Pin Controlled by PA3
-AT91C_PA3_RTS0 EQU (AT91C_PIO_PA3) ;- USART 0 Ready To Send
-AT91C_PA3_NPCS12 EQU (AT91C_PIO_PA3) ;- SPI 1 Peripheral Chip Select 2
-AT91C_PIO_PA30 EQU (1 << 30) ;- Pin Controlled by PA30
-AT91C_PA30_IRQ0 EQU (AT91C_PIO_PA30) ;- External Interrupt 0
-AT91C_PA30_PCK2 EQU (AT91C_PIO_PA30) ;- PMC Programmable Clock Output 2
-AT91C_PIO_PA4 EQU (1 << 4) ;- Pin Controlled by PA4
-AT91C_PA4_CTS0 EQU (AT91C_PIO_PA4) ;- USART 0 Clear To Send
-AT91C_PA4_NPCS13 EQU (AT91C_PIO_PA4) ;- SPI 1 Peripheral Chip Select 3
-AT91C_PIO_PA5 EQU (1 << 5) ;- Pin Controlled by PA5
-AT91C_PA5_RXD1 EQU (AT91C_PIO_PA5) ;- USART 1 Receive Data
-AT91C_PIO_PA6 EQU (1 << 6) ;- Pin Controlled by PA6
-AT91C_PA6_TXD1 EQU (AT91C_PIO_PA6) ;- USART 1 Transmit Data
-AT91C_PIO_PA7 EQU (1 << 7) ;- Pin Controlled by PA7
-AT91C_PA7_SCK1 EQU (AT91C_PIO_PA7) ;- USART 1 Serial Clock
-AT91C_PA7_NPCS01 EQU (AT91C_PIO_PA7) ;- SPI 0 Peripheral Chip Select 1
-AT91C_PIO_PA8 EQU (1 << 8) ;- Pin Controlled by PA8
-AT91C_PA8_RTS1 EQU (AT91C_PIO_PA8) ;- USART 1 Ready To Send
-AT91C_PA8_NPCS02 EQU (AT91C_PIO_PA8) ;- SPI 0 Peripheral Chip Select 2
-AT91C_PIO_PA9 EQU (1 << 9) ;- Pin Controlled by PA9
-AT91C_PA9_CTS1 EQU (AT91C_PIO_PA9) ;- USART 1 Clear To Send
-AT91C_PA9_NPCS03 EQU (AT91C_PIO_PA9) ;- SPI 0 Peripheral Chip Select 3
-AT91C_PIO_PB0 EQU (1 << 0) ;- Pin Controlled by PB0
-AT91C_PB0_ETXCK_EREFCK EQU (AT91C_PIO_PB0) ;- Ethernet MAC Transmit Clock/Reference Clock
-AT91C_PB0_PCK0 EQU (AT91C_PIO_PB0) ;- PMC Programmable Clock Output 0
-AT91C_PIO_PB1 EQU (1 << 1) ;- Pin Controlled by PB1
-AT91C_PB1_ETXEN EQU (AT91C_PIO_PB1) ;- Ethernet MAC Transmit Enable
-AT91C_PIO_PB10 EQU (1 << 10) ;- Pin Controlled by PB10
-AT91C_PB10_ETX2 EQU (AT91C_PIO_PB10) ;- Ethernet MAC Transmit Data 2
-AT91C_PB10_NPCS11 EQU (AT91C_PIO_PB10) ;- SPI 1 Peripheral Chip Select 1
-AT91C_PIO_PB11 EQU (1 << 11) ;- Pin Controlled by PB11
-AT91C_PB11_ETX3 EQU (AT91C_PIO_PB11) ;- Ethernet MAC Transmit Data 3
-AT91C_PB11_NPCS12 EQU (AT91C_PIO_PB11) ;- SPI 1 Peripheral Chip Select 2
-AT91C_PIO_PB12 EQU (1 << 12) ;- Pin Controlled by PB12
-AT91C_PB12_ETXER EQU (AT91C_PIO_PB12) ;- Ethernet MAC Transmikt Coding Error
-AT91C_PB12_TCLK0 EQU (AT91C_PIO_PB12) ;- Timer Counter 0 external clock input
-AT91C_PIO_PB13 EQU (1 << 13) ;- Pin Controlled by PB13
-AT91C_PB13_ERX2 EQU (AT91C_PIO_PB13) ;- Ethernet MAC Receive Data 2
-AT91C_PB13_NPCS01 EQU (AT91C_PIO_PB13) ;- SPI 0 Peripheral Chip Select 1
-AT91C_PIO_PB14 EQU (1 << 14) ;- Pin Controlled by PB14
-AT91C_PB14_ERX3 EQU (AT91C_PIO_PB14) ;- Ethernet MAC Receive Data 3
-AT91C_PB14_NPCS02 EQU (AT91C_PIO_PB14) ;- SPI 0 Peripheral Chip Select 2
-AT91C_PIO_PB15 EQU (1 << 15) ;- Pin Controlled by PB15
-AT91C_PB15_ERXDV EQU (AT91C_PIO_PB15) ;- Ethernet MAC Receive Data Valid
-AT91C_PIO_PB16 EQU (1 << 16) ;- Pin Controlled by PB16
-AT91C_PB16_ECOL EQU (AT91C_PIO_PB16) ;- Ethernet MAC Collision Detected
-AT91C_PB16_NPCS13 EQU (AT91C_PIO_PB16) ;- SPI 1 Peripheral Chip Select 3
-AT91C_PIO_PB17 EQU (1 << 17) ;- Pin Controlled by PB17
-AT91C_PB17_ERXCK EQU (AT91C_PIO_PB17) ;- Ethernet MAC Receive Clock
-AT91C_PB17_NPCS03 EQU (AT91C_PIO_PB17) ;- SPI 0 Peripheral Chip Select 3
-AT91C_PIO_PB18 EQU (1 << 18) ;- Pin Controlled by PB18
-AT91C_PB18_EF100 EQU (AT91C_PIO_PB18) ;- Ethernet MAC Force 100 Mbits/sec
-AT91C_PB18_ADTRG EQU (AT91C_PIO_PB18) ;- ADC External Trigger
-AT91C_PIO_PB19 EQU (1 << 19) ;- Pin Controlled by PB19
-AT91C_PB19_PWM0 EQU (AT91C_PIO_PB19) ;- PWM Channel 0
-AT91C_PB19_TCLK1 EQU (AT91C_PIO_PB19) ;- Timer Counter 1 external clock input
-AT91C_PIO_PB2 EQU (1 << 2) ;- Pin Controlled by PB2
-AT91C_PB2_ETX0 EQU (AT91C_PIO_PB2) ;- Ethernet MAC Transmit Data 0
-AT91C_PIO_PB20 EQU (1 << 20) ;- Pin Controlled by PB20
-AT91C_PB20_PWM1 EQU (AT91C_PIO_PB20) ;- PWM Channel 1
-AT91C_PB20_PCK0 EQU (AT91C_PIO_PB20) ;- PMC Programmable Clock Output 0
-AT91C_PIO_PB21 EQU (1 << 21) ;- Pin Controlled by PB21
-AT91C_PB21_PWM2 EQU (AT91C_PIO_PB21) ;- PWM Channel 2
-AT91C_PB21_PCK1 EQU (AT91C_PIO_PB21) ;- PMC Programmable Clock Output 1
-AT91C_PIO_PB22 EQU (1 << 22) ;- Pin Controlled by PB22
-AT91C_PB22_PWM3 EQU (AT91C_PIO_PB22) ;- PWM Channel 3
-AT91C_PB22_PCK2 EQU (AT91C_PIO_PB22) ;- PMC Programmable Clock Output 2
-AT91C_PIO_PB23 EQU (1 << 23) ;- Pin Controlled by PB23
-AT91C_PB23_TIOA0 EQU (AT91C_PIO_PB23) ;- Timer Counter 0 Multipurpose Timer I/O Pin A
-AT91C_PB23_DCD1 EQU (AT91C_PIO_PB23) ;- USART 1 Data Carrier Detect
-AT91C_PIO_PB24 EQU (1 << 24) ;- Pin Controlled by PB24
-AT91C_PB24_TIOB0 EQU (AT91C_PIO_PB24) ;- Timer Counter 0 Multipurpose Timer I/O Pin B
-AT91C_PB24_DSR1 EQU (AT91C_PIO_PB24) ;- USART 1 Data Set ready
-AT91C_PIO_PB25 EQU (1 << 25) ;- Pin Controlled by PB25
-AT91C_PB25_TIOA1 EQU (AT91C_PIO_PB25) ;- Timer Counter 1 Multipurpose Timer I/O Pin A
-AT91C_PB25_DTR1 EQU (AT91C_PIO_PB25) ;- USART 1 Data Terminal ready
-AT91C_PIO_PB26 EQU (1 << 26) ;- Pin Controlled by PB26
-AT91C_PB26_TIOB1 EQU (AT91C_PIO_PB26) ;- Timer Counter 1 Multipurpose Timer I/O Pin B
-AT91C_PB26_RI1 EQU (AT91C_PIO_PB26) ;- USART 1 Ring Indicator
-AT91C_PIO_PB27 EQU (1 << 27) ;- Pin Controlled by PB27
-AT91C_PB27_TIOA2 EQU (AT91C_PIO_PB27) ;- Timer Counter 2 Multipurpose Timer I/O Pin A
-AT91C_PB27_PWM0 EQU (AT91C_PIO_PB27) ;- PWM Channel 0
-AT91C_PIO_PB28 EQU (1 << 28) ;- Pin Controlled by PB28
-AT91C_PB28_TIOB2 EQU (AT91C_PIO_PB28) ;- Timer Counter 2 Multipurpose Timer I/O Pin B
-AT91C_PB28_PWM1 EQU (AT91C_PIO_PB28) ;- PWM Channel 1
-AT91C_PIO_PB29 EQU (1 << 29) ;- Pin Controlled by PB29
-AT91C_PB29_PCK1 EQU (AT91C_PIO_PB29) ;- PMC Programmable Clock Output 1
-AT91C_PB29_PWM2 EQU (AT91C_PIO_PB29) ;- PWM Channel 2
-AT91C_PIO_PB3 EQU (1 << 3) ;- Pin Controlled by PB3
-AT91C_PB3_ETX1 EQU (AT91C_PIO_PB3) ;- Ethernet MAC Transmit Data 1
-AT91C_PIO_PB30 EQU (1 << 30) ;- Pin Controlled by PB30
-AT91C_PB30_PCK2 EQU (AT91C_PIO_PB30) ;- PMC Programmable Clock Output 2
-AT91C_PB30_PWM3 EQU (AT91C_PIO_PB30) ;- PWM Channel 3
-AT91C_PIO_PB4 EQU (1 << 4) ;- Pin Controlled by PB4
-AT91C_PB4_ECRS_ECRSDV EQU (AT91C_PIO_PB4) ;- Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
-AT91C_PIO_PB5 EQU (1 << 5) ;- Pin Controlled by PB5
-AT91C_PB5_ERX0 EQU (AT91C_PIO_PB5) ;- Ethernet MAC Receive Data 0
-AT91C_PIO_PB6 EQU (1 << 6) ;- Pin Controlled by PB6
-AT91C_PB6_ERX1 EQU (AT91C_PIO_PB6) ;- Ethernet MAC Receive Data 1
-AT91C_PIO_PB7 EQU (1 << 7) ;- Pin Controlled by PB7
-AT91C_PB7_ERXER EQU (AT91C_PIO_PB7) ;- Ethernet MAC Receive Error
-AT91C_PIO_PB8 EQU (1 << 8) ;- Pin Controlled by PB8
-AT91C_PB8_EMDC EQU (AT91C_PIO_PB8) ;- Ethernet MAC Management Data Clock
-AT91C_PIO_PB9 EQU (1 << 9) ;- Pin Controlled by PB9
-AT91C_PB9_EMDIO EQU (AT91C_PIO_PB9) ;- Ethernet MAC Management Data Input/Output
-
-// - *****************************************************************************
-// - PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
-// - *****************************************************************************
-AT91C_ID_FIQ EQU ( 0) ;- Advanced Interrupt Controller (FIQ)
-AT91C_ID_SYS EQU ( 1) ;- System Peripheral
-AT91C_ID_PIOA EQU ( 2) ;- Parallel IO Controller A
-AT91C_ID_PIOB EQU ( 3) ;- Parallel IO Controller B
-AT91C_ID_SPI0 EQU ( 4) ;- Serial Peripheral Interface 0
-AT91C_ID_SPI1 EQU ( 5) ;- Serial Peripheral Interface 1
-AT91C_ID_US0 EQU ( 6) ;- USART 0
-AT91C_ID_US1 EQU ( 7) ;- USART 1
-AT91C_ID_SSC EQU ( 8) ;- Serial Synchronous Controller
-AT91C_ID_TWI EQU ( 9) ;- Two-Wire Interface
-AT91C_ID_PWMC EQU (10) ;- PWM Controller
-AT91C_ID_UDP EQU (11) ;- USB Device Port
-AT91C_ID_TC0 EQU (12) ;- Timer Counter 0
-AT91C_ID_TC1 EQU (13) ;- Timer Counter 1
-AT91C_ID_TC2 EQU (14) ;- Timer Counter 2
-AT91C_ID_CAN EQU (15) ;- Control Area Network Controller
-AT91C_ID_EMAC EQU (16) ;- Ethernet MAC
-AT91C_ID_ADC EQU (17) ;- Analog-to-Digital Converter
-AT91C_ID_AES EQU (18) ;- Advanced Encryption Standard 128-bit
-AT91C_ID_TDES EQU (19) ;- Triple Data Encryption Standard
-AT91C_ID_20_Reserved EQU (20) ;- Reserved
-AT91C_ID_21_Reserved EQU (21) ;- Reserved
-AT91C_ID_22_Reserved EQU (22) ;- Reserved
-AT91C_ID_23_Reserved EQU (23) ;- Reserved
-AT91C_ID_24_Reserved EQU (24) ;- Reserved
-AT91C_ID_25_Reserved EQU (25) ;- Reserved
-AT91C_ID_26_Reserved EQU (26) ;- Reserved
-AT91C_ID_27_Reserved EQU (27) ;- Reserved
-AT91C_ID_28_Reserved EQU (28) ;- Reserved
-AT91C_ID_29_Reserved EQU (29) ;- Reserved
-AT91C_ID_IRQ0 EQU (30) ;- Advanced Interrupt Controller (IRQ0)
-AT91C_ID_IRQ1 EQU (31) ;- Advanced Interrupt Controller (IRQ1)
-
-// - *****************************************************************************
-// - BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
-// - *****************************************************************************
-AT91C_BASE_SYS EQU (0xFFFFF000) ;- (SYS) Base Address
-AT91C_BASE_AIC EQU (0xFFFFF000) ;- (AIC) Base Address
-AT91C_BASE_PDC_DBGU EQU (0xFFFFF300) ;- (PDC_DBGU) Base Address
-AT91C_BASE_DBGU EQU (0xFFFFF200) ;- (DBGU) Base Address
-AT91C_BASE_PIOA EQU (0xFFFFF400) ;- (PIOA) Base Address
-AT91C_BASE_PIOB EQU (0xFFFFF600) ;- (PIOB) Base Address
-AT91C_BASE_CKGR EQU (0xFFFFFC20) ;- (CKGR) Base Address
-AT91C_BASE_PMC EQU (0xFFFFFC00) ;- (PMC) Base Address
-AT91C_BASE_RSTC EQU (0xFFFFFD00) ;- (RSTC) Base Address
-AT91C_BASE_RTTC EQU (0xFFFFFD20) ;- (RTTC) Base Address
-AT91C_BASE_PITC EQU (0xFFFFFD30) ;- (PITC) Base Address
-AT91C_BASE_WDTC EQU (0xFFFFFD40) ;- (WDTC) Base Address
-AT91C_BASE_VREG EQU (0xFFFFFD60) ;- (VREG) Base Address
-AT91C_BASE_MC EQU (0xFFFFFF00) ;- (MC) Base Address
-AT91C_BASE_PDC_SPI1 EQU (0xFFFE4100) ;- (PDC_SPI1) Base Address
-AT91C_BASE_SPI1 EQU (0xFFFE4000) ;- (SPI1) Base Address
-AT91C_BASE_PDC_SPI0 EQU (0xFFFE0100) ;- (PDC_SPI0) Base Address
-AT91C_BASE_SPI0 EQU (0xFFFE0000) ;- (SPI0) Base Address
-AT91C_BASE_PDC_US1 EQU (0xFFFC4100) ;- (PDC_US1) Base Address
-AT91C_BASE_US1 EQU (0xFFFC4000) ;- (US1) Base Address
-AT91C_BASE_PDC_US0 EQU (0xFFFC0100) ;- (PDC_US0) Base Address
-AT91C_BASE_US0 EQU (0xFFFC0000) ;- (US0) Base Address
-AT91C_BASE_PDC_SSC EQU (0xFFFD4100) ;- (PDC_SSC) Base Address
-AT91C_BASE_SSC EQU (0xFFFD4000) ;- (SSC) Base Address
-AT91C_BASE_TWI EQU (0xFFFB8000) ;- (TWI) Base Address
-AT91C_BASE_PWMC_CH3 EQU (0xFFFCC260) ;- (PWMC_CH3) Base Address
-AT91C_BASE_PWMC_CH2 EQU (0xFFFCC240) ;- (PWMC_CH2) Base Address
-AT91C_BASE_PWMC_CH1 EQU (0xFFFCC220) ;- (PWMC_CH1) Base Address
-AT91C_BASE_PWMC_CH0 EQU (0xFFFCC200) ;- (PWMC_CH0) Base Address
-AT91C_BASE_PWMC EQU (0xFFFCC000) ;- (PWMC) Base Address
-AT91C_BASE_UDP EQU (0xFFFB0000) ;- (UDP) Base Address
-AT91C_BASE_TC0 EQU (0xFFFA0000) ;- (TC0) Base Address
-AT91C_BASE_TC1 EQU (0xFFFA0040) ;- (TC1) Base Address
-AT91C_BASE_TC2 EQU (0xFFFA0080) ;- (TC2) Base Address
-AT91C_BASE_TCB EQU (0xFFFA0000) ;- (TCB) Base Address
-AT91C_BASE_CAN_MB0 EQU (0xFFFD0200) ;- (CAN_MB0) Base Address
-AT91C_BASE_CAN_MB1 EQU (0xFFFD0220) ;- (CAN_MB1) Base Address
-AT91C_BASE_CAN_MB2 EQU (0xFFFD0240) ;- (CAN_MB2) Base Address
-AT91C_BASE_CAN_MB3 EQU (0xFFFD0260) ;- (CAN_MB3) Base Address
-AT91C_BASE_CAN_MB4 EQU (0xFFFD0280) ;- (CAN_MB4) Base Address
-AT91C_BASE_CAN_MB5 EQU (0xFFFD02A0) ;- (CAN_MB5) Base Address
-AT91C_BASE_CAN_MB6 EQU (0xFFFD02C0) ;- (CAN_MB6) Base Address
-AT91C_BASE_CAN_MB7 EQU (0xFFFD02E0) ;- (CAN_MB7) Base Address
-AT91C_BASE_CAN EQU (0xFFFD0000) ;- (CAN) Base Address
-AT91C_BASE_EMAC EQU (0xFFFDC000) ;- (EMAC) Base Address
-AT91C_BASE_PDC_ADC EQU (0xFFFD8100) ;- (PDC_ADC) Base Address
-AT91C_BASE_ADC EQU (0xFFFD8000) ;- (ADC) Base Address
-AT91C_BASE_PDC_AES EQU (0xFFFA4100) ;- (PDC_AES) Base Address
-AT91C_BASE_AES EQU (0xFFFA4000) ;- (AES) Base Address
-AT91C_BASE_PDC_TDES EQU (0xFFFA8100) ;- (PDC_TDES) Base Address
-AT91C_BASE_TDES EQU (0xFFFA8000) ;- (TDES) Base Address
-
-// - *****************************************************************************
-// - MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
-// - *****************************************************************************
-AT91C_ISRAM EQU (0x00200000) ;- Internal SRAM base address
-AT91C_ISRAM_SIZE EQU (0x00010000) ;- Internal SRAM size in byte (64 Kbyte)
-AT91C_IFLASH EQU (0x00100000) ;- Internal ROM base address
-AT91C_IFLASH_SIZE EQU (0x00040000) ;- Internal ROM size in byte (256 Kbyte)
-
-
-
-#endif /* AT91SAM7X256_H */
+// - ----------------------------------------------------------------------------
+// - ATMEL Microcontroller Software Support - ROUSSET -
+// - ----------------------------------------------------------------------------
+// - DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+// - IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+// - DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+// - INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// - LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+// - OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// - LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// - NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+// - EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// - ----------------------------------------------------------------------------
+// - File Name : AT91SAM7X256.h
+// - Object : AT91SAM7X256 definitions
+// - Generated : AT91 SW Application Group 05/20/2005 (16:22:29)
+// -
+// - CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005//
+// - CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005//
+// - CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
+// - CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005//
+// - CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005//
+// - CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
+// - CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
+// - CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
+// - CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005//
+// - CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004//
+// - CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004//
+// - CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004//
+// - CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005//
+// - CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005//
+// - CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
+// - CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
+// - CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
+// - CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
+// - CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
+// - CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
+// - CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005//
+// - CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005//
+// - CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
+// - CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005//
+// - CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
+// - ----------------------------------------------------------------------------
+
+#ifndef AT91SAM7X256_H
+#define AT91SAM7X256_H
+
+typedef volatile unsigned int AT91_REG;// Hardware register definition
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR System Peripherals
+// *****************************************************************************
+typedef struct _AT91S_SYS {
+ AT91_REG AIC_SMR[32]; // Source Mode Register
+ AT91_REG AIC_SVR[32]; // Source Vector Register
+ AT91_REG AIC_IVR; // IRQ Vector Register
+ AT91_REG AIC_FVR; // FIQ Vector Register
+ AT91_REG AIC_ISR; // Interrupt Status Register
+ AT91_REG AIC_IPR; // Interrupt Pending Register
+ AT91_REG AIC_IMR; // Interrupt Mask Register
+ AT91_REG AIC_CISR; // Core Interrupt Status Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register
+ AT91_REG AIC_SPU; // Spurious Vector Register
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)
+ AT91_REG Reserved1[1]; //
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register
+ AT91_REG Reserved2[45]; //
+ AT91_REG DBGU_CR; // Control Register
+ AT91_REG DBGU_MR; // Mode Register
+ AT91_REG DBGU_IER; // Interrupt Enable Register
+ AT91_REG DBGU_IDR; // Interrupt Disable Register
+ AT91_REG DBGU_IMR; // Interrupt Mask Register
+ AT91_REG DBGU_CSR; // Channel Status Register
+ AT91_REG DBGU_RHR; // Receiver Holding Register
+ AT91_REG DBGU_THR; // Transmitter Holding Register
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register
+ AT91_REG Reserved3[7]; //
+ AT91_REG DBGU_CIDR; // Chip ID Register
+ AT91_REG DBGU_EXID; // Chip ID Extension Register
+ AT91_REG DBGU_FNTR; // Force NTRST Register
+ AT91_REG Reserved4[45]; //
+ AT91_REG DBGU_RPR; // Receive Pointer Register
+ AT91_REG DBGU_RCR; // Receive Counter Register
+ AT91_REG DBGU_TPR; // Transmit Pointer Register
+ AT91_REG DBGU_TCR; // Transmit Counter Register
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register
+ AT91_REG Reserved5[54]; //
+ AT91_REG PIOA_PER; // PIO Enable Register
+ AT91_REG PIOA_PDR; // PIO Disable Register
+ AT91_REG PIOA_PSR; // PIO Status Register
+ AT91_REG Reserved6[1]; //
+ AT91_REG PIOA_OER; // Output Enable Register
+ AT91_REG PIOA_ODR; // Output Disable Registerr
+ AT91_REG PIOA_OSR; // Output Status Register
+ AT91_REG Reserved7[1]; //
+ AT91_REG PIOA_IFER; // Input Filter Enable Register
+ AT91_REG PIOA_IFDR; // Input Filter Disable Register
+ AT91_REG PIOA_IFSR; // Input Filter Status Register
+ AT91_REG Reserved8[1]; //
+ AT91_REG PIOA_SODR; // Set Output Data Register
+ AT91_REG PIOA_CODR; // Clear Output Data Register
+ AT91_REG PIOA_ODSR; // Output Data Status Register
+ AT91_REG PIOA_PDSR; // Pin Data Status Register
+ AT91_REG PIOA_IER; // Interrupt Enable Register
+ AT91_REG PIOA_IDR; // Interrupt Disable Register
+ AT91_REG PIOA_IMR; // Interrupt Mask Register
+ AT91_REG PIOA_ISR; // Interrupt Status Register
+ AT91_REG PIOA_MDER; // Multi-driver Enable Register
+ AT91_REG PIOA_MDDR; // Multi-driver Disable Register
+ AT91_REG PIOA_MDSR; // Multi-driver Status Register
+ AT91_REG Reserved9[1]; //
+ AT91_REG PIOA_PPUDR; // Pull-up Disable Register
+ AT91_REG PIOA_PPUER; // Pull-up Enable Register
+ AT91_REG PIOA_PPUSR; // Pull-up Status Register
+ AT91_REG Reserved10[1]; //
+ AT91_REG PIOA_ASR; // Select A Register
+ AT91_REG PIOA_BSR; // Select B Register
+ AT91_REG PIOA_ABSR; // AB Select Status Register
+ AT91_REG Reserved11[9]; //
+ AT91_REG PIOA_OWER; // Output Write Enable Register
+ AT91_REG PIOA_OWDR; // Output Write Disable Register
+ AT91_REG PIOA_OWSR; // Output Write Status Register
+ AT91_REG Reserved12[85]; //
+ AT91_REG PIOB_PER; // PIO Enable Register
+ AT91_REG PIOB_PDR; // PIO Disable Register
+ AT91_REG PIOB_PSR; // PIO Status Register
+ AT91_REG Reserved13[1]; //
+ AT91_REG PIOB_OER; // Output Enable Register
+ AT91_REG PIOB_ODR; // Output Disable Registerr
+ AT91_REG PIOB_OSR; // Output Status Register
+ AT91_REG Reserved14[1]; //
+ AT91_REG PIOB_IFER; // Input Filter Enable Register
+ AT91_REG PIOB_IFDR; // Input Filter Disable Register
+ AT91_REG PIOB_IFSR; // Input Filter Status Register
+ AT91_REG Reserved15[1]; //
+ AT91_REG PIOB_SODR; // Set Output Data Register
+ AT91_REG PIOB_CODR; // Clear Output Data Register
+ AT91_REG PIOB_ODSR; // Output Data Status Register
+ AT91_REG PIOB_PDSR; // Pin Data Status Register
+ AT91_REG PIOB_IER; // Interrupt Enable Register
+ AT91_REG PIOB_IDR; // Interrupt Disable Register
+ AT91_REG PIOB_IMR; // Interrupt Mask Register
+ AT91_REG PIOB_ISR; // Interrupt Status Register
+ AT91_REG PIOB_MDER; // Multi-driver Enable Register
+ AT91_REG PIOB_MDDR; // Multi-driver Disable Register
+ AT91_REG PIOB_MDSR; // Multi-driver Status Register
+ AT91_REG Reserved16[1]; //
+ AT91_REG PIOB_PPUDR; // Pull-up Disable Register
+ AT91_REG PIOB_PPUER; // Pull-up Enable Register
+ AT91_REG PIOB_PPUSR; // Pull-up Status Register
+ AT91_REG Reserved17[1]; //
+ AT91_REG PIOB_ASR; // Select A Register
+ AT91_REG PIOB_BSR; // Select B Register
+ AT91_REG PIOB_ABSR; // AB Select Status Register
+ AT91_REG Reserved18[9]; //
+ AT91_REG PIOB_OWER; // Output Write Enable Register
+ AT91_REG PIOB_OWDR; // Output Write Disable Register
+ AT91_REG PIOB_OWSR; // Output Write Status Register
+ AT91_REG Reserved19[341]; //
+ AT91_REG PMC_SCER; // System Clock Enable Register
+ AT91_REG PMC_SCDR; // System Clock Disable Register
+ AT91_REG PMC_SCSR; // System Clock Status Register
+ AT91_REG Reserved20[1]; //
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register
+ AT91_REG Reserved21[1]; //
+ AT91_REG PMC_MOR; // Main Oscillator Register
+ AT91_REG PMC_MCFR; // Main Clock Frequency Register
+ AT91_REG Reserved22[1]; //
+ AT91_REG PMC_PLLR; // PLL Register
+ AT91_REG PMC_MCKR; // Master Clock Register
+ AT91_REG Reserved23[3]; //
+ AT91_REG PMC_PCKR[4]; // Programmable Clock Register
+ AT91_REG Reserved24[4]; //
+ AT91_REG PMC_IER; // Interrupt Enable Register
+ AT91_REG PMC_IDR; // Interrupt Disable Register
+ AT91_REG PMC_SR; // Status Register
+ AT91_REG PMC_IMR; // Interrupt Mask Register
+ AT91_REG Reserved25[36]; //
+ AT91_REG RSTC_RCR; // Reset Control Register
+ AT91_REG RSTC_RSR; // Reset Status Register
+ AT91_REG RSTC_RMR; // Reset Mode Register
+ AT91_REG Reserved26[5]; //
+ AT91_REG RTTC_RTMR; // Real-time Mode Register
+ AT91_REG RTTC_RTAR; // Real-time Alarm Register
+ AT91_REG RTTC_RTVR; // Real-time Value Register
+ AT91_REG RTTC_RTSR; // Real-time Status Register
+ AT91_REG PITC_PIMR; // Period Interval Mode Register
+ AT91_REG PITC_PISR; // Period Interval Status Register
+ AT91_REG PITC_PIVR; // Period Interval Value Register
+ AT91_REG PITC_PIIR; // Period Interval Image Register
+ AT91_REG WDTC_WDCR; // Watchdog Control Register
+ AT91_REG WDTC_WDMR; // Watchdog Mode Register
+ AT91_REG WDTC_WDSR; // Watchdog Status Register
+ AT91_REG Reserved27[5]; //
+ AT91_REG VREG_MR; // Voltage Regulator Mode Register
+} AT91S_SYS, *AT91PS_SYS;
+
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
+// *****************************************************************************
+typedef struct _AT91S_AIC {
+ AT91_REG AIC_SMR[32]; // Source Mode Register
+ AT91_REG AIC_SVR[32]; // Source Vector Register
+ AT91_REG AIC_IVR; // IRQ Vector Register
+ AT91_REG AIC_FVR; // FIQ Vector Register
+ AT91_REG AIC_ISR; // Interrupt Status Register
+ AT91_REG AIC_IPR; // Interrupt Pending Register
+ AT91_REG AIC_IMR; // Interrupt Mask Register
+ AT91_REG AIC_CISR; // Core Interrupt Status Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register
+ AT91_REG AIC_SPU; // Spurious Vector Register
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)
+ AT91_REG Reserved1[1]; //
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register
+} AT91S_AIC, *AT91PS_AIC;
+
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
+#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level
+#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level
+#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level
+#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type
+#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive
+#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive
+#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered
+#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered
+#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
+#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
+#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status
+#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
+#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode
+#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Peripheral DMA Controller
+// *****************************************************************************
+typedef struct _AT91S_PDC {
+ AT91_REG PDC_RPR; // Receive Pointer Register
+ AT91_REG PDC_RCR; // Receive Counter Register
+ AT91_REG PDC_TPR; // Transmit Pointer Register
+ AT91_REG PDC_TCR; // Transmit Counter Register
+ AT91_REG PDC_RNPR; // Receive Next Pointer Register
+ AT91_REG PDC_RNCR; // Receive Next Counter Register
+ AT91_REG PDC_TNPR; // Transmit Next Pointer Register
+ AT91_REG PDC_TNCR; // Transmit Next Counter Register
+ AT91_REG PDC_PTCR; // PDC Transfer Control Register
+ AT91_REG PDC_PTSR; // PDC Transfer Status Register
+} AT91S_PDC, *AT91PS_PDC;
+
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
+#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable
+#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable
+#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable
+#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Debug Unit
+// *****************************************************************************
+typedef struct _AT91S_DBGU {
+ AT91_REG DBGU_CR; // Control Register
+ AT91_REG DBGU_MR; // Mode Register
+ AT91_REG DBGU_IER; // Interrupt Enable Register
+ AT91_REG DBGU_IDR; // Interrupt Disable Register
+ AT91_REG DBGU_IMR; // Interrupt Mask Register
+ AT91_REG DBGU_CSR; // Channel Status Register
+ AT91_REG DBGU_RHR; // Receiver Holding Register
+ AT91_REG DBGU_THR; // Transmitter Holding Register
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register
+ AT91_REG Reserved0[7]; //
+ AT91_REG DBGU_CIDR; // Chip ID Register
+ AT91_REG DBGU_EXID; // Chip ID Extension Register
+ AT91_REG DBGU_FNTR; // Force NTRST Register
+ AT91_REG Reserved1[45]; //
+ AT91_REG DBGU_RPR; // Receive Pointer Register
+ AT91_REG DBGU_RCR; // Receive Counter Register
+ AT91_REG DBGU_TPR; // Transmit Pointer Register
+ AT91_REG DBGU_TCR; // Transmit Counter Register
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register
+} AT91S_DBGU, *AT91PS_DBGU;
+
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
+#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver
+#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter
+#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable
+#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable
+#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable
+#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable
+#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
+#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type
+#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity
+#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity
+#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space)
+#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
+#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity
+#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode
+#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
+#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
+#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt
+#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt
+#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
+#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt
+#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt
+#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt
+#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt
+#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt
+#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
+#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
+#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
+#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
+#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
+// *****************************************************************************
+typedef struct _AT91S_PIO {
+ AT91_REG PIO_PER; // PIO Enable Register
+ AT91_REG PIO_PDR; // PIO Disable Register
+ AT91_REG PIO_PSR; // PIO Status Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG PIO_OER; // Output Enable Register
+ AT91_REG PIO_ODR; // Output Disable Registerr
+ AT91_REG PIO_OSR; // Output Status Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG PIO_IFER; // Input Filter Enable Register
+ AT91_REG PIO_IFDR; // Input Filter Disable Register
+ AT91_REG PIO_IFSR; // Input Filter Status Register
+ AT91_REG Reserved2[1]; //
+ AT91_REG PIO_SODR; // Set Output Data Register
+ AT91_REG PIO_CODR; // Clear Output Data Register
+ AT91_REG PIO_ODSR; // Output Data Status Register
+ AT91_REG PIO_PDSR; // Pin Data Status Register
+ AT91_REG PIO_IER; // Interrupt Enable Register
+ AT91_REG PIO_IDR; // Interrupt Disable Register
+ AT91_REG PIO_IMR; // Interrupt Mask Register
+ AT91_REG PIO_ISR; // Interrupt Status Register
+ AT91_REG PIO_MDER; // Multi-driver Enable Register
+ AT91_REG PIO_MDDR; // Multi-driver Disable Register
+ AT91_REG PIO_MDSR; // Multi-driver Status Register
+ AT91_REG Reserved3[1]; //
+ AT91_REG PIO_PPUDR; // Pull-up Disable Register
+ AT91_REG PIO_PPUER; // Pull-up Enable Register
+ AT91_REG PIO_PPUSR; // Pull-up Status Register
+ AT91_REG Reserved4[1]; //
+ AT91_REG PIO_ASR; // Select A Register
+ AT91_REG PIO_BSR; // Select B Register
+ AT91_REG PIO_ABSR; // AB Select Status Register
+ AT91_REG Reserved5[9]; //
+ AT91_REG PIO_OWER; // Output Write Enable Register
+ AT91_REG PIO_OWDR; // Output Write Disable Register
+ AT91_REG PIO_OWSR; // Output Write Status Register
+} AT91S_PIO, *AT91PS_PIO;
+
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Clock Generator Controler
+// *****************************************************************************
+typedef struct _AT91S_CKGR {
+ AT91_REG CKGR_MOR; // Main Oscillator Register
+ AT91_REG CKGR_MCFR; // Main Clock Frequency Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG CKGR_PLLR; // PLL Register
+} AT91S_CKGR, *AT91PS_CKGR;
+
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
+#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable
+#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass
+#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
+#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency
+#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
+// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
+#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected
+#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0
+#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed
+#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter
+#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
+#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
+#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
+#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
+#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
+#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Power Management Controler
+// *****************************************************************************
+typedef struct _AT91S_PMC {
+ AT91_REG PMC_SCER; // System Clock Enable Register
+ AT91_REG PMC_SCDR; // System Clock Disable Register
+ AT91_REG PMC_SCSR; // System Clock Status Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG PMC_MOR; // Main Oscillator Register
+ AT91_REG PMC_MCFR; // Main Clock Frequency Register
+ AT91_REG Reserved2[1]; //
+ AT91_REG PMC_PLLR; // PLL Register
+ AT91_REG PMC_MCKR; // Master Clock Register
+ AT91_REG Reserved3[3]; //
+ AT91_REG PMC_PCKR[4]; // Programmable Clock Register
+ AT91_REG Reserved4[4]; //
+ AT91_REG PMC_IER; // Interrupt Enable Register
+ AT91_REG PMC_IDR; // Interrupt Disable Register
+ AT91_REG PMC_SR; // Status Register
+ AT91_REG PMC_IMR; // Interrupt Mask Register
+} AT91S_PMC, *AT91PS_PMC;
+
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
+#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock
+#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock
+#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
+// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
+#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection
+#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected
+#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected
+#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
+#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler
+#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock
+#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2
+#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4
+#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8
+#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16
+#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32
+#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
+#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask
+#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Reset Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RSTC {
+ AT91_REG RSTC_RCR; // Reset Control Register
+ AT91_REG RSTC_RSR; // Reset Status Register
+ AT91_REG RSTC_RMR; // Reset Mode Register
+} AT91S_RSTC, *AT91PS_RSTC;
+
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
+#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset
+#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset
+#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset
+#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
+#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status
+#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status
+#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type
+#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.
+#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.
+#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
+#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
+#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
+#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured.
+#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
+#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
+#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable
+#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable
+#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable
+#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RTTC {
+ AT91_REG RTTC_RTMR; // Real-time Mode Register
+ AT91_REG RTTC_RTAR; // Real-time Alarm Register
+ AT91_REG RTTC_RTVR; // Real-time Value Register
+ AT91_REG RTTC_RTSR; // Real-time Status Register
+} AT91S_RTTC, *AT91PS_RTTC;
+
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
+#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
+#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
+#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
+#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
+#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
+#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
+#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status
+#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PITC {
+ AT91_REG PITC_PIMR; // Period Interval Mode Register
+ AT91_REG PITC_PISR; // Period Interval Status Register
+ AT91_REG PITC_PIVR; // Period Interval Value Register
+ AT91_REG PITC_PIIR; // Period Interval Image Register
+} AT91S_PITC, *AT91PS_PITC;
+
+// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
+#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value
+#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
+#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
+// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
+#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status
+// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
+#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value
+#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
+// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_WDTC {
+ AT91_REG WDTC_WDCR; // Watchdog Control Register
+ AT91_REG WDTC_WDMR; // Watchdog Mode Register
+ AT91_REG WDTC_WDSR; // Watchdog Status Register
+} AT91S_WDTC, *AT91PS_WDTC;
+
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
+#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart
+#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
+#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
+#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
+#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
+#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
+#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
+#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
+#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow
+#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_VREG {
+ AT91_REG VREG_MR; // Voltage Regulator Mode Register
+} AT91S_VREG, *AT91PS_VREG;
+
+// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
+#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Memory Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_MC {
+ AT91_REG MC_RCR; // MC Remap Control Register
+ AT91_REG MC_ASR; // MC Abort Status Register
+ AT91_REG MC_AASR; // MC Abort Address Status Register
+ AT91_REG Reserved0[21]; //
+ AT91_REG MC_FMR; // MC Flash Mode Register
+ AT91_REG MC_FCR; // MC Flash Command Register
+ AT91_REG MC_FSR; // MC Flash Status Register
+} AT91S_MC, *AT91PS_MC;
+
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
+#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
+#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status
+#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status
+#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status
+#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte
+#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word
+#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word
+#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
+#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read
+#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write
+#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch
+#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
+#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
+#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
+#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
+// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
+#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready
+#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error
+#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error
+#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming
+#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State
+#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations
+#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations
+#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations
+#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations
+#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
+// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
+#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command
+#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
+#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
+#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
+#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
+#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
+#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit.
+#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number
+#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
+// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
+#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status
+#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status
+#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status
+#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
+#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
+#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
+#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
+#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
+#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
+#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
+#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
+#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
+#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
+#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
+#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
+#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
+#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
+#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
+#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
+#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
+#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
+#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
+#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Serial Parallel Interface
+// *****************************************************************************
+typedef struct _AT91S_SPI {
+ AT91_REG SPI_CR; // Control Register
+ AT91_REG SPI_MR; // Mode Register
+ AT91_REG SPI_RDR; // Receive Data Register
+ AT91_REG SPI_TDR; // Transmit Data Register
+ AT91_REG SPI_SR; // Status Register
+ AT91_REG SPI_IER; // Interrupt Enable Register
+ AT91_REG SPI_IDR; // Interrupt Disable Register
+ AT91_REG SPI_IMR; // Interrupt Mask Register
+ AT91_REG Reserved0[4]; //
+ AT91_REG SPI_CSR[4]; // Chip Select Register
+ AT91_REG Reserved1[48]; //
+ AT91_REG SPI_RPR; // Receive Pointer Register
+ AT91_REG SPI_RCR; // Receive Counter Register
+ AT91_REG SPI_TPR; // Transmit Pointer Register
+ AT91_REG SPI_TCR; // Transmit Counter Register
+ AT91_REG SPI_RNPR; // Receive Next Pointer Register
+ AT91_REG SPI_RNCR; // Receive Next Counter Register
+ AT91_REG SPI_TNPR; // Transmit Next Pointer Register
+ AT91_REG SPI_TNCR; // Transmit Next Counter Register
+ AT91_REG SPI_PTCR; // PDC Transfer Control Register
+ AT91_REG SPI_PTSR; // PDC Transfer Status Register
+} AT91S_SPI, *AT91PS_SPI;
+
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
+#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable
+#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable
+#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset
+#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
+#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode
+#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select
+#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select
+#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select
+#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode
+#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection
+#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection
+#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection
+#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
+#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
+#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data
+#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
+#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data
+#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
+#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full
+#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty
+#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error
+#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status
+#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt
+#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt
+#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt
+#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt
+#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
+#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity
+#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase
+#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer
+#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer
+#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer
+#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer
+#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer
+#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer
+#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer
+#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer
+#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer
+#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer
+#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer
+#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK
+#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Usart
+// *****************************************************************************
+typedef struct _AT91S_USART {
+ AT91_REG US_CR; // Control Register
+ AT91_REG US_MR; // Mode Register
+ AT91_REG US_IER; // Interrupt Enable Register
+ AT91_REG US_IDR; // Interrupt Disable Register
+ AT91_REG US_IMR; // Interrupt Mask Register
+ AT91_REG US_CSR; // Channel Status Register
+ AT91_REG US_RHR; // Receiver Holding Register
+ AT91_REG US_THR; // Transmitter Holding Register
+ AT91_REG US_BRGR; // Baud Rate Generator Register
+ AT91_REG US_RTOR; // Receiver Time-out Register
+ AT91_REG US_TTGR; // Transmitter Time-guard Register
+ AT91_REG Reserved0[5]; //
+ AT91_REG US_FIDI; // FI_DI_Ratio Register
+ AT91_REG US_NER; // Nb Errors Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG US_IF; // IRDA_FILTER Register
+ AT91_REG Reserved2[44]; //
+ AT91_REG US_RPR; // Receive Pointer Register
+ AT91_REG US_RCR; // Receive Counter Register
+ AT91_REG US_TPR; // Transmit Pointer Register
+ AT91_REG US_TCR; // Transmit Counter Register
+ AT91_REG US_RNPR; // Receive Next Pointer Register
+ AT91_REG US_RNCR; // Receive Next Counter Register
+ AT91_REG US_TNPR; // Transmit Next Pointer Register
+ AT91_REG US_TNCR; // Transmit Next Counter Register
+ AT91_REG US_PTCR; // PDC Transfer Control Register
+ AT91_REG US_PTSR; // PDC Transfer Status Register
+} AT91S_USART, *AT91PS_USART;
+
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
+#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break
+#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break
+#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out
+#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address
+#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
+#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
+#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
+#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
+#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
+#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
+#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
+#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode
+#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal
+#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485
+#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking
+#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem
+#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
+#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
+#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA
+#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking
+#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock
+#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1
+#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM)
+#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK)
+#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits
+#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits
+#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits
+#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits
+#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select
+#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
+#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
+#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
+#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order
+#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
+#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
+#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
+#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
+#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
+#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
+#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
+#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break
+#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out
+#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
+#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
+#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
+#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
+#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
+#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
+#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
+#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
+#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
+#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_SSC {
+ AT91_REG SSC_CR; // Control Register
+ AT91_REG SSC_CMR; // Clock Mode Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG SSC_RCMR; // Receive Clock ModeRegister
+ AT91_REG SSC_RFMR; // Receive Frame Mode Register
+ AT91_REG SSC_TCMR; // Transmit Clock Mode Register
+ AT91_REG SSC_TFMR; // Transmit Frame Mode Register
+ AT91_REG SSC_RHR; // Receive Holding Register
+ AT91_REG SSC_THR; // Transmit Holding Register
+ AT91_REG Reserved1[2]; //
+ AT91_REG SSC_RSHR; // Receive Sync Holding Register
+ AT91_REG SSC_TSHR; // Transmit Sync Holding Register
+ AT91_REG Reserved2[2]; //
+ AT91_REG SSC_SR; // Status Register
+ AT91_REG SSC_IER; // Interrupt Enable Register
+ AT91_REG SSC_IDR; // Interrupt Disable Register
+ AT91_REG SSC_IMR; // Interrupt Mask Register
+ AT91_REG Reserved3[44]; //
+ AT91_REG SSC_RPR; // Receive Pointer Register
+ AT91_REG SSC_RCR; // Receive Counter Register
+ AT91_REG SSC_TPR; // Transmit Pointer Register
+ AT91_REG SSC_TCR; // Transmit Counter Register
+ AT91_REG SSC_RNPR; // Receive Next Pointer Register
+ AT91_REG SSC_RNCR; // Receive Next Counter Register
+ AT91_REG SSC_TNPR; // Transmit Next Pointer Register
+ AT91_REG SSC_TNCR; // Transmit Next Counter Register
+ AT91_REG SSC_PTCR; // PDC Transfer Control Register
+ AT91_REG SSC_PTSR; // PDC Transfer Status Register
+} AT91S_SSC, *AT91PS_SSC;
+
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
+#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable
+#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable
+#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable
+#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable
+#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
+#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection
+#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock
+#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal
+#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin
+#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
+#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
+#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
+#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection
+#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start
+#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input
+#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input
+#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input
+#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input
+#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input
+#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input
+#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0
+#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
+#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
+#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length
+#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode
+#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First
+#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame
+#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
+#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
+#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
+#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value
+#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
+#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready
+#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty
+#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission
+#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty
+#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready
+#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun
+#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception
+#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full
+#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
+#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
+#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
+#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Two-wire Interface
+// *****************************************************************************
+typedef struct _AT91S_TWI {
+ AT91_REG TWI_CR; // Control Register
+ AT91_REG TWI_MMR; // Master Mode Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG TWI_IADR; // Internal Address Register
+ AT91_REG TWI_CWGR; // Clock Waveform Generator Register
+ AT91_REG Reserved1[3]; //
+ AT91_REG TWI_SR; // Status Register
+ AT91_REG TWI_IER; // Interrupt Enable Register
+ AT91_REG TWI_IDR; // Interrupt Disable Register
+ AT91_REG TWI_IMR; // Interrupt Mask Register
+ AT91_REG TWI_RHR; // Receive Holding Register
+ AT91_REG TWI_THR; // Transmit Holding Register
+} AT91S_TWI, *AT91PS_TWI;
+
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
+#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition
+#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition
+#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled
+#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled
+#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
+#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size
+#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address
+#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address
+#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address
+#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address
+#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
+#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
+#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider
+#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider
+#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
+#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed
+#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY
+#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error
+#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error
+#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR PWMC Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC_CH {
+ AT91_REG PWMC_CMR; // Channel Mode Register
+ AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register
+ AT91_REG PWMC_CPRDR; // Channel Period Register
+ AT91_REG PWMC_CCNTR; // Channel Counter Register
+ AT91_REG PWMC_CUPDR; // Channel Update Register
+ AT91_REG PWMC_Reserved[3]; // Reserved
+} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
+
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
+#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
+#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH)
+#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH)
+#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH)
+#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment
+#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity
+#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
+#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
+#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
+#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter
+// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
+#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC {
+ AT91_REG PWMC_MR; // PWMC Mode Register
+ AT91_REG PWMC_ENA; // PWMC Enable Register
+ AT91_REG PWMC_DIS; // PWMC Disable Register
+ AT91_REG PWMC_SR; // PWMC Status Register
+ AT91_REG PWMC_IER; // PWMC Interrupt Enable Register
+ AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register
+ AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register
+ AT91_REG PWMC_ISR; // PWMC Interrupt Status Register
+ AT91_REG Reserved0[55]; //
+ AT91_REG PWMC_VR; // PWMC Version Register
+ AT91_REG Reserved1[64]; //
+ AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel
+} AT91S_PWMC, *AT91PS_PWMC;
+
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
+#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor.
+#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A
+#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC)
+#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
+#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
+#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC)
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
+#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0
+#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1
+#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2
+#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
+// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
+// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
+// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
+// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR USB Device Interface
+// *****************************************************************************
+typedef struct _AT91S_UDP {
+ AT91_REG UDP_NUM; // Frame Number Register
+ AT91_REG UDP_GLBSTATE; // Global State Register
+ AT91_REG UDP_FADDR; // Function Address Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG UDP_IER; // Interrupt Enable Register
+ AT91_REG UDP_IDR; // Interrupt Disable Register
+ AT91_REG UDP_IMR; // Interrupt Mask Register
+ AT91_REG UDP_ISR; // Interrupt Status Register
+ AT91_REG UDP_ICR; // Interrupt Clear Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG UDP_RSTEP; // Reset Endpoint Register
+ AT91_REG Reserved2[1]; //
+ AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register
+ AT91_REG Reserved3[2]; //
+ AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register
+ AT91_REG Reserved4[3]; //
+ AT91_REG UDP_TXVC; // Transceiver Control Register
+} AT91S_UDP, *AT91PS_UDP;
+
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
+#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
+#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error
+#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
+#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable
+#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured
+#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume
+#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
+#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
+#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value
+#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
+#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt
+#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt
+#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt
+#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt
+#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt
+#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt
+#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
+#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
+#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
+#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
+#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0
+#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1
+#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2
+#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3
+#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4
+#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
+#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
+#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0
+#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
+#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
+#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready
+#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction
+#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type
+#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control
+#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT
+#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT
+#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT
+#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN
+#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN
+#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN
+#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
+#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
+#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
+// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
+#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP)
+#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_TC {
+ AT91_REG TC_CCR; // Channel Control Register
+ AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)
+ AT91_REG Reserved0[2]; //
+ AT91_REG TC_CV; // Counter Value
+ AT91_REG TC_RA; // Register A
+ AT91_REG TC_RB; // Register B
+ AT91_REG TC_RC; // Register C
+ AT91_REG TC_SR; // Status Register
+ AT91_REG TC_IER; // Interrupt Enable Register
+ AT91_REG TC_IDR; // Interrupt Disable Register
+ AT91_REG TC_IMR; // Interrupt Mask Register
+} AT91S_TC, *AT91PS_TC;
+
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
+#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command
+#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command
+#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
+#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection
+#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
+#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0
+#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1
+#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2
+#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert
+#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection
+#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal
+#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock
+#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock
+#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock
+#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
+#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
+#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare
+#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
+#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection
+#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
+#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
+#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
+#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
+#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection
+#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
+#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
+#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
+#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
+#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection
+#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
+#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
+#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
+#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
+#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
+#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
+#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection
+#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
+#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
+#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC)
+#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
+#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none
+#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set
+#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear
+#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
+#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
+#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None
+#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
+#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
+#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
+#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none
+#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set
+#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear
+#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
+#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
+#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None
+#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
+#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
+#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
+#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none
+#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set
+#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear
+#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
+#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
+#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none
+#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set
+#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear
+#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
+#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
+#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none
+#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set
+#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear
+#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
+#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
+#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none
+#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set
+#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear
+#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
+#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
+#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none
+#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set
+#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear
+#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
+#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
+#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none
+#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set
+#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear
+#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
+#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow
+#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun
+#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare
+#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare
+#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare
+#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading
+#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading
+#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger
+#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
+#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
+#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Timer Counter Interface
+// *****************************************************************************
+typedef struct _AT91S_TCB {
+ AT91S_TC TCB_TC0; // TC Channel 0
+ AT91_REG Reserved0[4]; //
+ AT91S_TC TCB_TC1; // TC Channel 1
+ AT91_REG Reserved1[4]; //
+ AT91S_TC TCB_TC2; // TC Channel 2
+ AT91_REG Reserved2[4]; //
+ AT91_REG TCB_BCR; // TC Block Control Register
+ AT91_REG TCB_BMR; // TC Block Mode Register
+} AT91S_TCB, *AT91PS_TCB;
+
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
+#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
+#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection
+#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
+#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0
+#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
+#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
+#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection
+#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1
+#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1
+#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1
+#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1
+#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection
+#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2
+#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2
+#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2
+#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface
+// *****************************************************************************
+typedef struct _AT91S_CAN_MB {
+ AT91_REG CAN_MB_MMR; // MailBox Mode Register
+ AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register
+ AT91_REG CAN_MB_MID; // MailBox ID Register
+ AT91_REG CAN_MB_MFID; // MailBox Family ID Register
+ AT91_REG CAN_MB_MSR; // MailBox Status Register
+ AT91_REG CAN_MB_MDL; // MailBox Data Low Register
+ AT91_REG CAN_MB_MDH; // MailBox Data High Register
+ AT91_REG CAN_MB_MCR; // MailBox Control Register
+} AT91S_CAN_MB, *AT91PS_CAN_MB;
+
+// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register --------
+#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark
+#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority
+#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type
+#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB)
+#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB)
+#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB)
+#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB)
+#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB)
+#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB)
+// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register --------
+#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode
+#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
+#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version
+// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register --------
+// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register --------
+// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register --------
+#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value
+#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code
+#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
+#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort
+#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready
+#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored
+// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register --------
+// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register --------
+// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register --------
+#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox
+#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Control Area Network Interface
+// *****************************************************************************
+typedef struct _AT91S_CAN {
+ AT91_REG CAN_MR; // Mode Register
+ AT91_REG CAN_IER; // Interrupt Enable Register
+ AT91_REG CAN_IDR; // Interrupt Disable Register
+ AT91_REG CAN_IMR; // Interrupt Mask Register
+ AT91_REG CAN_SR; // Status Register
+ AT91_REG CAN_BR; // Baudrate Register
+ AT91_REG CAN_TIM; // Timer Register
+ AT91_REG CAN_TIMESTP; // Time Stamp Register
+ AT91_REG CAN_ECR; // Error Counter Register
+ AT91_REG CAN_TCR; // Transfer Command Register
+ AT91_REG CAN_ACR; // Abort Command Register
+ AT91_REG Reserved0[52]; //
+ AT91_REG CAN_VR; // Version Register
+ AT91_REG Reserved1[64]; //
+ AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0
+ AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1
+ AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2
+ AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3
+ AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4
+ AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5
+ AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6
+ AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7
+ AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8
+ AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9
+ AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10
+ AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11
+ AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12
+ AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13
+ AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14
+ AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15
+} AT91S_CAN, *AT91PS_CAN;
+
+// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register --------
+#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable
+#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode
+#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode
+#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame
+#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame
+#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode
+#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze
+#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat
+// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register --------
+#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag
+#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag
+#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag
+#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag
+#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag
+#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag
+#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag
+#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag
+#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag
+#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag
+#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag
+#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag
+#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag
+#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag
+#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag
+#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag
+#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag
+#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag
+#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag
+#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag
+#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag
+#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag
+#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag
+#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag
+#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error
+#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error
+#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error
+#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error
+#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error
+// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register --------
+// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register --------
+// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register --------
+#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy
+#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy
+#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy
+// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register --------
+#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment
+#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment
+#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment
+#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment
+#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler
+#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode
+// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register --------
+#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field
+// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register --------
+// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register --------
+#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter
+#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter
+// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register --------
+#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field
+// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100
+// *****************************************************************************
+typedef struct _AT91S_EMAC {
+ AT91_REG EMAC_NCR; // Network Control Register
+ AT91_REG EMAC_NCFGR; // Network Configuration Register
+ AT91_REG EMAC_NSR; // Network Status Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG EMAC_TSR; // Transmit Status Register
+ AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer
+ AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer
+ AT91_REG EMAC_RSR; // Receive Status Register
+ AT91_REG EMAC_ISR; // Interrupt Status Register
+ AT91_REG EMAC_IER; // Interrupt Enable Register
+ AT91_REG EMAC_IDR; // Interrupt Disable Register
+ AT91_REG EMAC_IMR; // Interrupt Mask Register
+ AT91_REG EMAC_MAN; // PHY Maintenance Register
+ AT91_REG EMAC_PTR; // Pause Time Register
+ AT91_REG EMAC_PFR; // Pause Frames received Register
+ AT91_REG EMAC_FTO; // Frames Transmitted OK Register
+ AT91_REG EMAC_SCF; // Single Collision Frame Register
+ AT91_REG EMAC_MCF; // Multiple Collision Frame Register
+ AT91_REG EMAC_FRO; // Frames Received OK Register
+ AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register
+ AT91_REG EMAC_ALE; // Alignment Error Register
+ AT91_REG EMAC_DTF; // Deferred Transmission Frame Register
+ AT91_REG EMAC_LCOL; // Late Collision Register
+ AT91_REG EMAC_ECOL; // Excessive Collision Register
+ AT91_REG EMAC_TUND; // Transmit Underrun Error Register
+ AT91_REG EMAC_CSE; // Carrier Sense Error Register
+ AT91_REG EMAC_RRE; // Receive Ressource Error Register
+ AT91_REG EMAC_ROV; // Receive Overrun Errors Register
+ AT91_REG EMAC_RSE; // Receive Symbol Errors Register
+ AT91_REG EMAC_ELE; // Excessive Length Errors Register
+ AT91_REG EMAC_RJA; // Receive Jabbers Register
+ AT91_REG EMAC_USF; // Undersize Frames Register
+ AT91_REG EMAC_STE; // SQE Test Error Register
+ AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register
+ AT91_REG EMAC_TPF; // Transmitted Pause Frames Register
+ AT91_REG EMAC_HRB; // Hash Address Bottom[31:0]
+ AT91_REG EMAC_HRT; // Hash Address Top[63:32]
+ AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes
+ AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes
+ AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes
+ AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes
+ AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes
+ AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes
+ AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes
+ AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes
+ AT91_REG EMAC_TID; // Type ID Checking Register
+ AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register
+ AT91_REG EMAC_USRIO; // USER Input/Output Register
+ AT91_REG EMAC_WOL; // Wake On LAN Register
+ AT91_REG Reserved1[13]; //
+ AT91_REG EMAC_REV; // Revision Register
+} AT91S_EMAC, *AT91PS_EMAC;
+
+// -------- EMAC_NCR : (EMAC Offset: 0x0) --------
+#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
+#define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local.
+#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable.
+#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable.
+#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable.
+#define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers.
+#define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers.
+#define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers.
+#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure.
+#define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission.
+#define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt.
+#define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame
+#define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame
+// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register --------
+#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed.
+#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex.
+#define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames.
+#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames.
+#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast.
+#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable
+#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable.
+#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes.
+#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable.
+#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC)
+#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8
+#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16
+#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32
+#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64
+#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC)
+#define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC)
+#define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC)
+#define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer
+#define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer
+#define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
+#define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
+#define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable
+#define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS
+#define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC)
+#define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS
+// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register --------
+#define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC)
+#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC)
+#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC)
+// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register --------
+#define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC)
+#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC)
+#define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC)
+#define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go
+#define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame
+#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC)
+#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC)
+// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
+#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC)
+#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC)
+#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC)
+// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
+#define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC)
+#define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC)
+#define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC)
+#define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC)
+#define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC)
+#define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC)
+#define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC)
+#define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC)
+#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC)
+#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC)
+#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC)
+#define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC)
+#define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC)
+// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
+// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
+// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
+// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
+#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC)
+#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC)
+#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC)
+#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC)
+#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC)
+#define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC)
+// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register --------
+#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII
+// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register --------
+#define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address
+#define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable
+#define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable
+#define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable
+// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register --------
+#define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC)
+#define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC)
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Analog to Digital Convertor
+// *****************************************************************************
+typedef struct _AT91S_ADC {
+ AT91_REG ADC_CR; // ADC Control Register
+ AT91_REG ADC_MR; // ADC Mode Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG ADC_CHER; // ADC Channel Enable Register
+ AT91_REG ADC_CHDR; // ADC Channel Disable Register
+ AT91_REG ADC_CHSR; // ADC Channel Status Register
+ AT91_REG ADC_SR; // ADC Status Register
+ AT91_REG ADC_LCDR; // ADC Last Converted Data Register
+ AT91_REG ADC_IER; // ADC Interrupt Enable Register
+ AT91_REG ADC_IDR; // ADC Interrupt Disable Register
+ AT91_REG ADC_IMR; // ADC Interrupt Mask Register
+ AT91_REG ADC_CDR0; // ADC Channel Data Register 0
+ AT91_REG ADC_CDR1; // ADC Channel Data Register 1
+ AT91_REG ADC_CDR2; // ADC Channel Data Register 2
+ AT91_REG ADC_CDR3; // ADC Channel Data Register 3
+ AT91_REG ADC_CDR4; // ADC Channel Data Register 4
+ AT91_REG ADC_CDR5; // ADC Channel Data Register 5
+ AT91_REG ADC_CDR6; // ADC Channel Data Register 6
+ AT91_REG ADC_CDR7; // ADC Channel Data Register 7
+ AT91_REG Reserved1[44]; //
+ AT91_REG ADC_RPR; // Receive Pointer Register
+ AT91_REG ADC_RCR; // Receive Counter Register
+ AT91_REG ADC_TPR; // Transmit Pointer Register
+ AT91_REG ADC_TCR; // Transmit Counter Register
+ AT91_REG ADC_RNPR; // Receive Next Pointer Register
+ AT91_REG ADC_RNCR; // Receive Next Counter Register
+ AT91_REG ADC_TNPR; // Transmit Next Pointer Register
+ AT91_REG ADC_TNCR; // Transmit Next Counter Register
+ AT91_REG ADC_PTCR; // PDC Transfer Control Register
+ AT91_REG ADC_PTSR; // PDC Transfer Status Register
+} AT91S_ADC, *AT91PS_ADC;
+
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
+#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset
+#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
+#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable
+#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
+#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection
+#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
+#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
+#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
+#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
+#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
+#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
+#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
+#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution.
+#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution
+#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution
+#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
+#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode
+#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
+#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection
+#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time
+#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
+// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
+#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0
+#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1
+#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2
+#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3
+#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4
+#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5
+#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6
+#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7
+// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
+// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
+#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion
+#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion
+#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion
+#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion
+#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion
+#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion
+#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion
+#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion
+#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
+#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready
+#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun
+#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
+#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
+#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
+#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Advanced Encryption Standard
+// *****************************************************************************
+typedef struct _AT91S_AES {
+ AT91_REG AES_CR; // Control Register
+ AT91_REG AES_MR; // Mode Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG AES_IER; // Interrupt Enable Register
+ AT91_REG AES_IDR; // Interrupt Disable Register
+ AT91_REG AES_IMR; // Interrupt Mask Register
+ AT91_REG AES_ISR; // Interrupt Status Register
+ AT91_REG AES_KEYWxR[4]; // Key Word x Register
+ AT91_REG Reserved1[4]; //
+ AT91_REG AES_IDATAxR[4]; // Input Data x Register
+ AT91_REG AES_ODATAxR[4]; // Output Data x Register
+ AT91_REG AES_IVxR[4]; // Initialization Vector x Register
+ AT91_REG Reserved2[35]; //
+ AT91_REG AES_VR; // AES Version Register
+ AT91_REG AES_RPR; // Receive Pointer Register
+ AT91_REG AES_RCR; // Receive Counter Register
+ AT91_REG AES_TPR; // Transmit Pointer Register
+ AT91_REG AES_TCR; // Transmit Counter Register
+ AT91_REG AES_RNPR; // Receive Next Pointer Register
+ AT91_REG AES_RNCR; // Receive Next Counter Register
+ AT91_REG AES_TNPR; // Transmit Next Pointer Register
+ AT91_REG AES_TNCR; // Transmit Next Counter Register
+ AT91_REG AES_PTCR; // PDC Transfer Control Register
+ AT91_REG AES_PTSR; // PDC Transfer Status Register
+} AT91S_AES, *AT91PS_AES;
+
+// -------- AES_CR : (AES Offset: 0x0) Control Register --------
+#define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing
+#define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset
+#define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading
+// -------- AES_MR : (AES Offset: 0x4) Mode Register --------
+#define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode
+#define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay
+#define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode
+#define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
+#define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
+#define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet).
+#define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode
+#define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode.
+#define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
+#define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode.
+#define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode.
+#define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode.
+#define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode
+#define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size
+#define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit.
+#define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit.
+#define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit.
+#define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit.
+#define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit.
+#define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key
+#define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type
+#define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled.
+#define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled.
+#define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled.
+#define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled.
+#define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled.
+// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register --------
+#define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY
+#define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End
+#define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End
+#define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full
+#define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty
+#define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection
+// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register --------
+// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register --------
+// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register --------
+#define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status
+#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
+#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing.
+#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing.
+#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation.
+#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation.
+#define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access.
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard
+// *****************************************************************************
+typedef struct _AT91S_TDES {
+ AT91_REG TDES_CR; // Control Register
+ AT91_REG TDES_MR; // Mode Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG TDES_IER; // Interrupt Enable Register
+ AT91_REG TDES_IDR; // Interrupt Disable Register
+ AT91_REG TDES_IMR; // Interrupt Mask Register
+ AT91_REG TDES_ISR; // Interrupt Status Register
+ AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register
+ AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register
+ AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register
+ AT91_REG Reserved1[2]; //
+ AT91_REG TDES_IDATAxR[2]; // Input Data x Register
+ AT91_REG Reserved2[2]; //
+ AT91_REG TDES_ODATAxR[2]; // Output Data x Register
+ AT91_REG Reserved3[2]; //
+ AT91_REG TDES_IVxR[2]; // Initialization Vector x Register
+ AT91_REG Reserved4[37]; //
+ AT91_REG TDES_VR; // TDES Version Register
+ AT91_REG TDES_RPR; // Receive Pointer Register
+ AT91_REG TDES_RCR; // Receive Counter Register
+ AT91_REG TDES_TPR; // Transmit Pointer Register
+ AT91_REG TDES_TCR; // Transmit Counter Register
+ AT91_REG TDES_RNPR; // Receive Next Pointer Register
+ AT91_REG TDES_RNCR; // Receive Next Counter Register
+ AT91_REG TDES_TNPR; // Transmit Next Pointer Register
+ AT91_REG TDES_TNCR; // Transmit Next Counter Register
+ AT91_REG TDES_PTCR; // PDC Transfer Control Register
+ AT91_REG TDES_PTSR; // PDC Transfer Status Register
+} AT91S_TDES, *AT91PS_TDES;
+
+// -------- TDES_CR : (TDES Offset: 0x0) Control Register --------
+#define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing
+#define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset
+// -------- TDES_MR : (TDES Offset: 0x4) Mode Register --------
+#define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode
+#define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode
+#define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode
+#define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode
+#define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
+#define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
+#define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet).
+#define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode
+#define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
+#define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
+#define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode.
+#define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode.
+#define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode
+#define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size
+#define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit.
+#define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit.
+#define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit.
+#define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit.
+// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register --------
+#define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY
+#define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End
+#define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End
+#define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full
+#define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty
+#define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection
+// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register --------
+// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register --------
+// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register --------
+#define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status
+#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
+#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing.
+#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing.
+#define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access.
+
+// *****************************************************************************
+// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
+// *****************************************************************************
+// ========== Register definition for SYS peripheral ==========
+// ========== Register definition for AIC peripheral ==========
+#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register
+#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register
+#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register
+#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)
+#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register
+#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register
+#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register
+#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register
+#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register
+#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register
+#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register
+#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register
+#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register
+#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register
+#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register
+#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register
+#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register
+#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register
+// ========== Register definition for PDC_DBGU peripheral ==========
+#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
+#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
+#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
+#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
+#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
+#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register
+#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
+#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
+#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
+#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
+// ========== Register definition for DBGU peripheral ==========
+#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register
+#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register
+#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register
+#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register
+#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register
+#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register
+#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register
+#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register
+#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register
+#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register
+#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register
+#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register
+// ========== Register definition for PIOA peripheral ==========
+#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr
+#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register
+#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register
+#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register
+#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register
+#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register
+#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register
+#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register
+#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register
+#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register
+#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register
+#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register
+#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register
+#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register
+#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register
+#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register
+#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register
+#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register
+#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register
+#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register
+#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register
+#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register
+#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register
+#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register
+#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register
+#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register
+#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register
+#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register
+#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register
+// ========== Register definition for PIOB peripheral ==========
+#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register
+#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register
+#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register
+#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register
+#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register
+#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register
+#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register
+#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register
+#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register
+#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register
+#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register
+#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register
+#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register
+#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register
+#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register
+#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register
+#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr
+#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register
+#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register
+#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register
+#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register
+#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register
+#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register
+#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register
+#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register
+#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register
+#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register
+#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register
+#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register
+// ========== Register definition for CKGR peripheral ==========
+#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register
+#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register
+#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register
+// ========== Register definition for PMC peripheral ==========
+#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register
+#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
+#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register
+#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
+#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register
+#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
+#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register
+#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
+#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register
+#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register
+#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register
+#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register
+#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register
+#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register
+#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register
+// ========== Register definition for RSTC peripheral ==========
+#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register
+#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register
+#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register
+// ========== Register definition for RTTC peripheral ==========
+#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register
+#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register
+#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register
+#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register
+// ========== Register definition for PITC peripheral ==========
+#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register
+#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register
+#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register
+#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register
+// ========== Register definition for WDTC peripheral ==========
+#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register
+#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register
+#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register
+// ========== Register definition for VREG peripheral ==========
+#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
+// ========== Register definition for MC peripheral ==========
+#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register
+#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register
+#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register
+#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register
+#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register
+#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register
+// ========== Register definition for PDC_SPI1 peripheral ==========
+#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
+#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
+#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
+#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
+#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
+#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
+#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register
+#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
+#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
+#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
+// ========== Register definition for SPI1 peripheral ==========
+#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register
+#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register
+#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register
+#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register
+#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register
+#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register
+#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register
+#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register
+#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register
+// ========== Register definition for PDC_SPI0 peripheral ==========
+#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
+#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
+#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
+#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register
+#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
+#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
+#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
+#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
+#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
+#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
+// ========== Register definition for SPI0 peripheral ==========
+#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register
+#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register
+#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register
+#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register
+#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register
+#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register
+#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register
+#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register
+#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register
+// ========== Register definition for PDC_US1 peripheral ==========
+#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register
+#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
+#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register
+#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
+#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
+#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register
+#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
+#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register
+#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
+#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register
+// ========== Register definition for US1 peripheral ==========
+#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register
+#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register
+#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register
+#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register
+#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register
+#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register
+#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register
+#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register
+#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register
+#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register
+#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register
+#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register
+#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register
+#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register
+// ========== Register definition for PDC_US0 peripheral ==========
+#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
+#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
+#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register
+#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
+#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
+#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
+#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register
+#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register
+#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register
+#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register
+// ========== Register definition for US0 peripheral ==========
+#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register
+#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register
+#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register
+#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register
+#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register
+#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register
+#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register
+#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register
+#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register
+#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register
+#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register
+#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register
+#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register
+#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register
+// ========== Register definition for PDC_SSC peripheral ==========
+#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
+#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register
+#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
+#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
+#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
+#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register
+#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register
+#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
+#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
+#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
+// ========== Register definition for SSC peripheral ==========
+#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register
+#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register
+#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register
+#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register
+#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register
+#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister
+#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register
+#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register
+#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register
+#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register
+#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register
+#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register
+#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register
+#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register
+// ========== Register definition for TWI peripheral ==========
+#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register
+#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register
+#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register
+#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register
+#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register
+#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register
+#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register
+#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register
+#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register
+#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register
+// ========== Register definition for PWMC_CH3 peripheral ==========
+#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register
+#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved
+#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register
+#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
+#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
+#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register
+// ========== Register definition for PWMC_CH2 peripheral ==========
+#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved
+#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register
+#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
+#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register
+#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register
+#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH1 peripheral ==========
+#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved
+#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register
+#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register
+#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
+#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
+#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register
+// ========== Register definition for PWMC_CH0 peripheral ==========
+#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved
+#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register
+#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
+#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register
+#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register
+#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
+// ========== Register definition for PWMC peripheral ==========
+#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
+#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register
+#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
+#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register
+#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
+#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register
+#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
+#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register
+#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register
+// ========== Register definition for UDP peripheral ==========
+#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register
+#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register
+#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register
+#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register
+#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register
+#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register
+#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register
+#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register
+#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register
+#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register
+#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register
+#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register
+// ========== Register definition for TC0 peripheral ==========
+#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register
+#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C
+#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B
+#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register
+#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register
+#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A
+#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register
+#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value
+#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register
+// ========== Register definition for TC1 peripheral ==========
+#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B
+#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register
+#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register
+#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register
+#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register
+#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A
+#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C
+#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register
+#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value
+// ========== Register definition for TC2 peripheral ==========
+#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register
+#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value
+#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A
+#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B
+#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register
+#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register
+#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C
+#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register
+#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
+// ========== Register definition for TCB peripheral ==========
+#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register
+#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register
+// ========== Register definition for CAN_MB0 peripheral ==========
+#define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
+#define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register
+#define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register
+#define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register
+#define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
+#define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register
+#define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register
+// ========== Register definition for CAN_MB1 peripheral ==========
+#define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
+#define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register
+#define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register
+#define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register
+#define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register
+#define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register
+#define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
+// ========== Register definition for CAN_MB2 peripheral ==========
+#define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register
+#define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register
+#define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register
+#define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
+#define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register
+#define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
+#define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register
+// ========== Register definition for CAN_MB3 peripheral ==========
+#define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
+#define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register
+#define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register
+#define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register
+#define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register
+#define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
+#define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register
+// ========== Register definition for CAN_MB4 peripheral ==========
+#define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register
+#define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register
+#define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register
+#define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
+#define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register
+#define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register
+#define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
+#define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB5 peripheral ==========
+#define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register
+#define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register
+#define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
+#define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
+#define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register
+#define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
+#define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
+#define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB6 peripheral ==========
+#define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
+#define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register
+#define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register
+#define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
+#define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register
+#define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
+#define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
+// ========== Register definition for CAN_MB7 peripheral ==========
+#define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register
+#define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
+#define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
+#define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
+#define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register
+#define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
+#define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register
+// ========== Register definition for CAN peripheral ==========
+#define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register
+#define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register
+#define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register
+#define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register
+#define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register
+#define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register
+#define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register
+#define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register
+#define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register
+#define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register
+#define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register
+#define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register
+// ========== Register definition for EMAC peripheral ==========
+#define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register
+#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
+#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
+#define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register
+#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register
+#define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
+#define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register
+#define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
+#define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register
+#define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register
+#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
+#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register
+#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
+#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register
+#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register
+#define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register
+#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register
+#define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register
+#define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
+#define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
+#define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register
+#define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register
+#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
+#define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register
+#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register
+#define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register
+#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
+#define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
+#define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register
+#define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32]
+#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register
+#define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
+#define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
+#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register
+#define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register
+#define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register
+#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register
+#define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register
+#define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register
+#define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register
+#define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register
+#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
+#define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register
+#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register
+#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
+#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register
+#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
+#define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register
+#define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register
+// ========== Register definition for PDC_ADC peripheral ==========
+#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
+#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
+#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
+#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
+#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
+#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
+#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register
+#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register
+#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
+#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register
+// ========== Register definition for ADC peripheral ==========
+#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2
+#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3
+#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0
+#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5
+#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register
+#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register
+#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4
+#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1
+#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register
+#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register
+#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register
+#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7
+#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6
+#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register
+#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register
+#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register
+#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register
+#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register
+// ========== Register definition for PDC_AES peripheral ==========
+#define AT91C_AES_TPR ((AT91_REG *) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register
+#define AT91C_AES_PTCR ((AT91_REG *) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
+#define AT91C_AES_RNPR ((AT91_REG *) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
+#define AT91C_AES_TNCR ((AT91_REG *) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
+#define AT91C_AES_TCR ((AT91_REG *) 0xFFFA410C) // (PDC_AES) Transmit Counter Register
+#define AT91C_AES_RCR ((AT91_REG *) 0xFFFA4104) // (PDC_AES) Receive Counter Register
+#define AT91C_AES_RNCR ((AT91_REG *) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register
+#define AT91C_AES_TNPR ((AT91_REG *) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
+#define AT91C_AES_RPR ((AT91_REG *) 0xFFFA4100) // (PDC_AES) Receive Pointer Register
+#define AT91C_AES_PTSR ((AT91_REG *) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
+// ========== Register definition for AES peripheral ==========
+#define AT91C_AES_IVxR ((AT91_REG *) 0xFFFA4060) // (AES) Initialization Vector x Register
+#define AT91C_AES_MR ((AT91_REG *) 0xFFFA4004) // (AES) Mode Register
+#define AT91C_AES_VR ((AT91_REG *) 0xFFFA40FC) // (AES) AES Version Register
+#define AT91C_AES_ODATAxR ((AT91_REG *) 0xFFFA4050) // (AES) Output Data x Register
+#define AT91C_AES_IDATAxR ((AT91_REG *) 0xFFFA4040) // (AES) Input Data x Register
+#define AT91C_AES_CR ((AT91_REG *) 0xFFFA4000) // (AES) Control Register
+#define AT91C_AES_IDR ((AT91_REG *) 0xFFFA4014) // (AES) Interrupt Disable Register
+#define AT91C_AES_IMR ((AT91_REG *) 0xFFFA4018) // (AES) Interrupt Mask Register
+#define AT91C_AES_IER ((AT91_REG *) 0xFFFA4010) // (AES) Interrupt Enable Register
+#define AT91C_AES_KEYWxR ((AT91_REG *) 0xFFFA4020) // (AES) Key Word x Register
+#define AT91C_AES_ISR ((AT91_REG *) 0xFFFA401C) // (AES) Interrupt Status Register
+// ========== Register definition for PDC_TDES peripheral ==========
+#define AT91C_TDES_RNCR ((AT91_REG *) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
+#define AT91C_TDES_TCR ((AT91_REG *) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register
+#define AT91C_TDES_RCR ((AT91_REG *) 0xFFFA8104) // (PDC_TDES) Receive Counter Register
+#define AT91C_TDES_TNPR ((AT91_REG *) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
+#define AT91C_TDES_RNPR ((AT91_REG *) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
+#define AT91C_TDES_RPR ((AT91_REG *) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register
+#define AT91C_TDES_TNCR ((AT91_REG *) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
+#define AT91C_TDES_TPR ((AT91_REG *) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
+#define AT91C_TDES_PTSR ((AT91_REG *) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
+#define AT91C_TDES_PTCR ((AT91_REG *) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
+// ========== Register definition for TDES peripheral ==========
+#define AT91C_TDES_KEY2WxR ((AT91_REG *) 0xFFFA8028) // (TDES) Key 2 Word x Register
+#define AT91C_TDES_KEY3WxR ((AT91_REG *) 0xFFFA8030) // (TDES) Key 3 Word x Register
+#define AT91C_TDES_IDR ((AT91_REG *) 0xFFFA8014) // (TDES) Interrupt Disable Register
+#define AT91C_TDES_VR ((AT91_REG *) 0xFFFA80FC) // (TDES) TDES Version Register
+#define AT91C_TDES_IVxR ((AT91_REG *) 0xFFFA8060) // (TDES) Initialization Vector x Register
+#define AT91C_TDES_ODATAxR ((AT91_REG *) 0xFFFA8050) // (TDES) Output Data x Register
+#define AT91C_TDES_IMR ((AT91_REG *) 0xFFFA8018) // (TDES) Interrupt Mask Register
+#define AT91C_TDES_MR ((AT91_REG *) 0xFFFA8004) // (TDES) Mode Register
+#define AT91C_TDES_CR ((AT91_REG *) 0xFFFA8000) // (TDES) Control Register
+#define AT91C_TDES_IER ((AT91_REG *) 0xFFFA8010) // (TDES) Interrupt Enable Register
+#define AT91C_TDES_ISR ((AT91_REG *) 0xFFFA801C) // (TDES) Interrupt Status Register
+#define AT91C_TDES_IDATAxR ((AT91_REG *) 0xFFFA8040) // (TDES) Input Data x Register
+#define AT91C_TDES_KEY1WxR ((AT91_REG *) 0xFFFA8020) // (TDES) Key 1 Word x Register
+
+// *****************************************************************************
+// PIO DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0
+#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data
+#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1
+#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data
+#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10
+#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data
+#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11
+#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock
+#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12
+#define AT91C_PA12_NPCS00 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0
+#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13
+#define AT91C_PA13_NPCS01 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1
+#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1
+#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14
+#define AT91C_PA14_NPCS02 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2
+#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1
+#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15
+#define AT91C_PA15_NPCS03 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3
+#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input
+#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16
+#define AT91C_PA16_MISO0 ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave
+#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17
+#define AT91C_PA17_MOSI0 ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave
+#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18
+#define AT91C_PA18_SPCK0 ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock
+#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19
+#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive
+#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2
+#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock
+#define AT91C_PA2_NPCS11 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20
+#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit
+#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21
+#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync
+#define AT91C_PA21_NPCS10 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0
+#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22
+#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock
+#define AT91C_PA22_SPCK1 ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock
+#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23
+#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data
+#define AT91C_PA23_MOSI1 ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave
+#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24
+#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data
+#define AT91C_PA24_MISO1 ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave
+#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25
+#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock
+#define AT91C_PA25_NPCS11 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26
+#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync
+#define AT91C_PA26_NPCS12 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27
+#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data
+#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3
+#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28
+#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data
+#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29
+#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input
+#define AT91C_PA29_NPCS13 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3
+#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send
+#define AT91C_PA3_NPCS12 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30
+#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0
+#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2
+#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4
+#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send
+#define AT91C_PA4_NPCS13 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5
+#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data
+#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6
+#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data
+#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7
+#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock
+#define AT91C_PA7_NPCS01 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8
+#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send
+#define AT91C_PA8_NPCS02 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9
+#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send
+#define AT91C_PA9_NPCS03 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0
+#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock
+#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0
+#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1
+#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable
+#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10
+#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2
+#define AT91C_PB10_NPCS11 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11
+#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3
+#define AT91C_PB11_NPCS12 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12
+#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error
+#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input
+#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13
+#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2
+#define AT91C_PB13_NPCS01 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14
+#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3
+#define AT91C_PB14_NPCS02 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15
+#define AT91C_PB15_ERXDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid
+#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16
+#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected
+#define AT91C_PB16_NPCS13 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17
+#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock
+#define AT91C_PB17_NPCS03 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18
+#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec
+#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger
+#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19
+#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0
+#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input
+#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2
+#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0
+#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20
+#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1
+#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0
+#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21
+#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2
+#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1
+#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22
+#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3
+#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2
+#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23
+#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A
+#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect
+#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24
+#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B
+#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready
+#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25
+#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A
+#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready
+#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26
+#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B
+#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator
+#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27
+#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A
+#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0
+#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28
+#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B
+#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1
+#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29
+#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1
+#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2
+#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3
+#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1
+#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30
+#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2
+#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3
+#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4
+#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
+#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5
+#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0
+#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6
+#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1
+#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7
+#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error
+#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8
+#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock
+#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9
+#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output
+
+// *****************************************************************************
+// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ)
+#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral
+#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A
+#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B
+#define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0
+#define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1
+#define AT91C_ID_US0 ((unsigned int) 6) // USART 0
+#define AT91C_ID_US1 ((unsigned int) 7) // USART 1
+#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller
+#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface
+#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller
+#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port
+#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0
+#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1
+#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2
+#define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller
+#define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC
+#define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter
+#define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit
+#define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard
+#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
+#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
+#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
+#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
+#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
+#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
+#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
+#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
+#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
+#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
+#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
+#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
+
+// *****************************************************************************
+// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address
+#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address
+#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address
+#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address
+#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address
+#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address
+#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address
+#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address
+#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address
+#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address
+#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address
+#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address
+#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address
+#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address
+#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address
+#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address
+#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address
+#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address
+#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address
+#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address
+#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address
+#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address
+#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address
+#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address
+#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address
+#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address
+#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address
+#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address
+#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address
+#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address
+#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address
+#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address
+#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address
+#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address
+#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address
+#define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address
+#define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address
+#define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address
+#define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address
+#define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address
+#define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address
+#define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address
+#define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address
+#define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address
+#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address
+#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address
+#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address
+#define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address
+#define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address
+#define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address
+#define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address
+
+// *****************************************************************************
+// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address
+#define AT91C_ISRAM_SIZE ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte)
+#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address
+#define AT91C_IFLASH_SIZE ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte)
+
+
+
+// - Hardware register definition
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR System Peripherals
+// - *****************************************************************************
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
+// - *****************************************************************************
+// - -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
+#if 0 /*_RB_*/
+AT91C_AIC_PRIOR EQU (0x7 << 0) ;- (AIC) Priority Level
+AT91C_AIC_PRIOR_LOWEST EQU (0x0) ;- (AIC) Lowest priority level
+AT91C_AIC_PRIOR_HIGHEST EQU (0x7) ;- (AIC) Highest priority level
+AT91C_AIC_SRCTYPE EQU (0x3 << 5) ;- (AIC) Interrupt Source Type
+AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL EQU (0x0 << 5) ;- (AIC) Internal Sources Code Label High-level Sensitive
+AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL EQU (0x0 << 5) ;- (AIC) External Sources Code Label Low-level Sensitive
+AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE EQU (0x1 << 5) ;- (AIC) Internal Sources Code Label Positive Edge triggered
+AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE EQU (0x1 << 5) ;- (AIC) External Sources Code Label Negative Edge triggered
+AT91C_AIC_SRCTYPE_HIGH_LEVEL EQU (0x2 << 5) ;- (AIC) Internal Or External Sources Code Label High-level Sensitive
+AT91C_AIC_SRCTYPE_POSITIVE_EDGE EQU (0x3 << 5) ;- (AIC) Internal Or External Sources Code Label Positive Edge triggered
+// - -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
+AT91C_AIC_NFIQ EQU (0x1 << 0) ;- (AIC) NFIQ Status
+AT91C_AIC_NIRQ EQU (0x1 << 1) ;- (AIC) NIRQ Status
+// - -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
+AT91C_AIC_DCR_PROT EQU (0x1 << 0) ;- (AIC) Protection Mode
+AT91C_AIC_DCR_GMSK EQU (0x1 << 1) ;- (AIC) General Mask
+#endif
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Peripheral DMA Controller
+// - *****************************************************************************
+// - -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
+AT91C_PDC_RXTEN EQU (0x1 << 0) ;- (PDC) Receiver Transfer Enable
+AT91C_PDC_RXTDIS EQU (0x1 << 1) ;- (PDC) Receiver Transfer Disable
+AT91C_PDC_TXTEN EQU (0x1 << 8) ;- (PDC) Transmitter Transfer Enable
+AT91C_PDC_TXTDIS EQU (0x1 << 9) ;- (PDC) Transmitter Transfer Disable
+// - -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Debug Unit
+// - *****************************************************************************
+// - -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
+AT91C_US_RSTRX EQU (0x1 << 2) ;- (DBGU) Reset Receiver
+AT91C_US_RSTTX EQU (0x1 << 3) ;- (DBGU) Reset Transmitter
+AT91C_US_RXEN EQU (0x1 << 4) ;- (DBGU) Receiver Enable
+AT91C_US_RXDIS EQU (0x1 << 5) ;- (DBGU) Receiver Disable
+AT91C_US_TXEN EQU (0x1 << 6) ;- (DBGU) Transmitter Enable
+AT91C_US_TXDIS EQU (0x1 << 7) ;- (DBGU) Transmitter Disable
+AT91C_US_RSTSTA EQU (0x1 << 8) ;- (DBGU) Reset Status Bits
+// - -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
+AT91C_US_PAR EQU (0x7 << 9) ;- (DBGU) Parity type
+AT91C_US_PAR_EVEN EQU (0x0 << 9) ;- (DBGU) Even Parity
+AT91C_US_PAR_ODD EQU (0x1 << 9) ;- (DBGU) Odd Parity
+AT91C_US_PAR_SPACE EQU (0x2 << 9) ;- (DBGU) Parity forced to 0 (Space)
+AT91C_US_PAR_MARK EQU (0x3 << 9) ;- (DBGU) Parity forced to 1 (Mark)
+AT91C_US_PAR_NONE EQU (0x4 << 9) ;- (DBGU) No Parity
+AT91C_US_PAR_MULTI_DROP EQU (0x6 << 9) ;- (DBGU) Multi-drop mode
+AT91C_US_CHMODE EQU (0x3 << 14) ;- (DBGU) Channel Mode
+AT91C_US_CHMODE_NORMAL EQU (0x0 << 14) ;- (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+AT91C_US_CHMODE_AUTO EQU (0x1 << 14) ;- (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+AT91C_US_CHMODE_LOCAL EQU (0x2 << 14) ;- (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+AT91C_US_CHMODE_REMOTE EQU (0x3 << 14) ;- (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// - -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
+AT91C_US_RXRDY EQU (0x1 << 0) ;- (DBGU) RXRDY Interrupt
+AT91C_US_TXRDY EQU (0x1 << 1) ;- (DBGU) TXRDY Interrupt
+AT91C_US_ENDRX EQU (0x1 << 3) ;- (DBGU) End of Receive Transfer Interrupt
+AT91C_US_ENDTX EQU (0x1 << 4) ;- (DBGU) End of Transmit Interrupt
+AT91C_US_OVRE EQU (0x1 << 5) ;- (DBGU) Overrun Interrupt
+AT91C_US_FRAME EQU (0x1 << 6) ;- (DBGU) Framing Error Interrupt
+AT91C_US_PARE EQU (0x1 << 7) ;- (DBGU) Parity Error Interrupt
+AT91C_US_TXEMPTY EQU (0x1 << 9) ;- (DBGU) TXEMPTY Interrupt
+AT91C_US_TXBUFE EQU (0x1 << 11) ;- (DBGU) TXBUFE Interrupt
+AT91C_US_RXBUFF EQU (0x1 << 12) ;- (DBGU) RXBUFF Interrupt
+AT91C_US_COMM_TX EQU (0x1 << 30) ;- (DBGU) COMM_TX Interrupt
+AT91C_US_COMM_RX EQU (0x1 << 31) ;- (DBGU) COMM_RX Interrupt
+// - -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
+// - -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
+// - -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
+// - -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
+AT91C_US_FORCE_NTRST EQU (0x1 << 0) ;- (DBGU) Force NTRST in JTAG
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Parallel Input Output Controler
+// - *****************************************************************************
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Clock Generator Controler
+// - *****************************************************************************
+// - -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
+AT91C_CKGR_MOSCEN EQU (0x1 << 0) ;- (CKGR) Main Oscillator Enable
+AT91C_CKGR_OSCBYPASS EQU (0x1 << 1) ;- (CKGR) Main Oscillator Bypass
+AT91C_CKGR_OSCOUNT EQU (0xFF << 8) ;- (CKGR) Main Oscillator Start-up Time
+// - -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
+AT91C_CKGR_MAINF EQU (0xFFFF << 0) ;- (CKGR) Main Clock Frequency
+AT91C_CKGR_MAINRDY EQU (0x1 << 16) ;- (CKGR) Main Clock Ready
+// - -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
+AT91C_CKGR_DIV EQU (0xFF << 0) ;- (CKGR) Divider Selected
+AT91C_CKGR_DIV_0 EQU (0x0) ;- (CKGR) Divider output is 0
+AT91C_CKGR_DIV_BYPASS EQU (0x1) ;- (CKGR) Divider is bypassed
+AT91C_CKGR_PLLCOUNT EQU (0x3F << 8) ;- (CKGR) PLL Counter
+AT91C_CKGR_OUT EQU (0x3 << 14) ;- (CKGR) PLL Output Frequency Range
+AT91C_CKGR_OUT_0 EQU (0x0 << 14) ;- (CKGR) Please refer to the PLL datasheet
+AT91C_CKGR_OUT_1 EQU (0x1 << 14) ;- (CKGR) Please refer to the PLL datasheet
+AT91C_CKGR_OUT_2 EQU (0x2 << 14) ;- (CKGR) Please refer to the PLL datasheet
+AT91C_CKGR_OUT_3 EQU (0x3 << 14) ;- (CKGR) Please refer to the PLL datasheet
+AT91C_CKGR_MUL EQU (0x7FF << 16) ;- (CKGR) PLL Multiplier
+AT91C_CKGR_USBDIV EQU (0x3 << 28) ;- (CKGR) Divider for USB Clocks
+AT91C_CKGR_USBDIV_0 EQU (0x0 << 28) ;- (CKGR) Divider output is PLL clock output
+AT91C_CKGR_USBDIV_1 EQU (0x1 << 28) ;- (CKGR) Divider output is PLL clock output divided by 2
+AT91C_CKGR_USBDIV_2 EQU (0x2 << 28) ;- (CKGR) Divider output is PLL clock output divided by 4
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Power Management Controler
+// - *****************************************************************************
+// - -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
+AT91C_PMC_PCK EQU (0x1 << 0) ;- (PMC) Processor Clock
+AT91C_PMC_UDP EQU (0x1 << 7) ;- (PMC) USB Device Port Clock
+AT91C_PMC_PCK0 EQU (0x1 << 8) ;- (PMC) Programmable Clock Output
+AT91C_PMC_PCK1 EQU (0x1 << 9) ;- (PMC) Programmable Clock Output
+AT91C_PMC_PCK2 EQU (0x1 << 10) ;- (PMC) Programmable Clock Output
+AT91C_PMC_PCK3 EQU (0x1 << 11) ;- (PMC) Programmable Clock Output
+// - -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
+// - -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
+// - -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
+// - -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
+// - -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
+// - -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
+AT91C_PMC_CSS EQU (0x3 << 0) ;- (PMC) Programmable Clock Selection
+AT91C_PMC_CSS_SLOW_CLK EQU (0x0) ;- (PMC) Slow Clock is selected
+AT91C_PMC_CSS_MAIN_CLK EQU (0x1) ;- (PMC) Main Clock is selected
+AT91C_PMC_CSS_PLL_CLK EQU (0x3) ;- (PMC) Clock from PLL is selected
+AT91C_PMC_PRES EQU (0x7 << 2) ;- (PMC) Programmable Clock Prescaler
+AT91C_PMC_PRES_CLK EQU (0x0 << 2) ;- (PMC) Selected clock
+AT91C_PMC_PRES_CLK_2 EQU (0x1 << 2) ;- (PMC) Selected clock divided by 2
+AT91C_PMC_PRES_CLK_4 EQU (0x2 << 2) ;- (PMC) Selected clock divided by 4
+AT91C_PMC_PRES_CLK_8 EQU (0x3 << 2) ;- (PMC) Selected clock divided by 8
+AT91C_PMC_PRES_CLK_16 EQU (0x4 << 2) ;- (PMC) Selected clock divided by 16
+AT91C_PMC_PRES_CLK_32 EQU (0x5 << 2) ;- (PMC) Selected clock divided by 32
+AT91C_PMC_PRES_CLK_64 EQU (0x6 << 2) ;- (PMC) Selected clock divided by 64
+// - -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
+// - -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
+AT91C_PMC_MOSCS EQU (0x1 << 0) ;- (PMC) MOSC Status/Enable/Disable/Mask
+AT91C_PMC_LOCK EQU (0x1 << 2) ;- (PMC) PLL Status/Enable/Disable/Mask
+AT91C_PMC_MCKRDY EQU (0x1 << 3) ;- (PMC) MCK_RDY Status/Enable/Disable/Mask
+AT91C_PMC_PCK0RDY EQU (0x1 << 8) ;- (PMC) PCK0_RDY Status/Enable/Disable/Mask
+AT91C_PMC_PCK1RDY EQU (0x1 << 9) ;- (PMC) PCK1_RDY Status/Enable/Disable/Mask
+AT91C_PMC_PCK2RDY EQU (0x1 << 10) ;- (PMC) PCK2_RDY Status/Enable/Disable/Mask
+AT91C_PMC_PCK3RDY EQU (0x1 << 11) ;- (PMC) PCK3_RDY Status/Enable/Disable/Mask
+// - -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
+// - -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
+// - -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Reset Controller Interface
+// - *****************************************************************************
+// - -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
+AT91C_RSTC_PROCRST EQU (0x1 << 0) ;- (RSTC) Processor Reset
+AT91C_RSTC_PERRST EQU (0x1 << 2) ;- (RSTC) Peripheral Reset
+AT91C_RSTC_EXTRST EQU (0x1 << 3) ;- (RSTC) External Reset
+AT91C_RSTC_KEY EQU (0xFF << 24) ;- (RSTC) Password
+// - -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
+AT91C_RSTC_URSTS EQU (0x1 << 0) ;- (RSTC) User Reset Status
+AT91C_RSTC_BODSTS EQU (0x1 << 1) ;- (RSTC) Brownout Detection Status
+AT91C_RSTC_RSTTYP EQU (0x7 << 8) ;- (RSTC) Reset Type
+AT91C_RSTC_RSTTYP_POWERUP EQU (0x0 << 8) ;- (RSTC) Power-up Reset. VDDCORE rising.
+AT91C_RSTC_RSTTYP_WAKEUP EQU (0x1 << 8) ;- (RSTC) WakeUp Reset. VDDCORE rising.
+AT91C_RSTC_RSTTYP_WATCHDOG EQU (0x2 << 8) ;- (RSTC) Watchdog Reset. Watchdog overflow occured.
+AT91C_RSTC_RSTTYP_SOFTWARE EQU (0x3 << 8) ;- (RSTC) Software Reset. Processor reset required by the software.
+AT91C_RSTC_RSTTYP_USER EQU (0x4 << 8) ;- (RSTC) User Reset. NRST pin detected low.
+AT91C_RSTC_RSTTYP_BROWNOUT EQU (0x5 << 8) ;- (RSTC) Brownout Reset occured.
+AT91C_RSTC_NRSTL EQU (0x1 << 16) ;- (RSTC) NRST pin level
+AT91C_RSTC_SRCMP EQU (0x1 << 17) ;- (RSTC) Software Reset Command in Progress.
+// - -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
+AT91C_RSTC_URSTEN EQU (0x1 << 0) ;- (RSTC) User Reset Enable
+AT91C_RSTC_URSTIEN EQU (0x1 << 4) ;- (RSTC) User Reset Interrupt Enable
+AT91C_RSTC_ERSTL EQU (0xF << 8) ;- (RSTC) User Reset Enable
+AT91C_RSTC_BODIEN EQU (0x1 << 16) ;- (RSTC) Brownout Detection Interrupt Enable
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
+// - *****************************************************************************
+// - -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
+AT91C_RTTC_RTPRES EQU (0xFFFF << 0) ;- (RTTC) Real-time Timer Prescaler Value
+AT91C_RTTC_ALMIEN EQU (0x1 << 16) ;- (RTTC) Alarm Interrupt Enable
+AT91C_RTTC_RTTINCIEN EQU (0x1 << 17) ;- (RTTC) Real Time Timer Increment Interrupt Enable
+AT91C_RTTC_RTTRST EQU (0x1 << 18) ;- (RTTC) Real Time Timer Restart
+// - -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
+AT91C_RTTC_ALMV EQU (0x0 << 0) ;- (RTTC) Alarm Value
+// - -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
+AT91C_RTTC_CRTV EQU (0x0 << 0) ;- (RTTC) Current Real-time Value
+// - -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
+AT91C_RTTC_ALMS EQU (0x1 << 0) ;- (RTTC) Real-time Alarm Status
+AT91C_RTTC_RTTINC EQU (0x1 << 1) ;- (RTTC) Real-time Timer Increment
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
+// - *****************************************************************************
+// - -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
+AT91C_PITC_PIV EQU (0xFFFFF << 0) ;- (PITC) Periodic Interval Value
+AT91C_PITC_PITEN EQU (0x1 << 24) ;- (PITC) Periodic Interval Timer Enabled
+AT91C_PITC_PITIEN EQU (0x1 << 25) ;- (PITC) Periodic Interval Timer Interrupt Enable
+// - -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
+AT91C_PITC_PITS EQU (0x1 << 0) ;- (PITC) Periodic Interval Timer Status
+// - -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
+AT91C_PITC_CPIV EQU (0xFFFFF << 0) ;- (PITC) Current Periodic Interval Value
+AT91C_PITC_PICNT EQU (0xFFF << 20) ;- (PITC) Periodic Interval Counter
+// - -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
+// - *****************************************************************************
+// - -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
+AT91C_WDTC_WDRSTT EQU (0x1 << 0) ;- (WDTC) Watchdog Restart
+AT91C_WDTC_KEY EQU (0xFF << 24) ;- (WDTC) Watchdog KEY Password
+// - -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
+AT91C_WDTC_WDV EQU (0xFFF << 0) ;- (WDTC) Watchdog Timer Restart
+AT91C_WDTC_WDFIEN EQU (0x1 << 12) ;- (WDTC) Watchdog Fault Interrupt Enable
+AT91C_WDTC_WDRSTEN EQU (0x1 << 13) ;- (WDTC) Watchdog Reset Enable
+AT91C_WDTC_WDRPROC EQU (0x1 << 14) ;- (WDTC) Watchdog Timer Restart
+AT91C_WDTC_WDDIS EQU (0x1 << 15) ;- (WDTC) Watchdog Disable
+AT91C_WDTC_WDD EQU (0xFFF << 16) ;- (WDTC) Watchdog Delta Value
+AT91C_WDTC_WDDBGHLT EQU (0x1 << 28) ;- (WDTC) Watchdog Debug Halt
+AT91C_WDTC_WDIDLEHLT EQU (0x1 << 29) ;- (WDTC) Watchdog Idle Halt
+// - -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
+AT91C_WDTC_WDUNF EQU (0x1 << 0) ;- (WDTC) Watchdog Underflow
+AT91C_WDTC_WDERR EQU (0x1 << 1) ;- (WDTC) Watchdog Error
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface
+// - *****************************************************************************
+// - -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
+AT91C_VREG_PSTDBY EQU (0x1 << 0) ;- (VREG) Voltage Regulator Power Standby Mode
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Memory Controller Interface
+// - *****************************************************************************
+// - -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
+AT91C_MC_RCB EQU (0x1 << 0) ;- (MC) Remap Command Bit
+// - -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
+AT91C_MC_UNDADD EQU (0x1 << 0) ;- (MC) Undefined Addess Abort Status
+AT91C_MC_MISADD EQU (0x1 << 1) ;- (MC) Misaligned Addess Abort Status
+AT91C_MC_ABTSZ EQU (0x3 << 8) ;- (MC) Abort Size Status
+AT91C_MC_ABTSZ_BYTE EQU (0x0 << 8) ;- (MC) Byte
+AT91C_MC_ABTSZ_HWORD EQU (0x1 << 8) ;- (MC) Half-word
+AT91C_MC_ABTSZ_WORD EQU (0x2 << 8) ;- (MC) Word
+AT91C_MC_ABTTYP EQU (0x3 << 10) ;- (MC) Abort Type Status
+AT91C_MC_ABTTYP_DATAR EQU (0x0 << 10) ;- (MC) Data Read
+AT91C_MC_ABTTYP_DATAW EQU (0x1 << 10) ;- (MC) Data Write
+AT91C_MC_ABTTYP_FETCH EQU (0x2 << 10) ;- (MC) Code Fetch
+AT91C_MC_MST0 EQU (0x1 << 16) ;- (MC) Master 0 Abort Source
+AT91C_MC_MST1 EQU (0x1 << 17) ;- (MC) Master 1 Abort Source
+AT91C_MC_SVMST0 EQU (0x1 << 24) ;- (MC) Saved Master 0 Abort Source
+AT91C_MC_SVMST1 EQU (0x1 << 25) ;- (MC) Saved Master 1 Abort Source
+// - -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
+AT91C_MC_FRDY EQU (0x1 << 0) ;- (MC) Flash Ready
+AT91C_MC_LOCKE EQU (0x1 << 2) ;- (MC) Lock Error
+AT91C_MC_PROGE EQU (0x1 << 3) ;- (MC) Programming Error
+AT91C_MC_NEBP EQU (0x1 << 7) ;- (MC) No Erase Before Programming
+AT91C_MC_FWS EQU (0x3 << 8) ;- (MC) Flash Wait State
+AT91C_MC_FWS_0FWS EQU (0x0 << 8) ;- (MC) 1 cycle for Read, 2 for Write operations
+AT91C_MC_FWS_1FWS EQU (0x1 << 8) ;- (MC) 2 cycles for Read, 3 for Write operations
+AT91C_MC_FWS_2FWS EQU (0x2 << 8) ;- (MC) 3 cycles for Read, 4 for Write operations
+AT91C_MC_FWS_3FWS EQU (0x3 << 8) ;- (MC) 4 cycles for Read, 4 for Write operations
+AT91C_MC_FMCN EQU (0xFF << 16) ;- (MC) Flash Microsecond Cycle Number
+// - -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
+AT91C_MC_FCMD EQU (0xF << 0) ;- (MC) Flash Command
+AT91C_MC_FCMD_START_PROG EQU (0x1) ;- (MC) Starts the programming of th epage specified by PAGEN.
+AT91C_MC_FCMD_LOCK EQU (0x2) ;- (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+AT91C_MC_FCMD_PROG_AND_LOCK EQU (0x3) ;- (MC) The lock sequence automatically happens after the programming sequence is completed.
+AT91C_MC_FCMD_UNLOCK EQU (0x4) ;- (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+AT91C_MC_FCMD_ERASE_ALL EQU (0x8) ;- (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
+AT91C_MC_FCMD_SET_GP_NVM EQU (0xB) ;- (MC) Set General Purpose NVM bits.
+AT91C_MC_FCMD_CLR_GP_NVM EQU (0xD) ;- (MC) Clear General Purpose NVM bits.
+AT91C_MC_FCMD_SET_SECURITY EQU (0xF) ;- (MC) Set Security Bit.
+AT91C_MC_PAGEN EQU (0x3FF << 8) ;- (MC) Page Number
+AT91C_MC_KEY EQU (0xFF << 24) ;- (MC) Writing Protect Key
+// - -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
+AT91C_MC_SECURITY EQU (0x1 << 4) ;- (MC) Security Bit Status
+AT91C_MC_GPNVM0 EQU (0x1 << 8) ;- (MC) Sector 0 Lock Status
+AT91C_MC_GPNVM1 EQU (0x1 << 9) ;- (MC) Sector 1 Lock Status
+AT91C_MC_GPNVM2 EQU (0x1 << 10) ;- (MC) Sector 2 Lock Status
+AT91C_MC_GPNVM3 EQU (0x1 << 11) ;- (MC) Sector 3 Lock Status
+AT91C_MC_GPNVM4 EQU (0x1 << 12) ;- (MC) Sector 4 Lock Status
+AT91C_MC_GPNVM5 EQU (0x1 << 13) ;- (MC) Sector 5 Lock Status
+AT91C_MC_GPNVM6 EQU (0x1 << 14) ;- (MC) Sector 6 Lock Status
+AT91C_MC_GPNVM7 EQU (0x1 << 15) ;- (MC) Sector 7 Lock Status
+AT91C_MC_LOCKS0 EQU (0x1 << 16) ;- (MC) Sector 0 Lock Status
+AT91C_MC_LOCKS1 EQU (0x1 << 17) ;- (MC) Sector 1 Lock Status
+AT91C_MC_LOCKS2 EQU (0x1 << 18) ;- (MC) Sector 2 Lock Status
+AT91C_MC_LOCKS3 EQU (0x1 << 19) ;- (MC) Sector 3 Lock Status
+AT91C_MC_LOCKS4 EQU (0x1 << 20) ;- (MC) Sector 4 Lock Status
+AT91C_MC_LOCKS5 EQU (0x1 << 21) ;- (MC) Sector 5 Lock Status
+AT91C_MC_LOCKS6 EQU (0x1 << 22) ;- (MC) Sector 6 Lock Status
+AT91C_MC_LOCKS7 EQU (0x1 << 23) ;- (MC) Sector 7 Lock Status
+AT91C_MC_LOCKS8 EQU (0x1 << 24) ;- (MC) Sector 8 Lock Status
+AT91C_MC_LOCKS9 EQU (0x1 << 25) ;- (MC) Sector 9 Lock Status
+AT91C_MC_LOCKS10 EQU (0x1 << 26) ;- (MC) Sector 10 Lock Status
+AT91C_MC_LOCKS11 EQU (0x1 << 27) ;- (MC) Sector 11 Lock Status
+AT91C_MC_LOCKS12 EQU (0x1 << 28) ;- (MC) Sector 12 Lock Status
+AT91C_MC_LOCKS13 EQU (0x1 << 29) ;- (MC) Sector 13 Lock Status
+AT91C_MC_LOCKS14 EQU (0x1 << 30) ;- (MC) Sector 14 Lock Status
+AT91C_MC_LOCKS15 EQU (0x1 << 31) ;- (MC) Sector 15 Lock Status
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Serial Parallel Interface
+// - *****************************************************************************
+// - -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
+AT91C_SPI_SPIEN EQU (0x1 << 0) ;- (SPI) SPI Enable
+AT91C_SPI_SPIDIS EQU (0x1 << 1) ;- (SPI) SPI Disable
+AT91C_SPI_SWRST EQU (0x1 << 7) ;- (SPI) SPI Software reset
+AT91C_SPI_LASTXFER EQU (0x1 << 24) ;- (SPI) SPI Last Transfer
+// - -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
+AT91C_SPI_MSTR EQU (0x1 << 0) ;- (SPI) Master/Slave Mode
+AT91C_SPI_PS EQU (0x1 << 1) ;- (SPI) Peripheral Select
+AT91C_SPI_PS_FIXED EQU (0x0 << 1) ;- (SPI) Fixed Peripheral Select
+AT91C_SPI_PS_VARIABLE EQU (0x1 << 1) ;- (SPI) Variable Peripheral Select
+AT91C_SPI_PCSDEC EQU (0x1 << 2) ;- (SPI) Chip Select Decode
+AT91C_SPI_FDIV EQU (0x1 << 3) ;- (SPI) Clock Selection
+AT91C_SPI_MODFDIS EQU (0x1 << 4) ;- (SPI) Mode Fault Detection
+AT91C_SPI_LLB EQU (0x1 << 7) ;- (SPI) Clock Selection
+AT91C_SPI_PCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select
+AT91C_SPI_DLYBCS EQU (0xFF << 24) ;- (SPI) Delay Between Chip Selects
+// - -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
+AT91C_SPI_RD EQU (0xFFFF << 0) ;- (SPI) Receive Data
+AT91C_SPI_RPCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status
+// - -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
+AT91C_SPI_TD EQU (0xFFFF << 0) ;- (SPI) Transmit Data
+AT91C_SPI_TPCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status
+// - -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
+AT91C_SPI_RDRF EQU (0x1 << 0) ;- (SPI) Receive Data Register Full
+AT91C_SPI_TDRE EQU (0x1 << 1) ;- (SPI) Transmit Data Register Empty
+AT91C_SPI_MODF EQU (0x1 << 2) ;- (SPI) Mode Fault Error
+AT91C_SPI_OVRES EQU (0x1 << 3) ;- (SPI) Overrun Error Status
+AT91C_SPI_ENDRX EQU (0x1 << 4) ;- (SPI) End of Receiver Transfer
+AT91C_SPI_ENDTX EQU (0x1 << 5) ;- (SPI) End of Receiver Transfer
+AT91C_SPI_RXBUFF EQU (0x1 << 6) ;- (SPI) RXBUFF Interrupt
+AT91C_SPI_TXBUFE EQU (0x1 << 7) ;- (SPI) TXBUFE Interrupt
+AT91C_SPI_NSSR EQU (0x1 << 8) ;- (SPI) NSSR Interrupt
+AT91C_SPI_TXEMPTY EQU (0x1 << 9) ;- (SPI) TXEMPTY Interrupt
+AT91C_SPI_SPIENS EQU (0x1 << 16) ;- (SPI) Enable Status
+// - -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
+// - -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
+// - -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
+// - -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
+AT91C_SPI_CPOL EQU (0x1 << 0) ;- (SPI) Clock Polarity
+AT91C_SPI_NCPHA EQU (0x1 << 1) ;- (SPI) Clock Phase
+AT91C_SPI_CSAAT EQU (0x1 << 3) ;- (SPI) Chip Select Active After Transfer
+AT91C_SPI_BITS EQU (0xF << 4) ;- (SPI) Bits Per Transfer
+AT91C_SPI_BITS_8 EQU (0x0 << 4) ;- (SPI) 8 Bits Per transfer
+AT91C_SPI_BITS_9 EQU (0x1 << 4) ;- (SPI) 9 Bits Per transfer
+AT91C_SPI_BITS_10 EQU (0x2 << 4) ;- (SPI) 10 Bits Per transfer
+AT91C_SPI_BITS_11 EQU (0x3 << 4) ;- (SPI) 11 Bits Per transfer
+AT91C_SPI_BITS_12 EQU (0x4 << 4) ;- (SPI) 12 Bits Per transfer
+AT91C_SPI_BITS_13 EQU (0x5 << 4) ;- (SPI) 13 Bits Per transfer
+AT91C_SPI_BITS_14 EQU (0x6 << 4) ;- (SPI) 14 Bits Per transfer
+AT91C_SPI_BITS_15 EQU (0x7 << 4) ;- (SPI) 15 Bits Per transfer
+AT91C_SPI_BITS_16 EQU (0x8 << 4) ;- (SPI) 16 Bits Per transfer
+AT91C_SPI_SCBR EQU (0xFF << 8) ;- (SPI) Serial Clock Baud Rate
+AT91C_SPI_DLYBS EQU (0xFF << 16) ;- (SPI) Delay Before SPCK
+AT91C_SPI_DLYBCT EQU (0xFF << 24) ;- (SPI) Delay Between Consecutive Transfers
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Usart
+// - *****************************************************************************
+// - -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
+AT91C_US_STTBRK EQU (0x1 << 9) ;- (USART) Start Break
+AT91C_US_STPBRK EQU (0x1 << 10) ;- (USART) Stop Break
+AT91C_US_STTTO EQU (0x1 << 11) ;- (USART) Start Time-out
+AT91C_US_SENDA EQU (0x1 << 12) ;- (USART) Send Address
+AT91C_US_RSTIT EQU (0x1 << 13) ;- (USART) Reset Iterations
+AT91C_US_RSTNACK EQU (0x1 << 14) ;- (USART) Reset Non Acknowledge
+AT91C_US_RETTO EQU (0x1 << 15) ;- (USART) Rearm Time-out
+AT91C_US_DTREN EQU (0x1 << 16) ;- (USART) Data Terminal ready Enable
+AT91C_US_DTRDIS EQU (0x1 << 17) ;- (USART) Data Terminal ready Disable
+AT91C_US_RTSEN EQU (0x1 << 18) ;- (USART) Request to Send enable
+AT91C_US_RTSDIS EQU (0x1 << 19) ;- (USART) Request to Send Disable
+// - -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
+AT91C_US_USMODE EQU (0xF << 0) ;- (USART) Usart mode
+AT91C_US_USMODE_NORMAL EQU (0x0) ;- (USART) Normal
+AT91C_US_USMODE_RS485 EQU (0x1) ;- (USART) RS485
+AT91C_US_USMODE_HWHSH EQU (0x2) ;- (USART) Hardware Handshaking
+AT91C_US_USMODE_MODEM EQU (0x3) ;- (USART) Modem
+AT91C_US_USMODE_ISO7816_0 EQU (0x4) ;- (USART) ISO7816 protocol: T = 0
+AT91C_US_USMODE_ISO7816_1 EQU (0x6) ;- (USART) ISO7816 protocol: T = 1
+AT91C_US_USMODE_IRDA EQU (0x8) ;- (USART) IrDA
+AT91C_US_USMODE_SWHSH EQU (0xC) ;- (USART) Software Handshaking
+AT91C_US_CLKS EQU (0x3 << 4) ;- (USART) Clock Selection (Baud Rate generator Input Clock
+AT91C_US_CLKS_CLOCK EQU (0x0 << 4) ;- (USART) Clock
+AT91C_US_CLKS_FDIV1 EQU (0x1 << 4) ;- (USART) fdiv1
+AT91C_US_CLKS_SLOW EQU (0x2 << 4) ;- (USART) slow_clock (ARM)
+AT91C_US_CLKS_EXT EQU (0x3 << 4) ;- (USART) External (SCK)
+AT91C_US_CHRL EQU (0x3 << 6) ;- (USART) Clock Selection (Baud Rate generator Input Clock
+AT91C_US_CHRL_5_BITS EQU (0x0 << 6) ;- (USART) Character Length: 5 bits
+AT91C_US_CHRL_6_BITS EQU (0x1 << 6) ;- (USART) Character Length: 6 bits
+AT91C_US_CHRL_7_BITS EQU (0x2 << 6) ;- (USART) Character Length: 7 bits
+AT91C_US_CHRL_8_BITS EQU (0x3 << 6) ;- (USART) Character Length: 8 bits
+AT91C_US_SYNC EQU (0x1 << 8) ;- (USART) Synchronous Mode Select
+AT91C_US_NBSTOP EQU (0x3 << 12) ;- (USART) Number of Stop bits
+AT91C_US_NBSTOP_1_BIT EQU (0x0 << 12) ;- (USART) 1 stop bit
+AT91C_US_NBSTOP_15_BIT EQU (0x1 << 12) ;- (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+AT91C_US_NBSTOP_2_BIT EQU (0x2 << 12) ;- (USART) 2 stop bits
+AT91C_US_MSBF EQU (0x1 << 16) ;- (USART) Bit Order
+AT91C_US_MODE9 EQU (0x1 << 17) ;- (USART) 9-bit Character length
+AT91C_US_CKLO EQU (0x1 << 18) ;- (USART) Clock Output Select
+AT91C_US_OVER EQU (0x1 << 19) ;- (USART) Over Sampling Mode
+AT91C_US_INACK EQU (0x1 << 20) ;- (USART) Inhibit Non Acknowledge
+AT91C_US_DSNACK EQU (0x1 << 21) ;- (USART) Disable Successive NACK
+AT91C_US_MAX_ITER EQU (0x1 << 24) ;- (USART) Number of Repetitions
+AT91C_US_FILTER EQU (0x1 << 28) ;- (USART) Receive Line Filter
+// - -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
+AT91C_US_RXBRK EQU (0x1 << 2) ;- (USART) Break Received/End of Break
+AT91C_US_TIMEOUT EQU (0x1 << 8) ;- (USART) Receiver Time-out
+AT91C_US_ITERATION EQU (0x1 << 10) ;- (USART) Max number of Repetitions Reached
+AT91C_US_NACK EQU (0x1 << 13) ;- (USART) Non Acknowledge
+AT91C_US_RIIC EQU (0x1 << 16) ;- (USART) Ring INdicator Input Change Flag
+AT91C_US_DSRIC EQU (0x1 << 17) ;- (USART) Data Set Ready Input Change Flag
+AT91C_US_DCDIC EQU (0x1 << 18) ;- (USART) Data Carrier Flag
+AT91C_US_CTSIC EQU (0x1 << 19) ;- (USART) Clear To Send Input Change Flag
+// - -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
+// - -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
+// - -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
+AT91C_US_RI EQU (0x1 << 20) ;- (USART) Image of RI Input
+AT91C_US_DSR EQU (0x1 << 21) ;- (USART) Image of DSR Input
+AT91C_US_DCD EQU (0x1 << 22) ;- (USART) Image of DCD Input
+AT91C_US_CTS EQU (0x1 << 23) ;- (USART) Image of CTS Input
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
+// - *****************************************************************************
+// - -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
+AT91C_SSC_RXEN EQU (0x1 << 0) ;- (SSC) Receive Enable
+AT91C_SSC_RXDIS EQU (0x1 << 1) ;- (SSC) Receive Disable
+AT91C_SSC_TXEN EQU (0x1 << 8) ;- (SSC) Transmit Enable
+AT91C_SSC_TXDIS EQU (0x1 << 9) ;- (SSC) Transmit Disable
+AT91C_SSC_SWRST EQU (0x1 << 15) ;- (SSC) Software Reset
+// - -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
+AT91C_SSC_CKS EQU (0x3 << 0) ;- (SSC) Receive/Transmit Clock Selection
+AT91C_SSC_CKS_DIV EQU (0x0) ;- (SSC) Divided Clock
+AT91C_SSC_CKS_TK EQU (0x1) ;- (SSC) TK Clock signal
+AT91C_SSC_CKS_RK EQU (0x2) ;- (SSC) RK pin
+AT91C_SSC_CKO EQU (0x7 << 2) ;- (SSC) Receive/Transmit Clock Output Mode Selection
+AT91C_SSC_CKO_NONE EQU (0x0 << 2) ;- (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+AT91C_SSC_CKO_CONTINOUS EQU (0x1 << 2) ;- (SSC) Continuous Receive/Transmit Clock RK pin: Output
+AT91C_SSC_CKO_DATA_TX EQU (0x2 << 2) ;- (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+AT91C_SSC_CKI EQU (0x1 << 5) ;- (SSC) Receive/Transmit Clock Inversion
+AT91C_SSC_START EQU (0xF << 8) ;- (SSC) Receive/Transmit Start Selection
+AT91C_SSC_START_CONTINOUS EQU (0x0 << 8) ;- (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+AT91C_SSC_START_TX EQU (0x1 << 8) ;- (SSC) Transmit/Receive start
+AT91C_SSC_START_LOW_RF EQU (0x2 << 8) ;- (SSC) Detection of a low level on RF input
+AT91C_SSC_START_HIGH_RF EQU (0x3 << 8) ;- (SSC) Detection of a high level on RF input
+AT91C_SSC_START_FALL_RF EQU (0x4 << 8) ;- (SSC) Detection of a falling edge on RF input
+AT91C_SSC_START_RISE_RF EQU (0x5 << 8) ;- (SSC) Detection of a rising edge on RF input
+AT91C_SSC_START_LEVEL_RF EQU (0x6 << 8) ;- (SSC) Detection of any level change on RF input
+AT91C_SSC_START_EDGE_RF EQU (0x7 << 8) ;- (SSC) Detection of any edge on RF input
+AT91C_SSC_START_0 EQU (0x8 << 8) ;- (SSC) Compare 0
+AT91C_SSC_STTDLY EQU (0xFF << 16) ;- (SSC) Receive/Transmit Start Delay
+AT91C_SSC_PERIOD EQU (0xFF << 24) ;- (SSC) Receive/Transmit Period Divider Selection
+// - -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
+AT91C_SSC_DATLEN EQU (0x1F << 0) ;- (SSC) Data Length
+AT91C_SSC_LOOP EQU (0x1 << 5) ;- (SSC) Loop Mode
+AT91C_SSC_MSBF EQU (0x1 << 7) ;- (SSC) Most Significant Bit First
+AT91C_SSC_DATNB EQU (0xF << 8) ;- (SSC) Data Number per Frame
+AT91C_SSC_FSLEN EQU (0xF << 16) ;- (SSC) Receive/Transmit Frame Sync length
+AT91C_SSC_FSOS EQU (0x7 << 20) ;- (SSC) Receive/Transmit Frame Sync Output Selection
+AT91C_SSC_FSOS_NONE EQU (0x0 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+AT91C_SSC_FSOS_NEGATIVE EQU (0x1 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+AT91C_SSC_FSOS_POSITIVE EQU (0x2 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+AT91C_SSC_FSOS_LOW EQU (0x3 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+AT91C_SSC_FSOS_HIGH EQU (0x4 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+AT91C_SSC_FSOS_TOGGLE EQU (0x5 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+AT91C_SSC_FSEDGE EQU (0x1 << 24) ;- (SSC) Frame Sync Edge Detection
+// - -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
+// - -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
+AT91C_SSC_DATDEF EQU (0x1 << 5) ;- (SSC) Data Default Value
+AT91C_SSC_FSDEN EQU (0x1 << 23) ;- (SSC) Frame Sync Data Enable
+// - -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
+AT91C_SSC_TXRDY EQU (0x1 << 0) ;- (SSC) Transmit Ready
+AT91C_SSC_TXEMPTY EQU (0x1 << 1) ;- (SSC) Transmit Empty
+AT91C_SSC_ENDTX EQU (0x1 << 2) ;- (SSC) End Of Transmission
+AT91C_SSC_TXBUFE EQU (0x1 << 3) ;- (SSC) Transmit Buffer Empty
+AT91C_SSC_RXRDY EQU (0x1 << 4) ;- (SSC) Receive Ready
+AT91C_SSC_OVRUN EQU (0x1 << 5) ;- (SSC) Receive Overrun
+AT91C_SSC_ENDRX EQU (0x1 << 6) ;- (SSC) End of Reception
+AT91C_SSC_RXBUFF EQU (0x1 << 7) ;- (SSC) Receive Buffer Full
+AT91C_SSC_TXSYN EQU (0x1 << 10) ;- (SSC) Transmit Sync
+AT91C_SSC_RXSYN EQU (0x1 << 11) ;- (SSC) Receive Sync
+AT91C_SSC_TXENA EQU (0x1 << 16) ;- (SSC) Transmit Enable
+AT91C_SSC_RXENA EQU (0x1 << 17) ;- (SSC) Receive Enable
+// - -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
+// - -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
+// - -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Two-wire Interface
+// - *****************************************************************************
+// - -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
+AT91C_TWI_START EQU (0x1 << 0) ;- (TWI) Send a START Condition
+AT91C_TWI_STOP EQU (0x1 << 1) ;- (TWI) Send a STOP Condition
+AT91C_TWI_MSEN EQU (0x1 << 2) ;- (TWI) TWI Master Transfer Enabled
+AT91C_TWI_MSDIS EQU (0x1 << 3) ;- (TWI) TWI Master Transfer Disabled
+AT91C_TWI_SWRST EQU (0x1 << 7) ;- (TWI) Software Reset
+// - -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
+AT91C_TWI_IADRSZ EQU (0x3 << 8) ;- (TWI) Internal Device Address Size
+AT91C_TWI_IADRSZ_NO EQU (0x0 << 8) ;- (TWI) No internal device address
+AT91C_TWI_IADRSZ_1_BYTE EQU (0x1 << 8) ;- (TWI) One-byte internal device address
+AT91C_TWI_IADRSZ_2_BYTE EQU (0x2 << 8) ;- (TWI) Two-byte internal device address
+AT91C_TWI_IADRSZ_3_BYTE EQU (0x3 << 8) ;- (TWI) Three-byte internal device address
+AT91C_TWI_MREAD EQU (0x1 << 12) ;- (TWI) Master Read Direction
+AT91C_TWI_DADR EQU (0x7F << 16) ;- (TWI) Device Address
+// - -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
+AT91C_TWI_CLDIV EQU (0xFF << 0) ;- (TWI) Clock Low Divider
+AT91C_TWI_CHDIV EQU (0xFF << 8) ;- (TWI) Clock High Divider
+AT91C_TWI_CKDIV EQU (0x7 << 16) ;- (TWI) Clock Divider
+// - -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
+AT91C_TWI_TXCOMP EQU (0x1 << 0) ;- (TWI) Transmission Completed
+AT91C_TWI_RXRDY EQU (0x1 << 1) ;- (TWI) Receive holding register ReaDY
+AT91C_TWI_TXRDY EQU (0x1 << 2) ;- (TWI) Transmit holding register ReaDY
+AT91C_TWI_OVRE EQU (0x1 << 6) ;- (TWI) Overrun Error
+AT91C_TWI_UNRE EQU (0x1 << 7) ;- (TWI) Underrun Error
+AT91C_TWI_NACK EQU (0x1 << 8) ;- (TWI) Not Acknowledged
+// - -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
+// - -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
+// - -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR PWMC Channel Interface
+// - *****************************************************************************
+// - -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
+AT91C_PWMC_CPRE EQU (0xF << 0) ;- (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
+AT91C_PWMC_CPRE_MCK EQU (0x0) ;- (PWMC_CH)
+AT91C_PWMC_CPRE_MCKA EQU (0xB) ;- (PWMC_CH)
+AT91C_PWMC_CPRE_MCKB EQU (0xC) ;- (PWMC_CH)
+AT91C_PWMC_CALG EQU (0x1 << 8) ;- (PWMC_CH) Channel Alignment
+AT91C_PWMC_CPOL EQU (0x1 << 9) ;- (PWMC_CH) Channel Polarity
+AT91C_PWMC_CPD EQU (0x1 << 10) ;- (PWMC_CH) Channel Update Period
+// - -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
+AT91C_PWMC_CDTY EQU (0x0 << 0) ;- (PWMC_CH) Channel Duty Cycle
+// - -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
+AT91C_PWMC_CPRD EQU (0x0 << 0) ;- (PWMC_CH) Channel Period
+// - -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
+AT91C_PWMC_CCNT EQU (0x0 << 0) ;- (PWMC_CH) Channel Counter
+// - -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
+AT91C_PWMC_CUPD EQU (0x0 << 0) ;- (PWMC_CH) Channel Update
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
+// - *****************************************************************************
+// - -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
+AT91C_PWMC_DIVA EQU (0xFF << 0) ;- (PWMC) CLKA divide factor.
+AT91C_PWMC_PREA EQU (0xF << 8) ;- (PWMC) Divider Input Clock Prescaler A
+AT91C_PWMC_PREA_MCK EQU (0x0 << 8) ;- (PWMC)
+AT91C_PWMC_DIVB EQU (0xFF << 16) ;- (PWMC) CLKB divide factor.
+AT91C_PWMC_PREB EQU (0xF << 24) ;- (PWMC) Divider Input Clock Prescaler B
+AT91C_PWMC_PREB_MCK EQU (0x0 << 24) ;- (PWMC)
+// - -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
+AT91C_PWMC_CHID0 EQU (0x1 << 0) ;- (PWMC) Channel ID 0
+AT91C_PWMC_CHID1 EQU (0x1 << 1) ;- (PWMC) Channel ID 1
+AT91C_PWMC_CHID2 EQU (0x1 << 2) ;- (PWMC) Channel ID 2
+AT91C_PWMC_CHID3 EQU (0x1 << 3) ;- (PWMC) Channel ID 3
+// - -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
+// - -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
+// - -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
+// - -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
+// - -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
+// - -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR USB Device Interface
+// - *****************************************************************************
+// - -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
+AT91C_UDP_FRM_NUM EQU (0x7FF << 0) ;- (UDP) Frame Number as Defined in the Packet Field Formats
+AT91C_UDP_FRM_ERR EQU (0x1 << 16) ;- (UDP) Frame Error
+AT91C_UDP_FRM_OK EQU (0x1 << 17) ;- (UDP) Frame OK
+// - -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
+AT91C_UDP_FADDEN EQU (0x1 << 0) ;- (UDP) Function Address Enable
+AT91C_UDP_CONFG EQU (0x1 << 1) ;- (UDP) Configured
+AT91C_UDP_ESR EQU (0x1 << 2) ;- (UDP) Enable Send Resume
+AT91C_UDP_RSMINPR EQU (0x1 << 3) ;- (UDP) A Resume Has Been Sent to the Host
+AT91C_UDP_RMWUPE EQU (0x1 << 4) ;- (UDP) Remote Wake Up Enable
+// - -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
+AT91C_UDP_FADD EQU (0xFF << 0) ;- (UDP) Function Address Value
+AT91C_UDP_FEN EQU (0x1 << 8) ;- (UDP) Function Enable
+// - -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
+AT91C_UDP_EPINT0 EQU (0x1 << 0) ;- (UDP) Endpoint 0 Interrupt
+AT91C_UDP_EPINT1 EQU (0x1 << 1) ;- (UDP) Endpoint 0 Interrupt
+AT91C_UDP_EPINT2 EQU (0x1 << 2) ;- (UDP) Endpoint 2 Interrupt
+AT91C_UDP_EPINT3 EQU (0x1 << 3) ;- (UDP) Endpoint 3 Interrupt
+AT91C_UDP_EPINT4 EQU (0x1 << 4) ;- (UDP) Endpoint 4 Interrupt
+AT91C_UDP_EPINT5 EQU (0x1 << 5) ;- (UDP) Endpoint 5 Interrupt
+AT91C_UDP_RXSUSP EQU (0x1 << 8) ;- (UDP) USB Suspend Interrupt
+AT91C_UDP_RXRSM EQU (0x1 << 9) ;- (UDP) USB Resume Interrupt
+AT91C_UDP_EXTRSM EQU (0x1 << 10) ;- (UDP) USB External Resume Interrupt
+AT91C_UDP_SOFINT EQU (0x1 << 11) ;- (UDP) USB Start Of frame Interrupt
+AT91C_UDP_WAKEUP EQU (0x1 << 13) ;- (UDP) USB Resume Interrupt
+// - -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
+// - -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
+// - -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
+AT91C_UDP_ENDBUSRES EQU (0x1 << 12) ;- (UDP) USB End Of Bus Reset Interrupt
+// - -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
+// - -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
+AT91C_UDP_EP0 EQU (0x1 << 0) ;- (UDP) Reset Endpoint 0
+AT91C_UDP_EP1 EQU (0x1 << 1) ;- (UDP) Reset Endpoint 1
+AT91C_UDP_EP2 EQU (0x1 << 2) ;- (UDP) Reset Endpoint 2
+AT91C_UDP_EP3 EQU (0x1 << 3) ;- (UDP) Reset Endpoint 3
+AT91C_UDP_EP4 EQU (0x1 << 4) ;- (UDP) Reset Endpoint 4
+AT91C_UDP_EP5 EQU (0x1 << 5) ;- (UDP) Reset Endpoint 5
+// - -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
+AT91C_UDP_TXCOMP EQU (0x1 << 0) ;- (UDP) Generates an IN packet with data previously written in the DPR
+AT91C_UDP_RX_DATA_BK0 EQU (0x1 << 1) ;- (UDP) Receive Data Bank 0
+AT91C_UDP_RXSETUP EQU (0x1 << 2) ;- (UDP) Sends STALL to the Host (Control endpoints)
+AT91C_UDP_ISOERROR EQU (0x1 << 3) ;- (UDP) Isochronous error (Isochronous endpoints)
+AT91C_UDP_TXPKTRDY EQU (0x1 << 4) ;- (UDP) Transmit Packet Ready
+AT91C_UDP_FORCESTALL EQU (0x1 << 5) ;- (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+AT91C_UDP_RX_DATA_BK1 EQU (0x1 << 6) ;- (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+AT91C_UDP_DIR EQU (0x1 << 7) ;- (UDP) Transfer Direction
+AT91C_UDP_EPTYPE EQU (0x7 << 8) ;- (UDP) Endpoint type
+AT91C_UDP_EPTYPE_CTRL EQU (0x0 << 8) ;- (UDP) Control
+AT91C_UDP_EPTYPE_ISO_OUT EQU (0x1 << 8) ;- (UDP) Isochronous OUT
+AT91C_UDP_EPTYPE_BULK_OUT EQU (0x2 << 8) ;- (UDP) Bulk OUT
+AT91C_UDP_EPTYPE_INT_OUT EQU (0x3 << 8) ;- (UDP) Interrupt OUT
+AT91C_UDP_EPTYPE_ISO_IN EQU (0x5 << 8) ;- (UDP) Isochronous IN
+AT91C_UDP_EPTYPE_BULK_IN EQU (0x6 << 8) ;- (UDP) Bulk IN
+AT91C_UDP_EPTYPE_INT_IN EQU (0x7 << 8) ;- (UDP) Interrupt IN
+AT91C_UDP_DTGLE EQU (0x1 << 11) ;- (UDP) Data Toggle
+AT91C_UDP_EPEDS EQU (0x1 << 15) ;- (UDP) Endpoint Enable Disable
+AT91C_UDP_RXBYTECNT EQU (0x7FF << 16) ;- (UDP) Number Of Bytes Available in the FIFO
+// - -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
+AT91C_UDP_TXVDIS EQU (0x1 << 8) ;- (UDP)
+AT91C_UDP_PUON EQU (0x1 << 9) ;- (UDP) Pull-up ON
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
+// - *****************************************************************************
+// - -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
+AT91C_TC_CLKEN EQU (0x1 << 0) ;- (TC) Counter Clock Enable Command
+AT91C_TC_CLKDIS EQU (0x1 << 1) ;- (TC) Counter Clock Disable Command
+AT91C_TC_SWTRG EQU (0x1 << 2) ;- (TC) Software Trigger Command
+// - -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
+AT91C_TC_CLKS EQU (0x7 << 0) ;- (TC) Clock Selection
+AT91C_TC_CLKS_TIMER_DIV1_CLOCK EQU (0x0) ;- (TC) Clock selected: TIMER_DIV1_CLOCK
+AT91C_TC_CLKS_TIMER_DIV2_CLOCK EQU (0x1) ;- (TC) Clock selected: TIMER_DIV2_CLOCK
+AT91C_TC_CLKS_TIMER_DIV3_CLOCK EQU (0x2) ;- (TC) Clock selected: TIMER_DIV3_CLOCK
+AT91C_TC_CLKS_TIMER_DIV4_CLOCK EQU (0x3) ;- (TC) Clock selected: TIMER_DIV4_CLOCK
+AT91C_TC_CLKS_TIMER_DIV5_CLOCK EQU (0x4) ;- (TC) Clock selected: TIMER_DIV5_CLOCK
+AT91C_TC_CLKS_XC0 EQU (0x5) ;- (TC) Clock selected: XC0
+AT91C_TC_CLKS_XC1 EQU (0x6) ;- (TC) Clock selected: XC1
+AT91C_TC_CLKS_XC2 EQU (0x7) ;- (TC) Clock selected: XC2
+AT91C_TC_CLKI EQU (0x1 << 3) ;- (TC) Clock Invert
+AT91C_TC_BURST EQU (0x3 << 4) ;- (TC) Burst Signal Selection
+AT91C_TC_BURST_NONE EQU (0x0 << 4) ;- (TC) The clock is not gated by an external signal
+AT91C_TC_BURST_XC0 EQU (0x1 << 4) ;- (TC) XC0 is ANDed with the selected clock
+AT91C_TC_BURST_XC1 EQU (0x2 << 4) ;- (TC) XC1 is ANDed with the selected clock
+AT91C_TC_BURST_XC2 EQU (0x3 << 4) ;- (TC) XC2 is ANDed with the selected clock
+AT91C_TC_CPCSTOP EQU (0x1 << 6) ;- (TC) Counter Clock Stopped with RC Compare
+AT91C_TC_LDBSTOP EQU (0x1 << 6) ;- (TC) Counter Clock Stopped with RB Loading
+AT91C_TC_CPCDIS EQU (0x1 << 7) ;- (TC) Counter Clock Disable with RC Compare
+AT91C_TC_LDBDIS EQU (0x1 << 7) ;- (TC) Counter Clock Disabled with RB Loading
+AT91C_TC_ETRGEDG EQU (0x3 << 8) ;- (TC) External Trigger Edge Selection
+AT91C_TC_ETRGEDG_NONE EQU (0x0 << 8) ;- (TC) Edge: None
+AT91C_TC_ETRGEDG_RISING EQU (0x1 << 8) ;- (TC) Edge: rising edge
+AT91C_TC_ETRGEDG_FALLING EQU (0x2 << 8) ;- (TC) Edge: falling edge
+AT91C_TC_ETRGEDG_BOTH EQU (0x3 << 8) ;- (TC) Edge: each edge
+AT91C_TC_EEVTEDG EQU (0x3 << 8) ;- (TC) External Event Edge Selection
+AT91C_TC_EEVTEDG_NONE EQU (0x0 << 8) ;- (TC) Edge: None
+AT91C_TC_EEVTEDG_RISING EQU (0x1 << 8) ;- (TC) Edge: rising edge
+AT91C_TC_EEVTEDG_FALLING EQU (0x2 << 8) ;- (TC) Edge: falling edge
+AT91C_TC_EEVTEDG_BOTH EQU (0x3 << 8) ;- (TC) Edge: each edge
+AT91C_TC_EEVT EQU (0x3 << 10) ;- (TC) External Event Selection
+AT91C_TC_EEVT_TIOB EQU (0x0 << 10) ;- (TC) Signal selected as external event: TIOB TIOB direction: input
+AT91C_TC_EEVT_XC0 EQU (0x1 << 10) ;- (TC) Signal selected as external event: XC0 TIOB direction: output
+AT91C_TC_EEVT_XC1 EQU (0x2 << 10) ;- (TC) Signal selected as external event: XC1 TIOB direction: output
+AT91C_TC_EEVT_XC2 EQU (0x3 << 10) ;- (TC) Signal selected as external event: XC2 TIOB direction: output
+AT91C_TC_ABETRG EQU (0x1 << 10) ;- (TC) TIOA or TIOB External Trigger Selection
+AT91C_TC_ENETRG EQU (0x1 << 12) ;- (TC) External Event Trigger enable
+AT91C_TC_WAVESEL EQU (0x3 << 13) ;- (TC) Waveform Selection
+AT91C_TC_WAVESEL_UP EQU (0x0 << 13) ;- (TC) UP mode without atomatic trigger on RC Compare
+AT91C_TC_WAVESEL_UPDOWN EQU (0x1 << 13) ;- (TC) UPDOWN mode without automatic trigger on RC Compare
+AT91C_TC_WAVESEL_UP_AUTO EQU (0x2 << 13) ;- (TC) UP mode with automatic trigger on RC Compare
+AT91C_TC_WAVESEL_UPDOWN_AUTO EQU (0x3 << 13) ;- (TC) UPDOWN mode with automatic trigger on RC Compare
+AT91C_TC_CPCTRG EQU (0x1 << 14) ;- (TC) RC Compare Trigger Enable
+AT91C_TC_WAVE EQU (0x1 << 15) ;- (TC)
+AT91C_TC_ACPA EQU (0x3 << 16) ;- (TC) RA Compare Effect on TIOA
+AT91C_TC_ACPA_NONE EQU (0x0 << 16) ;- (TC) Effect: none
+AT91C_TC_ACPA_SET EQU (0x1 << 16) ;- (TC) Effect: set
+AT91C_TC_ACPA_CLEAR EQU (0x2 << 16) ;- (TC) Effect: clear
+AT91C_TC_ACPA_TOGGLE EQU (0x3 << 16) ;- (TC) Effect: toggle
+AT91C_TC_LDRA EQU (0x3 << 16) ;- (TC) RA Loading Selection
+AT91C_TC_LDRA_NONE EQU (0x0 << 16) ;- (TC) Edge: None
+AT91C_TC_LDRA_RISING EQU (0x1 << 16) ;- (TC) Edge: rising edge of TIOA
+AT91C_TC_LDRA_FALLING EQU (0x2 << 16) ;- (TC) Edge: falling edge of TIOA
+AT91C_TC_LDRA_BOTH EQU (0x3 << 16) ;- (TC) Edge: each edge of TIOA
+AT91C_TC_ACPC EQU (0x3 << 18) ;- (TC) RC Compare Effect on TIOA
+AT91C_TC_ACPC_NONE EQU (0x0 << 18) ;- (TC) Effect: none
+AT91C_TC_ACPC_SET EQU (0x1 << 18) ;- (TC) Effect: set
+AT91C_TC_ACPC_CLEAR EQU (0x2 << 18) ;- (TC) Effect: clear
+AT91C_TC_ACPC_TOGGLE EQU (0x3 << 18) ;- (TC) Effect: toggle
+AT91C_TC_LDRB EQU (0x3 << 18) ;- (TC) RB Loading Selection
+AT91C_TC_LDRB_NONE EQU (0x0 << 18) ;- (TC) Edge: None
+AT91C_TC_LDRB_RISING EQU (0x1 << 18) ;- (TC) Edge: rising edge of TIOA
+AT91C_TC_LDRB_FALLING EQU (0x2 << 18) ;- (TC) Edge: falling edge of TIOA
+AT91C_TC_LDRB_BOTH EQU (0x3 << 18) ;- (TC) Edge: each edge of TIOA
+AT91C_TC_AEEVT EQU (0x3 << 20) ;- (TC) External Event Effect on TIOA
+AT91C_TC_AEEVT_NONE EQU (0x0 << 20) ;- (TC) Effect: none
+AT91C_TC_AEEVT_SET EQU (0x1 << 20) ;- (TC) Effect: set
+AT91C_TC_AEEVT_CLEAR EQU (0x2 << 20) ;- (TC) Effect: clear
+AT91C_TC_AEEVT_TOGGLE EQU (0x3 << 20) ;- (TC) Effect: toggle
+AT91C_TC_ASWTRG EQU (0x3 << 22) ;- (TC) Software Trigger Effect on TIOA
+AT91C_TC_ASWTRG_NONE EQU (0x0 << 22) ;- (TC) Effect: none
+AT91C_TC_ASWTRG_SET EQU (0x1 << 22) ;- (TC) Effect: set
+AT91C_TC_ASWTRG_CLEAR EQU (0x2 << 22) ;- (TC) Effect: clear
+AT91C_TC_ASWTRG_TOGGLE EQU (0x3 << 22) ;- (TC) Effect: toggle
+AT91C_TC_BCPB EQU (0x3 << 24) ;- (TC) RB Compare Effect on TIOB
+AT91C_TC_BCPB_NONE EQU (0x0 << 24) ;- (TC) Effect: none
+AT91C_TC_BCPB_SET EQU (0x1 << 24) ;- (TC) Effect: set
+AT91C_TC_BCPB_CLEAR EQU (0x2 << 24) ;- (TC) Effect: clear
+AT91C_TC_BCPB_TOGGLE EQU (0x3 << 24) ;- (TC) Effect: toggle
+AT91C_TC_BCPC EQU (0x3 << 26) ;- (TC) RC Compare Effect on TIOB
+AT91C_TC_BCPC_NONE EQU (0x0 << 26) ;- (TC) Effect: none
+AT91C_TC_BCPC_SET EQU (0x1 << 26) ;- (TC) Effect: set
+AT91C_TC_BCPC_CLEAR EQU (0x2 << 26) ;- (TC) Effect: clear
+AT91C_TC_BCPC_TOGGLE EQU (0x3 << 26) ;- (TC) Effect: toggle
+AT91C_TC_BEEVT EQU (0x3 << 28) ;- (TC) External Event Effect on TIOB
+AT91C_TC_BEEVT_NONE EQU (0x0 << 28) ;- (TC) Effect: none
+AT91C_TC_BEEVT_SET EQU (0x1 << 28) ;- (TC) Effect: set
+AT91C_TC_BEEVT_CLEAR EQU (0x2 << 28) ;- (TC) Effect: clear
+AT91C_TC_BEEVT_TOGGLE EQU (0x3 << 28) ;- (TC) Effect: toggle
+AT91C_TC_BSWTRG EQU (0x3 << 30) ;- (TC) Software Trigger Effect on TIOB
+AT91C_TC_BSWTRG_NONE EQU (0x0 << 30) ;- (TC) Effect: none
+AT91C_TC_BSWTRG_SET EQU (0x1 << 30) ;- (TC) Effect: set
+AT91C_TC_BSWTRG_CLEAR EQU (0x2 << 30) ;- (TC) Effect: clear
+AT91C_TC_BSWTRG_TOGGLE EQU (0x3 << 30) ;- (TC) Effect: toggle
+// - -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
+AT91C_TC_COVFS EQU (0x1 << 0) ;- (TC) Counter Overflow
+AT91C_TC_LOVRS EQU (0x1 << 1) ;- (TC) Load Overrun
+AT91C_TC_CPAS EQU (0x1 << 2) ;- (TC) RA Compare
+AT91C_TC_CPBS EQU (0x1 << 3) ;- (TC) RB Compare
+AT91C_TC_CPCS EQU (0x1 << 4) ;- (TC) RC Compare
+AT91C_TC_LDRAS EQU (0x1 << 5) ;- (TC) RA Loading
+AT91C_TC_LDRBS EQU (0x1 << 6) ;- (TC) RB Loading
+AT91C_TC_ETRGS EQU (0x1 << 7) ;- (TC) External Trigger
+AT91C_TC_CLKSTA EQU (0x1 << 16) ;- (TC) Clock Enabling
+AT91C_TC_MTIOA EQU (0x1 << 17) ;- (TC) TIOA Mirror
+AT91C_TC_MTIOB EQU (0x1 << 18) ;- (TC) TIOA Mirror
+// - -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
+// - -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
+// - -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Timer Counter Interface
+// - *****************************************************************************
+// - -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
+AT91C_TCB_SYNC EQU (0x1 << 0) ;- (TCB) Synchro Command
+// - -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
+AT91C_TCB_TC0XC0S EQU (0x3 << 0) ;- (TCB) External Clock Signal 0 Selection
+AT91C_TCB_TC0XC0S_TCLK0 EQU (0x0) ;- (TCB) TCLK0 connected to XC0
+AT91C_TCB_TC0XC0S_NONE EQU (0x1) ;- (TCB) None signal connected to XC0
+AT91C_TCB_TC0XC0S_TIOA1 EQU (0x2) ;- (TCB) TIOA1 connected to XC0
+AT91C_TCB_TC0XC0S_TIOA2 EQU (0x3) ;- (TCB) TIOA2 connected to XC0
+AT91C_TCB_TC1XC1S EQU (0x3 << 2) ;- (TCB) External Clock Signal 1 Selection
+AT91C_TCB_TC1XC1S_TCLK1 EQU (0x0 << 2) ;- (TCB) TCLK1 connected to XC1
+AT91C_TCB_TC1XC1S_NONE EQU (0x1 << 2) ;- (TCB) None signal connected to XC1
+AT91C_TCB_TC1XC1S_TIOA0 EQU (0x2 << 2) ;- (TCB) TIOA0 connected to XC1
+AT91C_TCB_TC1XC1S_TIOA2 EQU (0x3 << 2) ;- (TCB) TIOA2 connected to XC1
+AT91C_TCB_TC2XC2S EQU (0x3 << 4) ;- (TCB) External Clock Signal 2 Selection
+AT91C_TCB_TC2XC2S_TCLK2 EQU (0x0 << 4) ;- (TCB) TCLK2 connected to XC2
+AT91C_TCB_TC2XC2S_NONE EQU (0x1 << 4) ;- (TCB) None signal connected to XC2
+AT91C_TCB_TC2XC2S_TIOA0 EQU (0x2 << 4) ;- (TCB) TIOA0 connected to XC2
+AT91C_TCB_TC2XC2S_TIOA1 EQU (0x3 << 4) ;- (TCB) TIOA2 connected to XC2
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface
+// - *****************************************************************************
+// - -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register --------
+AT91C_CAN_MTIMEMARK EQU (0xFFFF << 0) ;- (CAN_MB) Mailbox Timemark
+AT91C_CAN_PRIOR EQU (0xF << 16) ;- (CAN_MB) Mailbox Priority
+AT91C_CAN_MOT EQU (0x7 << 24) ;- (CAN_MB) Mailbox Object Type
+AT91C_CAN_MOT_DIS EQU (0x0 << 24) ;- (CAN_MB)
+AT91C_CAN_MOT_RX EQU (0x1 << 24) ;- (CAN_MB)
+AT91C_CAN_MOT_RXOVERWRITE EQU (0x2 << 24) ;- (CAN_MB)
+AT91C_CAN_MOT_TX EQU (0x3 << 24) ;- (CAN_MB)
+AT91C_CAN_MOT_CONSUMER EQU (0x4 << 24) ;- (CAN_MB)
+AT91C_CAN_MOT_PRODUCER EQU (0x5 << 24) ;- (CAN_MB)
+// - -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register --------
+AT91C_CAN_MIDvB EQU (0x3FFFF << 0) ;- (CAN_MB) Complementary bits for identifier in extended mode
+AT91C_CAN_MIDvA EQU (0x7FF << 18) ;- (CAN_MB) Identifier for standard frame mode
+AT91C_CAN_MIDE EQU (0x1 << 29) ;- (CAN_MB) Identifier Version
+// - -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register --------
+// - -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register --------
+// - -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register --------
+AT91C_CAN_MTIMESTAMP EQU (0xFFFF << 0) ;- (CAN_MB) Timer Value
+AT91C_CAN_MDLC EQU (0xF << 16) ;- (CAN_MB) Mailbox Data Length Code
+AT91C_CAN_MRTR EQU (0x1 << 20) ;- (CAN_MB) Mailbox Remote Transmission Request
+AT91C_CAN_MABT EQU (0x1 << 22) ;- (CAN_MB) Mailbox Message Abort
+AT91C_CAN_MRDY EQU (0x1 << 23) ;- (CAN_MB) Mailbox Ready
+AT91C_CAN_MMI EQU (0x1 << 24) ;- (CAN_MB) Mailbox Message Ignored
+// - -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register --------
+// - -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register --------
+// - -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register --------
+AT91C_CAN_MACR EQU (0x1 << 22) ;- (CAN_MB) Abort Request for Mailbox
+AT91C_CAN_MTCR EQU (0x1 << 23) ;- (CAN_MB) Mailbox Transfer Command
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Control Area Network Interface
+// - *****************************************************************************
+// - -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register --------
+AT91C_CAN_CANEN EQU (0x1 << 0) ;- (CAN) CAN Controller Enable
+AT91C_CAN_LPM EQU (0x1 << 1) ;- (CAN) Disable/Enable Low Power Mode
+AT91C_CAN_ABM EQU (0x1 << 2) ;- (CAN) Disable/Enable Autobaud/Listen Mode
+AT91C_CAN_OVL EQU (0x1 << 3) ;- (CAN) Disable/Enable Overload Frame
+AT91C_CAN_TEOF EQU (0x1 << 4) ;- (CAN) Time Stamp messages at each end of Frame
+AT91C_CAN_TTM EQU (0x1 << 5) ;- (CAN) Disable/Enable Time Trigger Mode
+AT91C_CAN_TIMFRZ EQU (0x1 << 6) ;- (CAN) Enable Timer Freeze
+AT91C_CAN_DRPT EQU (0x1 << 7) ;- (CAN) Disable Repeat
+// - -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register --------
+AT91C_CAN_MB0 EQU (0x1 << 0) ;- (CAN) Mailbox 0 Flag
+AT91C_CAN_MB1 EQU (0x1 << 1) ;- (CAN) Mailbox 1 Flag
+AT91C_CAN_MB2 EQU (0x1 << 2) ;- (CAN) Mailbox 2 Flag
+AT91C_CAN_MB3 EQU (0x1 << 3) ;- (CAN) Mailbox 3 Flag
+AT91C_CAN_MB4 EQU (0x1 << 4) ;- (CAN) Mailbox 4 Flag
+AT91C_CAN_MB5 EQU (0x1 << 5) ;- (CAN) Mailbox 5 Flag
+AT91C_CAN_MB6 EQU (0x1 << 6) ;- (CAN) Mailbox 6 Flag
+AT91C_CAN_MB7 EQU (0x1 << 7) ;- (CAN) Mailbox 7 Flag
+AT91C_CAN_MB8 EQU (0x1 << 8) ;- (CAN) Mailbox 8 Flag
+AT91C_CAN_MB9 EQU (0x1 << 9) ;- (CAN) Mailbox 9 Flag
+AT91C_CAN_MB10 EQU (0x1 << 10) ;- (CAN) Mailbox 10 Flag
+AT91C_CAN_MB11 EQU (0x1 << 11) ;- (CAN) Mailbox 11 Flag
+AT91C_CAN_MB12 EQU (0x1 << 12) ;- (CAN) Mailbox 12 Flag
+AT91C_CAN_MB13 EQU (0x1 << 13) ;- (CAN) Mailbox 13 Flag
+AT91C_CAN_MB14 EQU (0x1 << 14) ;- (CAN) Mailbox 14 Flag
+AT91C_CAN_MB15 EQU (0x1 << 15) ;- (CAN) Mailbox 15 Flag
+AT91C_CAN_ERRA EQU (0x1 << 16) ;- (CAN) Error Active Mode Flag
+AT91C_CAN_WARN EQU (0x1 << 17) ;- (CAN) Warning Limit Flag
+AT91C_CAN_ERRP EQU (0x1 << 18) ;- (CAN) Error Passive Mode Flag
+AT91C_CAN_BOFF EQU (0x1 << 19) ;- (CAN) Bus Off Mode Flag
+AT91C_CAN_SLEEP EQU (0x1 << 20) ;- (CAN) Sleep Flag
+AT91C_CAN_WAKEUP EQU (0x1 << 21) ;- (CAN) Wakeup Flag
+AT91C_CAN_TOVF EQU (0x1 << 22) ;- (CAN) Timer Overflow Flag
+AT91C_CAN_TSTP EQU (0x1 << 23) ;- (CAN) Timestamp Flag
+AT91C_CAN_CERR EQU (0x1 << 24) ;- (CAN) CRC Error
+AT91C_CAN_SERR EQU (0x1 << 25) ;- (CAN) Stuffing Error
+AT91C_CAN_AERR EQU (0x1 << 26) ;- (CAN) Acknowledgment Error
+AT91C_CAN_FERR EQU (0x1 << 27) ;- (CAN) Form Error
+AT91C_CAN_BERR EQU (0x1 << 28) ;- (CAN) Bit Error
+// - -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register --------
+// - -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register --------
+// - -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register --------
+AT91C_CAN_RBSY EQU (0x1 << 29) ;- (CAN) Receiver Busy
+AT91C_CAN_TBSY EQU (0x1 << 30) ;- (CAN) Transmitter Busy
+AT91C_CAN_OVLY EQU (0x1 << 31) ;- (CAN) Overload Busy
+// - -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register --------
+AT91C_CAN_PHASE2 EQU (0x7 << 0) ;- (CAN) Phase 2 segment
+AT91C_CAN_PHASE1 EQU (0x7 << 4) ;- (CAN) Phase 1 segment
+AT91C_CAN_PROPAG EQU (0x7 << 8) ;- (CAN) Programmation time segment
+AT91C_CAN_SYNC EQU (0x3 << 12) ;- (CAN) Re-synchronization jump width segment
+AT91C_CAN_BRP EQU (0x7F << 16) ;- (CAN) Baudrate Prescaler
+AT91C_CAN_SMP EQU (0x1 << 24) ;- (CAN) Sampling mode
+// - -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register --------
+AT91C_CAN_TIMER EQU (0xFFFF << 0) ;- (CAN) Timer field
+// - -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register --------
+// - -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register --------
+AT91C_CAN_REC EQU (0xFF << 0) ;- (CAN) Receive Error Counter
+AT91C_CAN_TEC EQU (0xFF << 16) ;- (CAN) Transmit Error Counter
+// - -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register --------
+AT91C_CAN_TIMRST EQU (0x1 << 31) ;- (CAN) Timer Reset Field
+// - -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register --------
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Ethernet MAC 10/100
+// - *****************************************************************************
+// - -------- EMAC_NCR : (EMAC Offset: 0x0) --------
+AT91C_EMAC_LB EQU (0x1 << 0) ;- (EMAC) Loopback. Optional. When set, loopback signal is at high level.
+AT91C_EMAC_LLB EQU (0x1 << 1) ;- (EMAC) Loopback local.
+AT91C_EMAC_RE EQU (0x1 << 2) ;- (EMAC) Receive enable.
+AT91C_EMAC_TE EQU (0x1 << 3) ;- (EMAC) Transmit enable.
+AT91C_EMAC_MPE EQU (0x1 << 4) ;- (EMAC) Management port enable.
+AT91C_EMAC_CLRSTAT EQU (0x1 << 5) ;- (EMAC) Clear statistics registers.
+AT91C_EMAC_INCSTAT EQU (0x1 << 6) ;- (EMAC) Increment statistics registers.
+AT91C_EMAC_WESTAT EQU (0x1 << 7) ;- (EMAC) Write enable for statistics registers.
+AT91C_EMAC_BP EQU (0x1 << 8) ;- (EMAC) Back pressure.
+AT91C_EMAC_TSTART EQU (0x1 << 9) ;- (EMAC) Start Transmission.
+AT91C_EMAC_THALT EQU (0x1 << 10) ;- (EMAC) Transmission Halt.
+AT91C_EMAC_TPFR EQU (0x1 << 11) ;- (EMAC) Transmit pause frame
+AT91C_EMAC_TZQ EQU (0x1 << 12) ;- (EMAC) Transmit zero quantum pause frame
+// - -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register --------
+AT91C_EMAC_SPD EQU (0x1 << 0) ;- (EMAC) Speed.
+AT91C_EMAC_FD EQU (0x1 << 1) ;- (EMAC) Full duplex.
+AT91C_EMAC_JFRAME EQU (0x1 << 3) ;- (EMAC) Jumbo Frames.
+AT91C_EMAC_CAF EQU (0x1 << 4) ;- (EMAC) Copy all frames.
+AT91C_EMAC_NBC EQU (0x1 << 5) ;- (EMAC) No broadcast.
+AT91C_EMAC_MTI EQU (0x1 << 6) ;- (EMAC) Multicast hash event enable
+AT91C_EMAC_UNI EQU (0x1 << 7) ;- (EMAC) Unicast hash enable.
+AT91C_EMAC_BIG EQU (0x1 << 8) ;- (EMAC) Receive 1522 bytes.
+AT91C_EMAC_EAE EQU (0x1 << 9) ;- (EMAC) External address match enable.
+AT91C_EMAC_CLK EQU (0x3 << 10) ;- (EMAC)
+AT91C_EMAC_CLK_HCLK_8 EQU (0x0 << 10) ;- (EMAC) HCLK divided by 8
+AT91C_EMAC_CLK_HCLK_16 EQU (0x1 << 10) ;- (EMAC) HCLK divided by 16
+AT91C_EMAC_CLK_HCLK_32 EQU (0x2 << 10) ;- (EMAC) HCLK divided by 32
+AT91C_EMAC_CLK_HCLK_64 EQU (0x3 << 10) ;- (EMAC) HCLK divided by 64
+AT91C_EMAC_RTY EQU (0x1 << 12) ;- (EMAC)
+AT91C_EMAC_PAE EQU (0x1 << 13) ;- (EMAC)
+AT91C_EMAC_RBOF EQU (0x3 << 14) ;- (EMAC)
+AT91C_EMAC_RBOF_OFFSET_0 EQU (0x0 << 14) ;- (EMAC) no offset from start of receive buffer
+AT91C_EMAC_RBOF_OFFSET_1 EQU (0x1 << 14) ;- (EMAC) one byte offset from start of receive buffer
+AT91C_EMAC_RBOF_OFFSET_2 EQU (0x2 << 14) ;- (EMAC) two bytes offset from start of receive buffer
+AT91C_EMAC_RBOF_OFFSET_3 EQU (0x3 << 14) ;- (EMAC) three bytes offset from start of receive buffer
+AT91C_EMAC_RLCE EQU (0x1 << 16) ;- (EMAC) Receive Length field Checking Enable
+AT91C_EMAC_DRFCS EQU (0x1 << 17) ;- (EMAC) Discard Receive FCS
+AT91C_EMAC_EFRHD EQU (0x1 << 18) ;- (EMAC)
+AT91C_EMAC_IRXFCS EQU (0x1 << 19) ;- (EMAC) Ignore RX FCS
+// - -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register --------
+AT91C_EMAC_LINKR EQU (0x1 << 0) ;- (EMAC)
+AT91C_EMAC_MDIO EQU (0x1 << 1) ;- (EMAC)
+AT91C_EMAC_IDLE EQU (0x1 << 2) ;- (EMAC)
+// - -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register --------
+AT91C_EMAC_UBR EQU (0x1 << 0) ;- (EMAC)
+AT91C_EMAC_COL EQU (0x1 << 1) ;- (EMAC)
+AT91C_EMAC_RLES EQU (0x1 << 2) ;- (EMAC)
+AT91C_EMAC_TGO EQU (0x1 << 3) ;- (EMAC) Transmit Go
+AT91C_EMAC_BEX EQU (0x1 << 4) ;- (EMAC) Buffers exhausted mid frame
+AT91C_EMAC_COMP EQU (0x1 << 5) ;- (EMAC)
+AT91C_EMAC_UND EQU (0x1 << 6) ;- (EMAC)
+// - -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
+AT91C_EMAC_BNA EQU (0x1 << 0) ;- (EMAC)
+AT91C_EMAC_REC EQU (0x1 << 1) ;- (EMAC)
+AT91C_EMAC_OVR EQU (0x1 << 2) ;- (EMAC)
+// - -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
+AT91C_EMAC_MFD EQU (0x1 << 0) ;- (EMAC)
+AT91C_EMAC_RCOMP EQU (0x1 << 1) ;- (EMAC)
+AT91C_EMAC_RXUBR EQU (0x1 << 2) ;- (EMAC)
+AT91C_EMAC_TXUBR EQU (0x1 << 3) ;- (EMAC)
+AT91C_EMAC_TUNDR EQU (0x1 << 4) ;- (EMAC)
+AT91C_EMAC_RLEX EQU (0x1 << 5) ;- (EMAC)
+AT91C_EMAC_TXERR EQU (0x1 << 6) ;- (EMAC)
+AT91C_EMAC_TCOMP EQU (0x1 << 7) ;- (EMAC)
+AT91C_EMAC_LINK EQU (0x1 << 9) ;- (EMAC)
+AT91C_EMAC_ROVR EQU (0x1 << 10) ;- (EMAC)
+AT91C_EMAC_HRESP EQU (0x1 << 11) ;- (EMAC)
+AT91C_EMAC_PFRE EQU (0x1 << 12) ;- (EMAC)
+AT91C_EMAC_PTZ EQU (0x1 << 13) ;- (EMAC)
+// - -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
+// - -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
+// - -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
+// - -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
+AT91C_EMAC_DATA EQU (0xFFFF << 0) ;- (EMAC)
+AT91C_EMAC_CODE EQU (0x3 << 16) ;- (EMAC)
+AT91C_EMAC_REGA EQU (0x1F << 18) ;- (EMAC)
+AT91C_EMAC_PHYA EQU (0x1F << 23) ;- (EMAC)
+AT91C_EMAC_RW EQU (0x3 << 28) ;- (EMAC)
+AT91C_EMAC_SOF EQU (0x3 << 30) ;- (EMAC)
+// - -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register --------
+AT91C_EMAC_RMII EQU (0x1 << 0) ;- (EMAC) Reduce MII
+// - -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register --------
+AT91C_EMAC_IP EQU (0xFFFF << 0) ;- (EMAC) ARP request IP address
+AT91C_EMAC_MAG EQU (0x1 << 16) ;- (EMAC) Magic packet event enable
+AT91C_EMAC_ARP EQU (0x1 << 17) ;- (EMAC) ARP request event enable
+AT91C_EMAC_SA1 EQU (0x1 << 18) ;- (EMAC) Specific address register 1 event enable
+// - -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register --------
+AT91C_EMAC_REVREF EQU (0xFFFF << 0) ;- (EMAC)
+AT91C_EMAC_PARTREF EQU (0xFFFF << 16) ;- (EMAC)
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Analog to Digital Convertor
+// - *****************************************************************************
+// - -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
+AT91C_ADC_SWRST EQU (0x1 << 0) ;- (ADC) Software Reset
+AT91C_ADC_START EQU (0x1 << 1) ;- (ADC) Start Conversion
+// - -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
+AT91C_ADC_TRGEN EQU (0x1 << 0) ;- (ADC) Trigger Enable
+AT91C_ADC_TRGEN_DIS EQU (0x0) ;- (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+AT91C_ADC_TRGEN_EN EQU (0x1) ;- (ADC) Hardware trigger selected by TRGSEL field is enabled.
+AT91C_ADC_TRGSEL EQU (0x7 << 1) ;- (ADC) Trigger Selection
+AT91C_ADC_TRGSEL_TIOA0 EQU (0x0 << 1) ;- (ADC) Selected TRGSEL = TIAO0
+AT91C_ADC_TRGSEL_TIOA1 EQU (0x1 << 1) ;- (ADC) Selected TRGSEL = TIAO1
+AT91C_ADC_TRGSEL_TIOA2 EQU (0x2 << 1) ;- (ADC) Selected TRGSEL = TIAO2
+AT91C_ADC_TRGSEL_TIOA3 EQU (0x3 << 1) ;- (ADC) Selected TRGSEL = TIAO3
+AT91C_ADC_TRGSEL_TIOA4 EQU (0x4 << 1) ;- (ADC) Selected TRGSEL = TIAO4
+AT91C_ADC_TRGSEL_TIOA5 EQU (0x5 << 1) ;- (ADC) Selected TRGSEL = TIAO5
+AT91C_ADC_TRGSEL_EXT EQU (0x6 << 1) ;- (ADC) Selected TRGSEL = External Trigger
+AT91C_ADC_LOWRES EQU (0x1 << 4) ;- (ADC) Resolution.
+AT91C_ADC_LOWRES_10_BIT EQU (0x0 << 4) ;- (ADC) 10-bit resolution
+AT91C_ADC_LOWRES_8_BIT EQU (0x1 << 4) ;- (ADC) 8-bit resolution
+AT91C_ADC_SLEEP EQU (0x1 << 5) ;- (ADC) Sleep Mode
+AT91C_ADC_SLEEP_NORMAL_MODE EQU (0x0 << 5) ;- (ADC) Normal Mode
+AT91C_ADC_SLEEP_MODE EQU (0x1 << 5) ;- (ADC) Sleep Mode
+AT91C_ADC_PRESCAL EQU (0x3F << 8) ;- (ADC) Prescaler rate selection
+AT91C_ADC_STARTUP EQU (0x1F << 16) ;- (ADC) Startup Time
+AT91C_ADC_SHTIM EQU (0xF << 24) ;- (ADC) Sample & Hold Time
+// - -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
+AT91C_ADC_CH0 EQU (0x1 << 0) ;- (ADC) Channel 0
+AT91C_ADC_CH1 EQU (0x1 << 1) ;- (ADC) Channel 1
+AT91C_ADC_CH2 EQU (0x1 << 2) ;- (ADC) Channel 2
+AT91C_ADC_CH3 EQU (0x1 << 3) ;- (ADC) Channel 3
+AT91C_ADC_CH4 EQU (0x1 << 4) ;- (ADC) Channel 4
+AT91C_ADC_CH5 EQU (0x1 << 5) ;- (ADC) Channel 5
+AT91C_ADC_CH6 EQU (0x1 << 6) ;- (ADC) Channel 6
+AT91C_ADC_CH7 EQU (0x1 << 7) ;- (ADC) Channel 7
+// - -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
+// - -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
+// - -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
+AT91C_ADC_EOC0 EQU (0x1 << 0) ;- (ADC) End of Conversion
+AT91C_ADC_EOC1 EQU (0x1 << 1) ;- (ADC) End of Conversion
+AT91C_ADC_EOC2 EQU (0x1 << 2) ;- (ADC) End of Conversion
+AT91C_ADC_EOC3 EQU (0x1 << 3) ;- (ADC) End of Conversion
+AT91C_ADC_EOC4 EQU (0x1 << 4) ;- (ADC) End of Conversion
+AT91C_ADC_EOC5 EQU (0x1 << 5) ;- (ADC) End of Conversion
+AT91C_ADC_EOC6 EQU (0x1 << 6) ;- (ADC) End of Conversion
+AT91C_ADC_EOC7 EQU (0x1 << 7) ;- (ADC) End of Conversion
+AT91C_ADC_OVRE0 EQU (0x1 << 8) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE1 EQU (0x1 << 9) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE2 EQU (0x1 << 10) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE3 EQU (0x1 << 11) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE4 EQU (0x1 << 12) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE5 EQU (0x1 << 13) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE6 EQU (0x1 << 14) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE7 EQU (0x1 << 15) ;- (ADC) Overrun Error
+AT91C_ADC_DRDY EQU (0x1 << 16) ;- (ADC) Data Ready
+AT91C_ADC_GOVRE EQU (0x1 << 17) ;- (ADC) General Overrun
+AT91C_ADC_ENDRX EQU (0x1 << 18) ;- (ADC) End of Receiver Transfer
+AT91C_ADC_RXBUFF EQU (0x1 << 19) ;- (ADC) RXBUFF Interrupt
+// - -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
+AT91C_ADC_LDATA EQU (0x3FF << 0) ;- (ADC) Last Data Converted
+// - -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
+// - -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
+// - -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
+// - -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
+AT91C_ADC_DATA EQU (0x3FF << 0) ;- (ADC) Converted Data
+// - -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
+// - -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
+// - -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
+// - -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
+// - -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
+// - -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
+// - -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Advanced Encryption Standard
+// - *****************************************************************************
+// - -------- AES_CR : (AES Offset: 0x0) Control Register --------
+AT91C_AES_START EQU (0x1 << 0) ;- (AES) Starts Processing
+AT91C_AES_SWRST EQU (0x1 << 8) ;- (AES) Software Reset
+AT91C_AES_LOADSEED EQU (0x1 << 16) ;- (AES) Random Number Generator Seed Loading
+// - -------- AES_MR : (AES Offset: 0x4) Mode Register --------
+AT91C_AES_CIPHER EQU (0x1 << 0) ;- (AES) Processing Mode
+AT91C_AES_PROCDLY EQU (0xF << 4) ;- (AES) Processing Delay
+AT91C_AES_SMOD EQU (0x3 << 8) ;- (AES) Start Mode
+AT91C_AES_SMOD_MANUAL EQU (0x0 << 8) ;- (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
+AT91C_AES_SMOD_AUTO EQU (0x1 << 8) ;- (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
+AT91C_AES_SMOD_PDC EQU (0x2 << 8) ;- (AES) PDC Mode (cf datasheet).
+AT91C_AES_OPMOD EQU (0x7 << 12) ;- (AES) Operation Mode
+AT91C_AES_OPMOD_ECB EQU (0x0 << 12) ;- (AES) ECB Electronic CodeBook mode.
+AT91C_AES_OPMOD_CBC EQU (0x1 << 12) ;- (AES) CBC Cipher Block Chaining mode.
+AT91C_AES_OPMOD_OFB EQU (0x2 << 12) ;- (AES) OFB Output Feedback mode.
+AT91C_AES_OPMOD_CFB EQU (0x3 << 12) ;- (AES) CFB Cipher Feedback mode.
+AT91C_AES_OPMOD_CTR EQU (0x4 << 12) ;- (AES) CTR Counter mode.
+AT91C_AES_LOD EQU (0x1 << 15) ;- (AES) Last Output Data Mode
+AT91C_AES_CFBS EQU (0x7 << 16) ;- (AES) Cipher Feedback Data Size
+AT91C_AES_CFBS_128_BIT EQU (0x0 << 16) ;- (AES) 128-bit.
+AT91C_AES_CFBS_64_BIT EQU (0x1 << 16) ;- (AES) 64-bit.
+AT91C_AES_CFBS_32_BIT EQU (0x2 << 16) ;- (AES) 32-bit.
+AT91C_AES_CFBS_16_BIT EQU (0x3 << 16) ;- (AES) 16-bit.
+AT91C_AES_CFBS_8_BIT EQU (0x4 << 16) ;- (AES) 8-bit.
+AT91C_AES_CKEY EQU (0xF << 20) ;- (AES) Countermeasure Key
+AT91C_AES_CTYPE EQU (0x1F << 24) ;- (AES) Countermeasure Type
+AT91C_AES_CTYPE_TYPE1_EN EQU (0x1 << 24) ;- (AES) Countermeasure type 1 is enabled.
+AT91C_AES_CTYPE_TYPE2_EN EQU (0x2 << 24) ;- (AES) Countermeasure type 2 is enabled.
+AT91C_AES_CTYPE_TYPE3_EN EQU (0x4 << 24) ;- (AES) Countermeasure type 3 is enabled.
+AT91C_AES_CTYPE_TYPE4_EN EQU (0x8 << 24) ;- (AES) Countermeasure type 4 is enabled.
+AT91C_AES_CTYPE_TYPE5_EN EQU (0x10 << 24) ;- (AES) Countermeasure type 5 is enabled.
+// - -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register --------
+AT91C_AES_DATRDY EQU (0x1 << 0) ;- (AES) DATRDY
+AT91C_AES_ENDRX EQU (0x1 << 1) ;- (AES) PDC Read Buffer End
+AT91C_AES_ENDTX EQU (0x1 << 2) ;- (AES) PDC Write Buffer End
+AT91C_AES_RXBUFF EQU (0x1 << 3) ;- (AES) PDC Read Buffer Full
+AT91C_AES_TXBUFE EQU (0x1 << 4) ;- (AES) PDC Write Buffer Empty
+AT91C_AES_URAD EQU (0x1 << 8) ;- (AES) Unspecified Register Access Detection
+// - -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register --------
+// - -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register --------
+// - -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register --------
+AT91C_AES_URAT EQU (0x7 << 12) ;- (AES) Unspecified Register Access Type Status
+AT91C_AES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (AES) Input data register written during the data processing in PDC mode.
+AT91C_AES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (AES) Output data register read during the data processing.
+AT91C_AES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (AES) Mode register written during the data processing.
+AT91C_AES_URAT_OUT_DAT_READ_SUBKEY EQU (0x3 << 12) ;- (AES) Output data register read during the sub-keys generation.
+AT91C_AES_URAT_MODEREG_WRITE_SUBKEY EQU (0x4 << 12) ;- (AES) Mode register written during the sub-keys generation.
+AT91C_AES_URAT_WO_REG_READ EQU (0x5 << 12) ;- (AES) Write-only register read access.
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Triple Data Encryption Standard
+// - *****************************************************************************
+// - -------- TDES_CR : (TDES Offset: 0x0) Control Register --------
+AT91C_TDES_START EQU (0x1 << 0) ;- (TDES) Starts Processing
+AT91C_TDES_SWRST EQU (0x1 << 8) ;- (TDES) Software Reset
+// - -------- TDES_MR : (TDES Offset: 0x4) Mode Register --------
+AT91C_TDES_CIPHER EQU (0x1 << 0) ;- (TDES) Processing Mode
+AT91C_TDES_TDESMOD EQU (0x1 << 1) ;- (TDES) Single or Triple DES Mode
+AT91C_TDES_KEYMOD EQU (0x1 << 4) ;- (TDES) Key Mode
+AT91C_TDES_SMOD EQU (0x3 << 8) ;- (TDES) Start Mode
+AT91C_TDES_SMOD_MANUAL EQU (0x0 << 8) ;- (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
+AT91C_TDES_SMOD_AUTO EQU (0x1 << 8) ;- (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
+AT91C_TDES_SMOD_PDC EQU (0x2 << 8) ;- (TDES) PDC Mode (cf datasheet).
+AT91C_TDES_OPMOD EQU (0x3 << 12) ;- (TDES) Operation Mode
+AT91C_TDES_OPMOD_ECB EQU (0x0 << 12) ;- (TDES) ECB Electronic CodeBook mode.
+AT91C_TDES_OPMOD_CBC EQU (0x1 << 12) ;- (TDES) CBC Cipher Block Chaining mode.
+AT91C_TDES_OPMOD_OFB EQU (0x2 << 12) ;- (TDES) OFB Output Feedback mode.
+AT91C_TDES_OPMOD_CFB EQU (0x3 << 12) ;- (TDES) CFB Cipher Feedback mode.
+AT91C_TDES_LOD EQU (0x1 << 15) ;- (TDES) Last Output Data Mode
+AT91C_TDES_CFBS EQU (0x3 << 16) ;- (TDES) Cipher Feedback Data Size
+AT91C_TDES_CFBS_64_BIT EQU (0x0 << 16) ;- (TDES) 64-bit.
+AT91C_TDES_CFBS_32_BIT EQU (0x1 << 16) ;- (TDES) 32-bit.
+AT91C_TDES_CFBS_16_BIT EQU (0x2 << 16) ;- (TDES) 16-bit.
+AT91C_TDES_CFBS_8_BIT EQU (0x3 << 16) ;- (TDES) 8-bit.
+// - -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register --------
+AT91C_TDES_DATRDY EQU (0x1 << 0) ;- (TDES) DATRDY
+AT91C_TDES_ENDRX EQU (0x1 << 1) ;- (TDES) PDC Read Buffer End
+AT91C_TDES_ENDTX EQU (0x1 << 2) ;- (TDES) PDC Write Buffer End
+AT91C_TDES_RXBUFF EQU (0x1 << 3) ;- (TDES) PDC Read Buffer Full
+AT91C_TDES_TXBUFE EQU (0x1 << 4) ;- (TDES) PDC Write Buffer Empty
+AT91C_TDES_URAD EQU (0x1 << 8) ;- (TDES) Unspecified Register Access Detection
+// - -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register --------
+// - -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register --------
+// - -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register --------
+AT91C_TDES_URAT EQU (0x3 << 12) ;- (TDES) Unspecified Register Access Type Status
+AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (TDES) Input data register written during the data processing in PDC mode.
+AT91C_TDES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (TDES) Output data register read during the data processing.
+AT91C_TDES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (TDES) Mode register written during the data processing.
+AT91C_TDES_URAT_WO_REG_READ EQU (0x3 << 12) ;- (TDES) Write-only register read access.
+
+// - *****************************************************************************
+// - REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
+// - *****************************************************************************
+// - ========== Register definition for SYS peripheral ==========
+// - ========== Register definition for AIC peripheral ==========
+AT91C_AIC_IVR EQU (0xFFFFF100) ;- (AIC) IRQ Vector Register
+AT91C_AIC_SMR EQU (0xFFFFF000) ;- (AIC) Source Mode Register
+AT91C_AIC_FVR EQU (0xFFFFF104) ;- (AIC) FIQ Vector Register
+AT91C_AIC_DCR EQU (0xFFFFF138) ;- (AIC) Debug Control Register (Protect)
+AT91C_AIC_EOICR EQU (0xFFFFF130) ;- (AIC) End of Interrupt Command Register
+AT91C_AIC_SVR EQU (0xFFFFF080) ;- (AIC) Source Vector Register
+AT91C_AIC_FFSR EQU (0xFFFFF148) ;- (AIC) Fast Forcing Status Register
+AT91C_AIC_ICCR EQU (0xFFFFF128) ;- (AIC) Interrupt Clear Command Register
+AT91C_AIC_ISR EQU (0xFFFFF108) ;- (AIC) Interrupt Status Register
+AT91C_AIC_IMR EQU (0xFFFFF110) ;- (AIC) Interrupt Mask Register
+AT91C_AIC_IPR EQU (0xFFFFF10C) ;- (AIC) Interrupt Pending Register
+AT91C_AIC_FFER EQU (0xFFFFF140) ;- (AIC) Fast Forcing Enable Register
+AT91C_AIC_IECR EQU (0xFFFFF120) ;- (AIC) Interrupt Enable Command Register
+AT91C_AIC_ISCR EQU (0xFFFFF12C) ;- (AIC) Interrupt Set Command Register
+AT91C_AIC_FFDR EQU (0xFFFFF144) ;- (AIC) Fast Forcing Disable Register
+AT91C_AIC_CISR EQU (0xFFFFF114) ;- (AIC) Core Interrupt Status Register
+AT91C_AIC_IDCR EQU (0xFFFFF124) ;- (AIC) Interrupt Disable Command Register
+AT91C_AIC_SPU EQU (0xFFFFF134) ;- (AIC) Spurious Vector Register
+// - ========== Register definition for PDC_DBGU peripheral ==========
+AT91C_DBGU_TCR EQU (0xFFFFF30C) ;- (PDC_DBGU) Transmit Counter Register
+AT91C_DBGU_RNPR EQU (0xFFFFF310) ;- (PDC_DBGU) Receive Next Pointer Register
+AT91C_DBGU_TNPR EQU (0xFFFFF318) ;- (PDC_DBGU) Transmit Next Pointer Register
+AT91C_DBGU_TPR EQU (0xFFFFF308) ;- (PDC_DBGU) Transmit Pointer Register
+AT91C_DBGU_RPR EQU (0xFFFFF300) ;- (PDC_DBGU) Receive Pointer Register
+AT91C_DBGU_RCR EQU (0xFFFFF304) ;- (PDC_DBGU) Receive Counter Register
+AT91C_DBGU_RNCR EQU (0xFFFFF314) ;- (PDC_DBGU) Receive Next Counter Register
+AT91C_DBGU_PTCR EQU (0xFFFFF320) ;- (PDC_DBGU) PDC Transfer Control Register
+AT91C_DBGU_PTSR EQU (0xFFFFF324) ;- (PDC_DBGU) PDC Transfer Status Register
+AT91C_DBGU_TNCR EQU (0xFFFFF31C) ;- (PDC_DBGU) Transmit Next Counter Register
+// - ========== Register definition for DBGU peripheral ==========
+AT91C_DBGU_EXID EQU (0xFFFFF244) ;- (DBGU) Chip ID Extension Register
+AT91C_DBGU_BRGR EQU (0xFFFFF220) ;- (DBGU) Baud Rate Generator Register
+AT91C_DBGU_IDR EQU (0xFFFFF20C) ;- (DBGU) Interrupt Disable Register
+AT91C_DBGU_CSR EQU (0xFFFFF214) ;- (DBGU) Channel Status Register
+AT91C_DBGU_CIDR EQU (0xFFFFF240) ;- (DBGU) Chip ID Register
+AT91C_DBGU_MR EQU (0xFFFFF204) ;- (DBGU) Mode Register
+AT91C_DBGU_IMR EQU (0xFFFFF210) ;- (DBGU) Interrupt Mask Register
+AT91C_DBGU_CR EQU (0xFFFFF200) ;- (DBGU) Control Register
+AT91C_DBGU_FNTR EQU (0xFFFFF248) ;- (DBGU) Force NTRST Register
+AT91C_DBGU_THR EQU (0xFFFFF21C) ;- (DBGU) Transmitter Holding Register
+AT91C_DBGU_RHR EQU (0xFFFFF218) ;- (DBGU) Receiver Holding Register
+AT91C_DBGU_IER EQU (0xFFFFF208) ;- (DBGU) Interrupt Enable Register
+// - ========== Register definition for PIOA peripheral ==========
+AT91C_PIOA_ODR EQU (0xFFFFF414) ;- (PIOA) Output Disable Registerr
+AT91C_PIOA_SODR EQU (0xFFFFF430) ;- (PIOA) Set Output Data Register
+AT91C_PIOA_ISR EQU (0xFFFFF44C) ;- (PIOA) Interrupt Status Register
+AT91C_PIOA_ABSR EQU (0xFFFFF478) ;- (PIOA) AB Select Status Register
+AT91C_PIOA_IER EQU (0xFFFFF440) ;- (PIOA) Interrupt Enable Register
+AT91C_PIOA_PPUDR EQU (0xFFFFF460) ;- (PIOA) Pull-up Disable Register
+AT91C_PIOA_IMR EQU (0xFFFFF448) ;- (PIOA) Interrupt Mask Register
+AT91C_PIOA_PER EQU (0xFFFFF400) ;- (PIOA) PIO Enable Register
+AT91C_PIOA_IFDR EQU (0xFFFFF424) ;- (PIOA) Input Filter Disable Register
+AT91C_PIOA_OWDR EQU (0xFFFFF4A4) ;- (PIOA) Output Write Disable Register
+AT91C_PIOA_MDSR EQU (0xFFFFF458) ;- (PIOA) Multi-driver Status Register
+AT91C_PIOA_IDR EQU (0xFFFFF444) ;- (PIOA) Interrupt Disable Register
+AT91C_PIOA_ODSR EQU (0xFFFFF438) ;- (PIOA) Output Data Status Register
+AT91C_PIOA_PPUSR EQU (0xFFFFF468) ;- (PIOA) Pull-up Status Register
+AT91C_PIOA_OWSR EQU (0xFFFFF4A8) ;- (PIOA) Output Write Status Register
+AT91C_PIOA_BSR EQU (0xFFFFF474) ;- (PIOA) Select B Register
+AT91C_PIOA_OWER EQU (0xFFFFF4A0) ;- (PIOA) Output Write Enable Register
+AT91C_PIOA_IFER EQU (0xFFFFF420) ;- (PIOA) Input Filter Enable Register
+AT91C_PIOA_PDSR EQU (0xFFFFF43C) ;- (PIOA) Pin Data Status Register
+AT91C_PIOA_PPUER EQU (0xFFFFF464) ;- (PIOA) Pull-up Enable Register
+AT91C_PIOA_OSR EQU (0xFFFFF418) ;- (PIOA) Output Status Register
+AT91C_PIOA_ASR EQU (0xFFFFF470) ;- (PIOA) Select A Register
+AT91C_PIOA_MDDR EQU (0xFFFFF454) ;- (PIOA) Multi-driver Disable Register
+AT91C_PIOA_CODR EQU (0xFFFFF434) ;- (PIOA) Clear Output Data Register
+AT91C_PIOA_MDER EQU (0xFFFFF450) ;- (PIOA) Multi-driver Enable Register
+AT91C_PIOA_PDR EQU (0xFFFFF404) ;- (PIOA) PIO Disable Register
+AT91C_PIOA_IFSR EQU (0xFFFFF428) ;- (PIOA) Input Filter Status Register
+AT91C_PIOA_OER EQU (0xFFFFF410) ;- (PIOA) Output Enable Register
+AT91C_PIOA_PSR EQU (0xFFFFF408) ;- (PIOA) PIO Status Register
+// - ========== Register definition for PIOB peripheral ==========
+AT91C_PIOB_OWDR EQU (0xFFFFF6A4) ;- (PIOB) Output Write Disable Register
+AT91C_PIOB_MDER EQU (0xFFFFF650) ;- (PIOB) Multi-driver Enable Register
+AT91C_PIOB_PPUSR EQU (0xFFFFF668) ;- (PIOB) Pull-up Status Register
+AT91C_PIOB_IMR EQU (0xFFFFF648) ;- (PIOB) Interrupt Mask Register
+AT91C_PIOB_ASR EQU (0xFFFFF670) ;- (PIOB) Select A Register
+AT91C_PIOB_PPUDR EQU (0xFFFFF660) ;- (PIOB) Pull-up Disable Register
+AT91C_PIOB_PSR EQU (0xFFFFF608) ;- (PIOB) PIO Status Register
+AT91C_PIOB_IER EQU (0xFFFFF640) ;- (PIOB) Interrupt Enable Register
+AT91C_PIOB_CODR EQU (0xFFFFF634) ;- (PIOB) Clear Output Data Register
+AT91C_PIOB_OWER EQU (0xFFFFF6A0) ;- (PIOB) Output Write Enable Register
+AT91C_PIOB_ABSR EQU (0xFFFFF678) ;- (PIOB) AB Select Status Register
+AT91C_PIOB_IFDR EQU (0xFFFFF624) ;- (PIOB) Input Filter Disable Register
+AT91C_PIOB_PDSR EQU (0xFFFFF63C) ;- (PIOB) Pin Data Status Register
+AT91C_PIOB_IDR EQU (0xFFFFF644) ;- (PIOB) Interrupt Disable Register
+AT91C_PIOB_OWSR EQU (0xFFFFF6A8) ;- (PIOB) Output Write Status Register
+AT91C_PIOB_PDR EQU (0xFFFFF604) ;- (PIOB) PIO Disable Register
+AT91C_PIOB_ODR EQU (0xFFFFF614) ;- (PIOB) Output Disable Registerr
+AT91C_PIOB_IFSR EQU (0xFFFFF628) ;- (PIOB) Input Filter Status Register
+AT91C_PIOB_PPUER EQU (0xFFFFF664) ;- (PIOB) Pull-up Enable Register
+AT91C_PIOB_SODR EQU (0xFFFFF630) ;- (PIOB) Set Output Data Register
+AT91C_PIOB_ISR EQU (0xFFFFF64C) ;- (PIOB) Interrupt Status Register
+AT91C_PIOB_ODSR EQU (0xFFFFF638) ;- (PIOB) Output Data Status Register
+AT91C_PIOB_OSR EQU (0xFFFFF618) ;- (PIOB) Output Status Register
+AT91C_PIOB_MDSR EQU (0xFFFFF658) ;- (PIOB) Multi-driver Status Register
+AT91C_PIOB_IFER EQU (0xFFFFF620) ;- (PIOB) Input Filter Enable Register
+AT91C_PIOB_BSR EQU (0xFFFFF674) ;- (PIOB) Select B Register
+AT91C_PIOB_MDDR EQU (0xFFFFF654) ;- (PIOB) Multi-driver Disable Register
+AT91C_PIOB_OER EQU (0xFFFFF610) ;- (PIOB) Output Enable Register
+AT91C_PIOB_PER EQU (0xFFFFF600) ;- (PIOB) PIO Enable Register
+// - ========== Register definition for CKGR peripheral ==========
+AT91C_CKGR_MOR EQU (0xFFFFFC20) ;- (CKGR) Main Oscillator Register
+AT91C_CKGR_PLLR EQU (0xFFFFFC2C) ;- (CKGR) PLL Register
+AT91C_CKGR_MCFR EQU (0xFFFFFC24) ;- (CKGR) Main Clock Frequency Register
+// - ========== Register definition for PMC peripheral ==========
+AT91C_PMC_IDR EQU (0xFFFFFC64) ;- (PMC) Interrupt Disable Register
+AT91C_PMC_MOR EQU (0xFFFFFC20) ;- (PMC) Main Oscillator Register
+AT91C_PMC_PLLR EQU (0xFFFFFC2C) ;- (PMC) PLL Register
+AT91C_PMC_PCER EQU (0xFFFFFC10) ;- (PMC) Peripheral Clock Enable Register
+AT91C_PMC_PCKR EQU (0xFFFFFC40) ;- (PMC) Programmable Clock Register
+AT91C_PMC_MCKR EQU (0xFFFFFC30) ;- (PMC) Master Clock Register
+AT91C_PMC_SCDR EQU (0xFFFFFC04) ;- (PMC) System Clock Disable Register
+AT91C_PMC_PCDR EQU (0xFFFFFC14) ;- (PMC) Peripheral Clock Disable Register
+AT91C_PMC_SCSR EQU (0xFFFFFC08) ;- (PMC) System Clock Status Register
+AT91C_PMC_PCSR EQU (0xFFFFFC18) ;- (PMC) Peripheral Clock Status Register
+AT91C_PMC_MCFR EQU (0xFFFFFC24) ;- (PMC) Main Clock Frequency Register
+AT91C_PMC_SCER EQU (0xFFFFFC00) ;- (PMC) System Clock Enable Register
+AT91C_PMC_IMR EQU (0xFFFFFC6C) ;- (PMC) Interrupt Mask Register
+AT91C_PMC_IER EQU (0xFFFFFC60) ;- (PMC) Interrupt Enable Register
+AT91C_PMC_SR EQU (0xFFFFFC68) ;- (PMC) Status Register
+// - ========== Register definition for RSTC peripheral ==========
+AT91C_RSTC_RCR EQU (0xFFFFFD00) ;- (RSTC) Reset Control Register
+AT91C_RSTC_RMR EQU (0xFFFFFD08) ;- (RSTC) Reset Mode Register
+AT91C_RSTC_RSR EQU (0xFFFFFD04) ;- (RSTC) Reset Status Register
+// - ========== Register definition for RTTC peripheral ==========
+AT91C_RTTC_RTSR EQU (0xFFFFFD2C) ;- (RTTC) Real-time Status Register
+AT91C_RTTC_RTMR EQU (0xFFFFFD20) ;- (RTTC) Real-time Mode Register
+AT91C_RTTC_RTVR EQU (0xFFFFFD28) ;- (RTTC) Real-time Value Register
+AT91C_RTTC_RTAR EQU (0xFFFFFD24) ;- (RTTC) Real-time Alarm Register
+// - ========== Register definition for PITC peripheral ==========
+AT91C_PITC_PIVR EQU (0xFFFFFD38) ;- (PITC) Period Interval Value Register
+AT91C_PITC_PISR EQU (0xFFFFFD34) ;- (PITC) Period Interval Status Register
+AT91C_PITC_PIIR EQU (0xFFFFFD3C) ;- (PITC) Period Interval Image Register
+AT91C_PITC_PIMR EQU (0xFFFFFD30) ;- (PITC) Period Interval Mode Register
+// - ========== Register definition for WDTC peripheral ==========
+AT91C_WDTC_WDCR EQU (0xFFFFFD40) ;- (WDTC) Watchdog Control Register
+AT91C_WDTC_WDSR EQU (0xFFFFFD48) ;- (WDTC) Watchdog Status Register
+AT91C_WDTC_WDMR EQU (0xFFFFFD44) ;- (WDTC) Watchdog Mode Register
+// - ========== Register definition for VREG peripheral ==========
+AT91C_VREG_MR EQU (0xFFFFFD60) ;- (VREG) Voltage Regulator Mode Register
+// - ========== Register definition for MC peripheral ==========
+AT91C_MC_ASR EQU (0xFFFFFF04) ;- (MC) MC Abort Status Register
+AT91C_MC_RCR EQU (0xFFFFFF00) ;- (MC) MC Remap Control Register
+AT91C_MC_FCR EQU (0xFFFFFF64) ;- (MC) MC Flash Command Register
+AT91C_MC_AASR EQU (0xFFFFFF08) ;- (MC) MC Abort Address Status Register
+AT91C_MC_FSR EQU (0xFFFFFF68) ;- (MC) MC Flash Status Register
+AT91C_MC_FMR EQU (0xFFFFFF60) ;- (MC) MC Flash Mode Register
+// - ========== Register definition for PDC_SPI1 peripheral ==========
+AT91C_SPI1_PTCR EQU (0xFFFE4120) ;- (PDC_SPI1) PDC Transfer Control Register
+AT91C_SPI1_RPR EQU (0xFFFE4100) ;- (PDC_SPI1) Receive Pointer Register
+AT91C_SPI1_TNCR EQU (0xFFFE411C) ;- (PDC_SPI1) Transmit Next Counter Register
+AT91C_SPI1_TPR EQU (0xFFFE4108) ;- (PDC_SPI1) Transmit Pointer Register
+AT91C_SPI1_TNPR EQU (0xFFFE4118) ;- (PDC_SPI1) Transmit Next Pointer Register
+AT91C_SPI1_TCR EQU (0xFFFE410C) ;- (PDC_SPI1) Transmit Counter Register
+AT91C_SPI1_RCR EQU (0xFFFE4104) ;- (PDC_SPI1) Receive Counter Register
+AT91C_SPI1_RNPR EQU (0xFFFE4110) ;- (PDC_SPI1) Receive Next Pointer Register
+AT91C_SPI1_RNCR EQU (0xFFFE4114) ;- (PDC_SPI1) Receive Next Counter Register
+AT91C_SPI1_PTSR EQU (0xFFFE4124) ;- (PDC_SPI1) PDC Transfer Status Register
+// - ========== Register definition for SPI1 peripheral ==========
+AT91C_SPI1_IMR EQU (0xFFFE401C) ;- (SPI1) Interrupt Mask Register
+AT91C_SPI1_IER EQU (0xFFFE4014) ;- (SPI1) Interrupt Enable Register
+AT91C_SPI1_MR EQU (0xFFFE4004) ;- (SPI1) Mode Register
+AT91C_SPI1_RDR EQU (0xFFFE4008) ;- (SPI1) Receive Data Register
+AT91C_SPI1_IDR EQU (0xFFFE4018) ;- (SPI1) Interrupt Disable Register
+AT91C_SPI1_SR EQU (0xFFFE4010) ;- (SPI1) Status Register
+AT91C_SPI1_TDR EQU (0xFFFE400C) ;- (SPI1) Transmit Data Register
+AT91C_SPI1_CR EQU (0xFFFE4000) ;- (SPI1) Control Register
+AT91C_SPI1_CSR EQU (0xFFFE4030) ;- (SPI1) Chip Select Register
+// - ========== Register definition for PDC_SPI0 peripheral ==========
+AT91C_SPI0_PTCR EQU (0xFFFE0120) ;- (PDC_SPI0) PDC Transfer Control Register
+AT91C_SPI0_TPR EQU (0xFFFE0108) ;- (PDC_SPI0) Transmit Pointer Register
+AT91C_SPI0_TCR EQU (0xFFFE010C) ;- (PDC_SPI0) Transmit Counter Register
+AT91C_SPI0_RCR EQU (0xFFFE0104) ;- (PDC_SPI0) Receive Counter Register
+AT91C_SPI0_PTSR EQU (0xFFFE0124) ;- (PDC_SPI0) PDC Transfer Status Register
+AT91C_SPI0_RNPR EQU (0xFFFE0110) ;- (PDC_SPI0) Receive Next Pointer Register
+AT91C_SPI0_RPR EQU (0xFFFE0100) ;- (PDC_SPI0) Receive Pointer Register
+AT91C_SPI0_TNCR EQU (0xFFFE011C) ;- (PDC_SPI0) Transmit Next Counter Register
+AT91C_SPI0_RNCR EQU (0xFFFE0114) ;- (PDC_SPI0) Receive Next Counter Register
+AT91C_SPI0_TNPR EQU (0xFFFE0118) ;- (PDC_SPI0) Transmit Next Pointer Register
+// - ========== Register definition for SPI0 peripheral ==========
+AT91C_SPI0_IER EQU (0xFFFE0014) ;- (SPI0) Interrupt Enable Register
+AT91C_SPI0_SR EQU (0xFFFE0010) ;- (SPI0) Status Register
+AT91C_SPI0_IDR EQU (0xFFFE0018) ;- (SPI0) Interrupt Disable Register
+AT91C_SPI0_CR EQU (0xFFFE0000) ;- (SPI0) Control Register
+AT91C_SPI0_MR EQU (0xFFFE0004) ;- (SPI0) Mode Register
+AT91C_SPI0_IMR EQU (0xFFFE001C) ;- (SPI0) Interrupt Mask Register
+AT91C_SPI0_TDR EQU (0xFFFE000C) ;- (SPI0) Transmit Data Register
+AT91C_SPI0_RDR EQU (0xFFFE0008) ;- (SPI0) Receive Data Register
+AT91C_SPI0_CSR EQU (0xFFFE0030) ;- (SPI0) Chip Select Register
+// - ========== Register definition for PDC_US1 peripheral ==========
+AT91C_US1_RNCR EQU (0xFFFC4114) ;- (PDC_US1) Receive Next Counter Register
+AT91C_US1_PTCR EQU (0xFFFC4120) ;- (PDC_US1) PDC Transfer Control Register
+AT91C_US1_TCR EQU (0xFFFC410C) ;- (PDC_US1) Transmit Counter Register
+AT91C_US1_PTSR EQU (0xFFFC4124) ;- (PDC_US1) PDC Transfer Status Register
+AT91C_US1_TNPR EQU (0xFFFC4118) ;- (PDC_US1) Transmit Next Pointer Register
+AT91C_US1_RCR EQU (0xFFFC4104) ;- (PDC_US1) Receive Counter Register
+AT91C_US1_RNPR EQU (0xFFFC4110) ;- (PDC_US1) Receive Next Pointer Register
+AT91C_US1_RPR EQU (0xFFFC4100) ;- (PDC_US1) Receive Pointer Register
+AT91C_US1_TNCR EQU (0xFFFC411C) ;- (PDC_US1) Transmit Next Counter Register
+AT91C_US1_TPR EQU (0xFFFC4108) ;- (PDC_US1) Transmit Pointer Register
+// - ========== Register definition for US1 peripheral ==========
+AT91C_US1_IF EQU (0xFFFC404C) ;- (US1) IRDA_FILTER Register
+AT91C_US1_NER EQU (0xFFFC4044) ;- (US1) Nb Errors Register
+AT91C_US1_RTOR EQU (0xFFFC4024) ;- (US1) Receiver Time-out Register
+AT91C_US1_CSR EQU (0xFFFC4014) ;- (US1) Channel Status Register
+AT91C_US1_IDR EQU (0xFFFC400C) ;- (US1) Interrupt Disable Register
+AT91C_US1_IER EQU (0xFFFC4008) ;- (US1) Interrupt Enable Register
+AT91C_US1_THR EQU (0xFFFC401C) ;- (US1) Transmitter Holding Register
+AT91C_US1_TTGR EQU (0xFFFC4028) ;- (US1) Transmitter Time-guard Register
+AT91C_US1_RHR EQU (0xFFFC4018) ;- (US1) Receiver Holding Register
+AT91C_US1_BRGR EQU (0xFFFC4020) ;- (US1) Baud Rate Generator Register
+AT91C_US1_IMR EQU (0xFFFC4010) ;- (US1) Interrupt Mask Register
+AT91C_US1_FIDI EQU (0xFFFC4040) ;- (US1) FI_DI_Ratio Register
+AT91C_US1_CR EQU (0xFFFC4000) ;- (US1) Control Register
+AT91C_US1_MR EQU (0xFFFC4004) ;- (US1) Mode Register
+// - ========== Register definition for PDC_US0 peripheral ==========
+AT91C_US0_TNPR EQU (0xFFFC0118) ;- (PDC_US0) Transmit Next Pointer Register
+AT91C_US0_RNPR EQU (0xFFFC0110) ;- (PDC_US0) Receive Next Pointer Register
+AT91C_US0_TCR EQU (0xFFFC010C) ;- (PDC_US0) Transmit Counter Register
+AT91C_US0_PTCR EQU (0xFFFC0120) ;- (PDC_US0) PDC Transfer Control Register
+AT91C_US0_PTSR EQU (0xFFFC0124) ;- (PDC_US0) PDC Transfer Status Register
+AT91C_US0_TNCR EQU (0xFFFC011C) ;- (PDC_US0) Transmit Next Counter Register
+AT91C_US0_TPR EQU (0xFFFC0108) ;- (PDC_US0) Transmit Pointer Register
+AT91C_US0_RCR EQU (0xFFFC0104) ;- (PDC_US0) Receive Counter Register
+AT91C_US0_RPR EQU (0xFFFC0100) ;- (PDC_US0) Receive Pointer Register
+AT91C_US0_RNCR EQU (0xFFFC0114) ;- (PDC_US0) Receive Next Counter Register
+// - ========== Register definition for US0 peripheral ==========
+AT91C_US0_BRGR EQU (0xFFFC0020) ;- (US0) Baud Rate Generator Register
+AT91C_US0_NER EQU (0xFFFC0044) ;- (US0) Nb Errors Register
+AT91C_US0_CR EQU (0xFFFC0000) ;- (US0) Control Register
+AT91C_US0_IMR EQU (0xFFFC0010) ;- (US0) Interrupt Mask Register
+AT91C_US0_FIDI EQU (0xFFFC0040) ;- (US0) FI_DI_Ratio Register
+AT91C_US0_TTGR EQU (0xFFFC0028) ;- (US0) Transmitter Time-guard Register
+AT91C_US0_MR EQU (0xFFFC0004) ;- (US0) Mode Register
+AT91C_US0_RTOR EQU (0xFFFC0024) ;- (US0) Receiver Time-out Register
+AT91C_US0_CSR EQU (0xFFFC0014) ;- (US0) Channel Status Register
+AT91C_US0_RHR EQU (0xFFFC0018) ;- (US0) Receiver Holding Register
+AT91C_US0_IDR EQU (0xFFFC000C) ;- (US0) Interrupt Disable Register
+AT91C_US0_THR EQU (0xFFFC001C) ;- (US0) Transmitter Holding Register
+AT91C_US0_IF EQU (0xFFFC004C) ;- (US0) IRDA_FILTER Register
+AT91C_US0_IER EQU (0xFFFC0008) ;- (US0) Interrupt Enable Register
+// - ========== Register definition for PDC_SSC peripheral ==========
+AT91C_SSC_TNCR EQU (0xFFFD411C) ;- (PDC_SSC) Transmit Next Counter Register
+AT91C_SSC_RPR EQU (0xFFFD4100) ;- (PDC_SSC) Receive Pointer Register
+AT91C_SSC_RNCR EQU (0xFFFD4114) ;- (PDC_SSC) Receive Next Counter Register
+AT91C_SSC_TPR EQU (0xFFFD4108) ;- (PDC_SSC) Transmit Pointer Register
+AT91C_SSC_PTCR EQU (0xFFFD4120) ;- (PDC_SSC) PDC Transfer Control Register
+AT91C_SSC_TCR EQU (0xFFFD410C) ;- (PDC_SSC) Transmit Counter Register
+AT91C_SSC_RCR EQU (0xFFFD4104) ;- (PDC_SSC) Receive Counter Register
+AT91C_SSC_RNPR EQU (0xFFFD4110) ;- (PDC_SSC) Receive Next Pointer Register
+AT91C_SSC_TNPR EQU (0xFFFD4118) ;- (PDC_SSC) Transmit Next Pointer Register
+AT91C_SSC_PTSR EQU (0xFFFD4124) ;- (PDC_SSC) PDC Transfer Status Register
+// - ========== Register definition for SSC peripheral ==========
+AT91C_SSC_RHR EQU (0xFFFD4020) ;- (SSC) Receive Holding Register
+AT91C_SSC_RSHR EQU (0xFFFD4030) ;- (SSC) Receive Sync Holding Register
+AT91C_SSC_TFMR EQU (0xFFFD401C) ;- (SSC) Transmit Frame Mode Register
+AT91C_SSC_IDR EQU (0xFFFD4048) ;- (SSC) Interrupt Disable Register
+AT91C_SSC_THR EQU (0xFFFD4024) ;- (SSC) Transmit Holding Register
+AT91C_SSC_RCMR EQU (0xFFFD4010) ;- (SSC) Receive Clock ModeRegister
+AT91C_SSC_IER EQU (0xFFFD4044) ;- (SSC) Interrupt Enable Register
+AT91C_SSC_TSHR EQU (0xFFFD4034) ;- (SSC) Transmit Sync Holding Register
+AT91C_SSC_SR EQU (0xFFFD4040) ;- (SSC) Status Register
+AT91C_SSC_CMR EQU (0xFFFD4004) ;- (SSC) Clock Mode Register
+AT91C_SSC_TCMR EQU (0xFFFD4018) ;- (SSC) Transmit Clock Mode Register
+AT91C_SSC_CR EQU (0xFFFD4000) ;- (SSC) Control Register
+AT91C_SSC_IMR EQU (0xFFFD404C) ;- (SSC) Interrupt Mask Register
+AT91C_SSC_RFMR EQU (0xFFFD4014) ;- (SSC) Receive Frame Mode Register
+// - ========== Register definition for TWI peripheral ==========
+AT91C_TWI_IER EQU (0xFFFB8024) ;- (TWI) Interrupt Enable Register
+AT91C_TWI_CR EQU (0xFFFB8000) ;- (TWI) Control Register
+AT91C_TWI_SR EQU (0xFFFB8020) ;- (TWI) Status Register
+AT91C_TWI_IMR EQU (0xFFFB802C) ;- (TWI) Interrupt Mask Register
+AT91C_TWI_THR EQU (0xFFFB8034) ;- (TWI) Transmit Holding Register
+AT91C_TWI_IDR EQU (0xFFFB8028) ;- (TWI) Interrupt Disable Register
+AT91C_TWI_IADR EQU (0xFFFB800C) ;- (TWI) Internal Address Register
+AT91C_TWI_MMR EQU (0xFFFB8004) ;- (TWI) Master Mode Register
+AT91C_TWI_CWGR EQU (0xFFFB8010) ;- (TWI) Clock Waveform Generator Register
+AT91C_TWI_RHR EQU (0xFFFB8030) ;- (TWI) Receive Holding Register
+// - ========== Register definition for PWMC_CH3 peripheral ==========
+AT91C_PWMC_CH3_CUPDR EQU (0xFFFCC270) ;- (PWMC_CH3) Channel Update Register
+AT91C_PWMC_CH3_Reserved EQU (0xFFFCC274) ;- (PWMC_CH3) Reserved
+AT91C_PWMC_CH3_CPRDR EQU (0xFFFCC268) ;- (PWMC_CH3) Channel Period Register
+AT91C_PWMC_CH3_CDTYR EQU (0xFFFCC264) ;- (PWMC_CH3) Channel Duty Cycle Register
+AT91C_PWMC_CH3_CCNTR EQU (0xFFFCC26C) ;- (PWMC_CH3) Channel Counter Register
+AT91C_PWMC_CH3_CMR EQU (0xFFFCC260) ;- (PWMC_CH3) Channel Mode Register
+// - ========== Register definition for PWMC_CH2 peripheral ==========
+AT91C_PWMC_CH2_Reserved EQU (0xFFFCC254) ;- (PWMC_CH2) Reserved
+AT91C_PWMC_CH2_CMR EQU (0xFFFCC240) ;- (PWMC_CH2) Channel Mode Register
+AT91C_PWMC_CH2_CCNTR EQU (0xFFFCC24C) ;- (PWMC_CH2) Channel Counter Register
+AT91C_PWMC_CH2_CPRDR EQU (0xFFFCC248) ;- (PWMC_CH2) Channel Period Register
+AT91C_PWMC_CH2_CUPDR EQU (0xFFFCC250) ;- (PWMC_CH2) Channel Update Register
+AT91C_PWMC_CH2_CDTYR EQU (0xFFFCC244) ;- (PWMC_CH2) Channel Duty Cycle Register
+// - ========== Register definition for PWMC_CH1 peripheral ==========
+AT91C_PWMC_CH1_Reserved EQU (0xFFFCC234) ;- (PWMC_CH1) Reserved
+AT91C_PWMC_CH1_CUPDR EQU (0xFFFCC230) ;- (PWMC_CH1) Channel Update Register
+AT91C_PWMC_CH1_CPRDR EQU (0xFFFCC228) ;- (PWMC_CH1) Channel Period Register
+AT91C_PWMC_CH1_CCNTR EQU (0xFFFCC22C) ;- (PWMC_CH1) Channel Counter Register
+AT91C_PWMC_CH1_CDTYR EQU (0xFFFCC224) ;- (PWMC_CH1) Channel Duty Cycle Register
+AT91C_PWMC_CH1_CMR EQU (0xFFFCC220) ;- (PWMC_CH1) Channel Mode Register
+// - ========== Register definition for PWMC_CH0 peripheral ==========
+AT91C_PWMC_CH0_Reserved EQU (0xFFFCC214) ;- (PWMC_CH0) Reserved
+AT91C_PWMC_CH0_CPRDR EQU (0xFFFCC208) ;- (PWMC_CH0) Channel Period Register
+AT91C_PWMC_CH0_CDTYR EQU (0xFFFCC204) ;- (PWMC_CH0) Channel Duty Cycle Register
+AT91C_PWMC_CH0_CMR EQU (0xFFFCC200) ;- (PWMC_CH0) Channel Mode Register
+AT91C_PWMC_CH0_CUPDR EQU (0xFFFCC210) ;- (PWMC_CH0) Channel Update Register
+AT91C_PWMC_CH0_CCNTR EQU (0xFFFCC20C) ;- (PWMC_CH0) Channel Counter Register
+// - ========== Register definition for PWMC peripheral ==========
+AT91C_PWMC_IDR EQU (0xFFFCC014) ;- (PWMC) PWMC Interrupt Disable Register
+AT91C_PWMC_DIS EQU (0xFFFCC008) ;- (PWMC) PWMC Disable Register
+AT91C_PWMC_IER EQU (0xFFFCC010) ;- (PWMC) PWMC Interrupt Enable Register
+AT91C_PWMC_VR EQU (0xFFFCC0FC) ;- (PWMC) PWMC Version Register
+AT91C_PWMC_ISR EQU (0xFFFCC01C) ;- (PWMC) PWMC Interrupt Status Register
+AT91C_PWMC_SR EQU (0xFFFCC00C) ;- (PWMC) PWMC Status Register
+AT91C_PWMC_IMR EQU (0xFFFCC018) ;- (PWMC) PWMC Interrupt Mask Register
+AT91C_PWMC_MR EQU (0xFFFCC000) ;- (PWMC) PWMC Mode Register
+AT91C_PWMC_ENA EQU (0xFFFCC004) ;- (PWMC) PWMC Enable Register
+// - ========== Register definition for UDP peripheral ==========
+AT91C_UDP_IMR EQU (0xFFFB0018) ;- (UDP) Interrupt Mask Register
+AT91C_UDP_FADDR EQU (0xFFFB0008) ;- (UDP) Function Address Register
+AT91C_UDP_NUM EQU (0xFFFB0000) ;- (UDP) Frame Number Register
+AT91C_UDP_FDR EQU (0xFFFB0050) ;- (UDP) Endpoint FIFO Data Register
+AT91C_UDP_ISR EQU (0xFFFB001C) ;- (UDP) Interrupt Status Register
+AT91C_UDP_CSR EQU (0xFFFB0030) ;- (UDP) Endpoint Control and Status Register
+AT91C_UDP_IDR EQU (0xFFFB0014) ;- (UDP) Interrupt Disable Register
+AT91C_UDP_ICR EQU (0xFFFB0020) ;- (UDP) Interrupt Clear Register
+AT91C_UDP_RSTEP EQU (0xFFFB0028) ;- (UDP) Reset Endpoint Register
+AT91C_UDP_TXVC EQU (0xFFFB0074) ;- (UDP) Transceiver Control Register
+AT91C_UDP_GLBSTATE EQU (0xFFFB0004) ;- (UDP) Global State Register
+AT91C_UDP_IER EQU (0xFFFB0010) ;- (UDP) Interrupt Enable Register
+// - ========== Register definition for TC0 peripheral ==========
+AT91C_TC0_SR EQU (0xFFFA0020) ;- (TC0) Status Register
+AT91C_TC0_RC EQU (0xFFFA001C) ;- (TC0) Register C
+AT91C_TC0_RB EQU (0xFFFA0018) ;- (TC0) Register B
+AT91C_TC0_CCR EQU (0xFFFA0000) ;- (TC0) Channel Control Register
+AT91C_TC0_CMR EQU (0xFFFA0004) ;- (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+AT91C_TC0_IER EQU (0xFFFA0024) ;- (TC0) Interrupt Enable Register
+AT91C_TC0_RA EQU (0xFFFA0014) ;- (TC0) Register A
+AT91C_TC0_IDR EQU (0xFFFA0028) ;- (TC0) Interrupt Disable Register
+AT91C_TC0_CV EQU (0xFFFA0010) ;- (TC0) Counter Value
+AT91C_TC0_IMR EQU (0xFFFA002C) ;- (TC0) Interrupt Mask Register
+// - ========== Register definition for TC1 peripheral ==========
+AT91C_TC1_RB EQU (0xFFFA0058) ;- (TC1) Register B
+AT91C_TC1_CCR EQU (0xFFFA0040) ;- (TC1) Channel Control Register
+AT91C_TC1_IER EQU (0xFFFA0064) ;- (TC1) Interrupt Enable Register
+AT91C_TC1_IDR EQU (0xFFFA0068) ;- (TC1) Interrupt Disable Register
+AT91C_TC1_SR EQU (0xFFFA0060) ;- (TC1) Status Register
+AT91C_TC1_CMR EQU (0xFFFA0044) ;- (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+AT91C_TC1_RA EQU (0xFFFA0054) ;- (TC1) Register A
+AT91C_TC1_RC EQU (0xFFFA005C) ;- (TC1) Register C
+AT91C_TC1_IMR EQU (0xFFFA006C) ;- (TC1) Interrupt Mask Register
+AT91C_TC1_CV EQU (0xFFFA0050) ;- (TC1) Counter Value
+// - ========== Register definition for TC2 peripheral ==========
+AT91C_TC2_CMR EQU (0xFFFA0084) ;- (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+AT91C_TC2_CCR EQU (0xFFFA0080) ;- (TC2) Channel Control Register
+AT91C_TC2_CV EQU (0xFFFA0090) ;- (TC2) Counter Value
+AT91C_TC2_RA EQU (0xFFFA0094) ;- (TC2) Register A
+AT91C_TC2_RB EQU (0xFFFA0098) ;- (TC2) Register B
+AT91C_TC2_IDR EQU (0xFFFA00A8) ;- (TC2) Interrupt Disable Register
+AT91C_TC2_IMR EQU (0xFFFA00AC) ;- (TC2) Interrupt Mask Register
+AT91C_TC2_RC EQU (0xFFFA009C) ;- (TC2) Register C
+AT91C_TC2_IER EQU (0xFFFA00A4) ;- (TC2) Interrupt Enable Register
+AT91C_TC2_SR EQU (0xFFFA00A0) ;- (TC2) Status Register
+// - ========== Register definition for TCB peripheral ==========
+AT91C_TCB_BMR EQU (0xFFFA00C4) ;- (TCB) TC Block Mode Register
+AT91C_TCB_BCR EQU (0xFFFA00C0) ;- (TCB) TC Block Control Register
+// - ========== Register definition for CAN_MB0 peripheral ==========
+AT91C_CAN_MB0_MDL EQU (0xFFFD0214) ;- (CAN_MB0) MailBox Data Low Register
+AT91C_CAN_MB0_MAM EQU (0xFFFD0204) ;- (CAN_MB0) MailBox Acceptance Mask Register
+AT91C_CAN_MB0_MCR EQU (0xFFFD021C) ;- (CAN_MB0) MailBox Control Register
+AT91C_CAN_MB0_MID EQU (0xFFFD0208) ;- (CAN_MB0) MailBox ID Register
+AT91C_CAN_MB0_MSR EQU (0xFFFD0210) ;- (CAN_MB0) MailBox Status Register
+AT91C_CAN_MB0_MFID EQU (0xFFFD020C) ;- (CAN_MB0) MailBox Family ID Register
+AT91C_CAN_MB0_MDH EQU (0xFFFD0218) ;- (CAN_MB0) MailBox Data High Register
+AT91C_CAN_MB0_MMR EQU (0xFFFD0200) ;- (CAN_MB0) MailBox Mode Register
+// - ========== Register definition for CAN_MB1 peripheral ==========
+AT91C_CAN_MB1_MDL EQU (0xFFFD0234) ;- (CAN_MB1) MailBox Data Low Register
+AT91C_CAN_MB1_MID EQU (0xFFFD0228) ;- (CAN_MB1) MailBox ID Register
+AT91C_CAN_MB1_MMR EQU (0xFFFD0220) ;- (CAN_MB1) MailBox Mode Register
+AT91C_CAN_MB1_MSR EQU (0xFFFD0230) ;- (CAN_MB1) MailBox Status Register
+AT91C_CAN_MB1_MAM EQU (0xFFFD0224) ;- (CAN_MB1) MailBox Acceptance Mask Register
+AT91C_CAN_MB1_MDH EQU (0xFFFD0238) ;- (CAN_MB1) MailBox Data High Register
+AT91C_CAN_MB1_MCR EQU (0xFFFD023C) ;- (CAN_MB1) MailBox Control Register
+AT91C_CAN_MB1_MFID EQU (0xFFFD022C) ;- (CAN_MB1) MailBox Family ID Register
+// - ========== Register definition for CAN_MB2 peripheral ==========
+AT91C_CAN_MB2_MCR EQU (0xFFFD025C) ;- (CAN_MB2) MailBox Control Register
+AT91C_CAN_MB2_MDH EQU (0xFFFD0258) ;- (CAN_MB2) MailBox Data High Register
+AT91C_CAN_MB2_MID EQU (0xFFFD0248) ;- (CAN_MB2) MailBox ID Register
+AT91C_CAN_MB2_MDL EQU (0xFFFD0254) ;- (CAN_MB2) MailBox Data Low Register
+AT91C_CAN_MB2_MMR EQU (0xFFFD0240) ;- (CAN_MB2) MailBox Mode Register
+AT91C_CAN_MB2_MAM EQU (0xFFFD0244) ;- (CAN_MB2) MailBox Acceptance Mask Register
+AT91C_CAN_MB2_MFID EQU (0xFFFD024C) ;- (CAN_MB2) MailBox Family ID Register
+AT91C_CAN_MB2_MSR EQU (0xFFFD0250) ;- (CAN_MB2) MailBox Status Register
+// - ========== Register definition for CAN_MB3 peripheral ==========
+AT91C_CAN_MB3_MFID EQU (0xFFFD026C) ;- (CAN_MB3) MailBox Family ID Register
+AT91C_CAN_MB3_MAM EQU (0xFFFD0264) ;- (CAN_MB3) MailBox Acceptance Mask Register
+AT91C_CAN_MB3_MID EQU (0xFFFD0268) ;- (CAN_MB3) MailBox ID Register
+AT91C_CAN_MB3_MCR EQU (0xFFFD027C) ;- (CAN_MB3) MailBox Control Register
+AT91C_CAN_MB3_MMR EQU (0xFFFD0260) ;- (CAN_MB3) MailBox Mode Register
+AT91C_CAN_MB3_MSR EQU (0xFFFD0270) ;- (CAN_MB3) MailBox Status Register
+AT91C_CAN_MB3_MDL EQU (0xFFFD0274) ;- (CAN_MB3) MailBox Data Low Register
+AT91C_CAN_MB3_MDH EQU (0xFFFD0278) ;- (CAN_MB3) MailBox Data High Register
+// - ========== Register definition for CAN_MB4 peripheral ==========
+AT91C_CAN_MB4_MID EQU (0xFFFD0288) ;- (CAN_MB4) MailBox ID Register
+AT91C_CAN_MB4_MMR EQU (0xFFFD0280) ;- (CAN_MB4) MailBox Mode Register
+AT91C_CAN_MB4_MDH EQU (0xFFFD0298) ;- (CAN_MB4) MailBox Data High Register
+AT91C_CAN_MB4_MFID EQU (0xFFFD028C) ;- (CAN_MB4) MailBox Family ID Register
+AT91C_CAN_MB4_MSR EQU (0xFFFD0290) ;- (CAN_MB4) MailBox Status Register
+AT91C_CAN_MB4_MCR EQU (0xFFFD029C) ;- (CAN_MB4) MailBox Control Register
+AT91C_CAN_MB4_MDL EQU (0xFFFD0294) ;- (CAN_MB4) MailBox Data Low Register
+AT91C_CAN_MB4_MAM EQU (0xFFFD0284) ;- (CAN_MB4) MailBox Acceptance Mask Register
+// - ========== Register definition for CAN_MB5 peripheral ==========
+AT91C_CAN_MB5_MSR EQU (0xFFFD02B0) ;- (CAN_MB5) MailBox Status Register
+AT91C_CAN_MB5_MCR EQU (0xFFFD02BC) ;- (CAN_MB5) MailBox Control Register
+AT91C_CAN_MB5_MFID EQU (0xFFFD02AC) ;- (CAN_MB5) MailBox Family ID Register
+AT91C_CAN_MB5_MDH EQU (0xFFFD02B8) ;- (CAN_MB5) MailBox Data High Register
+AT91C_CAN_MB5_MID EQU (0xFFFD02A8) ;- (CAN_MB5) MailBox ID Register
+AT91C_CAN_MB5_MMR EQU (0xFFFD02A0) ;- (CAN_MB5) MailBox Mode Register
+AT91C_CAN_MB5_MDL EQU (0xFFFD02B4) ;- (CAN_MB5) MailBox Data Low Register
+AT91C_CAN_MB5_MAM EQU (0xFFFD02A4) ;- (CAN_MB5) MailBox Acceptance Mask Register
+// - ========== Register definition for CAN_MB6 peripheral ==========
+AT91C_CAN_MB6_MFID EQU (0xFFFD02CC) ;- (CAN_MB6) MailBox Family ID Register
+AT91C_CAN_MB6_MID EQU (0xFFFD02C8) ;- (CAN_MB6) MailBox ID Register
+AT91C_CAN_MB6_MAM EQU (0xFFFD02C4) ;- (CAN_MB6) MailBox Acceptance Mask Register
+AT91C_CAN_MB6_MSR EQU (0xFFFD02D0) ;- (CAN_MB6) MailBox Status Register
+AT91C_CAN_MB6_MDL EQU (0xFFFD02D4) ;- (CAN_MB6) MailBox Data Low Register
+AT91C_CAN_MB6_MCR EQU (0xFFFD02DC) ;- (CAN_MB6) MailBox Control Register
+AT91C_CAN_MB6_MDH EQU (0xFFFD02D8) ;- (CAN_MB6) MailBox Data High Register
+AT91C_CAN_MB6_MMR EQU (0xFFFD02C0) ;- (CAN_MB6) MailBox Mode Register
+// - ========== Register definition for CAN_MB7 peripheral ==========
+AT91C_CAN_MB7_MCR EQU (0xFFFD02FC) ;- (CAN_MB7) MailBox Control Register
+AT91C_CAN_MB7_MDH EQU (0xFFFD02F8) ;- (CAN_MB7) MailBox Data High Register
+AT91C_CAN_MB7_MFID EQU (0xFFFD02EC) ;- (CAN_MB7) MailBox Family ID Register
+AT91C_CAN_MB7_MDL EQU (0xFFFD02F4) ;- (CAN_MB7) MailBox Data Low Register
+AT91C_CAN_MB7_MID EQU (0xFFFD02E8) ;- (CAN_MB7) MailBox ID Register
+AT91C_CAN_MB7_MMR EQU (0xFFFD02E0) ;- (CAN_MB7) MailBox Mode Register
+AT91C_CAN_MB7_MAM EQU (0xFFFD02E4) ;- (CAN_MB7) MailBox Acceptance Mask Register
+AT91C_CAN_MB7_MSR EQU (0xFFFD02F0) ;- (CAN_MB7) MailBox Status Register
+// - ========== Register definition for CAN peripheral ==========
+AT91C_CAN_TCR EQU (0xFFFD0024) ;- (CAN) Transfer Command Register
+AT91C_CAN_IMR EQU (0xFFFD000C) ;- (CAN) Interrupt Mask Register
+AT91C_CAN_IER EQU (0xFFFD0004) ;- (CAN) Interrupt Enable Register
+AT91C_CAN_ECR EQU (0xFFFD0020) ;- (CAN) Error Counter Register
+AT91C_CAN_TIMESTP EQU (0xFFFD001C) ;- (CAN) Time Stamp Register
+AT91C_CAN_MR EQU (0xFFFD0000) ;- (CAN) Mode Register
+AT91C_CAN_IDR EQU (0xFFFD0008) ;- (CAN) Interrupt Disable Register
+AT91C_CAN_ACR EQU (0xFFFD0028) ;- (CAN) Abort Command Register
+AT91C_CAN_TIM EQU (0xFFFD0018) ;- (CAN) Timer Register
+AT91C_CAN_SR EQU (0xFFFD0010) ;- (CAN) Status Register
+AT91C_CAN_BR EQU (0xFFFD0014) ;- (CAN) Baudrate Register
+AT91C_CAN_VR EQU (0xFFFD00FC) ;- (CAN) Version Register
+// - ========== Register definition for EMAC peripheral ==========
+AT91C_EMAC_ISR EQU (0xFFFDC024) ;- (EMAC) Interrupt Status Register
+AT91C_EMAC_SA4H EQU (0xFFFDC0B4) ;- (EMAC) Specific Address 4 Top, Last 2 bytes
+AT91C_EMAC_SA1L EQU (0xFFFDC098) ;- (EMAC) Specific Address 1 Bottom, First 4 bytes
+AT91C_EMAC_ELE EQU (0xFFFDC078) ;- (EMAC) Excessive Length Errors Register
+AT91C_EMAC_LCOL EQU (0xFFFDC05C) ;- (EMAC) Late Collision Register
+AT91C_EMAC_RLE EQU (0xFFFDC088) ;- (EMAC) Receive Length Field Mismatch Register
+AT91C_EMAC_WOL EQU (0xFFFDC0C4) ;- (EMAC) Wake On LAN Register
+AT91C_EMAC_DTF EQU (0xFFFDC058) ;- (EMAC) Deferred Transmission Frame Register
+AT91C_EMAC_TUND EQU (0xFFFDC064) ;- (EMAC) Transmit Underrun Error Register
+AT91C_EMAC_NCR EQU (0xFFFDC000) ;- (EMAC) Network Control Register
+AT91C_EMAC_SA4L EQU (0xFFFDC0B0) ;- (EMAC) Specific Address 4 Bottom, First 4 bytes
+AT91C_EMAC_RSR EQU (0xFFFDC020) ;- (EMAC) Receive Status Register
+AT91C_EMAC_SA3L EQU (0xFFFDC0A8) ;- (EMAC) Specific Address 3 Bottom, First 4 bytes
+AT91C_EMAC_TSR EQU (0xFFFDC014) ;- (EMAC) Transmit Status Register
+AT91C_EMAC_IDR EQU (0xFFFDC02C) ;- (EMAC) Interrupt Disable Register
+AT91C_EMAC_RSE EQU (0xFFFDC074) ;- (EMAC) Receive Symbol Errors Register
+AT91C_EMAC_ECOL EQU (0xFFFDC060) ;- (EMAC) Excessive Collision Register
+AT91C_EMAC_TID EQU (0xFFFDC0B8) ;- (EMAC) Type ID Checking Register
+AT91C_EMAC_HRB EQU (0xFFFDC090) ;- (EMAC) Hash Address Bottom[31:0]
+AT91C_EMAC_TBQP EQU (0xFFFDC01C) ;- (EMAC) Transmit Buffer Queue Pointer
+AT91C_EMAC_USRIO EQU (0xFFFDC0C0) ;- (EMAC) USER Input/Output Register
+AT91C_EMAC_PTR EQU (0xFFFDC038) ;- (EMAC) Pause Time Register
+AT91C_EMAC_SA2H EQU (0xFFFDC0A4) ;- (EMAC) Specific Address 2 Top, Last 2 bytes
+AT91C_EMAC_ROV EQU (0xFFFDC070) ;- (EMAC) Receive Overrun Errors Register
+AT91C_EMAC_ALE EQU (0xFFFDC054) ;- (EMAC) Alignment Error Register
+AT91C_EMAC_RJA EQU (0xFFFDC07C) ;- (EMAC) Receive Jabbers Register
+AT91C_EMAC_RBQP EQU (0xFFFDC018) ;- (EMAC) Receive Buffer Queue Pointer
+AT91C_EMAC_TPF EQU (0xFFFDC08C) ;- (EMAC) Transmitted Pause Frames Register
+AT91C_EMAC_NCFGR EQU (0xFFFDC004) ;- (EMAC) Network Configuration Register
+AT91C_EMAC_HRT EQU (0xFFFDC094) ;- (EMAC) Hash Address Top[63:32]
+AT91C_EMAC_USF EQU (0xFFFDC080) ;- (EMAC) Undersize Frames Register
+AT91C_EMAC_FCSE EQU (0xFFFDC050) ;- (EMAC) Frame Check Sequence Error Register
+AT91C_EMAC_TPQ EQU (0xFFFDC0BC) ;- (EMAC) Transmit Pause Quantum Register
+AT91C_EMAC_MAN EQU (0xFFFDC034) ;- (EMAC) PHY Maintenance Register
+AT91C_EMAC_FTO EQU (0xFFFDC040) ;- (EMAC) Frames Transmitted OK Register
+AT91C_EMAC_REV EQU (0xFFFDC0FC) ;- (EMAC) Revision Register
+AT91C_EMAC_IMR EQU (0xFFFDC030) ;- (EMAC) Interrupt Mask Register
+AT91C_EMAC_SCF EQU (0xFFFDC044) ;- (EMAC) Single Collision Frame Register
+AT91C_EMAC_PFR EQU (0xFFFDC03C) ;- (EMAC) Pause Frames received Register
+AT91C_EMAC_MCF EQU (0xFFFDC048) ;- (EMAC) Multiple Collision Frame Register
+AT91C_EMAC_NSR EQU (0xFFFDC008) ;- (EMAC) Network Status Register
+AT91C_EMAC_SA2L EQU (0xFFFDC0A0) ;- (EMAC) Specific Address 2 Bottom, First 4 bytes
+AT91C_EMAC_FRO EQU (0xFFFDC04C) ;- (EMAC) Frames Received OK Register
+AT91C_EMAC_IER EQU (0xFFFDC028) ;- (EMAC) Interrupt Enable Register
+AT91C_EMAC_SA1H EQU (0xFFFDC09C) ;- (EMAC) Specific Address 1 Top, Last 2 bytes
+AT91C_EMAC_CSE EQU (0xFFFDC068) ;- (EMAC) Carrier Sense Error Register
+AT91C_EMAC_SA3H EQU (0xFFFDC0AC) ;- (EMAC) Specific Address 3 Top, Last 2 bytes
+AT91C_EMAC_RRE EQU (0xFFFDC06C) ;- (EMAC) Receive Ressource Error Register
+AT91C_EMAC_STE EQU (0xFFFDC084) ;- (EMAC) SQE Test Error Register
+// - ========== Register definition for PDC_ADC peripheral ==========
+AT91C_ADC_PTSR EQU (0xFFFD8124) ;- (PDC_ADC) PDC Transfer Status Register
+AT91C_ADC_PTCR EQU (0xFFFD8120) ;- (PDC_ADC) PDC Transfer Control Register
+AT91C_ADC_TNPR EQU (0xFFFD8118) ;- (PDC_ADC) Transmit Next Pointer Register
+AT91C_ADC_TNCR EQU (0xFFFD811C) ;- (PDC_ADC) Transmit Next Counter Register
+AT91C_ADC_RNPR EQU (0xFFFD8110) ;- (PDC_ADC) Receive Next Pointer Register
+AT91C_ADC_RNCR EQU (0xFFFD8114) ;- (PDC_ADC) Receive Next Counter Register
+AT91C_ADC_RPR EQU (0xFFFD8100) ;- (PDC_ADC) Receive Pointer Register
+AT91C_ADC_TCR EQU (0xFFFD810C) ;- (PDC_ADC) Transmit Counter Register
+AT91C_ADC_TPR EQU (0xFFFD8108) ;- (PDC_ADC) Transmit Pointer Register
+AT91C_ADC_RCR EQU (0xFFFD8104) ;- (PDC_ADC) Receive Counter Register
+// - ========== Register definition for ADC peripheral ==========
+AT91C_ADC_CDR2 EQU (0xFFFD8038) ;- (ADC) ADC Channel Data Register 2
+AT91C_ADC_CDR3 EQU (0xFFFD803C) ;- (ADC) ADC Channel Data Register 3
+AT91C_ADC_CDR0 EQU (0xFFFD8030) ;- (ADC) ADC Channel Data Register 0
+AT91C_ADC_CDR5 EQU (0xFFFD8044) ;- (ADC) ADC Channel Data Register 5
+AT91C_ADC_CHDR EQU (0xFFFD8014) ;- (ADC) ADC Channel Disable Register
+AT91C_ADC_SR EQU (0xFFFD801C) ;- (ADC) ADC Status Register
+AT91C_ADC_CDR4 EQU (0xFFFD8040) ;- (ADC) ADC Channel Data Register 4
+AT91C_ADC_CDR1 EQU (0xFFFD8034) ;- (ADC) ADC Channel Data Register 1
+AT91C_ADC_LCDR EQU (0xFFFD8020) ;- (ADC) ADC Last Converted Data Register
+AT91C_ADC_IDR EQU (0xFFFD8028) ;- (ADC) ADC Interrupt Disable Register
+AT91C_ADC_CR EQU (0xFFFD8000) ;- (ADC) ADC Control Register
+AT91C_ADC_CDR7 EQU (0xFFFD804C) ;- (ADC) ADC Channel Data Register 7
+AT91C_ADC_CDR6 EQU (0xFFFD8048) ;- (ADC) ADC Channel Data Register 6
+AT91C_ADC_IER EQU (0xFFFD8024) ;- (ADC) ADC Interrupt Enable Register
+AT91C_ADC_CHER EQU (0xFFFD8010) ;- (ADC) ADC Channel Enable Register
+AT91C_ADC_CHSR EQU (0xFFFD8018) ;- (ADC) ADC Channel Status Register
+AT91C_ADC_MR EQU (0xFFFD8004) ;- (ADC) ADC Mode Register
+AT91C_ADC_IMR EQU (0xFFFD802C) ;- (ADC) ADC Interrupt Mask Register
+// - ========== Register definition for PDC_AES peripheral ==========
+AT91C_AES_TPR EQU (0xFFFA4108) ;- (PDC_AES) Transmit Pointer Register
+AT91C_AES_PTCR EQU (0xFFFA4120) ;- (PDC_AES) PDC Transfer Control Register
+AT91C_AES_RNPR EQU (0xFFFA4110) ;- (PDC_AES) Receive Next Pointer Register
+AT91C_AES_TNCR EQU (0xFFFA411C) ;- (PDC_AES) Transmit Next Counter Register
+AT91C_AES_TCR EQU (0xFFFA410C) ;- (PDC_AES) Transmit Counter Register
+AT91C_AES_RCR EQU (0xFFFA4104) ;- (PDC_AES) Receive Counter Register
+AT91C_AES_RNCR EQU (0xFFFA4114) ;- (PDC_AES) Receive Next Counter Register
+AT91C_AES_TNPR EQU (0xFFFA4118) ;- (PDC_AES) Transmit Next Pointer Register
+AT91C_AES_RPR EQU (0xFFFA4100) ;- (PDC_AES) Receive Pointer Register
+AT91C_AES_PTSR EQU (0xFFFA4124) ;- (PDC_AES) PDC Transfer Status Register
+// - ========== Register definition for AES peripheral ==========
+AT91C_AES_IVxR EQU (0xFFFA4060) ;- (AES) Initialization Vector x Register
+AT91C_AES_MR EQU (0xFFFA4004) ;- (AES) Mode Register
+AT91C_AES_VR EQU (0xFFFA40FC) ;- (AES) AES Version Register
+AT91C_AES_ODATAxR EQU (0xFFFA4050) ;- (AES) Output Data x Register
+AT91C_AES_IDATAxR EQU (0xFFFA4040) ;- (AES) Input Data x Register
+AT91C_AES_CR EQU (0xFFFA4000) ;- (AES) Control Register
+AT91C_AES_IDR EQU (0xFFFA4014) ;- (AES) Interrupt Disable Register
+AT91C_AES_IMR EQU (0xFFFA4018) ;- (AES) Interrupt Mask Register
+AT91C_AES_IER EQU (0xFFFA4010) ;- (AES) Interrupt Enable Register
+AT91C_AES_KEYWxR EQU (0xFFFA4020) ;- (AES) Key Word x Register
+AT91C_AES_ISR EQU (0xFFFA401C) ;- (AES) Interrupt Status Register
+// - ========== Register definition for PDC_TDES peripheral ==========
+AT91C_TDES_RNCR EQU (0xFFFA8114) ;- (PDC_TDES) Receive Next Counter Register
+AT91C_TDES_TCR EQU (0xFFFA810C) ;- (PDC_TDES) Transmit Counter Register
+AT91C_TDES_RCR EQU (0xFFFA8104) ;- (PDC_TDES) Receive Counter Register
+AT91C_TDES_TNPR EQU (0xFFFA8118) ;- (PDC_TDES) Transmit Next Pointer Register
+AT91C_TDES_RNPR EQU (0xFFFA8110) ;- (PDC_TDES) Receive Next Pointer Register
+AT91C_TDES_RPR EQU (0xFFFA8100) ;- (PDC_TDES) Receive Pointer Register
+AT91C_TDES_TNCR EQU (0xFFFA811C) ;- (PDC_TDES) Transmit Next Counter Register
+AT91C_TDES_TPR EQU (0xFFFA8108) ;- (PDC_TDES) Transmit Pointer Register
+AT91C_TDES_PTSR EQU (0xFFFA8124) ;- (PDC_TDES) PDC Transfer Status Register
+AT91C_TDES_PTCR EQU (0xFFFA8120) ;- (PDC_TDES) PDC Transfer Control Register
+// - ========== Register definition for TDES peripheral ==========
+AT91C_TDES_KEY2WxR EQU (0xFFFA8028) ;- (TDES) Key 2 Word x Register
+AT91C_TDES_KEY3WxR EQU (0xFFFA8030) ;- (TDES) Key 3 Word x Register
+AT91C_TDES_IDR EQU (0xFFFA8014) ;- (TDES) Interrupt Disable Register
+AT91C_TDES_VR EQU (0xFFFA80FC) ;- (TDES) TDES Version Register
+AT91C_TDES_IVxR EQU (0xFFFA8060) ;- (TDES) Initialization Vector x Register
+AT91C_TDES_ODATAxR EQU (0xFFFA8050) ;- (TDES) Output Data x Register
+AT91C_TDES_IMR EQU (0xFFFA8018) ;- (TDES) Interrupt Mask Register
+AT91C_TDES_MR EQU (0xFFFA8004) ;- (TDES) Mode Register
+AT91C_TDES_CR EQU (0xFFFA8000) ;- (TDES) Control Register
+AT91C_TDES_IER EQU (0xFFFA8010) ;- (TDES) Interrupt Enable Register
+AT91C_TDES_ISR EQU (0xFFFA801C) ;- (TDES) Interrupt Status Register
+AT91C_TDES_IDATAxR EQU (0xFFFA8040) ;- (TDES) Input Data x Register
+AT91C_TDES_KEY1WxR EQU (0xFFFA8020) ;- (TDES) Key 1 Word x Register
+
+// - *****************************************************************************
+// - PIO DEFINITIONS FOR AT91SAM7X256
+// - *****************************************************************************
+AT91C_PIO_PA0 EQU (1 << 0) ;- Pin Controlled by PA0
+AT91C_PA0_RXD0 EQU (AT91C_PIO_PA0) ;- USART 0 Receive Data
+AT91C_PIO_PA1 EQU (1 << 1) ;- Pin Controlled by PA1
+AT91C_PA1_TXD0 EQU (AT91C_PIO_PA1) ;- USART 0 Transmit Data
+AT91C_PIO_PA10 EQU (1 << 10) ;- Pin Controlled by PA10
+AT91C_PA10_TWD EQU (AT91C_PIO_PA10) ;- TWI Two-wire Serial Data
+AT91C_PIO_PA11 EQU (1 << 11) ;- Pin Controlled by PA11
+AT91C_PA11_TWCK EQU (AT91C_PIO_PA11) ;- TWI Two-wire Serial Clock
+AT91C_PIO_PA12 EQU (1 << 12) ;- Pin Controlled by PA12
+AT91C_PA12_NPCS00 EQU (AT91C_PIO_PA12) ;- SPI 0 Peripheral Chip Select 0
+AT91C_PIO_PA13 EQU (1 << 13) ;- Pin Controlled by PA13
+AT91C_PA13_NPCS01 EQU (AT91C_PIO_PA13) ;- SPI 0 Peripheral Chip Select 1
+AT91C_PA13_PCK1 EQU (AT91C_PIO_PA13) ;- PMC Programmable Clock Output 1
+AT91C_PIO_PA14 EQU (1 << 14) ;- Pin Controlled by PA14
+AT91C_PA14_NPCS02 EQU (AT91C_PIO_PA14) ;- SPI 0 Peripheral Chip Select 2
+AT91C_PA14_IRQ1 EQU (AT91C_PIO_PA14) ;- External Interrupt 1
+AT91C_PIO_PA15 EQU (1 << 15) ;- Pin Controlled by PA15
+AT91C_PA15_NPCS03 EQU (AT91C_PIO_PA15) ;- SPI 0 Peripheral Chip Select 3
+AT91C_PA15_TCLK2 EQU (AT91C_PIO_PA15) ;- Timer Counter 2 external clock input
+AT91C_PIO_PA16 EQU (1 << 16) ;- Pin Controlled by PA16
+AT91C_PA16_MISO0 EQU (AT91C_PIO_PA16) ;- SPI 0 Master In Slave
+AT91C_PIO_PA17 EQU (1 << 17) ;- Pin Controlled by PA17
+AT91C_PA17_MOSI0 EQU (AT91C_PIO_PA17) ;- SPI 0 Master Out Slave
+AT91C_PIO_PA18 EQU (1 << 18) ;- Pin Controlled by PA18
+AT91C_PA18_SPCK0 EQU (AT91C_PIO_PA18) ;- SPI 0 Serial Clock
+AT91C_PIO_PA19 EQU (1 << 19) ;- Pin Controlled by PA19
+AT91C_PA19_CANRX EQU (AT91C_PIO_PA19) ;- CAN Receive
+AT91C_PIO_PA2 EQU (1 << 2) ;- Pin Controlled by PA2
+AT91C_PA2_SCK0 EQU (AT91C_PIO_PA2) ;- USART 0 Serial Clock
+AT91C_PA2_NPCS11 EQU (AT91C_PIO_PA2) ;- SPI 1 Peripheral Chip Select 1
+AT91C_PIO_PA20 EQU (1 << 20) ;- Pin Controlled by PA20
+AT91C_PA20_CANTX EQU (AT91C_PIO_PA20) ;- CAN Transmit
+AT91C_PIO_PA21 EQU (1 << 21) ;- Pin Controlled by PA21
+AT91C_PA21_TF EQU (AT91C_PIO_PA21) ;- SSC Transmit Frame Sync
+AT91C_PA21_NPCS10 EQU (AT91C_PIO_PA21) ;- SPI 1 Peripheral Chip Select 0
+AT91C_PIO_PA22 EQU (1 << 22) ;- Pin Controlled by PA22
+AT91C_PA22_TK EQU (AT91C_PIO_PA22) ;- SSC Transmit Clock
+AT91C_PA22_SPCK1 EQU (AT91C_PIO_PA22) ;- SPI 1 Serial Clock
+AT91C_PIO_PA23 EQU (1 << 23) ;- Pin Controlled by PA23
+AT91C_PA23_TD EQU (AT91C_PIO_PA23) ;- SSC Transmit data
+AT91C_PA23_MOSI1 EQU (AT91C_PIO_PA23) ;- SPI 1 Master Out Slave
+AT91C_PIO_PA24 EQU (1 << 24) ;- Pin Controlled by PA24
+AT91C_PA24_RD EQU (AT91C_PIO_PA24) ;- SSC Receive Data
+AT91C_PA24_MISO1 EQU (AT91C_PIO_PA24) ;- SPI 1 Master In Slave
+AT91C_PIO_PA25 EQU (1 << 25) ;- Pin Controlled by PA25
+AT91C_PA25_RK EQU (AT91C_PIO_PA25) ;- SSC Receive Clock
+AT91C_PA25_NPCS11 EQU (AT91C_PIO_PA25) ;- SPI 1 Peripheral Chip Select 1
+AT91C_PIO_PA26 EQU (1 << 26) ;- Pin Controlled by PA26
+AT91C_PA26_RF EQU (AT91C_PIO_PA26) ;- SSC Receive Frame Sync
+AT91C_PA26_NPCS12 EQU (AT91C_PIO_PA26) ;- SPI 1 Peripheral Chip Select 2
+AT91C_PIO_PA27 EQU (1 << 27) ;- Pin Controlled by PA27
+AT91C_PA27_DRXD EQU (AT91C_PIO_PA27) ;- DBGU Debug Receive Data
+AT91C_PA27_PCK3 EQU (AT91C_PIO_PA27) ;- PMC Programmable Clock Output 3
+AT91C_PIO_PA28 EQU (1 << 28) ;- Pin Controlled by PA28
+AT91C_PA28_DTXD EQU (AT91C_PIO_PA28) ;- DBGU Debug Transmit Data
+AT91C_PIO_PA29 EQU (1 << 29) ;- Pin Controlled by PA29
+AT91C_PA29_FIQ EQU (AT91C_PIO_PA29) ;- AIC Fast Interrupt Input
+AT91C_PA29_NPCS13 EQU (AT91C_PIO_PA29) ;- SPI 1 Peripheral Chip Select 3
+AT91C_PIO_PA3 EQU (1 << 3) ;- Pin Controlled by PA3
+AT91C_PA3_RTS0 EQU (AT91C_PIO_PA3) ;- USART 0 Ready To Send
+AT91C_PA3_NPCS12 EQU (AT91C_PIO_PA3) ;- SPI 1 Peripheral Chip Select 2
+AT91C_PIO_PA30 EQU (1 << 30) ;- Pin Controlled by PA30
+AT91C_PA30_IRQ0 EQU (AT91C_PIO_PA30) ;- External Interrupt 0
+AT91C_PA30_PCK2 EQU (AT91C_PIO_PA30) ;- PMC Programmable Clock Output 2
+AT91C_PIO_PA4 EQU (1 << 4) ;- Pin Controlled by PA4
+AT91C_PA4_CTS0 EQU (AT91C_PIO_PA4) ;- USART 0 Clear To Send
+AT91C_PA4_NPCS13 EQU (AT91C_PIO_PA4) ;- SPI 1 Peripheral Chip Select 3
+AT91C_PIO_PA5 EQU (1 << 5) ;- Pin Controlled by PA5
+AT91C_PA5_RXD1 EQU (AT91C_PIO_PA5) ;- USART 1 Receive Data
+AT91C_PIO_PA6 EQU (1 << 6) ;- Pin Controlled by PA6
+AT91C_PA6_TXD1 EQU (AT91C_PIO_PA6) ;- USART 1 Transmit Data
+AT91C_PIO_PA7 EQU (1 << 7) ;- Pin Controlled by PA7
+AT91C_PA7_SCK1 EQU (AT91C_PIO_PA7) ;- USART 1 Serial Clock
+AT91C_PA7_NPCS01 EQU (AT91C_PIO_PA7) ;- SPI 0 Peripheral Chip Select 1
+AT91C_PIO_PA8 EQU (1 << 8) ;- Pin Controlled by PA8
+AT91C_PA8_RTS1 EQU (AT91C_PIO_PA8) ;- USART 1 Ready To Send
+AT91C_PA8_NPCS02 EQU (AT91C_PIO_PA8) ;- SPI 0 Peripheral Chip Select 2
+AT91C_PIO_PA9 EQU (1 << 9) ;- Pin Controlled by PA9
+AT91C_PA9_CTS1 EQU (AT91C_PIO_PA9) ;- USART 1 Clear To Send
+AT91C_PA9_NPCS03 EQU (AT91C_PIO_PA9) ;- SPI 0 Peripheral Chip Select 3
+AT91C_PIO_PB0 EQU (1 << 0) ;- Pin Controlled by PB0
+AT91C_PB0_ETXCK_EREFCK EQU (AT91C_PIO_PB0) ;- Ethernet MAC Transmit Clock/Reference Clock
+AT91C_PB0_PCK0 EQU (AT91C_PIO_PB0) ;- PMC Programmable Clock Output 0
+AT91C_PIO_PB1 EQU (1 << 1) ;- Pin Controlled by PB1
+AT91C_PB1_ETXEN EQU (AT91C_PIO_PB1) ;- Ethernet MAC Transmit Enable
+AT91C_PIO_PB10 EQU (1 << 10) ;- Pin Controlled by PB10
+AT91C_PB10_ETX2 EQU (AT91C_PIO_PB10) ;- Ethernet MAC Transmit Data 2
+AT91C_PB10_NPCS11 EQU (AT91C_PIO_PB10) ;- SPI 1 Peripheral Chip Select 1
+AT91C_PIO_PB11 EQU (1 << 11) ;- Pin Controlled by PB11
+AT91C_PB11_ETX3 EQU (AT91C_PIO_PB11) ;- Ethernet MAC Transmit Data 3
+AT91C_PB11_NPCS12 EQU (AT91C_PIO_PB11) ;- SPI 1 Peripheral Chip Select 2
+AT91C_PIO_PB12 EQU (1 << 12) ;- Pin Controlled by PB12
+AT91C_PB12_ETXER EQU (AT91C_PIO_PB12) ;- Ethernet MAC Transmikt Coding Error
+AT91C_PB12_TCLK0 EQU (AT91C_PIO_PB12) ;- Timer Counter 0 external clock input
+AT91C_PIO_PB13 EQU (1 << 13) ;- Pin Controlled by PB13
+AT91C_PB13_ERX2 EQU (AT91C_PIO_PB13) ;- Ethernet MAC Receive Data 2
+AT91C_PB13_NPCS01 EQU (AT91C_PIO_PB13) ;- SPI 0 Peripheral Chip Select 1
+AT91C_PIO_PB14 EQU (1 << 14) ;- Pin Controlled by PB14
+AT91C_PB14_ERX3 EQU (AT91C_PIO_PB14) ;- Ethernet MAC Receive Data 3
+AT91C_PB14_NPCS02 EQU (AT91C_PIO_PB14) ;- SPI 0 Peripheral Chip Select 2
+AT91C_PIO_PB15 EQU (1 << 15) ;- Pin Controlled by PB15
+AT91C_PB15_ERXDV EQU (AT91C_PIO_PB15) ;- Ethernet MAC Receive Data Valid
+AT91C_PIO_PB16 EQU (1 << 16) ;- Pin Controlled by PB16
+AT91C_PB16_ECOL EQU (AT91C_PIO_PB16) ;- Ethernet MAC Collision Detected
+AT91C_PB16_NPCS13 EQU (AT91C_PIO_PB16) ;- SPI 1 Peripheral Chip Select 3
+AT91C_PIO_PB17 EQU (1 << 17) ;- Pin Controlled by PB17
+AT91C_PB17_ERXCK EQU (AT91C_PIO_PB17) ;- Ethernet MAC Receive Clock
+AT91C_PB17_NPCS03 EQU (AT91C_PIO_PB17) ;- SPI 0 Peripheral Chip Select 3
+AT91C_PIO_PB18 EQU (1 << 18) ;- Pin Controlled by PB18
+AT91C_PB18_EF100 EQU (AT91C_PIO_PB18) ;- Ethernet MAC Force 100 Mbits/sec
+AT91C_PB18_ADTRG EQU (AT91C_PIO_PB18) ;- ADC External Trigger
+AT91C_PIO_PB19 EQU (1 << 19) ;- Pin Controlled by PB19
+AT91C_PB19_PWM0 EQU (AT91C_PIO_PB19) ;- PWM Channel 0
+AT91C_PB19_TCLK1 EQU (AT91C_PIO_PB19) ;- Timer Counter 1 external clock input
+AT91C_PIO_PB2 EQU (1 << 2) ;- Pin Controlled by PB2
+AT91C_PB2_ETX0 EQU (AT91C_PIO_PB2) ;- Ethernet MAC Transmit Data 0
+AT91C_PIO_PB20 EQU (1 << 20) ;- Pin Controlled by PB20
+AT91C_PB20_PWM1 EQU (AT91C_PIO_PB20) ;- PWM Channel 1
+AT91C_PB20_PCK0 EQU (AT91C_PIO_PB20) ;- PMC Programmable Clock Output 0
+AT91C_PIO_PB21 EQU (1 << 21) ;- Pin Controlled by PB21
+AT91C_PB21_PWM2 EQU (AT91C_PIO_PB21) ;- PWM Channel 2
+AT91C_PB21_PCK1 EQU (AT91C_PIO_PB21) ;- PMC Programmable Clock Output 1
+AT91C_PIO_PB22 EQU (1 << 22) ;- Pin Controlled by PB22
+AT91C_PB22_PWM3 EQU (AT91C_PIO_PB22) ;- PWM Channel 3
+AT91C_PB22_PCK2 EQU (AT91C_PIO_PB22) ;- PMC Programmable Clock Output 2
+AT91C_PIO_PB23 EQU (1 << 23) ;- Pin Controlled by PB23
+AT91C_PB23_TIOA0 EQU (AT91C_PIO_PB23) ;- Timer Counter 0 Multipurpose Timer I/O Pin A
+AT91C_PB23_DCD1 EQU (AT91C_PIO_PB23) ;- USART 1 Data Carrier Detect
+AT91C_PIO_PB24 EQU (1 << 24) ;- Pin Controlled by PB24
+AT91C_PB24_TIOB0 EQU (AT91C_PIO_PB24) ;- Timer Counter 0 Multipurpose Timer I/O Pin B
+AT91C_PB24_DSR1 EQU (AT91C_PIO_PB24) ;- USART 1 Data Set ready
+AT91C_PIO_PB25 EQU (1 << 25) ;- Pin Controlled by PB25
+AT91C_PB25_TIOA1 EQU (AT91C_PIO_PB25) ;- Timer Counter 1 Multipurpose Timer I/O Pin A
+AT91C_PB25_DTR1 EQU (AT91C_PIO_PB25) ;- USART 1 Data Terminal ready
+AT91C_PIO_PB26 EQU (1 << 26) ;- Pin Controlled by PB26
+AT91C_PB26_TIOB1 EQU (AT91C_PIO_PB26) ;- Timer Counter 1 Multipurpose Timer I/O Pin B
+AT91C_PB26_RI1 EQU (AT91C_PIO_PB26) ;- USART 1 Ring Indicator
+AT91C_PIO_PB27 EQU (1 << 27) ;- Pin Controlled by PB27
+AT91C_PB27_TIOA2 EQU (AT91C_PIO_PB27) ;- Timer Counter 2 Multipurpose Timer I/O Pin A
+AT91C_PB27_PWM0 EQU (AT91C_PIO_PB27) ;- PWM Channel 0
+AT91C_PIO_PB28 EQU (1 << 28) ;- Pin Controlled by PB28
+AT91C_PB28_TIOB2 EQU (AT91C_PIO_PB28) ;- Timer Counter 2 Multipurpose Timer I/O Pin B
+AT91C_PB28_PWM1 EQU (AT91C_PIO_PB28) ;- PWM Channel 1
+AT91C_PIO_PB29 EQU (1 << 29) ;- Pin Controlled by PB29
+AT91C_PB29_PCK1 EQU (AT91C_PIO_PB29) ;- PMC Programmable Clock Output 1
+AT91C_PB29_PWM2 EQU (AT91C_PIO_PB29) ;- PWM Channel 2
+AT91C_PIO_PB3 EQU (1 << 3) ;- Pin Controlled by PB3
+AT91C_PB3_ETX1 EQU (AT91C_PIO_PB3) ;- Ethernet MAC Transmit Data 1
+AT91C_PIO_PB30 EQU (1 << 30) ;- Pin Controlled by PB30
+AT91C_PB30_PCK2 EQU (AT91C_PIO_PB30) ;- PMC Programmable Clock Output 2
+AT91C_PB30_PWM3 EQU (AT91C_PIO_PB30) ;- PWM Channel 3
+AT91C_PIO_PB4 EQU (1 << 4) ;- Pin Controlled by PB4
+AT91C_PB4_ECRS_ECRSDV EQU (AT91C_PIO_PB4) ;- Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
+AT91C_PIO_PB5 EQU (1 << 5) ;- Pin Controlled by PB5
+AT91C_PB5_ERX0 EQU (AT91C_PIO_PB5) ;- Ethernet MAC Receive Data 0
+AT91C_PIO_PB6 EQU (1 << 6) ;- Pin Controlled by PB6
+AT91C_PB6_ERX1 EQU (AT91C_PIO_PB6) ;- Ethernet MAC Receive Data 1
+AT91C_PIO_PB7 EQU (1 << 7) ;- Pin Controlled by PB7
+AT91C_PB7_ERXER EQU (AT91C_PIO_PB7) ;- Ethernet MAC Receive Error
+AT91C_PIO_PB8 EQU (1 << 8) ;- Pin Controlled by PB8
+AT91C_PB8_EMDC EQU (AT91C_PIO_PB8) ;- Ethernet MAC Management Data Clock
+AT91C_PIO_PB9 EQU (1 << 9) ;- Pin Controlled by PB9
+AT91C_PB9_EMDIO EQU (AT91C_PIO_PB9) ;- Ethernet MAC Management Data Input/Output
+
+// - *****************************************************************************
+// - PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
+// - *****************************************************************************
+AT91C_ID_FIQ EQU ( 0) ;- Advanced Interrupt Controller (FIQ)
+AT91C_ID_SYS EQU ( 1) ;- System Peripheral
+AT91C_ID_PIOA EQU ( 2) ;- Parallel IO Controller A
+AT91C_ID_PIOB EQU ( 3) ;- Parallel IO Controller B
+AT91C_ID_SPI0 EQU ( 4) ;- Serial Peripheral Interface 0
+AT91C_ID_SPI1 EQU ( 5) ;- Serial Peripheral Interface 1
+AT91C_ID_US0 EQU ( 6) ;- USART 0
+AT91C_ID_US1 EQU ( 7) ;- USART 1
+AT91C_ID_SSC EQU ( 8) ;- Serial Synchronous Controller
+AT91C_ID_TWI EQU ( 9) ;- Two-Wire Interface
+AT91C_ID_PWMC EQU (10) ;- PWM Controller
+AT91C_ID_UDP EQU (11) ;- USB Device Port
+AT91C_ID_TC0 EQU (12) ;- Timer Counter 0
+AT91C_ID_TC1 EQU (13) ;- Timer Counter 1
+AT91C_ID_TC2 EQU (14) ;- Timer Counter 2
+AT91C_ID_CAN EQU (15) ;- Control Area Network Controller
+AT91C_ID_EMAC EQU (16) ;- Ethernet MAC
+AT91C_ID_ADC EQU (17) ;- Analog-to-Digital Converter
+AT91C_ID_AES EQU (18) ;- Advanced Encryption Standard 128-bit
+AT91C_ID_TDES EQU (19) ;- Triple Data Encryption Standard
+AT91C_ID_20_Reserved EQU (20) ;- Reserved
+AT91C_ID_21_Reserved EQU (21) ;- Reserved
+AT91C_ID_22_Reserved EQU (22) ;- Reserved
+AT91C_ID_23_Reserved EQU (23) ;- Reserved
+AT91C_ID_24_Reserved EQU (24) ;- Reserved
+AT91C_ID_25_Reserved EQU (25) ;- Reserved
+AT91C_ID_26_Reserved EQU (26) ;- Reserved
+AT91C_ID_27_Reserved EQU (27) ;- Reserved
+AT91C_ID_28_Reserved EQU (28) ;- Reserved
+AT91C_ID_29_Reserved EQU (29) ;- Reserved
+AT91C_ID_IRQ0 EQU (30) ;- Advanced Interrupt Controller (IRQ0)
+AT91C_ID_IRQ1 EQU (31) ;- Advanced Interrupt Controller (IRQ1)
+
+// - *****************************************************************************
+// - BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
+// - *****************************************************************************
+AT91C_BASE_SYS EQU (0xFFFFF000) ;- (SYS) Base Address
+AT91C_BASE_AIC EQU (0xFFFFF000) ;- (AIC) Base Address
+AT91C_BASE_PDC_DBGU EQU (0xFFFFF300) ;- (PDC_DBGU) Base Address
+AT91C_BASE_DBGU EQU (0xFFFFF200) ;- (DBGU) Base Address
+AT91C_BASE_PIOA EQU (0xFFFFF400) ;- (PIOA) Base Address
+AT91C_BASE_PIOB EQU (0xFFFFF600) ;- (PIOB) Base Address
+AT91C_BASE_CKGR EQU (0xFFFFFC20) ;- (CKGR) Base Address
+AT91C_BASE_PMC EQU (0xFFFFFC00) ;- (PMC) Base Address
+AT91C_BASE_RSTC EQU (0xFFFFFD00) ;- (RSTC) Base Address
+AT91C_BASE_RTTC EQU (0xFFFFFD20) ;- (RTTC) Base Address
+AT91C_BASE_PITC EQU (0xFFFFFD30) ;- (PITC) Base Address
+AT91C_BASE_WDTC EQU (0xFFFFFD40) ;- (WDTC) Base Address
+AT91C_BASE_VREG EQU (0xFFFFFD60) ;- (VREG) Base Address
+AT91C_BASE_MC EQU (0xFFFFFF00) ;- (MC) Base Address
+AT91C_BASE_PDC_SPI1 EQU (0xFFFE4100) ;- (PDC_SPI1) Base Address
+AT91C_BASE_SPI1 EQU (0xFFFE4000) ;- (SPI1) Base Address
+AT91C_BASE_PDC_SPI0 EQU (0xFFFE0100) ;- (PDC_SPI0) Base Address
+AT91C_BASE_SPI0 EQU (0xFFFE0000) ;- (SPI0) Base Address
+AT91C_BASE_PDC_US1 EQU (0xFFFC4100) ;- (PDC_US1) Base Address
+AT91C_BASE_US1 EQU (0xFFFC4000) ;- (US1) Base Address
+AT91C_BASE_PDC_US0 EQU (0xFFFC0100) ;- (PDC_US0) Base Address
+AT91C_BASE_US0 EQU (0xFFFC0000) ;- (US0) Base Address
+AT91C_BASE_PDC_SSC EQU (0xFFFD4100) ;- (PDC_SSC) Base Address
+AT91C_BASE_SSC EQU (0xFFFD4000) ;- (SSC) Base Address
+AT91C_BASE_TWI EQU (0xFFFB8000) ;- (TWI) Base Address
+AT91C_BASE_PWMC_CH3 EQU (0xFFFCC260) ;- (PWMC_CH3) Base Address
+AT91C_BASE_PWMC_CH2 EQU (0xFFFCC240) ;- (PWMC_CH2) Base Address
+AT91C_BASE_PWMC_CH1 EQU (0xFFFCC220) ;- (PWMC_CH1) Base Address
+AT91C_BASE_PWMC_CH0 EQU (0xFFFCC200) ;- (PWMC_CH0) Base Address
+AT91C_BASE_PWMC EQU (0xFFFCC000) ;- (PWMC) Base Address
+AT91C_BASE_UDP EQU (0xFFFB0000) ;- (UDP) Base Address
+AT91C_BASE_TC0 EQU (0xFFFA0000) ;- (TC0) Base Address
+AT91C_BASE_TC1 EQU (0xFFFA0040) ;- (TC1) Base Address
+AT91C_BASE_TC2 EQU (0xFFFA0080) ;- (TC2) Base Address
+AT91C_BASE_TCB EQU (0xFFFA0000) ;- (TCB) Base Address
+AT91C_BASE_CAN_MB0 EQU (0xFFFD0200) ;- (CAN_MB0) Base Address
+AT91C_BASE_CAN_MB1 EQU (0xFFFD0220) ;- (CAN_MB1) Base Address
+AT91C_BASE_CAN_MB2 EQU (0xFFFD0240) ;- (CAN_MB2) Base Address
+AT91C_BASE_CAN_MB3 EQU (0xFFFD0260) ;- (CAN_MB3) Base Address
+AT91C_BASE_CAN_MB4 EQU (0xFFFD0280) ;- (CAN_MB4) Base Address
+AT91C_BASE_CAN_MB5 EQU (0xFFFD02A0) ;- (CAN_MB5) Base Address
+AT91C_BASE_CAN_MB6 EQU (0xFFFD02C0) ;- (CAN_MB6) Base Address
+AT91C_BASE_CAN_MB7 EQU (0xFFFD02E0) ;- (CAN_MB7) Base Address
+AT91C_BASE_CAN EQU (0xFFFD0000) ;- (CAN) Base Address
+AT91C_BASE_EMAC EQU (0xFFFDC000) ;- (EMAC) Base Address
+AT91C_BASE_PDC_ADC EQU (0xFFFD8100) ;- (PDC_ADC) Base Address
+AT91C_BASE_ADC EQU (0xFFFD8000) ;- (ADC) Base Address
+AT91C_BASE_PDC_AES EQU (0xFFFA4100) ;- (PDC_AES) Base Address
+AT91C_BASE_AES EQU (0xFFFA4000) ;- (AES) Base Address
+AT91C_BASE_PDC_TDES EQU (0xFFFA8100) ;- (PDC_TDES) Base Address
+AT91C_BASE_TDES EQU (0xFFFA8000) ;- (TDES) Base Address
+
+// - *****************************************************************************
+// - MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
+// - *****************************************************************************
+AT91C_ISRAM EQU (0x00200000) ;- Internal SRAM base address
+AT91C_ISRAM_SIZE EQU (0x00010000) ;- Internal SRAM size in byte (64 Kbyte)
+AT91C_IFLASH EQU (0x00100000) ;- Internal ROM base address
+AT91C_IFLASH_SIZE EQU (0x00040000) ;- Internal ROM size in byte (256 Kbyte)
+
+
+
+#endif /* AT91SAM7X256_H */
diff --git a/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c b/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c
index 9cbd823..240c733 100644
--- a/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c
+++ b/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c
@@ -1,51 +1,50 @@
-//* ----------------------------------------------------------------------------
-//* ATMEL Microcontroller Software Support - ROUSSET -
-//* ----------------------------------------------------------------------------
-//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//* ----------------------------------------------------------------------------
-//* File Name : lib_AT91SAM7X256.h
-//* Object : AT91SAM7X256 inlined functions
-//* Generated : AT91 SW Application Group 05/20/2005 (16:22:29)
-//*
-//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003//
-//* CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005//
-//* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005//
-//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004//
-//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//
-//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004//
-//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//
-//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003//
-//* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004//
-//* CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005//
-//* CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005//
-//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004//
-//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003//
-//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004//
-//* CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005//
-//* CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005//
-//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
-//* CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004//
-//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//
-//* CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003//
-//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
-//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002//
-//* ----------------------------------------------------------------------------
-
-
-#include "AT91SAM7X256.h"
-
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_AIC_ConfigureIt
-//* \brief Interrupt Handler Initialization
-//*----------------------------------------------------------------------------
-
+//* ----------------------------------------------------------------------------
+//* ATMEL Microcontroller Software Support - ROUSSET -
+//* ----------------------------------------------------------------------------
+//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//* ----------------------------------------------------------------------------
+//* File Name : lib_AT91SAM7X256.h
+//* Object : AT91SAM7X256 inlined functions
+//* Generated : AT91 SW Application Group 05/20/2005 (16:22:29)
+//*
+//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003//
+//* CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005//
+//* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005//
+//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004//
+//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//
+//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004//
+//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//
+//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003//
+//* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004//
+//* CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005//
+//* CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005//
+//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004//
+//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003//
+//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004//
+//* CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005//
+//* CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005//
+//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
+//* CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004//
+//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//
+//* CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003//
+//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
+//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002//
+//* ----------------------------------------------------------------------------
+
+
+#include "AT91SAM7X256.h"
+
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_ConfigureIt
+//* \brief Interrupt Handler Initialization
+//*----------------------------------------------------------------------------
diff --git a/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h b/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h
index e66b4e1..556e0ca 100644
--- a/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h
+++ b/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h
@@ -1,4558 +1,1469 @@
-//* ----------------------------------------------------------------------------
-//* ATMEL Microcontroller Software Support - ROUSSET -
-//* ----------------------------------------------------------------------------
-//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//* ----------------------------------------------------------------------------
-//* File Name : lib_AT91SAM7X256.h
-//* Object : AT91SAM7X256 inlined functions
-//* Generated : AT91 SW Application Group 05/20/2005 (16:22:29)
-//*
-//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003//
-//* CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005//
-//* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005//
-//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004//
-//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//
-//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004//
-//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//
-//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003//
-//* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004//
-//* CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005//
-//* CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005//
-//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004//
-//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003//
-//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004//
-//* CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005//
-//* CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005//
-//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
-//* CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004//
-//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//
-//* CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003//
-//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
-//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002//
-//* ----------------------------------------------------------------------------
-
-#ifndef lib_AT91SAM7X256_H
-#define lib_AT91SAM7X256_H
-
-/* *****************************************************************************
- SOFTWARE API FOR AIC
- ***************************************************************************** */
-#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20]
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_AIC_ConfigureIt
-//* \brief Interrupt Handler Initialization
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_AIC_ConfigureIt (
- AT91PS_AIC pAic, // \arg pointer to the AIC registers
- unsigned int irq_id, // \arg interrupt number to initialize
- unsigned int priority, // \arg priority to give to the interrupt
- unsigned int src_type, // \arg activation and sense of activation
- void (*newHandler) (void) ) // \arg address of the interrupt handler
-{
- unsigned int oldHandler;
- unsigned int mask ;
-
- oldHandler = pAic->AIC_SVR[irq_id];
-
- mask = 0x1 << irq_id ;
- //* Disable the interrupt on the interrupt controller
- pAic->AIC_IDCR = mask ;
- //* Save the interrupt handler routine pointer and the interrupt priority
- pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ;
- //* Store the Source Mode Register
- pAic->AIC_SMR[irq_id] = src_type | priority ;
- //* Clear the interrupt on the interrupt controller
- pAic->AIC_ICCR = mask ;
-
- return oldHandler;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_AIC_EnableIt
-//* \brief Enable corresponding IT number
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_EnableIt (
- AT91PS_AIC pAic, // \arg pointer to the AIC registers
- unsigned int irq_id ) // \arg interrupt number to initialize
-{
- //* Enable the interrupt on the interrupt controller
- pAic->AIC_IECR = 0x1 << irq_id ;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_AIC_DisableIt
-//* \brief Disable corresponding IT number
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_DisableIt (
- AT91PS_AIC pAic, // \arg pointer to the AIC registers
- unsigned int irq_id ) // \arg interrupt number to initialize
-{
- unsigned int mask = 0x1 << irq_id;
- //* Disable the interrupt on the interrupt controller
- pAic->AIC_IDCR = mask ;
- //* Clear the interrupt on the Interrupt Controller ( if one is pending )
- pAic->AIC_ICCR = mask ;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_AIC_ClearIt
-//* \brief Clear corresponding IT number
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_ClearIt (
- AT91PS_AIC pAic, // \arg pointer to the AIC registers
- unsigned int irq_id) // \arg interrupt number to initialize
-{
- //* Clear the interrupt on the Interrupt Controller ( if one is pending )
- pAic->AIC_ICCR = (0x1 << irq_id);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_AIC_AcknowledgeIt
-//* \brief Acknowledge corresponding IT number
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_AcknowledgeIt (
- AT91PS_AIC pAic) // \arg pointer to the AIC registers
-{
- pAic->AIC_EOICR = pAic->AIC_EOICR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_AIC_SetExceptionVector
-//* \brief Configure vector handler
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_AIC_SetExceptionVector (
- unsigned int *pVector, // \arg pointer to the AIC registers
- void (*Handler) () ) // \arg Interrupt Handler
-{
- unsigned int oldVector = *pVector;
-
- if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE)
- *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE;
- else
- *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000;
-
- return oldVector;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_AIC_Trig
-//* \brief Trig an IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_Trig (
- AT91PS_AIC pAic, // \arg pointer to the AIC registers
- unsigned int irq_id) // \arg interrupt number
-{
- pAic->AIC_ISCR = (0x1 << irq_id) ;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_AIC_IsActive
-//* \brief Test if an IT is active
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_AIC_IsActive (
- AT91PS_AIC pAic, // \arg pointer to the AIC registers
- unsigned int irq_id) // \arg Interrupt Number
-{
- return (pAic->AIC_ISR & (0x1 << irq_id));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_AIC_IsPending
-//* \brief Test if an IT is pending
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_AIC_IsPending (
- AT91PS_AIC pAic, // \arg pointer to the AIC registers
- unsigned int irq_id) // \arg Interrupt Number
-{
- return (pAic->AIC_IPR & (0x1 << irq_id));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_AIC_Open
-//* \brief Set exception vectors and AIC registers to default values
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_Open(
- AT91PS_AIC pAic, // \arg pointer to the AIC registers
- void (*IrqHandler) (), // \arg Default IRQ vector exception
- void (*FiqHandler) (), // \arg Default FIQ vector exception
- void (*DefaultHandler) (), // \arg Default Handler set in ISR
- void (*SpuriousHandler) (), // \arg Default Spurious Handler
- unsigned int protectMode) // \arg Debug Control Register
-{
- int i;
-
- // Disable all interrupts and set IVR to the default handler
- for (i = 0; i < 32; ++i) {
- AT91F_AIC_DisableIt(pAic, i);
- AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler);
- }
-
- // Set the IRQ exception vector
- AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler);
- // Set the Fast Interrupt exception vector
- AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler);
-
- pAic->AIC_SPU = (unsigned int) SpuriousHandler;
- pAic->AIC_DCR = protectMode;
-}
-/* *****************************************************************************
- SOFTWARE API FOR PDC
- ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PDC_SetNextRx
-//* \brief Set the next receive transfer descriptor
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_SetNextRx (
- AT91PS_PDC pPDC, // \arg pointer to a PDC controller
- char *address, // \arg address to the next bloc to be received
- unsigned int bytes) // \arg number of bytes to be received
-{
- pPDC->PDC_RNPR = (unsigned int) address;
- pPDC->PDC_RNCR = bytes;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PDC_SetNextTx
-//* \brief Set the next transmit transfer descriptor
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_SetNextTx (
- AT91PS_PDC pPDC, // \arg pointer to a PDC controller
- char *address, // \arg address to the next bloc to be transmitted
- unsigned int bytes) // \arg number of bytes to be transmitted
-{
- pPDC->PDC_TNPR = (unsigned int) address;
- pPDC->PDC_TNCR = bytes;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PDC_SetRx
-//* \brief Set the receive transfer descriptor
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_SetRx (
- AT91PS_PDC pPDC, // \arg pointer to a PDC controller
- char *address, // \arg address to the next bloc to be received
- unsigned int bytes) // \arg number of bytes to be received
-{
- pPDC->PDC_RPR = (unsigned int) address;
- pPDC->PDC_RCR = bytes;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PDC_SetTx
-//* \brief Set the transmit transfer descriptor
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_SetTx (
- AT91PS_PDC pPDC, // \arg pointer to a PDC controller
- char *address, // \arg address to the next bloc to be transmitted
- unsigned int bytes) // \arg number of bytes to be transmitted
-{
- pPDC->PDC_TPR = (unsigned int) address;
- pPDC->PDC_TCR = bytes;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PDC_EnableTx
-//* \brief Enable transmit
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_EnableTx (
- AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
-{
- pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PDC_EnableRx
-//* \brief Enable receive
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_EnableRx (
- AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
-{
- pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PDC_DisableTx
-//* \brief Disable transmit
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_DisableTx (
- AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
-{
- pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PDC_DisableRx
-//* \brief Disable receive
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_DisableRx (
- AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
-{
- pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PDC_IsTxEmpty
-//* \brief Test if the current transfer descriptor has been sent
-//*----------------------------------------------------------------------------
-__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete
- AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
-{
- return !(pPDC->PDC_TCR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PDC_IsNextTxEmpty
-//* \brief Test if the next transfer descriptor has been moved to the current td
-//*----------------------------------------------------------------------------
-__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete
- AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
-{
- return !(pPDC->PDC_TNCR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PDC_IsRxEmpty
-//* \brief Test if the current transfer descriptor has been filled
-//*----------------------------------------------------------------------------
-__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete
- AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
-{
- return !(pPDC->PDC_RCR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PDC_IsNextRxEmpty
-//* \brief Test if the next transfer descriptor has been moved to the current td
-//*----------------------------------------------------------------------------
-__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete
- AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
-{
- return !(pPDC->PDC_RNCR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PDC_Open
-//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_Open (
- AT91PS_PDC pPDC) // \arg pointer to a PDC controller
-{
- //* Disable the RX and TX PDC transfer requests
- AT91F_PDC_DisableRx(pPDC);
- AT91F_PDC_DisableTx(pPDC);
-
- //* Reset all Counter register Next buffer first
- AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
- AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
- AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
- AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
-
- //* Enable the RX and TX PDC transfer requests
- AT91F_PDC_EnableRx(pPDC);
- AT91F_PDC_EnableTx(pPDC);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PDC_Close
-//* \brief Close PDC: disable TX and RX reset transfer descriptors
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_Close (
- AT91PS_PDC pPDC) // \arg pointer to a PDC controller
-{
- //* Disable the RX and TX PDC transfer requests
- AT91F_PDC_DisableRx(pPDC);
- AT91F_PDC_DisableTx(pPDC);
-
- //* Reset all Counter register Next buffer first
- AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
- AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
- AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
- AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
-
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PDC_SendFrame
-//* \brief Close PDC: disable TX and RX reset transfer descriptors
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PDC_SendFrame(
- AT91PS_PDC pPDC,
- char *pBuffer,
- unsigned int szBuffer,
- char *pNextBuffer,
- unsigned int szNextBuffer )
-{
- if (AT91F_PDC_IsTxEmpty(pPDC)) {
- //* Buffer and next buffer can be initialized
- AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer);
- AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer);
- return 2;
- }
- else if (AT91F_PDC_IsNextTxEmpty(pPDC)) {
- //* Only one buffer can be initialized
- AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer);
- return 1;
- }
- else {
- //* All buffer are in use...
- return 0;
- }
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PDC_ReceiveFrame
-//* \brief Close PDC: disable TX and RX reset transfer descriptors
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PDC_ReceiveFrame (
- AT91PS_PDC pPDC,
- char *pBuffer,
- unsigned int szBuffer,
- char *pNextBuffer,
- unsigned int szNextBuffer )
-{
- if (AT91F_PDC_IsRxEmpty(pPDC)) {
- //* Buffer and next buffer can be initialized
- AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer);
- AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer);
- return 2;
- }
- else if (AT91F_PDC_IsNextRxEmpty(pPDC)) {
- //* Only one buffer can be initialized
- AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer);
- return 1;
- }
- else {
- //* All buffer are in use...
- return 0;
- }
-}
-/* *****************************************************************************
- SOFTWARE API FOR DBGU
- ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn AT91F_DBGU_InterruptEnable
-//* \brief Enable DBGU Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_DBGU_InterruptEnable(
- AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller
- unsigned int flag) // \arg dbgu interrupt to be enabled
-{
- pDbgu->DBGU_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_DBGU_InterruptDisable
-//* \brief Disable DBGU Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_DBGU_InterruptDisable(
- AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller
- unsigned int flag) // \arg dbgu interrupt to be disabled
-{
- pDbgu->DBGU_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_DBGU_GetInterruptMaskStatus
-//* \brief Return DBGU Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status
- AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller
-{
- return pDbgu->DBGU_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_DBGU_IsInterruptMasked
-//* \brief Test if DBGU Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline int AT91F_DBGU_IsInterruptMasked(
- AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller
- unsigned int flag) // \arg flag to be tested
-{
- return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag);
-}
-
-/* *****************************************************************************
- SOFTWARE API FOR PIO
- ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_CfgPeriph
-//* \brief Enable pins to be drived by peripheral
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgPeriph(
- AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int periphAEnable, // \arg PERIPH A to enable
- unsigned int periphBEnable) // \arg PERIPH B to enable
-
-{
- pPio->PIO_ASR = periphAEnable;
- pPio->PIO_BSR = periphBEnable;
- pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_CfgOutput
-//* \brief Enable PIO in output mode
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgOutput(
- AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int pioEnable) // \arg PIO to be enabled
-{
- pPio->PIO_PER = pioEnable; // Set in PIO mode
- pPio->PIO_OER = pioEnable; // Configure in Output
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_CfgInput
-//* \brief Enable PIO in input mode
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgInput(
- AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int inputEnable) // \arg PIO to be enabled
-{
- // Disable output
- pPio->PIO_ODR = inputEnable;
- pPio->PIO_PER = inputEnable;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_CfgOpendrain
-//* \brief Configure PIO in open drain
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgOpendrain(
- AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int multiDrvEnable) // \arg pio to be configured in open drain
-{
- // Configure the multi-drive option
- pPio->PIO_MDDR = ~multiDrvEnable;
- pPio->PIO_MDER = multiDrvEnable;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_CfgPullup
-//* \brief Enable pullup on PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgPullup(
- AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int pullupEnable) // \arg enable pullup on PIO
-{
- // Connect or not Pullup
- pPio->PIO_PPUDR = ~pullupEnable;
- pPio->PIO_PPUER = pullupEnable;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_CfgDirectDrive
-//* \brief Enable direct drive on PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgDirectDrive(
- AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int directDrive) // \arg PIO to be configured with direct drive
-
-{
- // Configure the Direct Drive
- pPio->PIO_OWDR = ~directDrive;
- pPio->PIO_OWER = directDrive;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_CfgInputFilter
-//* \brief Enable input filter on input PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgInputFilter(
- AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int inputFilter) // \arg PIO to be configured with input filter
-
-{
- // Configure the Direct Drive
- pPio->PIO_IFDR = ~inputFilter;
- pPio->PIO_IFER = inputFilter;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_GetInput
-//* \brief Return PIO input value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetInput( // \return PIO input
- AT91PS_PIO pPio) // \arg pointer to a PIO controller
-{
- return pPio->PIO_PDSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_IsInputSet
-//* \brief Test if PIO is input flag is active
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsInputSet(
- AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag) // \arg flag to be tested
-{
- return (AT91F_PIO_GetInput(pPio) & flag);
-}
-
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_SetOutput
-//* \brief Set to 1 output PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_SetOutput(
- AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag) // \arg output to be set
-{
- pPio->PIO_SODR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_ClearOutput
-//* \brief Set to 0 output PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_ClearOutput(
- AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag) // \arg output to be cleared
-{
- pPio->PIO_CODR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_ForceOutput
-//* \brief Force output when Direct drive option is enabled
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_ForceOutput(
- AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag) // \arg output to be forced
-{
- pPio->PIO_ODSR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_Enable
-//* \brief Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_Enable(
- AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag) // \arg pio to be enabled
-{
- pPio->PIO_PER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_Disable
-//* \brief Disable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_Disable(
- AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag) // \arg pio to be disabled
-{
- pPio->PIO_PDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_GetStatus
-//* \brief Return PIO Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status
- AT91PS_PIO pPio) // \arg pointer to a PIO controller
-{
- return pPio->PIO_PSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_IsSet
-//* \brief Test if PIO is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsSet(
- AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag) // \arg flag to be tested
-{
- return (AT91F_PIO_GetStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_OutputEnable
-//* \brief Output Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_OutputEnable(
- AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag) // \arg pio output to be enabled
-{
- pPio->PIO_OER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_OutputDisable
-//* \brief Output Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_OutputDisable(
- AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag) // \arg pio output to be disabled
-{
- pPio->PIO_ODR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_GetOutputStatus
-//* \brief Return PIO Output Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status
- AT91PS_PIO pPio) // \arg pointer to a PIO controller
-{
- return pPio->PIO_OSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_IsOuputSet
-//* \brief Test if PIO Output is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsOutputSet(
- AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag) // \arg flag to be tested
-{
- return (AT91F_PIO_GetOutputStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_InputFilterEnable
-//* \brief Input Filter Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_InputFilterEnable(
- AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag) // \arg pio input filter to be enabled
-{
- pPio->PIO_IFER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_InputFilterDisable
-//* \brief Input Filter Disable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_InputFilterDisable(
- AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag) // \arg pio input filter to be disabled
-{
- pPio->PIO_IFDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_GetInputFilterStatus
-//* \brief Return PIO Input Filter Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status
- AT91PS_PIO pPio) // \arg pointer to a PIO controller
-{
- return pPio->PIO_IFSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_IsInputFilterSet
-//* \brief Test if PIO Input filter is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsInputFilterSet(
- AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag) // \arg flag to be tested
-{
- return (AT91F_PIO_GetInputFilterStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_GetOutputDataStatus
-//* \brief Return PIO Output Data Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status
- AT91PS_PIO pPio) // \arg pointer to a PIO controller
-{
- return pPio->PIO_ODSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_InterruptEnable
-//* \brief Enable PIO Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_InterruptEnable(
- AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag) // \arg pio interrupt to be enabled
-{
- pPio->PIO_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_InterruptDisable
-//* \brief Disable PIO Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_InterruptDisable(
- AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag) // \arg pio interrupt to be disabled
-{
- pPio->PIO_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_GetInterruptMaskStatus
-//* \brief Return PIO Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status
- AT91PS_PIO pPio) // \arg pointer to a PIO controller
-{
- return pPio->PIO_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_GetInterruptStatus
-//* \brief Return PIO Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status
- AT91PS_PIO pPio) // \arg pointer to a PIO controller
-{
- return pPio->PIO_ISR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_IsInterruptMasked
-//* \brief Test if PIO Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsInterruptMasked(
- AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag) // \arg flag to be tested
-{
- return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_IsInterruptSet
-//* \brief Test if PIO Interrupt is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsInterruptSet(
- AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag) // \arg flag to be tested
-{
- return (AT91F_PIO_GetInterruptStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_MultiDriverEnable
-//* \brief Multi Driver Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_MultiDriverEnable(
- AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag) // \arg pio to be enabled
-{
- pPio->PIO_MDER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_MultiDriverDisable
-//* \brief Multi Driver Disable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_MultiDriverDisable(
- AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag) // \arg pio to be disabled
-{
- pPio->PIO_MDDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_GetMultiDriverStatus
-//* \brief Return PIO Multi Driver Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status
- AT91PS_PIO pPio) // \arg pointer to a PIO controller
-{
- return pPio->PIO_MDSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_IsMultiDriverSet
-//* \brief Test if PIO MultiDriver is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsMultiDriverSet(
- AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag) // \arg flag to be tested
-{
- return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_A_RegisterSelection
-//* \brief PIO A Register Selection
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_A_RegisterSelection(
- AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag) // \arg pio A register selection
-{
- pPio->PIO_ASR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_B_RegisterSelection
-//* \brief PIO B Register Selection
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_B_RegisterSelection(
- AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag) // \arg pio B register selection
-{
- pPio->PIO_BSR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_Get_AB_RegisterStatus
-//* \brief Return PIO Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status
- AT91PS_PIO pPio) // \arg pointer to a PIO controller
-{
- return pPio->PIO_ABSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_IsAB_RegisterSet
-//* \brief Test if PIO AB Register is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsAB_RegisterSet(
- AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag) // \arg flag to be tested
-{
- return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_OutputWriteEnable
-//* \brief Output Write Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_OutputWriteEnable(
- AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag) // \arg pio output write to be enabled
-{
- pPio->PIO_OWER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_OutputWriteDisable
-//* \brief Output Write Disable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_OutputWriteDisable(
- AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag) // \arg pio output write to be disabled
-{
- pPio->PIO_OWDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_GetOutputWriteStatus
-//* \brief Return PIO Output Write Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status
- AT91PS_PIO pPio) // \arg pointer to a PIO controller
-{
- return pPio->PIO_OWSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_IsOutputWriteSet
-//* \brief Test if PIO OutputWrite is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsOutputWriteSet(
- AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag) // \arg flag to be tested
-{
- return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_GetCfgPullup
-//* \brief Return PIO Configuration Pullup
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup
- AT91PS_PIO pPio) // \arg pointer to a PIO controller
-{
- return pPio->PIO_PPUSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_IsOutputDataStatusSet
-//* \brief Test if PIO Output Data Status is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsOutputDataStatusSet(
- AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag) // \arg flag to be tested
-{
- return (AT91F_PIO_GetOutputDataStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_IsCfgPullupStatusSet
-//* \brief Test if PIO Configuration Pullup Status is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsCfgPullupStatusSet(
- AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag) // \arg flag to be tested
-{
- return (~AT91F_PIO_GetCfgPullup(pPio) & flag);
-}
-
-/* *****************************************************************************
- SOFTWARE API FOR PMC
- ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PMC_CfgSysClkEnableReg
-//* \brief Configure the System Clock Enable Register of the PMC controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_CfgSysClkEnableReg (
- AT91PS_PMC pPMC, // \arg pointer to PMC controller
- unsigned int mode)
-{
- //* Write to the SCER register
- pPMC->PMC_SCER = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PMC_CfgSysClkDisableReg
-//* \brief Configure the System Clock Disable Register of the PMC controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_CfgSysClkDisableReg (
- AT91PS_PMC pPMC, // \arg pointer to PMC controller
- unsigned int mode)
-{
- //* Write to the SCDR register
- pPMC->PMC_SCDR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PMC_GetSysClkStatusReg
-//* \brief Return the System Clock Status Register of the PMC controller
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetSysClkStatusReg (
- AT91PS_PMC pPMC // pointer to a CAN controller
- )
-{
- return pPMC->PMC_SCSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PMC_EnablePeriphClock
-//* \brief Enable peripheral clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_EnablePeriphClock (
- AT91PS_PMC pPMC, // \arg pointer to PMC controller
- unsigned int periphIds) // \arg IDs of peripherals to enable
-{
- pPMC->PMC_PCER = periphIds;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PMC_DisablePeriphClock
-//* \brief Disable peripheral clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_DisablePeriphClock (
- AT91PS_PMC pPMC, // \arg pointer to PMC controller
- unsigned int periphIds) // \arg IDs of peripherals to enable
-{
- pPMC->PMC_PCDR = periphIds;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PMC_GetPeriphClock
-//* \brief Get peripheral clock status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetPeriphClock (
- AT91PS_PMC pPMC) // \arg pointer to PMC controller
-{
- return pPMC->PMC_PCSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CKGR_CfgMainOscillatorReg
-//* \brief Cfg the main oscillator
-//*----------------------------------------------------------------------------
-__inline void AT91F_CKGR_CfgMainOscillatorReg (
- AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
- unsigned int mode)
-{
- pCKGR->CKGR_MOR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CKGR_GetMainOscillatorReg
-//* \brief Cfg the main oscillator
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CKGR_GetMainOscillatorReg (
- AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
-{
- return pCKGR->CKGR_MOR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CKGR_EnableMainOscillator
-//* \brief Enable the main oscillator
-//*----------------------------------------------------------------------------
-__inline void AT91F_CKGR_EnableMainOscillator(
- AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
-{
- pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CKGR_DisableMainOscillator
-//* \brief Disable the main oscillator
-//*----------------------------------------------------------------------------
-__inline void AT91F_CKGR_DisableMainOscillator (
- AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
-{
- pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CKGR_CfgMainOscStartUpTime
-//* \brief Cfg MOR Register according to the main osc startup time
-//*----------------------------------------------------------------------------
-__inline void AT91F_CKGR_CfgMainOscStartUpTime (
- AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
- unsigned int startup_time, // \arg main osc startup time in microsecond (us)
- unsigned int slowClock) // \arg slowClock in Hz
-{
- pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT;
- pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CKGR_GetMainClockFreqReg
-//* \brief Cfg the main oscillator
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CKGR_GetMainClockFreqReg (
- AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
-{
- return pCKGR->CKGR_MCFR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CKGR_GetMainClock
-//* \brief Return Main clock in Hz
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CKGR_GetMainClock (
- AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
- unsigned int slowClock) // \arg slowClock in Hz
-{
- return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PMC_CfgMCKReg
-//* \brief Cfg Master Clock Register
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_CfgMCKReg (
- AT91PS_PMC pPMC, // \arg pointer to PMC controller
- unsigned int mode)
-{
- pPMC->PMC_MCKR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PMC_GetMCKReg
-//* \brief Return Master Clock Register
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetMCKReg(
- AT91PS_PMC pPMC) // \arg pointer to PMC controller
-{
- return pPMC->PMC_MCKR;
-}
-
-//*------------------------------------------------------------------------------
-//* \fn AT91F_PMC_GetMasterClock
-//* \brief Return master clock in Hz which correponds to processor clock for ARM7
-//*------------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetMasterClock (
- AT91PS_PMC pPMC, // \arg pointer to PMC controller
- AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
- unsigned int slowClock) // \arg slowClock in Hz
-{
- unsigned int reg = pPMC->PMC_MCKR;
- unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2));
- unsigned int pllDivider, pllMultiplier;
-
- switch (reg & AT91C_PMC_CSS) {
- case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected
- return slowClock / prescaler;
- case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected
- return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler;
- case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected
- reg = pCKGR->CKGR_PLLR;
- pllDivider = (reg & AT91C_CKGR_DIV);
- pllMultiplier = ((reg & AT91C_CKGR_MUL) >> 16) + 1;
- return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler;
- }
- return 0;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PMC_EnablePCK
-//* \brief Enable peripheral clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_EnablePCK (
- AT91PS_PMC pPMC, // \arg pointer to PMC controller
- unsigned int pck, // \arg Peripheral clock identifier 0 .. 7
- unsigned int mode)
-{
- pPMC->PMC_PCKR[pck] = mode;
- pPMC->PMC_SCER = (1 << pck) << 8;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PMC_DisablePCK
-//* \brief Enable peripheral clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_DisablePCK (
- AT91PS_PMC pPMC, // \arg pointer to PMC controller
- unsigned int pck) // \arg Peripheral clock identifier 0 .. 7
-{
- pPMC->PMC_SCDR = (1 << pck) << 8;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PMC_EnableIt
-//* \brief Enable PMC interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_EnableIt (
- AT91PS_PMC pPMC, // pointer to a PMC controller
- unsigned int flag) // IT to be enabled
-{
- //* Write to the IER register
- pPMC->PMC_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PMC_DisableIt
-//* \brief Disable PMC interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_DisableIt (
- AT91PS_PMC pPMC, // pointer to a PMC controller
- unsigned int flag) // IT to be disabled
-{
- //* Write to the IDR register
- pPMC->PMC_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PMC_GetStatus
-//* \brief Return PMC Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status
- AT91PS_PMC pPMC) // pointer to a PMC controller
-{
- return pPMC->PMC_SR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PMC_GetInterruptMaskStatus
-//* \brief Return PMC Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status
- AT91PS_PMC pPMC) // pointer to a PMC controller
-{
- return pPMC->PMC_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PMC_IsInterruptMasked
-//* \brief Test if PMC Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_IsInterruptMasked(
- AT91PS_PMC pPMC, // \arg pointer to a PMC controller
- unsigned int flag) // \arg flag to be tested
-{
- return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PMC_IsStatusSet
-//* \brief Test if PMC Status is Set
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_IsStatusSet(
- AT91PS_PMC pPMC, // \arg pointer to a PMC controller
- unsigned int flag) // \arg flag to be tested
-{
- return (AT91F_PMC_GetStatus(pPMC) & flag);
-}/* *****************************************************************************
- SOFTWARE API FOR RSTC
- ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn AT91F_RSTSoftReset
-//* \brief Start Software Reset
-//*----------------------------------------------------------------------------
-__inline void AT91F_RSTSoftReset(
- AT91PS_RSTC pRSTC,
- unsigned int reset)
-{
- pRSTC->RSTC_RCR = (0xA5000000 | reset);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_RSTSetMode
-//* \brief Set Reset Mode
-//*----------------------------------------------------------------------------
-__inline void AT91F_RSTSetMode(
- AT91PS_RSTC pRSTC,
- unsigned int mode)
-{
- pRSTC->RSTC_RMR = (0xA5000000 | mode);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_RSTGetMode
-//* \brief Get Reset Mode
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_RSTGetMode(
- AT91PS_RSTC pRSTC)
-{
- return (pRSTC->RSTC_RMR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_RSTGetStatus
-//* \brief Get Reset Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_RSTGetStatus(
- AT91PS_RSTC pRSTC)
-{
- return (pRSTC->RSTC_RSR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_RSTIsSoftRstActive
-//* \brief Return !=0 if software reset is still not completed
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_RSTIsSoftRstActive(
- AT91PS_RSTC pRSTC)
-{
- return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP);
-}
-/* *****************************************************************************
- SOFTWARE API FOR RTTC
- ***************************************************************************** */
-//*--------------------------------------------------------------------------------------
-//* \fn AT91F_SetRTT_TimeBase()
-//* \brief Set the RTT prescaler according to the TimeBase in ms
-//*--------------------------------------------------------------------------------------
-__inline unsigned int AT91F_RTTSetTimeBase(
- AT91PS_RTTC pRTTC,
- unsigned int ms)
-{
- if (ms > 2000)
- return 1; // AT91C_TIME_OUT_OF_RANGE
- pRTTC->RTTC_RTMR &= ~0xFFFF;
- pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF);
- return 0;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn AT91F_RTTSetPrescaler()
-//* \brief Set the new prescaler value
-//*--------------------------------------------------------------------------------------
-__inline unsigned int AT91F_RTTSetPrescaler(
- AT91PS_RTTC pRTTC,
- unsigned int rtpres)
-{
- pRTTC->RTTC_RTMR &= ~0xFFFF;
- pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF);
- return (pRTTC->RTTC_RTMR);
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn AT91F_RTTRestart()
-//* \brief Restart the RTT prescaler
-//*--------------------------------------------------------------------------------------
-__inline void AT91F_RTTRestart(
- AT91PS_RTTC pRTTC)
-{
- pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST;
-}
-
-
-//*--------------------------------------------------------------------------------------
-//* \fn AT91F_RTT_SetAlarmINT()
-//* \brief Enable RTT Alarm Interrupt
-//*--------------------------------------------------------------------------------------
-__inline void AT91F_RTTSetAlarmINT(
- AT91PS_RTTC pRTTC)
-{
- pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn AT91F_RTT_ClearAlarmINT()
-//* \brief Disable RTT Alarm Interrupt
-//*--------------------------------------------------------------------------------------
-__inline void AT91F_RTTClearAlarmINT(
- AT91PS_RTTC pRTTC)
-{
- pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn AT91F_RTT_SetRttIncINT()
-//* \brief Enable RTT INC Interrupt
-//*--------------------------------------------------------------------------------------
-__inline void AT91F_RTTSetRttIncINT(
- AT91PS_RTTC pRTTC)
-{
- pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn AT91F_RTT_ClearRttIncINT()
-//* \brief Disable RTT INC Interrupt
-//*--------------------------------------------------------------------------------------
-__inline void AT91F_RTTClearRttIncINT(
- AT91PS_RTTC pRTTC)
-{
- pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn AT91F_RTT_SetAlarmValue()
-//* \brief Set RTT Alarm Value
-//*--------------------------------------------------------------------------------------
-__inline void AT91F_RTTSetAlarmValue(
- AT91PS_RTTC pRTTC, unsigned int alarm)
-{
- pRTTC->RTTC_RTAR = alarm;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn AT91F_RTT_GetAlarmValue()
-//* \brief Get RTT Alarm Value
-//*--------------------------------------------------------------------------------------
-__inline unsigned int AT91F_RTTGetAlarmValue(
- AT91PS_RTTC pRTTC)
-{
- return(pRTTC->RTTC_RTAR);
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn AT91F_RTTGetStatus()
-//* \brief Read the RTT status
-//*--------------------------------------------------------------------------------------
-__inline unsigned int AT91F_RTTGetStatus(
- AT91PS_RTTC pRTTC)
-{
- return(pRTTC->RTTC_RTSR);
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn AT91F_RTT_ReadValue()
-//* \brief Read the RTT value
-//*--------------------------------------------------------------------------------------
-__inline unsigned int AT91F_RTTReadValue(
- AT91PS_RTTC pRTTC)
-{
- register volatile unsigned int val1,val2;
- do
- {
- val1 = pRTTC->RTTC_RTVR;
- val2 = pRTTC->RTTC_RTVR;
- }
- while(val1 != val2);
- return(val1);
-}
-/* *****************************************************************************
- SOFTWARE API FOR PITC
- ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PITInit
-//* \brief System timer init : period in µsecond, system clock freq in MHz
-//*----------------------------------------------------------------------------
-__inline void AT91F_PITInit(
- AT91PS_PITC pPITC,
- unsigned int period,
- unsigned int pit_frequency)
-{
- pPITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10
- pPITC->PITC_PIMR |= AT91C_PITC_PITEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PITSetPIV
-//* \brief Set the PIT Periodic Interval Value
-//*----------------------------------------------------------------------------
-__inline void AT91F_PITSetPIV(
- AT91PS_PITC pPITC,
- unsigned int piv)
-{
- pPITC->PITC_PIMR = piv | (pPITC->PITC_PIMR & (AT91C_PITC_PITEN | AT91C_PITC_PITIEN));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PITEnableInt
-//* \brief Enable PIT periodic interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PITEnableInt(
- AT91PS_PITC pPITC)
-{
- pPITC->PITC_PIMR |= AT91C_PITC_PITIEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PITDisableInt
-//* \brief Disable PIT periodic interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PITDisableInt(
- AT91PS_PITC pPITC)
-{
- pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PITGetMode
-//* \brief Read PIT mode register
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PITGetMode(
- AT91PS_PITC pPITC)
-{
- return(pPITC->PITC_PIMR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PITGetStatus
-//* \brief Read PIT status register
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PITGetStatus(
- AT91PS_PITC pPITC)
-{
- return(pPITC->PITC_PISR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PITGetPIIR
-//* \brief Read PIT CPIV and PICNT without ressetting the counters
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PITGetPIIR(
- AT91PS_PITC pPITC)
-{
- return(pPITC->PITC_PIIR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PITGetPIVR
-//* \brief Read System timer CPIV and PICNT without ressetting the counters
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PITGetPIVR(
- AT91PS_PITC pPITC)
-{
- return(pPITC->PITC_PIVR);
-}
-/* *****************************************************************************
- SOFTWARE API FOR WDTC
- ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn AT91F_WDTSetMode
-//* \brief Set Watchdog Mode Register
-//*----------------------------------------------------------------------------
-__inline void AT91F_WDTSetMode(
- AT91PS_WDTC pWDTC,
- unsigned int Mode)
-{
- pWDTC->WDTC_WDMR = Mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_WDTRestart
-//* \brief Restart Watchdog
-//*----------------------------------------------------------------------------
-__inline void AT91F_WDTRestart(
- AT91PS_WDTC pWDTC)
-{
- pWDTC->WDTC_WDCR = 0xA5000001;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_WDTSGettatus
-//* \brief Get Watchdog Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_WDTSGettatus(
- AT91PS_WDTC pWDTC)
-{
- return(pWDTC->WDTC_WDSR & 0x3);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_WDTGetPeriod
-//* \brief Translate ms into Watchdog Compatible value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_WDTGetPeriod(unsigned int ms)
-{
- if ((ms < 4) || (ms > 16000))
- return 0;
- return((ms << 8) / 1000);
-}
-/* *****************************************************************************
- SOFTWARE API FOR VREG
- ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn AT91F_VREG_Enable_LowPowerMode
-//* \brief Enable VREG Low Power Mode
-//*----------------------------------------------------------------------------
-__inline void AT91F_VREG_Enable_LowPowerMode(
- AT91PS_VREG pVREG)
-{
- pVREG->VREG_MR |= AT91C_VREG_PSTDBY;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_VREG_Disable_LowPowerMode
-//* \brief Disable VREG Low Power Mode
-//*----------------------------------------------------------------------------
-__inline void AT91F_VREG_Disable_LowPowerMode(
- AT91PS_VREG pVREG)
-{
- pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY;
-}/* *****************************************************************************
- SOFTWARE API FOR MC
- ***************************************************************************** */
-
-#define AT91C_MC_CORRECT_KEY ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_MC_Remap
-//* \brief Make Remap
-//*----------------------------------------------------------------------------
-__inline void AT91F_MC_Remap (void) //
-{
- AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC;
-
- pMC->MC_RCR = AT91C_MC_RCB;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_MC_EFC_CfgModeReg
-//* \brief Configure the EFC Mode Register of the MC controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_MC_EFC_CfgModeReg (
- AT91PS_MC pMC, // pointer to a MC controller
- unsigned int mode) // mode register
-{
- // Write to the FMR register
- pMC->MC_FMR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_MC_EFC_GetModeReg
-//* \brief Return MC EFC Mode Regsiter
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_MC_EFC_GetModeReg(
- AT91PS_MC pMC) // pointer to a MC controller
-{
- return pMC->MC_FMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_MC_EFC_ComputeFMCN
-//* \brief Return MC EFC Mode Regsiter
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_MC_EFC_ComputeFMCN(
- int master_clock) // master clock in Hz
-{
- return (master_clock/1000000 +2);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_MC_EFC_PerformCmd
-//* \brief Perform EFC Command
-//*----------------------------------------------------------------------------
-__inline void AT91F_MC_EFC_PerformCmd (
- AT91PS_MC pMC, // pointer to a MC controller
- unsigned int transfer_cmd)
-{
- pMC->MC_FCR = transfer_cmd;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_MC_EFC_GetStatus
-//* \brief Return MC EFC Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_MC_EFC_GetStatus(
- AT91PS_MC pMC) // pointer to a MC controller
-{
- return pMC->MC_FSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_MC_EFC_IsInterruptMasked
-//* \brief Test if EFC MC Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_MC_EFC_IsInterruptMasked(
- AT91PS_MC pMC, // \arg pointer to a MC controller
- unsigned int flag) // \arg flag to be tested
-{
- return (AT91F_MC_EFC_GetModeReg(pMC) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_MC_EFC_IsInterruptSet
-//* \brief Test if EFC MC Interrupt is Set
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_MC_EFC_IsInterruptSet(
- AT91PS_MC pMC, // \arg pointer to a MC controller
- unsigned int flag) // \arg flag to be tested
-{
- return (AT91F_MC_EFC_GetStatus(pMC) & flag);
-}
-
-/* *****************************************************************************
- SOFTWARE API FOR SPI
- ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SPI_Open
-//* \brief Open a SPI Port
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_SPI_Open (
- const unsigned int null) // \arg
-{
- /* NOT DEFINED AT THIS MOMENT */
- return ( 0 );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SPI_CfgCs
-//* \brief Configure SPI chip select register
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_CfgCs (
- AT91PS_SPI pSPI, // pointer to a SPI controller
- int cs, // SPI cs number (0 to 3)
- int val) // chip select register
-{
- //* Write to the CSR register
- *(pSPI->SPI_CSR + cs) = val;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SPI_EnableIt
-//* \brief Enable SPI interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_EnableIt (
- AT91PS_SPI pSPI, // pointer to a SPI controller
- unsigned int flag) // IT to be enabled
-{
- //* Write to the IER register
- pSPI->SPI_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SPI_DisableIt
-//* \brief Disable SPI interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_DisableIt (
- AT91PS_SPI pSPI, // pointer to a SPI controller
- unsigned int flag) // IT to be disabled
-{
- //* Write to the IDR register
- pSPI->SPI_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SPI_Reset
-//* \brief Reset the SPI controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_Reset (
- AT91PS_SPI pSPI // pointer to a SPI controller
- )
-{
- //* Write to the CR register
- pSPI->SPI_CR = AT91C_SPI_SWRST;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SPI_Enable
-//* \brief Enable the SPI controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_Enable (
- AT91PS_SPI pSPI // pointer to a SPI controller
- )
-{
- //* Write to the CR register
- pSPI->SPI_CR = AT91C_SPI_SPIEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SPI_Disable
-//* \brief Disable the SPI controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_Disable (
- AT91PS_SPI pSPI // pointer to a SPI controller
- )
-{
- //* Write to the CR register
- pSPI->SPI_CR = AT91C_SPI_SPIDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SPI_CfgMode
-//* \brief Enable the SPI controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_CfgMode (
- AT91PS_SPI pSPI, // pointer to a SPI controller
- int mode) // mode register
-{
- //* Write to the MR register
- pSPI->SPI_MR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SPI_CfgPCS
-//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_CfgPCS (
- AT91PS_SPI pSPI, // pointer to a SPI controller
- char PCS_Device) // PCS of the Device
-{
- //* Write to the MR register
- pSPI->SPI_MR &= 0xFFF0FFFF;
- pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SPI_ReceiveFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_SPI_ReceiveFrame (
- AT91PS_SPI pSPI,
- char *pBuffer,
- unsigned int szBuffer,
- char *pNextBuffer,
- unsigned int szNextBuffer )
-{
- return AT91F_PDC_ReceiveFrame(
- (AT91PS_PDC) &(pSPI->SPI_RPR),
- pBuffer,
- szBuffer,
- pNextBuffer,
- szNextBuffer);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SPI_SendFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_SPI_SendFrame(
- AT91PS_SPI pSPI,
- char *pBuffer,
- unsigned int szBuffer,
- char *pNextBuffer,
- unsigned int szNextBuffer )
-{
- return AT91F_PDC_SendFrame(
- (AT91PS_PDC) &(pSPI->SPI_RPR),
- pBuffer,
- szBuffer,
- pNextBuffer,
- szNextBuffer);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SPI_Close
-//* \brief Close SPI: disable IT disable transfert, close PDC
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_Close (
- AT91PS_SPI pSPI) // \arg pointer to a SPI controller
-{
- //* Reset all the Chip Select register
- pSPI->SPI_CSR[0] = 0 ;
- pSPI->SPI_CSR[1] = 0 ;
- pSPI->SPI_CSR[2] = 0 ;
- pSPI->SPI_CSR[3] = 0 ;
-
- //* Reset the SPI mode
- pSPI->SPI_MR = 0 ;
-
- //* Disable all interrupts
- pSPI->SPI_IDR = 0xFFFFFFFF ;
-
- //* Abort the Peripheral Data Transfers
- AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR));
-
- //* Disable receiver and transmitter and stop any activity immediately
- pSPI->SPI_CR = AT91C_SPI_SPIDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SPI_PutChar
-//* \brief Send a character,does not check if ready to send
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_PutChar (
- AT91PS_SPI pSPI,
- unsigned int character,
- unsigned int cs_number )
-{
- unsigned int value_for_cs;
- value_for_cs = (~(1 << cs_number)) & 0xF; //Place a zero among a 4 ONEs number
- pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SPI_GetChar
-//* \brief Receive a character,does not check if a character is available
-//*----------------------------------------------------------------------------
-__inline int AT91F_SPI_GetChar (
- const AT91PS_SPI pSPI)
-{
- return((pSPI->SPI_RDR) & 0xFFFF);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SPI_GetInterruptMaskStatus
-//* \brief Return SPI Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status
- AT91PS_SPI pSpi) // \arg pointer to a SPI controller
-{
- return pSpi->SPI_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SPI_IsInterruptMasked
-//* \brief Test if SPI Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline int AT91F_SPI_IsInterruptMasked(
- AT91PS_SPI pSpi, // \arg pointer to a SPI controller
- unsigned int flag) // \arg flag to be tested
-{
- return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag);
-}
-
-/* *****************************************************************************
- SOFTWARE API FOR USART
- ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US_Baudrate
-//* \brief Calculate the baudrate
-//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity
-#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \
- AT91C_US_NBSTOP_1_BIT + \
- AT91C_US_PAR_NONE + \
- AT91C_US_CHRL_8_BITS + \
- AT91C_US_CLKS_CLOCK )
-
-//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity
-#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \
- AT91C_US_NBSTOP_1_BIT + \
- AT91C_US_PAR_NONE + \
- AT91C_US_CHRL_8_BITS + \
- AT91C_US_CLKS_EXT )
-
-//* Standard Synchronous Mode : 8 bits , 1 stop , no parity
-#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \
- AT91C_US_USMODE_NORMAL + \
- AT91C_US_NBSTOP_1_BIT + \
- AT91C_US_PAR_NONE + \
- AT91C_US_CHRL_8_BITS + \
- AT91C_US_CLKS_CLOCK )
-
-//* SCK used Label
-#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT)
-
-//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity
-#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \
- AT91C_US_CLKS_CLOCK +\
- AT91C_US_NBSTOP_1_BIT + \
- AT91C_US_PAR_EVEN + \
- AT91C_US_CHRL_8_BITS + \
- AT91C_US_CKLO +\
- AT91C_US_OVER)
-
-//* Standard IRDA mode
-#define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \
- AT91C_US_NBSTOP_1_BIT + \
- AT91C_US_PAR_NONE + \
- AT91C_US_CHRL_8_BITS + \
- AT91C_US_CLKS_CLOCK )
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US_Baudrate
-//* \brief Caluculate baud_value according to the main clock and the baud rate
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_US_Baudrate (
- const unsigned int main_clock, // \arg peripheral clock
- const unsigned int baud_rate) // \arg UART baudrate
-{
- unsigned int baud_value = ((main_clock*10)/(baud_rate * 16));
- if ((baud_value % 10) >= 5)
- baud_value = (baud_value / 10) + 1;
- else
- baud_value /= 10;
- return baud_value;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US_SetBaudrate
-//* \brief Set the baudrate according to the CPU clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_SetBaudrate (
- AT91PS_USART pUSART, // \arg pointer to a USART controller
- unsigned int mainClock, // \arg peripheral clock
- unsigned int speed) // \arg UART baudrate
-{
- //* Define the baud rate divisor register
- pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US_SetTimeguard
-//* \brief Set USART timeguard
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_SetTimeguard (
- AT91PS_USART pUSART, // \arg pointer to a USART controller
- unsigned int timeguard) // \arg timeguard value
-{
- //* Write the Timeguard Register
- pUSART->US_TTGR = timeguard ;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US_EnableIt
-//* \brief Enable USART IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_EnableIt (
- AT91PS_USART pUSART, // \arg pointer to a USART controller
- unsigned int flag) // \arg IT to be enabled
-{
- //* Write to the IER register
- pUSART->US_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US_DisableIt
-//* \brief Disable USART IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_DisableIt (
- AT91PS_USART pUSART, // \arg pointer to a USART controller
- unsigned int flag) // \arg IT to be disabled
-{
- //* Write to the IER register
- pUSART->US_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US_Configure
-//* \brief Configure USART
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_Configure (
- AT91PS_USART pUSART, // \arg pointer to a USART controller
- unsigned int mainClock, // \arg peripheral clock
- unsigned int mode , // \arg mode Register to be programmed
- unsigned int baudRate , // \arg baudrate to be programmed
- unsigned int timeguard ) // \arg timeguard to be programmed
-{
- //* Disable interrupts
- pUSART->US_IDR = (unsigned int) -1;
-
- //* Reset receiver and transmitter
- pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ;
-
- //* Define the baud rate divisor register
- AT91F_US_SetBaudrate(pUSART, mainClock, baudRate);
-
- //* Write the Timeguard Register
- AT91F_US_SetTimeguard(pUSART, timeguard);
-
- //* Clear Transmit and Receive Counters
- AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR));
-
- //* Define the USART mode
- pUSART->US_MR = mode ;
-
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US_EnableRx
-//* \brief Enable receiving characters
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_EnableRx (
- AT91PS_USART pUSART) // \arg pointer to a USART controller
-{
- //* Enable receiver
- pUSART->US_CR = AT91C_US_RXEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US_EnableTx
-//* \brief Enable sending characters
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_EnableTx (
- AT91PS_USART pUSART) // \arg pointer to a USART controller
-{
- //* Enable transmitter
- pUSART->US_CR = AT91C_US_TXEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US_ResetRx
-//* \brief Reset Receiver and re-enable it
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_ResetRx (
- AT91PS_USART pUSART) // \arg pointer to a USART controller
-{
- //* Reset receiver
- pUSART->US_CR = AT91C_US_RSTRX;
- //* Re-Enable receiver
- pUSART->US_CR = AT91C_US_RXEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US_ResetTx
-//* \brief Reset Transmitter and re-enable it
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_ResetTx (
- AT91PS_USART pUSART) // \arg pointer to a USART controller
-{
- //* Reset transmitter
- pUSART->US_CR = AT91C_US_RSTTX;
- //* Enable transmitter
- pUSART->US_CR = AT91C_US_TXEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US_DisableRx
-//* \brief Disable Receiver
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_DisableRx (
- AT91PS_USART pUSART) // \arg pointer to a USART controller
-{
- //* Disable receiver
- pUSART->US_CR = AT91C_US_RXDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US_DisableTx
-//* \brief Disable Transmitter
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_DisableTx (
- AT91PS_USART pUSART) // \arg pointer to a USART controller
-{
- //* Disable transmitter
- pUSART->US_CR = AT91C_US_TXDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US_Close
-//* \brief Close USART: disable IT disable receiver and transmitter, close PDC
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_Close (
- AT91PS_USART pUSART) // \arg pointer to a USART controller
-{
- //* Reset the baud rate divisor register
- pUSART->US_BRGR = 0 ;
-
- //* Reset the USART mode
- pUSART->US_MR = 0 ;
-
- //* Reset the Timeguard Register
- pUSART->US_TTGR = 0;
-
- //* Disable all interrupts
- pUSART->US_IDR = 0xFFFFFFFF ;
-
- //* Abort the Peripheral Data Transfers
- AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR));
-
- //* Disable receiver and transmitter and stop any activity immediately
- pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US_TxReady
-//* \brief Return 1 if a character can be written in US_THR
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_US_TxReady (
- AT91PS_USART pUSART ) // \arg pointer to a USART controller
-{
- return (pUSART->US_CSR & AT91C_US_TXRDY);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US_RxReady
-//* \brief Return 1 if a character can be read in US_RHR
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_US_RxReady (
- AT91PS_USART pUSART ) // \arg pointer to a USART controller
-{
- return (pUSART->US_CSR & AT91C_US_RXRDY);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US_Error
-//* \brief Return the error flag
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_US_Error (
- AT91PS_USART pUSART ) // \arg pointer to a USART controller
-{
- return (pUSART->US_CSR &
- (AT91C_US_OVRE | // Overrun error
- AT91C_US_FRAME | // Framing error
- AT91C_US_PARE)); // Parity error
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US_PutChar
-//* \brief Send a character,does not check if ready to send
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_PutChar (
- AT91PS_USART pUSART,
- int character )
-{
- pUSART->US_THR = (character & 0x1FF);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US_GetChar
-//* \brief Receive a character,does not check if a character is available
-//*----------------------------------------------------------------------------
-__inline int AT91F_US_GetChar (
- const AT91PS_USART pUSART)
-{
- return((pUSART->US_RHR) & 0x1FF);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US_SendFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_US_SendFrame(
- AT91PS_USART pUSART,
- char *pBuffer,
- unsigned int szBuffer,
- char *pNextBuffer,
- unsigned int szNextBuffer )
-{
- return AT91F_PDC_SendFrame(
- (AT91PS_PDC) &(pUSART->US_RPR),
- pBuffer,
- szBuffer,
- pNextBuffer,
- szNextBuffer);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US_ReceiveFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_US_ReceiveFrame (
- AT91PS_USART pUSART,
- char *pBuffer,
- unsigned int szBuffer,
- char *pNextBuffer,
- unsigned int szNextBuffer )
-{
- return AT91F_PDC_ReceiveFrame(
- (AT91PS_PDC) &(pUSART->US_RPR),
- pBuffer,
- szBuffer,
- pNextBuffer,
- szNextBuffer);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US_SetIrdaFilter
-//* \brief Set the value of IrDa filter tregister
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_SetIrdaFilter (
- AT91PS_USART pUSART,
- unsigned char value
-)
-{
- pUSART->US_IF = value;
-}
-
-/* *****************************************************************************
- SOFTWARE API FOR SSC
- ***************************************************************************** */
-//* Define the standard I2S mode configuration
-
-//* Configuration to set in the SSC Transmit Clock Mode Register
-//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits
-//* nb_slot_by_frame : number of channels
-#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
- AT91C_SSC_CKS_DIV +\
- AT91C_SSC_CKO_CONTINOUS +\
- AT91C_SSC_CKG_NONE +\
- AT91C_SSC_START_FALL_RF +\
- AT91C_SSC_STTOUT +\
- ((1<<16) & AT91C_SSC_STTDLY) +\
- ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24))
-
-
-//* Configuration to set in the SSC Transmit Frame Mode Register
-//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits
-//* nb_slot_by_frame : number of channels
-#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
- (nb_bit_by_slot-1) +\
- AT91C_SSC_MSBF +\
- (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\
- (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\
- AT91C_SSC_FSOS_NEGATIVE)
-
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SSC_SetBaudrate
-//* \brief Set the baudrate according to the CPU clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_SetBaudrate (
- AT91PS_SSC pSSC, // \arg pointer to a SSC controller
- unsigned int mainClock, // \arg peripheral clock
- unsigned int speed) // \arg SSC baudrate
-{
- unsigned int baud_value;
- //* Define the baud rate divisor register
- if (speed == 0)
- baud_value = 0;
- else
- {
- baud_value = (unsigned int) (mainClock * 10)/(2*speed);
- if ((baud_value % 10) >= 5)
- baud_value = (baud_value / 10) + 1;
- else
- baud_value /= 10;
- }
-
- pSSC->SSC_CMR = baud_value;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SSC_Configure
-//* \brief Configure SSC
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_Configure (
- AT91PS_SSC pSSC, // \arg pointer to a SSC controller
- unsigned int syst_clock, // \arg System Clock Frequency
- unsigned int baud_rate, // \arg Expected Baud Rate Frequency
- unsigned int clock_rx, // \arg Receiver Clock Parameters
- unsigned int mode_rx, // \arg mode Register to be programmed
- unsigned int clock_tx, // \arg Transmitter Clock Parameters
- unsigned int mode_tx) // \arg mode Register to be programmed
-{
- //* Disable interrupts
- pSSC->SSC_IDR = (unsigned int) -1;
-
- //* Reset receiver and transmitter
- pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ;
-
- //* Define the Clock Mode Register
- AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate);
-
- //* Write the Receive Clock Mode Register
- pSSC->SSC_RCMR = clock_rx;
-
- //* Write the Transmit Clock Mode Register
- pSSC->SSC_TCMR = clock_tx;
-
- //* Write the Receive Frame Mode Register
- pSSC->SSC_RFMR = mode_rx;
-
- //* Write the Transmit Frame Mode Register
- pSSC->SSC_TFMR = mode_tx;
-
- //* Clear Transmit and Receive Counters
- AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR));
-
-
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SSC_EnableRx
-//* \brief Enable receiving datas
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_EnableRx (
- AT91PS_SSC pSSC) // \arg pointer to a SSC controller
-{
- //* Enable receiver
- pSSC->SSC_CR = AT91C_SSC_RXEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SSC_DisableRx
-//* \brief Disable receiving datas
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_DisableRx (
- AT91PS_SSC pSSC) // \arg pointer to a SSC controller
-{
- //* Disable receiver
- pSSC->SSC_CR = AT91C_SSC_RXDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SSC_EnableTx
-//* \brief Enable sending datas
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_EnableTx (
- AT91PS_SSC pSSC) // \arg pointer to a SSC controller
-{
- //* Enable transmitter
- pSSC->SSC_CR = AT91C_SSC_TXEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SSC_DisableTx
-//* \brief Disable sending datas
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_DisableTx (
- AT91PS_SSC pSSC) // \arg pointer to a SSC controller
-{
- //* Disable transmitter
- pSSC->SSC_CR = AT91C_SSC_TXDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SSC_EnableIt
-//* \brief Enable SSC IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_EnableIt (
- AT91PS_SSC pSSC, // \arg pointer to a SSC controller
- unsigned int flag) // \arg IT to be enabled
-{
- //* Write to the IER register
- pSSC->SSC_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SSC_DisableIt
-//* \brief Disable SSC IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_DisableIt (
- AT91PS_SSC pSSC, // \arg pointer to a SSC controller
- unsigned int flag) // \arg IT to be disabled
-{
- //* Write to the IDR register
- pSSC->SSC_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SSC_ReceiveFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_SSC_ReceiveFrame (
- AT91PS_SSC pSSC,
- char *pBuffer,
- unsigned int szBuffer,
- char *pNextBuffer,
- unsigned int szNextBuffer )
-{
- return AT91F_PDC_ReceiveFrame(
- (AT91PS_PDC) &(pSSC->SSC_RPR),
- pBuffer,
- szBuffer,
- pNextBuffer,
- szNextBuffer);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SSC_SendFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_SSC_SendFrame(
- AT91PS_SSC pSSC,
- char *pBuffer,
- unsigned int szBuffer,
- char *pNextBuffer,
- unsigned int szNextBuffer )
-{
- return AT91F_PDC_SendFrame(
- (AT91PS_PDC) &(pSSC->SSC_RPR),
- pBuffer,
- szBuffer,
- pNextBuffer,
- szNextBuffer);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SSC_GetInterruptMaskStatus
-//* \brief Return SSC Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status
- AT91PS_SSC pSsc) // \arg pointer to a SSC controller
-{
- return pSsc->SSC_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SSC_IsInterruptMasked
-//* \brief Test if SSC Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline int AT91F_SSC_IsInterruptMasked(
- AT91PS_SSC pSsc, // \arg pointer to a SSC controller
- unsigned int flag) // \arg flag to be tested
-{
- return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag);
-}
-
-/* *****************************************************************************
- SOFTWARE API FOR TWI
- ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TWI_EnableIt
-//* \brief Enable TWI IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_TWI_EnableIt (
- AT91PS_TWI pTWI, // \arg pointer to a TWI controller
- unsigned int flag) // \arg IT to be enabled
-{
- //* Write to the IER register
- pTWI->TWI_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TWI_DisableIt
-//* \brief Disable TWI IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_TWI_DisableIt (
- AT91PS_TWI pTWI, // \arg pointer to a TWI controller
- unsigned int flag) // \arg IT to be disabled
-{
- //* Write to the IDR register
- pTWI->TWI_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TWI_Configure
-//* \brief Configure TWI in master mode
-//*----------------------------------------------------------------------------
-__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller
-{
- //* Disable interrupts
- pTWI->TWI_IDR = (unsigned int) -1;
-
- //* Reset peripheral
- pTWI->TWI_CR = AT91C_TWI_SWRST;
-
- //* Set Master mode
- pTWI->TWI_CR = AT91C_TWI_MSEN;
-
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TWI_GetInterruptMaskStatus
-//* \brief Return TWI Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status
- AT91PS_TWI pTwi) // \arg pointer to a TWI controller
-{
- return pTwi->TWI_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TWI_IsInterruptMasked
-//* \brief Test if TWI Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline int AT91F_TWI_IsInterruptMasked(
- AT91PS_TWI pTwi, // \arg pointer to a TWI controller
- unsigned int flag) // \arg flag to be tested
-{
- return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag);
-}
-
-/* *****************************************************************************
- SOFTWARE API FOR PWMC
- ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PWM_GetStatus
-//* \brief Return PWM Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status
- AT91PS_PWMC pPWM) // pointer to a PWM controller
-{
- return pPWM->PWMC_SR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PWM_InterruptEnable
-//* \brief Enable PWM Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_InterruptEnable(
- AT91PS_PWMC pPwm, // \arg pointer to a PWM controller
- unsigned int flag) // \arg PWM interrupt to be enabled
-{
- pPwm->PWMC_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PWM_InterruptDisable
-//* \brief Disable PWM Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_InterruptDisable(
- AT91PS_PWMC pPwm, // \arg pointer to a PWM controller
- unsigned int flag) // \arg PWM interrupt to be disabled
-{
- pPwm->PWMC_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PWM_GetInterruptMaskStatus
-//* \brief Return PWM Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status
- AT91PS_PWMC pPwm) // \arg pointer to a PWM controller
-{
- return pPwm->PWMC_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PWM_IsInterruptMasked
-//* \brief Test if PWM Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PWMC_IsInterruptMasked(
- AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
- unsigned int flag) // \arg flag to be tested
-{
- return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PWM_IsStatusSet
-//* \brief Test if PWM Interrupt is Set
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PWMC_IsStatusSet(
- AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
- unsigned int flag) // \arg flag to be tested
-{
- return (AT91F_PWMC_GetStatus(pPWM) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PWM_CfgChannel
-//* \brief Test if PWM Interrupt is Set
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_CfgChannel(
- AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
- unsigned int channelId, // \arg PWM channel ID
- unsigned int mode, // \arg PWM mode
- unsigned int period, // \arg PWM period
- unsigned int duty) // \arg PWM duty cycle
-{
- pPWM->PWMC_CH[channelId].PWMC_CMR = mode;
- pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty;
- pPWM->PWMC_CH[channelId].PWMC_CPRDR = period;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PWM_StartChannel
-//* \brief Enable channel
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_StartChannel(
- AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
- unsigned int flag) // \arg Channels IDs to be enabled
-{
- pPWM->PWMC_ENA = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PWM_StopChannel
-//* \brief Disable channel
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_StopChannel(
- AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
- unsigned int flag) // \arg Channels IDs to be enabled
-{
- pPWM->PWMC_DIS = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PWM_UpdateChannel
-//* \brief Update Period or Duty Cycle
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_UpdateChannel(
- AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
- unsigned int channelId, // \arg PWM channel ID
- unsigned int update) // \arg Channels IDs to be enabled
-{
- pPWM->PWMC_CH[channelId].PWMC_CUPDR = update;
-}
-
-/* *****************************************************************************
- SOFTWARE API FOR UDP
- ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn AT91F_UDP_EnableIt
-//* \brief Enable UDP IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_EnableIt (
- AT91PS_UDP pUDP, // \arg pointer to a UDP controller
- unsigned int flag) // \arg IT to be enabled
-{
- //* Write to the IER register
- pUDP->UDP_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_UDP_DisableIt
-//* \brief Disable UDP IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_DisableIt (
- AT91PS_UDP pUDP, // \arg pointer to a UDP controller
- unsigned int flag) // \arg IT to be disabled
-{
- //* Write to the IDR register
- pUDP->UDP_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_UDP_SetAddress
-//* \brief Set UDP functional address
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_SetAddress (
- AT91PS_UDP pUDP, // \arg pointer to a UDP controller
- unsigned char address) // \arg new UDP address
-{
- pUDP->UDP_FADDR = (AT91C_UDP_FEN | address);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_UDP_EnableEp
-//* \brief Enable Endpoint
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_EnableEp (
- AT91PS_UDP pUDP, // \arg pointer to a UDP controller
- unsigned char endpoint) // \arg endpoint number
-{
- pUDP->UDP_CSR[endpoint] |= AT91C_UDP_EPEDS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_UDP_DisableEp
-//* \brief Enable Endpoint
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_DisableEp (
- AT91PS_UDP pUDP, // \arg pointer to a UDP controller
- unsigned char endpoint) // \arg endpoint number
-{
- pUDP->UDP_CSR[endpoint] &= ~AT91C_UDP_EPEDS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_UDP_SetState
-//* \brief Set UDP Device state
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_SetState (
- AT91PS_UDP pUDP, // \arg pointer to a UDP controller
- unsigned int flag) // \arg new UDP address
-{
- pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG);
- pUDP->UDP_GLBSTATE |= flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_UDP_GetState
-//* \brief return UDP Device state
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state
- AT91PS_UDP pUDP) // \arg pointer to a UDP controller
-{
- return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_UDP_ResetEp
-//* \brief Reset UDP endpoint
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_ResetEp ( // \return the UDP device state
- AT91PS_UDP pUDP, // \arg pointer to a UDP controller
- unsigned int flag) // \arg Endpoints to be reset
-{
- pUDP->UDP_RSTEP = flag;
- pUDP->UDP_RSTEP = 0;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_UDP_EpStall
-//* \brief Endpoint will STALL requests
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_EpStall(
- AT91PS_UDP pUDP, // \arg pointer to a UDP controller
- unsigned char endpoint) // \arg endpoint number
-{
- pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_UDP_EpWrite
-//* \brief Write value in the DPR
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_EpWrite(
- AT91PS_UDP pUDP, // \arg pointer to a UDP controller
- unsigned char endpoint, // \arg endpoint number
- unsigned char value) // \arg value to be written in the DPR
-{
- pUDP->UDP_FDR[endpoint] = value;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_UDP_EpRead
-//* \brief Return value from the DPR
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_UDP_EpRead(
- AT91PS_UDP pUDP, // \arg pointer to a UDP controller
- unsigned char endpoint) // \arg endpoint number
-{
- return pUDP->UDP_FDR[endpoint];
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_UDP_EpEndOfWr
-//* \brief Notify the UDP that values in DPR are ready to be sent
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_EpEndOfWr(
- AT91PS_UDP pUDP, // \arg pointer to a UDP controller
- unsigned char endpoint) // \arg endpoint number
-{
- pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_UDP_EpClear
-//* \brief Clear flag in the endpoint CSR register
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_EpClear(
- AT91PS_UDP pUDP, // \arg pointer to a UDP controller
- unsigned char endpoint, // \arg endpoint number
- unsigned int flag) // \arg flag to be cleared
-{
- pUDP->UDP_CSR[endpoint] &= ~(flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_UDP_EpSet
-//* \brief Set flag in the endpoint CSR register
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_EpSet(
- AT91PS_UDP pUDP, // \arg pointer to a UDP controller
- unsigned char endpoint, // \arg endpoint number
- unsigned int flag) // \arg flag to be cleared
-{
- pUDP->UDP_CSR[endpoint] |= flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_UDP_EpStatus
-//* \brief Return the endpoint CSR register
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_UDP_EpStatus(
- AT91PS_UDP pUDP, // \arg pointer to a UDP controller
- unsigned char endpoint) // \arg endpoint number
-{
- return pUDP->UDP_CSR[endpoint];
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_UDP_GetInterruptMaskStatus
-//* \brief Return UDP Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status
- AT91PS_UDP pUdp) // \arg pointer to a UDP controller
-{
- return pUdp->UDP_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_UDP_IsInterruptMasked
-//* \brief Test if UDP Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline int AT91F_UDP_IsInterruptMasked(
- AT91PS_UDP pUdp, // \arg pointer to a UDP controller
- unsigned int flag) // \arg flag to be tested
-{
- return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag);
-}
-
-/* *****************************************************************************
- SOFTWARE API FOR TC
- ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TC_InterruptEnable
-//* \brief Enable TC Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC_InterruptEnable(
- AT91PS_TC pTc, // \arg pointer to a TC controller
- unsigned int flag) // \arg TC interrupt to be enabled
-{
- pTc->TC_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TC_InterruptDisable
-//* \brief Disable TC Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC_InterruptDisable(
- AT91PS_TC pTc, // \arg pointer to a TC controller
- unsigned int flag) // \arg TC interrupt to be disabled
-{
- pTc->TC_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TC_GetInterruptMaskStatus
-//* \brief Return TC Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status
- AT91PS_TC pTc) // \arg pointer to a TC controller
-{
- return pTc->TC_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TC_IsInterruptMasked
-//* \brief Test if TC Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline int AT91F_TC_IsInterruptMasked(
- AT91PS_TC pTc, // \arg pointer to a TC controller
- unsigned int flag) // \arg flag to be tested
-{
- return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag);
-}
-
-/* *****************************************************************************
- SOFTWARE API FOR CAN
- ***************************************************************************** */
-#define STANDARD_FORMAT 0
-#define EXTENDED_FORMAT 1
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_InitMailboxRegisters()
-//* \brief Configure the corresponding mailbox
-//*----------------------------------------------------------------------------
-__inline void AT91F_InitMailboxRegisters(AT91PS_CAN_MB CAN_Mailbox,
- int mode_reg,
- int acceptance_mask_reg,
- int id_reg,
- int data_low_reg,
- int data_high_reg,
- int control_reg)
-{
- CAN_Mailbox->CAN_MB_MCR = 0x0;
- CAN_Mailbox->CAN_MB_MMR = mode_reg;
- CAN_Mailbox->CAN_MB_MAM = acceptance_mask_reg;
- CAN_Mailbox->CAN_MB_MID = id_reg;
- CAN_Mailbox->CAN_MB_MDL = data_low_reg;
- CAN_Mailbox->CAN_MB_MDH = data_high_reg;
- CAN_Mailbox->CAN_MB_MCR = control_reg;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_EnableCAN()
-//* \brief
-//*----------------------------------------------------------------------------
-__inline void AT91F_EnableCAN(
- AT91PS_CAN pCAN) // pointer to a CAN controller
-{
- pCAN->CAN_MR |= AT91C_CAN_CANEN;
-
- // Wait for WAKEUP flag raising <=> 11-recessive-bit were scanned by the transceiver
- while( (pCAN->CAN_SR & AT91C_CAN_WAKEUP) != AT91C_CAN_WAKEUP );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_DisableCAN()
-//* \brief
-//*----------------------------------------------------------------------------
-__inline void AT91F_DisableCAN(
- AT91PS_CAN pCAN) // pointer to a CAN controller
-{
- pCAN->CAN_MR &= ~AT91C_CAN_CANEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_EnableIt
-//* \brief Enable CAN interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_EnableIt (
- AT91PS_CAN pCAN, // pointer to a CAN controller
- unsigned int flag) // IT to be enabled
-{
- //* Write to the IER register
- pCAN->CAN_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_DisableIt
-//* \brief Disable CAN interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_DisableIt (
- AT91PS_CAN pCAN, // pointer to a CAN controller
- unsigned int flag) // IT to be disabled
-{
- //* Write to the IDR register
- pCAN->CAN_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_GetStatus
-//* \brief Return CAN Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetStatus( // \return CAN Interrupt Status
- AT91PS_CAN pCAN) // pointer to a CAN controller
-{
- return pCAN->CAN_SR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_GetInterruptMaskStatus
-//* \brief Return CAN Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetInterruptMaskStatus( // \return CAN Interrupt Mask Status
- AT91PS_CAN pCAN) // pointer to a CAN controller
-{
- return pCAN->CAN_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_IsInterruptMasked
-//* \brief Test if CAN Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_IsInterruptMasked(
- AT91PS_CAN pCAN, // \arg pointer to a CAN controller
- unsigned int flag) // \arg flag to be tested
-{
- return (AT91F_CAN_GetInterruptMaskStatus(pCAN) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_IsStatusSet
-//* \brief Test if CAN Interrupt is Set
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_IsStatusSet(
- AT91PS_CAN pCAN, // \arg pointer to a CAN controller
- unsigned int flag) // \arg flag to be tested
-{
- return (AT91F_CAN_GetStatus(pCAN) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_CfgModeReg
-//* \brief Configure the Mode Register of the CAN controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_CfgModeReg (
- AT91PS_CAN pCAN, // pointer to a CAN controller
- unsigned int mode) // mode register
-{
- //* Write to the MR register
- pCAN->CAN_MR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_GetModeReg
-//* \brief Return the Mode Register of the CAN controller value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetModeReg (
- AT91PS_CAN pCAN // pointer to a CAN controller
- )
-{
- return pCAN->CAN_MR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_CfgBaudrateReg
-//* \brief Configure the Baudrate of the CAN controller for the network
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_CfgBaudrateReg (
- AT91PS_CAN pCAN, // pointer to a CAN controller
- unsigned int baudrate_cfg)
-{
- //* Write to the BR register
- pCAN->CAN_BR = baudrate_cfg;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_GetBaudrate
-//* \brief Return the Baudrate of the CAN controller for the network value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetBaudrate (
- AT91PS_CAN pCAN // pointer to a CAN controller
- )
-{
- return pCAN->CAN_BR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_GetInternalCounter
-//* \brief Return CAN Timer Regsiter Value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetInternalCounter (
- AT91PS_CAN pCAN // pointer to a CAN controller
- )
-{
- return pCAN->CAN_TIM;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_GetTimestamp
-//* \brief Return CAN Timestamp Register Value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetTimestamp (
- AT91PS_CAN pCAN // pointer to a CAN controller
- )
-{
- return pCAN->CAN_TIMESTP;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_GetErrorCounter
-//* \brief Return CAN Error Counter Register Value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetErrorCounter (
- AT91PS_CAN pCAN // pointer to a CAN controller
- )
-{
- return pCAN->CAN_ECR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_InitTransferRequest
-//* \brief Request for a transfer on the corresponding mailboxes
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_InitTransferRequest (
- AT91PS_CAN pCAN, // pointer to a CAN controller
- unsigned int transfer_cmd)
-{
- pCAN->CAN_TCR = transfer_cmd;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_InitAbortRequest
-//* \brief Abort the corresponding mailboxes
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_InitAbortRequest (
- AT91PS_CAN pCAN, // pointer to a CAN controller
- unsigned int abort_cmd)
-{
- pCAN->CAN_ACR = abort_cmd;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_CfgMessageModeReg
-//* \brief Program the Message Mode Register
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_CfgMessageModeReg (
- AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox
- unsigned int mode)
-{
- CAN_Mailbox->CAN_MB_MMR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_GetMessageModeReg
-//* \brief Return the Message Mode Register
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetMessageModeReg (
- AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox
-{
- return CAN_Mailbox->CAN_MB_MMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_CfgMessageIDReg
-//* \brief Program the Message ID Register
-//* \brief Version == 0 for Standard messsage, Version == 1 for Extended
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_CfgMessageIDReg (
- AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox
- unsigned int id,
- unsigned char version)
-{
- if(version==0) // IDvA Standard Format
- CAN_Mailbox->CAN_MB_MID = id<<18;
- else // IDvB Extended Format
- CAN_Mailbox->CAN_MB_MID = id | (1<<29); // set MIDE bit
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_GetMessageIDReg
-//* \brief Return the Message ID Register
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetMessageIDReg (
- AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox
-{
- return CAN_Mailbox->CAN_MB_MID;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_CfgMessageAcceptanceMaskReg
-//* \brief Program the Message Acceptance Mask Register
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_CfgMessageAcceptanceMaskReg (
- AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox
- unsigned int mask)
-{
- CAN_Mailbox->CAN_MB_MAM = mask;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_GetMessageAcceptanceMaskReg
-//* \brief Return the Message Acceptance Mask Register
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetMessageAcceptanceMaskReg (
- AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox
-{
- return CAN_Mailbox->CAN_MB_MAM;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_GetFamilyID
-//* \brief Return the Message ID Register
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetFamilyID (
- AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox
-{
- return CAN_Mailbox->CAN_MB_MFID;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_CfgMessageCtrl
-//* \brief Request and config for a transfer on the corresponding mailbox
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_CfgMessageCtrlReg (
- AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox
- unsigned int message_ctrl_cmd)
-{
- CAN_Mailbox->CAN_MB_MCR = message_ctrl_cmd;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_GetMessageStatus
-//* \brief Return CAN Mailbox Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetMessageStatus (
- AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox
-{
- return CAN_Mailbox->CAN_MB_MSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_CfgMessageDataLow
-//* \brief Program data low value
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_CfgMessageDataLow (
- AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox
- unsigned int data)
-{
- CAN_Mailbox->CAN_MB_MDL = data;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_GetMessageDataLow
-//* \brief Return data low value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetMessageDataLow (
- AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox
-{
- return CAN_Mailbox->CAN_MB_MDL;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_CfgMessageDataHigh
-//* \brief Program data high value
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_CfgMessageDataHigh (
- AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox
- unsigned int data)
-{
- CAN_Mailbox->CAN_MB_MDH = data;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_GetMessageDataHigh
-//* \brief Return data high value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetMessageDataHigh (
- AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox
-{
- return CAN_Mailbox->CAN_MB_MDH;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_Open
-//* \brief Open a CAN Port
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_Open (
- const unsigned int null) // \arg
-{
- /* NOT DEFINED AT THIS MOMENT */
- return ( 0 );
-}
-/* *****************************************************************************
- SOFTWARE API FOR ADC
- ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_EnableIt
-//* \brief Enable ADC interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_EnableIt (
- AT91PS_ADC pADC, // pointer to a ADC controller
- unsigned int flag) // IT to be enabled
-{
- //* Write to the IER register
- pADC->ADC_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_DisableIt
-//* \brief Disable ADC interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_DisableIt (
- AT91PS_ADC pADC, // pointer to a ADC controller
- unsigned int flag) // IT to be disabled
-{
- //* Write to the IDR register
- pADC->ADC_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_GetStatus
-//* \brief Return ADC Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status
- AT91PS_ADC pADC) // pointer to a ADC controller
-{
- return pADC->ADC_SR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_GetInterruptMaskStatus
-//* \brief Return ADC Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status
- AT91PS_ADC pADC) // pointer to a ADC controller
-{
- return pADC->ADC_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_IsInterruptMasked
-//* \brief Test if ADC Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_IsInterruptMasked(
- AT91PS_ADC pADC, // \arg pointer to a ADC controller
- unsigned int flag) // \arg flag to be tested
-{
- return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_IsStatusSet
-//* \brief Test if ADC Status is Set
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_IsStatusSet(
- AT91PS_ADC pADC, // \arg pointer to a ADC controller
- unsigned int flag) // \arg flag to be tested
-{
- return (AT91F_ADC_GetStatus(pADC) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_CfgModeReg
-//* \brief Configure the Mode Register of the ADC controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_CfgModeReg (
- AT91PS_ADC pADC, // pointer to a ADC controller
- unsigned int mode) // mode register
-{
- //* Write to the MR register
- pADC->ADC_MR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_GetModeReg
-//* \brief Return the Mode Register of the ADC controller value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetModeReg (
- AT91PS_ADC pADC // pointer to a ADC controller
- )
-{
- return pADC->ADC_MR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_CfgTimings
-//* \brief Configure the different necessary timings of the ADC controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_CfgTimings (
- AT91PS_ADC pADC, // pointer to a ADC controller
- unsigned int mck_clock, // in MHz
- unsigned int adc_clock, // in MHz
- unsigned int startup_time, // in us
- unsigned int sample_and_hold_time) // in ns
-{
- unsigned int prescal,startup,shtim;
-
- prescal = mck_clock/(2*adc_clock) - 1;
- startup = adc_clock*startup_time/8 - 1;
- shtim = adc_clock*sample_and_hold_time/1000 - 1;
-
- //* Write to the MR register
- pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_EnableChannel
-//* \brief Return ADC Timer Register Value
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_EnableChannel (
- AT91PS_ADC pADC, // pointer to a ADC controller
- unsigned int channel) // mode register
-{
- //* Write to the CHER register
- pADC->ADC_CHER = channel;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_DisableChannel
-//* \brief Return ADC Timer Register Value
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_DisableChannel (
- AT91PS_ADC pADC, // pointer to a ADC controller
- unsigned int channel) // mode register
-{
- //* Write to the CHDR register
- pADC->ADC_CHDR = channel;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_GetChannelStatus
-//* \brief Return ADC Timer Register Value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetChannelStatus (
- AT91PS_ADC pADC // pointer to a ADC controller
- )
-{
- return pADC->ADC_CHSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_StartConversion
-//* \brief Software request for a analog to digital conversion
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_StartConversion (
- AT91PS_ADC pADC // pointer to a ADC controller
- )
-{
- pADC->ADC_CR = AT91C_ADC_START;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_SoftReset
-//* \brief Software reset
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_SoftReset (
- AT91PS_ADC pADC // pointer to a ADC controller
- )
-{
- pADC->ADC_CR = AT91C_ADC_SWRST;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_GetLastConvertedData
-//* \brief Return the Last Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetLastConvertedData (
- AT91PS_ADC pADC // pointer to a ADC controller
- )
-{
- return pADC->ADC_LCDR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_GetConvertedDataCH0
-//* \brief Return the Channel 0 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH0 (
- AT91PS_ADC pADC // pointer to a ADC controller
- )
-{
- return pADC->ADC_CDR0;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_GetConvertedDataCH1
-//* \brief Return the Channel 1 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH1 (
- AT91PS_ADC pADC // pointer to a ADC controller
- )
-{
- return pADC->ADC_CDR1;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_GetConvertedDataCH2
-//* \brief Return the Channel 2 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH2 (
- AT91PS_ADC pADC // pointer to a ADC controller
- )
-{
- return pADC->ADC_CDR2;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_GetConvertedDataCH3
-//* \brief Return the Channel 3 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH3 (
- AT91PS_ADC pADC // pointer to a ADC controller
- )
-{
- return pADC->ADC_CDR3;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_GetConvertedDataCH4
-//* \brief Return the Channel 4 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH4 (
- AT91PS_ADC pADC // pointer to a ADC controller
- )
-{
- return pADC->ADC_CDR4;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_GetConvertedDataCH5
-//* \brief Return the Channel 5 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH5 (
- AT91PS_ADC pADC // pointer to a ADC controller
- )
-{
- return pADC->ADC_CDR5;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_GetConvertedDataCH6
-//* \brief Return the Channel 6 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH6 (
- AT91PS_ADC pADC // pointer to a ADC controller
- )
-{
- return pADC->ADC_CDR6;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_GetConvertedDataCH7
-//* \brief Return the Channel 7 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH7 (
- AT91PS_ADC pADC // pointer to a ADC controller
- )
-{
- return pADC->ADC_CDR7;
-}
-
-/* *****************************************************************************
- SOFTWARE API FOR AES
- ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn AT91F_AES_EnableIt
-//* \brief Enable AES interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_AES_EnableIt (
- AT91PS_AES pAES, // pointer to a AES controller
- unsigned int flag) // IT to be enabled
-{
- //* Write to the IER register
- pAES->AES_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_AES_DisableIt
-//* \brief Disable AES interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_AES_DisableIt (
- AT91PS_AES pAES, // pointer to a AES controller
- unsigned int flag) // IT to be disabled
-{
- //* Write to the IDR register
- pAES->AES_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_AES_GetStatus
-//* \brief Return AES Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_AES_GetStatus( // \return AES Interrupt Status
- AT91PS_AES pAES) // pointer to a AES controller
-{
- return pAES->AES_ISR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_AES_GetInterruptMaskStatus
-//* \brief Return AES Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_AES_GetInterruptMaskStatus( // \return AES Interrupt Mask Status
- AT91PS_AES pAES) // pointer to a AES controller
-{
- return pAES->AES_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_AES_IsInterruptMasked
-//* \brief Test if AES Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_AES_IsInterruptMasked(
- AT91PS_AES pAES, // \arg pointer to a AES controller
- unsigned int flag) // \arg flag to be tested
-{
- return (AT91F_AES_GetInterruptMaskStatus(pAES) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_AES_IsStatusSet
-//* \brief Test if AES Status is Set
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_AES_IsStatusSet(
- AT91PS_AES pAES, // \arg pointer to a AES controller
- unsigned int flag) // \arg flag to be tested
-{
- return (AT91F_AES_GetStatus(pAES) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_AES_CfgModeReg
-//* \brief Configure the Mode Register of the AES controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_AES_CfgModeReg (
- AT91PS_AES pAES, // pointer to a AES controller
- unsigned int mode) // mode register
-{
- //* Write to the MR register
- pAES->AES_MR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_AES_GetModeReg
-//* \brief Return the Mode Register of the AES controller value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_AES_GetModeReg (
- AT91PS_AES pAES // pointer to a AES controller
- )
-{
- return pAES->AES_MR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_AES_StartProcessing
-//* \brief Start Encryption or Decryption
-//*----------------------------------------------------------------------------
-__inline void AT91F_AES_StartProcessing (
- AT91PS_AES pAES // pointer to a AES controller
- )
-{
- pAES->AES_CR = AT91C_AES_START;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_AES_SoftReset
-//* \brief Reset AES
-//*----------------------------------------------------------------------------
-__inline void AT91F_AES_SoftReset (
- AT91PS_AES pAES // pointer to a AES controller
- )
-{
- pAES->AES_CR = AT91C_AES_SWRST;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_AES_LoadNewSeed
-//* \brief Load New Seed in the random number generator
-//*----------------------------------------------------------------------------
-__inline void AT91F_AES_LoadNewSeed (
- AT91PS_AES pAES // pointer to a AES controller
- )
-{
- pAES->AES_CR = AT91C_AES_LOADSEED;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_AES_SetCryptoKey
-//* \brief Set Cryptographic Key x
-//*----------------------------------------------------------------------------
-__inline void AT91F_AES_SetCryptoKey (
- AT91PS_AES pAES, // pointer to a AES controller
- unsigned char index,
- unsigned int keyword
- )
-{
- pAES->AES_KEYWxR[index] = keyword;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_AES_InputData
-//* \brief Set Input Data x
-//*----------------------------------------------------------------------------
-__inline void AT91F_AES_InputData (
- AT91PS_AES pAES, // pointer to a AES controller
- unsigned char index,
- unsigned int indata
- )
-{
- pAES->AES_IDATAxR[index] = indata;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_AES_GetOutputData
-//* \brief Get Output Data x
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_AES_GetOutputData (
- AT91PS_AES pAES, // pointer to a AES controller
- unsigned char index
- )
-{
- return pAES->AES_ODATAxR[index];
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_AES_SetInitializationVector
-//* \brief Set Initialization Vector (or Counter) x
-//*----------------------------------------------------------------------------
-__inline void AT91F_AES_SetInitializationVector (
- AT91PS_AES pAES, // pointer to a AES controller
- unsigned char index,
- unsigned int initvector
- )
-{
- pAES->AES_IVxR[index] = initvector;
-}
-
-/* *****************************************************************************
- SOFTWARE API FOR TDES
- ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TDES_EnableIt
-//* \brief Enable TDES interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_TDES_EnableIt (
- AT91PS_TDES pTDES, // pointer to a TDES controller
- unsigned int flag) // IT to be enabled
-{
- //* Write to the IER register
- pTDES->TDES_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TDES_DisableIt
-//* \brief Disable TDES interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_TDES_DisableIt (
- AT91PS_TDES pTDES, // pointer to a TDES controller
- unsigned int flag) // IT to be disabled
-{
- //* Write to the IDR register
- pTDES->TDES_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TDES_GetStatus
-//* \brief Return TDES Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_TDES_GetStatus( // \return TDES Interrupt Status
- AT91PS_TDES pTDES) // pointer to a TDES controller
-{
- return pTDES->TDES_ISR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TDES_GetInterruptMaskStatus
-//* \brief Return TDES Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_TDES_GetInterruptMaskStatus( // \return TDES Interrupt Mask Status
- AT91PS_TDES pTDES) // pointer to a TDES controller
-{
- return pTDES->TDES_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TDES_IsInterruptMasked
-//* \brief Test if TDES Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_TDES_IsInterruptMasked(
- AT91PS_TDES pTDES, // \arg pointer to a TDES controller
- unsigned int flag) // \arg flag to be tested
-{
- return (AT91F_TDES_GetInterruptMaskStatus(pTDES) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TDES_IsStatusSet
-//* \brief Test if TDES Status is Set
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_TDES_IsStatusSet(
- AT91PS_TDES pTDES, // \arg pointer to a TDES controller
- unsigned int flag) // \arg flag to be tested
-{
- return (AT91F_TDES_GetStatus(pTDES) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TDES_CfgModeReg
-//* \brief Configure the Mode Register of the TDES controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_TDES_CfgModeReg (
- AT91PS_TDES pTDES, // pointer to a TDES controller
- unsigned int mode) // mode register
-{
- //* Write to the MR register
- pTDES->TDES_MR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TDES_GetModeReg
-//* \brief Return the Mode Register of the TDES controller value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_TDES_GetModeReg (
- AT91PS_TDES pTDES // pointer to a TDES controller
- )
-{
- return pTDES->TDES_MR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TDES_StartProcessing
-//* \brief Start Encryption or Decryption
-//*----------------------------------------------------------------------------
-__inline void AT91F_TDES_StartProcessing (
- AT91PS_TDES pTDES // pointer to a TDES controller
- )
-{
- pTDES->TDES_CR = AT91C_TDES_START;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TDES_SoftReset
-//* \brief Reset TDES
-//*----------------------------------------------------------------------------
-__inline void AT91F_TDES_SoftReset (
- AT91PS_TDES pTDES // pointer to a TDES controller
- )
-{
- pTDES->TDES_CR = AT91C_TDES_SWRST;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TDES_SetCryptoKey1
-//* \brief Set Cryptographic Key 1 Word x
-//*----------------------------------------------------------------------------
-__inline void AT91F_TDES_SetCryptoKey1 (
- AT91PS_TDES pTDES, // pointer to a TDES controller
- unsigned char index,
- unsigned int keyword
- )
-{
- pTDES->TDES_KEY1WxR[index] = keyword;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TDES_SetCryptoKey2
-//* \brief Set Cryptographic Key 2 Word x
-//*----------------------------------------------------------------------------
-__inline void AT91F_TDES_SetCryptoKey2 (
- AT91PS_TDES pTDES, // pointer to a TDES controller
- unsigned char index,
- unsigned int keyword
- )
-{
- pTDES->TDES_KEY2WxR[index] = keyword;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TDES_SetCryptoKey3
-//* \brief Set Cryptographic Key 3 Word x
-//*----------------------------------------------------------------------------
-__inline void AT91F_TDES_SetCryptoKey3 (
- AT91PS_TDES pTDES, // pointer to a TDES controller
- unsigned char index,
- unsigned int keyword
- )
-{
- pTDES->TDES_KEY3WxR[index] = keyword;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TDES_InputData
-//* \brief Set Input Data x
-//*----------------------------------------------------------------------------
-__inline void AT91F_TDES_InputData (
- AT91PS_TDES pTDES, // pointer to a TDES controller
- unsigned char index,
- unsigned int indata
- )
-{
- pTDES->TDES_IDATAxR[index] = indata;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TDES_GetOutputData
-//* \brief Get Output Data x
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_TDES_GetOutputData (
- AT91PS_TDES pTDES, // pointer to a TDES controller
- unsigned char index
- )
-{
- return pTDES->TDES_ODATAxR[index];
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TDES_SetInitializationVector
-//* \brief Set Initialization Vector x
-//*----------------------------------------------------------------------------
-__inline void AT91F_TDES_SetInitializationVector (
- AT91PS_TDES pTDES, // pointer to a TDES controller
- unsigned char index,
- unsigned int initvector
- )
-{
- pTDES->TDES_IVxR[index] = initvector;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_DBGU_CfgPMC
-//* \brief Enable Peripheral clock in PMC for DBGU
-//*----------------------------------------------------------------------------
-__inline void AT91F_DBGU_CfgPMC (void)
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, // PIO controller base address
- ((unsigned int) 1 << AT91C_ID_SYS));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_DBGU_CfgPIO
-//* \brief Configure PIO controllers to drive DBGU signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_DBGU_CfgPIO (void)
-{
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, // PIO controller base address
- ((unsigned int) AT91C_PA27_DRXD ) |
- ((unsigned int) AT91C_PA28_DTXD ), // Peripheral A
- 0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PMC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for PMC
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_CfgPMC (void)
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, // PIO controller base address
- ((unsigned int) 1 << AT91C_ID_SYS));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PMC_CfgPIO
-//* \brief Configure PIO controllers to drive PMC signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_CfgPIO (void)
-{
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, // PIO controller base address
- ((unsigned int) AT91C_PB30_PCK2 ) |
- ((unsigned int) AT91C_PB29_PCK1 ), // Peripheral A
- ((unsigned int) AT91C_PB20_PCK0 ) |
- ((unsigned int) AT91C_PB0_PCK0 ) |
- ((unsigned int) AT91C_PB22_PCK2 ) |
- ((unsigned int) AT91C_PB21_PCK1 )); // Peripheral B
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, // PIO controller base address
- 0, // Peripheral A
- ((unsigned int) AT91C_PA30_PCK2 ) |
- ((unsigned int) AT91C_PA13_PCK1 ) |
- ((unsigned int) AT91C_PA27_PCK3 )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_VREG_CfgPMC
-//* \brief Enable Peripheral clock in PMC for VREG
-//*----------------------------------------------------------------------------
-__inline void AT91F_VREG_CfgPMC (void)
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, // PIO controller base address
- ((unsigned int) 1 << AT91C_ID_SYS));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_RSTC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for RSTC
-//*----------------------------------------------------------------------------
-__inline void AT91F_RSTC_CfgPMC (void)
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, // PIO controller base address
- ((unsigned int) 1 << AT91C_ID_SYS));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SSC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for SSC
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_CfgPMC (void)
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, // PIO controller base address
- ((unsigned int) 1 << AT91C_ID_SSC));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SSC_CfgPIO
-//* \brief Configure PIO controllers to drive SSC signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_CfgPIO (void)
-{
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, // PIO controller base address
- ((unsigned int) AT91C_PA25_RK ) |
- ((unsigned int) AT91C_PA22_TK ) |
- ((unsigned int) AT91C_PA21_TF ) |
- ((unsigned int) AT91C_PA24_RD ) |
- ((unsigned int) AT91C_PA26_RF ) |
- ((unsigned int) AT91C_PA23_TD ), // Peripheral A
- 0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_WDTC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for WDTC
-//*----------------------------------------------------------------------------
-__inline void AT91F_WDTC_CfgPMC (void)
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, // PIO controller base address
- ((unsigned int) 1 << AT91C_ID_SYS));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US1_CfgPMC
-//* \brief Enable Peripheral clock in PMC for US1
-//*----------------------------------------------------------------------------
-__inline void AT91F_US1_CfgPMC (void)
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, // PIO controller base address
- ((unsigned int) 1 << AT91C_ID_US1));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US1_CfgPIO
-//* \brief Configure PIO controllers to drive US1 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_US1_CfgPIO (void)
-{
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, // PIO controller base address
- 0, // Peripheral A
- ((unsigned int) AT91C_PB26_RI1 ) |
- ((unsigned int) AT91C_PB24_DSR1 ) |
- ((unsigned int) AT91C_PB23_DCD1 ) |
- ((unsigned int) AT91C_PB25_DTR1 )); // Peripheral B
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, // PIO controller base address
- ((unsigned int) AT91C_PA7_SCK1 ) |
- ((unsigned int) AT91C_PA8_RTS1 ) |
- ((unsigned int) AT91C_PA6_TXD1 ) |
- ((unsigned int) AT91C_PA5_RXD1 ) |
- ((unsigned int) AT91C_PA9_CTS1 ), // Peripheral A
- 0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US0_CfgPMC
-//* \brief Enable Peripheral clock in PMC for US0
-//*----------------------------------------------------------------------------
-__inline void AT91F_US0_CfgPMC (void)
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, // PIO controller base address
- ((unsigned int) 1 << AT91C_ID_US0));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US0_CfgPIO
-//* \brief Configure PIO controllers to drive US0 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_US0_CfgPIO (void)
-{
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, // PIO controller base address
- ((unsigned int) AT91C_PA0_RXD0 ) |
- ((unsigned int) AT91C_PA4_CTS0 ) |
- ((unsigned int) AT91C_PA3_RTS0 ) |
- ((unsigned int) AT91C_PA2_SCK0 ) |
- ((unsigned int) AT91C_PA1_TXD0 ), // Peripheral A
- 0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SPI1_CfgPMC
-//* \brief Enable Peripheral clock in PMC for SPI1
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI1_CfgPMC (void)
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, // PIO controller base address
- ((unsigned int) 1 << AT91C_ID_SPI1));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SPI1_CfgPIO
-//* \brief Configure PIO controllers to drive SPI1 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI1_CfgPIO (void)
-{
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, // PIO controller base address
- 0, // Peripheral A
- ((unsigned int) AT91C_PB16_NPCS13 ) |
- ((unsigned int) AT91C_PB10_NPCS11 ) |
- ((unsigned int) AT91C_PB11_NPCS12 )); // Peripheral B
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, // PIO controller base address
- 0, // Peripheral A
- ((unsigned int) AT91C_PA4_NPCS13 ) |
- ((unsigned int) AT91C_PA29_NPCS13 ) |
- ((unsigned int) AT91C_PA21_NPCS10 ) |
- ((unsigned int) AT91C_PA22_SPCK1 ) |
- ((unsigned int) AT91C_PA25_NPCS11 ) |
- ((unsigned int) AT91C_PA2_NPCS11 ) |
- ((unsigned int) AT91C_PA24_MISO1 ) |
- ((unsigned int) AT91C_PA3_NPCS12 ) |
- ((unsigned int) AT91C_PA26_NPCS12 ) |
- ((unsigned int) AT91C_PA23_MOSI1 )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SPI0_CfgPMC
-//* \brief Enable Peripheral clock in PMC for SPI0
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI0_CfgPMC (void)
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, // PIO controller base address
- ((unsigned int) 1 << AT91C_ID_SPI0));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SPI0_CfgPIO
-//* \brief Configure PIO controllers to drive SPI0 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI0_CfgPIO (void)
-{
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, // PIO controller base address
- 0, // Peripheral A
- ((unsigned int) AT91C_PB13_NPCS01 ) |
- ((unsigned int) AT91C_PB17_NPCS03 ) |
- ((unsigned int) AT91C_PB14_NPCS02 )); // Peripheral B
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, // PIO controller base address
- ((unsigned int) AT91C_PA16_MISO0 ) |
- ((unsigned int) AT91C_PA13_NPCS01 ) |
- ((unsigned int) AT91C_PA15_NPCS03 ) |
- ((unsigned int) AT91C_PA17_MOSI0 ) |
- ((unsigned int) AT91C_PA18_SPCK0 ) |
- ((unsigned int) AT91C_PA14_NPCS02 ) |
- ((unsigned int) AT91C_PA12_NPCS00 ), // Peripheral A
- ((unsigned int) AT91C_PA7_NPCS01 ) |
- ((unsigned int) AT91C_PA9_NPCS03 ) |
- ((unsigned int) AT91C_PA8_NPCS02 )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PITC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for PITC
-//*----------------------------------------------------------------------------
-__inline void AT91F_PITC_CfgPMC (void)
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, // PIO controller base address
- ((unsigned int) 1 << AT91C_ID_SYS));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_AIC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for AIC
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_CfgPMC (void)
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, // PIO controller base address
- ((unsigned int) 1 << AT91C_ID_FIQ) |
- ((unsigned int) 1 << AT91C_ID_IRQ0) |
- ((unsigned int) 1 << AT91C_ID_IRQ1));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_AIC_CfgPIO
-//* \brief Configure PIO controllers to drive AIC signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_CfgPIO (void)
-{
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, // PIO controller base address
- ((unsigned int) AT91C_PA30_IRQ0 ) |
- ((unsigned int) AT91C_PA29_FIQ ), // Peripheral A
- ((unsigned int) AT91C_PA14_IRQ1 )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_AES_CfgPMC
-//* \brief Enable Peripheral clock in PMC for AES
-//*----------------------------------------------------------------------------
-__inline void AT91F_AES_CfgPMC (void)
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, // PIO controller base address
- ((unsigned int) 1 << AT91C_ID_AES));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TWI_CfgPMC
-//* \brief Enable Peripheral clock in PMC for TWI
-//*----------------------------------------------------------------------------
-__inline void AT91F_TWI_CfgPMC (void)
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, // PIO controller base address
- ((unsigned int) 1 << AT91C_ID_TWI));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TWI_CfgPIO
-//* \brief Configure PIO controllers to drive TWI signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_TWI_CfgPIO (void)
-{
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, // PIO controller base address
- ((unsigned int) AT91C_PA11_TWCK ) |
- ((unsigned int) AT91C_PA10_TWD ), // Peripheral A
- 0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for ADC
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_CfgPMC (void)
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, // PIO controller base address
- ((unsigned int) 1 << AT91C_ID_ADC));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_CfgPIO
-//* \brief Configure PIO controllers to drive ADC signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_CfgPIO (void)
-{
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, // PIO controller base address
- 0, // Peripheral A
- ((unsigned int) AT91C_PB18_ADTRG )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PWMC_CH3_CfgPIO
-//* \brief Configure PIO controllers to drive PWMC_CH3 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_CH3_CfgPIO (void)
-{
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, // PIO controller base address
- ((unsigned int) AT91C_PB22_PWM3 ), // Peripheral A
- ((unsigned int) AT91C_PB30_PWM3 )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PWMC_CH2_CfgPIO
-//* \brief Configure PIO controllers to drive PWMC_CH2 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_CH2_CfgPIO (void)
-{
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, // PIO controller base address
- ((unsigned int) AT91C_PB21_PWM2 ), // Peripheral A
- ((unsigned int) AT91C_PB29_PWM2 )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PWMC_CH1_CfgPIO
-//* \brief Configure PIO controllers to drive PWMC_CH1 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_CH1_CfgPIO (void)
-{
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, // PIO controller base address
- ((unsigned int) AT91C_PB20_PWM1 ), // Peripheral A
- ((unsigned int) AT91C_PB28_PWM1 )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PWMC_CH0_CfgPIO
-//* \brief Configure PIO controllers to drive PWMC_CH0 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_CH0_CfgPIO (void)
-{
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, // PIO controller base address
- ((unsigned int) AT91C_PB19_PWM0 ), // Peripheral A
- ((unsigned int) AT91C_PB27_PWM0 )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_RTTC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for RTTC
-//*----------------------------------------------------------------------------
-__inline void AT91F_RTTC_CfgPMC (void)
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, // PIO controller base address
- ((unsigned int) 1 << AT91C_ID_SYS));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_UDP_CfgPMC
-//* \brief Enable Peripheral clock in PMC for UDP
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_CfgPMC (void)
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, // PIO controller base address
- ((unsigned int) 1 << AT91C_ID_UDP));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TDES_CfgPMC
-//* \brief Enable Peripheral clock in PMC for TDES
-//*----------------------------------------------------------------------------
-__inline void AT91F_TDES_CfgPMC (void)
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, // PIO controller base address
- ((unsigned int) 1 << AT91C_ID_TDES));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_EMAC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for EMAC
-//*----------------------------------------------------------------------------
-__inline void AT91F_EMAC_CfgPMC (void)
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, // PIO controller base address
- ((unsigned int) 1 << AT91C_ID_EMAC));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_EMAC_CfgPIO
-//* \brief Configure PIO controllers to drive EMAC signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_EMAC_CfgPIO (void)
-{
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, // PIO controller base address
- ((unsigned int) AT91C_PB2_ETX0 ) |
- ((unsigned int) AT91C_PB12_ETXER ) |
- ((unsigned int) AT91C_PB16_ECOL ) |
- ((unsigned int) AT91C_PB11_ETX3 ) |
- ((unsigned int) AT91C_PB6_ERX1 ) |
- ((unsigned int) AT91C_PB15_ERXDV ) |
- ((unsigned int) AT91C_PB13_ERX2 ) |
- ((unsigned int) AT91C_PB3_ETX1 ) |
- ((unsigned int) AT91C_PB8_EMDC ) |
- ((unsigned int) AT91C_PB5_ERX0 ) |
- //((unsigned int) AT91C_PB18_EF100 ) |
- ((unsigned int) AT91C_PB14_ERX3 ) |
- ((unsigned int) AT91C_PB4_ECRS_ECRSDV) |
- ((unsigned int) AT91C_PB1_ETXEN ) |
- ((unsigned int) AT91C_PB10_ETX2 ) |
- ((unsigned int) AT91C_PB0_ETXCK_EREFCK) |
- ((unsigned int) AT91C_PB9_EMDIO ) |
- ((unsigned int) AT91C_PB7_ERXER ) |
- ((unsigned int) AT91C_PB17_ERXCK ), // Peripheral A
- 0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TC0_CfgPMC
-//* \brief Enable Peripheral clock in PMC for TC0
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC0_CfgPMC (void)
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, // PIO controller base address
- ((unsigned int) 1 << AT91C_ID_TC0));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TC0_CfgPIO
-//* \brief Configure PIO controllers to drive TC0 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC0_CfgPIO (void)
-{
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, // PIO controller base address
- ((unsigned int) AT91C_PB23_TIOA0 ) |
- ((unsigned int) AT91C_PB24_TIOB0 ), // Peripheral A
- ((unsigned int) AT91C_PB12_TCLK0 )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TC1_CfgPMC
-//* \brief Enable Peripheral clock in PMC for TC1
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC1_CfgPMC (void)
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, // PIO controller base address
- ((unsigned int) 1 << AT91C_ID_TC1));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TC1_CfgPIO
-//* \brief Configure PIO controllers to drive TC1 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC1_CfgPIO (void)
-{
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, // PIO controller base address
- ((unsigned int) AT91C_PB25_TIOA1 ) |
- ((unsigned int) AT91C_PB26_TIOB1 ), // Peripheral A
- ((unsigned int) AT91C_PB19_TCLK1 )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TC2_CfgPMC
-//* \brief Enable Peripheral clock in PMC for TC2
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC2_CfgPMC (void)
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, // PIO controller base address
- ((unsigned int) 1 << AT91C_ID_TC2));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TC2_CfgPIO
-//* \brief Configure PIO controllers to drive TC2 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC2_CfgPIO (void)
-{
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOB, // PIO controller base address
- ((unsigned int) AT91C_PB28_TIOB2 ) |
- ((unsigned int) AT91C_PB27_TIOA2 ), // Peripheral A
- 0); // Peripheral B
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, // PIO controller base address
- 0, // Peripheral A
- ((unsigned int) AT91C_PA15_TCLK2 )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_MC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for MC
-//*----------------------------------------------------------------------------
-__inline void AT91F_MC_CfgPMC (void)
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, // PIO controller base address
- ((unsigned int) 1 << AT91C_ID_SYS));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIOA_CfgPMC
-//* \brief Enable Peripheral clock in PMC for PIOA
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIOA_CfgPMC (void)
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, // PIO controller base address
- ((unsigned int) 1 << AT91C_ID_PIOA));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIOB_CfgPMC
-//* \brief Enable Peripheral clock in PMC for PIOB
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIOB_CfgPMC (void)
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, // PIO controller base address
- ((unsigned int) 1 << AT91C_ID_PIOB));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_CfgPMC
-//* \brief Enable Peripheral clock in PMC for CAN
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_CfgPMC (void)
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, // PIO controller base address
- ((unsigned int) 1 << AT91C_ID_CAN));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_CfgPIO
-//* \brief Configure PIO controllers to drive CAN signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_CfgPIO (void)
-{
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph(
- AT91C_BASE_PIOA, // PIO controller base address
- ((unsigned int) AT91C_PA20_CANTX ) |
- ((unsigned int) AT91C_PA19_CANRX ), // Peripheral A
- 0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PWMC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for PWMC
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_CfgPMC (void)
-{
- AT91F_PMC_EnablePeriphClock(
- AT91C_BASE_PMC, // PIO controller base address
- ((unsigned int) 1 << AT91C_ID_PWMC));
-}
-
-#endif // lib_AT91SAM7X256_H
+//* ----------------------------------------------------------------------------
+//* ATMEL Microcontroller Software Support - ROUSSET -
+//* ----------------------------------------------------------------------------
+//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//* ----------------------------------------------------------------------------
+//* File Name : lib_AT91SAM7X256.h
+//* Object : AT91SAM7X256 inlined functions
+//* Generated : AT91 SW Application Group 05/20/2005 (16:22:29)
+//*
+//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003//
+//* CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005//
+//* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005//
+//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004//
+//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//
+//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004//
+//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//
+//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003//
+//* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004//
+//* CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005//
+//* CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005//
+//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004//
+//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003//
+//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004//
+//* CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005//
+//* CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005//
+//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
+//* CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004//
+//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//
+//* CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003//
+//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
+//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002//
+//* ----------------------------------------------------------------------------
+
+#ifndef lib_AT91SAM7X256_H
+#define lib_AT91SAM7X256_H
+
+/* *****************************************************************************
+ SOFTWARE API FOR AIC
+ ***************************************************************************** */
+#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20]
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_ConfigureIt
+//* \brief Interrupt Handler Initialization
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AIC_ConfigureIt (
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ unsigned int irq_id, // \arg interrupt number to initialize
+ unsigned int priority, // \arg priority to give to the interrupt
+ unsigned int src_type, // \arg activation and sense of activation
+ void (*newHandler) (void) ) // \arg address of the interrupt handler
+{
+ unsigned int oldHandler;
+ unsigned int mask ;
+
+ oldHandler = pAic->AIC_SVR[irq_id];
+
+ mask = 0x1 << irq_id ;
+ //* Disable the interrupt on the interrupt controller
+ pAic->AIC_IDCR = mask ;
+ //* Save the interrupt handler routine pointer and the interrupt priority
+ pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ;
+ //* Store the Source Mode Register
+ pAic->AIC_SMR[irq_id] = src_type | priority ;
+ //* Clear the interrupt on the interrupt controller
+ pAic->AIC_ICCR = mask ;
+
+ return oldHandler;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_EnableIt
+//* \brief Enable corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_EnableIt (
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ unsigned int irq_id ) // \arg interrupt number to initialize
+{
+ //* Enable the interrupt on the interrupt controller
+ pAic->AIC_IECR = 0x1 << irq_id ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_DisableIt
+//* \brief Disable corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_DisableIt (
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ unsigned int irq_id ) // \arg interrupt number to initialize
+{
+ unsigned int mask = 0x1 << irq_id;
+ //* Disable the interrupt on the interrupt controller
+ pAic->AIC_IDCR = mask ;
+ //* Clear the interrupt on the Interrupt Controller ( if one is pending )
+ pAic->AIC_ICCR = mask ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_ClearIt
+//* \brief Clear corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_ClearIt (
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ unsigned int irq_id) // \arg interrupt number to initialize
+{
+ //* Clear the interrupt on the Interrupt Controller ( if one is pending )
+ pAic->AIC_ICCR = (0x1 << irq_id);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_AcknowledgeIt
+//* \brief Acknowledge corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_AcknowledgeIt (
+ AT91PS_AIC pAic) // \arg pointer to the AIC registers
+{
+ pAic->AIC_EOICR = pAic->AIC_EOICR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_SetExceptionVector
+//* \brief Configure vector handler
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AIC_SetExceptionVector (
+ unsigned int *pVector, // \arg pointer to the AIC registers
+ void (*Handler) () ) // \arg Interrupt Handler
+{
+ unsigned int oldVector = *pVector;
+
+ if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE)
+ *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE;
+ else
+ *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000;
+
+ return oldVector;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_Trig
+//* \brief Trig an IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_Trig (
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ unsigned int irq_id) // \arg interrupt number
+{
+ pAic->AIC_ISCR = (0x1 << irq_id) ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_IsActive
+//* \brief Test if an IT is active
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AIC_IsActive (
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ unsigned int irq_id) // \arg Interrupt Number
+{
+ return (pAic->AIC_ISR & (0x1 << irq_id));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_IsPending
+//* \brief Test if an IT is pending
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AIC_IsPending (
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ unsigned int irq_id) // \arg Interrupt Number
+{
+ return (pAic->AIC_IPR & (0x1 << irq_id));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_Open
+//* \brief Set exception vectors and AIC registers to default values
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_Open(
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ void (*IrqHandler) (), // \arg Default IRQ vector exception
+ void (*FiqHandler) (), // \arg Default FIQ vector exception
+ void (*DefaultHandler) (), // \arg Default Handler set in ISR
+ void (*SpuriousHandler) (), // \arg Default Spurious Handler
+ unsigned int protectMode) // \arg Debug Control Register
+{
+ int i;
+
+ // Disable all interrupts and set IVR to the default handler
+ for (i = 0; i < 32; ++i) {
+ AT91F_AIC_DisableIt(pAic, i);
+ AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler);
+ }
+
+ // Set the IRQ exception vector
+ AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler);
+ // Set the Fast Interrupt exception vector
+ AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler);
+
+ pAic->AIC_SPU = (unsigned int) SpuriousHandler;
+ pAic->AIC_DCR = protectMode;
+}
+/* *****************************************************************************
+ SOFTWARE API FOR PDC
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_SetNextRx
+//* \brief Set the next receive transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetNextRx (
+ AT91PS_PDC pPDC, // \arg pointer to a PDC controller
+ char *address, // \arg address to the next bloc to be received
+ unsigned int bytes) // \arg number of bytes to be received
+{
+ pPDC->PDC_RNPR = (unsigned int) address;
+ pPDC->PDC_RNCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_SetNextTx
+//* \brief Set the next transmit transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetNextTx (
+ AT91PS_PDC pPDC, // \arg pointer to a PDC controller
+ char *address, // \arg address to the next bloc to be transmitted
+ unsigned int bytes) // \arg number of bytes to be transmitted
+{
+ pPDC->PDC_TNPR = (unsigned int) address;
+ pPDC->PDC_TNCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_SetRx
+//* \brief Set the receive transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetRx (
+ AT91PS_PDC pPDC, // \arg pointer to a PDC controller
+ char *address, // \arg address to the next bloc to be received
+ unsigned int bytes) // \arg number of bytes to be received
+{
+ pPDC->PDC_RPR = (unsigned int) address;
+ pPDC->PDC_RCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_SetTx
+//* \brief Set the transmit transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetTx (
+ AT91PS_PDC pPDC, // \arg pointer to a PDC controller
+ char *address, // \arg address to the next bloc to be transmitted
+ unsigned int bytes) // \arg number of bytes to be transmitted
+{
+ pPDC->PDC_TPR = (unsigned int) address;
+ pPDC->PDC_TCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_EnableTx
+//* \brief Enable transmit
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_EnableTx (
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
+{
+ pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_EnableRx
+//* \brief Enable receive
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_EnableRx (
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
+{
+ pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_DisableTx
+//* \brief Disable transmit
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_DisableTx (
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
+{
+ pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_DisableRx
+//* \brief Disable receive
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_DisableRx (
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
+{
+ pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_IsTxEmpty
+//* \brief Test if the current transfer descriptor has been sent
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
+{
+ return !(pPDC->PDC_TCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_IsNextTxEmpty
+//* \brief Test if the next transfer descriptor has been moved to the current td
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
+{
+ return !(pPDC->PDC_TNCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_IsRxEmpty
+//* \brief Test if the current transfer descriptor has been filled
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
+{
+ return !(pPDC->PDC_RCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_IsNextRxEmpty
+//* \brief Test if the next transfer descriptor has been moved to the current td
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
+{
+ return !(pPDC->PDC_RNCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_Open
+//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_Open (
+ AT91PS_PDC pPDC) // \arg pointer to a PDC controller
+{
+ //* Disable the RX and TX PDC transfer requests
+ AT91F_PDC_DisableRx(pPDC);
+ AT91F_PDC_DisableTx(pPDC);
+
+ //* Reset all Counter register Next buffer first
+ AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
+ AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
+ AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
+ AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
+
+ //* Enable the RX and TX PDC transfer requests
+ AT91F_PDC_EnableRx(pPDC);
+ AT91F_PDC_EnableTx(pPDC);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_Close
+//* \brief Close PDC: disable TX and RX reset transfer descriptors
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_Close (
+ AT91PS_PDC pPDC) // \arg pointer to a PDC controller
+{
+ //* Disable the RX and TX PDC transfer requests
+ AT91F_PDC_DisableRx(pPDC);
+ AT91F_PDC_DisableTx(pPDC);
+
+ //* Reset all Counter register Next buffer first
+ AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
+ AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
+ AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
+ AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
+
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_SendFrame
+//* \brief Close PDC: disable TX and RX reset transfer descriptors
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PDC_SendFrame(
+ AT91PS_PDC pPDC,
+ char *pBuffer,
+ unsigned int szBuffer,
+ char *pNextBuffer,
+ unsigned int szNextBuffer )
+{
+ if (AT91F_PDC_IsTxEmpty(pPDC)) {
+ //* Buffer and next buffer can be initialized
+ AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer);
+ AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer);
+ return 2;
+ }
+ else if (AT91F_PDC_IsNextTxEmpty(pPDC)) {
+ //* Only one buffer can be initialized
+ AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer);
+ return 1;
+ }
+ else {
+ //* All buffer are in use...
+ return 0;
+ }
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_ReceiveFrame
+//* \brief Close PDC: disable TX and RX reset transfer descriptors
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PDC_ReceiveFrame (
+ AT91PS_PDC pPDC,
+ char *pBuffer,
+ unsigned int szBuffer,
+ char *pNextBuffer,
+ unsigned int szNextBuffer )
+{
+ if (AT91F_PDC_IsRxEmpty(pPDC)) {
+ //* Buffer and next buffer can be initialized
+ AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer);
+ AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer);
+ return 2;
+ }
+ else if (AT91F_PDC_IsNextRxEmpty(pPDC)) {
+ //* Only one buffer can be initialized
+ AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer);
+ return 1;
+ }
+ else {
+ //* All buffer are in use...
+ return 0;
+ }
+}
+/* *****************************************************************************
+ SOFTWARE API FOR DBGU
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_DBGU_InterruptEnable
+//* \brief Enable DBGU Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_InterruptEnable(
+ AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller
+ unsigned int flag) // \arg dbgu interrupt to be enabled
+{
+ pDbgu->DBGU_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_DBGU_InterruptDisable
+//* \brief Disable DBGU Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_InterruptDisable(
+ AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller
+ unsigned int flag) // \arg dbgu interrupt to be disabled
+{
+ pDbgu->DBGU_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_DBGU_GetInterruptMaskStatus
+//* \brief Return DBGU Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status
+ AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller
+{
+ return pDbgu->DBGU_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_DBGU_IsInterruptMasked
+//* \brief Test if DBGU Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_DBGU_IsInterruptMasked(
+ AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag);
+}
+
+/* *****************************************************************************
+ SOFTWARE API FOR PIO
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_CfgPeriph
+//* \brief Enable pins to be drived by peripheral
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgPeriph(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int periphAEnable, // \arg PERIPH A to enable
+ unsigned int periphBEnable) // \arg PERIPH B to enable
+
+{
+ pPio->PIO_ASR = periphAEnable;
+ pPio->PIO_BSR = periphBEnable;
+ pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_CfgOutput
+//* \brief Enable PIO in output mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgOutput(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int pioEnable) // \arg PIO to be enabled
+{
+ pPio->PIO_PER = pioEnable; // Set in PIO mode
+ pPio->PIO_OER = pioEnable; // Configure in Output
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_CfgInput
+//* \brief Enable PIO in input mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgInput(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int inputEnable) // \arg PIO to be enabled
+{
+ // Disable output
+ pPio->PIO_ODR = inputEnable;
+ pPio->PIO_PER = inputEnable;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_CfgOpendrain
+//* \brief Configure PIO in open drain
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgOpendrain(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int multiDrvEnable) // \arg pio to be configured in open drain
+{
+ // Configure the multi-drive option
+ pPio->PIO_MDDR = ~multiDrvEnable;
+ pPio->PIO_MDER = multiDrvEnable;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_CfgPullup
+//* \brief Enable pullup on PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgPullup(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int pullupEnable) // \arg enable pullup on PIO
+{
+ // Connect or not Pullup
+ pPio->PIO_PPUDR = ~pullupEnable;
+ pPio->PIO_PPUER = pullupEnable;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_CfgDirectDrive
+//* \brief Enable direct drive on PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgDirectDrive(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int directDrive) // \arg PIO to be configured with direct drive
+
+{
+ // Configure the Direct Drive
+ pPio->PIO_OWDR = ~directDrive;
+ pPio->PIO_OWER = directDrive;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_CfgInputFilter
+//* \brief Enable input filter on input PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgInputFilter(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int inputFilter) // \arg PIO to be configured with input filter
+
+{
+ // Configure the Direct Drive
+ pPio->PIO_IFDR = ~inputFilter;
+ pPio->PIO_IFER = inputFilter;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetInput
+//* \brief Return PIO input value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInput( // \return PIO input
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_PDSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsInputSet
+//* \brief Test if PIO is input flag is active
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInputSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PIO_GetInput(pPio) & flag);
+}
+
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_SetOutput
+//* \brief Set to 1 output PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_SetOutput(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg output to be set
+{
+ pPio->PIO_SODR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_ClearOutput
+//* \brief Set to 0 output PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_ClearOutput(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg output to be cleared
+{
+ pPio->PIO_CODR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_ForceOutput
+//* \brief Force output when Direct drive option is enabled
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_ForceOutput(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg output to be forced
+{
+ pPio->PIO_ODSR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_Enable
+//* \brief Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_Enable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio to be enabled
+{
+ pPio->PIO_PER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_Disable
+//* \brief Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_Disable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio to be disabled
+{
+ pPio->PIO_PDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetStatus
+//* \brief Return PIO Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_PSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsSet
+//* \brief Test if PIO is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PIO_GetStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_OutputEnable
+//* \brief Output Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputEnable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio output to be enabled
+{
+ pPio->PIO_OER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_OutputDisable
+//* \brief Output Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputDisable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio output to be disabled
+{
+ pPio->PIO_ODR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetOutputStatus
+//* \brief Return PIO Output Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_OSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsOuputSet
+//* \brief Test if PIO Output is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsOutputSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PIO_GetOutputStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_InputFilterEnable
+//* \brief Input Filter Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InputFilterEnable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio input filter to be enabled
+{
+ pPio->PIO_IFER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_InputFilterDisable
+//* \brief Input Filter Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InputFilterDisable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio input filter to be disabled
+{
+ pPio->PIO_IFDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetInputFilterStatus
+//* \brief Return PIO Input Filter Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_IFSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsInputFilterSet
+//* \brief Test if PIO Input filter is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInputFilterSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PIO_GetInputFilterStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetOutputDataStatus
+//* \brief Return PIO Output Data Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_ODSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_InterruptEnable
+//* \brief Enable PIO Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InterruptEnable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio interrupt to be enabled
+{
+ pPio->PIO_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_InterruptDisable
+//* \brief Disable PIO Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InterruptDisable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio interrupt to be disabled
+{
+ pPio->PIO_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetInterruptMaskStatus
+//* \brief Return PIO Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetInterruptStatus
+//* \brief Return PIO Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_ISR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsInterruptMasked
+//* \brief Test if PIO Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInterruptMasked(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsInterruptSet
+//* \brief Test if PIO Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInterruptSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PIO_GetInterruptStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_MultiDriverEnable
+//* \brief Multi Driver Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_MultiDriverEnable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio to be enabled
+{
+ pPio->PIO_MDER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_MultiDriverDisable
+//* \brief Multi Driver Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_MultiDriverDisable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio to be disabled
+{
+ pPio->PIO_MDDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetMultiDriverStatus
+//* \brief Return PIO Multi Driver Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_MDSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsMultiDriverSet
+//* \brief Test if PIO MultiDriver is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsMultiDriverSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_A_RegisterSelection
+//* \brief PIO A Register Selection
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_A_RegisterSelection(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio A register selection
+{
+ pPio->PIO_ASR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_B_RegisterSelection
+//* \brief PIO B Register Selection
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_B_RegisterSelection(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio B register selection
+{
+ pPio->PIO_BSR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_Get_AB_RegisterStatus
+//* \brief Return PIO Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_ABSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsAB_RegisterSet
+//* \brief Test if PIO AB Register is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsAB_RegisterSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_OutputWriteEnable
+//* \brief Output Write Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputWriteEnable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio output write to be enabled
+{
+ pPio->PIO_OWER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_OutputWriteDisable
+//* \brief Output Write Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputWriteDisable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio output write to be disabled
+{
+ pPio->PIO_OWDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetOutputWriteStatus
+//* \brief Return PIO Output Write Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_OWSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsOutputWriteSet
+//* \brief Test if PIO OutputWrite is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsOutputWriteSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetCfgPullup
+//* \brief Return PIO Configuration Pullup
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_PPUSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsOutputDataStatusSet
+//* \brief Test if PIO Output Data Status is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsOutputDataStatusSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PIO_GetOutputDataStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsCfgPullupStatusSet
+//* \brief Test if PIO Configuration Pullup Status is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsCfgPullupStatusSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (~AT91F_PIO_GetCfgPullup(pPio) & flag);
+}
+
+/* *****************************************************************************
+ SOFTWARE API FOR PMC
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_CfgSysClkEnableReg
+//* \brief Configure the System Clock Enable Register of the PMC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgSysClkEnableReg (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ unsigned int mode)
+{
+ //* Write to the SCER register
+ pPMC->PMC_SCER = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_CfgSysClkDisableReg
+//* \brief Configure the System Clock Disable Register of the PMC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgSysClkDisableReg (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ unsigned int mode)
+{
+ //* Write to the SCDR register
+ pPMC->PMC_SCDR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_GetSysClkStatusReg
+//* \brief Return the System Clock Status Register of the PMC controller
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetSysClkStatusReg (
+ AT91PS_PMC pPMC // pointer to a CAN controller
+ )
+{
+ return pPMC->PMC_SCSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_EnablePeriphClock
+//* \brief Enable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_EnablePeriphClock (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ unsigned int periphIds) // \arg IDs of peripherals to enable
+{
+ pPMC->PMC_PCER = periphIds;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_DisablePeriphClock
+//* \brief Disable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_DisablePeriphClock (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ unsigned int periphIds) // \arg IDs of peripherals to enable
+{
+ pPMC->PMC_PCDR = periphIds;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_GetPeriphClock
+//* \brief Get peripheral clock status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetPeriphClock (
+ AT91PS_PMC pPMC) // \arg pointer to PMC controller
+{
+ return pPMC->PMC_PCSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CKGR_CfgMainOscillatorReg
+//* \brief Cfg the main oscillator
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_CfgMainOscillatorReg (
+ AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+ unsigned int mode)
+{
+ pCKGR->CKGR_MOR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CKGR_GetMainOscillatorReg
+//* \brief Cfg the main oscillator
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CKGR_GetMainOscillatorReg (
+ AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+ return pCKGR->CKGR_MOR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CKGR_EnableMainOscillator
+//* \brief Enable the main oscillator
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_EnableMainOscillator(
+ AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+ pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CKGR_DisableMainOscillator
+//* \brief Disable the main oscillator
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_DisableMainOscillator (
+ AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+ pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CKGR_CfgMainOscStartUpTime
+//* \brief Cfg MOR Register according to the main osc startup time
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_CfgMainOscStartUpTime (
+ AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+ unsigned int startup_time, // \arg main osc startup time in microsecond (us)
+ unsigned int slowClock) // \arg slowClock in Hz
+{
+ pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT;
+ pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CKGR_GetMainClockFreqReg
+//* \brief Cfg the main oscillator
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CKGR_GetMainClockFreqReg (
+ AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+ return pCKGR->CKGR_MCFR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CKGR_GetMainClock
+//* \brief Return Main clock in Hz
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CKGR_GetMainClock (
+ AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+ unsigned int slowClock) // \arg slowClock in Hz
+{
+ return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_CfgMCKReg
+//* \brief Cfg Master Clock Register
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgMCKReg (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ unsigned int mode)
+{
+ pPMC->PMC_MCKR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_GetMCKReg
+//* \brief Return Master Clock Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetMCKReg(
+ AT91PS_PMC pPMC) // \arg pointer to PMC controller
+{
+ return pPMC->PMC_MCKR;
+}
+
+//*------------------------------------------------------------------------------
+//* \fn AT91F_PMC_GetMasterClock
+//* \brief Return master clock in Hz which correponds to processor clock for ARM7
+//*------------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetMasterClock (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+ unsigned int slowClock) // \arg slowClock in Hz
+{
+ unsigned int reg = pPMC->PMC_MCKR;
+ unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2));
+ unsigned int pllDivider, pllMultiplier;
+
+ switch (reg & AT91C_PMC_CSS) {
+ case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected
+ return slowClock / prescaler;
+ case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected
+ return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler;
+ case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected
+ reg = pCKGR->CKGR_PLLR;
+ pllDivider = (reg & AT91C_CKGR_DIV);
+ pllMultiplier = ((reg & AT91C_CKGR_MUL) >> 16) + 1;
+ return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler;
+ }
+ return 0;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_EnablePCK
+//* \brief Enable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_EnablePCK (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ unsigned int pck, // \arg Peripheral clock identifier 0 .. 7
+ unsigned int mode)
+{
+ pPMC->PMC_PCKR[pck] = mode;
+ pPMC->PMC_SCER = (1 << pck) << 8;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_DisablePCK
+//* \brief Enable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_DisablePCK (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ unsigned int pck) // \arg Peripheral clock identifier 0 .. 7
+{
+ pPMC->PMC_SCDR = (1 << pck) << 8;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_EnableIt
+//* \brief Enable PMC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_EnableIt (
+ AT91PS_PMC pPMC, // pointer to a PMC controller
+ unsigned int flag) // IT to be enabled
+{
+ //* Write to the IER register
+ pPMC->PMC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_DisableIt
+//* \brief Disable PMC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_DisableIt (
+ AT91PS_PMC pPMC, // pointer to a PMC controller
+ unsigned int flag) // IT to be disabled
+{
+ //* Write to the IDR register
+ pPMC->PMC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_GetStatus
+//* \brief Return PMC Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status
+ AT91PS_PMC pPMC) // pointer to a PMC controller
+{
+ return pPMC->PMC_SR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_GetInterruptMaskStatus
+//* \brief Return PMC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status
+ AT91PS_PMC pPMC) // pointer to a PMC controller
+{
+ return pPMC->PMC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_IsInterruptMasked
+//* \brief Test if PMC Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_IsInterruptMasked(
+ AT91PS_PMC pPMC, // \arg pointer to a PMC controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_IsStatusSet
+//* \brief Test if PMC Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_IsStatusSet(
+ AT91PS_PMC pPMC, // \arg pointer to a PMC controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PMC_GetStatus(pPMC) & flag);
+}/* *****************************************************************************
+ SOFTWARE API FOR RSTC
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_RSTSoftReset
+//* \brief Start Software Reset
+//*----------------------------------------------------------------------------
+__inline void AT91F_RSTSoftReset(
+ AT91PS_RSTC pRSTC,
+ unsigned int reset)
+{
+ pRSTC->RSTC_RCR = (0xA5000000 | reset);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_RSTSetMode
+//* \brief Set Reset Mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_RSTSetMode(
+ AT91PS_RSTC pRSTC,
+ unsigned int mode)
+{
+ pRSTC->RSTC_RMR = (0xA5000000 | mode);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_RSTGetMode
+//* \brief Get Reset Mode
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_RSTGetMode(
+ AT91PS_RSTC pRSTC)
+{
+ return (pRSTC->RSTC_RMR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_RSTGetStatus
+//* \brief Get Reset Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_RSTGetStatus(
+ AT91PS_RSTC pRSTC)
+{
+ return (pRSTC->RSTC_RSR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_RSTIsSoftRstActive
+//* \brief Return !=0 if software reset is still not completed
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_RSTIsSoftRstActive(
+ AT91PS_RSTC pRSTC)
+{
+ return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP);
+}
+/* *****************************************************************************
+ SOFTWARE API FOR RTTC
+ ***************************************************************************** */
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_SetRTT_TimeBase()
+//* \brief Set the RTT prescaler according to the TimeBase in ms
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTSetTimeBase(
+ AT91PS_RTTC pRTTC,
+ unsigned int ms)
+{
+ if (ms > 2000)
+ return 1; // AT91C_TIME_OUT_OF_RANGE
+ pRTTC->RTTC_RTMR &= ~0xFFFF;
+ pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF);
+ return 0;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTTSetPrescaler()
+//* \brief Set the new prescaler value
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTSetPrescaler(
+ AT91PS_RTTC pRTTC,
+ unsigned int rtpres)
+{
+ pRTTC->RTTC_RTMR &= ~0xFFFF;
+ pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF);
+ return (pRTTC->RTTC_RTMR);
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTTRestart()
+//* \brief Restart the RTT prescaler
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTRestart(
+ AT91PS_RTTC pRTTC)
+{
+ pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST;
+}
+
+
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTT_SetAlarmINT()
+//* \brief Enable RTT Alarm Interrupt
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTSetAlarmINT(
+ AT91PS_RTTC pRTTC)
+{
+ pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTT_ClearAlarmINT()
+//* \brief Disable RTT Alarm Interrupt
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTClearAlarmINT(
+ AT91PS_RTTC pRTTC)
+{
+ pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTT_SetRttIncINT()
+//* \brief Enable RTT INC Interrupt
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTSetRttIncINT(
+ AT91PS_RTTC pRTTC)
+{
+ pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTT_ClearRttIncINT()
+//* \brief Disable RTT INC Interrupt
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTClearRttIncINT(
+ AT91PS_RTTC pRTTC)
+{
+ pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTT_SetAlarmValue()
+//* \brief Set RTT Alarm Value
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTSetAlarmValue(
+ AT91PS_RTTC pRTTC, unsigned int alarm)
+{
+ pRTTC->RTTC_RTAR = alarm;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTT_GetAlarmValue()
+//* \brief Get RTT Alarm Value
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTGetAlarmValue(
+ AT91PS_RTTC pRTTC)
+{
+ return(pRTTC->RTTC_RTAR);
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTTGetStatus()
+//* \brief Read the RTT status
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTGetStatus(
+ AT91PS_RTTC pRTTC)
+{
+ return(pRTTC->RTTC_RTSR);
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTT_ReadValue()
+//* \brief Read the RTT value
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTReadValue(
+ AT91PS_RTTC pRTTC)
+{
+ register volatile unsigned int val1,val2;
+ do
+ {
+ val1 = pRTTC->RTTC_RTVR;
+ val2 = pRTTC->RTTC_RTVR;
+ }
+ while(val1 != val2);
+ return(val1);
+}
+/* *****************************************************************************
+ SOFTWARE API FOR PITC
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PITInit
+//* \brief System timer init : period in
\ No newline at end of file
diff --git a/portable/GCC/ARM7_AT91SAM7S/port.c b/portable/GCC/ARM7_AT91SAM7S/port.c
index d744d5e..335f985 100644
--- a/portable/GCC/ARM7_AT91SAM7S/port.c
+++ b/portable/GCC/ARM7_AT91SAM7S/port.c
@@ -1,214 +1,211 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the ARM7 port.
- *
- * Components that can be compiled to either ARM or THUMB mode are
- * contained in this file. The ISR routines, which can only be compiled
- * to ARM mode are contained in portISR.c.
- *----------------------------------------------------------*/
-
-/* Standard includes. */
-#include <stdlib.h>
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Processor constants. */
-#include "AT91SAM7X256.h"
-
-/* Constants required to setup the task context. */
-#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
-#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
-#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 )
-
-/* Constants required to setup the tick ISR. */
-#define portENABLE_TIMER ( ( uint8_t ) 0x01 )
-#define portPRESCALE_VALUE 0x00
-#define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 )
-#define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 )
-
-/* Constants required to setup the PIT. */
-#define portPIT_CLOCK_DIVISOR ( ( uint32_t ) 16 )
-#define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_PERIOD_MS )
-
-#define portINT_LEVEL_SENSITIVE 0
-#define portPIT_ENABLE ( ( uint16_t ) 0x1 << 24 )
-#define portPIT_INT_ENABLE ( ( uint16_t ) 0x1 << 25 )
-/*-----------------------------------------------------------*/
-
-/* Setup the timer to generate the tick interrupts. */
-static void prvSetupTimerInterrupt( void );
-
-/*
- * The scheduler can only be started from ARM mode, so
- * vPortISRStartFirstSTask() is defined in portISR.c.
- */
-extern void vPortISRStartFirstTask( void );
-
-/*-----------------------------------------------------------*/
-
-/*
- * Initialise the stack of a task to look exactly as if a call to
- * portSAVE_CONTEXT had been called.
- *
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-StackType_t *pxOriginalTOS;
-
- pxOriginalTOS = pxTopOfStack;
-
- /* To ensure asserts in tasks.c don't fail, although in this case the assert
- is not really required. */
- pxTopOfStack--;
-
- /* Setup the initial stack of the task. The stack is set exactly as
- expected by the portRESTORE_CONTEXT() macro. */
-
- /* First on the stack is the return address - which in this case is the
- start of the task. The offset is added to make the return address appear
- as it would within an IRQ ISR. */
- *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
- pxTopOfStack--;
-
- *pxTopOfStack = ( StackType_t ) 0x00000000; /* R14 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
- pxTopOfStack--;
-
- /* When the task starts is will expect to find the function parameter in
- R0. */
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack--;
-
- /* The last thing onto the stack is the status register, which is set for
- system mode, with interrupts enabled. */
- *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
-
- #ifdef THUMB_INTERWORK
- {
- /* We want the task to start in thumb mode. */
- *pxTopOfStack |= portTHUMB_MODE_BIT;
- }
- #endif
-
- pxTopOfStack--;
-
- /* Some optimisation levels use the stack differently to others. This
- means the interrupt flags cannot always be stored on the stack and will
- instead be stored in a variable, which is then saved as part of the
- tasks context. */
- *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
-
- return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
- /* Start the timer that generates the tick ISR. Interrupts are disabled
- here already. */
- prvSetupTimerInterrupt();
-
- /* Start the first task. */
- vPortISRStartFirstTask();
-
- /* Should not get here! */
- return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
- /* It is unlikely that the ARM port will require this function as there
- is nothing to return to. */
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the timer 0 to generate the tick interrupts at the required frequency.
- */
-static void prvSetupTimerInterrupt( void )
-{
-AT91PS_PITC pxPIT = AT91C_BASE_PITC;
-
- /* Setup the AIC for PIT interrupts. The interrupt routine chosen depends
- on whether the preemptive or cooperative scheduler is being used. */
- #if configUSE_PREEMPTION == 0
-
- extern void ( vNonPreemptiveTick ) ( void );
- AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vNonPreemptiveTick );
-
- #else
-
- extern void ( vPreemptiveTick )( void );
- AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPreemptiveTick );
-
- #endif
-
- /* Configure the PIT period. */
- pxPIT->PITC_PIMR = portPIT_ENABLE | portPIT_INT_ENABLE | portPIT_COUNTER_VALUE;
-
- /* Enable the interrupt. Global interrupts are disables at this point so
- this is safe. */
- AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_SYS;
-}
-/*-----------------------------------------------------------*/
-
-
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM7 port.
+ *
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in this file. The ISR routines, which can only be compiled
+ * to ARM mode are contained in portISR.c.
+ *----------------------------------------------------------*/
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Processor constants. */
+#include "AT91SAM7X256.h"
+
+/* Constants required to setup the task context. */
+#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
+#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 )
+
+/* Constants required to setup the tick ISR. */
+#define portENABLE_TIMER ( ( uint8_t ) 0x01 )
+#define portPRESCALE_VALUE 0x00
+#define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 )
+#define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 )
+
+/* Constants required to setup the PIT. */
+#define portPIT_CLOCK_DIVISOR ( ( uint32_t ) 16 )
+#define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_PERIOD_MS )
+
+#define portINT_LEVEL_SENSITIVE 0
+#define portPIT_ENABLE ( ( uint16_t ) 0x1 << 24 )
+#define portPIT_INT_ENABLE ( ( uint16_t ) 0x1 << 25 )
+/*-----------------------------------------------------------*/
+
+/* Setup the timer to generate the tick interrupts. */
+static void prvSetupTimerInterrupt( void );
+
+/*
+ * The scheduler can only be started from ARM mode, so
+ * vPortISRStartFirstSTask() is defined in portISR.c.
+ */
+extern void vPortISRStartFirstTask( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been called.
+ *
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+StackType_t *pxOriginalTOS;
+
+ pxOriginalTOS = pxTopOfStack;
+
+ /* To ensure asserts in tasks.c don't fail, although in this case the assert
+ is not really required. */
+ pxTopOfStack--;
+
+ /* Setup the initial stack of the task. The stack is set exactly as
+ expected by the portRESTORE_CONTEXT() macro. */
+
+ /* First on the stack is the return address - which in this case is the
+ start of the task. The offset is added to make the return address appear
+ as it would within an IRQ ISR. */
+ *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
+ pxTopOfStack--;
+
+ *pxTopOfStack = ( StackType_t ) 0x00000000; /* R14 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+ pxTopOfStack--;
+
+ /* When the task starts is will expect to find the function parameter in
+ R0. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
+
+ /* The last thing onto the stack is the status register, which is set for
+ system mode, with interrupts enabled. */
+ *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+
+ #ifdef THUMB_INTERWORK
+ {
+ /* We want the task to start in thumb mode. */
+ *pxTopOfStack |= portTHUMB_MODE_BIT;
+ }
+ #endif
+
+ pxTopOfStack--;
+
+ /* Some optimisation levels use the stack differently to others. This
+ means the interrupt flags cannot always be stored on the stack and will
+ instead be stored in a variable, which is then saved as part of the
+ tasks context. */
+ *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
+
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ here already. */
+ prvSetupTimerInterrupt();
+
+ /* Start the first task. */
+ vPortISRStartFirstTask();
+
+ /* Should not get here! */
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+ /* It is unlikely that the ARM port will require this function as there
+ is nothing to return to. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the timer 0 to generate the tick interrupts at the required frequency.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+AT91PS_PITC pxPIT = AT91C_BASE_PITC;
+
+ /* Setup the AIC for PIT interrupts. The interrupt routine chosen depends
+ on whether the preemptive or cooperative scheduler is being used. */
+ #if configUSE_PREEMPTION == 0
+
+ extern void ( vNonPreemptiveTick ) ( void );
+ AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vNonPreemptiveTick );
+
+ #else
+
+ extern void ( vPreemptiveTick )( void );
+ AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPreemptiveTick );
+
+ #endif
+
+ /* Configure the PIT period. */
+ pxPIT->PITC_PIMR = portPIT_ENABLE | portPIT_INT_ENABLE | portPIT_COUNTER_VALUE;
+
+ /* Enable the interrupt. Global interrupts are disables at this point so
+ this is safe. */
+ AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_SYS;
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM7_AT91SAM7S/portISR.c b/portable/GCC/ARM7_AT91SAM7S/portISR.c
index 1df5b2e..61cb804 100644
--- a/portable/GCC/ARM7_AT91SAM7S/portISR.c
+++ b/portable/GCC/ARM7_AT91SAM7S/portISR.c
@@ -1,228 +1,227 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-
-/*-----------------------------------------------------------
- * Components that can be compiled to either ARM or THUMB mode are
- * contained in port.c The ISR routines, which can only be compiled
- * to ARM mode, are contained in this file.
- *----------------------------------------------------------*/
-
-/*
- Changes from V3.2.4
-
- + The assembler statements are now included in a single asm block rather
- than each line having its own asm block.
-*/
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-#include "AT91SAM7X256.h"
-
-/* Constants required to handle interrupts. */
-#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 )
-#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 )
-
-/* Constants required to handle critical sections. */
-#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
-volatile uint32_t ulCriticalNesting = 9999UL;
-
-/*-----------------------------------------------------------*/
-
-/* ISR to handle manual context switches (from a call to taskYIELD()). */
-void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
-
-/*
- * The scheduler can only be started from ARM mode, hence the inclusion of this
- * function here.
- */
-void vPortISRStartFirstTask( void );
-/*-----------------------------------------------------------*/
-
-void vPortISRStartFirstTask( void )
-{
- /* Simply start the scheduler. This is included here as it can only be
- called from ARM mode. */
- portRESTORE_CONTEXT();
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Called by portYIELD() or taskYIELD() to manually force a context switch.
- *
- * When a context switch is performed from the task level the saved task
- * context is made to look as if it occurred from within the tick ISR. This
- * way the same restore context function can be used when restoring the context
- * saved from the ISR or that saved from a call to vPortYieldProcessor.
- */
-void vPortYieldProcessor( void )
-{
- /* Within an IRQ ISR the link register has an offset from the true return
- address, but an SWI ISR does not. Add the offset manually so the same
- ISR return code can be used in both cases. */
- __asm volatile ( "ADD LR, LR, #4" );
-
- /* Perform the context switch. First save the context of the current task. */
- portSAVE_CONTEXT();
-
- /* Find the highest priority task that is ready to run. */
- vTaskSwitchContext();
-
- /* Restore the context of the new task. */
- portRESTORE_CONTEXT();
-}
-/*-----------------------------------------------------------*/
-
-/*
- * The ISR used for the scheduler tick depends on whether the cooperative or
- * the preemptive scheduler is being used.
- */
-
-#if configUSE_PREEMPTION == 0
-
- /* The cooperative scheduler requires a normal IRQ service routine to
- simply increment the system tick. */
- void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ")));
- void vNonPreemptiveTick( void )
- {
- uint32_t ulDummy;
-
- /* Increment the tick count - which may wake some tasks but as the
- preemptive scheduler is not being used any woken task is not given
- processor time no matter what its priority. */
- xTaskIncrementTick();
-
- /* Clear the PIT interrupt. */
- ulDummy = AT91C_BASE_PITC->PITC_PIVR;
-
- /* End the interrupt in the AIC. */
- AT91C_BASE_AIC->AIC_EOICR = ulDummy;
- }
-
-#else
-
- /* The preemptive scheduler is defined as "naked" as the full context is
- saved on entry as part of the context switch. */
- void vPreemptiveTick( void ) __attribute__((naked));
- void vPreemptiveTick( void )
- {
- /* Save the context of the current task. */
- portSAVE_CONTEXT();
-
- /* Increment the tick count - this may wake a task. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- /* Find the highest priority task that is ready to run. */
- vTaskSwitchContext();
- }
-
- /* End the interrupt in the AIC. */
- AT91C_BASE_AIC->AIC_EOICR = AT91C_BASE_PITC->PITC_PIVR;
-
- portRESTORE_CONTEXT();
- }
-
-#endif
-/*-----------------------------------------------------------*/
-
-/*
- * The interrupt management utilities can only be called from ARM mode. When
- * THUMB_INTERWORK is defined the utilities are defined as functions here to
- * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then
- * the utilities are defined as macros in portmacro.h - as per other ports.
- */
-void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
-void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
-
-void vPortDisableInterruptsFromThumb( void )
-{
- __asm volatile (
- "STMDB SP!, {R0} \n\t" /* Push R0. */
- "MRS R0, CPSR \n\t" /* Get CPSR. */
- "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
- "MSR CPSR, R0 \n\t" /* Write back modified value. */
- "LDMIA SP!, {R0} \n\t" /* Pop R0. */
- "BX R14" ); /* Return back to thumb. */
-}
-
-void vPortEnableInterruptsFromThumb( void )
-{
- __asm volatile (
- "STMDB SP!, {R0} \n\t" /* Push R0. */
- "MRS R0, CPSR \n\t" /* Get CPSR. */
- "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
- "MSR CPSR, R0 \n\t" /* Write back modified value. */
- "LDMIA SP!, {R0} \n\t" /* Pop R0. */
- "BX R14" ); /* Return back to thumb. */
-}
-
-
-/* The code generated by the GCC compiler uses the stack in different ways at
-different optimisation levels. The interrupt flags can therefore not always
-be saved to the stack. Instead the critical section nesting level is stored
-in a variable, which is then saved as part of the stack context. */
-void vPortEnterCritical( void )
-{
- /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
- __asm volatile (
- "STMDB SP!, {R0} \n\t" /* Push R0. */
- "MRS R0, CPSR \n\t" /* Get CPSR. */
- "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
- "MSR CPSR, R0 \n\t" /* Write back modified value. */
- "LDMIA SP!, {R0}" ); /* Pop R0. */
-
- /* Now interrupts are disabled ulCriticalNesting can be accessed
- directly. Increment ulCriticalNesting to keep a count of how many times
- portENTER_CRITICAL() has been called. */
- ulCriticalNesting++;
-}
-
-void vPortExitCritical( void )
-{
- if( ulCriticalNesting > portNO_CRITICAL_NESTING )
- {
- /* Decrement the nesting count as we are leaving a critical section. */
- ulCriticalNesting--;
-
- /* If the nesting level has reached zero then interrupts should be
- re-enabled. */
- if( ulCriticalNesting == portNO_CRITICAL_NESTING )
- {
- /* Enable interrupts as per portEXIT_CRITICAL(). */
- __asm volatile (
- "STMDB SP!, {R0} \n\t" /* Push R0. */
- "MRS R0, CPSR \n\t" /* Get CPSR. */
- "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
- "MSR CPSR, R0 \n\t" /* Write back modified value. */
- "LDMIA SP!, {R0}" ); /* Pop R0. */
- }
- }
-}
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+/*-----------------------------------------------------------
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in port.c The ISR routines, which can only be compiled
+ * to ARM mode, are contained in this file.
+ *----------------------------------------------------------*/
+
+/*
+ Changes from V3.2.4
+
+ + The assembler statements are now included in a single asm block rather
+ than each line having its own asm block.
+*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#include "AT91SAM7X256.h"
+
+/* Constants required to handle interrupts. */
+#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 )
+#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 )
+
+/* Constants required to handle critical sections. */
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
+volatile uint32_t ulCriticalNesting = 9999UL;
+
+/*-----------------------------------------------------------*/
+
+/* ISR to handle manual context switches (from a call to taskYIELD()). */
+void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
+
+/*
+ * The scheduler can only be started from ARM mode, hence the inclusion of this
+ * function here.
+ */
+void vPortISRStartFirstTask( void );
+/*-----------------------------------------------------------*/
+
+void vPortISRStartFirstTask( void )
+{
+ /* Simply start the scheduler. This is included here as it can only be
+ called from ARM mode. */
+ portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Called by portYIELD() or taskYIELD() to manually force a context switch.
+ *
+ * When a context switch is performed from the task level the saved task
+ * context is made to look as if it occurred from within the tick ISR. This
+ * way the same restore context function can be used when restoring the context
+ * saved from the ISR or that saved from a call to vPortYieldProcessor.
+ */
+void vPortYieldProcessor( void )
+{
+ /* Within an IRQ ISR the link register has an offset from the true return
+ address, but an SWI ISR does not. Add the offset manually so the same
+ ISR return code can be used in both cases. */
+ __asm volatile ( "ADD LR, LR, #4" );
+
+ /* Perform the context switch. First save the context of the current task. */
+ portSAVE_CONTEXT();
+
+ /* Find the highest priority task that is ready to run. */
+ vTaskSwitchContext();
+
+ /* Restore the context of the new task. */
+ portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * The ISR used for the scheduler tick depends on whether the cooperative or
+ * the preemptive scheduler is being used.
+ */
+
+#if configUSE_PREEMPTION == 0
+
+ /* The cooperative scheduler requires a normal IRQ service routine to
+ simply increment the system tick. */
+ void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ")));
+ void vNonPreemptiveTick( void )
+ {
+ uint32_t ulDummy;
+
+ /* Increment the tick count - which may wake some tasks but as the
+ preemptive scheduler is not being used any woken task is not given
+ processor time no matter what its priority. */
+ xTaskIncrementTick();
+
+ /* Clear the PIT interrupt. */
+ ulDummy = AT91C_BASE_PITC->PITC_PIVR;
+
+ /* End the interrupt in the AIC. */
+ AT91C_BASE_AIC->AIC_EOICR = ulDummy;
+ }
+
+#else
+
+ /* The preemptive scheduler is defined as "naked" as the full context is
+ saved on entry as part of the context switch. */
+ void vPreemptiveTick( void ) __attribute__((naked));
+ void vPreemptiveTick( void )
+ {
+ /* Save the context of the current task. */
+ portSAVE_CONTEXT();
+
+ /* Increment the tick count - this may wake a task. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ /* Find the highest priority task that is ready to run. */
+ vTaskSwitchContext();
+ }
+
+ /* End the interrupt in the AIC. */
+ AT91C_BASE_AIC->AIC_EOICR = AT91C_BASE_PITC->PITC_PIVR;
+
+ portRESTORE_CONTEXT();
+ }
+
+#endif
+/*-----------------------------------------------------------*/
+
+/*
+ * The interrupt management utilities can only be called from ARM mode. When
+ * THUMB_INTERWORK is defined the utilities are defined as functions here to
+ * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then
+ * the utilities are defined as macros in portmacro.h - as per other ports.
+ */
+void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+
+void vPortDisableInterruptsFromThumb( void )
+{
+ __asm volatile (
+ "STMDB SP!, {R0} \n\t" /* Push R0. */
+ "MRS R0, CPSR \n\t" /* Get CPSR. */
+ "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */
+ "LDMIA SP!, {R0} \n\t" /* Pop R0. */
+ "BX R14" ); /* Return back to thumb. */
+}
+
+void vPortEnableInterruptsFromThumb( void )
+{
+ __asm volatile (
+ "STMDB SP!, {R0} \n\t" /* Push R0. */
+ "MRS R0, CPSR \n\t" /* Get CPSR. */
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */
+ "LDMIA SP!, {R0} \n\t" /* Pop R0. */
+ "BX R14" ); /* Return back to thumb. */
+}
+
+
+/* The code generated by the GCC compiler uses the stack in different ways at
+different optimisation levels. The interrupt flags can therefore not always
+be saved to the stack. Instead the critical section nesting level is stored
+in a variable, which is then saved as part of the stack context. */
+void vPortEnterCritical( void )
+{
+ /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
+ __asm volatile (
+ "STMDB SP!, {R0} \n\t" /* Push R0. */
+ "MRS R0, CPSR \n\t" /* Get CPSR. */
+ "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */
+ "LDMIA SP!, {R0}" ); /* Pop R0. */
+
+ /* Now interrupts are disabled ulCriticalNesting can be accessed
+ directly. Increment ulCriticalNesting to keep a count of how many times
+ portENTER_CRITICAL() has been called. */
+ ulCriticalNesting++;
+}
+
+void vPortExitCritical( void )
+{
+ if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+ {
+ /* Decrement the nesting count as we are leaving a critical section. */
+ ulCriticalNesting--;
+
+ /* If the nesting level has reached zero then interrupts should be
+ re-enabled. */
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+ {
+ /* Enable interrupts as per portEXIT_CRITICAL(). */
+ __asm volatile (
+ "STMDB SP!, {R0} \n\t" /* Push R0. */
+ "MRS R0, CPSR \n\t" /* Get CPSR. */
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */
+ "LDMIA SP!, {R0}" ); /* Pop R0. */
+ }
+ }
+}
diff --git a/portable/GCC/ARM7_AT91SAM7S/portmacro.h b/portable/GCC/ARM7_AT91SAM7S/portmacro.h
index 23af701..4f51425 100644
--- a/portable/GCC/ARM7_AT91SAM7S/portmacro.h
+++ b/portable/GCC/ARM7_AT91SAM7S/portmacro.h
@@ -1,250 +1,249 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*
- Changes from V3.2.3
-
- + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
-
- Changes from V3.2.4
-
- + Removed the use of the %0 parameter within the assembler macros and
- replaced them with hard coded registers. This will ensure the
- assembler does not select the link register as the temp register as
- was occasionally happening previously.
-
- + The assembler statements are now included in a single asm block rather
- than each line having its own asm block.
-
- Changes from V4.5.0
-
- + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
- and replaced them with portYIELD_FROM_ISR() macro. Application code
- should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
- macros as per the V4.5.1 demo code.
-*/
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT short
-#define portSTACK_TYPE uint32_t
-#define portBASE_TYPE portLONG
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
-#else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH ( -1 )
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT 8
-#define portNOP() __asm volatile ( "NOP" );
-/*-----------------------------------------------------------*/
-
-
-/* Scheduler utilities. */
-
-/*
- * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR
- * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but
- * are included here for efficiency. An attempt to call one from
- * THUMB mode code will result in a compile time error.
- */
-
-#define portRESTORE_CONTEXT() \
-{ \
-extern volatile void * volatile pxCurrentTCB; \
-extern volatile uint32_t ulCriticalNesting; \
- \
- /* Set the LR to the task stack. */ \
- __asm volatile ( \
- "LDR R0, =pxCurrentTCB \n\t" \
- "LDR R0, [R0] \n\t" \
- "LDR LR, [R0] \n\t" \
- \
- /* The critical nesting depth is the first item on the stack. */ \
- /* Load it into the ulCriticalNesting variable. */ \
- "LDR R0, =ulCriticalNesting \n\t" \
- "LDMFD LR!, {R1} \n\t" \
- "STR R1, [R0] \n\t" \
- \
- /* Get the SPSR from the stack. */ \
- "LDMFD LR!, {R0} \n\t" \
- "MSR SPSR, R0 \n\t" \
- \
- /* Restore all system mode registers for the task. */ \
- "LDMFD LR, {R0-R14}^ \n\t" \
- "NOP \n\t" \
- \
- /* Restore the return address. */ \
- "LDR LR, [LR, #+60] \n\t" \
- \
- /* And return - correcting the offset in the LR to obtain the */ \
- /* correct address. */ \
- "SUBS PC, LR, #4 \n\t" \
- ); \
- ( void ) ulCriticalNesting; \
- ( void ) pxCurrentTCB; \
-}
-/*-----------------------------------------------------------*/
-
-#define portSAVE_CONTEXT() \
-{ \
-extern volatile void * volatile pxCurrentTCB; \
-extern volatile uint32_t ulCriticalNesting; \
- \
- /* Push R0 as we are going to use the register. */ \
- __asm volatile ( \
- "STMDB SP!, {R0} \n\t" \
- \
- /* Set R0 to point to the task stack pointer. */ \
- "STMDB SP,{SP}^ \n\t" \
- "NOP \n\t" \
- "SUB SP, SP, #4 \n\t" \
- "LDMIA SP!,{R0} \n\t" \
- \
- /* Push the return address onto the stack. */ \
- "STMDB R0!, {LR} \n\t" \
- \
- /* Now we have saved LR we can use it instead of R0. */ \
- "MOV LR, R0 \n\t" \
- \
- /* Pop R0 so we can save it onto the system mode stack. */ \
- "LDMIA SP!, {R0} \n\t" \
- \
- /* Push all the system mode registers onto the task stack. */ \
- "STMDB LR,{R0-LR}^ \n\t" \
- "NOP \n\t" \
- "SUB LR, LR, #60 \n\t" \
- \
- /* Push the SPSR onto the task stack. */ \
- "MRS R0, SPSR \n\t" \
- "STMDB LR!, {R0} \n\t" \
- \
- "LDR R0, =ulCriticalNesting \n\t" \
- "LDR R0, [R0] \n\t" \
- "STMDB LR!, {R0} \n\t" \
- \
- /* Store the new top of stack for the task. */ \
- "LDR R0, =pxCurrentTCB \n\t" \
- "LDR R0, [R0] \n\t" \
- "STR LR, [R0] \n\t" \
- ); \
- ( void ) ulCriticalNesting; \
- ( void ) pxCurrentTCB; \
-}
-
-
-#define portYIELD_FROM_ISR() vTaskSwitchContext()
-#define portYIELD() __asm volatile ( "SWI 0" )
-/*-----------------------------------------------------------*/
-
-
-/* Critical section management. */
-
-/*
- * The interrupt management utilities can only be called from ARM mode. When
- * THUMB_INTERWORK is defined the utilities are defined as functions in
- * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not
- * defined then the utilities are defined as macros here - as per other ports.
- */
-
-#ifdef THUMB_INTERWORK
-
- extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
- extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
-
- #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb()
- #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb()
-
-#else
-
- #define portDISABLE_INTERRUPTS() \
- __asm volatile ( \
- "STMDB SP!, {R0} \n\t" /* Push R0. */ \
- "MRS R0, CPSR \n\t" /* Get CPSR. */ \
- "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \
- "MSR CPSR, R0 \n\t" /* Write back modified value. */ \
- "LDMIA SP!, {R0} " ) /* Pop R0. */
-
- #define portENABLE_INTERRUPTS() \
- __asm volatile ( \
- "STMDB SP!, {R0} \n\t" /* Push R0. */ \
- "MRS R0, CPSR \n\t" /* Get CPSR. */ \
- "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \
- "MSR CPSR, R0 \n\t" /* Write back modified value. */ \
- "LDMIA SP!, {R0} " ) /* Pop R0. */
-
-#endif /* THUMB_INTERWORK */
-
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-
-#define portENTER_CRITICAL() vPortEnterCritical();
-#define portEXIT_CRITICAL() vPortExitCritical();
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*
+ Changes from V3.2.3
+
+ + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
+
+ Changes from V3.2.4
+
+ + Removed the use of the %0 parameter within the assembler macros and
+ replaced them with hard coded registers. This will ensure the
+ assembler does not select the link register as the temp register as
+ was occasionally happening previously.
+
+ + The assembler statements are now included in a single asm block rather
+ than each line having its own asm block.
+
+ Changes from V4.5.0
+
+ + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
+ and replaced them with portYIELD_FROM_ISR() macro. Application code
+ should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
+ macros as per the V4.5.1 demo code.
+*/
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE portLONG
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portNOP() __asm volatile ( "NOP" );
+/*-----------------------------------------------------------*/
+
+
+/* Scheduler utilities. */
+
+/*
+ * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR
+ * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but
+ * are included here for efficiency. An attempt to call one from
+ * THUMB mode code will result in a compile time error.
+ */
+
+#define portRESTORE_CONTEXT() \
+{ \
+extern volatile void * volatile pxCurrentTCB; \
+extern volatile uint32_t ulCriticalNesting; \
+ \
+ /* Set the LR to the task stack. */ \
+ __asm volatile ( \
+ "LDR R0, =pxCurrentTCB \n\t" \
+ "LDR R0, [R0] \n\t" \
+ "LDR LR, [R0] \n\t" \
+ \
+ /* The critical nesting depth is the first item on the stack. */ \
+ /* Load it into the ulCriticalNesting variable. */ \
+ "LDR R0, =ulCriticalNesting \n\t" \
+ "LDMFD LR!, {R1} \n\t" \
+ "STR R1, [R0] \n\t" \
+ \
+ /* Get the SPSR from the stack. */ \
+ "LDMFD LR!, {R0} \n\t" \
+ "MSR SPSR, R0 \n\t" \
+ \
+ /* Restore all system mode registers for the task. */ \
+ "LDMFD LR, {R0-R14}^ \n\t" \
+ "NOP \n\t" \
+ \
+ /* Restore the return address. */ \
+ "LDR LR, [LR, #+60] \n\t" \
+ \
+ /* And return - correcting the offset in the LR to obtain the */ \
+ /* correct address. */ \
+ "SUBS PC, LR, #4 \n\t" \
+ ); \
+ ( void ) ulCriticalNesting; \
+ ( void ) pxCurrentTCB; \
+}
+/*-----------------------------------------------------------*/
+
+#define portSAVE_CONTEXT() \
+{ \
+extern volatile void * volatile pxCurrentTCB; \
+extern volatile uint32_t ulCriticalNesting; \
+ \
+ /* Push R0 as we are going to use the register. */ \
+ __asm volatile ( \
+ "STMDB SP!, {R0} \n\t" \
+ \
+ /* Set R0 to point to the task stack pointer. */ \
+ "STMDB SP,{SP}^ \n\t" \
+ "NOP \n\t" \
+ "SUB SP, SP, #4 \n\t" \
+ "LDMIA SP!,{R0} \n\t" \
+ \
+ /* Push the return address onto the stack. */ \
+ "STMDB R0!, {LR} \n\t" \
+ \
+ /* Now we have saved LR we can use it instead of R0. */ \
+ "MOV LR, R0 \n\t" \
+ \
+ /* Pop R0 so we can save it onto the system mode stack. */ \
+ "LDMIA SP!, {R0} \n\t" \
+ \
+ /* Push all the system mode registers onto the task stack. */ \
+ "STMDB LR,{R0-LR}^ \n\t" \
+ "NOP \n\t" \
+ "SUB LR, LR, #60 \n\t" \
+ \
+ /* Push the SPSR onto the task stack. */ \
+ "MRS R0, SPSR \n\t" \
+ "STMDB LR!, {R0} \n\t" \
+ \
+ "LDR R0, =ulCriticalNesting \n\t" \
+ "LDR R0, [R0] \n\t" \
+ "STMDB LR!, {R0} \n\t" \
+ \
+ /* Store the new top of stack for the task. */ \
+ "LDR R0, =pxCurrentTCB \n\t" \
+ "LDR R0, [R0] \n\t" \
+ "STR LR, [R0] \n\t" \
+ ); \
+ ( void ) ulCriticalNesting; \
+ ( void ) pxCurrentTCB; \
+}
+
+
+#define portYIELD_FROM_ISR() vTaskSwitchContext()
+#define portYIELD() __asm volatile ( "SWI 0" )
+/*-----------------------------------------------------------*/
+
+
+/* Critical section management. */
+
+/*
+ * The interrupt management utilities can only be called from ARM mode. When
+ * THUMB_INTERWORK is defined the utilities are defined as functions in
+ * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not
+ * defined then the utilities are defined as macros here - as per other ports.
+ */
+
+#ifdef THUMB_INTERWORK
+
+ extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+ extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+
+ #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb()
+ #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb()
+
+#else
+
+ #define portDISABLE_INTERRUPTS() \
+ __asm volatile ( \
+ "STMDB SP!, {R0} \n\t" /* Push R0. */ \
+ "MRS R0, CPSR \n\t" /* Get CPSR. */ \
+ "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */ \
+ "LDMIA SP!, {R0} " ) /* Pop R0. */
+
+ #define portENABLE_INTERRUPTS() \
+ __asm volatile ( \
+ "STMDB SP!, {R0} \n\t" /* Push R0. */ \
+ "MRS R0, CPSR \n\t" /* Get CPSR. */ \
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */ \
+ "LDMIA SP!, {R0} " ) /* Pop R0. */
+
+#endif /* THUMB_INTERWORK */
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portENTER_CRITICAL() vPortEnterCritical();
+#define portEXIT_CRITICAL() vPortExitCritical();
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/portable/GCC/ARM7_LPC2000/port.c b/portable/GCC/ARM7_LPC2000/port.c
index d5dc4b1..87a8fd3 100644
--- a/portable/GCC/ARM7_LPC2000/port.c
+++ b/portable/GCC/ARM7_LPC2000/port.c
@@ -1,222 +1,219 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the ARM7 port.
- *
- * Components that can be compiled to either ARM or THUMB mode are
- * contained in this file. The ISR routines, which can only be compiled
- * to ARM mode are contained in portISR.c.
- *----------------------------------------------------------*/
-
-
-/* Standard includes. */
-#include <stdlib.h>
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Constants required to setup the task context. */
-#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
-#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
-#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 )
-
-/* Constants required to setup the tick ISR. */
-#define portENABLE_TIMER ( ( uint8_t ) 0x01 )
-#define portPRESCALE_VALUE 0x00
-#define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 )
-#define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 )
-
-/* Constants required to setup the VIC for the tick ISR. */
-#define portTIMER_VIC_CHANNEL ( ( uint32_t ) 0x0004 )
-#define portTIMER_VIC_CHANNEL_BIT ( ( uint32_t ) 0x0010 )
-#define portTIMER_VIC_ENABLE ( ( uint32_t ) 0x0020 )
-
-/*-----------------------------------------------------------*/
-
-/* Setup the timer to generate the tick interrupts. */
-static void prvSetupTimerInterrupt( void );
-
-/*
- * The scheduler can only be started from ARM mode, so
- * vPortISRStartFirstSTask() is defined in portISR.c.
- */
-extern void vPortISRStartFirstTask( void );
-
-/*-----------------------------------------------------------*/
-
-/*
- * Initialise the stack of a task to look exactly as if a call to
- * portSAVE_CONTEXT had been called.
- *
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-StackType_t *pxOriginalTOS;
-
- pxOriginalTOS = pxTopOfStack;
-
- /* To ensure asserts in tasks.c don't fail, although in this case the assert
- is not really required. */
- pxTopOfStack--;
-
- /* Setup the initial stack of the task. The stack is set exactly as
- expected by the portRESTORE_CONTEXT() macro. */
-
- /* First on the stack is the return address - which in this case is the
- start of the task. The offset is added to make the return address appear
- as it would within an IRQ ISR. */
- *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
- pxTopOfStack--;
-
- *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
- pxTopOfStack--;
-
- /* When the task starts is will expect to find the function parameter in
- R0. */
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack--;
-
- /* The last thing onto the stack is the status register, which is set for
- system mode, with interrupts enabled. */
- *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
-
- if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00 )
- {
- /* We want the task to start in thumb mode. */
- *pxTopOfStack |= portTHUMB_MODE_BIT;
- }
-
- pxTopOfStack--;
-
- /* Some optimisation levels use the stack differently to others. This
- means the interrupt flags cannot always be stored on the stack and will
- instead be stored in a variable, which is then saved as part of the
- tasks context. */
- *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
-
- return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
- /* Start the timer that generates the tick ISR. Interrupts are disabled
- here already. */
- prvSetupTimerInterrupt();
-
- /* Start the first task. */
- vPortISRStartFirstTask();
-
- /* Should not get here! */
- return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
- /* It is unlikely that the ARM port will require this function as there
- is nothing to return to. */
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the timer 0 to generate the tick interrupts at the required frequency.
- */
-static void prvSetupTimerInterrupt( void )
-{
-uint32_t ulCompareMatch;
-extern void ( vTickISR )( void );
-
- /* A 1ms tick does not require the use of the timer prescale. This is
- defaulted to zero but can be used if necessary. */
- T0_PR = portPRESCALE_VALUE;
-
- /* Calculate the match value required for our wanted tick rate. */
- ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
-
- /* Protect against divide by zero. Using an if() statement still results
- in a warning - hence the #if. */
- #if portPRESCALE_VALUE != 0
- {
- ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
- }
- #endif
- T0_MR0 = ulCompareMatch;
-
- /* Generate tick with timer 0 compare match. */
- T0_MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH;
-
- /* Setup the VIC for the timer. */
- VICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT );
- VICIntEnable |= portTIMER_VIC_CHANNEL_BIT;
-
- /* The ISR installed depends on whether the preemptive or cooperative
- scheduler is being used. */
-
- VICVectAddr0 = ( int32_t ) vTickISR;
- VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE;
-
- /* Start the timer - interrupts are disabled when this function is called
- so it is okay to do this here. */
- T0_TCR = portENABLE_TIMER;
-}
-/*-----------------------------------------------------------*/
-
-
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM7 port.
+ *
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in this file. The ISR routines, which can only be compiled
+ * to ARM mode are contained in portISR.c.
+ *----------------------------------------------------------*/
+
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to setup the task context. */
+#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
+#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 )
+
+/* Constants required to setup the tick ISR. */
+#define portENABLE_TIMER ( ( uint8_t ) 0x01 )
+#define portPRESCALE_VALUE 0x00
+#define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 )
+#define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 )
+
+/* Constants required to setup the VIC for the tick ISR. */
+#define portTIMER_VIC_CHANNEL ( ( uint32_t ) 0x0004 )
+#define portTIMER_VIC_CHANNEL_BIT ( ( uint32_t ) 0x0010 )
+#define portTIMER_VIC_ENABLE ( ( uint32_t ) 0x0020 )
+
+/*-----------------------------------------------------------*/
+
+/* Setup the timer to generate the tick interrupts. */
+static void prvSetupTimerInterrupt( void );
+
+/*
+ * The scheduler can only be started from ARM mode, so
+ * vPortISRStartFirstSTask() is defined in portISR.c.
+ */
+extern void vPortISRStartFirstTask( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been called.
+ *
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+StackType_t *pxOriginalTOS;
+
+ pxOriginalTOS = pxTopOfStack;
+
+ /* To ensure asserts in tasks.c don't fail, although in this case the assert
+ is not really required. */
+ pxTopOfStack--;
+
+ /* Setup the initial stack of the task. The stack is set exactly as
+ expected by the portRESTORE_CONTEXT() macro. */
+
+ /* First on the stack is the return address - which in this case is the
+ start of the task. The offset is added to make the return address appear
+ as it would within an IRQ ISR. */
+ *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
+ pxTopOfStack--;
+
+ *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+ pxTopOfStack--;
+
+ /* When the task starts is will expect to find the function parameter in
+ R0. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
+
+ /* The last thing onto the stack is the status register, which is set for
+ system mode, with interrupts enabled. */
+ *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+
+ if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00 )
+ {
+ /* We want the task to start in thumb mode. */
+ *pxTopOfStack |= portTHUMB_MODE_BIT;
+ }
+
+ pxTopOfStack--;
+
+ /* Some optimisation levels use the stack differently to others. This
+ means the interrupt flags cannot always be stored on the stack and will
+ instead be stored in a variable, which is then saved as part of the
+ tasks context. */
+ *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
+
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ here already. */
+ prvSetupTimerInterrupt();
+
+ /* Start the first task. */
+ vPortISRStartFirstTask();
+
+ /* Should not get here! */
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+ /* It is unlikely that the ARM port will require this function as there
+ is nothing to return to. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the timer 0 to generate the tick interrupts at the required frequency.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+uint32_t ulCompareMatch;
+extern void ( vTickISR )( void );
+
+ /* A 1ms tick does not require the use of the timer prescale. This is
+ defaulted to zero but can be used if necessary. */
+ T0_PR = portPRESCALE_VALUE;
+
+ /* Calculate the match value required for our wanted tick rate. */
+ ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+
+ /* Protect against divide by zero. Using an if() statement still results
+ in a warning - hence the #if. */
+ #if portPRESCALE_VALUE != 0
+ {
+ ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
+ }
+ #endif
+ T0_MR0 = ulCompareMatch;
+
+ /* Generate tick with timer 0 compare match. */
+ T0_MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH;
+
+ /* Setup the VIC for the timer. */
+ VICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT );
+ VICIntEnable |= portTIMER_VIC_CHANNEL_BIT;
+
+ /* The ISR installed depends on whether the preemptive or cooperative
+ scheduler is being used. */
+
+ VICVectAddr0 = ( int32_t ) vTickISR;
+ VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE;
+
+ /* Start the timer - interrupts are disabled when this function is called
+ so it is okay to do this here. */
+ T0_TCR = portENABLE_TIMER;
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM7_LPC2000/portISR.c b/portable/GCC/ARM7_LPC2000/portISR.c
index 67dd2c2..f66b4fa 100644
--- a/portable/GCC/ARM7_LPC2000/portISR.c
+++ b/portable/GCC/ARM7_LPC2000/portISR.c
@@ -1,216 +1,216 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-
-/*-----------------------------------------------------------
- * Components that can be compiled to either ARM or THUMB mode are
- * contained in port.c The ISR routines, which can only be compiled
- * to ARM mode, are contained in this file.
- *----------------------------------------------------------*/
-
-/*
- Changes from V2.5.2
-
- + The critical section management functions have been changed. These no
- longer modify the stack and are safe to use at all optimisation levels.
- The functions are now also the same for both ARM and THUMB modes.
-
- Changes from V2.6.0
-
- + Removed the 'static' from the definition of vNonPreemptiveTick() to
- allow the demo to link when using the cooperative scheduler.
-
- Changes from V3.2.4
-
- + The assembler statements are now included in a single asm block rather
- than each line having its own asm block.
-*/
-
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-
-/* Constants required to handle interrupts. */
-#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 )
-#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 )
-
-/* Constants required to handle critical sections. */
-#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
-volatile uint32_t ulCriticalNesting = 9999UL;
-
-/*-----------------------------------------------------------*/
-
-/* ISR to handle manual context switches (from a call to taskYIELD()). */
-void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
-
-/*
- * The scheduler can only be started from ARM mode, hence the inclusion of this
- * function here.
- */
-void vPortISRStartFirstTask( void );
-/*-----------------------------------------------------------*/
-
-void vPortISRStartFirstTask( void )
-{
- /* Simply start the scheduler. This is included here as it can only be
- called from ARM mode. */
- portRESTORE_CONTEXT();
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Called by portYIELD() or taskYIELD() to manually force a context switch.
- *
- * When a context switch is performed from the task level the saved task
- * context is made to look as if it occurred from within the tick ISR. This
- * way the same restore context function can be used when restoring the context
- * saved from the ISR or that saved from a call to vPortYieldProcessor.
- */
-void vPortYieldProcessor( void )
-{
- /* Within an IRQ ISR the link register has an offset from the true return
- address, but an SWI ISR does not. Add the offset manually so the same
- ISR return code can be used in both cases. */
- __asm volatile ( "ADD LR, LR, #4" );
-
- /* Perform the context switch. First save the context of the current task. */
- portSAVE_CONTEXT();
-
- /* Find the highest priority task that is ready to run. */
- __asm volatile ( "bl vTaskSwitchContext" );
-
- /* Restore the context of the new task. */
- portRESTORE_CONTEXT();
-}
-/*-----------------------------------------------------------*/
-
-/*
- * The ISR used for the scheduler tick.
- */
-void vTickISR( void ) __attribute__((naked));
-void vTickISR( void )
-{
- /* Save the context of the interrupted task. */
- portSAVE_CONTEXT();
-
- /* Increment the RTOS tick count, then look for the highest priority
- task that is ready to run. */
- __asm volatile
- (
- " bl xTaskIncrementTick \t\n" \
- " cmp r0, #0 \t\n" \
- " beq SkipContextSwitch \t\n" \
- " bl vTaskSwitchContext \t\n" \
- "SkipContextSwitch: \t\n"
- );
-
- /* Ready for the next interrupt. */
- T0_IR = portTIMER_MATCH_ISR_BIT;
- VICVectAddr = portCLEAR_VIC_INTERRUPT;
-
- /* Restore the context of the new task. */
- portRESTORE_CONTEXT();
-}
-/*-----------------------------------------------------------*/
-
-/*
- * The interrupt management utilities can only be called from ARM mode. When
- * THUMB_INTERWORK is defined the utilities are defined as functions here to
- * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then
- * the utilities are defined as macros in portmacro.h - as per other ports.
- */
-#ifdef THUMB_INTERWORK
-
- void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
- void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
-
- void vPortDisableInterruptsFromThumb( void )
- {
- __asm volatile (
- "STMDB SP!, {R0} \n\t" /* Push R0. */
- "MRS R0, CPSR \n\t" /* Get CPSR. */
- "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
- "MSR CPSR, R0 \n\t" /* Write back modified value. */
- "LDMIA SP!, {R0} \n\t" /* Pop R0. */
- "BX R14" ); /* Return back to thumb. */
- }
-
- void vPortEnableInterruptsFromThumb( void )
- {
- __asm volatile (
- "STMDB SP!, {R0} \n\t" /* Push R0. */
- "MRS R0, CPSR \n\t" /* Get CPSR. */
- "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
- "MSR CPSR, R0 \n\t" /* Write back modified value. */
- "LDMIA SP!, {R0} \n\t" /* Pop R0. */
- "BX R14" ); /* Return back to thumb. */
- }
-
-#endif /* THUMB_INTERWORK */
-
-/* The code generated by the GCC compiler uses the stack in different ways at
-different optimisation levels. The interrupt flags can therefore not always
-be saved to the stack. Instead the critical section nesting level is stored
-in a variable, which is then saved as part of the stack context. */
-void vPortEnterCritical( void )
-{
- /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
- __asm volatile (
- "STMDB SP!, {R0} \n\t" /* Push R0. */
- "MRS R0, CPSR \n\t" /* Get CPSR. */
- "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
- "MSR CPSR, R0 \n\t" /* Write back modified value. */
- "LDMIA SP!, {R0}" ); /* Pop R0. */
-
- /* Now interrupts are disabled ulCriticalNesting can be accessed
- directly. Increment ulCriticalNesting to keep a count of how many times
- portENTER_CRITICAL() has been called. */
- ulCriticalNesting++;
-}
-
-void vPortExitCritical( void )
-{
- if( ulCriticalNesting > portNO_CRITICAL_NESTING )
- {
- /* Decrement the nesting count as we are leaving a critical section. */
- ulCriticalNesting--;
-
- /* If the nesting level has reached zero then interrupts should be
- re-enabled. */
- if( ulCriticalNesting == portNO_CRITICAL_NESTING )
- {
- /* Enable interrupts as per portEXIT_CRITICAL(). */
- __asm volatile (
- "STMDB SP!, {R0} \n\t" /* Push R0. */
- "MRS R0, CPSR \n\t" /* Get CPSR. */
- "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
- "MSR CPSR, R0 \n\t" /* Write back modified value. */
- "LDMIA SP!, {R0}" ); /* Pop R0. */
- }
- }
-}
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+/*-----------------------------------------------------------
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in port.c The ISR routines, which can only be compiled
+ * to ARM mode, are contained in this file.
+ *----------------------------------------------------------*/
+
+/*
+ Changes from V2.5.2
+
+ + The critical section management functions have been changed. These no
+ longer modify the stack and are safe to use at all optimisation levels.
+ The functions are now also the same for both ARM and THUMB modes.
+
+ Changes from V2.6.0
+
+ + Removed the 'static' from the definition of vNonPreemptiveTick() to
+ allow the demo to link when using the cooperative scheduler.
+
+ Changes from V3.2.4
+
+ + The assembler statements are now included in a single asm block rather
+ than each line having its own asm block.
+*/
+
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* Constants required to handle interrupts. */
+#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 )
+#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 )
+
+/* Constants required to handle critical sections. */
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
+volatile uint32_t ulCriticalNesting = 9999UL;
+
+/*-----------------------------------------------------------*/
+
+/* ISR to handle manual context switches (from a call to taskYIELD()). */
+void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
+
+/*
+ * The scheduler can only be started from ARM mode, hence the inclusion of this
+ * function here.
+ */
+void vPortISRStartFirstTask( void );
+/*-----------------------------------------------------------*/
+
+void vPortISRStartFirstTask( void )
+{
+ /* Simply start the scheduler. This is included here as it can only be
+ called from ARM mode. */
+ portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Called by portYIELD() or taskYIELD() to manually force a context switch.
+ *
+ * When a context switch is performed from the task level the saved task
+ * context is made to look as if it occurred from within the tick ISR. This
+ * way the same restore context function can be used when restoring the context
+ * saved from the ISR or that saved from a call to vPortYieldProcessor.
+ */
+void vPortYieldProcessor( void )
+{
+ /* Within an IRQ ISR the link register has an offset from the true return
+ address, but an SWI ISR does not. Add the offset manually so the same
+ ISR return code can be used in both cases. */
+ __asm volatile ( "ADD LR, LR, #4" );
+
+ /* Perform the context switch. First save the context of the current task. */
+ portSAVE_CONTEXT();
+
+ /* Find the highest priority task that is ready to run. */
+ __asm volatile ( "bl vTaskSwitchContext" );
+
+ /* Restore the context of the new task. */
+ portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * The ISR used for the scheduler tick.
+ */
+void vTickISR( void ) __attribute__((naked));
+void vTickISR( void )
+{
+ /* Save the context of the interrupted task. */
+ portSAVE_CONTEXT();
+
+ /* Increment the RTOS tick count, then look for the highest priority
+ task that is ready to run. */
+ __asm volatile
+ (
+ " bl xTaskIncrementTick \t\n" \
+ " cmp r0, #0 \t\n" \
+ " beq SkipContextSwitch \t\n" \
+ " bl vTaskSwitchContext \t\n" \
+ "SkipContextSwitch: \t\n"
+ );
+
+ /* Ready for the next interrupt. */
+ T0_IR = portTIMER_MATCH_ISR_BIT;
+ VICVectAddr = portCLEAR_VIC_INTERRUPT;
+
+ /* Restore the context of the new task. */
+ portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * The interrupt management utilities can only be called from ARM mode. When
+ * THUMB_INTERWORK is defined the utilities are defined as functions here to
+ * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then
+ * the utilities are defined as macros in portmacro.h - as per other ports.
+ */
+#ifdef THUMB_INTERWORK
+
+ void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+ void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+
+ void vPortDisableInterruptsFromThumb( void )
+ {
+ __asm volatile (
+ "STMDB SP!, {R0} \n\t" /* Push R0. */
+ "MRS R0, CPSR \n\t" /* Get CPSR. */
+ "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */
+ "LDMIA SP!, {R0} \n\t" /* Pop R0. */
+ "BX R14" ); /* Return back to thumb. */
+ }
+
+ void vPortEnableInterruptsFromThumb( void )
+ {
+ __asm volatile (
+ "STMDB SP!, {R0} \n\t" /* Push R0. */
+ "MRS R0, CPSR \n\t" /* Get CPSR. */
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */
+ "LDMIA SP!, {R0} \n\t" /* Pop R0. */
+ "BX R14" ); /* Return back to thumb. */
+ }
+
+#endif /* THUMB_INTERWORK */
+
+/* The code generated by the GCC compiler uses the stack in different ways at
+different optimisation levels. The interrupt flags can therefore not always
+be saved to the stack. Instead the critical section nesting level is stored
+in a variable, which is then saved as part of the stack context. */
+void vPortEnterCritical( void )
+{
+ /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
+ __asm volatile (
+ "STMDB SP!, {R0} \n\t" /* Push R0. */
+ "MRS R0, CPSR \n\t" /* Get CPSR. */
+ "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */
+ "LDMIA SP!, {R0}" ); /* Pop R0. */
+
+ /* Now interrupts are disabled ulCriticalNesting can be accessed
+ directly. Increment ulCriticalNesting to keep a count of how many times
+ portENTER_CRITICAL() has been called. */
+ ulCriticalNesting++;
+}
+
+void vPortExitCritical( void )
+{
+ if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+ {
+ /* Decrement the nesting count as we are leaving a critical section. */
+ ulCriticalNesting--;
+
+ /* If the nesting level has reached zero then interrupts should be
+ re-enabled. */
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+ {
+ /* Enable interrupts as per portEXIT_CRITICAL(). */
+ __asm volatile (
+ "STMDB SP!, {R0} \n\t" /* Push R0. */
+ "MRS R0, CPSR \n\t" /* Get CPSR. */
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */
+ "LDMIA SP!, {R0}" ); /* Pop R0. */
+ }
+ }
+}
diff --git a/portable/GCC/ARM7_LPC2000/portmacro.h b/portable/GCC/ARM7_LPC2000/portmacro.h
index cb4cb64..8402996 100644
--- a/portable/GCC/ARM7_LPC2000/portmacro.h
+++ b/portable/GCC/ARM7_LPC2000/portmacro.h
@@ -1,227 +1,226 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT short
-#define portSTACK_TYPE uint32_t
-#define portBASE_TYPE portLONG
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
-#else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH ( -1 )
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT 8
-#define portNOP() __asm volatile ( "NOP" );
-/*-----------------------------------------------------------*/
-
-
-/* Scheduler utilities. */
-
-/*
- * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR
- * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but
- * are included here for efficiency. An attempt to call one from
- * THUMB mode code will result in a compile time error.
- */
-
-#define portRESTORE_CONTEXT() \
-{ \
-extern volatile void * volatile pxCurrentTCB; \
-extern volatile uint32_t ulCriticalNesting; \
- \
- /* Set the LR to the task stack. */ \
- __asm volatile ( \
- "LDR R0, =pxCurrentTCB \n\t" \
- "LDR R0, [R0] \n\t" \
- "LDR LR, [R0] \n\t" \
- \
- /* The critical nesting depth is the first item on the stack. */ \
- /* Load it into the ulCriticalNesting variable. */ \
- "LDR R0, =ulCriticalNesting \n\t" \
- "LDMFD LR!, {R1} \n\t" \
- "STR R1, [R0] \n\t" \
- \
- /* Get the SPSR from the stack. */ \
- "LDMFD LR!, {R0} \n\t" \
- "MSR SPSR, R0 \n\t" \
- \
- /* Restore all system mode registers for the task. */ \
- "LDMFD LR, {R0-R14}^ \n\t" \
- "NOP \n\t" \
- \
- /* Restore the return address. */ \
- "LDR LR, [LR, #+60] \n\t" \
- \
- /* And return - correcting the offset in the LR to obtain the */ \
- /* correct address. */ \
- "SUBS PC, LR, #4 \n\t" \
- ); \
- ( void ) ulCriticalNesting; \
- ( void ) pxCurrentTCB; \
-}
-/*-----------------------------------------------------------*/
-
-#define portSAVE_CONTEXT() \
-{ \
-extern volatile void * volatile pxCurrentTCB; \
-extern volatile uint32_t ulCriticalNesting; \
- \
- /* Push R0 as we are going to use the register. */ \
- __asm volatile ( \
- "STMDB SP!, {R0} \n\t" \
- \
- /* Set R0 to point to the task stack pointer. */ \
- "STMDB SP,{SP}^ \n\t" \
- "NOP \n\t" \
- "SUB SP, SP, #4 \n\t" \
- "LDMIA SP!,{R0} \n\t" \
- \
- /* Push the return address onto the stack. */ \
- "STMDB R0!, {LR} \n\t" \
- \
- /* Now we have saved LR we can use it instead of R0. */ \
- "MOV LR, R0 \n\t" \
- \
- /* Pop R0 so we can save it onto the system mode stack. */ \
- "LDMIA SP!, {R0} \n\t" \
- \
- /* Push all the system mode registers onto the task stack. */ \
- "STMDB LR,{R0-LR}^ \n\t" \
- "NOP \n\t" \
- "SUB LR, LR, #60 \n\t" \
- \
- /* Push the SPSR onto the task stack. */ \
- "MRS R0, SPSR \n\t" \
- "STMDB LR!, {R0} \n\t" \
- \
- "LDR R0, =ulCriticalNesting \n\t" \
- "LDR R0, [R0] \n\t" \
- "STMDB LR!, {R0} \n\t" \
- \
- /* Store the new top of stack for the task. */ \
- "LDR R0, =pxCurrentTCB \n\t" \
- "LDR R0, [R0] \n\t" \
- "STR LR, [R0] \n\t" \
- ); \
- ( void ) ulCriticalNesting; \
- ( void ) pxCurrentTCB; \
-}
-
-extern void vTaskSwitchContext( void );
-#define portYIELD_FROM_ISR() vTaskSwitchContext()
-#define portYIELD() __asm volatile ( "SWI 0" )
-/*-----------------------------------------------------------*/
-
-
-/* Critical section management. */
-
-/*
- * The interrupt management utilities can only be called from ARM mode. When
- * THUMB_INTERWORK is defined the utilities are defined as functions in
- * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not
- * defined then the utilities are defined as macros here - as per other ports.
- */
-
-#ifdef THUMB_INTERWORK
-
- extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
- extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
-
- #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb()
- #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb()
-
-#else
-
- #define portDISABLE_INTERRUPTS() \
- __asm volatile ( \
- "STMDB SP!, {R0} \n\t" /* Push R0. */ \
- "MRS R0, CPSR \n\t" /* Get CPSR. */ \
- "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \
- "MSR CPSR, R0 \n\t" /* Write back modified value. */ \
- "LDMIA SP!, {R0} " ) /* Pop R0. */
-
- #define portENABLE_INTERRUPTS() \
- __asm volatile ( \
- "STMDB SP!, {R0} \n\t" /* Push R0. */ \
- "MRS R0, CPSR \n\t" /* Get CPSR. */ \
- "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \
- "MSR CPSR, R0 \n\t" /* Write back modified value. */ \
- "LDMIA SP!, {R0} " ) /* Pop R0. */
-
-#endif /* THUMB_INTERWORK */
-
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-
-#define portENTER_CRITICAL() vPortEnterCritical();
-#define portEXIT_CRITICAL() vPortExitCritical();
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE portLONG
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portNOP() __asm volatile ( "NOP" );
+/*-----------------------------------------------------------*/
+
+
+/* Scheduler utilities. */
+
+/*
+ * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR
+ * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but
+ * are included here for efficiency. An attempt to call one from
+ * THUMB mode code will result in a compile time error.
+ */
+
+#define portRESTORE_CONTEXT() \
+{ \
+extern volatile void * volatile pxCurrentTCB; \
+extern volatile uint32_t ulCriticalNesting; \
+ \
+ /* Set the LR to the task stack. */ \
+ __asm volatile ( \
+ "LDR R0, =pxCurrentTCB \n\t" \
+ "LDR R0, [R0] \n\t" \
+ "LDR LR, [R0] \n\t" \
+ \
+ /* The critical nesting depth is the first item on the stack. */ \
+ /* Load it into the ulCriticalNesting variable. */ \
+ "LDR R0, =ulCriticalNesting \n\t" \
+ "LDMFD LR!, {R1} \n\t" \
+ "STR R1, [R0] \n\t" \
+ \
+ /* Get the SPSR from the stack. */ \
+ "LDMFD LR!, {R0} \n\t" \
+ "MSR SPSR, R0 \n\t" \
+ \
+ /* Restore all system mode registers for the task. */ \
+ "LDMFD LR, {R0-R14}^ \n\t" \
+ "NOP \n\t" \
+ \
+ /* Restore the return address. */ \
+ "LDR LR, [LR, #+60] \n\t" \
+ \
+ /* And return - correcting the offset in the LR to obtain the */ \
+ /* correct address. */ \
+ "SUBS PC, LR, #4 \n\t" \
+ ); \
+ ( void ) ulCriticalNesting; \
+ ( void ) pxCurrentTCB; \
+}
+/*-----------------------------------------------------------*/
+
+#define portSAVE_CONTEXT() \
+{ \
+extern volatile void * volatile pxCurrentTCB; \
+extern volatile uint32_t ulCriticalNesting; \
+ \
+ /* Push R0 as we are going to use the register. */ \
+ __asm volatile ( \
+ "STMDB SP!, {R0} \n\t" \
+ \
+ /* Set R0 to point to the task stack pointer. */ \
+ "STMDB SP,{SP}^ \n\t" \
+ "NOP \n\t" \
+ "SUB SP, SP, #4 \n\t" \
+ "LDMIA SP!,{R0} \n\t" \
+ \
+ /* Push the return address onto the stack. */ \
+ "STMDB R0!, {LR} \n\t" \
+ \
+ /* Now we have saved LR we can use it instead of R0. */ \
+ "MOV LR, R0 \n\t" \
+ \
+ /* Pop R0 so we can save it onto the system mode stack. */ \
+ "LDMIA SP!, {R0} \n\t" \
+ \
+ /* Push all the system mode registers onto the task stack. */ \
+ "STMDB LR,{R0-LR}^ \n\t" \
+ "NOP \n\t" \
+ "SUB LR, LR, #60 \n\t" \
+ \
+ /* Push the SPSR onto the task stack. */ \
+ "MRS R0, SPSR \n\t" \
+ "STMDB LR!, {R0} \n\t" \
+ \
+ "LDR R0, =ulCriticalNesting \n\t" \
+ "LDR R0, [R0] \n\t" \
+ "STMDB LR!, {R0} \n\t" \
+ \
+ /* Store the new top of stack for the task. */ \
+ "LDR R0, =pxCurrentTCB \n\t" \
+ "LDR R0, [R0] \n\t" \
+ "STR LR, [R0] \n\t" \
+ ); \
+ ( void ) ulCriticalNesting; \
+ ( void ) pxCurrentTCB; \
+}
+
+extern void vTaskSwitchContext( void );
+#define portYIELD_FROM_ISR() vTaskSwitchContext()
+#define portYIELD() __asm volatile ( "SWI 0" )
+/*-----------------------------------------------------------*/
+
+
+/* Critical section management. */
+
+/*
+ * The interrupt management utilities can only be called from ARM mode. When
+ * THUMB_INTERWORK is defined the utilities are defined as functions in
+ * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not
+ * defined then the utilities are defined as macros here - as per other ports.
+ */
+
+#ifdef THUMB_INTERWORK
+
+ extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+ extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+
+ #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb()
+ #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb()
+
+#else
+
+ #define portDISABLE_INTERRUPTS() \
+ __asm volatile ( \
+ "STMDB SP!, {R0} \n\t" /* Push R0. */ \
+ "MRS R0, CPSR \n\t" /* Get CPSR. */ \
+ "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */ \
+ "LDMIA SP!, {R0} " ) /* Pop R0. */
+
+ #define portENABLE_INTERRUPTS() \
+ __asm volatile ( \
+ "STMDB SP!, {R0} \n\t" /* Push R0. */ \
+ "MRS R0, CPSR \n\t" /* Get CPSR. */ \
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */ \
+ "LDMIA SP!, {R0} " ) /* Pop R0. */
+
+#endif /* THUMB_INTERWORK */
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portENTER_CRITICAL() vPortEnterCritical();
+#define portEXIT_CRITICAL() vPortExitCritical();
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/portable/GCC/ARM7_LPC23xx/port.c b/portable/GCC/ARM7_LPC23xx/port.c
index 15d1a21..3b99217 100644
--- a/portable/GCC/ARM7_LPC23xx/port.c
+++ b/portable/GCC/ARM7_LPC23xx/port.c
@@ -1,234 +1,231 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the ARM7 port.
- *
- * Components that can be compiled to either ARM or THUMB mode are
- * contained in this file. The ISR routines, which can only be compiled
- * to ARM mode are contained in portISR.c.
- *----------------------------------------------------------*/
-
-
-/* Standard includes. */
-#include <stdlib.h>
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Constants required to setup the task context. */
-#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
-#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
-#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 )
-
-/* Constants required to setup the tick ISR. */
-#define portENABLE_TIMER ( ( uint8_t ) 0x01 )
-#define portPRESCALE_VALUE 0x00
-#define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 )
-#define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 )
-
-/* Constants required to setup the VIC for the tick ISR. */
-#define portTIMER_VIC_CHANNEL ( ( uint32_t ) 0x0004 )
-#define portTIMER_VIC_CHANNEL_BIT ( ( uint32_t ) 0x0010 )
-#define portTIMER_VIC_ENABLE ( ( uint32_t ) 0x0020 )
-
-/*-----------------------------------------------------------*/
-
-/* Setup the timer to generate the tick interrupts. */
-static void prvSetupTimerInterrupt( void );
-
-/*
- * The scheduler can only be started from ARM mode, so
- * vPortISRStartFirstSTask() is defined in portISR.c.
- */
-extern void vPortISRStartFirstTask( void );
-
-/*-----------------------------------------------------------*/
-
-/*
- * Initialise the stack of a task to look exactly as if a call to
- * portSAVE_CONTEXT had been called.
- *
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-StackType_t *pxOriginalTOS;
-
- pxOriginalTOS = pxTopOfStack;
-
- /* To ensure asserts in tasks.c don't fail, although in this case the assert
- is not really required. */
- pxTopOfStack--;
-
- /* Setup the initial stack of the task. The stack is set exactly as
- expected by the portRESTORE_CONTEXT() macro. */
-
- /* First on the stack is the return address - which in this case is the
- start of the task. The offset is added to make the return address appear
- as it would within an IRQ ISR. */
- *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
- pxTopOfStack--;
-
- *pxTopOfStack = ( StackType_t ) 0x00000000; /* R14 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
- pxTopOfStack--;
-
- /* When the task starts is will expect to find the function parameter in
- R0. */
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack--;
-
- /* The last thing onto the stack is the status register, which is set for
- system mode, with interrupts enabled. */
- *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
-
- if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00 )
- {
- /* We want the task to start in thumb mode. */
- *pxTopOfStack |= portTHUMB_MODE_BIT;
- }
-
- pxTopOfStack--;
-
- /* Some optimisation levels use the stack differently to others. This
- means the interrupt flags cannot always be stored on the stack and will
- instead be stored in a variable, which is then saved as part of the
- tasks context. */
- *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
-
- return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
- /* Start the timer that generates the tick ISR. Interrupts are disabled
- here already. */
- prvSetupTimerInterrupt();
-
- /* Start the first task. */
- vPortISRStartFirstTask();
-
- /* Should not get here! */
- return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
- /* It is unlikely that the ARM port will require this function as there
- is nothing to return to. */
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the timer 0 to generate the tick interrupts at the required frequency.
- */
-static void prvSetupTimerInterrupt( void )
-{
-uint32_t ulCompareMatch;
-
- PCLKSEL0 = (PCLKSEL0 & (~(0x3<<2))) | (0x01 << 2);
- T0TCR = 2; /* Stop and reset the timer */
- T0CTCR = 0; /* Timer mode */
-
- /* A 1ms tick does not require the use of the timer prescale. This is
- defaulted to zero but can be used if necessary. */
- T0PR = portPRESCALE_VALUE;
-
- /* Calculate the match value required for our wanted tick rate. */
- ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
-
- /* Protect against divide by zero. Using an if() statement still results
- in a warning - hence the #if. */
- #if portPRESCALE_VALUE != 0
- {
- ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
- }
- #endif
- T0MR1 = ulCompareMatch;
-
- /* Generate tick with timer 0 compare match. */
- T0MCR = (3 << 3); /* Reset timer on match and generate interrupt */
-
- /* Setup the VIC for the timer. */
- VICIntEnable = 0x00000010;
-
- /* The ISR installed depends on whether the preemptive or cooperative
- scheduler is being used. */
- #if configUSE_PREEMPTION == 1
- {
- extern void ( vPreemptiveTick )( void );
- VICVectAddr4 = ( int32_t ) vPreemptiveTick;
- }
- #else
- {
- extern void ( vNonPreemptiveTick )( void );
- VICVectAddr4 = ( int32_t ) vNonPreemptiveTick;
- }
- #endif
-
- VICVectCntl4 = 1;
-
- /* Start the timer - interrupts are disabled when this function is called
- so it is okay to do this here. */
- T0TCR = portENABLE_TIMER;
-}
-/*-----------------------------------------------------------*/
-
-
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM7 port.
+ *
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in this file. The ISR routines, which can only be compiled
+ * to ARM mode are contained in portISR.c.
+ *----------------------------------------------------------*/
+
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to setup the task context. */
+#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
+#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 )
+
+/* Constants required to setup the tick ISR. */
+#define portENABLE_TIMER ( ( uint8_t ) 0x01 )
+#define portPRESCALE_VALUE 0x00
+#define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 )
+#define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 )
+
+/* Constants required to setup the VIC for the tick ISR. */
+#define portTIMER_VIC_CHANNEL ( ( uint32_t ) 0x0004 )
+#define portTIMER_VIC_CHANNEL_BIT ( ( uint32_t ) 0x0010 )
+#define portTIMER_VIC_ENABLE ( ( uint32_t ) 0x0020 )
+
+/*-----------------------------------------------------------*/
+
+/* Setup the timer to generate the tick interrupts. */
+static void prvSetupTimerInterrupt( void );
+
+/*
+ * The scheduler can only be started from ARM mode, so
+ * vPortISRStartFirstSTask() is defined in portISR.c.
+ */
+extern void vPortISRStartFirstTask( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been called.
+ *
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+StackType_t *pxOriginalTOS;
+
+ pxOriginalTOS = pxTopOfStack;
+
+ /* To ensure asserts in tasks.c don't fail, although in this case the assert
+ is not really required. */
+ pxTopOfStack--;
+
+ /* Setup the initial stack of the task. The stack is set exactly as
+ expected by the portRESTORE_CONTEXT() macro. */
+
+ /* First on the stack is the return address - which in this case is the
+ start of the task. The offset is added to make the return address appear
+ as it would within an IRQ ISR. */
+ *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
+ pxTopOfStack--;
+
+ *pxTopOfStack = ( StackType_t ) 0x00000000; /* R14 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+ pxTopOfStack--;
+
+ /* When the task starts is will expect to find the function parameter in
+ R0. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
+
+ /* The last thing onto the stack is the status register, which is set for
+ system mode, with interrupts enabled. */
+ *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+
+ if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00 )
+ {
+ /* We want the task to start in thumb mode. */
+ *pxTopOfStack |= portTHUMB_MODE_BIT;
+ }
+
+ pxTopOfStack--;
+
+ /* Some optimisation levels use the stack differently to others. This
+ means the interrupt flags cannot always be stored on the stack and will
+ instead be stored in a variable, which is then saved as part of the
+ tasks context. */
+ *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
+
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ here already. */
+ prvSetupTimerInterrupt();
+
+ /* Start the first task. */
+ vPortISRStartFirstTask();
+
+ /* Should not get here! */
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+ /* It is unlikely that the ARM port will require this function as there
+ is nothing to return to. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the timer 0 to generate the tick interrupts at the required frequency.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+uint32_t ulCompareMatch;
+
+ PCLKSEL0 = (PCLKSEL0 & (~(0x3<<2))) | (0x01 << 2);
+ T0TCR = 2; /* Stop and reset the timer */
+ T0CTCR = 0; /* Timer mode */
+
+ /* A 1ms tick does not require the use of the timer prescale. This is
+ defaulted to zero but can be used if necessary. */
+ T0PR = portPRESCALE_VALUE;
+
+ /* Calculate the match value required for our wanted tick rate. */
+ ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+
+ /* Protect against divide by zero. Using an if() statement still results
+ in a warning - hence the #if. */
+ #if portPRESCALE_VALUE != 0
+ {
+ ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
+ }
+ #endif
+ T0MR1 = ulCompareMatch;
+
+ /* Generate tick with timer 0 compare match. */
+ T0MCR = (3 << 3); /* Reset timer on match and generate interrupt */
+
+ /* Setup the VIC for the timer. */
+ VICIntEnable = 0x00000010;
+
+ /* The ISR installed depends on whether the preemptive or cooperative
+ scheduler is being used. */
+ #if configUSE_PREEMPTION == 1
+ {
+ extern void ( vPreemptiveTick )( void );
+ VICVectAddr4 = ( int32_t ) vPreemptiveTick;
+ }
+ #else
+ {
+ extern void ( vNonPreemptiveTick )( void );
+ VICVectAddr4 = ( int32_t ) vNonPreemptiveTick;
+ }
+ #endif
+
+ VICVectCntl4 = 1;
+
+ /* Start the timer - interrupts are disabled when this function is called
+ so it is okay to do this here. */
+ T0TCR = portENABLE_TIMER;
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM7_LPC23xx/portISR.c b/portable/GCC/ARM7_LPC23xx/portISR.c
index 2c1f891..a3279d2 100644
--- a/portable/GCC/ARM7_LPC23xx/portISR.c
+++ b/portable/GCC/ARM7_LPC23xx/portISR.c
@@ -1,219 +1,219 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-
-/*-----------------------------------------------------------
- * Components that can be compiled to either ARM or THUMB mode are
- * contained in port.c The ISR routines, which can only be compiled
- * to ARM mode, are contained in this file.
- *----------------------------------------------------------*/
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Constants required to handle interrupts. */
-#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 )
-#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 )
-
-/* Constants required to handle critical sections. */
-#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
-volatile uint32_t ulCriticalNesting = 9999UL;
-
-/*-----------------------------------------------------------*/
-
-/* ISR to handle manual context switches (from a call to taskYIELD()). */
-void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
-
-/*
- * The scheduler can only be started from ARM mode, hence the inclusion of this
- * function here.
- */
-void vPortISRStartFirstTask( void );
-/*-----------------------------------------------------------*/
-
-void vPortISRStartFirstTask( void )
-{
- /* Simply start the scheduler. This is included here as it can only be
- called from ARM mode. */
- portRESTORE_CONTEXT();
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Called by portYIELD() or taskYIELD() to manually force a context switch.
- *
- * When a context switch is performed from the task level the saved task
- * context is made to look as if it occurred from within the tick ISR. This
- * way the same restore context function can be used when restoring the context
- * saved from the ISR or that saved from a call to vPortYieldProcessor.
- */
-void vPortYieldProcessor( void )
-{
- /* Within an IRQ ISR the link register has an offset from the true return
- address, but an SWI ISR does not. Add the offset manually so the same
- ISR return code can be used in both cases. */
- __asm volatile ( "ADD LR, LR, #4" );
-
- /* Perform the context switch. First save the context of the current task. */
- portSAVE_CONTEXT();
-
- /* Find the highest priority task that is ready to run. */
- __asm volatile( "bl vTaskSwitchContext" );
-
- /* Restore the context of the new task. */
- portRESTORE_CONTEXT();
-}
-/*-----------------------------------------------------------*/
-
-/*
- * The ISR used for the scheduler tick depends on whether the cooperative or
- * the preemptive scheduler is being used.
- */
-
-
-#if configUSE_PREEMPTION == 0
-
- /* The cooperative scheduler requires a normal IRQ service routine to
- simply increment the system tick. */
- void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ")));
- void vNonPreemptiveTick( void )
- {
- xTaskIncrementTick();
- T0IR = 2;
- VICVectAddr = portCLEAR_VIC_INTERRUPT;
- }
-
-#else
-
- /* The preemptive scheduler is defined as "naked" as the full context is
- saved on entry as part of the context switch. */
- void vPreemptiveTick( void ) __attribute__((naked));
- void vPreemptiveTick( void )
- {
- /* Save the context of the interrupted task. */
- portSAVE_CONTEXT();
-
- /* Increment the RTOS tick count, then look for the highest priority
- task that is ready to run. */
- __asm volatile
- (
- " bl xTaskIncrementTick \t\n" \
- " cmp r0, #0 \t\n" \
- " beq SkipContextSwitch \t\n" \
- " bl vTaskSwitchContext \t\n" \
- "SkipContextSwitch: \t\n"
- );
-
- /* Ready for the next interrupt. */
- T0IR = 2;
- VICVectAddr = portCLEAR_VIC_INTERRUPT;
-
- /* Restore the context of the new task. */
- portRESTORE_CONTEXT();
- }
-
-#endif
-/*-----------------------------------------------------------*/
-
-/*
- * The interrupt management utilities can only be called from ARM mode. When
- * THUMB_INTERWORK is defined the utilities are defined as functions here to
- * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then
- * the utilities are defined as macros in portmacro.h - as per other ports.
- */
-#ifdef THUMB_INTERWORK
-
- void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
- void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
-
- void vPortDisableInterruptsFromThumb( void )
- {
- __asm volatile (
- "STMDB SP!, {R0} \n\t" /* Push R0. */
- "MRS R0, CPSR \n\t" /* Get CPSR. */
- "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
- "MSR CPSR, R0 \n\t" /* Write back modified value. */
- "LDMIA SP!, {R0} \n\t" /* Pop R0. */
- "BX R14" ); /* Return back to thumb. */
- }
-
- void vPortEnableInterruptsFromThumb( void )
- {
- __asm volatile (
- "STMDB SP!, {R0} \n\t" /* Push R0. */
- "MRS R0, CPSR \n\t" /* Get CPSR. */
- "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
- "MSR CPSR, R0 \n\t" /* Write back modified value. */
- "LDMIA SP!, {R0} \n\t" /* Pop R0. */
- "BX R14" ); /* Return back to thumb. */
- }
-
-#endif /* THUMB_INTERWORK */
-
-/* The code generated by the GCC compiler uses the stack in different ways at
-different optimisation levels. The interrupt flags can therefore not always
-be saved to the stack. Instead the critical section nesting level is stored
-in a variable, which is then saved as part of the stack context. */
-void vPortEnterCritical( void )
-{
- /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
- __asm volatile (
- "STMDB SP!, {R0} \n\t" /* Push R0. */
- "MRS R0, CPSR \n\t" /* Get CPSR. */
- "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
- "MSR CPSR, R0 \n\t" /* Write back modified value. */
- "LDMIA SP!, {R0}" ); /* Pop R0. */
-
- /* Now interrupts are disabled ulCriticalNesting can be accessed
- directly. Increment ulCriticalNesting to keep a count of how many times
- portENTER_CRITICAL() has been called. */
- ulCriticalNesting++;
-}
-
-void vPortExitCritical( void )
-{
- if( ulCriticalNesting > portNO_CRITICAL_NESTING )
- {
- /* Decrement the nesting count as we are leaving a critical section. */
- ulCriticalNesting--;
-
- /* If the nesting level has reached zero then interrupts should be
- re-enabled. */
- if( ulCriticalNesting == portNO_CRITICAL_NESTING )
- {
- /* Enable interrupts as per portEXIT_CRITICAL(). */
- __asm volatile (
- "STMDB SP!, {R0} \n\t" /* Push R0. */
- "MRS R0, CPSR \n\t" /* Get CPSR. */
- "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
- "MSR CPSR, R0 \n\t" /* Write back modified value. */
- "LDMIA SP!, {R0}" ); /* Pop R0. */
- }
- }
-}
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+/*-----------------------------------------------------------
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in port.c The ISR routines, which can only be compiled
+ * to ARM mode, are contained in this file.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to handle interrupts. */
+#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 )
+#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 )
+
+/* Constants required to handle critical sections. */
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
+volatile uint32_t ulCriticalNesting = 9999UL;
+
+/*-----------------------------------------------------------*/
+
+/* ISR to handle manual context switches (from a call to taskYIELD()). */
+void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
+
+/*
+ * The scheduler can only be started from ARM mode, hence the inclusion of this
+ * function here.
+ */
+void vPortISRStartFirstTask( void );
+/*-----------------------------------------------------------*/
+
+void vPortISRStartFirstTask( void )
+{
+ /* Simply start the scheduler. This is included here as it can only be
+ called from ARM mode. */
+ portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Called by portYIELD() or taskYIELD() to manually force a context switch.
+ *
+ * When a context switch is performed from the task level the saved task
+ * context is made to look as if it occurred from within the tick ISR. This
+ * way the same restore context function can be used when restoring the context
+ * saved from the ISR or that saved from a call to vPortYieldProcessor.
+ */
+void vPortYieldProcessor( void )
+{
+ /* Within an IRQ ISR the link register has an offset from the true return
+ address, but an SWI ISR does not. Add the offset manually so the same
+ ISR return code can be used in both cases. */
+ __asm volatile ( "ADD LR, LR, #4" );
+
+ /* Perform the context switch. First save the context of the current task. */
+ portSAVE_CONTEXT();
+
+ /* Find the highest priority task that is ready to run. */
+ __asm volatile( "bl vTaskSwitchContext" );
+
+ /* Restore the context of the new task. */
+ portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * The ISR used for the scheduler tick depends on whether the cooperative or
+ * the preemptive scheduler is being used.
+ */
+
+
+#if configUSE_PREEMPTION == 0
+
+ /* The cooperative scheduler requires a normal IRQ service routine to
+ simply increment the system tick. */
+ void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ")));
+ void vNonPreemptiveTick( void )
+ {
+ xTaskIncrementTick();
+ T0IR = 2;
+ VICVectAddr = portCLEAR_VIC_INTERRUPT;
+ }
+
+#else
+
+ /* The preemptive scheduler is defined as "naked" as the full context is
+ saved on entry as part of the context switch. */
+ void vPreemptiveTick( void ) __attribute__((naked));
+ void vPreemptiveTick( void )
+ {
+ /* Save the context of the interrupted task. */
+ portSAVE_CONTEXT();
+
+ /* Increment the RTOS tick count, then look for the highest priority
+ task that is ready to run. */
+ __asm volatile
+ (
+ " bl xTaskIncrementTick \t\n" \
+ " cmp r0, #0 \t\n" \
+ " beq SkipContextSwitch \t\n" \
+ " bl vTaskSwitchContext \t\n" \
+ "SkipContextSwitch: \t\n"
+ );
+
+ /* Ready for the next interrupt. */
+ T0IR = 2;
+ VICVectAddr = portCLEAR_VIC_INTERRUPT;
+
+ /* Restore the context of the new task. */
+ portRESTORE_CONTEXT();
+ }
+
+#endif
+/*-----------------------------------------------------------*/
+
+/*
+ * The interrupt management utilities can only be called from ARM mode. When
+ * THUMB_INTERWORK is defined the utilities are defined as functions here to
+ * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then
+ * the utilities are defined as macros in portmacro.h - as per other ports.
+ */
+#ifdef THUMB_INTERWORK
+
+ void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+ void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+
+ void vPortDisableInterruptsFromThumb( void )
+ {
+ __asm volatile (
+ "STMDB SP!, {R0} \n\t" /* Push R0. */
+ "MRS R0, CPSR \n\t" /* Get CPSR. */
+ "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */
+ "LDMIA SP!, {R0} \n\t" /* Pop R0. */
+ "BX R14" ); /* Return back to thumb. */
+ }
+
+ void vPortEnableInterruptsFromThumb( void )
+ {
+ __asm volatile (
+ "STMDB SP!, {R0} \n\t" /* Push R0. */
+ "MRS R0, CPSR \n\t" /* Get CPSR. */
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */
+ "LDMIA SP!, {R0} \n\t" /* Pop R0. */
+ "BX R14" ); /* Return back to thumb. */
+ }
+
+#endif /* THUMB_INTERWORK */
+
+/* The code generated by the GCC compiler uses the stack in different ways at
+different optimisation levels. The interrupt flags can therefore not always
+be saved to the stack. Instead the critical section nesting level is stored
+in a variable, which is then saved as part of the stack context. */
+void vPortEnterCritical( void )
+{
+ /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
+ __asm volatile (
+ "STMDB SP!, {R0} \n\t" /* Push R0. */
+ "MRS R0, CPSR \n\t" /* Get CPSR. */
+ "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */
+ "LDMIA SP!, {R0}" ); /* Pop R0. */
+
+ /* Now interrupts are disabled ulCriticalNesting can be accessed
+ directly. Increment ulCriticalNesting to keep a count of how many times
+ portENTER_CRITICAL() has been called. */
+ ulCriticalNesting++;
+}
+
+void vPortExitCritical( void )
+{
+ if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+ {
+ /* Decrement the nesting count as we are leaving a critical section. */
+ ulCriticalNesting--;
+
+ /* If the nesting level has reached zero then interrupts should be
+ re-enabled. */
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+ {
+ /* Enable interrupts as per portEXIT_CRITICAL(). */
+ __asm volatile (
+ "STMDB SP!, {R0} \n\t" /* Push R0. */
+ "MRS R0, CPSR \n\t" /* Get CPSR. */
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */
+ "LDMIA SP!, {R0}" ); /* Pop R0. */
+ }
+ }
+}
diff --git a/portable/GCC/ARM7_LPC23xx/portmacro.h b/portable/GCC/ARM7_LPC23xx/portmacro.h
index a4f0a46..c69003c 100644
--- a/portable/GCC/ARM7_LPC23xx/portmacro.h
+++ b/portable/GCC/ARM7_LPC23xx/portmacro.h
@@ -1,250 +1,249 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*
- Changes from V3.2.3
-
- + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
-
- Changes from V3.2.4
-
- + Removed the use of the %0 parameter within the assembler macros and
- replaced them with hard coded registers. This will ensure the
- assembler does not select the link register as the temp register as
- was occasionally happening previously.
-
- + The assembler statements are now included in a single asm block rather
- than each line having its own asm block.
-
- Changes from V4.5.0
-
- + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
- and replaced them with portYIELD_FROM_ISR() macro. Application code
- should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
- macros as per the V4.5.1 demo code.
-*/
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT short
-#define portSTACK_TYPE uint32_t
-#define portBASE_TYPE portLONG
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
-#else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH ( -1 )
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT 8
-#define portNOP() __asm volatile ( "NOP" );
-/*-----------------------------------------------------------*/
-
-
-/* Scheduler utilities. */
-
-/*
- * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR
- * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but
- * are included here for efficiency. An attempt to call one from
- * THUMB mode code will result in a compile time error.
- */
-
-#define portRESTORE_CONTEXT() \
-{ \
-extern volatile void * volatile pxCurrentTCB; \
-extern volatile uint32_t ulCriticalNesting; \
- \
- /* Set the LR to the task stack. */ \
- __asm volatile ( \
- "LDR R0, =pxCurrentTCB \n\t" \
- "LDR R0, [R0] \n\t" \
- "LDR LR, [R0] \n\t" \
- \
- /* The critical nesting depth is the first item on the stack. */ \
- /* Load it into the ulCriticalNesting variable. */ \
- "LDR R0, =ulCriticalNesting \n\t" \
- "LDMFD LR!, {R1} \n\t" \
- "STR R1, [R0] \n\t" \
- \
- /* Get the SPSR from the stack. */ \
- "LDMFD LR!, {R0} \n\t" \
- "MSR SPSR, R0 \n\t" \
- \
- /* Restore all system mode registers for the task. */ \
- "LDMFD LR, {R0-R14}^ \n\t" \
- "NOP \n\t" \
- \
- /* Restore the return address. */ \
- "LDR LR, [LR, #+60] \n\t" \
- \
- /* And return - correcting the offset in the LR to obtain the */ \
- /* correct address. */ \
- "SUBS PC, LR, #4 \n\t" \
- ); \
- ( void ) ulCriticalNesting; \
- ( void ) pxCurrentTCB; \
-}
-/*-----------------------------------------------------------*/
-
-#define portSAVE_CONTEXT() \
-{ \
-extern volatile void * volatile pxCurrentTCB; \
-extern volatile uint32_t ulCriticalNesting; \
- \
- /* Push R0 as we are going to use the register. */ \
- __asm volatile ( \
- "STMDB SP!, {R0} \n\t" \
- \
- /* Set R0 to point to the task stack pointer. */ \
- "STMDB SP,{SP}^ \n\t" \
- "NOP \n\t" \
- "SUB SP, SP, #4 \n\t" \
- "LDMIA SP!,{R0} \n\t" \
- \
- /* Push the return address onto the stack. */ \
- "STMDB R0!, {LR} \n\t" \
- \
- /* Now we have saved LR we can use it instead of R0. */ \
- "MOV LR, R0 \n\t" \
- \
- /* Pop R0 so we can save it onto the system mode stack. */ \
- "LDMIA SP!, {R0} \n\t" \
- \
- /* Push all the system mode registers onto the task stack. */ \
- "STMDB LR,{R0-LR}^ \n\t" \
- "NOP \n\t" \
- "SUB LR, LR, #60 \n\t" \
- \
- /* Push the SPSR onto the task stack. */ \
- "MRS R0, SPSR \n\t" \
- "STMDB LR!, {R0} \n\t" \
- \
- "LDR R0, =ulCriticalNesting \n\t" \
- "LDR R0, [R0] \n\t" \
- "STMDB LR!, {R0} \n\t" \
- \
- /* Store the new top of stack for the task. */ \
- "LDR R0, =pxCurrentTCB \n\t" \
- "LDR R0, [R0] \n\t" \
- "STR LR, [R0] \n\t" \
- ); \
- ( void ) ulCriticalNesting; \
- ( void ) pxCurrentTCB; \
-}
-
-
-#define portYIELD_FROM_ISR() vTaskSwitchContext()
-#define portYIELD() __asm volatile ( "SWI 0" )
-/*-----------------------------------------------------------*/
-
-
-/* Critical section management. */
-
-/*
- * The interrupt management utilities can only be called from ARM mode. When
- * THUMB_INTERWORK is defined the utilities are defined as functions in
- * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not
- * defined then the utilities are defined as macros here - as per other ports.
- */
-
-#ifdef THUMB_INTERWORK
-
- extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
- extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
-
- #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb()
- #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb()
-
-#else
-
- #define portDISABLE_INTERRUPTS() \
- __asm volatile ( \
- "STMDB SP!, {R0} \n\t" /* Push R0. */ \
- "MRS R0, CPSR \n\t" /* Get CPSR. */ \
- "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \
- "MSR CPSR, R0 \n\t" /* Write back modified value. */ \
- "LDMIA SP!, {R0} " ) /* Pop R0. */
-
- #define portENABLE_INTERRUPTS() \
- __asm volatile ( \
- "STMDB SP!, {R0} \n\t" /* Push R0. */ \
- "MRS R0, CPSR \n\t" /* Get CPSR. */ \
- "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \
- "MSR CPSR, R0 \n\t" /* Write back modified value. */ \
- "LDMIA SP!, {R0} " ) /* Pop R0. */
-
-#endif /* THUMB_INTERWORK */
-
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-
-#define portENTER_CRITICAL() vPortEnterCritical();
-#define portEXIT_CRITICAL() vPortExitCritical();
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*
+ Changes from V3.2.3
+
+ + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
+
+ Changes from V3.2.4
+
+ + Removed the use of the %0 parameter within the assembler macros and
+ replaced them with hard coded registers. This will ensure the
+ assembler does not select the link register as the temp register as
+ was occasionally happening previously.
+
+ + The assembler statements are now included in a single asm block rather
+ than each line having its own asm block.
+
+ Changes from V4.5.0
+
+ + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
+ and replaced them with portYIELD_FROM_ISR() macro. Application code
+ should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
+ macros as per the V4.5.1 demo code.
+*/
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE portLONG
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portNOP() __asm volatile ( "NOP" );
+/*-----------------------------------------------------------*/
+
+
+/* Scheduler utilities. */
+
+/*
+ * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR
+ * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but
+ * are included here for efficiency. An attempt to call one from
+ * THUMB mode code will result in a compile time error.
+ */
+
+#define portRESTORE_CONTEXT() \
+{ \
+extern volatile void * volatile pxCurrentTCB; \
+extern volatile uint32_t ulCriticalNesting; \
+ \
+ /* Set the LR to the task stack. */ \
+ __asm volatile ( \
+ "LDR R0, =pxCurrentTCB \n\t" \
+ "LDR R0, [R0] \n\t" \
+ "LDR LR, [R0] \n\t" \
+ \
+ /* The critical nesting depth is the first item on the stack. */ \
+ /* Load it into the ulCriticalNesting variable. */ \
+ "LDR R0, =ulCriticalNesting \n\t" \
+ "LDMFD LR!, {R1} \n\t" \
+ "STR R1, [R0] \n\t" \
+ \
+ /* Get the SPSR from the stack. */ \
+ "LDMFD LR!, {R0} \n\t" \
+ "MSR SPSR, R0 \n\t" \
+ \
+ /* Restore all system mode registers for the task. */ \
+ "LDMFD LR, {R0-R14}^ \n\t" \
+ "NOP \n\t" \
+ \
+ /* Restore the return address. */ \
+ "LDR LR, [LR, #+60] \n\t" \
+ \
+ /* And return - correcting the offset in the LR to obtain the */ \
+ /* correct address. */ \
+ "SUBS PC, LR, #4 \n\t" \
+ ); \
+ ( void ) ulCriticalNesting; \
+ ( void ) pxCurrentTCB; \
+}
+/*-----------------------------------------------------------*/
+
+#define portSAVE_CONTEXT() \
+{ \
+extern volatile void * volatile pxCurrentTCB; \
+extern volatile uint32_t ulCriticalNesting; \
+ \
+ /* Push R0 as we are going to use the register. */ \
+ __asm volatile ( \
+ "STMDB SP!, {R0} \n\t" \
+ \
+ /* Set R0 to point to the task stack pointer. */ \
+ "STMDB SP,{SP}^ \n\t" \
+ "NOP \n\t" \
+ "SUB SP, SP, #4 \n\t" \
+ "LDMIA SP!,{R0} \n\t" \
+ \
+ /* Push the return address onto the stack. */ \
+ "STMDB R0!, {LR} \n\t" \
+ \
+ /* Now we have saved LR we can use it instead of R0. */ \
+ "MOV LR, R0 \n\t" \
+ \
+ /* Pop R0 so we can save it onto the system mode stack. */ \
+ "LDMIA SP!, {R0} \n\t" \
+ \
+ /* Push all the system mode registers onto the task stack. */ \
+ "STMDB LR,{R0-LR}^ \n\t" \
+ "NOP \n\t" \
+ "SUB LR, LR, #60 \n\t" \
+ \
+ /* Push the SPSR onto the task stack. */ \
+ "MRS R0, SPSR \n\t" \
+ "STMDB LR!, {R0} \n\t" \
+ \
+ "LDR R0, =ulCriticalNesting \n\t" \
+ "LDR R0, [R0] \n\t" \
+ "STMDB LR!, {R0} \n\t" \
+ \
+ /* Store the new top of stack for the task. */ \
+ "LDR R0, =pxCurrentTCB \n\t" \
+ "LDR R0, [R0] \n\t" \
+ "STR LR, [R0] \n\t" \
+ ); \
+ ( void ) ulCriticalNesting; \
+ ( void ) pxCurrentTCB; \
+}
+
+
+#define portYIELD_FROM_ISR() vTaskSwitchContext()
+#define portYIELD() __asm volatile ( "SWI 0" )
+/*-----------------------------------------------------------*/
+
+
+/* Critical section management. */
+
+/*
+ * The interrupt management utilities can only be called from ARM mode. When
+ * THUMB_INTERWORK is defined the utilities are defined as functions in
+ * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not
+ * defined then the utilities are defined as macros here - as per other ports.
+ */
+
+#ifdef THUMB_INTERWORK
+
+ extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+ extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+
+ #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb()
+ #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb()
+
+#else
+
+ #define portDISABLE_INTERRUPTS() \
+ __asm volatile ( \
+ "STMDB SP!, {R0} \n\t" /* Push R0. */ \
+ "MRS R0, CPSR \n\t" /* Get CPSR. */ \
+ "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */ \
+ "LDMIA SP!, {R0} " ) /* Pop R0. */
+
+ #define portENABLE_INTERRUPTS() \
+ __asm volatile ( \
+ "STMDB SP!, {R0} \n\t" /* Push R0. */ \
+ "MRS R0, CPSR \n\t" /* Get CPSR. */ \
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */ \
+ "LDMIA SP!, {R0} " ) /* Pop R0. */
+
+#endif /* THUMB_INTERWORK */
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portENTER_CRITICAL() vPortEnterCritical();
+#define portEXIT_CRITICAL() vPortExitCritical();
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/portable/GCC/ARM_CA53_64_BIT/port.c b/portable/GCC/ARM_CA53_64_BIT/port.c
index cdeb698..3e686e3 100644
--- a/portable/GCC/ARM_CA53_64_BIT/port.c
+++ b/portable/GCC/ARM_CA53_64_BIT/port.c
@@ -1,519 +1,518 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/* Standard includes. */
-#include <stdlib.h>
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
- #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
-#endif
-
-#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
- #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
-#endif
-
-#ifndef configUNIQUE_INTERRUPT_PRIORITIES
- #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
-#endif
-
-#ifndef configSETUP_TICK_INTERRUPT
- #error configSETUP_TICK_INTERRUPT() must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
-#endif /* configSETUP_TICK_INTERRUPT */
-
-#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
-#endif
-
-#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
-#endif
-
-#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
-#endif
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
- /* Check the configuration. */
- #if( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-/* In case security extensions are implemented. */
-#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
-#endif
-
-/* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in
-portmacro.h. */
-#ifndef configCLEAR_TICK_INTERRUPT
- #define configCLEAR_TICK_INTERRUPT()
-#endif
-
-/* A critical section is exited when the critical section nesting count reaches
-this value. */
-#define portNO_CRITICAL_NESTING ( ( size_t ) 0 )
-
-/* In all GICs 255 can be written to the priority mask register to unmask all
-(but the lowest) interrupt priority. */
-#define portUNMASK_VALUE ( 0xFFUL )
-
-/* Tasks are not created with a floating point context, but can be given a
-floating point context after they have been created. A variable is stored as
-part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
-does not have an FPU context, or any other value if the task does have an FPU
-context. */
-#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
-
-/* Constants required to setup the initial task context. */
-#define portSP_ELx ( ( StackType_t ) 0x01 )
-#define portSP_EL0 ( ( StackType_t ) 0x00 )
-
-#if defined( GUEST )
- #define portEL1 ( ( StackType_t ) 0x04 )
- #define portINITIAL_PSTATE ( portEL1 | portSP_EL0 )
-#else
- #define portEL3 ( ( StackType_t ) 0x0c )
- /* At the time of writing, the BSP only supports EL3. */
- #define portINITIAL_PSTATE ( portEL3 | portSP_EL0 )
-#endif
-
-
-/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
-point is zero. */
-#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 )
-
-/* Masks all bits in the APSR other than the mode bits. */
-#define portAPSR_MODE_BITS_MASK ( 0x0C )
-
-/* The I bit in the DAIF bits. */
-#define portDAIF_I ( 0x80 )
-
-/* Macro to unmask all interrupt priorities. */
-#define portCLEAR_INTERRUPT_MASK() \
-{ \
- portDISABLE_INTERRUPTS(); \
- portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
- __asm volatile ( "DSB SY \n" \
- "ISB SY \n" ); \
- portENABLE_INTERRUPTS(); \
-}
-
-/* Hardware specifics used when sanity checking the configuration. */
-#define portINTERRUPT_PRIORITY_REGISTER_OFFSET 0x400UL
-#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
-#define portBIT_0_SET ( ( uint8_t ) 0x01 )
-
-/*-----------------------------------------------------------*/
-
-/*
- * Starts the first task executing. This function is necessarily written in
- * assembly code so is implemented in portASM.s.
- */
-extern void vPortRestoreTaskContext( void );
-
-/*-----------------------------------------------------------*/
-
-/* A variable is used to keep track of the critical section nesting. This
-variable has to be stored as part of the task context and must be initialised to
-a non zero value to ensure interrupts don't inadvertently become unmasked before
-the scheduler starts. As it is stored as part of the task context it will
-automatically be set to 0 when the first task is started. */
-volatile uint64_t ullCriticalNesting = 9999ULL;
-
-/* Saved as part of the task context. If ullPortTaskHasFPUContext is non-zero
-then floating point context must be saved and restored for the task. */
-uint64_t ullPortTaskHasFPUContext = pdFALSE;
-
-/* Set to 1 to pend a context switch from an ISR. */
-uint64_t ullPortYieldRequired = pdFALSE;
-
-/* Counts the interrupt nesting depth. A context switch is only performed if
-if the nesting depth is 0. */
-uint64_t ullPortInterruptNesting = 0;
-
-/* Used in the ASM code. */
-__attribute__(( used )) const uint64_t ullICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
-__attribute__(( used )) const uint64_t ullICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
-__attribute__(( used )) const uint64_t ullICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
-__attribute__(( used )) const uint64_t ullMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
- /* Setup the initial stack of the task. The stack is set exactly as
- expected by the portRESTORE_CONTEXT() macro. */
-
- /* First all the general purpose registers. */
- pxTopOfStack--;
- *pxTopOfStack = 0x0101010101010101ULL; /* R1 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack--;
- *pxTopOfStack = 0x0303030303030303ULL; /* R3 */
- pxTopOfStack--;
- *pxTopOfStack = 0x0202020202020202ULL; /* R2 */
- pxTopOfStack--;
- *pxTopOfStack = 0x0505050505050505ULL; /* R5 */
- pxTopOfStack--;
- *pxTopOfStack = 0x0404040404040404ULL; /* R4 */
- pxTopOfStack--;
- *pxTopOfStack = 0x0707070707070707ULL; /* R7 */
- pxTopOfStack--;
- *pxTopOfStack = 0x0606060606060606ULL; /* R6 */
- pxTopOfStack--;
- *pxTopOfStack = 0x0909090909090909ULL; /* R9 */
- pxTopOfStack--;
- *pxTopOfStack = 0x0808080808080808ULL; /* R8 */
- pxTopOfStack--;
- *pxTopOfStack = 0x1111111111111111ULL; /* R11 */
- pxTopOfStack--;
- *pxTopOfStack = 0x1010101010101010ULL; /* R10 */
- pxTopOfStack--;
- *pxTopOfStack = 0x1313131313131313ULL; /* R13 */
- pxTopOfStack--;
- *pxTopOfStack = 0x1212121212121212ULL; /* R12 */
- pxTopOfStack--;
- *pxTopOfStack = 0x1515151515151515ULL; /* R15 */
- pxTopOfStack--;
- *pxTopOfStack = 0x1414141414141414ULL; /* R14 */
- pxTopOfStack--;
- *pxTopOfStack = 0x1717171717171717ULL; /* R17 */
- pxTopOfStack--;
- *pxTopOfStack = 0x1616161616161616ULL; /* R16 */
- pxTopOfStack--;
- *pxTopOfStack = 0x1919191919191919ULL; /* R19 */
- pxTopOfStack--;
- *pxTopOfStack = 0x1818181818181818ULL; /* R18 */
- pxTopOfStack--;
- *pxTopOfStack = 0x2121212121212121ULL; /* R21 */
- pxTopOfStack--;
- *pxTopOfStack = 0x2020202020202020ULL; /* R20 */
- pxTopOfStack--;
- *pxTopOfStack = 0x2323232323232323ULL; /* R23 */
- pxTopOfStack--;
- *pxTopOfStack = 0x2222222222222222ULL; /* R22 */
- pxTopOfStack--;
- *pxTopOfStack = 0x2525252525252525ULL; /* R25 */
- pxTopOfStack--;
- *pxTopOfStack = 0x2424242424242424ULL; /* R24 */
- pxTopOfStack--;
- *pxTopOfStack = 0x2727272727272727ULL; /* R27 */
- pxTopOfStack--;
- *pxTopOfStack = 0x2626262626262626ULL; /* R26 */
- pxTopOfStack--;
- *pxTopOfStack = 0x2929292929292929ULL; /* R29 */
- pxTopOfStack--;
- *pxTopOfStack = 0x2828282828282828ULL; /* R28 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x00; /* XZR - has no effect, used so there are an even number of registers. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x00; /* R30 - procedure call link register. */
- pxTopOfStack--;
-
- *pxTopOfStack = portINITIAL_PSTATE;
- pxTopOfStack--;
-
- *pxTopOfStack = ( StackType_t ) pxCode; /* Exception return address. */
- pxTopOfStack--;
-
- /* The task will start with a critical nesting count of 0 as interrupts are
- enabled. */
- *pxTopOfStack = portNO_CRITICAL_NESTING;
- pxTopOfStack--;
-
- /* The task will start without a floating point context. A task that uses
- the floating point hardware must call vPortTaskUsesFPU() before executing
- any floating point instructions. */
- *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
-
- return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-uint32_t ulAPSR;
-
- #if( configASSERT_DEFINED == 1 )
- {
- volatile uint32_t ulOriginalPriority;
- volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );
- volatile uint8_t ucMaxPriorityValue;
-
- /* Determine how many priority bits are implemented in the GIC.
-
- Save the interrupt priority value that is about to be clobbered. */
- ulOriginalPriority = *pucFirstUserPriorityRegister;
-
- /* Determine the number of priority bits available. First write to
- all possible bits. */
- *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
-
- /* Read the value back to see how many bits stuck. */
- ucMaxPriorityValue = *pucFirstUserPriorityRegister;
-
- /* Shift to the least significant bits. */
- while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET )
- {
- ucMaxPriorityValue >>= ( uint8_t ) 0x01;
- }
-
- /* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
- value. */
-
- configASSERT( ucMaxPriorityValue >= portLOWEST_INTERRUPT_PRIORITY );
-
-
- /* Restore the clobbered interrupt priority register to its original
- value. */
- *pucFirstUserPriorityRegister = ulOriginalPriority;
- }
- #endif /* configASSERT_DEFINED */
-
-
- /* At the time of writing, the BSP only supports EL3. */
- __asm volatile ( "MRS %0, CurrentEL" : "=r" ( ulAPSR ) );
- ulAPSR &= portAPSR_MODE_BITS_MASK;
-
-#if defined( GUEST )
- #warning Building for execution as a guest under XEN. THIS IS NOT A FULLY TESTED PATH.
- configASSERT( ulAPSR == portEL1 );
- if( ulAPSR == portEL1 )
-#else
- configASSERT( ulAPSR == portEL3 );
- if( ulAPSR == portEL3 )
-#endif
- {
- /* Only continue if the binary point value is set to its lowest possible
- setting. See the comments in vPortValidateInterruptPriority() below for
- more information. */
- configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
-
- if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
- {
- /* Interrupts are turned off in the CPU itself to ensure a tick does
- not execute while the scheduler is being started. Interrupts are
- automatically turned back on in the CPU when the first task starts
- executing. */
- portDISABLE_INTERRUPTS();
-
- /* Start the timer that generates the tick ISR. */
- configSETUP_TICK_INTERRUPT();
-
- /* Start the first task executing. */
- vPortRestoreTaskContext();
- }
- }
-
- return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
- /* Not implemented in ports where there is nothing to return to.
- Artificially force an assert. */
- configASSERT( ullCriticalNesting == 1000ULL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
- /* Mask interrupts up to the max syscall interrupt priority. */
- uxPortSetInterruptMask();
-
- /* Now interrupts are disabled ullCriticalNesting can be accessed
- directly. Increment ullCriticalNesting to keep a count of how many times
- portENTER_CRITICAL() has been called. */
- ullCriticalNesting++;
-
- /* This is not the interrupt safe version of the enter critical function so
- assert() if it is being called from an interrupt context. Only API
- functions that end in "FromISR" can be used in an interrupt. Only assert if
- the critical nesting count is 1 to protect against recursive calls if the
- assert function also uses a critical section. */
- if( ullCriticalNesting == 1ULL )
- {
- configASSERT( ullPortInterruptNesting == 0 );
- }
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
- if( ullCriticalNesting > portNO_CRITICAL_NESTING )
- {
- /* Decrement the nesting count as the critical section is being
- exited. */
- ullCriticalNesting--;
-
- /* If the nesting level has reached zero then all interrupt
- priorities must be re-enabled. */
- if( ullCriticalNesting == portNO_CRITICAL_NESTING )
- {
- /* Critical nesting has reached zero so all interrupt priorities
- should be unmasked. */
- portCLEAR_INTERRUPT_MASK();
- }
- }
-}
-/*-----------------------------------------------------------*/
-
-void FreeRTOS_Tick_Handler( void )
-{
- /* Must be the lowest possible priority. */
- #if !defined( QEMU )
- {
- configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER == ( uint32_t ) ( portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
- }
- #endif
-
- /* Interrupts should not be enabled before this point. */
- #if( configASSERT_DEFINED == 1 )
- {
- uint32_t ulMaskBits;
-
- __asm volatile( "mrs %0, daif" : "=r"( ulMaskBits ) :: "memory" );
- configASSERT( ( ulMaskBits & portDAIF_I ) != 0 );
- }
- #endif /* configASSERT_DEFINED */
-
- /* Set interrupt mask before altering scheduler structures. The tick
- handler runs at the lowest priority, so interrupts cannot already be masked,
- so there is no need to save and restore the current mask value. It is
- necessary to turn off interrupts in the CPU itself while the ICCPMR is being
- updated. */
- portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
- __asm volatile ( "dsb sy \n"
- "isb sy \n" ::: "memory" );
-
- /* Ok to enable interrupts after the interrupt source has been cleared. */
- configCLEAR_TICK_INTERRUPT();
- portENABLE_INTERRUPTS();
-
- /* Increment the RTOS tick. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- ullPortYieldRequired = pdTRUE;
- }
-
- /* Ensure all interrupt priorities are active again. */
- portCLEAR_INTERRUPT_MASK();
-}
-/*-----------------------------------------------------------*/
-
-void vPortTaskUsesFPU( void )
-{
- /* A task is registering the fact that it needs an FPU context. Set the
- FPU flag (which is saved as part of the task context). */
- ullPortTaskHasFPUContext = pdTRUE;
-
- /* Consider initialising the FPSR here - but probably not necessary in
- AArch64. */
-}
-/*-----------------------------------------------------------*/
-
-void vPortClearInterruptMask( UBaseType_t uxNewMaskValue )
-{
- if( uxNewMaskValue == pdFALSE )
- {
- portCLEAR_INTERRUPT_MASK();
- }
-}
-/*-----------------------------------------------------------*/
-
-UBaseType_t uxPortSetInterruptMask( void )
-{
-uint32_t ulReturn;
-
- /* Interrupt in the CPU must be turned off while the ICCPMR is being
- updated. */
- portDISABLE_INTERRUPTS();
- if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
- {
- /* Interrupts were already masked. */
- ulReturn = pdTRUE;
- }
- else
- {
- ulReturn = pdFALSE;
- portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
- __asm volatile ( "dsb sy \n"
- "isb sy \n" ::: "memory" );
- }
- portENABLE_INTERRUPTS();
-
- return ulReturn;
-}
-/*-----------------------------------------------------------*/
-
-#if( configASSERT_DEFINED == 1 )
-
- void vPortValidateInterruptPriority( void )
- {
- /* The following assertion will fail if a service routine (ISR) for
- an interrupt that has been assigned a priority above
- configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
- function. ISR safe FreeRTOS API functions must *only* be called
- from interrupts that have been assigned a priority at or below
- configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
- Numerically low interrupt priority numbers represent logically high
- interrupt priorities, therefore the priority of the interrupt must
- be set to a value equal to or numerically *higher* than
- configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
- FreeRTOS maintains separate thread and ISR API functions to ensure
- interrupt entry is as fast and simple as possible. */
- configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
-
- /* Priority grouping: The interrupt controller (GIC) allows the bits
- that define each interrupt's priority to be split between bits that
- define the interrupt's pre-emption priority bits and bits that define
- the interrupt's sub-priority. For simplicity all bits must be defined
- to be pre-emption priority bits. The following assertion will fail if
- this is not the case (if some bits represent a sub-priority).
-
- The priority grouping is configured by the GIC's binary point register
- (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest
- possible value (which may be above 0). */
- configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
- }
-
-#endif /* configASSERT_DEFINED */
-/*-----------------------------------------------------------*/
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
+ #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
+ #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#ifndef configUNIQUE_INTERRUPT_PRIORITIES
+ #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#ifndef configSETUP_TICK_INTERRUPT
+ #error configSETUP_TICK_INTERRUPT() must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif /* configSETUP_TICK_INTERRUPT */
+
+#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
+#endif
+
+#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+ /* Check the configuration. */
+ #if( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/* In case security extensions are implemented. */
+#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
+#endif
+
+/* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in
+portmacro.h. */
+#ifndef configCLEAR_TICK_INTERRUPT
+ #define configCLEAR_TICK_INTERRUPT()
+#endif
+
+/* A critical section is exited when the critical section nesting count reaches
+this value. */
+#define portNO_CRITICAL_NESTING ( ( size_t ) 0 )
+
+/* In all GICs 255 can be written to the priority mask register to unmask all
+(but the lowest) interrupt priority. */
+#define portUNMASK_VALUE ( 0xFFUL )
+
+/* Tasks are not created with a floating point context, but can be given a
+floating point context after they have been created. A variable is stored as
+part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+does not have an FPU context, or any other value if the task does have an FPU
+context. */
+#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
+
+/* Constants required to setup the initial task context. */
+#define portSP_ELx ( ( StackType_t ) 0x01 )
+#define portSP_EL0 ( ( StackType_t ) 0x00 )
+
+#if defined( GUEST )
+ #define portEL1 ( ( StackType_t ) 0x04 )
+ #define portINITIAL_PSTATE ( portEL1 | portSP_EL0 )
+#else
+ #define portEL3 ( ( StackType_t ) 0x0c )
+ /* At the time of writing, the BSP only supports EL3. */
+ #define portINITIAL_PSTATE ( portEL3 | portSP_EL0 )
+#endif
+
+
+/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
+point is zero. */
+#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 )
+
+/* Masks all bits in the APSR other than the mode bits. */
+#define portAPSR_MODE_BITS_MASK ( 0x0C )
+
+/* The I bit in the DAIF bits. */
+#define portDAIF_I ( 0x80 )
+
+/* Macro to unmask all interrupt priorities. */
+#define portCLEAR_INTERRUPT_MASK() \
+{ \
+ portDISABLE_INTERRUPTS(); \
+ portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
+ __asm volatile ( "DSB SY \n" \
+ "ISB SY \n" ); \
+ portENABLE_INTERRUPTS(); \
+}
+
+/* Hardware specifics used when sanity checking the configuration. */
+#define portINTERRUPT_PRIORITY_REGISTER_OFFSET 0x400UL
+#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
+#define portBIT_0_SET ( ( uint8_t ) 0x01 )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Starts the first task executing. This function is necessarily written in
+ * assembly code so is implemented in portASM.s.
+ */
+extern void vPortRestoreTaskContext( void );
+
+/*-----------------------------------------------------------*/
+
+/* A variable is used to keep track of the critical section nesting. This
+variable has to be stored as part of the task context and must be initialised to
+a non zero value to ensure interrupts don't inadvertently become unmasked before
+the scheduler starts. As it is stored as part of the task context it will
+automatically be set to 0 when the first task is started. */
+volatile uint64_t ullCriticalNesting = 9999ULL;
+
+/* Saved as part of the task context. If ullPortTaskHasFPUContext is non-zero
+then floating point context must be saved and restored for the task. */
+uint64_t ullPortTaskHasFPUContext = pdFALSE;
+
+/* Set to 1 to pend a context switch from an ISR. */
+uint64_t ullPortYieldRequired = pdFALSE;
+
+/* Counts the interrupt nesting depth. A context switch is only performed if
+if the nesting depth is 0. */
+uint64_t ullPortInterruptNesting = 0;
+
+/* Used in the ASM code. */
+__attribute__(( used )) const uint64_t ullICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
+__attribute__(( used )) const uint64_t ullICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
+__attribute__(( used )) const uint64_t ullICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
+__attribute__(( used )) const uint64_t ullMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+ /* Setup the initial stack of the task. The stack is set exactly as
+ expected by the portRESTORE_CONTEXT() macro. */
+
+ /* First all the general purpose registers. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x0101010101010101ULL; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x0303030303030303ULL; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x0202020202020202ULL; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x0505050505050505ULL; /* R5 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x0404040404040404ULL; /* R4 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x0707070707070707ULL; /* R7 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x0606060606060606ULL; /* R6 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x0909090909090909ULL; /* R9 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x0808080808080808ULL; /* R8 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x1111111111111111ULL; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x1010101010101010ULL; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x1313131313131313ULL; /* R13 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x1212121212121212ULL; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x1515151515151515ULL; /* R15 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x1414141414141414ULL; /* R14 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x1717171717171717ULL; /* R17 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x1616161616161616ULL; /* R16 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x1919191919191919ULL; /* R19 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x1818181818181818ULL; /* R18 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2121212121212121ULL; /* R21 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2020202020202020ULL; /* R20 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2323232323232323ULL; /* R23 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2222222222222222ULL; /* R22 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2525252525252525ULL; /* R25 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2424242424242424ULL; /* R24 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2727272727272727ULL; /* R27 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2626262626262626ULL; /* R26 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2929292929292929ULL; /* R29 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2828282828282828ULL; /* R28 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x00; /* XZR - has no effect, used so there are an even number of registers. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x00; /* R30 - procedure call link register. */
+ pxTopOfStack--;
+
+ *pxTopOfStack = portINITIAL_PSTATE;
+ pxTopOfStack--;
+
+ *pxTopOfStack = ( StackType_t ) pxCode; /* Exception return address. */
+ pxTopOfStack--;
+
+ /* The task will start with a critical nesting count of 0 as interrupts are
+ enabled. */
+ *pxTopOfStack = portNO_CRITICAL_NESTING;
+ pxTopOfStack--;
+
+ /* The task will start without a floating point context. A task that uses
+ the floating point hardware must call vPortTaskUsesFPU() before executing
+ any floating point instructions. */
+ *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+uint32_t ulAPSR;
+
+ #if( configASSERT_DEFINED == 1 )
+ {
+ volatile uint32_t ulOriginalPriority;
+ volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine how many priority bits are implemented in the GIC.
+
+ Save the interrupt priority value that is about to be clobbered. */
+ ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+ /* Determine the number of priority bits available. First write to
+ all possible bits. */
+ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+ /* Shift to the least significant bits. */
+ while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET )
+ {
+ ucMaxPriorityValue >>= ( uint8_t ) 0x01;
+ }
+
+ /* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
+ value. */
+
+ configASSERT( ucMaxPriorityValue >= portLOWEST_INTERRUPT_PRIORITY );
+
+
+ /* Restore the clobbered interrupt priority register to its original
+ value. */
+ *pucFirstUserPriorityRegister = ulOriginalPriority;
+ }
+ #endif /* configASSERT_DEFINED */
+
+
+ /* At the time of writing, the BSP only supports EL3. */
+ __asm volatile ( "MRS %0, CurrentEL" : "=r" ( ulAPSR ) );
+ ulAPSR &= portAPSR_MODE_BITS_MASK;
+
+#if defined( GUEST )
+ #warning Building for execution as a guest under XEN. THIS IS NOT A FULLY TESTED PATH.
+ configASSERT( ulAPSR == portEL1 );
+ if( ulAPSR == portEL1 )
+#else
+ configASSERT( ulAPSR == portEL3 );
+ if( ulAPSR == portEL3 )
+#endif
+ {
+ /* Only continue if the binary point value is set to its lowest possible
+ setting. See the comments in vPortValidateInterruptPriority() below for
+ more information. */
+ configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
+
+ if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
+ {
+ /* Interrupts are turned off in the CPU itself to ensure a tick does
+ not execute while the scheduler is being started. Interrupts are
+ automatically turned back on in the CPU when the first task starts
+ executing. */
+ portDISABLE_INTERRUPTS();
+
+ /* Start the timer that generates the tick ISR. */
+ configSETUP_TICK_INTERRUPT();
+
+ /* Start the first task executing. */
+ vPortRestoreTaskContext();
+ }
+ }
+
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+ /* Not implemented in ports where there is nothing to return to.
+ Artificially force an assert. */
+ configASSERT( ullCriticalNesting == 1000ULL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+ /* Mask interrupts up to the max syscall interrupt priority. */
+ uxPortSetInterruptMask();
+
+ /* Now interrupts are disabled ullCriticalNesting can be accessed
+ directly. Increment ullCriticalNesting to keep a count of how many times
+ portENTER_CRITICAL() has been called. */
+ ullCriticalNesting++;
+
+ /* This is not the interrupt safe version of the enter critical function so
+ assert() if it is being called from an interrupt context. Only API
+ functions that end in "FromISR" can be used in an interrupt. Only assert if
+ the critical nesting count is 1 to protect against recursive calls if the
+ assert function also uses a critical section. */
+ if( ullCriticalNesting == 1ULL )
+ {
+ configASSERT( ullPortInterruptNesting == 0 );
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+ if( ullCriticalNesting > portNO_CRITICAL_NESTING )
+ {
+ /* Decrement the nesting count as the critical section is being
+ exited. */
+ ullCriticalNesting--;
+
+ /* If the nesting level has reached zero then all interrupt
+ priorities must be re-enabled. */
+ if( ullCriticalNesting == portNO_CRITICAL_NESTING )
+ {
+ /* Critical nesting has reached zero so all interrupt priorities
+ should be unmasked. */
+ portCLEAR_INTERRUPT_MASK();
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+void FreeRTOS_Tick_Handler( void )
+{
+ /* Must be the lowest possible priority. */
+ #if !defined( QEMU )
+ {
+ configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER == ( uint32_t ) ( portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
+ }
+ #endif
+
+ /* Interrupts should not be enabled before this point. */
+ #if( configASSERT_DEFINED == 1 )
+ {
+ uint32_t ulMaskBits;
+
+ __asm volatile( "mrs %0, daif" : "=r"( ulMaskBits ) :: "memory" );
+ configASSERT( ( ulMaskBits & portDAIF_I ) != 0 );
+ }
+ #endif /* configASSERT_DEFINED */
+
+ /* Set interrupt mask before altering scheduler structures. The tick
+ handler runs at the lowest priority, so interrupts cannot already be masked,
+ so there is no need to save and restore the current mask value. It is
+ necessary to turn off interrupts in the CPU itself while the ICCPMR is being
+ updated. */
+ portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+ __asm volatile ( "dsb sy \n"
+ "isb sy \n" ::: "memory" );
+
+ /* Ok to enable interrupts after the interrupt source has been cleared. */
+ configCLEAR_TICK_INTERRUPT();
+ portENABLE_INTERRUPTS();
+
+ /* Increment the RTOS tick. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ ullPortYieldRequired = pdTRUE;
+ }
+
+ /* Ensure all interrupt priorities are active again. */
+ portCLEAR_INTERRUPT_MASK();
+}
+/*-----------------------------------------------------------*/
+
+void vPortTaskUsesFPU( void )
+{
+ /* A task is registering the fact that it needs an FPU context. Set the
+ FPU flag (which is saved as part of the task context). */
+ ullPortTaskHasFPUContext = pdTRUE;
+
+ /* Consider initialising the FPSR here - but probably not necessary in
+ AArch64. */
+}
+/*-----------------------------------------------------------*/
+
+void vPortClearInterruptMask( UBaseType_t uxNewMaskValue )
+{
+ if( uxNewMaskValue == pdFALSE )
+ {
+ portCLEAR_INTERRUPT_MASK();
+ }
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxPortSetInterruptMask( void )
+{
+uint32_t ulReturn;
+
+ /* Interrupt in the CPU must be turned off while the ICCPMR is being
+ updated. */
+ portDISABLE_INTERRUPTS();
+ if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
+ {
+ /* Interrupts were already masked. */
+ ulReturn = pdTRUE;
+ }
+ else
+ {
+ ulReturn = pdFALSE;
+ portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+ __asm volatile ( "dsb sy \n"
+ "isb sy \n" ::: "memory" );
+ }
+ portENABLE_INTERRUPTS();
+
+ return ulReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if( configASSERT_DEFINED == 1 )
+
+ void vPortValidateInterruptPriority( void )
+ {
+ /* The following assertion will fail if a service routine (ISR) for
+ an interrupt that has been assigned a priority above
+ configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+ function. ISR safe FreeRTOS API functions must *only* be called
+ from interrupts that have been assigned a priority at or below
+ configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+ Numerically low interrupt priority numbers represent logically high
+ interrupt priorities, therefore the priority of the interrupt must
+ be set to a value equal to or numerically *higher* than
+ configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+ FreeRTOS maintains separate thread and ISR API functions to ensure
+ interrupt entry is as fast and simple as possible. */
+ configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
+
+ /* Priority grouping: The interrupt controller (GIC) allows the bits
+ that define each interrupt's priority to be split between bits that
+ define the interrupt's pre-emption priority bits and bits that define
+ the interrupt's sub-priority. For simplicity all bits must be defined
+ to be pre-emption priority bits. The following assertion will fail if
+ this is not the case (if some bits represent a sub-priority).
+
+ The priority grouping is configured by the GIC's binary point register
+ (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest
+ possible value (which may be above 0). */
+ configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
+ }
+
+#endif /* configASSERT_DEFINED */
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CA53_64_BIT/portASM.S b/portable/GCC/ARM_CA53_64_BIT/portASM.S
index 8a7cf79..c98cadb 100644
--- a/portable/GCC/ARM_CA53_64_BIT/portASM.S
+++ b/portable/GCC/ARM_CA53_64_BIT/portASM.S
@@ -1,432 +1,427 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
- .text
-
- /* Variables and functions. */
- .extern ullMaxAPIPriorityMask
- .extern pxCurrentTCB
- .extern vTaskSwitchContext
- .extern vApplicationIRQHandler
- .extern ullPortInterruptNesting
- .extern ullPortTaskHasFPUContext
- .extern ullCriticalNesting
- .extern ullPortYieldRequired
- .extern ullICCEOIR
- .extern ullICCIAR
- .extern _freertos_vector_table
-
- .global FreeRTOS_IRQ_Handler
- .global FreeRTOS_SWI_Handler
- .global vPortRestoreTaskContext
-
-
-.macro portSAVE_CONTEXT
-
- /* Switch to use the EL0 stack pointer. */
- MSR SPSEL, #0
-
- /* Save the entire context. */
- STP X0, X1, [SP, #-0x10]!
- STP X2, X3, [SP, #-0x10]!
- STP X4, X5, [SP, #-0x10]!
- STP X6, X7, [SP, #-0x10]!
- STP X8, X9, [SP, #-0x10]!
- STP X10, X11, [SP, #-0x10]!
- STP X12, X13, [SP, #-0x10]!
- STP X14, X15, [SP, #-0x10]!
- STP X16, X17, [SP, #-0x10]!
- STP X18, X19, [SP, #-0x10]!
- STP X20, X21, [SP, #-0x10]!
- STP X22, X23, [SP, #-0x10]!
- STP X24, X25, [SP, #-0x10]!
- STP X26, X27, [SP, #-0x10]!
- STP X28, X29, [SP, #-0x10]!
- STP X30, XZR, [SP, #-0x10]!
-
- /* Save the SPSR. */
-#if defined( GUEST )
- MRS X3, SPSR_EL1
- MRS X2, ELR_EL1
-#else
- MRS X3, SPSR_EL3
- /* Save the ELR. */
- MRS X2, ELR_EL3
-#endif
-
- STP X2, X3, [SP, #-0x10]!
-
- /* Save the critical section nesting depth. */
- LDR X0, ullCriticalNestingConst
- LDR X3, [X0]
-
- /* Save the FPU context indicator. */
- LDR X0, ullPortTaskHasFPUContextConst
- LDR X2, [X0]
-
- /* Save the FPU context, if any (32 128-bit registers). */
- CMP X2, #0
- B.EQ 1f
- STP Q0, Q1, [SP,#-0x20]!
- STP Q2, Q3, [SP,#-0x20]!
- STP Q4, Q5, [SP,#-0x20]!
- STP Q6, Q7, [SP,#-0x20]!
- STP Q8, Q9, [SP,#-0x20]!
- STP Q10, Q11, [SP,#-0x20]!
- STP Q12, Q13, [SP,#-0x20]!
- STP Q14, Q15, [SP,#-0x20]!
- STP Q16, Q17, [SP,#-0x20]!
- STP Q18, Q19, [SP,#-0x20]!
- STP Q20, Q21, [SP,#-0x20]!
- STP Q22, Q23, [SP,#-0x20]!
- STP Q24, Q25, [SP,#-0x20]!
- STP Q26, Q27, [SP,#-0x20]!
- STP Q28, Q29, [SP,#-0x20]!
- STP Q30, Q31, [SP,#-0x20]!
-
-1:
- /* Store the critical nesting count and FPU context indicator. */
- STP X2, X3, [SP, #-0x10]!
-
- LDR X0, pxCurrentTCBConst
- LDR X1, [X0]
- MOV X0, SP /* Move SP into X0 for saving. */
- STR X0, [X1]
-
- /* Switch to use the ELx stack pointer. */
- MSR SPSEL, #1
-
- .endm
-
-; /**********************************************************************/
-
-.macro portRESTORE_CONTEXT
-
- /* Switch to use the EL0 stack pointer. */
- MSR SPSEL, #0
-
- /* Set the SP to point to the stack of the task being restored. */
- LDR X0, pxCurrentTCBConst
- LDR X1, [X0]
- LDR X0, [X1]
- MOV SP, X0
-
- LDP X2, X3, [SP], #0x10 /* Critical nesting and FPU context. */
-
- /* Set the PMR register to be correct for the current critical nesting
- depth. */
- LDR X0, ullCriticalNestingConst /* X0 holds the address of ullCriticalNesting. */
- MOV X1, #255 /* X1 holds the unmask value. */
- LDR X4, ullICCPMRConst /* X4 holds the address of the ICCPMR constant. */
- CMP X3, #0
- LDR X5, [X4] /* X5 holds the address of the ICCPMR register. */
- B.EQ 1f
- LDR X6, ullMaxAPIPriorityMaskConst
- LDR X1, [X6] /* X1 holds the mask value. */
-1:
- STR W1, [X5] /* Write the mask value to ICCPMR. */
- DSB SY /* _RB_Barriers probably not required here. */
- ISB SY
- STR X3, [X0] /* Restore the task's critical nesting count. */
-
- /* Restore the FPU context indicator. */
- LDR X0, ullPortTaskHasFPUContextConst
- STR X2, [X0]
-
- /* Restore the FPU context, if any. */
- CMP X2, #0
- B.EQ 1f
- LDP Q30, Q31, [SP], #0x20
- LDP Q28, Q29, [SP], #0x20
- LDP Q26, Q27, [SP], #0x20
- LDP Q24, Q25, [SP], #0x20
- LDP Q22, Q23, [SP], #0x20
- LDP Q20, Q21, [SP], #0x20
- LDP Q18, Q19, [SP], #0x20
- LDP Q16, Q17, [SP], #0x20
- LDP Q14, Q15, [SP], #0x20
- LDP Q12, Q13, [SP], #0x20
- LDP Q10, Q11, [SP], #0x20
- LDP Q8, Q9, [SP], #0x20
- LDP Q6, Q7, [SP], #0x20
- LDP Q4, Q5, [SP], #0x20
- LDP Q2, Q3, [SP], #0x20
- LDP Q0, Q1, [SP], #0x20
-1:
- LDP X2, X3, [SP], #0x10 /* SPSR and ELR. */
-
-#if defined( GUEST )
- /* Restore the SPSR. */
- MSR SPSR_EL1, X3
- /* Restore the ELR. */
- MSR ELR_EL1, X2
-#else
- /* Restore the SPSR. */
- MSR SPSR_EL3, X3 /*_RB_ Assumes started in EL3. */
- /* Restore the ELR. */
- MSR ELR_EL3, X2
-#endif
-
- LDP X30, XZR, [SP], #0x10
- LDP X28, X29, [SP], #0x10
- LDP X26, X27, [SP], #0x10
- LDP X24, X25, [SP], #0x10
- LDP X22, X23, [SP], #0x10
- LDP X20, X21, [SP], #0x10
- LDP X18, X19, [SP], #0x10
- LDP X16, X17, [SP], #0x10
- LDP X14, X15, [SP], #0x10
- LDP X12, X13, [SP], #0x10
- LDP X10, X11, [SP], #0x10
- LDP X8, X9, [SP], #0x10
- LDP X6, X7, [SP], #0x10
- LDP X4, X5, [SP], #0x10
- LDP X2, X3, [SP], #0x10
- LDP X0, X1, [SP], #0x10
-
- /* Switch to use the ELx stack pointer. _RB_ Might not be required. */
- MSR SPSEL, #1
-
- ERET
-
- .endm
-
-
-/******************************************************************************
- * FreeRTOS_SWI_Handler handler is used to perform a context switch.
- *****************************************************************************/
-.align 8
-.type FreeRTOS_SWI_Handler, %function
-FreeRTOS_SWI_Handler:
- /* Save the context of the current task and select a new task to run. */
- portSAVE_CONTEXT
-#if defined( GUEST )
- MRS X0, ESR_EL1
-#else
- MRS X0, ESR_EL3
-#endif
-
- LSR X1, X0, #26
-
-#if defined( GUEST )
- CMP X1, #0x15 /* 0x15 = SVC instruction. */
-#else
- CMP X1, #0x17 /* 0x17 = SMC instruction. */
-#endif
- B.NE FreeRTOS_Abort
- BL vTaskSwitchContext
-
- portRESTORE_CONTEXT
-
-FreeRTOS_Abort:
- /* Full ESR is in X0, exception class code is in X1. */
- B .
-
-/******************************************************************************
- * vPortRestoreTaskContext is used to start the scheduler.
- *****************************************************************************/
-.align 8
-.type vPortRestoreTaskContext, %function
-vPortRestoreTaskContext:
-.set freertos_vector_base, _freertos_vector_table
-
- /* Install the FreeRTOS interrupt handlers. */
- LDR X1, =freertos_vector_base
-#if defined( GUEST )
- MSR VBAR_EL1, X1
-#else
- MSR VBAR_EL3, X1
-#endif
- DSB SY
- ISB SY
-
- /* Start the first task. */
- portRESTORE_CONTEXT
-
-
-/******************************************************************************
- * FreeRTOS_IRQ_Handler handles IRQ entry and exit.
- *****************************************************************************/
-.align 8
-.type FreeRTOS_IRQ_Handler, %function
-FreeRTOS_IRQ_Handler:
- /* Save volatile registers. */
- STP X0, X1, [SP, #-0x10]!
- STP X2, X3, [SP, #-0x10]!
- STP X4, X5, [SP, #-0x10]!
- STP X6, X7, [SP, #-0x10]!
- STP X8, X9, [SP, #-0x10]!
- STP X10, X11, [SP, #-0x10]!
- STP X12, X13, [SP, #-0x10]!
- STP X14, X15, [SP, #-0x10]!
- STP X16, X17, [SP, #-0x10]!
- STP X18, X19, [SP, #-0x10]!
- STP X29, X30, [SP, #-0x10]!
-
- /* Save the SPSR and ELR. */
-#if defined( GUEST )
- MRS X3, SPSR_EL1
- MRS X2, ELR_EL1
-#else
- MRS X3, SPSR_EL3
- MRS X2, ELR_EL3
-#endif
- STP X2, X3, [SP, #-0x10]!
-
- /* Increment the interrupt nesting counter. */
- LDR X5, ullPortInterruptNestingConst
- LDR X1, [X5] /* Old nesting count in X1. */
- ADD X6, X1, #1
- STR X6, [X5] /* Address of nesting count variable in X5. */
-
- /* Maintain the interrupt nesting information across the function call. */
- STP X1, X5, [SP, #-0x10]!
-
- /* Read value from the interrupt acknowledge register, which is stored in W0
- for future parameter and interrupt clearing use. */
- LDR X2, ullICCIARConst
- LDR X3, [X2]
- LDR W0, [X3] /* ICCIAR in W0 as parameter. */
-
- /* Maintain the ICCIAR value across the function call. */
- STP X0, X1, [SP, #-0x10]!
-
- /* Call the C handler. */
- BL vApplicationIRQHandler
-
- /* Disable interrupts. */
- MSR DAIFSET, #2
- DSB SY
- ISB SY
-
- /* Restore the ICCIAR value. */
- LDP X0, X1, [SP], #0x10
-
- /* End IRQ processing by writing ICCIAR to the EOI register. */
- LDR X4, ullICCEOIRConst
- LDR X4, [X4]
- STR W0, [X4]
-
- /* Restore the critical nesting count. */
- LDP X1, X5, [SP], #0x10
- STR X1, [X5]
-
- /* Has interrupt nesting unwound? */
- CMP X1, #0
- B.NE Exit_IRQ_No_Context_Switch
-
- /* Is a context switch required? */
- LDR X0, ullPortYieldRequiredConst
- LDR X1, [X0]
- CMP X1, #0
- B.EQ Exit_IRQ_No_Context_Switch
-
- /* Reset ullPortYieldRequired to 0. */
- MOV X2, #0
- STR X2, [X0]
-
- /* Restore volatile registers. */
- LDP X4, X5, [SP], #0x10 /* SPSR and ELR. */
-#if defined( GUEST )
- MSR SPSR_EL1, X5
- MSR ELR_EL1, X4
-#else
- MSR SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */
- MSR ELR_EL3, X4
-#endif
- DSB SY
- ISB SY
-
- LDP X29, X30, [SP], #0x10
- LDP X18, X19, [SP], #0x10
- LDP X16, X17, [SP], #0x10
- LDP X14, X15, [SP], #0x10
- LDP X12, X13, [SP], #0x10
- LDP X10, X11, [SP], #0x10
- LDP X8, X9, [SP], #0x10
- LDP X6, X7, [SP], #0x10
- LDP X4, X5, [SP], #0x10
- LDP X2, X3, [SP], #0x10
- LDP X0, X1, [SP], #0x10
-
- /* Save the context of the current task and select a new task to run. */
- portSAVE_CONTEXT
- BL vTaskSwitchContext
- portRESTORE_CONTEXT
-
-Exit_IRQ_No_Context_Switch:
- /* Restore volatile registers. */
- LDP X4, X5, [SP], #0x10 /* SPSR and ELR. */
-#if defined( GUEST )
- MSR SPSR_EL1, X5
- MSR ELR_EL1, X4
-#else
- MSR SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */
- MSR ELR_EL3, X4
-#endif
- DSB SY
- ISB SY
-
- LDP X29, X30, [SP], #0x10
- LDP X18, X19, [SP], #0x10
- LDP X16, X17, [SP], #0x10
- LDP X14, X15, [SP], #0x10
- LDP X12, X13, [SP], #0x10
- LDP X10, X11, [SP], #0x10
- LDP X8, X9, [SP], #0x10
- LDP X6, X7, [SP], #0x10
- LDP X4, X5, [SP], #0x10
- LDP X2, X3, [SP], #0x10
- LDP X0, X1, [SP], #0x10
-
- ERET
-
-
-
-
-.align 8
-pxCurrentTCBConst: .dword pxCurrentTCB
-ullCriticalNestingConst: .dword ullCriticalNesting
-ullPortTaskHasFPUContextConst: .dword ullPortTaskHasFPUContext
-
-ullICCPMRConst: .dword ullICCPMR
-ullMaxAPIPriorityMaskConst: .dword ullMaxAPIPriorityMask
-ullPortInterruptNestingConst: .dword ullPortInterruptNesting
-ullPortYieldRequiredConst: .dword ullPortYieldRequired
-ullICCIARConst: .dword ullICCIAR
-ullICCEOIRConst: .dword ullICCEOIR
-vApplicationIRQHandlerConst: .word vApplicationIRQHandler
-
-
-
-.end
-
-
-
-
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+ .text
+
+ /* Variables and functions. */
+ .extern ullMaxAPIPriorityMask
+ .extern pxCurrentTCB
+ .extern vTaskSwitchContext
+ .extern vApplicationIRQHandler
+ .extern ullPortInterruptNesting
+ .extern ullPortTaskHasFPUContext
+ .extern ullCriticalNesting
+ .extern ullPortYieldRequired
+ .extern ullICCEOIR
+ .extern ullICCIAR
+ .extern _freertos_vector_table
+
+ .global FreeRTOS_IRQ_Handler
+ .global FreeRTOS_SWI_Handler
+ .global vPortRestoreTaskContext
+
+
+.macro portSAVE_CONTEXT
+
+ /* Switch to use the EL0 stack pointer. */
+ MSR SPSEL, #0
+
+ /* Save the entire context. */
+ STP X0, X1, [SP, #-0x10]!
+ STP X2, X3, [SP, #-0x10]!
+ STP X4, X5, [SP, #-0x10]!
+ STP X6, X7, [SP, #-0x10]!
+ STP X8, X9, [SP, #-0x10]!
+ STP X10, X11, [SP, #-0x10]!
+ STP X12, X13, [SP, #-0x10]!
+ STP X14, X15, [SP, #-0x10]!
+ STP X16, X17, [SP, #-0x10]!
+ STP X18, X19, [SP, #-0x10]!
+ STP X20, X21, [SP, #-0x10]!
+ STP X22, X23, [SP, #-0x10]!
+ STP X24, X25, [SP, #-0x10]!
+ STP X26, X27, [SP, #-0x10]!
+ STP X28, X29, [SP, #-0x10]!
+ STP X30, XZR, [SP, #-0x10]!
+
+ /* Save the SPSR. */
+#if defined( GUEST )
+ MRS X3, SPSR_EL1
+ MRS X2, ELR_EL1
+#else
+ MRS X3, SPSR_EL3
+ /* Save the ELR. */
+ MRS X2, ELR_EL3
+#endif
+
+ STP X2, X3, [SP, #-0x10]!
+
+ /* Save the critical section nesting depth. */
+ LDR X0, ullCriticalNestingConst
+ LDR X3, [X0]
+
+ /* Save the FPU context indicator. */
+ LDR X0, ullPortTaskHasFPUContextConst
+ LDR X2, [X0]
+
+ /* Save the FPU context, if any (32 128-bit registers). */
+ CMP X2, #0
+ B.EQ 1f
+ STP Q0, Q1, [SP,#-0x20]!
+ STP Q2, Q3, [SP,#-0x20]!
+ STP Q4, Q5, [SP,#-0x20]!
+ STP Q6, Q7, [SP,#-0x20]!
+ STP Q8, Q9, [SP,#-0x20]!
+ STP Q10, Q11, [SP,#-0x20]!
+ STP Q12, Q13, [SP,#-0x20]!
+ STP Q14, Q15, [SP,#-0x20]!
+ STP Q16, Q17, [SP,#-0x20]!
+ STP Q18, Q19, [SP,#-0x20]!
+ STP Q20, Q21, [SP,#-0x20]!
+ STP Q22, Q23, [SP,#-0x20]!
+ STP Q24, Q25, [SP,#-0x20]!
+ STP Q26, Q27, [SP,#-0x20]!
+ STP Q28, Q29, [SP,#-0x20]!
+ STP Q30, Q31, [SP,#-0x20]!
+
+1:
+ /* Store the critical nesting count and FPU context indicator. */
+ STP X2, X3, [SP, #-0x10]!
+
+ LDR X0, pxCurrentTCBConst
+ LDR X1, [X0]
+ MOV X0, SP /* Move SP into X0 for saving. */
+ STR X0, [X1]
+
+ /* Switch to use the ELx stack pointer. */
+ MSR SPSEL, #1
+
+ .endm
+
+; /**********************************************************************/
+
+.macro portRESTORE_CONTEXT
+
+ /* Switch to use the EL0 stack pointer. */
+ MSR SPSEL, #0
+
+ /* Set the SP to point to the stack of the task being restored. */
+ LDR X0, pxCurrentTCBConst
+ LDR X1, [X0]
+ LDR X0, [X1]
+ MOV SP, X0
+
+ LDP X2, X3, [SP], #0x10 /* Critical nesting and FPU context. */
+
+ /* Set the PMR register to be correct for the current critical nesting
+ depth. */
+ LDR X0, ullCriticalNestingConst /* X0 holds the address of ullCriticalNesting. */
+ MOV X1, #255 /* X1 holds the unmask value. */
+ LDR X4, ullICCPMRConst /* X4 holds the address of the ICCPMR constant. */
+ CMP X3, #0
+ LDR X5, [X4] /* X5 holds the address of the ICCPMR register. */
+ B.EQ 1f
+ LDR X6, ullMaxAPIPriorityMaskConst
+ LDR X1, [X6] /* X1 holds the mask value. */
+1:
+ STR W1, [X5] /* Write the mask value to ICCPMR. */
+ DSB SY /* _RB_Barriers probably not required here. */
+ ISB SY
+ STR X3, [X0] /* Restore the task's critical nesting count. */
+
+ /* Restore the FPU context indicator. */
+ LDR X0, ullPortTaskHasFPUContextConst
+ STR X2, [X0]
+
+ /* Restore the FPU context, if any. */
+ CMP X2, #0
+ B.EQ 1f
+ LDP Q30, Q31, [SP], #0x20
+ LDP Q28, Q29, [SP], #0x20
+ LDP Q26, Q27, [SP], #0x20
+ LDP Q24, Q25, [SP], #0x20
+ LDP Q22, Q23, [SP], #0x20
+ LDP Q20, Q21, [SP], #0x20
+ LDP Q18, Q19, [SP], #0x20
+ LDP Q16, Q17, [SP], #0x20
+ LDP Q14, Q15, [SP], #0x20
+ LDP Q12, Q13, [SP], #0x20
+ LDP Q10, Q11, [SP], #0x20
+ LDP Q8, Q9, [SP], #0x20
+ LDP Q6, Q7, [SP], #0x20
+ LDP Q4, Q5, [SP], #0x20
+ LDP Q2, Q3, [SP], #0x20
+ LDP Q0, Q1, [SP], #0x20
+1:
+ LDP X2, X3, [SP], #0x10 /* SPSR and ELR. */
+
+#if defined( GUEST )
+ /* Restore the SPSR. */
+ MSR SPSR_EL1, X3
+ /* Restore the ELR. */
+ MSR ELR_EL1, X2
+#else
+ /* Restore the SPSR. */
+ MSR SPSR_EL3, X3 /*_RB_ Assumes started in EL3. */
+ /* Restore the ELR. */
+ MSR ELR_EL3, X2
+#endif
+
+ LDP X30, XZR, [SP], #0x10
+ LDP X28, X29, [SP], #0x10
+ LDP X26, X27, [SP], #0x10
+ LDP X24, X25, [SP], #0x10
+ LDP X22, X23, [SP], #0x10
+ LDP X20, X21, [SP], #0x10
+ LDP X18, X19, [SP], #0x10
+ LDP X16, X17, [SP], #0x10
+ LDP X14, X15, [SP], #0x10
+ LDP X12, X13, [SP], #0x10
+ LDP X10, X11, [SP], #0x10
+ LDP X8, X9, [SP], #0x10
+ LDP X6, X7, [SP], #0x10
+ LDP X4, X5, [SP], #0x10
+ LDP X2, X3, [SP], #0x10
+ LDP X0, X1, [SP], #0x10
+
+ /* Switch to use the ELx stack pointer. _RB_ Might not be required. */
+ MSR SPSEL, #1
+
+ ERET
+
+ .endm
+
+
+/******************************************************************************
+ * FreeRTOS_SWI_Handler handler is used to perform a context switch.
+ *****************************************************************************/
+.align 8
+.type FreeRTOS_SWI_Handler, %function
+FreeRTOS_SWI_Handler:
+ /* Save the context of the current task and select a new task to run. */
+ portSAVE_CONTEXT
+#if defined( GUEST )
+ MRS X0, ESR_EL1
+#else
+ MRS X0, ESR_EL3
+#endif
+
+ LSR X1, X0, #26
+
+#if defined( GUEST )
+ CMP X1, #0x15 /* 0x15 = SVC instruction. */
+#else
+ CMP X1, #0x17 /* 0x17 = SMC instruction. */
+#endif
+ B.NE FreeRTOS_Abort
+ BL vTaskSwitchContext
+
+ portRESTORE_CONTEXT
+
+FreeRTOS_Abort:
+ /* Full ESR is in X0, exception class code is in X1. */
+ B .
+
+/******************************************************************************
+ * vPortRestoreTaskContext is used to start the scheduler.
+ *****************************************************************************/
+.align 8
+.type vPortRestoreTaskContext, %function
+vPortRestoreTaskContext:
+.set freertos_vector_base, _freertos_vector_table
+
+ /* Install the FreeRTOS interrupt handlers. */
+ LDR X1, =freertos_vector_base
+#if defined( GUEST )
+ MSR VBAR_EL1, X1
+#else
+ MSR VBAR_EL3, X1
+#endif
+ DSB SY
+ ISB SY
+
+ /* Start the first task. */
+ portRESTORE_CONTEXT
+
+
+/******************************************************************************
+ * FreeRTOS_IRQ_Handler handles IRQ entry and exit.
+ *****************************************************************************/
+.align 8
+.type FreeRTOS_IRQ_Handler, %function
+FreeRTOS_IRQ_Handler:
+ /* Save volatile registers. */
+ STP X0, X1, [SP, #-0x10]!
+ STP X2, X3, [SP, #-0x10]!
+ STP X4, X5, [SP, #-0x10]!
+ STP X6, X7, [SP, #-0x10]!
+ STP X8, X9, [SP, #-0x10]!
+ STP X10, X11, [SP, #-0x10]!
+ STP X12, X13, [SP, #-0x10]!
+ STP X14, X15, [SP, #-0x10]!
+ STP X16, X17, [SP, #-0x10]!
+ STP X18, X19, [SP, #-0x10]!
+ STP X29, X30, [SP, #-0x10]!
+
+ /* Save the SPSR and ELR. */
+#if defined( GUEST )
+ MRS X3, SPSR_EL1
+ MRS X2, ELR_EL1
+#else
+ MRS X3, SPSR_EL3
+ MRS X2, ELR_EL3
+#endif
+ STP X2, X3, [SP, #-0x10]!
+
+ /* Increment the interrupt nesting counter. */
+ LDR X5, ullPortInterruptNestingConst
+ LDR X1, [X5] /* Old nesting count in X1. */
+ ADD X6, X1, #1
+ STR X6, [X5] /* Address of nesting count variable in X5. */
+
+ /* Maintain the interrupt nesting information across the function call. */
+ STP X1, X5, [SP, #-0x10]!
+
+ /* Read value from the interrupt acknowledge register, which is stored in W0
+ for future parameter and interrupt clearing use. */
+ LDR X2, ullICCIARConst
+ LDR X3, [X2]
+ LDR W0, [X3] /* ICCIAR in W0 as parameter. */
+
+ /* Maintain the ICCIAR value across the function call. */
+ STP X0, X1, [SP, #-0x10]!
+
+ /* Call the C handler. */
+ BL vApplicationIRQHandler
+
+ /* Disable interrupts. */
+ MSR DAIFSET, #2
+ DSB SY
+ ISB SY
+
+ /* Restore the ICCIAR value. */
+ LDP X0, X1, [SP], #0x10
+
+ /* End IRQ processing by writing ICCIAR to the EOI register. */
+ LDR X4, ullICCEOIRConst
+ LDR X4, [X4]
+ STR W0, [X4]
+
+ /* Restore the critical nesting count. */
+ LDP X1, X5, [SP], #0x10
+ STR X1, [X5]
+
+ /* Has interrupt nesting unwound? */
+ CMP X1, #0
+ B.NE Exit_IRQ_No_Context_Switch
+
+ /* Is a context switch required? */
+ LDR X0, ullPortYieldRequiredConst
+ LDR X1, [X0]
+ CMP X1, #0
+ B.EQ Exit_IRQ_No_Context_Switch
+
+ /* Reset ullPortYieldRequired to 0. */
+ MOV X2, #0
+ STR X2, [X0]
+
+ /* Restore volatile registers. */
+ LDP X4, X5, [SP], #0x10 /* SPSR and ELR. */
+#if defined( GUEST )
+ MSR SPSR_EL1, X5
+ MSR ELR_EL1, X4
+#else
+ MSR SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */
+ MSR ELR_EL3, X4
+#endif
+ DSB SY
+ ISB SY
+
+ LDP X29, X30, [SP], #0x10
+ LDP X18, X19, [SP], #0x10
+ LDP X16, X17, [SP], #0x10
+ LDP X14, X15, [SP], #0x10
+ LDP X12, X13, [SP], #0x10
+ LDP X10, X11, [SP], #0x10
+ LDP X8, X9, [SP], #0x10
+ LDP X6, X7, [SP], #0x10
+ LDP X4, X5, [SP], #0x10
+ LDP X2, X3, [SP], #0x10
+ LDP X0, X1, [SP], #0x10
+
+ /* Save the context of the current task and select a new task to run. */
+ portSAVE_CONTEXT
+ BL vTaskSwitchContext
+ portRESTORE_CONTEXT
+
+Exit_IRQ_No_Context_Switch:
+ /* Restore volatile registers. */
+ LDP X4, X5, [SP], #0x10 /* SPSR and ELR. */
+#if defined( GUEST )
+ MSR SPSR_EL1, X5
+ MSR ELR_EL1, X4
+#else
+ MSR SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */
+ MSR ELR_EL3, X4
+#endif
+ DSB SY
+ ISB SY
+
+ LDP X29, X30, [SP], #0x10
+ LDP X18, X19, [SP], #0x10
+ LDP X16, X17, [SP], #0x10
+ LDP X14, X15, [SP], #0x10
+ LDP X12, X13, [SP], #0x10
+ LDP X10, X11, [SP], #0x10
+ LDP X8, X9, [SP], #0x10
+ LDP X6, X7, [SP], #0x10
+ LDP X4, X5, [SP], #0x10
+ LDP X2, X3, [SP], #0x10
+ LDP X0, X1, [SP], #0x10
+
+ ERET
+
+
+
+
+.align 8
+pxCurrentTCBConst: .dword pxCurrentTCB
+ullCriticalNestingConst: .dword ullCriticalNesting
+ullPortTaskHasFPUContextConst: .dword ullPortTaskHasFPUContext
+
+ullICCPMRConst: .dword ullICCPMR
+ullMaxAPIPriorityMaskConst: .dword ullMaxAPIPriorityMask
+ullPortInterruptNestingConst: .dword ullPortInterruptNesting
+ullPortYieldRequiredConst: .dword ullPortYieldRequired
+ullICCIARConst: .dword ullICCIAR
+ullICCEOIRConst: .dword ullICCEOIR
+vApplicationIRQHandlerConst: .word vApplicationIRQHandler
+
+
+
+.end
diff --git a/portable/GCC/ARM_CA53_64_BIT/portmacro.h b/portable/GCC/ARM_CA53_64_BIT/portmacro.h
index b824c7d..1b2e277 100644
--- a/portable/GCC/ARM_CA53_64_BIT/portmacro.h
+++ b/portable/GCC/ARM_CA53_64_BIT/portmacro.h
@@ -1,212 +1,211 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT short
-#define portSTACK_TYPE size_t
-#define portBASE_TYPE long
-
-typedef portSTACK_TYPE StackType_t;
-typedef portBASE_TYPE BaseType_t;
-typedef uint64_t UBaseType_t;
-
-typedef uint64_t TickType_t;
-#define portMAX_DELAY ( ( TickType_t ) 0xffffffffffffffff )
-
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-not need to be guarded with a critical section. */
-#define portTICK_TYPE_IS_ATOMIC 1
-
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portSTACK_GROWTH ( -1 )
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT 16
-#define portPOINTER_SIZE_TYPE uint64_t
-
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-
-/* Called at the end of an ISR that can cause a context switch. */
-#define portEND_SWITCHING_ISR( xSwitchRequired )\
-{ \
-extern uint64_t ullPortYieldRequired; \
- \
- if( xSwitchRequired != pdFALSE ) \
- { \
- ullPortYieldRequired = pdTRUE; \
- } \
-}
-
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-#if defined( GUEST )
- #define portYIELD() __asm volatile ( "SVC 0" ::: "memory" )
-#else
- #define portYIELD() __asm volatile ( "SMC 0" ::: "memory" )
-#endif
-/*-----------------------------------------------------------
- * Critical section control
- *----------------------------------------------------------*/
-
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-extern UBaseType_t uxPortSetInterruptMask( void );
-extern void vPortClearInterruptMask( UBaseType_t uxNewMaskValue );
-extern void vPortInstallFreeRTOSVectorTable( void );
-
-#define portDISABLE_INTERRUPTS() \
- __asm volatile ( "MSR DAIFSET, #2" ::: "memory" ); \
- __asm volatile ( "DSB SY" ); \
- __asm volatile ( "ISB SY" );
-
-#define portENABLE_INTERRUPTS() \
- __asm volatile ( "MSR DAIFCLR, #2" ::: "memory" ); \
- __asm volatile ( "DSB SY" ); \
- __asm volatile ( "ISB SY" );
-
-
-/* These macros do not globally disable/enable interrupts. They do mask off
-interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
-#define portENTER_CRITICAL() vPortEnterCritical();
-#define portEXIT_CRITICAL() vPortExitCritical();
-#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMask()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask(x)
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. These are
-not required for this port but included in case common demo code that uses these
-macros is used. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-/* Prototype of the FreeRTOS tick handler. This must be installed as the
-handler for whichever peripheral is used to generate the RTOS tick. */
-void FreeRTOS_Tick_Handler( void );
-
-/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
-before any floating point instructions are executed. */
-void vPortTaskUsesFPU( void );
-#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
-
-#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
-#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
-
-/* Architecture specific optimisations. */
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-#endif
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
- /* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
- /*-----------------------------------------------------------*/
-
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) )
-
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-#ifdef configASSERT
- void vPortValidateInterruptPriority( void );
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
-#endif /* configASSERT */
-
-#define portNOP() __asm volatile( "NOP" )
-#define portINLINE __inline
-
-#ifdef __cplusplus
- } /* extern C */
-#endif
-
-
-/* The number of bits to shift for an interrupt priority is dependent on the
-number of bits implemented by the interrupt controller. */
-#if configUNIQUE_INTERRUPT_PRIORITIES == 16
- #define portPRIORITY_SHIFT 4
- #define portMAX_BINARY_POINT_VALUE 3
-#elif configUNIQUE_INTERRUPT_PRIORITIES == 32
- #define portPRIORITY_SHIFT 3
- #define portMAX_BINARY_POINT_VALUE 2
-#elif configUNIQUE_INTERRUPT_PRIORITIES == 64
- #define portPRIORITY_SHIFT 2
- #define portMAX_BINARY_POINT_VALUE 1
-#elif configUNIQUE_INTERRUPT_PRIORITIES == 128
- #define portPRIORITY_SHIFT 1
- #define portMAX_BINARY_POINT_VALUE 0
-#elif configUNIQUE_INTERRUPT_PRIORITIES == 256
- #define portPRIORITY_SHIFT 0
- #define portMAX_BINARY_POINT_VALUE 0
-#else
- #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
-#endif
-
-/* Interrupt controller access addresses. */
-#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 )
-#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C )
-#define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 )
-#define portICCBPR_BINARY_POINT_OFFSET ( 0x08 )
-#define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 )
-
-#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
-#define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
-#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
-#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
-#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
-#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
-#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
-
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
-
-#endif /* PORTMACRO_H */
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE size_t
+#define portBASE_TYPE long
+
+typedef portSTACK_TYPE StackType_t;
+typedef portBASE_TYPE BaseType_t;
+typedef uint64_t UBaseType_t;
+
+typedef uint64_t TickType_t;
+#define portMAX_DELAY ( ( TickType_t ) 0xffffffffffffffff )
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+not need to be guarded with a critical section. */
+#define portTICK_TYPE_IS_ATOMIC 1
+
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 16
+#define portPOINTER_SIZE_TYPE uint64_t
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+/* Called at the end of an ISR that can cause a context switch. */
+#define portEND_SWITCHING_ISR( xSwitchRequired )\
+{ \
+extern uint64_t ullPortYieldRequired; \
+ \
+ if( xSwitchRequired != pdFALSE ) \
+ { \
+ ullPortYieldRequired = pdTRUE; \
+ } \
+}
+
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#if defined( GUEST )
+ #define portYIELD() __asm volatile ( "SVC 0" ::: "memory" )
+#else
+ #define portYIELD() __asm volatile ( "SMC 0" ::: "memory" )
+#endif
+/*-----------------------------------------------------------
+ * Critical section control
+ *----------------------------------------------------------*/
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+extern UBaseType_t uxPortSetInterruptMask( void );
+extern void vPortClearInterruptMask( UBaseType_t uxNewMaskValue );
+extern void vPortInstallFreeRTOSVectorTable( void );
+
+#define portDISABLE_INTERRUPTS() \
+ __asm volatile ( "MSR DAIFSET, #2" ::: "memory" ); \
+ __asm volatile ( "DSB SY" ); \
+ __asm volatile ( "ISB SY" );
+
+#define portENABLE_INTERRUPTS() \
+ __asm volatile ( "MSR DAIFCLR, #2" ::: "memory" ); \
+ __asm volatile ( "DSB SY" ); \
+ __asm volatile ( "ISB SY" );
+
+
+/* These macros do not globally disable/enable interrupts. They do mask off
+interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
+#define portENTER_CRITICAL() vPortEnterCritical();
+#define portEXIT_CRITICAL() vPortExitCritical();
+#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask(x)
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. These are
+not required for this port but included in case common demo code that uses these
+macros is used. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+/* Prototype of the FreeRTOS tick handler. This must be installed as the
+handler for whichever peripheral is used to generate the RTOS tick. */
+void FreeRTOS_Tick_Handler( void );
+
+/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
+before any floating point instructions are executed. */
+void vPortTaskUsesFPU( void );
+#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+
+#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
+#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+ /* Store/clear the ready priorities in a bit map. */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+ /*-----------------------------------------------------------*/
+
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+#ifdef configASSERT
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+#endif /* configASSERT */
+
+#define portNOP() __asm volatile( "NOP" )
+#define portINLINE __inline
+
+#ifdef __cplusplus
+ } /* extern C */
+#endif
+
+
+/* The number of bits to shift for an interrupt priority is dependent on the
+number of bits implemented by the interrupt controller. */
+#if configUNIQUE_INTERRUPT_PRIORITIES == 16
+ #define portPRIORITY_SHIFT 4
+ #define portMAX_BINARY_POINT_VALUE 3
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 32
+ #define portPRIORITY_SHIFT 3
+ #define portMAX_BINARY_POINT_VALUE 2
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 64
+ #define portPRIORITY_SHIFT 2
+ #define portMAX_BINARY_POINT_VALUE 1
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 128
+ #define portPRIORITY_SHIFT 1
+ #define portMAX_BINARY_POINT_VALUE 0
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 256
+ #define portPRIORITY_SHIFT 0
+ #define portMAX_BINARY_POINT_VALUE 0
+#else
+ #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
+#endif
+
+/* Interrupt controller access addresses. */
+#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C )
+#define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 )
+#define portICCBPR_BINARY_POINT_OFFSET ( 0x08 )
+#define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 )
+
+#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
+#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
+#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
+#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
+
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+
+#endif /* PORTMACRO_H */
diff --git a/portable/GCC/ARM_CA53_64_BIT_SRE/port.c b/portable/GCC/ARM_CA53_64_BIT_SRE/port.c
index 475916f..b1f7789 100644
--- a/portable/GCC/ARM_CA53_64_BIT_SRE/port.c
+++ b/portable/GCC/ARM_CA53_64_BIT_SRE/port.c
@@ -34,91 +34,91 @@
#include "task.h"
#ifndef configUNIQUE_INTERRUPT_PRIORITIES
- #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+ #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#endif
#ifndef configSETUP_TICK_INTERRUPT
- #error configSETUP_TICK_INTERRUPT() must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+ #error configSETUP_TICK_INTERRUPT() must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#endif /* configSETUP_TICK_INTERRUPT */
#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
#endif
#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
#endif
#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
#endif
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
- /* Check the configuration. */
- #if( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
+ /* Check the configuration. */
+ #if( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
/* In case security extensions are implemented. */
#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
#endif
/* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in
portmacro.h. */
#ifndef configCLEAR_TICK_INTERRUPT
- #define configCLEAR_TICK_INTERRUPT()
+ #define configCLEAR_TICK_INTERRUPT()
#endif
/* A critical section is exited when the critical section nesting count reaches
this value. */
-#define portNO_CRITICAL_NESTING ( ( size_t ) 0 )
+#define portNO_CRITICAL_NESTING ( ( size_t ) 0 )
/* In all GICs 255 can be written to the priority mask register to unmask all
(but the lowest) interrupt priority. */
-#define portUNMASK_VALUE ( 0xFFUL )
+#define portUNMASK_VALUE ( 0xFFUL )
/* Tasks are not created with a floating point context, but can be given a
floating point context after they have been created. A variable is stored as
part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
does not have an FPU context, or any other value if the task does have an FPU
context. */
-#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
+#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
/* Constants required to setup the initial task context. */
-#define portSP_ELx ( ( StackType_t ) 0x01 )
-#define portSP_EL0 ( ( StackType_t ) 0x00 )
+#define portSP_ELx ( ( StackType_t ) 0x01 )
+#define portSP_EL0 ( ( StackType_t ) 0x00 )
#if defined( GUEST )
- #define portEL1 ( ( StackType_t ) 0x04 )
- #define portINITIAL_PSTATE ( portEL1 | portSP_EL0 )
+ #define portEL1 ( ( StackType_t ) 0x04 )
+ #define portINITIAL_PSTATE ( portEL1 | portSP_EL0 )
#else
- #define portEL3 ( ( StackType_t ) 0x0c )
- /* At the time of writing, the BSP only supports EL3. */
- #define portINITIAL_PSTATE ( portEL3 | portSP_EL0 )
+ #define portEL3 ( ( StackType_t ) 0x0c )
+ /* At the time of writing, the BSP only supports EL3. */
+ #define portINITIAL_PSTATE ( portEL3 | portSP_EL0 )
#endif
/* Masks all bits in the APSR other than the mode bits. */
-#define portAPSR_MODE_BITS_MASK ( 0x0C )
+#define portAPSR_MODE_BITS_MASK ( 0x0C )
/* The I bit in the DAIF bits. */
-#define portDAIF_I ( 0x80 )
+#define portDAIF_I ( 0x80 )
/* Macro to unmask all interrupt priorities. */
/* s3_0_c4_c6_0 is ICC_PMR_EL1. */
-#define portCLEAR_INTERRUPT_MASK() \
-{ \
- __asm volatile ( "MSR DAIFSET, #2 \n" \
- "DSB SY \n" \
- "ISB SY \n" \
- "MSR s3_0_c4_c6_0, %0 \n" \
- "DSB SY \n" \
- "ISB SY \n" \
- "MSR DAIFCLR, #2 \n" \
- "DSB SY \n" \
- "ISB SY \n" \
- ::"r"( portUNMASK_VALUE ) ); \
+#define portCLEAR_INTERRUPT_MASK() \
+{ \
+ __asm volatile ( "MSR DAIFSET, #2 \n" \
+ "DSB SY \n" \
+ "ISB SY \n" \
+ "MSR s3_0_c4_c6_0, %0 \n" \
+ "DSB SY \n" \
+ "ISB SY \n" \
+ "MSR DAIFCLR, #2 \n" \
+ "DSB SY \n" \
+ "ISB SY \n" \
+ ::"r"( portUNMASK_VALUE ) ); \
}
/*-----------------------------------------------------------*/
@@ -159,93 +159,93 @@
*/
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- /* Setup the initial stack of the task. The stack is set exactly as
- expected by the portRESTORE_CONTEXT() macro. */
+ /* Setup the initial stack of the task. The stack is set exactly as
+ expected by the portRESTORE_CONTEXT() macro. */
- /* First all the general purpose registers. */
- pxTopOfStack--;
- *pxTopOfStack = 0x0101010101010101ULL; /* R1 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack--;
- *pxTopOfStack = 0x0303030303030303ULL; /* R3 */
- pxTopOfStack--;
- *pxTopOfStack = 0x0202020202020202ULL; /* R2 */
- pxTopOfStack--;
- *pxTopOfStack = 0x0505050505050505ULL; /* R5 */
- pxTopOfStack--;
- *pxTopOfStack = 0x0404040404040404ULL; /* R4 */
- pxTopOfStack--;
- *pxTopOfStack = 0x0707070707070707ULL; /* R7 */
- pxTopOfStack--;
- *pxTopOfStack = 0x0606060606060606ULL; /* R6 */
- pxTopOfStack--;
- *pxTopOfStack = 0x0909090909090909ULL; /* R9 */
- pxTopOfStack--;
- *pxTopOfStack = 0x0808080808080808ULL; /* R8 */
- pxTopOfStack--;
- *pxTopOfStack = 0x1111111111111111ULL; /* R11 */
- pxTopOfStack--;
- *pxTopOfStack = 0x1010101010101010ULL; /* R10 */
- pxTopOfStack--;
- *pxTopOfStack = 0x1313131313131313ULL; /* R13 */
- pxTopOfStack--;
- *pxTopOfStack = 0x1212121212121212ULL; /* R12 */
- pxTopOfStack--;
- *pxTopOfStack = 0x1515151515151515ULL; /* R15 */
- pxTopOfStack--;
- *pxTopOfStack = 0x1414141414141414ULL; /* R14 */
- pxTopOfStack--;
- *pxTopOfStack = 0x1717171717171717ULL; /* R17 */
- pxTopOfStack--;
- *pxTopOfStack = 0x1616161616161616ULL; /* R16 */
- pxTopOfStack--;
- *pxTopOfStack = 0x1919191919191919ULL; /* R19 */
- pxTopOfStack--;
- *pxTopOfStack = 0x1818181818181818ULL; /* R18 */
- pxTopOfStack--;
- *pxTopOfStack = 0x2121212121212121ULL; /* R21 */
- pxTopOfStack--;
- *pxTopOfStack = 0x2020202020202020ULL; /* R20 */
- pxTopOfStack--;
- *pxTopOfStack = 0x2323232323232323ULL; /* R23 */
- pxTopOfStack--;
- *pxTopOfStack = 0x2222222222222222ULL; /* R22 */
- pxTopOfStack--;
- *pxTopOfStack = 0x2525252525252525ULL; /* R25 */
- pxTopOfStack--;
- *pxTopOfStack = 0x2424242424242424ULL; /* R24 */
- pxTopOfStack--;
- *pxTopOfStack = 0x2727272727272727ULL; /* R27 */
- pxTopOfStack--;
- *pxTopOfStack = 0x2626262626262626ULL; /* R26 */
- pxTopOfStack--;
- *pxTopOfStack = 0x2929292929292929ULL; /* R29 */
- pxTopOfStack--;
- *pxTopOfStack = 0x2828282828282828ULL; /* R28 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x00; /* XZR - has no effect, used so there are an even number of registers. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x00; /* R30 - procedure call link register. */
- pxTopOfStack--;
+ /* First all the general purpose registers. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x0101010101010101ULL; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x0303030303030303ULL; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x0202020202020202ULL; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x0505050505050505ULL; /* R5 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x0404040404040404ULL; /* R4 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x0707070707070707ULL; /* R7 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x0606060606060606ULL; /* R6 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x0909090909090909ULL; /* R9 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x0808080808080808ULL; /* R8 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x1111111111111111ULL; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x1010101010101010ULL; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x1313131313131313ULL; /* R13 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x1212121212121212ULL; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x1515151515151515ULL; /* R15 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x1414141414141414ULL; /* R14 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x1717171717171717ULL; /* R17 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x1616161616161616ULL; /* R16 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x1919191919191919ULL; /* R19 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x1818181818181818ULL; /* R18 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2121212121212121ULL; /* R21 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2020202020202020ULL; /* R20 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2323232323232323ULL; /* R23 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2222222222222222ULL; /* R22 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2525252525252525ULL; /* R25 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2424242424242424ULL; /* R24 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2727272727272727ULL; /* R27 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2626262626262626ULL; /* R26 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2929292929292929ULL; /* R29 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x2828282828282828ULL; /* R28 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x00; /* XZR - has no effect, used so there are an even number of registers. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x00; /* R30 - procedure call link register. */
+ pxTopOfStack--;
- *pxTopOfStack = portINITIAL_PSTATE;
- pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_PSTATE;
+ pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode; /* Exception return address. */
- pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* Exception return address. */
+ pxTopOfStack--;
- /* The task will start with a critical nesting count of 0 as interrupts are
- enabled. */
- *pxTopOfStack = portNO_CRITICAL_NESTING;
- pxTopOfStack--;
+ /* The task will start with a critical nesting count of 0 as interrupts are
+ enabled. */
+ *pxTopOfStack = portNO_CRITICAL_NESTING;
+ pxTopOfStack--;
- /* The task will start without a floating point context. A task that uses
- the floating point hardware must call vPortTaskUsesFPU() before executing
- any floating point instructions. */
- *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+ /* The task will start without a floating point context. A task that uses
+ the floating point hardware must call vPortTaskUsesFPU() before executing
+ any floating point instructions. */
+ *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
- return pxTopOfStack;
+ return pxTopOfStack;
}
/*-----------------------------------------------------------*/
@@ -253,149 +253,149 @@
{
uint32_t ulAPSR;
- __asm volatile ( "MRS %0, CurrentEL" : "=r" ( ulAPSR ) );
- ulAPSR &= portAPSR_MODE_BITS_MASK;
+ __asm volatile ( "MRS %0, CurrentEL" : "=r" ( ulAPSR ) );
+ ulAPSR &= portAPSR_MODE_BITS_MASK;
#if defined( GUEST )
- configASSERT( ulAPSR == portEL1 );
- if( ulAPSR == portEL1 )
+ configASSERT( ulAPSR == portEL1 );
+ if( ulAPSR == portEL1 )
#else
- configASSERT( ulAPSR == portEL3 );
- if( ulAPSR == portEL3 )
+ configASSERT( ulAPSR == portEL3 );
+ if( ulAPSR == portEL3 )
#endif
- {
- /* Interrupts are turned off in the CPU itself to ensure a tick does
- not execute while the scheduler is being started. Interrupts are
- automatically turned back on in the CPU when the first task starts
- executing. */
- portDISABLE_INTERRUPTS();
+ {
+ /* Interrupts are turned off in the CPU itself to ensure a tick does
+ not execute while the scheduler is being started. Interrupts are
+ automatically turned back on in the CPU when the first task starts
+ executing. */
+ portDISABLE_INTERRUPTS();
- /* Start the timer that generates the tick ISR. */
- configSETUP_TICK_INTERRUPT();
+ /* Start the timer that generates the tick ISR. */
+ configSETUP_TICK_INTERRUPT();
- /* Start the first task executing. */
- vPortRestoreTaskContext();
- }
+ /* Start the first task executing. */
+ vPortRestoreTaskContext();
+ }
- return 0;
+ return 0;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* Not implemented in ports where there is nothing to return to.
- Artificially force an assert. */
- configASSERT( ullCriticalNesting == 1000ULL );
+ /* Not implemented in ports where there is nothing to return to.
+ Artificially force an assert. */
+ configASSERT( ullCriticalNesting == 1000ULL );
}
/*-----------------------------------------------------------*/
void vPortEnterCritical( void )
{
- /* Mask interrupts up to the max syscall interrupt priority. */
- uxPortSetInterruptMask();
+ /* Mask interrupts up to the max syscall interrupt priority. */
+ uxPortSetInterruptMask();
- /* Now interrupts are disabled ullCriticalNesting can be accessed
- directly. Increment ullCriticalNesting to keep a count of how many times
- portENTER_CRITICAL() has been called. */
- ullCriticalNesting++;
+ /* Now interrupts are disabled ullCriticalNesting can be accessed
+ directly. Increment ullCriticalNesting to keep a count of how many times
+ portENTER_CRITICAL() has been called. */
+ ullCriticalNesting++;
- /* This is not the interrupt safe version of the enter critical function so
- assert() if it is being called from an interrupt context. Only API
- functions that end in "FromISR" can be used in an interrupt. Only assert if
- the critical nesting count is 1 to protect against recursive calls if the
- assert function also uses a critical section. */
- if( ullCriticalNesting == 1ULL )
- {
- configASSERT( ullPortInterruptNesting == 0 );
- }
+ /* This is not the interrupt safe version of the enter critical function so
+ assert() if it is being called from an interrupt context. Only API
+ functions that end in "FromISR" can be used in an interrupt. Only assert if
+ the critical nesting count is 1 to protect against recursive calls if the
+ assert function also uses a critical section. */
+ if( ullCriticalNesting == 1ULL )
+ {
+ configASSERT( ullPortInterruptNesting == 0 );
+ }
}
/*-----------------------------------------------------------*/
void vPortExitCritical( void )
{
- if( ullCriticalNesting > portNO_CRITICAL_NESTING )
- {
- /* Decrement the nesting count as the critical section is being
- exited. */
- ullCriticalNesting--;
+ if( ullCriticalNesting > portNO_CRITICAL_NESTING )
+ {
+ /* Decrement the nesting count as the critical section is being
+ exited. */
+ ullCriticalNesting--;
- /* If the nesting level has reached zero then all interrupt
- priorities must be re-enabled. */
- if( ullCriticalNesting == portNO_CRITICAL_NESTING )
- {
- /* Critical nesting has reached zero so all interrupt priorities
- should be unmasked. */
- portCLEAR_INTERRUPT_MASK();
- }
- }
+ /* If the nesting level has reached zero then all interrupt
+ priorities must be re-enabled. */
+ if( ullCriticalNesting == portNO_CRITICAL_NESTING )
+ {
+ /* Critical nesting has reached zero so all interrupt priorities
+ should be unmasked. */
+ portCLEAR_INTERRUPT_MASK();
+ }
+ }
}
/*-----------------------------------------------------------*/
void FreeRTOS_Tick_Handler( void )
{
- /* Must be the lowest possible priority. */
- #if !defined( QEMU )
- {
- uint64_t ullRunningInterruptPriority;
- /* s3_0_c12_c11_3 is ICC_RPR_EL1. */
- __asm volatile ( "MRS %0, s3_0_c12_c11_3" : "=r" ( ullRunningInterruptPriority ) );
- configASSERT( ullRunningInterruptPriority == ( portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
- }
- #endif
+ /* Must be the lowest possible priority. */
+ #if !defined( QEMU )
+ {
+ uint64_t ullRunningInterruptPriority;
+ /* s3_0_c12_c11_3 is ICC_RPR_EL1. */
+ __asm volatile ( "MRS %0, s3_0_c12_c11_3" : "=r" ( ullRunningInterruptPriority ) );
+ configASSERT( ullRunningInterruptPriority == ( portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
+ }
+ #endif
- /* Interrupts should not be enabled before this point. */
- #if( configASSERT_DEFINED == 1 )
- {
- uint32_t ulMaskBits;
+ /* Interrupts should not be enabled before this point. */
+ #if( configASSERT_DEFINED == 1 )
+ {
+ uint32_t ulMaskBits;
- __asm volatile( "MRS %0, DAIF" : "=r"( ulMaskBits ) :: "memory" );
- configASSERT( ( ulMaskBits & portDAIF_I ) != 0 );
- }
- #endif /* configASSERT_DEFINED */
+ __asm volatile( "MRS %0, DAIF" : "=r"( ulMaskBits ) :: "memory" );
+ configASSERT( ( ulMaskBits & portDAIF_I ) != 0 );
+ }
+ #endif /* configASSERT_DEFINED */
- /* Set interrupt mask before altering scheduler structures. The tick
- handler runs at the lowest priority, so interrupts cannot already be masked,
- so there is no need to save and restore the current mask value. It is
- necessary to turn off interrupts in the CPU itself while the ICCPMR is being
- updated. */
- /* s3_0_c4_c6_0 is ICC_PMR_EL1. */
- __asm volatile ( "MSR s3_0_c4_c6_0, %0 \n"
- "DSB SY \n"
- "ISB SY \n"
- :: "r" ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) : "memory" );
+ /* Set interrupt mask before altering scheduler structures. The tick
+ handler runs at the lowest priority, so interrupts cannot already be masked,
+ so there is no need to save and restore the current mask value. It is
+ necessary to turn off interrupts in the CPU itself while the ICCPMR is being
+ updated. */
+ /* s3_0_c4_c6_0 is ICC_PMR_EL1. */
+ __asm volatile ( "MSR s3_0_c4_c6_0, %0 \n"
+ "DSB SY \n"
+ "ISB SY \n"
+ :: "r" ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) : "memory" );
- /* Ok to enable interrupts after the interrupt source has been cleared. */
- configCLEAR_TICK_INTERRUPT();
- portENABLE_INTERRUPTS();
+ /* Ok to enable interrupts after the interrupt source has been cleared. */
+ configCLEAR_TICK_INTERRUPT();
+ portENABLE_INTERRUPTS();
- /* Increment the RTOS tick. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- ullPortYieldRequired = pdTRUE;
- }
+ /* Increment the RTOS tick. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ ullPortYieldRequired = pdTRUE;
+ }
- /* Ensure all interrupt priorities are active again. */
- portCLEAR_INTERRUPT_MASK();
+ /* Ensure all interrupt priorities are active again. */
+ portCLEAR_INTERRUPT_MASK();
}
/*-----------------------------------------------------------*/
void vPortTaskUsesFPU( void )
{
- /* A task is registering the fact that it needs an FPU context. Set the
- FPU flag (which is saved as part of the task context). */
- ullPortTaskHasFPUContext = pdTRUE;
+ /* A task is registering the fact that it needs an FPU context. Set the
+ FPU flag (which is saved as part of the task context). */
+ ullPortTaskHasFPUContext = pdTRUE;
- /* Consider initialising the FPSR here - but probably not necessary in
- AArch64. */
+ /* Consider initialising the FPSR here - but probably not necessary in
+ AArch64. */
}
/*-----------------------------------------------------------*/
void vPortClearInterruptMask( UBaseType_t uxNewMaskValue )
{
- if( uxNewMaskValue == pdFALSE )
- {
- portCLEAR_INTERRUPT_MASK();
- }
+ if( uxNewMaskValue == pdFALSE )
+ {
+ portCLEAR_INTERRUPT_MASK();
+ }
}
/*-----------------------------------------------------------*/
@@ -404,56 +404,55 @@
uint32_t ulReturn;
uint64_t ullPMRValue;
- /* Interrupt in the CPU must be turned off while the ICCPMR is being
- updated. */
- portDISABLE_INTERRUPTS();
- /* s3_0_c4_c6_0 is ICC_PMR_EL1. */
- __asm volatile ( "MRS %0, s3_0_c4_c6_0" : "=r" ( ullPMRValue ) );
- if( ullPMRValue == ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
- {
- /* Interrupts were already masked. */
- ulReturn = pdTRUE;
- }
- else
- {
- ulReturn = pdFALSE;
- /* s3_0_c4_c6_0 is ICC_PMR_EL1. */
- __asm volatile ( "MSR s3_0_c4_c6_0, %0 \n"
- "DSB SY \n"
- "ISB SY \n"
- :: "r" ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) : "memory" );
- }
+ /* Interrupt in the CPU must be turned off while the ICCPMR is being
+ updated. */
+ portDISABLE_INTERRUPTS();
+ /* s3_0_c4_c6_0 is ICC_PMR_EL1. */
+ __asm volatile ( "MRS %0, s3_0_c4_c6_0" : "=r" ( ullPMRValue ) );
+ if( ullPMRValue == ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
+ {
+ /* Interrupts were already masked. */
+ ulReturn = pdTRUE;
+ }
+ else
+ {
+ ulReturn = pdFALSE;
+ /* s3_0_c4_c6_0 is ICC_PMR_EL1. */
+ __asm volatile ( "MSR s3_0_c4_c6_0, %0 \n"
+ "DSB SY \n"
+ "ISB SY \n"
+ :: "r" ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) : "memory" );
+ }
- portENABLE_INTERRUPTS();
+ portENABLE_INTERRUPTS();
- return ulReturn;
+ return ulReturn;
}
/*-----------------------------------------------------------*/
#if( configASSERT_DEFINED == 1 )
- void vPortValidateInterruptPriority( void )
- {
- /* The following assertion will fail if a service routine (ISR) for
- an interrupt that has been assigned a priority above
- configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
- function. ISR safe FreeRTOS API functions must *only* be called
- from interrupts that have been assigned a priority at or below
- configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ void vPortValidateInterruptPriority( void )
+ {
+ /* The following assertion will fail if a service routine (ISR) for
+ an interrupt that has been assigned a priority above
+ configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+ function. ISR safe FreeRTOS API functions must *only* be called
+ from interrupts that have been assigned a priority at or below
+ configMAX_SYSCALL_INTERRUPT_PRIORITY.
- Numerically low interrupt priority numbers represent logically high
- interrupt priorities, therefore the priority of the interrupt must
- be set to a value equal to or numerically *higher* than
- configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ Numerically low interrupt priority numbers represent logically high
+ interrupt priorities, therefore the priority of the interrupt must
+ be set to a value equal to or numerically *higher* than
+ configMAX_SYSCALL_INTERRUPT_PRIORITY.
- FreeRTOS maintains separate thread and ISR API functions to ensure
- interrupt entry is as fast and simple as possible. */
- uint64_t ullRunningInterruptPriority;
- /* s3_0_c12_c11_3 is ICC_RPR_EL1. */
- __asm volatile ( "MRS %0, s3_0_c12_c11_3" : "=r" ( ullRunningInterruptPriority ) );
- configASSERT( ullRunningInterruptPriority >= ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
- }
+ FreeRTOS maintains separate thread and ISR API functions to ensure
+ interrupt entry is as fast and simple as possible. */
+ uint64_t ullRunningInterruptPriority;
+ /* s3_0_c12_c11_3 is ICC_RPR_EL1. */
+ __asm volatile ( "MRS %0, s3_0_c12_c11_3" : "=r" ( ullRunningInterruptPriority ) );
+ configASSERT( ullRunningInterruptPriority >= ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
+ }
#endif /* configASSERT_DEFINED */
/*-----------------------------------------------------------*/
-
diff --git a/portable/GCC/ARM_CA53_64_BIT_SRE/portASM.S b/portable/GCC/ARM_CA53_64_BIT_SRE/portASM.S
index 7c8bc92..d779890 100644
--- a/portable/GCC/ARM_CA53_64_BIT_SRE/portASM.S
+++ b/portable/GCC/ARM_CA53_64_BIT_SRE/portASM.S
@@ -26,191 +26,191 @@
*
*/
- .text
+ .text
- /* Variables and functions. */
- .extern ullMaxAPIPriorityMask
- .extern pxCurrentTCB
- .extern vTaskSwitchContext
- .extern vApplicationIRQHandler
- .extern ullPortInterruptNesting
- .extern ullPortTaskHasFPUContext
- .extern ullCriticalNesting
- .extern ullPortYieldRequired
- .extern _freertos_vector_table
+ /* Variables and functions. */
+ .extern ullMaxAPIPriorityMask
+ .extern pxCurrentTCB
+ .extern vTaskSwitchContext
+ .extern vApplicationIRQHandler
+ .extern ullPortInterruptNesting
+ .extern ullPortTaskHasFPUContext
+ .extern ullCriticalNesting
+ .extern ullPortYieldRequired
+ .extern _freertos_vector_table
- .global FreeRTOS_IRQ_Handler
- .global FreeRTOS_SWI_Handler
- .global vPortRestoreTaskContext
+ .global FreeRTOS_IRQ_Handler
+ .global FreeRTOS_SWI_Handler
+ .global vPortRestoreTaskContext
.macro portSAVE_CONTEXT
- /* Switch to use the EL0 stack pointer. */
- MSR SPSEL, #0
+ /* Switch to use the EL0 stack pointer. */
+ MSR SPSEL, #0
- /* Save the entire context. */
- STP X0, X1, [SP, #-0x10]!
- STP X2, X3, [SP, #-0x10]!
- STP X4, X5, [SP, #-0x10]!
- STP X6, X7, [SP, #-0x10]!
- STP X8, X9, [SP, #-0x10]!
- STP X10, X11, [SP, #-0x10]!
- STP X12, X13, [SP, #-0x10]!
- STP X14, X15, [SP, #-0x10]!
- STP X16, X17, [SP, #-0x10]!
- STP X18, X19, [SP, #-0x10]!
- STP X20, X21, [SP, #-0x10]!
- STP X22, X23, [SP, #-0x10]!
- STP X24, X25, [SP, #-0x10]!
- STP X26, X27, [SP, #-0x10]!
- STP X28, X29, [SP, #-0x10]!
- STP X30, XZR, [SP, #-0x10]!
+ /* Save the entire context. */
+ STP X0, X1, [SP, #-0x10]!
+ STP X2, X3, [SP, #-0x10]!
+ STP X4, X5, [SP, #-0x10]!
+ STP X6, X7, [SP, #-0x10]!
+ STP X8, X9, [SP, #-0x10]!
+ STP X10, X11, [SP, #-0x10]!
+ STP X12, X13, [SP, #-0x10]!
+ STP X14, X15, [SP, #-0x10]!
+ STP X16, X17, [SP, #-0x10]!
+ STP X18, X19, [SP, #-0x10]!
+ STP X20, X21, [SP, #-0x10]!
+ STP X22, X23, [SP, #-0x10]!
+ STP X24, X25, [SP, #-0x10]!
+ STP X26, X27, [SP, #-0x10]!
+ STP X28, X29, [SP, #-0x10]!
+ STP X30, XZR, [SP, #-0x10]!
- /* Save the SPSR. */
+ /* Save the SPSR. */
#if defined( GUEST )
- MRS X3, SPSR_EL1
- MRS X2, ELR_EL1
+ MRS X3, SPSR_EL1
+ MRS X2, ELR_EL1
#else
- MRS X3, SPSR_EL3
- /* Save the ELR. */
- MRS X2, ELR_EL3
+ MRS X3, SPSR_EL3
+ /* Save the ELR. */
+ MRS X2, ELR_EL3
#endif
- STP X2, X3, [SP, #-0x10]!
+ STP X2, X3, [SP, #-0x10]!
- /* Save the critical section nesting depth. */
- LDR X0, ullCriticalNestingConst
- LDR X3, [X0]
+ /* Save the critical section nesting depth. */
+ LDR X0, ullCriticalNestingConst
+ LDR X3, [X0]
- /* Save the FPU context indicator. */
- LDR X0, ullPortTaskHasFPUContextConst
- LDR X2, [X0]
+ /* Save the FPU context indicator. */
+ LDR X0, ullPortTaskHasFPUContextConst
+ LDR X2, [X0]
- /* Save the FPU context, if any (32 128-bit registers). */
- CMP X2, #0
- B.EQ 1f
- STP Q0, Q1, [SP,#-0x20]!
- STP Q2, Q3, [SP,#-0x20]!
- STP Q4, Q5, [SP,#-0x20]!
- STP Q6, Q7, [SP,#-0x20]!
- STP Q8, Q9, [SP,#-0x20]!
- STP Q10, Q11, [SP,#-0x20]!
- STP Q12, Q13, [SP,#-0x20]!
- STP Q14, Q15, [SP,#-0x20]!
- STP Q16, Q17, [SP,#-0x20]!
- STP Q18, Q19, [SP,#-0x20]!
- STP Q20, Q21, [SP,#-0x20]!
- STP Q22, Q23, [SP,#-0x20]!
- STP Q24, Q25, [SP,#-0x20]!
- STP Q26, Q27, [SP,#-0x20]!
- STP Q28, Q29, [SP,#-0x20]!
- STP Q30, Q31, [SP,#-0x20]!
+ /* Save the FPU context, if any (32 128-bit registers). */
+ CMP X2, #0
+ B.EQ 1f
+ STP Q0, Q1, [SP,#-0x20]!
+ STP Q2, Q3, [SP,#-0x20]!
+ STP Q4, Q5, [SP,#-0x20]!
+ STP Q6, Q7, [SP,#-0x20]!
+ STP Q8, Q9, [SP,#-0x20]!
+ STP Q10, Q11, [SP,#-0x20]!
+ STP Q12, Q13, [SP,#-0x20]!
+ STP Q14, Q15, [SP,#-0x20]!
+ STP Q16, Q17, [SP,#-0x20]!
+ STP Q18, Q19, [SP,#-0x20]!
+ STP Q20, Q21, [SP,#-0x20]!
+ STP Q22, Q23, [SP,#-0x20]!
+ STP Q24, Q25, [SP,#-0x20]!
+ STP Q26, Q27, [SP,#-0x20]!
+ STP Q28, Q29, [SP,#-0x20]!
+ STP Q30, Q31, [SP,#-0x20]!
1:
- /* Store the critical nesting count and FPU context indicator. */
- STP X2, X3, [SP, #-0x10]!
+ /* Store the critical nesting count and FPU context indicator. */
+ STP X2, X3, [SP, #-0x10]!
- LDR X0, pxCurrentTCBConst
- LDR X1, [X0]
- MOV X0, SP /* Move SP into X0 for saving. */
- STR X0, [X1]
+ LDR X0, pxCurrentTCBConst
+ LDR X1, [X0]
+ MOV X0, SP /* Move SP into X0 for saving. */
+ STR X0, [X1]
- /* Switch to use the ELx stack pointer. */
- MSR SPSEL, #1
+ /* Switch to use the ELx stack pointer. */
+ MSR SPSEL, #1
- .endm
+ .endm
; /**********************************************************************/
.macro portRESTORE_CONTEXT
- /* Switch to use the EL0 stack pointer. */
- MSR SPSEL, #0
+ /* Switch to use the EL0 stack pointer. */
+ MSR SPSEL, #0
- /* Set the SP to point to the stack of the task being restored. */
- LDR X0, pxCurrentTCBConst
- LDR X1, [X0]
- LDR X0, [X1]
- MOV SP, X0
+ /* Set the SP to point to the stack of the task being restored. */
+ LDR X0, pxCurrentTCBConst
+ LDR X1, [X0]
+ LDR X0, [X1]
+ MOV SP, X0
- LDP X2, X3, [SP], #0x10 /* Critical nesting and FPU context. */
+ LDP X2, X3, [SP], #0x10 /* Critical nesting and FPU context. */
- /* Set the PMR register to be correct for the current critical nesting
- depth. */
- LDR X0, ullCriticalNestingConst /* X0 holds the address of ullCriticalNesting. */
- MOV X1, #255 /* X1 holds the unmask value. */
- CMP X3, #0
- B.EQ 1f
- LDR X6, ullMaxAPIPriorityMaskConst
- LDR X1, [X6] /* X1 holds the mask value. */
+ /* Set the PMR register to be correct for the current critical nesting
+ depth. */
+ LDR X0, ullCriticalNestingConst /* X0 holds the address of ullCriticalNesting. */
+ MOV X1, #255 /* X1 holds the unmask value. */
+ CMP X3, #0
+ B.EQ 1f
+ LDR X6, ullMaxAPIPriorityMaskConst
+ LDR X1, [X6] /* X1 holds the mask value. */
1:
- MSR s3_0_c4_c6_0, X1 /* Write the mask value to ICCPMR. s3_0_c4_c6_0 is ICC_PMR_EL1. */
- DSB SY /* _RB_Barriers probably not required here. */
- ISB SY
- STR X3, [X0] /* Restore the task's critical nesting count. */
+ MSR s3_0_c4_c6_0, X1 /* Write the mask value to ICCPMR. s3_0_c4_c6_0 is ICC_PMR_EL1. */
+ DSB SY /* _RB_Barriers probably not required here. */
+ ISB SY
+ STR X3, [X0] /* Restore the task's critical nesting count. */
- /* Restore the FPU context indicator. */
- LDR X0, ullPortTaskHasFPUContextConst
- STR X2, [X0]
+ /* Restore the FPU context indicator. */
+ LDR X0, ullPortTaskHasFPUContextConst
+ STR X2, [X0]
- /* Restore the FPU context, if any. */
- CMP X2, #0
- B.EQ 1f
- LDP Q30, Q31, [SP], #0x20
- LDP Q28, Q29, [SP], #0x20
- LDP Q26, Q27, [SP], #0x20
- LDP Q24, Q25, [SP], #0x20
- LDP Q22, Q23, [SP], #0x20
- LDP Q20, Q21, [SP], #0x20
- LDP Q18, Q19, [SP], #0x20
- LDP Q16, Q17, [SP], #0x20
- LDP Q14, Q15, [SP], #0x20
- LDP Q12, Q13, [SP], #0x20
- LDP Q10, Q11, [SP], #0x20
- LDP Q8, Q9, [SP], #0x20
- LDP Q6, Q7, [SP], #0x20
- LDP Q4, Q5, [SP], #0x20
- LDP Q2, Q3, [SP], #0x20
- LDP Q0, Q1, [SP], #0x20
+ /* Restore the FPU context, if any. */
+ CMP X2, #0
+ B.EQ 1f
+ LDP Q30, Q31, [SP], #0x20
+ LDP Q28, Q29, [SP], #0x20
+ LDP Q26, Q27, [SP], #0x20
+ LDP Q24, Q25, [SP], #0x20
+ LDP Q22, Q23, [SP], #0x20
+ LDP Q20, Q21, [SP], #0x20
+ LDP Q18, Q19, [SP], #0x20
+ LDP Q16, Q17, [SP], #0x20
+ LDP Q14, Q15, [SP], #0x20
+ LDP Q12, Q13, [SP], #0x20
+ LDP Q10, Q11, [SP], #0x20
+ LDP Q8, Q9, [SP], #0x20
+ LDP Q6, Q7, [SP], #0x20
+ LDP Q4, Q5, [SP], #0x20
+ LDP Q2, Q3, [SP], #0x20
+ LDP Q0, Q1, [SP], #0x20
1:
- LDP X2, X3, [SP], #0x10 /* SPSR and ELR. */
+ LDP X2, X3, [SP], #0x10 /* SPSR and ELR. */
#if defined( GUEST )
- /* Restore the SPSR. */
- MSR SPSR_EL1, X3
- /* Restore the ELR. */
- MSR ELR_EL1, X2
+ /* Restore the SPSR. */
+ MSR SPSR_EL1, X3
+ /* Restore the ELR. */
+ MSR ELR_EL1, X2
#else
- /* Restore the SPSR. */
- MSR SPSR_EL3, X3 /*_RB_ Assumes started in EL3. */
- /* Restore the ELR. */
- MSR ELR_EL3, X2
+ /* Restore the SPSR. */
+ MSR SPSR_EL3, X3 /*_RB_ Assumes started in EL3. */
+ /* Restore the ELR. */
+ MSR ELR_EL3, X2
#endif
- LDP X30, XZR, [SP], #0x10
- LDP X28, X29, [SP], #0x10
- LDP X26, X27, [SP], #0x10
- LDP X24, X25, [SP], #0x10
- LDP X22, X23, [SP], #0x10
- LDP X20, X21, [SP], #0x10
- LDP X18, X19, [SP], #0x10
- LDP X16, X17, [SP], #0x10
- LDP X14, X15, [SP], #0x10
- LDP X12, X13, [SP], #0x10
- LDP X10, X11, [SP], #0x10
- LDP X8, X9, [SP], #0x10
- LDP X6, X7, [SP], #0x10
- LDP X4, X5, [SP], #0x10
- LDP X2, X3, [SP], #0x10
- LDP X0, X1, [SP], #0x10
+ LDP X30, XZR, [SP], #0x10
+ LDP X28, X29, [SP], #0x10
+ LDP X26, X27, [SP], #0x10
+ LDP X24, X25, [SP], #0x10
+ LDP X22, X23, [SP], #0x10
+ LDP X20, X21, [SP], #0x10
+ LDP X18, X19, [SP], #0x10
+ LDP X16, X17, [SP], #0x10
+ LDP X14, X15, [SP], #0x10
+ LDP X12, X13, [SP], #0x10
+ LDP X10, X11, [SP], #0x10
+ LDP X8, X9, [SP], #0x10
+ LDP X6, X7, [SP], #0x10
+ LDP X4, X5, [SP], #0x10
+ LDP X2, X3, [SP], #0x10
+ LDP X0, X1, [SP], #0x10
- /* Switch to use the ELx stack pointer. _RB_ Might not be required. */
- MSR SPSEL, #1
+ /* Switch to use the ELx stack pointer. _RB_ Might not be required. */
+ MSR SPSEL, #1
- ERET
+ ERET
- .endm
+ .endm
/******************************************************************************
@@ -219,29 +219,29 @@
.align 8
.type FreeRTOS_SWI_Handler, %function
FreeRTOS_SWI_Handler:
- /* Save the context of the current task and select a new task to run. */
- portSAVE_CONTEXT
+ /* Save the context of the current task and select a new task to run. */
+ portSAVE_CONTEXT
#if defined( GUEST )
- MRS X0, ESR_EL1
+ MRS X0, ESR_EL1
#else
- MRS X0, ESR_EL3
+ MRS X0, ESR_EL3
#endif
- LSR X1, X0, #26
+ LSR X1, X0, #26
#if defined( GUEST )
- CMP X1, #0x15 /* 0x15 = SVC instruction. */
+ CMP X1, #0x15 /* 0x15 = SVC instruction. */
#else
- CMP X1, #0x17 /* 0x17 = SMC instruction. */
+ CMP X1, #0x17 /* 0x17 = SMC instruction. */
#endif
- B.NE FreeRTOS_Abort
- BL vTaskSwitchContext
+ B.NE FreeRTOS_Abort
+ BL vTaskSwitchContext
- portRESTORE_CONTEXT
+ portRESTORE_CONTEXT
FreeRTOS_Abort:
- /* Full ESR is in X0, exception class code is in X1. */
- B .
+ /* Full ESR is in X0, exception class code is in X1. */
+ B .
/******************************************************************************
* vPortRestoreTaskContext is used to start the scheduler.
@@ -249,20 +249,20 @@
.align 8
.type vPortRestoreTaskContext, %function
vPortRestoreTaskContext:
-.set freertos_vector_base, _freertos_vector_table
+.set freertos_vector_base, _freertos_vector_table
- /* Install the FreeRTOS interrupt handlers. */
- LDR X1, =freertos_vector_base
+ /* Install the FreeRTOS interrupt handlers. */
+ LDR X1, =freertos_vector_base
#if defined( GUEST )
- MSR VBAR_EL1, X1
+ MSR VBAR_EL1, X1
#else
- MSR VBAR_EL3, X1
+ MSR VBAR_EL3, X1
#endif
- DSB SY
- ISB SY
+ DSB SY
+ ISB SY
- /* Start the first task. */
- portRESTORE_CONTEXT
+ /* Start the first task. */
+ portRESTORE_CONTEXT
/******************************************************************************
@@ -279,132 +279,132 @@
.align 8
.type FreeRTOS_IRQ_Handler, %function
FreeRTOS_IRQ_Handler:
- /* Save volatile registers. */
- STP X0, X1, [SP, #-0x10]!
- STP X2, X3, [SP, #-0x10]!
- STP X4, X5, [SP, #-0x10]!
- STP X6, X7, [SP, #-0x10]!
- STP X8, X9, [SP, #-0x10]!
- STP X10, X11, [SP, #-0x10]!
- STP X12, X13, [SP, #-0x10]!
- STP X14, X15, [SP, #-0x10]!
- STP X16, X17, [SP, #-0x10]!
- STP X18, X19, [SP, #-0x10]!
- STP X29, X30, [SP, #-0x10]!
+ /* Save volatile registers. */
+ STP X0, X1, [SP, #-0x10]!
+ STP X2, X3, [SP, #-0x10]!
+ STP X4, X5, [SP, #-0x10]!
+ STP X6, X7, [SP, #-0x10]!
+ STP X8, X9, [SP, #-0x10]!
+ STP X10, X11, [SP, #-0x10]!
+ STP X12, X13, [SP, #-0x10]!
+ STP X14, X15, [SP, #-0x10]!
+ STP X16, X17, [SP, #-0x10]!
+ STP X18, X19, [SP, #-0x10]!
+ STP X29, X30, [SP, #-0x10]!
- /* Save the SPSR and ELR. */
+ /* Save the SPSR and ELR. */
#if defined( GUEST )
- MRS X3, SPSR_EL1
- MRS X2, ELR_EL1
+ MRS X3, SPSR_EL1
+ MRS X2, ELR_EL1
#else
- MRS X3, SPSR_EL3
- MRS X2, ELR_EL3
+ MRS X3, SPSR_EL3
+ MRS X2, ELR_EL3
#endif
- STP X2, X3, [SP, #-0x10]!
+ STP X2, X3, [SP, #-0x10]!
- /* Increment the interrupt nesting counter. */
- LDR X5, ullPortInterruptNestingConst
- LDR X1, [X5] /* Old nesting count in X1. */
- ADD X6, X1, #1
- STR X6, [X5] /* Address of nesting count variable in X5. */
+ /* Increment the interrupt nesting counter. */
+ LDR X5, ullPortInterruptNestingConst
+ LDR X1, [X5] /* Old nesting count in X1. */
+ ADD X6, X1, #1
+ STR X6, [X5] /* Address of nesting count variable in X5. */
- /* Maintain the interrupt nesting information across the function call. */
- STP X1, X5, [SP, #-0x10]!
+ /* Maintain the interrupt nesting information across the function call. */
+ STP X1, X5, [SP, #-0x10]!
- /* Read interrupt ID from the interrupt acknowledge register and store it
- in X0 for future parameter and interrupt clearing use. */
- MRS X0, S3_0_C12_C12_0 /* S3_0_C12_C12_0 is ICC_IAR1_EL1. */
+ /* Read interrupt ID from the interrupt acknowledge register and store it
+ in X0 for future parameter and interrupt clearing use. */
+ MRS X0, S3_0_C12_C12_0 /* S3_0_C12_C12_0 is ICC_IAR1_EL1. */
- /* Maintain the interrupt ID value across the function call. */
- STP X0, X1, [SP, #-0x10]!
+ /* Maintain the interrupt ID value across the function call. */
+ STP X0, X1, [SP, #-0x10]!
- /* Call the C handler. */
- BL vApplicationIRQHandler
+ /* Call the C handler. */
+ BL vApplicationIRQHandler
- /* Disable interrupts. */
- MSR DAIFSET, #2
- DSB SY
- ISB SY
+ /* Disable interrupts. */
+ MSR DAIFSET, #2
+ DSB SY
+ ISB SY
- /* Restore the interrupt ID value. */
- LDP X0, X1, [SP], #0x10
+ /* Restore the interrupt ID value. */
+ LDP X0, X1, [SP], #0x10
- /* End IRQ processing by writing interrupt ID value to the EOI register. */
- MSR S3_0_C12_C12_1, X0 /* S3_0_C12_C12_1 is ICC_EOIR1_EL1. */
+ /* End IRQ processing by writing interrupt ID value to the EOI register. */
+ MSR S3_0_C12_C12_1, X0 /* S3_0_C12_C12_1 is ICC_EOIR1_EL1. */
- /* Restore the critical nesting count. */
- LDP X1, X5, [SP], #0x10
- STR X1, [X5]
+ /* Restore the critical nesting count. */
+ LDP X1, X5, [SP], #0x10
+ STR X1, [X5]
- /* Has interrupt nesting unwound? */
- CMP X1, #0
- B.NE Exit_IRQ_No_Context_Switch
+ /* Has interrupt nesting unwound? */
+ CMP X1, #0
+ B.NE Exit_IRQ_No_Context_Switch
- /* Is a context switch required? */
- LDR X0, ullPortYieldRequiredConst
- LDR X1, [X0]
- CMP X1, #0
- B.EQ Exit_IRQ_No_Context_Switch
+ /* Is a context switch required? */
+ LDR X0, ullPortYieldRequiredConst
+ LDR X1, [X0]
+ CMP X1, #0
+ B.EQ Exit_IRQ_No_Context_Switch
- /* Reset ullPortYieldRequired to 0. */
- MOV X2, #0
- STR X2, [X0]
+ /* Reset ullPortYieldRequired to 0. */
+ MOV X2, #0
+ STR X2, [X0]
- /* Restore volatile registers. */
- LDP X4, X5, [SP], #0x10 /* SPSR and ELR. */
+ /* Restore volatile registers. */
+ LDP X4, X5, [SP], #0x10 /* SPSR and ELR. */
#if defined( GUEST )
- MSR SPSR_EL1, X5
- MSR ELR_EL1, X4
+ MSR SPSR_EL1, X5
+ MSR ELR_EL1, X4
#else
- MSR SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */
- MSR ELR_EL3, X4
+ MSR SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */
+ MSR ELR_EL3, X4
#endif
- DSB SY
- ISB SY
+ DSB SY
+ ISB SY
- LDP X29, X30, [SP], #0x10
- LDP X18, X19, [SP], #0x10
- LDP X16, X17, [SP], #0x10
- LDP X14, X15, [SP], #0x10
- LDP X12, X13, [SP], #0x10
- LDP X10, X11, [SP], #0x10
- LDP X8, X9, [SP], #0x10
- LDP X6, X7, [SP], #0x10
- LDP X4, X5, [SP], #0x10
- LDP X2, X3, [SP], #0x10
- LDP X0, X1, [SP], #0x10
+ LDP X29, X30, [SP], #0x10
+ LDP X18, X19, [SP], #0x10
+ LDP X16, X17, [SP], #0x10
+ LDP X14, X15, [SP], #0x10
+ LDP X12, X13, [SP], #0x10
+ LDP X10, X11, [SP], #0x10
+ LDP X8, X9, [SP], #0x10
+ LDP X6, X7, [SP], #0x10
+ LDP X4, X5, [SP], #0x10
+ LDP X2, X3, [SP], #0x10
+ LDP X0, X1, [SP], #0x10
- /* Save the context of the current task and select a new task to run. */
- portSAVE_CONTEXT
- BL vTaskSwitchContext
- portRESTORE_CONTEXT
+ /* Save the context of the current task and select a new task to run. */
+ portSAVE_CONTEXT
+ BL vTaskSwitchContext
+ portRESTORE_CONTEXT
Exit_IRQ_No_Context_Switch:
- /* Restore volatile registers. */
- LDP X4, X5, [SP], #0x10 /* SPSR and ELR. */
+ /* Restore volatile registers. */
+ LDP X4, X5, [SP], #0x10 /* SPSR and ELR. */
#if defined( GUEST )
- MSR SPSR_EL1, X5
- MSR ELR_EL1, X4
+ MSR SPSR_EL1, X5
+ MSR ELR_EL1, X4
#else
- MSR SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */
- MSR ELR_EL3, X4
+ MSR SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */
+ MSR ELR_EL3, X4
#endif
- DSB SY
- ISB SY
+ DSB SY
+ ISB SY
- LDP X29, X30, [SP], #0x10
- LDP X18, X19, [SP], #0x10
- LDP X16, X17, [SP], #0x10
- LDP X14, X15, [SP], #0x10
- LDP X12, X13, [SP], #0x10
- LDP X10, X11, [SP], #0x10
- LDP X8, X9, [SP], #0x10
- LDP X6, X7, [SP], #0x10
- LDP X4, X5, [SP], #0x10
- LDP X2, X3, [SP], #0x10
- LDP X0, X1, [SP], #0x10
+ LDP X29, X30, [SP], #0x10
+ LDP X18, X19, [SP], #0x10
+ LDP X16, X17, [SP], #0x10
+ LDP X14, X15, [SP], #0x10
+ LDP X12, X13, [SP], #0x10
+ LDP X10, X11, [SP], #0x10
+ LDP X8, X9, [SP], #0x10
+ LDP X6, X7, [SP], #0x10
+ LDP X4, X5, [SP], #0x10
+ LDP X2, X3, [SP], #0x10
+ LDP X0, X1, [SP], #0x10
- ERET
+ ERET
diff --git a/portable/GCC/ARM_CA53_64_BIT_SRE/portmacro.h b/portable/GCC/ARM_CA53_64_BIT_SRE/portmacro.h
index 2cfeb80..d8d911f 100644
--- a/portable/GCC/ARM_CA53_64_BIT_SRE/portmacro.h
+++ b/portable/GCC/ARM_CA53_64_BIT_SRE/portmacro.h
@@ -30,7 +30,7 @@
#define PORTMACRO_H
#ifdef __cplusplus
- extern "C" {
+ extern "C" {
#endif
/*-----------------------------------------------------------
@@ -44,13 +44,13 @@
*/
/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT short
-#define portSTACK_TYPE size_t
-#define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE size_t
+#define portBASE_TYPE long
typedef portSTACK_TYPE StackType_t;
typedef portBASE_TYPE BaseType_t;
@@ -66,10 +66,10 @@
/*-----------------------------------------------------------*/
/* Hardware specifics. */
-#define portSTACK_GROWTH ( -1 )
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT 16
-#define portPOINTER_SIZE_TYPE uint64_t
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 16
+#define portPOINTER_SIZE_TYPE uint64_t
/*-----------------------------------------------------------*/
@@ -77,20 +77,20 @@
/* Called at the end of an ISR that can cause a context switch. */
#define portEND_SWITCHING_ISR( xSwitchRequired )\
-{ \
-extern uint64_t ullPortYieldRequired; \
- \
- if( xSwitchRequired != pdFALSE ) \
- { \
- ullPortYieldRequired = pdTRUE; \
- } \
+{ \
+extern uint64_t ullPortYieldRequired; \
+ \
+ if( xSwitchRequired != pdFALSE ) \
+ { \
+ ullPortYieldRequired = pdTRUE; \
+ } \
}
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
#if defined( GUEST )
- #define portYIELD() __asm volatile ( "SVC 0" ::: "memory" )
+ #define portYIELD() __asm volatile ( "SVC 0" ::: "memory" )
#else
- #define portYIELD() __asm volatile ( "SMC 0" ::: "memory" )
+ #define portYIELD() __asm volatile ( "SMC 0" ::: "memory" )
#endif
/*-----------------------------------------------------------
* Critical section control
@@ -102,31 +102,31 @@
extern void vPortClearInterruptMask( UBaseType_t uxNewMaskValue );
extern void vPortInstallFreeRTOSVectorTable( void );
-#define portDISABLE_INTERRUPTS() \
- __asm volatile ( "MSR DAIFSET, #2" ::: "memory" ); \
- __asm volatile ( "DSB SY" ); \
- __asm volatile ( "ISB SY" );
+#define portDISABLE_INTERRUPTS() \
+ __asm volatile ( "MSR DAIFSET, #2" ::: "memory" ); \
+ __asm volatile ( "DSB SY" ); \
+ __asm volatile ( "ISB SY" );
-#define portENABLE_INTERRUPTS() \
- __asm volatile ( "MSR DAIFCLR, #2" ::: "memory" ); \
- __asm volatile ( "DSB SY" ); \
- __asm volatile ( "ISB SY" );
+#define portENABLE_INTERRUPTS() \
+ __asm volatile ( "MSR DAIFCLR, #2" ::: "memory" ); \
+ __asm volatile ( "DSB SY" ); \
+ __asm volatile ( "ISB SY" );
/* These macros do not globally disable/enable interrupts. They do mask off
interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
-#define portENTER_CRITICAL() vPortEnterCritical();
-#define portEXIT_CRITICAL() vPortExitCritical();
-#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMask()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask(x)
+#define portENTER_CRITICAL() vPortEnterCritical();
+#define portEXIT_CRITICAL() vPortExitCritical();
+#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask(x)
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. These are
not required for this port but included in case common demo code that uses these
macros is used. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
/* Prototype of the FreeRTOS tick handler. This must be installed as the
handler for whichever peripheral is used to generate the RTOS tick. */
@@ -142,56 +142,55 @@
/* Architecture specific optimisations. */
#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
#endif
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
- /* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+ /* Store/clear the ready priorities in a bit map. */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
- /*-----------------------------------------------------------*/
+ /*-----------------------------------------------------------*/
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) )
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) )
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
#ifdef configASSERT
- void vPortValidateInterruptPriority( void );
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
#endif /* configASSERT */
#define portNOP() __asm volatile( "NOP" )
#define portINLINE __inline
#ifdef __cplusplus
- } /* extern C */
+ } /* extern C */
#endif
/* The number of bits to shift for an interrupt priority is dependent on the
number of bits implemented by the interrupt controller. */
#if configUNIQUE_INTERRUPT_PRIORITIES == 16
- #define portPRIORITY_SHIFT 4
- #define portMAX_BINARY_POINT_VALUE 3
+ #define portPRIORITY_SHIFT 4
+ #define portMAX_BINARY_POINT_VALUE 3
#elif configUNIQUE_INTERRUPT_PRIORITIES == 32
- #define portPRIORITY_SHIFT 3
- #define portMAX_BINARY_POINT_VALUE 2
+ #define portPRIORITY_SHIFT 3
+ #define portMAX_BINARY_POINT_VALUE 2
#elif configUNIQUE_INTERRUPT_PRIORITIES == 64
- #define portPRIORITY_SHIFT 2
- #define portMAX_BINARY_POINT_VALUE 1
+ #define portPRIORITY_SHIFT 2
+ #define portMAX_BINARY_POINT_VALUE 1
#elif configUNIQUE_INTERRUPT_PRIORITIES == 128
- #define portPRIORITY_SHIFT 1
- #define portMAX_BINARY_POINT_VALUE 0
+ #define portPRIORITY_SHIFT 1
+ #define portMAX_BINARY_POINT_VALUE 0
#elif configUNIQUE_INTERRUPT_PRIORITIES == 256
- #define portPRIORITY_SHIFT 0
- #define portMAX_BINARY_POINT_VALUE 0
+ #define portPRIORITY_SHIFT 0
+ #define portMAX_BINARY_POINT_VALUE 0
#else
- #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
+ #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
#endif
#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
#endif /* PORTMACRO_H */
-
diff --git a/portable/GCC/ARM_CA9/port.c b/portable/GCC/ARM_CA9/port.c
index 6dbccf3..75e69f8 100644
--- a/portable/GCC/ARM_CA9/port.c
+++ b/portable/GCC/ARM_CA9/port.c
@@ -1,570 +1,570 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/* Standard includes. */
-#include <stdlib.h>
-#include <string.h>
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
- #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
-#endif
-
-#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
- #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
-#endif
-
-#ifndef configUNIQUE_INTERRUPT_PRIORITIES
- #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
-#endif
-
-#ifndef configSETUP_TICK_INTERRUPT
- #error configSETUP_TICK_INTERRUPT() must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
-#endif /* configSETUP_TICK_INTERRUPT */
-
-#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
-#endif
-
-#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
-#endif
-
-#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
-#endif
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
- /* Check the configuration. */
- #if( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-/* In case security extensions are implemented. */
-#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
-#endif
-
-/* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in
-portmacro.h. */
-#ifndef configCLEAR_TICK_INTERRUPT
- #define configCLEAR_TICK_INTERRUPT()
-#endif
-
-/* A critical section is exited when the critical section nesting count reaches
-this value. */
-#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
-
-/* In all GICs 255 can be written to the priority mask register to unmask all
-(but the lowest) interrupt priority. */
-#define portUNMASK_VALUE ( 0xFFUL )
-
-/* Tasks are not created with a floating point context, but can be given a
-floating point context after they have been created. A variable is stored as
-part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
-does not have an FPU context, or any other value if the task does have an FPU
-context. */
-#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
-
-/* Constants required to setup the initial task context. */
-#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
-#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
-#define portINTERRUPT_ENABLE_BIT ( 0x80UL )
-#define portTHUMB_MODE_ADDRESS ( 0x01UL )
-
-/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
-point is zero. */
-#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 )
-
-/* Masks all bits in the APSR other than the mode bits. */
-#define portAPSR_MODE_BITS_MASK ( 0x1F )
-
-/* The value of the mode bits in the APSR when the CPU is executing in user
-mode. */
-#define portAPSR_USER_MODE ( 0x10 )
-
-/* The critical section macros only mask interrupts up to an application
-determined priority level. Sometimes it is necessary to turn interrupt off in
-the CPU itself before modifying certain hardware registers. */
-#define portCPU_IRQ_DISABLE() \
- __asm volatile ( "CPSID i" ::: "memory" ); \
- __asm volatile ( "DSB" ); \
- __asm volatile ( "ISB" );
-
-#define portCPU_IRQ_ENABLE() \
- __asm volatile ( "CPSIE i" ::: "memory" ); \
- __asm volatile ( "DSB" ); \
- __asm volatile ( "ISB" );
-
-
-/* Macro to unmask all interrupt priorities. */
-#define portCLEAR_INTERRUPT_MASK() \
-{ \
- portCPU_IRQ_DISABLE(); \
- portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
- __asm volatile ( "DSB \n" \
- "ISB \n" ); \
- portCPU_IRQ_ENABLE(); \
-}
-
-#define portINTERRUPT_PRIORITY_REGISTER_OFFSET 0x400UL
-#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
-#define portBIT_0_SET ( ( uint8_t ) 0x01 )
-
-/* Let the user override the pre-loading of the initial LR with the address of
-prvTaskExitError() in case it messes up unwinding of the stack in the
-debugger. */
-#ifdef configTASK_RETURN_ADDRESS
- #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
-#else
- #define portTASK_RETURN_ADDRESS prvTaskExitError
-#endif
-
-/* The space on the stack required to hold the FPU registers. This is 32 64-bit
-registers, plus a 32-bit status register. */
-#define portFPU_REGISTER_WORDS ( ( 32 * 2 ) + 1 )
-
-/*-----------------------------------------------------------*/
-
-/*
- * Starts the first task executing. This function is necessarily written in
- * assembly code so is implemented in portASM.s.
- */
-extern void vPortRestoreTaskContext( void );
-
-/*
- * Used to catch tasks that attempt to return from their implementing function.
- */
-static void prvTaskExitError( void );
-
-/*
- * If the application provides an implementation of vApplicationIRQHandler(),
- * then it will get called directly without saving the FPU registers on
- * interrupt entry, and this weak implementation of
- * vApplicationFPUSafeIRQHandler() is just provided to remove linkage errors -
- * it should never actually get called so its implementation contains a
- * call to configASSERT() that will always fail.
- *
- * If the application provides its own implementation of
- * vApplicationFPUSafeIRQHandler() then the implementation of
- * vApplicationIRQHandler() provided in portASM.S will save the FPU registers
- * before calling it.
- *
- * Therefore, if the application writer wants FPU registers to be saved on
- * interrupt entry their IRQ handler must be called
- * vApplicationFPUSafeIRQHandler(), and if the application writer does not want
- * FPU registers to be saved on interrupt entry their IRQ handler must be
- * called vApplicationIRQHandler().
- */
-void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR ) __attribute__((weak) );
-
-/*-----------------------------------------------------------*/
-
-/* A variable is used to keep track of the critical section nesting. This
-variable has to be stored as part of the task context and must be initialised to
-a non zero value to ensure interrupts don't inadvertently become unmasked before
-the scheduler starts. As it is stored as part of the task context it will
-automatically be set to 0 when the first task is started. */
-volatile uint32_t ulCriticalNesting = 9999UL;
-
-/* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then
-a floating point context must be saved and restored for the task. */
-volatile uint32_t ulPortTaskHasFPUContext = pdFALSE;
-
-/* Set to 1 to pend a context switch from an ISR. */
-volatile uint32_t ulPortYieldRequired = pdFALSE;
-
-/* Counts the interrupt nesting depth. A context switch is only performed if
-if the nesting depth is 0. */
-volatile uint32_t ulPortInterruptNesting = 0UL;
-
-/* Used in the asm file. */
-__attribute__(( used )) const uint32_t ulICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
-__attribute__(( used )) const uint32_t ulICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
-__attribute__(( used )) const uint32_t ulICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
-__attribute__(( used )) const uint32_t ulMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
- /* Setup the initial stack of the task. The stack is set exactly as
- expected by the portRESTORE_CONTEXT() macro.
-
- The fist real value on the stack is the status register, which is set for
- system mode, with interrupts enabled. A few NULLs are added first to ensure
- GDB does not try decoding a non-existent return address. */
- *pxTopOfStack = ( StackType_t ) NULL;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) NULL;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) NULL;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
-
- if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
- {
- /* The task will start in THUMB mode. */
- *pxTopOfStack |= portTHUMB_MODE_BIT;
- }
-
- pxTopOfStack--;
-
- /* Next the return address, which in this case is the start of the task. */
- *pxTopOfStack = ( StackType_t ) pxCode;
- pxTopOfStack--;
-
- /* Next all the registers other than the stack pointer. */
- *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack--;
-
- /* The task will start with a critical nesting count of 0 as interrupts are
- enabled. */
- *pxTopOfStack = portNO_CRITICAL_NESTING;
-
- #if( configUSE_TASK_FPU_SUPPORT == 1 )
- {
- /* The task will start without a floating point context. A task that
- uses the floating point hardware must call vPortTaskUsesFPU() before
- executing any floating point instructions. */
- pxTopOfStack--;
- *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
- }
- #elif( configUSE_TASK_FPU_SUPPORT == 2 )
- {
- /* The task will start with a floating point context. Leave enough
- space for the registers - and ensure they are initialised to 0. */
- pxTopOfStack -= portFPU_REGISTER_WORDS;
- memset( pxTopOfStack, 0x00, portFPU_REGISTER_WORDS * sizeof( StackType_t ) );
-
- pxTopOfStack--;
- *pxTopOfStack = pdTRUE;
- ulPortTaskHasFPUContext = pdTRUE;
- }
- #else
- {
- #error Invalid configUSE_TASK_FPU_SUPPORT setting - configUSE_TASK_FPU_SUPPORT must be set to 1, 2, or left undefined.
- }
- #endif
-
- return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
- /* A function that implements a task must not exit or attempt to return to
- its caller as there is nothing to return to. If a task wants to exit it
- should instead call vTaskDelete( NULL ).
-
- Artificially force an assert() to be triggered if configASSERT() is
- defined, then stop here so application writers can catch the error. */
- configASSERT( ulPortInterruptNesting == ~0UL );
- portDISABLE_INTERRUPTS();
- for( ;; );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-uint32_t ulAPSR;
-
- #if( configASSERT_DEFINED == 1 )
- {
- volatile uint32_t ulOriginalPriority;
- volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );
- volatile uint8_t ucMaxPriorityValue;
-
- /* Determine how many priority bits are implemented in the GIC.
-
- Save the interrupt priority value that is about to be clobbered. */
- ulOriginalPriority = *pucFirstUserPriorityRegister;
-
- /* Determine the number of priority bits available. First write to
- all possible bits. */
- *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
-
- /* Read the value back to see how many bits stuck. */
- ucMaxPriorityValue = *pucFirstUserPriorityRegister;
-
- /* Shift to the least significant bits. */
- while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET )
- {
- ucMaxPriorityValue >>= ( uint8_t ) 0x01;
- }
-
- /* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
- value. */
- configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY );
-
- /* Restore the clobbered interrupt priority register to its original
- value. */
- *pucFirstUserPriorityRegister = ulOriginalPriority;
- }
- #endif /* configASSERT_DEFINED */
-
-
- /* Only continue if the CPU is not in User mode. The CPU must be in a
- Privileged mode for the scheduler to start. */
- __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) :: "memory" );
- ulAPSR &= portAPSR_MODE_BITS_MASK;
- configASSERT( ulAPSR != portAPSR_USER_MODE );
-
- if( ulAPSR != portAPSR_USER_MODE )
- {
- /* Only continue if the binary point value is set to its lowest possible
- setting. See the comments in vPortValidateInterruptPriority() below for
- more information. */
- configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
-
- if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
- {
- /* Interrupts are turned off in the CPU itself to ensure tick does
- not execute while the scheduler is being started. Interrupts are
- automatically turned back on in the CPU when the first task starts
- executing. */
- portCPU_IRQ_DISABLE();
-
- /* Start the timer that generates the tick ISR. */
- configSETUP_TICK_INTERRUPT();
-
- /* Start the first task executing. */
- vPortRestoreTaskContext();
- }
- }
-
- /* Will only get here if vTaskStartScheduler() was called with the CPU in
- a non-privileged mode or the binary point register was not set to its lowest
- possible value. prvTaskExitError() is referenced to prevent a compiler
- warning about it being defined but not referenced in the case that the user
- defines their own exit address. */
- ( void ) prvTaskExitError;
- return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
- /* Not implemented in ports where there is nothing to return to.
- Artificially force an assert. */
- configASSERT( ulCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
- /* Mask interrupts up to the max syscall interrupt priority. */
- ulPortSetInterruptMask();
-
- /* Now interrupts are disabled ulCriticalNesting can be accessed
- directly. Increment ulCriticalNesting to keep a count of how many times
- portENTER_CRITICAL() has been called. */
- ulCriticalNesting++;
-
- /* This is not the interrupt safe version of the enter critical function so
- assert() if it is being called from an interrupt context. Only API
- functions that end in "FromISR" can be used in an interrupt. Only assert if
- the critical nesting count is 1 to protect against recursive calls if the
- assert function also uses a critical section. */
- if( ulCriticalNesting == 1 )
- {
- configASSERT( ulPortInterruptNesting == 0 );
- }
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
- if( ulCriticalNesting > portNO_CRITICAL_NESTING )
- {
- /* Decrement the nesting count as the critical section is being
- exited. */
- ulCriticalNesting--;
-
- /* If the nesting level has reached zero then all interrupt
- priorities must be re-enabled. */
- if( ulCriticalNesting == portNO_CRITICAL_NESTING )
- {
- /* Critical nesting has reached zero so all interrupt priorities
- should be unmasked. */
- portCLEAR_INTERRUPT_MASK();
- }
- }
-}
-/*-----------------------------------------------------------*/
-
-void FreeRTOS_Tick_Handler( void )
-{
- /* Set interrupt mask before altering scheduler structures. The tick
- handler runs at the lowest priority, so interrupts cannot already be masked,
- so there is no need to save and restore the current mask value. It is
- necessary to turn off interrupts in the CPU itself while the ICCPMR is being
- updated. */
- portCPU_IRQ_DISABLE();
- portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
- __asm volatile ( "dsb \n"
- "isb \n" ::: "memory" );
- portCPU_IRQ_ENABLE();
-
- /* Increment the RTOS tick. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- ulPortYieldRequired = pdTRUE;
- }
-
- /* Ensure all interrupt priorities are active again. */
- portCLEAR_INTERRUPT_MASK();
- configCLEAR_TICK_INTERRUPT();
-}
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TASK_FPU_SUPPORT != 2 )
-
- void vPortTaskUsesFPU( void )
- {
- uint32_t ulInitialFPSCR = 0;
-
- /* A task is registering the fact that it needs an FPU context. Set the
- FPU flag (which is saved as part of the task context). */
- ulPortTaskHasFPUContext = pdTRUE;
-
- /* Initialise the floating point status register. */
- __asm volatile ( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) : "memory" );
- }
-
-#endif /* configUSE_TASK_FPU_SUPPORT */
-/*-----------------------------------------------------------*/
-
-void vPortClearInterruptMask( uint32_t ulNewMaskValue )
-{
- if( ulNewMaskValue == pdFALSE )
- {
- portCLEAR_INTERRUPT_MASK();
- }
-}
-/*-----------------------------------------------------------*/
-
-uint32_t ulPortSetInterruptMask( void )
-{
-uint32_t ulReturn;
-
- /* Interrupt in the CPU must be turned off while the ICCPMR is being
- updated. */
- portCPU_IRQ_DISABLE();
- if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
- {
- /* Interrupts were already masked. */
- ulReturn = pdTRUE;
- }
- else
- {
- ulReturn = pdFALSE;
- portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
- __asm volatile ( "dsb \n"
- "isb \n" ::: "memory" );
- }
- portCPU_IRQ_ENABLE();
-
- return ulReturn;
-}
-/*-----------------------------------------------------------*/
-
-#if( configASSERT_DEFINED == 1 )
-
- void vPortValidateInterruptPriority( void )
- {
- /* The following assertion will fail if a service routine (ISR) for
- an interrupt that has been assigned a priority above
- configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
- function. ISR safe FreeRTOS API functions must *only* be called
- from interrupts that have been assigned a priority at or below
- configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
- Numerically low interrupt priority numbers represent logically high
- interrupt priorities, therefore the priority of the interrupt must
- be set to a value equal to or numerically *higher* than
- configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
- FreeRTOS maintains separate thread and ISR API functions to ensure
- interrupt entry is as fast and simple as possible. */
- configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
-
- /* Priority grouping: The interrupt controller (GIC) allows the bits
- that define each interrupt's priority to be split between bits that
- define the interrupt's pre-emption priority bits and bits that define
- the interrupt's sub-priority. For simplicity all bits must be defined
- to be pre-emption priority bits. The following assertion will fail if
- this is not the case (if some bits represent a sub-priority).
-
- The priority grouping is configured by the GIC's binary point register
- (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest
- possible value (which may be above 0). */
- configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
- }
-
-#endif /* configASSERT_DEFINED */
-/*-----------------------------------------------------------*/
-
-void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR )
-{
- ( void ) ulICCIAR;
- configASSERT( ( volatile void * ) NULL );
-}
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Standard includes. */
+#include <stdlib.h>
+#include <string.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
+ #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
+ #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#ifndef configUNIQUE_INTERRUPT_PRIORITIES
+ #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#ifndef configSETUP_TICK_INTERRUPT
+ #error configSETUP_TICK_INTERRUPT() must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif /* configSETUP_TICK_INTERRUPT */
+
+#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
+#endif
+
+#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+ /* Check the configuration. */
+ #if( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/* In case security extensions are implemented. */
+#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
+#endif
+
+/* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in
+portmacro.h. */
+#ifndef configCLEAR_TICK_INTERRUPT
+ #define configCLEAR_TICK_INTERRUPT()
+#endif
+
+/* A critical section is exited when the critical section nesting count reaches
+this value. */
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
+
+/* In all GICs 255 can be written to the priority mask register to unmask all
+(but the lowest) interrupt priority. */
+#define portUNMASK_VALUE ( 0xFFUL )
+
+/* Tasks are not created with a floating point context, but can be given a
+floating point context after they have been created. A variable is stored as
+part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+does not have an FPU context, or any other value if the task does have an FPU
+context. */
+#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
+
+/* Constants required to setup the initial task context. */
+#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
+#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
+#define portINTERRUPT_ENABLE_BIT ( 0x80UL )
+#define portTHUMB_MODE_ADDRESS ( 0x01UL )
+
+/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
+point is zero. */
+#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 )
+
+/* Masks all bits in the APSR other than the mode bits. */
+#define portAPSR_MODE_BITS_MASK ( 0x1F )
+
+/* The value of the mode bits in the APSR when the CPU is executing in user
+mode. */
+#define portAPSR_USER_MODE ( 0x10 )
+
+/* The critical section macros only mask interrupts up to an application
+determined priority level. Sometimes it is necessary to turn interrupt off in
+the CPU itself before modifying certain hardware registers. */
+#define portCPU_IRQ_DISABLE() \
+ __asm volatile ( "CPSID i" ::: "memory" ); \
+ __asm volatile ( "DSB" ); \
+ __asm volatile ( "ISB" );
+
+#define portCPU_IRQ_ENABLE() \
+ __asm volatile ( "CPSIE i" ::: "memory" ); \
+ __asm volatile ( "DSB" ); \
+ __asm volatile ( "ISB" );
+
+
+/* Macro to unmask all interrupt priorities. */
+#define portCLEAR_INTERRUPT_MASK() \
+{ \
+ portCPU_IRQ_DISABLE(); \
+ portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
+ __asm volatile ( "DSB \n" \
+ "ISB \n" ); \
+ portCPU_IRQ_ENABLE(); \
+}
+
+#define portINTERRUPT_PRIORITY_REGISTER_OFFSET 0x400UL
+#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
+#define portBIT_0_SET ( ( uint8_t ) 0x01 )
+
+/* Let the user override the pre-loading of the initial LR with the address of
+prvTaskExitError() in case it messes up unwinding of the stack in the
+debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
+#else
+ #define portTASK_RETURN_ADDRESS prvTaskExitError
+#endif
+
+/* The space on the stack required to hold the FPU registers. This is 32 64-bit
+registers, plus a 32-bit status register. */
+#define portFPU_REGISTER_WORDS ( ( 32 * 2 ) + 1 )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Starts the first task executing. This function is necessarily written in
+ * assembly code so is implemented in portASM.s.
+ */
+extern void vPortRestoreTaskContext( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*
+ * If the application provides an implementation of vApplicationIRQHandler(),
+ * then it will get called directly without saving the FPU registers on
+ * interrupt entry, and this weak implementation of
+ * vApplicationFPUSafeIRQHandler() is just provided to remove linkage errors -
+ * it should never actually get called so its implementation contains a
+ * call to configASSERT() that will always fail.
+ *
+ * If the application provides its own implementation of
+ * vApplicationFPUSafeIRQHandler() then the implementation of
+ * vApplicationIRQHandler() provided in portASM.S will save the FPU registers
+ * before calling it.
+ *
+ * Therefore, if the application writer wants FPU registers to be saved on
+ * interrupt entry their IRQ handler must be called
+ * vApplicationFPUSafeIRQHandler(), and if the application writer does not want
+ * FPU registers to be saved on interrupt entry their IRQ handler must be
+ * called vApplicationIRQHandler().
+ */
+void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR ) __attribute__((weak) );
+
+/*-----------------------------------------------------------*/
+
+/* A variable is used to keep track of the critical section nesting. This
+variable has to be stored as part of the task context and must be initialised to
+a non zero value to ensure interrupts don't inadvertently become unmasked before
+the scheduler starts. As it is stored as part of the task context it will
+automatically be set to 0 when the first task is started. */
+volatile uint32_t ulCriticalNesting = 9999UL;
+
+/* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then
+a floating point context must be saved and restored for the task. */
+volatile uint32_t ulPortTaskHasFPUContext = pdFALSE;
+
+/* Set to 1 to pend a context switch from an ISR. */
+volatile uint32_t ulPortYieldRequired = pdFALSE;
+
+/* Counts the interrupt nesting depth. A context switch is only performed if
+if the nesting depth is 0. */
+volatile uint32_t ulPortInterruptNesting = 0UL;
+
+/* Used in the asm file. */
+__attribute__(( used )) const uint32_t ulICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
+__attribute__(( used )) const uint32_t ulICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
+__attribute__(( used )) const uint32_t ulICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
+__attribute__(( used )) const uint32_t ulMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+ /* Setup the initial stack of the task. The stack is set exactly as
+ expected by the portRESTORE_CONTEXT() macro.
+
+ The fist real value on the stack is the status register, which is set for
+ system mode, with interrupts enabled. A few NULLs are added first to ensure
+ GDB does not try decoding a non-existent return address. */
+ *pxTopOfStack = ( StackType_t ) NULL;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) NULL;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) NULL;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+
+ if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
+ {
+ /* The task will start in THUMB mode. */
+ *pxTopOfStack |= portTHUMB_MODE_BIT;
+ }
+
+ pxTopOfStack--;
+
+ /* Next the return address, which in this case is the start of the task. */
+ *pxTopOfStack = ( StackType_t ) pxCode;
+ pxTopOfStack--;
+
+ /* Next all the registers other than the stack pointer. */
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
+
+ /* The task will start with a critical nesting count of 0 as interrupts are
+ enabled. */
+ *pxTopOfStack = portNO_CRITICAL_NESTING;
+
+ #if( configUSE_TASK_FPU_SUPPORT == 1 )
+ {
+ /* The task will start without a floating point context. A task that
+ uses the floating point hardware must call vPortTaskUsesFPU() before
+ executing any floating point instructions. */
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+ }
+ #elif( configUSE_TASK_FPU_SUPPORT == 2 )
+ {
+ /* The task will start with a floating point context. Leave enough
+ space for the registers - and ensure they are initialised to 0. */
+ pxTopOfStack -= portFPU_REGISTER_WORDS;
+ memset( pxTopOfStack, 0x00, portFPU_REGISTER_WORDS * sizeof( StackType_t ) );
+
+ pxTopOfStack--;
+ *pxTopOfStack = pdTRUE;
+ ulPortTaskHasFPUContext = pdTRUE;
+ }
+ #else
+ {
+ #error Invalid configUSE_TASK_FPU_SUPPORT setting - configUSE_TASK_FPU_SUPPORT must be set to 1, 2, or left undefined.
+ }
+ #endif
+
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+ /* A function that implements a task must not exit or attempt to return to
+ its caller as there is nothing to return to. If a task wants to exit it
+ should instead call vTaskDelete( NULL ).
+
+ Artificially force an assert() to be triggered if configASSERT() is
+ defined, then stop here so application writers can catch the error. */
+ configASSERT( ulPortInterruptNesting == ~0UL );
+ portDISABLE_INTERRUPTS();
+ for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+uint32_t ulAPSR;
+
+ #if( configASSERT_DEFINED == 1 )
+ {
+ volatile uint32_t ulOriginalPriority;
+ volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine how many priority bits are implemented in the GIC.
+
+ Save the interrupt priority value that is about to be clobbered. */
+ ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+ /* Determine the number of priority bits available. First write to
+ all possible bits. */
+ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+ /* Shift to the least significant bits. */
+ while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET )
+ {
+ ucMaxPriorityValue >>= ( uint8_t ) 0x01;
+ }
+
+ /* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
+ value. */
+ configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY );
+
+ /* Restore the clobbered interrupt priority register to its original
+ value. */
+ *pucFirstUserPriorityRegister = ulOriginalPriority;
+ }
+ #endif /* configASSERT_DEFINED */
+
+
+ /* Only continue if the CPU is not in User mode. The CPU must be in a
+ Privileged mode for the scheduler to start. */
+ __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) :: "memory" );
+ ulAPSR &= portAPSR_MODE_BITS_MASK;
+ configASSERT( ulAPSR != portAPSR_USER_MODE );
+
+ if( ulAPSR != portAPSR_USER_MODE )
+ {
+ /* Only continue if the binary point value is set to its lowest possible
+ setting. See the comments in vPortValidateInterruptPriority() below for
+ more information. */
+ configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
+
+ if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
+ {
+ /* Interrupts are turned off in the CPU itself to ensure tick does
+ not execute while the scheduler is being started. Interrupts are
+ automatically turned back on in the CPU when the first task starts
+ executing. */
+ portCPU_IRQ_DISABLE();
+
+ /* Start the timer that generates the tick ISR. */
+ configSETUP_TICK_INTERRUPT();
+
+ /* Start the first task executing. */
+ vPortRestoreTaskContext();
+ }
+ }
+
+ /* Will only get here if vTaskStartScheduler() was called with the CPU in
+ a non-privileged mode or the binary point register was not set to its lowest
+ possible value. prvTaskExitError() is referenced to prevent a compiler
+ warning about it being defined but not referenced in the case that the user
+ defines their own exit address. */
+ ( void ) prvTaskExitError;
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+ /* Not implemented in ports where there is nothing to return to.
+ Artificially force an assert. */
+ configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+ /* Mask interrupts up to the max syscall interrupt priority. */
+ ulPortSetInterruptMask();
+
+ /* Now interrupts are disabled ulCriticalNesting can be accessed
+ directly. Increment ulCriticalNesting to keep a count of how many times
+ portENTER_CRITICAL() has been called. */
+ ulCriticalNesting++;
+
+ /* This is not the interrupt safe version of the enter critical function so
+ assert() if it is being called from an interrupt context. Only API
+ functions that end in "FromISR" can be used in an interrupt. Only assert if
+ the critical nesting count is 1 to protect against recursive calls if the
+ assert function also uses a critical section. */
+ if( ulCriticalNesting == 1 )
+ {
+ configASSERT( ulPortInterruptNesting == 0 );
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+ if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+ {
+ /* Decrement the nesting count as the critical section is being
+ exited. */
+ ulCriticalNesting--;
+
+ /* If the nesting level has reached zero then all interrupt
+ priorities must be re-enabled. */
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+ {
+ /* Critical nesting has reached zero so all interrupt priorities
+ should be unmasked. */
+ portCLEAR_INTERRUPT_MASK();
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+void FreeRTOS_Tick_Handler( void )
+{
+ /* Set interrupt mask before altering scheduler structures. The tick
+ handler runs at the lowest priority, so interrupts cannot already be masked,
+ so there is no need to save and restore the current mask value. It is
+ necessary to turn off interrupts in the CPU itself while the ICCPMR is being
+ updated. */
+ portCPU_IRQ_DISABLE();
+ portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+ __asm volatile ( "dsb \n"
+ "isb \n" ::: "memory" );
+ portCPU_IRQ_ENABLE();
+
+ /* Increment the RTOS tick. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ ulPortYieldRequired = pdTRUE;
+ }
+
+ /* Ensure all interrupt priorities are active again. */
+ portCLEAR_INTERRUPT_MASK();
+ configCLEAR_TICK_INTERRUPT();
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_FPU_SUPPORT != 2 )
+
+ void vPortTaskUsesFPU( void )
+ {
+ uint32_t ulInitialFPSCR = 0;
+
+ /* A task is registering the fact that it needs an FPU context. Set the
+ FPU flag (which is saved as part of the task context). */
+ ulPortTaskHasFPUContext = pdTRUE;
+
+ /* Initialise the floating point status register. */
+ __asm volatile ( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) : "memory" );
+ }
+
+#endif /* configUSE_TASK_FPU_SUPPORT */
+/*-----------------------------------------------------------*/
+
+void vPortClearInterruptMask( uint32_t ulNewMaskValue )
+{
+ if( ulNewMaskValue == pdFALSE )
+ {
+ portCLEAR_INTERRUPT_MASK();
+ }
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulPortSetInterruptMask( void )
+{
+uint32_t ulReturn;
+
+ /* Interrupt in the CPU must be turned off while the ICCPMR is being
+ updated. */
+ portCPU_IRQ_DISABLE();
+ if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
+ {
+ /* Interrupts were already masked. */
+ ulReturn = pdTRUE;
+ }
+ else
+ {
+ ulReturn = pdFALSE;
+ portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+ __asm volatile ( "dsb \n"
+ "isb \n" ::: "memory" );
+ }
+ portCPU_IRQ_ENABLE();
+
+ return ulReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if( configASSERT_DEFINED == 1 )
+
+ void vPortValidateInterruptPriority( void )
+ {
+ /* The following assertion will fail if a service routine (ISR) for
+ an interrupt that has been assigned a priority above
+ configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+ function. ISR safe FreeRTOS API functions must *only* be called
+ from interrupts that have been assigned a priority at or below
+ configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+ Numerically low interrupt priority numbers represent logically high
+ interrupt priorities, therefore the priority of the interrupt must
+ be set to a value equal to or numerically *higher* than
+ configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+ FreeRTOS maintains separate thread and ISR API functions to ensure
+ interrupt entry is as fast and simple as possible. */
+ configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
+
+ /* Priority grouping: The interrupt controller (GIC) allows the bits
+ that define each interrupt's priority to be split between bits that
+ define the interrupt's pre-emption priority bits and bits that define
+ the interrupt's sub-priority. For simplicity all bits must be defined
+ to be pre-emption priority bits. The following assertion will fail if
+ this is not the case (if some bits represent a sub-priority).
+
+ The priority grouping is configured by the GIC's binary point register
+ (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest
+ possible value (which may be above 0). */
+ configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
+ }
+
+#endif /* configASSERT_DEFINED */
+/*-----------------------------------------------------------*/
+
+void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR )
+{
+ ( void ) ulICCIAR;
+ configASSERT( ( volatile void * ) NULL );
+}
diff --git a/portable/GCC/ARM_CA9/portASM.S b/portable/GCC/ARM_CA9/portASM.S
index 051e203..150cfab 100644
--- a/portable/GCC/ARM_CA9/portASM.S
+++ b/portable/GCC/ARM_CA9/portASM.S
@@ -1,324 +1,319 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
- .eabi_attribute Tag_ABI_align_preserved, 1
- .text
- .arm
-
- .set SYS_MODE, 0x1f
- .set SVC_MODE, 0x13
- .set IRQ_MODE, 0x12
-
- /* Hardware registers. */
- .extern ulICCIAR
- .extern ulICCEOIR
- .extern ulICCPMR
-
- /* Variables and functions. */
- .extern ulMaxAPIPriorityMask
- .extern _freertos_vector_table
- .extern pxCurrentTCB
- .extern vTaskSwitchContext
- .extern vApplicationIRQHandler
- .extern ulPortInterruptNesting
- .extern ulPortTaskHasFPUContext
-
- .global FreeRTOS_IRQ_Handler
- .global FreeRTOS_SWI_Handler
- .global vPortRestoreTaskContext
-
-
-
-
-.macro portSAVE_CONTEXT
-
- /* Save the LR and SPSR onto the system mode stack before switching to
- system mode to save the remaining system mode registers. */
- SRSDB sp!, #SYS_MODE
- CPS #SYS_MODE
- PUSH {R0-R12, R14}
-
- /* Push the critical nesting count. */
- LDR R2, ulCriticalNestingConst
- LDR R1, [R2]
- PUSH {R1}
-
- /* Does the task have a floating point context that needs saving? If
- ulPortTaskHasFPUContext is 0 then no. */
- LDR R2, ulPortTaskHasFPUContextConst
- LDR R3, [R2]
- CMP R3, #0
-
- /* Save the floating point context, if any. */
- FMRXNE R1, FPSCR
- VPUSHNE {D0-D15}
- VPUSHNE {D16-D31}
- PUSHNE {R1}
-
- /* Save ulPortTaskHasFPUContext itself. */
- PUSH {R3}
-
- /* Save the stack pointer in the TCB. */
- LDR R0, pxCurrentTCBConst
- LDR R1, [R0]
- STR SP, [R1]
-
- .endm
-
-; /**********************************************************************/
-
-.macro portRESTORE_CONTEXT
-
- /* Set the SP to point to the stack of the task being restored. */
- LDR R0, pxCurrentTCBConst
- LDR R1, [R0]
- LDR SP, [R1]
-
- /* Is there a floating point context to restore? If the restored
- ulPortTaskHasFPUContext is zero then no. */
- LDR R0, ulPortTaskHasFPUContextConst
- POP {R1}
- STR R1, [R0]
- CMP R1, #0
-
- /* Restore the floating point context, if any. */
- POPNE {R0}
- VPOPNE {D16-D31}
- VPOPNE {D0-D15}
- VMSRNE FPSCR, R0
-
- /* Restore the critical section nesting depth. */
- LDR R0, ulCriticalNestingConst
- POP {R1}
- STR R1, [R0]
-
- /* Ensure the priority mask is correct for the critical nesting depth. */
- LDR R2, ulICCPMRConst
- LDR R2, [R2]
- CMP R1, #0
- MOVEQ R4, #255
- LDRNE R4, ulMaxAPIPriorityMaskConst
- LDRNE R4, [R4]
- STR R4, [R2]
-
- /* Restore all system mode registers other than the SP (which is already
- being used). */
- POP {R0-R12, R14}
-
- /* Return to the task code, loading CPSR on the way. */
- RFEIA sp!
-
- .endm
-
-
-
-
-/******************************************************************************
- * SVC handler is used to start the scheduler.
- *****************************************************************************/
-.align 4
-.type FreeRTOS_SWI_Handler, %function
-FreeRTOS_SWI_Handler:
- /* Save the context of the current task and select a new task to run. */
- portSAVE_CONTEXT
- LDR R0, vTaskSwitchContextConst
- BLX R0
- portRESTORE_CONTEXT
-
-
-/******************************************************************************
- * vPortRestoreTaskContext is used to start the scheduler.
- *****************************************************************************/
-.type vPortRestoreTaskContext, %function
-vPortRestoreTaskContext:
- /* Switch to system mode. */
- CPS #SYS_MODE
- portRESTORE_CONTEXT
-
-.align 4
-.type FreeRTOS_IRQ_Handler, %function
-FreeRTOS_IRQ_Handler:
- /* Return to the interrupted instruction. */
- SUB lr, lr, #4
-
- /* Push the return address and SPSR. */
- PUSH {lr}
- MRS lr, SPSR
- PUSH {lr}
-
- /* Change to supervisor mode to allow reentry. */
- CPS #SVC_MODE
-
- /* Push used registers. */
- PUSH {r0-r4, r12}
-
- /* Increment nesting count. r3 holds the address of ulPortInterruptNesting
- for future use. r1 holds the original ulPortInterruptNesting value for
- future use. */
- LDR r3, ulPortInterruptNestingConst
- LDR r1, [r3]
- ADD r4, r1, #1
- STR r4, [r3]
-
- /* Read value from the interrupt acknowledge register, which is stored in r0
- for future parameter and interrupt clearing use. */
- LDR r2, ulICCIARConst
- LDR r2, [r2]
- LDR r0, [r2]
-
- /* Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for
- future use. _RB_ Does this ever actually need to be done provided the start
- of the stack is 8-byte aligned? */
- MOV r2, sp
- AND r2, r2, #4
- SUB sp, sp, r2
-
- /* Call the interrupt handler. r4 pushed to maintain alignment. */
- PUSH {r0-r4, lr}
- LDR r1, vApplicationIRQHandlerConst
- BLX r1
- POP {r0-r4, lr}
- ADD sp, sp, r2
-
- CPSID i
- DSB
- ISB
-
- /* Write the value read from ICCIAR to ICCEOIR. */
- LDR r4, ulICCEOIRConst
- LDR r4, [r4]
- STR r0, [r4]
-
- /* Restore the old nesting count. */
- STR r1, [r3]
-
- /* A context switch is never performed if the nesting count is not 0. */
- CMP r1, #0
- BNE exit_without_switch
-
- /* Did the interrupt request a context switch? r1 holds the address of
- ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
- use. */
- LDR r1, =ulPortYieldRequired
- LDR r0, [r1]
- CMP r0, #0
- BNE switch_before_exit
-
-exit_without_switch:
- /* No context switch. Restore used registers, LR_irq and SPSR before
- returning. */
- POP {r0-r4, r12}
- CPS #IRQ_MODE
- POP {LR}
- MSR SPSR_cxsf, LR
- POP {LR}
- MOVS PC, LR
-
-switch_before_exit:
- /* A context swtich is to be performed. Clear the context switch pending
- flag. */
- MOV r0, #0
- STR r0, [r1]
-
- /* Restore used registers, LR-irq and SPSR before saving the context
- to the task stack. */
- POP {r0-r4, r12}
- CPS #IRQ_MODE
- POP {LR}
- MSR SPSR_cxsf, LR
- POP {LR}
- portSAVE_CONTEXT
-
- /* Call the function that selects the new task to execute.
- vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
- instructions, or 8 byte aligned stack allocated data. LR does not need
- saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */
- LDR R0, vTaskSwitchContextConst
- BLX R0
-
- /* Restore the context of, and branch to, the task selected to execute
- next. */
- portRESTORE_CONTEXT
-
-
-/******************************************************************************
- * If the application provides an implementation of vApplicationIRQHandler(),
- * then it will get called directly without saving the FPU registers on
- * interrupt entry, and this weak implementation of
- * vApplicationIRQHandler() will not get called.
- *
- * If the application provides its own implementation of
- * vApplicationFPUSafeIRQHandler() then this implementation of
- * vApplicationIRQHandler() will be called, save the FPU registers, and then
- * call vApplicationFPUSafeIRQHandler().
- *
- * Therefore, if the application writer wants FPU registers to be saved on
- * interrupt entry their IRQ handler must be called
- * vApplicationFPUSafeIRQHandler(), and if the application writer does not want
- * FPU registers to be saved on interrupt entry their IRQ handler must be
- * called vApplicationIRQHandler().
- *****************************************************************************/
-
-.align 4
-.weak vApplicationIRQHandler
-.type vApplicationIRQHandler, %function
-vApplicationIRQHandler:
- PUSH {LR}
- FMRX R1, FPSCR
- VPUSH {D0-D15}
- VPUSH {D16-D31}
- PUSH {R1}
-
- LDR r1, vApplicationFPUSafeIRQHandlerConst
- BLX r1
-
- POP {R0}
- VPOP {D16-D31}
- VPOP {D0-D15}
- VMSR FPSCR, R0
-
- POP {PC}
-
-
-ulICCIARConst: .word ulICCIAR
-ulICCEOIRConst: .word ulICCEOIR
-ulICCPMRConst: .word ulICCPMR
-pxCurrentTCBConst: .word pxCurrentTCB
-ulCriticalNestingConst: .word ulCriticalNesting
-ulPortTaskHasFPUContextConst: .word ulPortTaskHasFPUContext
-ulMaxAPIPriorityMaskConst: .word ulMaxAPIPriorityMask
-vTaskSwitchContextConst: .word vTaskSwitchContext
-vApplicationIRQHandlerConst: .word vApplicationIRQHandler
-ulPortInterruptNestingConst: .word ulPortInterruptNesting
-vApplicationFPUSafeIRQHandlerConst: .word vApplicationFPUSafeIRQHandler
-
-.end
-
-
-
-
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+ .eabi_attribute Tag_ABI_align_preserved, 1
+ .text
+ .arm
+
+ .set SYS_MODE, 0x1f
+ .set SVC_MODE, 0x13
+ .set IRQ_MODE, 0x12
+
+ /* Hardware registers. */
+ .extern ulICCIAR
+ .extern ulICCEOIR
+ .extern ulICCPMR
+
+ /* Variables and functions. */
+ .extern ulMaxAPIPriorityMask
+ .extern _freertos_vector_table
+ .extern pxCurrentTCB
+ .extern vTaskSwitchContext
+ .extern vApplicationIRQHandler
+ .extern ulPortInterruptNesting
+ .extern ulPortTaskHasFPUContext
+
+ .global FreeRTOS_IRQ_Handler
+ .global FreeRTOS_SWI_Handler
+ .global vPortRestoreTaskContext
+
+
+
+
+.macro portSAVE_CONTEXT
+
+ /* Save the LR and SPSR onto the system mode stack before switching to
+ system mode to save the remaining system mode registers. */
+ SRSDB sp!, #SYS_MODE
+ CPS #SYS_MODE
+ PUSH {R0-R12, R14}
+
+ /* Push the critical nesting count. */
+ LDR R2, ulCriticalNestingConst
+ LDR R1, [R2]
+ PUSH {R1}
+
+ /* Does the task have a floating point context that needs saving? If
+ ulPortTaskHasFPUContext is 0 then no. */
+ LDR R2, ulPortTaskHasFPUContextConst
+ LDR R3, [R2]
+ CMP R3, #0
+
+ /* Save the floating point context, if any. */
+ FMRXNE R1, FPSCR
+ VPUSHNE {D0-D15}
+ VPUSHNE {D16-D31}
+ PUSHNE {R1}
+
+ /* Save ulPortTaskHasFPUContext itself. */
+ PUSH {R3}
+
+ /* Save the stack pointer in the TCB. */
+ LDR R0, pxCurrentTCBConst
+ LDR R1, [R0]
+ STR SP, [R1]
+
+ .endm
+
+; /**********************************************************************/
+
+.macro portRESTORE_CONTEXT
+
+ /* Set the SP to point to the stack of the task being restored. */
+ LDR R0, pxCurrentTCBConst
+ LDR R1, [R0]
+ LDR SP, [R1]
+
+ /* Is there a floating point context to restore? If the restored
+ ulPortTaskHasFPUContext is zero then no. */
+ LDR R0, ulPortTaskHasFPUContextConst
+ POP {R1}
+ STR R1, [R0]
+ CMP R1, #0
+
+ /* Restore the floating point context, if any. */
+ POPNE {R0}
+ VPOPNE {D16-D31}
+ VPOPNE {D0-D15}
+ VMSRNE FPSCR, R0
+
+ /* Restore the critical section nesting depth. */
+ LDR R0, ulCriticalNestingConst
+ POP {R1}
+ STR R1, [R0]
+
+ /* Ensure the priority mask is correct for the critical nesting depth. */
+ LDR R2, ulICCPMRConst
+ LDR R2, [R2]
+ CMP R1, #0
+ MOVEQ R4, #255
+ LDRNE R4, ulMaxAPIPriorityMaskConst
+ LDRNE R4, [R4]
+ STR R4, [R2]
+
+ /* Restore all system mode registers other than the SP (which is already
+ being used). */
+ POP {R0-R12, R14}
+
+ /* Return to the task code, loading CPSR on the way. */
+ RFEIA sp!
+
+ .endm
+
+
+
+
+/******************************************************************************
+ * SVC handler is used to start the scheduler.
+ *****************************************************************************/
+.align 4
+.type FreeRTOS_SWI_Handler, %function
+FreeRTOS_SWI_Handler:
+ /* Save the context of the current task and select a new task to run. */
+ portSAVE_CONTEXT
+ LDR R0, vTaskSwitchContextConst
+ BLX R0
+ portRESTORE_CONTEXT
+
+
+/******************************************************************************
+ * vPortRestoreTaskContext is used to start the scheduler.
+ *****************************************************************************/
+.type vPortRestoreTaskContext, %function
+vPortRestoreTaskContext:
+ /* Switch to system mode. */
+ CPS #SYS_MODE
+ portRESTORE_CONTEXT
+
+.align 4
+.type FreeRTOS_IRQ_Handler, %function
+FreeRTOS_IRQ_Handler:
+ /* Return to the interrupted instruction. */
+ SUB lr, lr, #4
+
+ /* Push the return address and SPSR. */
+ PUSH {lr}
+ MRS lr, SPSR
+ PUSH {lr}
+
+ /* Change to supervisor mode to allow reentry. */
+ CPS #SVC_MODE
+
+ /* Push used registers. */
+ PUSH {r0-r4, r12}
+
+ /* Increment nesting count. r3 holds the address of ulPortInterruptNesting
+ for future use. r1 holds the original ulPortInterruptNesting value for
+ future use. */
+ LDR r3, ulPortInterruptNestingConst
+ LDR r1, [r3]
+ ADD r4, r1, #1
+ STR r4, [r3]
+
+ /* Read value from the interrupt acknowledge register, which is stored in r0
+ for future parameter and interrupt clearing use. */
+ LDR r2, ulICCIARConst
+ LDR r2, [r2]
+ LDR r0, [r2]
+
+ /* Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for
+ future use. _RB_ Does this ever actually need to be done provided the start
+ of the stack is 8-byte aligned? */
+ MOV r2, sp
+ AND r2, r2, #4
+ SUB sp, sp, r2
+
+ /* Call the interrupt handler. r4 pushed to maintain alignment. */
+ PUSH {r0-r4, lr}
+ LDR r1, vApplicationIRQHandlerConst
+ BLX r1
+ POP {r0-r4, lr}
+ ADD sp, sp, r2
+
+ CPSID i
+ DSB
+ ISB
+
+ /* Write the value read from ICCIAR to ICCEOIR. */
+ LDR r4, ulICCEOIRConst
+ LDR r4, [r4]
+ STR r0, [r4]
+
+ /* Restore the old nesting count. */
+ STR r1, [r3]
+
+ /* A context switch is never performed if the nesting count is not 0. */
+ CMP r1, #0
+ BNE exit_without_switch
+
+ /* Did the interrupt request a context switch? r1 holds the address of
+ ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
+ use. */
+ LDR r1, =ulPortYieldRequired
+ LDR r0, [r1]
+ CMP r0, #0
+ BNE switch_before_exit
+
+exit_without_switch:
+ /* No context switch. Restore used registers, LR_irq and SPSR before
+ returning. */
+ POP {r0-r4, r12}
+ CPS #IRQ_MODE
+ POP {LR}
+ MSR SPSR_cxsf, LR
+ POP {LR}
+ MOVS PC, LR
+
+switch_before_exit:
+ /* A context swtich is to be performed. Clear the context switch pending
+ flag. */
+ MOV r0, #0
+ STR r0, [r1]
+
+ /* Restore used registers, LR-irq and SPSR before saving the context
+ to the task stack. */
+ POP {r0-r4, r12}
+ CPS #IRQ_MODE
+ POP {LR}
+ MSR SPSR_cxsf, LR
+ POP {LR}
+ portSAVE_CONTEXT
+
+ /* Call the function that selects the new task to execute.
+ vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
+ instructions, or 8 byte aligned stack allocated data. LR does not need
+ saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */
+ LDR R0, vTaskSwitchContextConst
+ BLX R0
+
+ /* Restore the context of, and branch to, the task selected to execute
+ next. */
+ portRESTORE_CONTEXT
+
+
+/******************************************************************************
+ * If the application provides an implementation of vApplicationIRQHandler(),
+ * then it will get called directly without saving the FPU registers on
+ * interrupt entry, and this weak implementation of
+ * vApplicationIRQHandler() will not get called.
+ *
+ * If the application provides its own implementation of
+ * vApplicationFPUSafeIRQHandler() then this implementation of
+ * vApplicationIRQHandler() will be called, save the FPU registers, and then
+ * call vApplicationFPUSafeIRQHandler().
+ *
+ * Therefore, if the application writer wants FPU registers to be saved on
+ * interrupt entry their IRQ handler must be called
+ * vApplicationFPUSafeIRQHandler(), and if the application writer does not want
+ * FPU registers to be saved on interrupt entry their IRQ handler must be
+ * called vApplicationIRQHandler().
+ *****************************************************************************/
+
+.align 4
+.weak vApplicationIRQHandler
+.type vApplicationIRQHandler, %function
+vApplicationIRQHandler:
+ PUSH {LR}
+ FMRX R1, FPSCR
+ VPUSH {D0-D15}
+ VPUSH {D16-D31}
+ PUSH {R1}
+
+ LDR r1, vApplicationFPUSafeIRQHandlerConst
+ BLX r1
+
+ POP {R0}
+ VPOP {D16-D31}
+ VPOP {D0-D15}
+ VMSR FPSCR, R0
+
+ POP {PC}
+
+
+ulICCIARConst: .word ulICCIAR
+ulICCEOIRConst: .word ulICCEOIR
+ulICCPMRConst: .word ulICCPMR
+pxCurrentTCBConst: .word pxCurrentTCB
+ulCriticalNestingConst: .word ulCriticalNesting
+ulPortTaskHasFPUContextConst: .word ulPortTaskHasFPUContext
+ulMaxAPIPriorityMaskConst: .word ulMaxAPIPriorityMask
+vTaskSwitchContextConst: .word vTaskSwitchContext
+vApplicationIRQHandlerConst: .word vApplicationIRQHandler
+ulPortInterruptNestingConst: .word ulPortInterruptNesting
+vApplicationFPUSafeIRQHandlerConst: .word vApplicationFPUSafeIRQHandler
+
+.end
diff --git a/portable/GCC/ARM_CA9/portmacro.h b/portable/GCC/ARM_CA9/portmacro.h
index af928d0..d97fb53 100644
--- a/portable/GCC/ARM_CA9/portmacro.h
+++ b/portable/GCC/ARM_CA9/portmacro.h
@@ -1,209 +1,208 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT short
-#define portSTACK_TYPE uint32_t
-#define portBASE_TYPE long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-typedef uint32_t TickType_t;
-#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-not need to be guarded with a critical section. */
-#define portTICK_TYPE_IS_ATOMIC 1
-
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portSTACK_GROWTH ( -1 )
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT 8
-
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-
-/* Called at the end of an ISR that can cause a context switch. */
-#define portEND_SWITCHING_ISR( xSwitchRequired )\
-{ \
-extern uint32_t ulPortYieldRequired; \
- \
- if( xSwitchRequired != pdFALSE ) \
- { \
- ulPortYieldRequired = pdTRUE; \
- } \
-}
-
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-#define portYIELD() __asm volatile ( "SWI 0" ::: "memory" );
-
-
-/*-----------------------------------------------------------
- * Critical section control
- *----------------------------------------------------------*/
-
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-extern uint32_t ulPortSetInterruptMask( void );
-extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
-extern void vPortInstallFreeRTOSVectorTable( void );
-
-/* These macros do not globally disable/enable interrupts. They do mask off
-interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
-#define portENTER_CRITICAL() vPortEnterCritical();
-#define portEXIT_CRITICAL() vPortExitCritical();
-#define portDISABLE_INTERRUPTS() ulPortSetInterruptMask()
-#define portENABLE_INTERRUPTS() vPortClearInterruptMask( 0 )
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask(x)
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. These are
-not required for this port but included in case common demo code that uses these
-macros is used. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-/* Prototype of the FreeRTOS tick handler. This must be installed as the
-handler for whichever peripheral is used to generate the RTOS tick. */
-void FreeRTOS_Tick_Handler( void );
-
-/* If configUSE_TASK_FPU_SUPPORT is set to 1 (or left undefined) then tasks are
-created without an FPU context and must call vPortTaskUsesFPU() to give
-themselves an FPU context before using any FPU instructions. If
-configUSE_TASK_FPU_SUPPORT is set to 2 then all tasks will have an FPU context
-by default. */
-#if( configUSE_TASK_FPU_SUPPORT != 2 )
- void vPortTaskUsesFPU( void );
-#else
- /* Each task has an FPU context already, so define this function away to
- nothing to prevent it being called accidentally. */
- #define vPortTaskUsesFPU()
-#endif
-#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
-
-#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
-#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
-
-/* Architecture specific optimisations. */
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-#endif
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
- /* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
- /*-----------------------------------------------------------*/
-
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __builtin_clz( uxReadyPriorities ) )
-
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-#ifdef configASSERT
- void vPortValidateInterruptPriority( void );
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
-#endif /* configASSERT */
-
-#define portNOP() __asm volatile( "NOP" )
-#define portINLINE __inline
-
-#ifdef __cplusplus
- } /* extern C */
-#endif
-
-
-/* The number of bits to shift for an interrupt priority is dependent on the
-number of bits implemented by the interrupt controller. */
-#if configUNIQUE_INTERRUPT_PRIORITIES == 16
- #define portPRIORITY_SHIFT 4
- #define portMAX_BINARY_POINT_VALUE 3
-#elif configUNIQUE_INTERRUPT_PRIORITIES == 32
- #define portPRIORITY_SHIFT 3
- #define portMAX_BINARY_POINT_VALUE 2
-#elif configUNIQUE_INTERRUPT_PRIORITIES == 64
- #define portPRIORITY_SHIFT 2
- #define portMAX_BINARY_POINT_VALUE 1
-#elif configUNIQUE_INTERRUPT_PRIORITIES == 128
- #define portPRIORITY_SHIFT 1
- #define portMAX_BINARY_POINT_VALUE 0
-#elif configUNIQUE_INTERRUPT_PRIORITIES == 256
- #define portPRIORITY_SHIFT 0
- #define portMAX_BINARY_POINT_VALUE 0
-#else
- #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
-#endif
-
-/* Interrupt controller access addresses. */
-#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 )
-#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C )
-#define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 )
-#define portICCBPR_BINARY_POINT_OFFSET ( 0x08 )
-#define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 )
-
-#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
-#define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
-#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
-#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
-#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
-#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
-#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
-
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
-
-#endif /* PORTMACRO_H */
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+typedef uint32_t TickType_t;
+#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+not need to be guarded with a critical section. */
+#define portTICK_TYPE_IS_ATOMIC 1
+
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+/* Called at the end of an ISR that can cause a context switch. */
+#define portEND_SWITCHING_ISR( xSwitchRequired )\
+{ \
+extern uint32_t ulPortYieldRequired; \
+ \
+ if( xSwitchRequired != pdFALSE ) \
+ { \
+ ulPortYieldRequired = pdTRUE; \
+ } \
+}
+
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD() __asm volatile ( "SWI 0" ::: "memory" );
+
+
+/*-----------------------------------------------------------
+ * Critical section control
+ *----------------------------------------------------------*/
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+extern uint32_t ulPortSetInterruptMask( void );
+extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
+extern void vPortInstallFreeRTOSVectorTable( void );
+
+/* These macros do not globally disable/enable interrupts. They do mask off
+interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
+#define portENTER_CRITICAL() vPortEnterCritical();
+#define portEXIT_CRITICAL() vPortExitCritical();
+#define portDISABLE_INTERRUPTS() ulPortSetInterruptMask()
+#define portENABLE_INTERRUPTS() vPortClearInterruptMask( 0 )
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask(x)
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. These are
+not required for this port but included in case common demo code that uses these
+macros is used. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+/* Prototype of the FreeRTOS tick handler. This must be installed as the
+handler for whichever peripheral is used to generate the RTOS tick. */
+void FreeRTOS_Tick_Handler( void );
+
+/* If configUSE_TASK_FPU_SUPPORT is set to 1 (or left undefined) then tasks are
+created without an FPU context and must call vPortTaskUsesFPU() to give
+themselves an FPU context before using any FPU instructions. If
+configUSE_TASK_FPU_SUPPORT is set to 2 then all tasks will have an FPU context
+by default. */
+#if( configUSE_TASK_FPU_SUPPORT != 2 )
+ void vPortTaskUsesFPU( void );
+#else
+ /* Each task has an FPU context already, so define this function away to
+ nothing to prevent it being called accidentally. */
+ #define vPortTaskUsesFPU()
+#endif
+#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+
+#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
+#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+ /* Store/clear the ready priorities in a bit map. */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+ /*-----------------------------------------------------------*/
+
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __builtin_clz( uxReadyPriorities ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+#ifdef configASSERT
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+#endif /* configASSERT */
+
+#define portNOP() __asm volatile( "NOP" )
+#define portINLINE __inline
+
+#ifdef __cplusplus
+ } /* extern C */
+#endif
+
+
+/* The number of bits to shift for an interrupt priority is dependent on the
+number of bits implemented by the interrupt controller. */
+#if configUNIQUE_INTERRUPT_PRIORITIES == 16
+ #define portPRIORITY_SHIFT 4
+ #define portMAX_BINARY_POINT_VALUE 3
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 32
+ #define portPRIORITY_SHIFT 3
+ #define portMAX_BINARY_POINT_VALUE 2
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 64
+ #define portPRIORITY_SHIFT 2
+ #define portMAX_BINARY_POINT_VALUE 1
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 128
+ #define portPRIORITY_SHIFT 1
+ #define portMAX_BINARY_POINT_VALUE 0
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 256
+ #define portPRIORITY_SHIFT 0
+ #define portMAX_BINARY_POINT_VALUE 0
+#else
+ #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
+#endif
+
+/* Interrupt controller access addresses. */
+#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C )
+#define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 )
+#define portICCBPR_BINARY_POINT_OFFSET ( 0x08 )
+#define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 )
+
+#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
+#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
+#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
+#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
+
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+
+#endif /* PORTMACRO_H */
diff --git a/portable/GCC/ARM_CM0/port.c b/portable/GCC/ARM_CM0/port.c
index 1983073..261c12d 100644
--- a/portable/GCC/ARM_CM0/port.c
+++ b/portable/GCC/ARM_CM0/port.c
@@ -1,633 +1,633 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the ARM CM0 port.
-*----------------------------------------------------------*/
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Constants required to manipulate the NVIC. */
-#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
-#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
-#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
-#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
-#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
-#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
-#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
-#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
-#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
-#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
-#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
-#define portMIN_INTERRUPT_PRIORITY ( 255UL )
-#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )
-#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )
-
-/* Constants required to set up the initial stack. */
-#define portINITIAL_XPSR ( 0x01000000 )
-
-/* The systick is a 24-bit counter. */
-#define portMAX_24_BIT_NUMBER ( 0xffffffUL )
-
-/* A fiddle factor to estimate the number of SysTick counts that would have
- * occurred while the SysTick counter is stopped during tickless idle
- * calculations. */
-#ifndef portMISSED_COUNTS_FACTOR
- #define portMISSED_COUNTS_FACTOR ( 94UL )
-#endif
-
-/* Let the user override the default SysTick clock rate. If defined by the
- * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
- * configuration register. */
-#ifndef configSYSTICK_CLOCK_HZ
- #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ )
- /* Ensure the SysTick is clocked at the same frequency as the core. */
- #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT )
-#else
- /* Select the option to clock SysTick not at the same frequency as the core. */
- #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 )
-#endif
-
-/* Let the user override the pre-loading of the initial LR with the address of
- * prvTaskExitError() in case it messes up unwinding of the stack in the
- * debugger. */
-#ifdef configTASK_RETURN_ADDRESS
- #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
-#else
- #define portTASK_RETURN_ADDRESS prvTaskExitError
-#endif
-
-/*
- * Setup the timer to generate the tick interrupts. The implementation in this
- * file is weak to allow application writers to change the timer used to
- * generate the tick interrupt.
- */
-void vPortSetupTimerInterrupt( void );
-
-/*
- * Exception handlers.
- */
-void xPortPendSVHandler( void ) __attribute__( ( naked ) );
-void xPortSysTickHandler( void );
-void vPortSVCHandler( void );
-
-/*
- * Start first task is a separate function so it can be tested in isolation.
- */
-static void vPortStartFirstTask( void ) __attribute__( ( naked ) );
-
-/*
- * Used to catch tasks that attempt to return from their implementing function.
- */
-static void prvTaskExitError( void );
-
-/*-----------------------------------------------------------*/
-
-/* Each task maintains its own interrupt status in the critical nesting
- * variable. */
-static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
-
-/*-----------------------------------------------------------*/
-
-/*
- * The number of SysTick increments that make up one tick period.
- */
-#if ( configUSE_TICKLESS_IDLE == 1 )
- static uint32_t ulTimerCountsForOneTick = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * The maximum number of tick periods that can be suppressed is limited by the
- * 24 bit resolution of the SysTick timer.
- */
-#if ( configUSE_TICKLESS_IDLE == 1 )
- static uint32_t xMaximumPossibleSuppressedTicks = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * Compensate for the CPU cycles that pass while the SysTick is stopped (low
- * power functionality only.
- */
-#if ( configUSE_TICKLESS_IDLE == 1 )
- static uint32_t ulStoppedTimerCompensation = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
-{
- /* Simulate the stack frame as it would be created by a context switch
- * interrupt. */
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
- *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
- pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack -= 8; /* R11..R4. */
-
- return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
- volatile uint32_t ulDummy = 0UL;
-
- /* A function that implements a task must not exit or attempt to return to
- * its caller as there is nothing to return to. If a task wants to exit it
- * should instead call vTaskDelete( NULL ).
- *
- * Artificially force an assert() to be triggered if configASSERT() is
- * defined, then stop here so application writers can catch the error. */
- configASSERT( uxCriticalNesting == ~0UL );
- portDISABLE_INTERRUPTS();
-
- while( ulDummy == 0 )
- {
- /* This file calls prvTaskExitError() after the scheduler has been
- * started to remove a compiler warning about the function being defined
- * but never called. ulDummy is used purely to quieten other warnings
- * about code appearing after this function is called - making ulDummy
- * volatile makes the compiler think the function could return and
- * therefore not output an 'unreachable code' warning for code that appears
- * after it. */
- }
-}
-/*-----------------------------------------------------------*/
-
-void vPortSVCHandler( void )
-{
- /* This function is no longer used, but retained for backward
- * compatibility. */
-}
-/*-----------------------------------------------------------*/
-
-void vPortStartFirstTask( void )
-{
- /* The MSP stack is not reset as, unlike on M3/4 parts, there is no vector
- * table offset register that can be used to locate the initial stack value.
- * Not all M0 parts have the application vector table at address 0. */
- __asm volatile (
- " .syntax unified \n"
- " ldr r2, pxCurrentTCBConst2 \n"/* Obtain location of pxCurrentTCB. */
- " ldr r3, [r2] \n"
- " ldr r0, [r3] \n"/* The first item in pxCurrentTCB is the task top of stack. */
- " adds r0, #32 \n"/* Discard everything up to r0. */
- " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
- " movs r0, #2 \n"/* Switch to the psp stack. */
- " msr CONTROL, r0 \n"
- " isb \n"
- " pop {r0-r5} \n"/* Pop the registers that are saved automatically. */
- " mov lr, r5 \n"/* lr is now in r5. */
- " pop {r3} \n"/* Return address is now in r3. */
- " pop {r2} \n"/* Pop and discard XPSR. */
- " cpsie i \n"/* The first task has its context and interrupts can be enabled. */
- " bx r3 \n"/* Finally, jump to the user defined task code. */
- " \n"
- " .align 4 \n"
- "pxCurrentTCBConst2: .word pxCurrentTCB "
- );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-BaseType_t xPortStartScheduler( void )
-{
- /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
- portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
- portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
-
- /* Start the timer that generates the tick ISR. Interrupts are disabled
- * here already. */
- vPortSetupTimerInterrupt();
-
- /* Initialise the critical nesting count ready for the first task. */
- uxCriticalNesting = 0;
-
- /* Start the first task. */
- vPortStartFirstTask();
-
- /* Should never get here as the tasks will now be executing! Call the task
- * exit error function to prevent compiler warnings about a static function
- * not being called in the case that the application writer overrides this
- * functionality by defining configTASK_RETURN_ADDRESS. Call
- * vTaskSwitchContext() so link time optimisation does not remove the
- * symbol. */
- vTaskSwitchContext();
- prvTaskExitError();
-
- /* Should not get here! */
- return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
- /* Not implemented in ports where there is nothing to return to.
- * Artificially force an assert. */
- configASSERT( uxCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortYield( void )
-{
- /* Set a PendSV to request a context switch. */
- portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
-
- /* Barriers are normally not required but do ensure the code is completely
- * within the specified behaviour for the architecture. */
- __asm volatile ( "dsb" ::: "memory" );
- __asm volatile ( "isb" );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
- portDISABLE_INTERRUPTS();
- uxCriticalNesting++;
- __asm volatile ( "dsb" ::: "memory" );
- __asm volatile ( "isb" );
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
- configASSERT( uxCriticalNesting );
- uxCriticalNesting--;
-
- if( uxCriticalNesting == 0 )
- {
- portENABLE_INTERRUPTS();
- }
-}
-/*-----------------------------------------------------------*/
-
-uint32_t ulSetInterruptMaskFromISR( void )
-{
- __asm volatile (
- " mrs r0, PRIMASK \n"
- " cpsid i \n"
- " bx lr "
- ::: "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask )
-{
- __asm volatile (
- " msr PRIMASK, r0 \n"
- " bx lr "
- ::: "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-void xPortPendSVHandler( void )
-{
- /* This is a naked function. */
-
- __asm volatile
- (
- " .syntax unified \n"
- " mrs r0, psp \n"
- " \n"
- " ldr r3, pxCurrentTCBConst \n"/* Get the location of the current TCB. */
- " ldr r2, [r3] \n"
- " \n"
- " subs r0, r0, #32 \n"/* Make space for the remaining low registers. */
- " str r0, [r2] \n"/* Save the new top of stack. */
- " stmia r0!, {r4-r7} \n"/* Store the low registers that are not saved automatically. */
- " mov r4, r8 \n"/* Store the high registers. */
- " mov r5, r9 \n"
- " mov r6, r10 \n"
- " mov r7, r11 \n"
- " stmia r0!, {r4-r7} \n"
- " \n"
- " push {r3, r14} \n"
- " cpsid i \n"
- " bl vTaskSwitchContext \n"
- " cpsie i \n"
- " pop {r2, r3} \n"/* lr goes in r3. r2 now holds tcb pointer. */
- " \n"
- " ldr r1, [r2] \n"
- " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. */
- " adds r0, r0, #16 \n"/* Move to the high registers. */
- " ldmia r0!, {r4-r7} \n"/* Pop the high registers. */
- " mov r8, r4 \n"
- " mov r9, r5 \n"
- " mov r10, r6 \n"
- " mov r11, r7 \n"
- " \n"
- " msr psp, r0 \n"/* Remember the new top of stack for the task. */
- " \n"
- " subs r0, r0, #32 \n"/* Go back for the low registers that are not automatically restored. */
- " ldmia r0!, {r4-r7} \n"/* Pop low registers. */
- " \n"
- " bx r3 \n"
- " \n"
- " .align 4 \n"
- "pxCurrentTCBConst: .word pxCurrentTCB "
- );
-}
-/*-----------------------------------------------------------*/
-
-void xPortSysTickHandler( void )
-{
- uint32_t ulPreviousMask;
-
- ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
- {
- /* Increment the RTOS tick. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- /* Pend a context switch. */
- portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
- }
- }
- portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the systick timer to generate the tick interrupts at the required
- * frequency.
- */
-__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
-{
- /* Calculate the constants required to configure the tick interrupt. */
- #if ( configUSE_TICKLESS_IDLE == 1 )
- {
- ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
- xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
- ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
- }
- #endif /* configUSE_TICKLESS_IDLE */
-
- /* Stop and reset the SysTick. */
- portNVIC_SYSTICK_CTRL_REG = 0UL;
- portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
- /* Configure SysTick to interrupt at the requested rate. */
- portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
-}
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TICKLESS_IDLE == 1 )
-
- __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
- {
- uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
- TickType_t xModifiableIdleTime;
-
- /* Make sure the SysTick reload value does not overflow the counter. */
- if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
- {
- xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
- }
-
- /* Enter a critical section but don't use the taskENTER_CRITICAL()
- * method as that will mask interrupts that should exit sleep mode. */
- __asm volatile ( "cpsid i" ::: "memory" );
- __asm volatile ( "dsb" );
- __asm volatile ( "isb" );
-
- /* If a context switch is pending or a task is waiting for the scheduler
- * to be unsuspended then abandon the low power entry. */
- if( eTaskConfirmSleepModeStatus() == eAbortSleep )
- {
- /* Re-enable interrupts - see comments above the cpsid instruction
- * above. */
- __asm volatile ( "cpsie i" ::: "memory" );
- }
- else
- {
- /* Stop the SysTick momentarily. The time the SysTick is stopped for
- * is accounted for as best it can be, but using the tickless mode will
- * inevitably result in some tiny drift of the time maintained by the
- * kernel with respect to calendar time. */
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
-
- /* Use the SysTick current-value register to determine the number of
- * SysTick decrements remaining until the next tick interrupt. If the
- * current-value register is zero, then there are actually
- * ulTimerCountsForOneTick decrements remaining, not zero, because the
- * SysTick requests the interrupt when decrementing from 1 to 0. */
- ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
- if( ulSysTickDecrementsLeft == 0 )
- {
- ulSysTickDecrementsLeft = ulTimerCountsForOneTick;
- }
-
- /* Calculate the reload value required to wait xExpectedIdleTime
- * tick periods. -1 is used because this code normally executes part
- * way through the first tick period. But if the SysTick IRQ is now
- * pending, then clear the IRQ, suppressing the first tick, and correct
- * the reload value to reflect that the second tick period is already
- * underway. The expected idle time is always at least two ticks. */
- ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
-
- if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )
- {
- portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;
- ulReloadValue -= ulTimerCountsForOneTick;
- }
-
- if( ulReloadValue > ulStoppedTimerCompensation )
- {
- ulReloadValue -= ulStoppedTimerCompensation;
- }
-
- /* Set the new reload value. */
- portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
-
- /* Clear the SysTick count flag and set the count value back to
- * zero. */
- portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
- /* Restart SysTick. */
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
- /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
- * set its parameter to 0 to indicate that its implementation contains
- * its own wait for interrupt or wait for event instruction, and so wfi
- * should not be executed again. However, the original expected idle
- * time variable must remain unmodified, so a copy is taken. */
- xModifiableIdleTime = xExpectedIdleTime;
- configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
-
- if( xModifiableIdleTime > 0 )
- {
- __asm volatile ( "dsb" ::: "memory" );
- __asm volatile ( "wfi" );
- __asm volatile ( "isb" );
- }
-
- configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
-
- /* Re-enable interrupts to allow the interrupt that brought the MCU
- * out of sleep mode to execute immediately. See comments above
- * the cpsid instruction above. */
- __asm volatile ( "cpsie i" ::: "memory" );
- __asm volatile ( "dsb" );
- __asm volatile ( "isb" );
-
- /* Disable interrupts again because the clock is about to be stopped
- * and interrupts that execute while the clock is stopped will increase
- * any slippage between the time maintained by the RTOS and calendar
- * time. */
- __asm volatile ( "cpsid i" ::: "memory" );
- __asm volatile ( "dsb" );
- __asm volatile ( "isb" );
-
- /* Disable the SysTick clock without reading the
- * portNVIC_SYSTICK_CTRL_REG register to ensure the
- * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
- * the time the SysTick is stopped for is accounted for as best it can
- * be, but using the tickless mode will inevitably result in some tiny
- * drift of the time maintained by the kernel with respect to calendar
- * time*/
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
-
- /* Determine whether the SysTick has already counted to zero. */
- if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
- {
- uint32_t ulCalculatedLoadValue;
-
- /* The tick interrupt ended the sleep (or is now pending), and
- * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG
- * with whatever remains of the new tick period. */
- ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
-
- /* Don't allow a tiny value, or values that have somehow
- * underflowed because the post sleep hook did something
- * that took too long or because the SysTick current-value register
- * is zero. */
- if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
- {
- ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
- }
-
- portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
-
- /* As the pending tick will be processed as soon as this
- * function exits, the tick value maintained by the tick is stepped
- * forward by one less than the time spent waiting. */
- ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
- }
- else
- {
- /* Something other than the tick interrupt ended the sleep. */
-
- /* Use the SysTick current-value register to determine the
- * number of SysTick decrements remaining until the expected idle
- * time would have ended. */
- ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
- #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )
- {
- /* If the SysTick is not using the core clock, the current-
- * value register might still be zero here. In that case, the
- * SysTick didn't load from the reload register, and there are
- * ulReloadValue decrements remaining in the expected idle
- * time, not zero. */
- if( ulSysTickDecrementsLeft == 0 )
- {
- ulSysTickDecrementsLeft = ulReloadValue;
- }
- }
- #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
-
- /* Work out how long the sleep lasted rounded to complete tick
- * periods (not the ulReload value which accounted for part
- * ticks). */
- ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;
-
- /* How many complete tick periods passed while the processor
- * was waiting? */
- ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
-
- /* The reload value is set to whatever fraction of a single tick
- * period remains. */
- portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
- }
-
- /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,
- * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If
- * the SysTick is not using the core clock, temporarily configure it to
- * use the core clock. This configuration forces the SysTick to load
- * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next
- * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready
- * to receive the standard value immediately. */
- portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
- portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
- #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )
- {
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
- }
- #else
- {
- /* The temporary usage of the core clock has served its purpose,
- * as described above. Resume usage of the other clock. */
- portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
-
- if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
- {
- /* The partial tick period already ended. Be sure the SysTick
- * counts it only once. */
- portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;
- }
-
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
- portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
- }
- #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
-
- /* Step the tick to account for any tick periods that elapsed. */
- vTaskStepTick( ulCompleteTickPeriods );
-
- /* Exit with interrupts enabled. */
- __asm volatile ( "cpsie i" ::: "memory" );
- }
- }
-
-#endif /* configUSE_TICKLESS_IDLE */
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*-----------------------------------------------------------
+* Implementation of functions defined in portable.h for the ARM CM0 port.
+*----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to manipulate the NVIC. */
+#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
+#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
+#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )
+#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR ( 0x01000000 )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER ( 0xffffffUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+ * occurred while the SysTick counter is stopped during tickless idle
+ * calculations. */
+#ifndef portMISSED_COUNTS_FACTOR
+ #define portMISSED_COUNTS_FACTOR ( 94UL )
+#endif
+
+/* Let the user override the default SysTick clock rate. If defined by the
+ * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
+ * configuration register. */
+#ifndef configSYSTICK_CLOCK_HZ
+ #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ )
+ /* Ensure the SysTick is clocked at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT )
+#else
+ /* Select the option to clock SysTick not at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 )
+#endif
+
+/* Let the user override the pre-loading of the initial LR with the address of
+ * prvTaskExitError() in case it messes up unwinding of the stack in the
+ * debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
+#else
+ #define portTASK_RETURN_ADDRESS prvTaskExitError
+#endif
+
+/*
+ * Setup the timer to generate the tick interrupts. The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortPendSVHandler( void ) __attribute__( ( naked ) );
+void xPortSysTickHandler( void );
+void vPortSVCHandler( void );
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+static void vPortStartFirstTask( void ) __attribute__( ( naked ) );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+ * variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+ static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+ static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+ static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+ TaskFunction_t pxCode,
+ void * pvParameters )
+{
+ /* Simulate the stack frame as it would be created by a context switch
+ * interrupt. */
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack -= 8; /* R11..R4. */
+
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+ volatile uint32_t ulDummy = 0UL;
+
+ /* A function that implements a task must not exit or attempt to return to
+ * its caller as there is nothing to return to. If a task wants to exit it
+ * should instead call vTaskDelete( NULL ).
+ *
+ * Artificially force an assert() to be triggered if configASSERT() is
+ * defined, then stop here so application writers can catch the error. */
+ configASSERT( uxCriticalNesting == ~0UL );
+ portDISABLE_INTERRUPTS();
+
+ while( ulDummy == 0 )
+ {
+ /* This file calls prvTaskExitError() after the scheduler has been
+ * started to remove a compiler warning about the function being defined
+ * but never called. ulDummy is used purely to quieten other warnings
+ * about code appearing after this function is called - making ulDummy
+ * volatile makes the compiler think the function could return and
+ * therefore not output an 'unreachable code' warning for code that appears
+ * after it. */
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler( void )
+{
+ /* This function is no longer used, but retained for backward
+ * compatibility. */
+}
+/*-----------------------------------------------------------*/
+
+void vPortStartFirstTask( void )
+{
+ /* The MSP stack is not reset as, unlike on M3/4 parts, there is no vector
+ * table offset register that can be used to locate the initial stack value.
+ * Not all M0 parts have the application vector table at address 0. */
+ __asm volatile (
+ " .syntax unified \n"
+ " ldr r2, pxCurrentTCBConst2 \n"/* Obtain location of pxCurrentTCB. */
+ " ldr r3, [r2] \n"
+ " ldr r0, [r3] \n"/* The first item in pxCurrentTCB is the task top of stack. */
+ " adds r0, #32 \n"/* Discard everything up to r0. */
+ " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
+ " movs r0, #2 \n"/* Switch to the psp stack. */
+ " msr CONTROL, r0 \n"
+ " isb \n"
+ " pop {r0-r5} \n"/* Pop the registers that are saved automatically. */
+ " mov lr, r5 \n"/* lr is now in r5. */
+ " pop {r3} \n"/* Return address is now in r3. */
+ " pop {r2} \n"/* Pop and discard XPSR. */
+ " cpsie i \n"/* The first task has its context and interrupts can be enabled. */
+ " bx r3 \n"/* Finally, jump to the user defined task code. */
+ " \n"
+ " .align 4 \n"
+ "pxCurrentTCBConst2: .word pxCurrentTCB "
+ );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+ /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
+ portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ * here already. */
+ vPortSetupTimerInterrupt();
+
+ /* Initialise the critical nesting count ready for the first task. */
+ uxCriticalNesting = 0;
+
+ /* Start the first task. */
+ vPortStartFirstTask();
+
+ /* Should never get here as the tasks will now be executing! Call the task
+ * exit error function to prevent compiler warnings about a static function
+ * not being called in the case that the application writer overrides this
+ * functionality by defining configTASK_RETURN_ADDRESS. Call
+ * vTaskSwitchContext() so link time optimisation does not remove the
+ * symbol. */
+ vTaskSwitchContext();
+ prvTaskExitError();
+
+ /* Should not get here! */
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+ /* Not implemented in ports where there is nothing to return to.
+ * Artificially force an assert. */
+ configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortYield( void )
+{
+ /* Set a PendSV to request a context switch. */
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+
+ /* Barriers are normally not required but do ensure the code is completely
+ * within the specified behaviour for the architecture. */
+ __asm volatile ( "dsb" ::: "memory" );
+ __asm volatile ( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+ portDISABLE_INTERRUPTS();
+ uxCriticalNesting++;
+ __asm volatile ( "dsb" ::: "memory" );
+ __asm volatile ( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+ configASSERT( uxCriticalNesting );
+ uxCriticalNesting--;
+
+ if( uxCriticalNesting == 0 )
+ {
+ portENABLE_INTERRUPTS();
+ }
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulSetInterruptMaskFromISR( void )
+{
+ __asm volatile (
+ " mrs r0, PRIMASK \n"
+ " cpsid i \n"
+ " bx lr "
+ ::: "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask )
+{
+ __asm volatile (
+ " msr PRIMASK, r0 \n"
+ " bx lr "
+ ::: "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void xPortPendSVHandler( void )
+{
+ /* This is a naked function. */
+
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " mrs r0, psp \n"
+ " \n"
+ " ldr r3, pxCurrentTCBConst \n"/* Get the location of the current TCB. */
+ " ldr r2, [r3] \n"
+ " \n"
+ " subs r0, r0, #32 \n"/* Make space for the remaining low registers. */
+ " str r0, [r2] \n"/* Save the new top of stack. */
+ " stmia r0!, {r4-r7} \n"/* Store the low registers that are not saved automatically. */
+ " mov r4, r8 \n"/* Store the high registers. */
+ " mov r5, r9 \n"
+ " mov r6, r10 \n"
+ " mov r7, r11 \n"
+ " stmia r0!, {r4-r7} \n"
+ " \n"
+ " push {r3, r14} \n"
+ " cpsid i \n"
+ " bl vTaskSwitchContext \n"
+ " cpsie i \n"
+ " pop {r2, r3} \n"/* lr goes in r3. r2 now holds tcb pointer. */
+ " \n"
+ " ldr r1, [r2] \n"
+ " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. */
+ " adds r0, r0, #16 \n"/* Move to the high registers. */
+ " ldmia r0!, {r4-r7} \n"/* Pop the high registers. */
+ " mov r8, r4 \n"
+ " mov r9, r5 \n"
+ " mov r10, r6 \n"
+ " mov r11, r7 \n"
+ " \n"
+ " msr psp, r0 \n"/* Remember the new top of stack for the task. */
+ " \n"
+ " subs r0, r0, #32 \n"/* Go back for the low registers that are not automatically restored. */
+ " ldmia r0!, {r4-r7} \n"/* Pop low registers. */
+ " \n"
+ " bx r3 \n"
+ " \n"
+ " .align 4 \n"
+ "pxCurrentTCBConst: .word pxCurrentTCB "
+ );
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+ uint32_t ulPreviousMask;
+
+ ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+ {
+ /* Increment the RTOS tick. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ /* Pend a context switch. */
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+ }
+ }
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
+{
+ /* Calculate the constants required to configure the tick interrupt. */
+ #if ( configUSE_TICKLESS_IDLE == 1 )
+ {
+ ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+ xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+ ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+ }
+ #endif /* configUSE_TICKLESS_IDLE */
+
+ /* Stop and reset the SysTick. */
+ portNVIC_SYSTICK_CTRL_REG = 0UL;
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+ /* Configure SysTick to interrupt at the requested rate. */
+ portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+
+ __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+ {
+ uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
+ TickType_t xModifiableIdleTime;
+
+ /* Make sure the SysTick reload value does not overflow the counter. */
+ if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+ {
+ xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+ }
+
+ /* Enter a critical section but don't use the taskENTER_CRITICAL()
+ * method as that will mask interrupts that should exit sleep mode. */
+ __asm volatile ( "cpsid i" ::: "memory" );
+ __asm volatile ( "dsb" );
+ __asm volatile ( "isb" );
+
+ /* If a context switch is pending or a task is waiting for the scheduler
+ * to be unsuspended then abandon the low power entry. */
+ if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+ {
+ /* Re-enable interrupts - see comments above the cpsid instruction
+ * above. */
+ __asm volatile ( "cpsie i" ::: "memory" );
+ }
+ else
+ {
+ /* Stop the SysTick momentarily. The time the SysTick is stopped for
+ * is accounted for as best it can be, but using the tickless mode will
+ * inevitably result in some tiny drift of the time maintained by the
+ * kernel with respect to calendar time. */
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
+
+ /* Use the SysTick current-value register to determine the number of
+ * SysTick decrements remaining until the next tick interrupt. If the
+ * current-value register is zero, then there are actually
+ * ulTimerCountsForOneTick decrements remaining, not zero, because the
+ * SysTick requests the interrupt when decrementing from 1 to 0. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulTimerCountsForOneTick;
+ }
+
+ /* Calculate the reload value required to wait xExpectedIdleTime
+ * tick periods. -1 is used because this code normally executes part
+ * way through the first tick period. But if the SysTick IRQ is now
+ * pending, then clear the IRQ, suppressing the first tick, and correct
+ * the reload value to reflect that the second tick period is already
+ * underway. The expected idle time is always at least two ticks. */
+ ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+ if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )
+ {
+ portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;
+ ulReloadValue -= ulTimerCountsForOneTick;
+ }
+
+ if( ulReloadValue > ulStoppedTimerCompensation )
+ {
+ ulReloadValue -= ulStoppedTimerCompensation;
+ }
+
+ /* Set the new reload value. */
+ portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+ /* Clear the SysTick count flag and set the count value back to
+ * zero. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+ /* Restart SysTick. */
+ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+ /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
+ * set its parameter to 0 to indicate that its implementation contains
+ * its own wait for interrupt or wait for event instruction, and so wfi
+ * should not be executed again. However, the original expected idle
+ * time variable must remain unmodified, so a copy is taken. */
+ xModifiableIdleTime = xExpectedIdleTime;
+ configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+
+ if( xModifiableIdleTime > 0 )
+ {
+ __asm volatile ( "dsb" ::: "memory" );
+ __asm volatile ( "wfi" );
+ __asm volatile ( "isb" );
+ }
+
+ configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+ /* Re-enable interrupts to allow the interrupt that brought the MCU
+ * out of sleep mode to execute immediately. See comments above
+ * the cpsid instruction above. */
+ __asm volatile ( "cpsie i" ::: "memory" );
+ __asm volatile ( "dsb" );
+ __asm volatile ( "isb" );
+
+ /* Disable interrupts again because the clock is about to be stopped
+ * and interrupts that execute while the clock is stopped will increase
+ * any slippage between the time maintained by the RTOS and calendar
+ * time. */
+ __asm volatile ( "cpsid i" ::: "memory" );
+ __asm volatile ( "dsb" );
+ __asm volatile ( "isb" );
+
+ /* Disable the SysTick clock without reading the
+ * portNVIC_SYSTICK_CTRL_REG register to ensure the
+ * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
+ * the time the SysTick is stopped for is accounted for as best it can
+ * be, but using the tickless mode will inevitably result in some tiny
+ * drift of the time maintained by the kernel with respect to calendar
+ * time*/
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
+
+ /* Determine whether the SysTick has already counted to zero. */
+ if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+ {
+ uint32_t ulCalculatedLoadValue;
+
+ /* The tick interrupt ended the sleep (or is now pending), and
+ * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG
+ * with whatever remains of the new tick period. */
+ ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+ /* Don't allow a tiny value, or values that have somehow
+ * underflowed because the post sleep hook did something
+ * that took too long or because the SysTick current-value register
+ * is zero. */
+ if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+ {
+ ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+ }
+
+ portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+ /* As the pending tick will be processed as soon as this
+ * function exits, the tick value maintained by the tick is stepped
+ * forward by one less than the time spent waiting. */
+ ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+ }
+ else
+ {
+ /* Something other than the tick interrupt ended the sleep. */
+
+ /* Use the SysTick current-value register to determine the
+ * number of SysTick decrements remaining until the expected idle
+ * time would have ended. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )
+ {
+ /* If the SysTick is not using the core clock, the current-
+ * value register might still be zero here. In that case, the
+ * SysTick didn't load from the reload register, and there are
+ * ulReloadValue decrements remaining in the expected idle
+ * time, not zero. */
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulReloadValue;
+ }
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Work out how long the sleep lasted rounded to complete tick
+ * periods (not the ulReload value which accounted for part
+ * ticks). */
+ ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;
+
+ /* How many complete tick periods passed while the processor
+ * was waiting? */
+ ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+ /* The reload value is set to whatever fraction of a single tick
+ * period remains. */
+ portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+ }
+
+ /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,
+ * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If
+ * the SysTick is not using the core clock, temporarily configure it to
+ * use the core clock. This configuration forces the SysTick to load
+ * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next
+ * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready
+ * to receive the standard value immediately. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )
+ {
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ }
+ #else
+ {
+ /* The temporary usage of the core clock has served its purpose,
+ * as described above. Resume usage of the other clock. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
+
+ if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+ {
+ /* The partial tick period already ended. Be sure the SysTick
+ * counts it only once. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;
+ }
+
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Step the tick to account for any tick periods that elapsed. */
+ vTaskStepTick( ulCompleteTickPeriods );
+
+ /* Exit with interrupts enabled. */
+ __asm volatile ( "cpsie i" ::: "memory" );
+ }
+ }
+
+#endif /* configUSE_TICKLESS_IDLE */
diff --git a/portable/GCC/ARM_CM0/portmacro.h b/portable/GCC/ARM_CM0/portmacro.h
index dc05280..a89c8ba 100644
--- a/portable/GCC/ARM_CM0/portmacro.h
+++ b/portable/GCC/ARM_CM0/portmacro.h
@@ -1,125 +1,125 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-
-#ifndef PORTMACRO_H
- #define PORTMACRO_H
-
- #ifdef __cplusplus
- extern "C" {
- #endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
-
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
-
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portDONT_DISCARD __attribute__( ( used ) )
-/*-----------------------------------------------------------*/
-
-
-/* Scheduler utilities. */
- extern void vPortYield( void );
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portYIELD() vPortYield()
- #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-
-/* Critical section management. */
- extern void vPortEnterCritical( void );
- extern void vPortExitCritical( void );
- extern uint32_t ulSetInterruptMaskFromISR( void ) __attribute__( ( naked ) );
- extern void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__( ( naked ) );
-
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMaskFromISR( x )
- #define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
- #define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
-
-/*-----------------------------------------------------------*/
-
-/* Tickless idle/low power functionality. */
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
-
- #define portNOP()
-
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
-
- #ifdef __cplusplus
- }
- #endif
-
-#endif /* PORTMACRO_H */
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+#ifndef PORTMACRO_H
+ #define PORTMACRO_H
+
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+ #define portCHAR char
+ #define portFLOAT float
+ #define portDOUBLE double
+ #define portLONG long
+ #define portSHORT short
+ #define portSTACK_TYPE uint32_t
+ #define portBASE_TYPE long
+
+ typedef portSTACK_TYPE StackType_t;
+ typedef long BaseType_t;
+ typedef unsigned long UBaseType_t;
+
+ #if ( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+ #else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+ #endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+ #define portSTACK_GROWTH ( -1 )
+ #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+ #define portBYTE_ALIGNMENT 8
+ #define portDONT_DISCARD __attribute__( ( used ) )
+/*-----------------------------------------------------------*/
+
+
+/* Scheduler utilities. */
+ extern void vPortYield( void );
+ #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+ #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+ #define portYIELD() vPortYield()
+ #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
+ #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+
+/* Critical section management. */
+ extern void vPortEnterCritical( void );
+ extern void vPortExitCritical( void );
+ extern uint32_t ulSetInterruptMaskFromISR( void ) __attribute__( ( naked ) );
+ extern void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__( ( naked ) );
+
+ #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()
+ #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMaskFromISR( x )
+ #define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
+ #define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )
+ #define portENTER_CRITICAL() vPortEnterCritical()
+ #define portEXIT_CRITICAL() vPortExitCritical()
+
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+ #ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+ #endif
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+ #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+ #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+
+ #define portNOP()
+
+ #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+
+ #ifdef __cplusplus
+ }
+ #endif
+
+#endif /* PORTMACRO_H */
diff --git a/portable/GCC/ARM_CM23/non_secure/portasm.c b/portable/GCC/ARM_CM23/non_secure/portasm.c
index a55b48b..5435439 100644
--- a/portable/GCC/ARM_CM23/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM23/non_secure/portasm.c
@@ -1,478 +1,478 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/* Standard includes. */
-#include <stdint.h>
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
- * is defined correctly and privileged functions are placed in correct sections. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Portasm includes. */
-#include "portasm.h"
-
-/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
- * header files. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#if ( configENABLE_FPU == 1 )
- #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
-#endif
-
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " ldr r2, pxCurrentTCBConst2 \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r3, [r2] \n"/* Read pxCurrentTCB. */
- " ldr r0, [r3] \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
- " \n"
- #if ( configENABLE_MPU == 1 )
- " dmb \n"/* Complete outstanding transfers before disabling MPU. */
- " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
- " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
- " movs r5, #1 \n"/* r5 = 1. */
- " bics r4, r5 \n"/* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
- " str r4, [r2] \n"/* Disable MPU. */
- " \n"
- " adds r3, #4 \n"/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
- " ldr r4, [r3] \n"/* r4 = *r3 i.e. r4 = MAIR0. */
- " ldr r2, xMAIR0Const2 \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
- " str r4, [r2] \n"/* Program MAIR0. */
- " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
- " adds r3, #4 \n"/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
- " movs r5, #4 \n"/* r5 = 4. */
- " str r5, [r2] \n"/* Program RNR = 4. */
- " ldmia r3!, {r6,r7} \n"/* Read first set of RBAR/RLAR from TCB. */
- " ldr r4, xRBARConst2 \n"/* r4 = 0xe000ed9c [Location of RBAR]. */
- " stmia r4!, {r6,r7} \n"/* Write first set of RBAR/RLAR registers. */
- " movs r5, #5 \n"/* r5 = 5. */
- " str r5, [r2] \n"/* Program RNR = 5. */
- " ldmia r3!, {r6,r7} \n"/* Read second set of RBAR/RLAR from TCB. */
- " ldr r4, xRBARConst2 \n"/* r4 = 0xe000ed9c [Location of RBAR]. */
- " stmia r4!, {r6,r7} \n"/* Write second set of RBAR/RLAR registers. */
- " movs r5, #6 \n"/* r5 = 6. */
- " str r5, [r2] \n"/* Program RNR = 6. */
- " ldmia r3!, {r6,r7} \n"/* Read third set of RBAR/RLAR from TCB. */
- " ldr r4, xRBARConst2 \n"/* r4 = 0xe000ed9c [Location of RBAR]. */
- " stmia r4!, {r6,r7} \n"/* Write third set of RBAR/RLAR registers. */
- " movs r5, #7 \n"/* r5 = 7. */
- " str r5, [r2] \n"/* Program RNR = 7. */
- " ldmia r3!, {r6,r7} \n"/* Read fourth set of RBAR/RLAR from TCB. */
- " ldr r4, xRBARConst2 \n"/* r4 = 0xe000ed9c [Location of RBAR]. */
- " stmia r4!, {r6,r7} \n"/* Write fourth set of RBAR/RLAR registers. */
- " \n"
- " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
- " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
- " movs r5, #1 \n"/* r5 = 1. */
- " orrs r4, r5 \n"/* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
- " str r4, [r2] \n"/* Enable MPU. */
- " dsb \n"/* Force memory writes before continuing. */
- #endif /* configENABLE_MPU */
- " \n"
- #if ( configENABLE_MPU == 1 )
- " ldm r0!, {r1-r4} \n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
- " ldr r5, xSecureContextConst2 \n"
- " str r1, [r5] \n"/* Set xSecureContext to this task's value for the same. */
- " msr psplim, r2 \n"/* Set this task's PSPLIM value. */
- " msr control, r3 \n"/* Set this task's CONTROL value. */
- " adds r0, #32 \n"/* Discard everything up to r0. */
- " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
- " isb \n"
- " bx r4 \n"/* Finally, branch to EXC_RETURN. */
- #else /* configENABLE_MPU */
- " ldm r0!, {r1-r3} \n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
- " ldr r4, xSecureContextConst2 \n"
- " str r1, [r4] \n"/* Set xSecureContext to this task's value for the same. */
- " msr psplim, r2 \n"/* Set this task's PSPLIM value. */
- " movs r1, #2 \n"/* r1 = 2. */
- " msr CONTROL, r1 \n"/* Switch to use PSP in the thread mode. */
- " adds r0, #32 \n"/* Discard everything up to r0. */
- " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
- " isb \n"
- " bx r3 \n"/* Finally, branch to EXC_RETURN. */
- #endif /* configENABLE_MPU */
- " \n"
- " .align 4 \n"
- "pxCurrentTCBConst2: .word pxCurrentTCB \n"
- "xSecureContextConst2: .word xSecureContext \n"
- #if ( configENABLE_MPU == 1 )
- "xMPUCTRLConst2: .word 0xe000ed94 \n"
- "xMAIR0Const2: .word 0xe000edc0 \n"
- "xRNRConst2: .word 0xe000ed98 \n"
- "xRBARConst2: .word 0xe000ed9c \n"
- #endif /* configENABLE_MPU */
- );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " mrs r0, control \n"/* r0 = CONTROL. */
- " movs r1, #1 \n"/* r1 = 1. */
- " tst r0, r1 \n"/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
- " beq running_privileged \n"/* If the result of previous AND operation was 0, branch. */
- " movs r0, #0 \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
- " bx lr \n"/* Return. */
- " running_privileged: \n"
- " movs r0, #1 \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
- " bx lr \n"/* Return. */
- " \n"
- " .align 4 \n"
- ::: "r0", "r1", "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " mrs r0, control \n"/* Read the CONTROL register. */
- " movs r1, #1 \n"/* r1 = 1. */
- " bics r0, r1 \n"/* Clear the bit 0. */
- " msr control, r0 \n"/* Write back the new CONTROL value. */
- " bx lr \n"/* Return to the caller. */
- ::: "r0", "r1", "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-void vResetPrivilege( void ) /* __attribute__ (( naked )) */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " mrs r0, control \n"/* r0 = CONTROL. */
- " movs r1, #1 \n"/* r1 = 1. */
- " orrs r0, r1 \n"/* r0 = r0 | r1. */
- " msr control, r0 \n"/* CONTROL = r0. */
- " bx lr \n"/* Return to the caller. */
- ::: "r0", "r1", "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " ldr r0, xVTORConst \n"/* Use the NVIC offset register to locate the stack. */
- " ldr r0, [r0] \n"/* Read the VTOR register which gives the address of vector table. */
- " ldr r0, [r0] \n"/* The first entry in vector table is stack pointer. */
- " msr msp, r0 \n"/* Set the MSP back to the start of the stack. */
- " cpsie i \n"/* Globally enable interrupts. */
- " dsb \n"
- " isb \n"
- " svc %0 \n"/* System call to start the first task. */
- " nop \n"
- " \n"
- " .align 4 \n"
- "xVTORConst: .word 0xe000ed08 \n"
- ::"i" ( portSVC_START_SCHEDULER ) : "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " mrs r0, PRIMASK \n"
- " cpsid i \n"
- " bx lr \n"
- ::: "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " msr PRIMASK, r0 \n"
- " bx lr \n"
- ::: "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " .extern SecureContext_SaveContext \n"
- " .extern SecureContext_LoadContext \n"
- " \n"
- " ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
- " ldr r0, [r3] \n"/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
- " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r3] \n"/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later.*/
- " mrs r2, psp \n"/* Read PSP in r2. */
- " \n"
- " cbz r0, save_ns_context \n"/* No secure context to save. */
- " push {r0-r2, r14} \n"
- " bl SecureContext_SaveContext \n"/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
- " pop {r0-r3} \n"/* LR is now in r3. */
- " mov lr, r3 \n"/* LR = r3. */
- " lsls r1, r3, #25 \n"/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
- " bpl save_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
- " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r3] \n"/* Read pxCurrentTCB. */
- #if ( configENABLE_MPU == 1 )
- " subs r2, r2, #16 \n"/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
- " str r2, [r1] \n"/* Save the new top of stack in TCB. */
- " mrs r1, psplim \n"/* r1 = PSPLIM. */
- " mrs r3, control \n"/* r3 = CONTROL. */
- " mov r4, lr \n"/* r4 = LR/EXC_RETURN. */
- " stmia r2!, {r0, r1, r3, r4} \n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
- #else /* configENABLE_MPU */
- " subs r2, r2, #12 \n"/* Make space for xSecureContext, PSPLIM and LR on the stack. */
- " str r2, [r1] \n"/* Save the new top of stack in TCB. */
- " mrs r1, psplim \n"/* r1 = PSPLIM. */
- " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */
- " stmia r2!, {r0, r1, r3} \n"/* Store xSecureContext, PSPLIM and LR on the stack. */
- #endif /* configENABLE_MPU */
- " b select_next_task \n"
- " \n"
- " save_ns_context: \n"
- " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r3] \n"/* Read pxCurrentTCB. */
- #if ( configENABLE_MPU == 1 )
- " subs r2, r2, #48 \n"/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
- " str r2, [r1] \n"/* Save the new top of stack in TCB. */
- " adds r2, r2, #16 \n"/* r2 = r2 + 16. */
- " stmia r2!, {r4-r7} \n"/* Store the low registers that are not saved automatically. */
- " mov r4, r8 \n"/* r4 = r8. */
- " mov r5, r9 \n"/* r5 = r9. */
- " mov r6, r10 \n"/* r6 = r10. */
- " mov r7, r11 \n"/* r7 = r11. */
- " stmia r2!, {r4-r7} \n"/* Store the high registers that are not saved automatically. */
- " mrs r1, psplim \n"/* r1 = PSPLIM. */
- " mrs r3, control \n"/* r3 = CONTROL. */
- " mov r4, lr \n"/* r4 = LR/EXC_RETURN. */
- " subs r2, r2, #48 \n"/* r2 = r2 - 48. */
- " stmia r2!, {r0, r1, r3, r4} \n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
- #else /* configENABLE_MPU */
- " subs r2, r2, #44 \n"/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
- " str r2, [r1] \n"/* Save the new top of stack in TCB. */
- " mrs r1, psplim \n"/* r1 = PSPLIM. */
- " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */
- " stmia r2!, {r0, r1, r3-r7} \n"/* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
- " mov r4, r8 \n"/* r4 = r8. */
- " mov r5, r9 \n"/* r5 = r9. */
- " mov r6, r10 \n"/* r6 = r10. */
- " mov r7, r11 \n"/* r7 = r11. */
- " stmia r2!, {r4-r7} \n"/* Store the high registers that are not saved automatically. */
- #endif /* configENABLE_MPU */
- " \n"
- " select_next_task: \n"
- " cpsid i \n"
- " bl vTaskSwitchContext \n"
- " cpsie i \n"
- " \n"
- " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r3] \n"/* Read pxCurrentTCB. */
- " ldr r2, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
- " \n"
- #if ( configENABLE_MPU == 1 )
- " dmb \n"/* Complete outstanding transfers before disabling MPU. */
- " ldr r3, xMPUCTRLConst \n"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */
- " ldr r4, [r3] \n"/* Read the value of MPU_CTRL. */
- " movs r5, #1 \n"/* r5 = 1. */
- " bics r4, r5 \n"/* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
- " str r4, [r3] \n"/* Disable MPU. */
- " \n"
- " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
- " ldr r4, [r1] \n"/* r4 = *r1 i.e. r4 = MAIR0. */
- " ldr r3, xMAIR0Const \n"/* r3 = 0xe000edc0 [Location of MAIR0]. */
- " str r4, [r3] \n"/* Program MAIR0. */
- " ldr r4, xRNRConst \n"/* r4 = 0xe000ed98 [Location of RNR]. */
- " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
- " movs r5, #4 \n"/* r5 = 4. */
- " str r5, [r4] \n"/* Program RNR = 4. */
- " ldmia r1!, {r6,r7} \n"/* Read first set of RBAR/RLAR from TCB. */
- " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
- " stmia r3!, {r6,r7} \n"/* Write first set of RBAR/RLAR registers. */
- " movs r5, #5 \n"/* r5 = 5. */
- " str r5, [r4] \n"/* Program RNR = 5. */
- " ldmia r1!, {r6,r7} \n"/* Read second set of RBAR/RLAR from TCB. */
- " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
- " stmia r3!, {r6,r7} \n"/* Write second set of RBAR/RLAR registers. */
- " movs r5, #6 \n"/* r5 = 6. */
- " str r5, [r4] \n"/* Program RNR = 6. */
- " ldmia r1!, {r6,r7} \n"/* Read third set of RBAR/RLAR from TCB. */
- " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
- " stmia r3!, {r6,r7} \n"/* Write third set of RBAR/RLAR registers. */
- " movs r5, #7 \n"/* r5 = 7. */
- " str r5, [r4] \n"/* Program RNR = 7. */
- " ldmia r1!, {r6,r7} \n"/* Read fourth set of RBAR/RLAR from TCB. */
- " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
- " stmia r3!, {r6,r7} \n"/* Write fourth set of RBAR/RLAR registers. */
- " \n"
- " ldr r3, xMPUCTRLConst \n"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */
- " ldr r4, [r3] \n"/* Read the value of MPU_CTRL. */
- " movs r5, #1 \n"/* r5 = 1. */
- " orrs r4, r5 \n"/* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
- " str r4, [r3] \n"/* Enable MPU. */
- " dsb \n"/* Force memory writes before continuing. */
- #endif /* configENABLE_MPU */
- " \n"
- #if ( configENABLE_MPU == 1 )
- " ldmia r2!, {r0, r1, r3, r4} \n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */
- " msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */
- " msr control, r3 \n"/* Restore the CONTROL register value for the task. */
- " mov lr, r4 \n"/* LR = r4. */
- " ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
- " str r0, [r3] \n"/* Restore the task's xSecureContext. */
- " cbz r0, restore_ns_context \n"/* If there is no secure context for the task, restore the non-secure context. */
- " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r3] \n"/* Read pxCurrentTCB. */
- " push {r2, r4} \n"
- " bl SecureContext_LoadContext \n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
- " pop {r2, r4} \n"
- " mov lr, r4 \n"/* LR = r4. */
- " lsls r1, r4, #25 \n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
- " bpl restore_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
- " msr psp, r2 \n"/* Remember the new top of stack for the task. */
- " bx lr \n"
- #else /* configENABLE_MPU */
- " ldmia r2!, {r0, r1, r4} \n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
- " msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */
- " mov lr, r4 \n"/* LR = r4. */
- " ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
- " str r0, [r3] \n"/* Restore the task's xSecureContext. */
- " cbz r0, restore_ns_context \n"/* If there is no secure context for the task, restore the non-secure context. */
- " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r3] \n"/* Read pxCurrentTCB. */
- " push {r2, r4} \n"
- " bl SecureContext_LoadContext \n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
- " pop {r2, r4} \n"
- " mov lr, r4 \n"/* LR = r4. */
- " lsls r1, r4, #25 \n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
- " bpl restore_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
- " msr psp, r2 \n"/* Remember the new top of stack for the task. */
- " bx lr \n"
- #endif /* configENABLE_MPU */
- " \n"
- " restore_ns_context: \n"
- " adds r2, r2, #16 \n"/* Move to the high registers. */
- " ldmia r2!, {r4-r7} \n"/* Restore the high registers that are not automatically restored. */
- " mov r8, r4 \n"/* r8 = r4. */
- " mov r9, r5 \n"/* r9 = r5. */
- " mov r10, r6 \n"/* r10 = r6. */
- " mov r11, r7 \n"/* r11 = r7. */
- " msr psp, r2 \n"/* Remember the new top of stack for the task. */
- " subs r2, r2, #32 \n"/* Go back to the low registers. */
- " ldmia r2!, {r4-r7} \n"/* Restore the low registers that are not automatically restored. */
- " bx lr \n"
- " \n"
- " .align 4 \n"
- "pxCurrentTCBConst: .word pxCurrentTCB \n"
- "xSecureContextConst: .word xSecureContext \n"
- #if ( configENABLE_MPU == 1 )
- "xMPUCTRLConst: .word 0xe000ed94 \n"
- "xMAIR0Const: .word 0xe000edc0 \n"
- "xRNRConst: .word 0xe000ed98 \n"
- "xRBARConst: .word 0xe000ed9c \n"
- #endif /* configENABLE_MPU */
- );
-}
-/*-----------------------------------------------------------*/
-
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " movs r0, #4 \n"
- " mov r1, lr \n"
- " tst r0, r1 \n"
- " beq stacking_used_msp \n"
- " mrs r0, psp \n"
- " ldr r2, svchandler_address_const \n"
- " bx r2 \n"
- " stacking_used_msp: \n"
- " mrs r0, msp \n"
- " ldr r2, svchandler_address_const \n"
- " bx r2 \n"
- " \n"
- " .align 4 \n"
- "svchandler_address_const: .word vPortSVCHandler_C \n"
- );
-}
-/*-----------------------------------------------------------*/
-
-void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " svc %0 \n"/* Secure context is allocated in the supervisor call. */
- " bx lr \n"/* Return. */
- ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " ldr r2, [r0] \n"/* The first item in the TCB is the top of the stack. */
- " ldr r1, [r2] \n"/* The first item on the stack is the task's xSecureContext. */
- " cmp r1, #0 \n"/* Raise svc if task's xSecureContext is not NULL. */
- " bne free_secure_context \n"/* Branch if r1 != 0. */
- " bx lr \n"/* There is no secure context (xSecureContext is NULL). */
- " free_secure_context: \n"
- " svc %0 \n"/* Secure context is freed in the supervisor call. */
- " bx lr \n"/* Return. */
- ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
- );
-}
-/*-----------------------------------------------------------*/
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
+ * is defined correctly and privileged functions are placed in correct sections. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Portasm includes. */
+#include "portasm.h"
+
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
+ * header files. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#if ( configENABLE_FPU == 1 )
+ #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
+#endif
+
+void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " ldr r2, pxCurrentTCBConst2 \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r3, [r2] \n"/* Read pxCurrentTCB. */
+ " ldr r0, [r3] \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+ " \n"
+ #if ( configENABLE_MPU == 1 )
+ " dmb \n"/* Complete outstanding transfers before disabling MPU. */
+ " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
+ " movs r5, #1 \n"/* r5 = 1. */
+ " bics r4, r5 \n"/* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
+ " str r4, [r2] \n"/* Disable MPU. */
+ " \n"
+ " adds r3, #4 \n"/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+ " ldr r4, [r3] \n"/* r4 = *r3 i.e. r4 = MAIR0. */
+ " ldr r2, xMAIR0Const2 \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
+ " str r4, [r2] \n"/* Program MAIR0. */
+ " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
+ " adds r3, #4 \n"/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+ " movs r5, #4 \n"/* r5 = 4. */
+ " str r5, [r2] \n"/* Program RNR = 4. */
+ " ldmia r3!, {r6,r7} \n"/* Read first set of RBAR/RLAR from TCB. */
+ " ldr r4, xRBARConst2 \n"/* r4 = 0xe000ed9c [Location of RBAR]. */
+ " stmia r4!, {r6,r7} \n"/* Write first set of RBAR/RLAR registers. */
+ " movs r5, #5 \n"/* r5 = 5. */
+ " str r5, [r2] \n"/* Program RNR = 5. */
+ " ldmia r3!, {r6,r7} \n"/* Read second set of RBAR/RLAR from TCB. */
+ " ldr r4, xRBARConst2 \n"/* r4 = 0xe000ed9c [Location of RBAR]. */
+ " stmia r4!, {r6,r7} \n"/* Write second set of RBAR/RLAR registers. */
+ " movs r5, #6 \n"/* r5 = 6. */
+ " str r5, [r2] \n"/* Program RNR = 6. */
+ " ldmia r3!, {r6,r7} \n"/* Read third set of RBAR/RLAR from TCB. */
+ " ldr r4, xRBARConst2 \n"/* r4 = 0xe000ed9c [Location of RBAR]. */
+ " stmia r4!, {r6,r7} \n"/* Write third set of RBAR/RLAR registers. */
+ " movs r5, #7 \n"/* r5 = 7. */
+ " str r5, [r2] \n"/* Program RNR = 7. */
+ " ldmia r3!, {r6,r7} \n"/* Read fourth set of RBAR/RLAR from TCB. */
+ " ldr r4, xRBARConst2 \n"/* r4 = 0xe000ed9c [Location of RBAR]. */
+ " stmia r4!, {r6,r7} \n"/* Write fourth set of RBAR/RLAR registers. */
+ " \n"
+ " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
+ " movs r5, #1 \n"/* r5 = 1. */
+ " orrs r4, r5 \n"/* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
+ " str r4, [r2] \n"/* Enable MPU. */
+ " dsb \n"/* Force memory writes before continuing. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ #if ( configENABLE_MPU == 1 )
+ " ldm r0!, {r1-r4} \n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
+ " ldr r5, xSecureContextConst2 \n"
+ " str r1, [r5] \n"/* Set xSecureContext to this task's value for the same. */
+ " msr psplim, r2 \n"/* Set this task's PSPLIM value. */
+ " msr control, r3 \n"/* Set this task's CONTROL value. */
+ " adds r0, #32 \n"/* Discard everything up to r0. */
+ " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
+ " isb \n"
+ " bx r4 \n"/* Finally, branch to EXC_RETURN. */
+ #else /* configENABLE_MPU */
+ " ldm r0!, {r1-r3} \n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
+ " ldr r4, xSecureContextConst2 \n"
+ " str r1, [r4] \n"/* Set xSecureContext to this task's value for the same. */
+ " msr psplim, r2 \n"/* Set this task's PSPLIM value. */
+ " movs r1, #2 \n"/* r1 = 2. */
+ " msr CONTROL, r1 \n"/* Switch to use PSP in the thread mode. */
+ " adds r0, #32 \n"/* Discard everything up to r0. */
+ " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
+ " isb \n"
+ " bx r3 \n"/* Finally, branch to EXC_RETURN. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ " .align 4 \n"
+ "pxCurrentTCBConst2: .word pxCurrentTCB \n"
+ "xSecureContextConst2: .word xSecureContext \n"
+ #if ( configENABLE_MPU == 1 )
+ "xMPUCTRLConst2: .word 0xe000ed94 \n"
+ "xMAIR0Const2: .word 0xe000edc0 \n"
+ "xRNRConst2: .word 0xe000ed98 \n"
+ "xRBARConst2: .word 0xe000ed9c \n"
+ #endif /* configENABLE_MPU */
+ );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, control \n"/* r0 = CONTROL. */
+ " movs r1, #1 \n"/* r1 = 1. */
+ " tst r0, r1 \n"/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
+ " beq running_privileged \n"/* If the result of previous AND operation was 0, branch. */
+ " movs r0, #0 \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+ " bx lr \n"/* Return. */
+ " running_privileged: \n"
+ " movs r0, #1 \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+ " bx lr \n"/* Return. */
+ " \n"
+ " .align 4 \n"
+ ::: "r0", "r1", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, control \n"/* Read the CONTROL register. */
+ " movs r1, #1 \n"/* r1 = 1. */
+ " bics r0, r1 \n"/* Clear the bit 0. */
+ " msr control, r0 \n"/* Write back the new CONTROL value. */
+ " bx lr \n"/* Return to the caller. */
+ ::: "r0", "r1", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, control \n"/* r0 = CONTROL. */
+ " movs r1, #1 \n"/* r1 = 1. */
+ " orrs r0, r1 \n"/* r0 = r0 | r1. */
+ " msr control, r0 \n"/* CONTROL = r0. */
+ " bx lr \n"/* Return to the caller. */
+ ::: "r0", "r1", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " ldr r0, xVTORConst \n"/* Use the NVIC offset register to locate the stack. */
+ " ldr r0, [r0] \n"/* Read the VTOR register which gives the address of vector table. */
+ " ldr r0, [r0] \n"/* The first entry in vector table is stack pointer. */
+ " msr msp, r0 \n"/* Set the MSP back to the start of the stack. */
+ " cpsie i \n"/* Globally enable interrupts. */
+ " dsb \n"
+ " isb \n"
+ " svc %0 \n"/* System call to start the first task. */
+ " nop \n"
+ " \n"
+ " .align 4 \n"
+ "xVTORConst: .word 0xe000ed08 \n"
+ ::"i" ( portSVC_START_SCHEDULER ) : "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, PRIMASK \n"
+ " cpsid i \n"
+ " bx lr \n"
+ ::: "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " msr PRIMASK, r0 \n"
+ " bx lr \n"
+ ::: "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern SecureContext_SaveContext \n"
+ " .extern SecureContext_LoadContext \n"
+ " \n"
+ " ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ " ldr r0, [r3] \n"/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+ " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r3] \n"/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later.*/
+ " mrs r2, psp \n"/* Read PSP in r2. */
+ " \n"
+ " cbz r0, save_ns_context \n"/* No secure context to save. */
+ " push {r0-r2, r14} \n"
+ " bl SecureContext_SaveContext \n"/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+ " pop {r0-r3} \n"/* LR is now in r3. */
+ " mov lr, r3 \n"/* LR = r3. */
+ " lsls r1, r3, #25 \n"/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+ " bpl save_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+ " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r3] \n"/* Read pxCurrentTCB. */
+ #if ( configENABLE_MPU == 1 )
+ " subs r2, r2, #16 \n"/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+ " str r2, [r1] \n"/* Save the new top of stack in TCB. */
+ " mrs r1, psplim \n"/* r1 = PSPLIM. */
+ " mrs r3, control \n"/* r3 = CONTROL. */
+ " mov r4, lr \n"/* r4 = LR/EXC_RETURN. */
+ " stmia r2!, {r0, r1, r3, r4} \n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+ #else /* configENABLE_MPU */
+ " subs r2, r2, #12 \n"/* Make space for xSecureContext, PSPLIM and LR on the stack. */
+ " str r2, [r1] \n"/* Save the new top of stack in TCB. */
+ " mrs r1, psplim \n"/* r1 = PSPLIM. */
+ " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */
+ " stmia r2!, {r0, r1, r3} \n"/* Store xSecureContext, PSPLIM and LR on the stack. */
+ #endif /* configENABLE_MPU */
+ " b select_next_task \n"
+ " \n"
+ " save_ns_context: \n"
+ " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r3] \n"/* Read pxCurrentTCB. */
+ #if ( configENABLE_MPU == 1 )
+ " subs r2, r2, #48 \n"/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+ " str r2, [r1] \n"/* Save the new top of stack in TCB. */
+ " adds r2, r2, #16 \n"/* r2 = r2 + 16. */
+ " stmia r2!, {r4-r7} \n"/* Store the low registers that are not saved automatically. */
+ " mov r4, r8 \n"/* r4 = r8. */
+ " mov r5, r9 \n"/* r5 = r9. */
+ " mov r6, r10 \n"/* r6 = r10. */
+ " mov r7, r11 \n"/* r7 = r11. */
+ " stmia r2!, {r4-r7} \n"/* Store the high registers that are not saved automatically. */
+ " mrs r1, psplim \n"/* r1 = PSPLIM. */
+ " mrs r3, control \n"/* r3 = CONTROL. */
+ " mov r4, lr \n"/* r4 = LR/EXC_RETURN. */
+ " subs r2, r2, #48 \n"/* r2 = r2 - 48. */
+ " stmia r2!, {r0, r1, r3, r4} \n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+ #else /* configENABLE_MPU */
+ " subs r2, r2, #44 \n"/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+ " str r2, [r1] \n"/* Save the new top of stack in TCB. */
+ " mrs r1, psplim \n"/* r1 = PSPLIM. */
+ " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */
+ " stmia r2!, {r0, r1, r3-r7} \n"/* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
+ " mov r4, r8 \n"/* r4 = r8. */
+ " mov r5, r9 \n"/* r5 = r9. */
+ " mov r6, r10 \n"/* r6 = r10. */
+ " mov r7, r11 \n"/* r7 = r11. */
+ " stmia r2!, {r4-r7} \n"/* Store the high registers that are not saved automatically. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ " select_next_task: \n"
+ " cpsid i \n"
+ " bl vTaskSwitchContext \n"
+ " cpsie i \n"
+ " \n"
+ " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r3] \n"/* Read pxCurrentTCB. */
+ " ldr r2, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
+ " \n"
+ #if ( configENABLE_MPU == 1 )
+ " dmb \n"/* Complete outstanding transfers before disabling MPU. */
+ " ldr r3, xMPUCTRLConst \n"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r4, [r3] \n"/* Read the value of MPU_CTRL. */
+ " movs r5, #1 \n"/* r5 = 1. */
+ " bics r4, r5 \n"/* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
+ " str r4, [r3] \n"/* Disable MPU. */
+ " \n"
+ " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+ " ldr r4, [r1] \n"/* r4 = *r1 i.e. r4 = MAIR0. */
+ " ldr r3, xMAIR0Const \n"/* r3 = 0xe000edc0 [Location of MAIR0]. */
+ " str r4, [r3] \n"/* Program MAIR0. */
+ " ldr r4, xRNRConst \n"/* r4 = 0xe000ed98 [Location of RNR]. */
+ " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+ " movs r5, #4 \n"/* r5 = 4. */
+ " str r5, [r4] \n"/* Program RNR = 4. */
+ " ldmia r1!, {r6,r7} \n"/* Read first set of RBAR/RLAR from TCB. */
+ " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+ " stmia r3!, {r6,r7} \n"/* Write first set of RBAR/RLAR registers. */
+ " movs r5, #5 \n"/* r5 = 5. */
+ " str r5, [r4] \n"/* Program RNR = 5. */
+ " ldmia r1!, {r6,r7} \n"/* Read second set of RBAR/RLAR from TCB. */
+ " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+ " stmia r3!, {r6,r7} \n"/* Write second set of RBAR/RLAR registers. */
+ " movs r5, #6 \n"/* r5 = 6. */
+ " str r5, [r4] \n"/* Program RNR = 6. */
+ " ldmia r1!, {r6,r7} \n"/* Read third set of RBAR/RLAR from TCB. */
+ " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+ " stmia r3!, {r6,r7} \n"/* Write third set of RBAR/RLAR registers. */
+ " movs r5, #7 \n"/* r5 = 7. */
+ " str r5, [r4] \n"/* Program RNR = 7. */
+ " ldmia r1!, {r6,r7} \n"/* Read fourth set of RBAR/RLAR from TCB. */
+ " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+ " stmia r3!, {r6,r7} \n"/* Write fourth set of RBAR/RLAR registers. */
+ " \n"
+ " ldr r3, xMPUCTRLConst \n"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r4, [r3] \n"/* Read the value of MPU_CTRL. */
+ " movs r5, #1 \n"/* r5 = 1. */
+ " orrs r4, r5 \n"/* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
+ " str r4, [r3] \n"/* Enable MPU. */
+ " dsb \n"/* Force memory writes before continuing. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ #if ( configENABLE_MPU == 1 )
+ " ldmia r2!, {r0, r1, r3, r4} \n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */
+ " msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */
+ " msr control, r3 \n"/* Restore the CONTROL register value for the task. */
+ " mov lr, r4 \n"/* LR = r4. */
+ " ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ " str r0, [r3] \n"/* Restore the task's xSecureContext. */
+ " cbz r0, restore_ns_context \n"/* If there is no secure context for the task, restore the non-secure context. */
+ " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r3] \n"/* Read pxCurrentTCB. */
+ " push {r2, r4} \n"
+ " bl SecureContext_LoadContext \n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+ " pop {r2, r4} \n"
+ " mov lr, r4 \n"/* LR = r4. */
+ " lsls r1, r4, #25 \n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+ " bpl restore_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+ " msr psp, r2 \n"/* Remember the new top of stack for the task. */
+ " bx lr \n"
+ #else /* configENABLE_MPU */
+ " ldmia r2!, {r0, r1, r4} \n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
+ " msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */
+ " mov lr, r4 \n"/* LR = r4. */
+ " ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ " str r0, [r3] \n"/* Restore the task's xSecureContext. */
+ " cbz r0, restore_ns_context \n"/* If there is no secure context for the task, restore the non-secure context. */
+ " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r3] \n"/* Read pxCurrentTCB. */
+ " push {r2, r4} \n"
+ " bl SecureContext_LoadContext \n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+ " pop {r2, r4} \n"
+ " mov lr, r4 \n"/* LR = r4. */
+ " lsls r1, r4, #25 \n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+ " bpl restore_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+ " msr psp, r2 \n"/* Remember the new top of stack for the task. */
+ " bx lr \n"
+ #endif /* configENABLE_MPU */
+ " \n"
+ " restore_ns_context: \n"
+ " adds r2, r2, #16 \n"/* Move to the high registers. */
+ " ldmia r2!, {r4-r7} \n"/* Restore the high registers that are not automatically restored. */
+ " mov r8, r4 \n"/* r8 = r4. */
+ " mov r9, r5 \n"/* r9 = r5. */
+ " mov r10, r6 \n"/* r10 = r6. */
+ " mov r11, r7 \n"/* r11 = r7. */
+ " msr psp, r2 \n"/* Remember the new top of stack for the task. */
+ " subs r2, r2, #32 \n"/* Go back to the low registers. */
+ " ldmia r2!, {r4-r7} \n"/* Restore the low registers that are not automatically restored. */
+ " bx lr \n"
+ " \n"
+ " .align 4 \n"
+ "pxCurrentTCBConst: .word pxCurrentTCB \n"
+ "xSecureContextConst: .word xSecureContext \n"
+ #if ( configENABLE_MPU == 1 )
+ "xMPUCTRLConst: .word 0xe000ed94 \n"
+ "xMAIR0Const: .word 0xe000edc0 \n"
+ "xRNRConst: .word 0xe000ed98 \n"
+ "xRBARConst: .word 0xe000ed9c \n"
+ #endif /* configENABLE_MPU */
+ );
+}
+/*-----------------------------------------------------------*/
+
+void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " movs r0, #4 \n"
+ " mov r1, lr \n"
+ " tst r0, r1 \n"
+ " beq stacking_used_msp \n"
+ " mrs r0, psp \n"
+ " ldr r2, svchandler_address_const \n"
+ " bx r2 \n"
+ " stacking_used_msp: \n"
+ " mrs r0, msp \n"
+ " ldr r2, svchandler_address_const \n"
+ " bx r2 \n"
+ " \n"
+ " .align 4 \n"
+ "svchandler_address_const: .word vPortSVCHandler_C \n"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " svc %0 \n"/* Secure context is allocated in the supervisor call. */
+ " bx lr \n"/* Return. */
+ ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " ldr r2, [r0] \n"/* The first item in the TCB is the top of the stack. */
+ " ldr r1, [r2] \n"/* The first item on the stack is the task's xSecureContext. */
+ " cmp r1, #0 \n"/* Raise svc if task's xSecureContext is not NULL. */
+ " bne free_secure_context \n"/* Branch if r1 != 0. */
+ " bx lr \n"/* There is no secure context (xSecureContext is NULL). */
+ " free_secure_context: \n"
+ " svc %0 \n"/* Secure context is freed in the supervisor call. */
+ " bx lr \n"/* Return. */
+ ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
+ );
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM23/non_secure/portasm.h b/portable/GCC/ARM_CM23/non_secure/portasm.h
index b37f6d1..ecd86b9 100644
--- a/portable/GCC/ARM_CM23/non_secure/portasm.h
+++ b/portable/GCC/ARM_CM23/non_secure/portasm.h
@@ -1,114 +1,114 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef __PORT_ASM_H__
-#define __PORT_ASM_H__
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-
-/* MPU wrappers includes. */
-#include "mpu_wrappers.h"
-
-/**
- * @brief Restore the context of the first task so that the first task starts
- * executing.
- */
-void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
-BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
-
-/**
- * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
- * register.
- *
- * @note This is a privileged function and should only be called from the kenrel
- * code.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- * Bit[0] = 0 --> The processor is running privileged
- * Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- * Bit[0] = 0 --> The processor is running privileged
- * Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vResetPrivilege( void ) __attribute__( ( naked ) );
-
-/**
- * @brief Starts the first task.
- */
-void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Disables interrupts.
- */
-uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Enables interrupts.
- */
-void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief PendSV Exception handler.
- */
-void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief SVC Handler.
- */
-void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Allocate a Secure context for the calling task.
- *
- * @param[in] ulSecureStackSize The size of the stack to be allocated on the
- * secure side for the calling task.
- */
-void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );
-
-/**
- * @brief Free the task's secure context.
- *
- * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
- */
-void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-#endif /* __PORT_ASM_H__ */
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/portable/GCC/ARM_CM23/non_secure/portmacro.h b/portable/GCC/ARM_CM23/non_secure/portmacro.h
index 3486481..f98b8f2 100644
--- a/portable/GCC/ARM_CM23/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM23/non_secure/portmacro.h
@@ -1,71 +1,71 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "portmacrocommon.h"
-
-/*------------------------------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *------------------------------------------------------------------------------
- */
-
-/**
- * Architecture specifics.
- */
-#define portARCH_NAME "Cortex-M23"
-#define portDONT_DISCARD __attribute__( ( used ) )
-/*-----------------------------------------------------------*/
-
-#if( configTOTAL_MPU_REGIONS == 16 )
- #error 16 MPU regions are not yet supported for this port.
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Critical section management.
- */
-#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
-#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )
-/*-----------------------------------------------------------*/
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* PORTMACRO_H */
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "portmacrocommon.h"
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME "Cortex-M23"
+#define portDONT_DISCARD __attribute__( ( used ) )
+/*-----------------------------------------------------------*/
+
+#if( configTOTAL_MPU_REGIONS == 16 )
+ #error 16 MPU regions are not yet supported for this port.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
index 4b1f99b..51e21ea 100644
--- a/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
@@ -155,9 +155,9 @@
* 8-bit values encoded as follows:
* Bit[7:4] - 0000 - Device Memory
* Bit[3:2] - 00 --> Device-nGnRnE
- * 01 --> Device-nGnRE
- * 10 --> Device-nGRE
- * 11 --> Device-GRE
+ * 01 --> Device-nGnRE
+ * 10 --> Device-nGRE
+ * 11 --> Device-GRE
* Bit[1:0] - 00, Reserved.
*/
#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
diff --git a/portable/GCC/ARM_CM23/secure/secure_context.c b/portable/GCC/ARM_CM23/secure/secure_context.c
index b1d5503..0730d57 100644
--- a/portable/GCC/ARM_CM23/secure/secure_context.c
+++ b/portable/GCC/ARM_CM23/secure/secure_context.c
@@ -1,351 +1,351 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/* Secure context includes. */
-#include "secure_context.h"
-
-/* Secure heap includes. */
-#include "secure_heap.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/**
- * @brief CONTROL value for privileged tasks.
- *
- * Bit[0] - 0 --> Thread mode is privileged.
- * Bit[1] - 1 --> Thread mode uses PSP.
- */
-#define securecontextCONTROL_VALUE_PRIVILEGED 0x02
-
-/**
- * @brief CONTROL value for un-privileged tasks.
- *
- * Bit[0] - 1 --> Thread mode is un-privileged.
- * Bit[1] - 1 --> Thread mode uses PSP.
- */
-#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03
-
-/**
- * @brief Size of stack seal values in bytes.
- */
-#define securecontextSTACK_SEAL_SIZE 8
-
-/**
- * @brief Stack seal value as recommended by ARM.
- */
-#define securecontextSTACK_SEAL_VALUE 0xFEF5EDA5
-
-/**
- * @brief Maximum number of secure contexts.
- */
-#ifndef secureconfigMAX_SECURE_CONTEXTS
- #define secureconfigMAX_SECURE_CONTEXTS 8UL
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Pre-allocated array of secure contexts.
- */
-SecureContext_t xSecureContexts[ secureconfigMAX_SECURE_CONTEXTS ];
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Get a free secure context for a task from the secure context pool (xSecureContexts).
- *
- * This function ensures that only one secure context is allocated for a task.
- *
- * @param[in] pvTaskHandle The task handle for which the secure context is allocated.
- *
- * @return Index of a free secure context in the xSecureContexts array.
- */
-static uint32_t ulGetSecureContext( void * pvTaskHandle );
-
-/**
- * @brief Return the secure context to the secure context pool (xSecureContexts).
- *
- * @param[in] ulSecureContextIndex Index of the context in the xSecureContexts array.
- */
-static void vReturnSecureContext( uint32_t ulSecureContextIndex );
-
-/* These are implemented in assembly. */
-extern void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext );
-extern void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext );
-/*-----------------------------------------------------------*/
-
-static uint32_t ulGetSecureContext( void * pvTaskHandle )
-{
- /* Start with invalid index. */
- uint32_t i, ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS;
-
- for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ )
- {
- if( ( xSecureContexts[ i ].pucCurrentStackPointer == NULL ) &&
- ( xSecureContexts[ i ].pucStackLimit == NULL ) &&
- ( xSecureContexts[ i ].pucStackStart == NULL ) &&
- ( xSecureContexts[ i ].pvTaskHandle == NULL ) &&
- ( ulSecureContextIndex == secureconfigMAX_SECURE_CONTEXTS ) )
- {
- ulSecureContextIndex = i;
- }
- else if( xSecureContexts[ i ].pvTaskHandle == pvTaskHandle )
- {
- /* A task can only have one secure context. Do not allocate a second
- * context for the same task. */
- ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS;
- break;
- }
- }
-
- return ulSecureContextIndex;
-}
-/*-----------------------------------------------------------*/
-
-static void vReturnSecureContext( uint32_t ulSecureContextIndex )
-{
- xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = NULL;
- xSecureContexts[ ulSecureContextIndex ].pucStackLimit = NULL;
- xSecureContexts[ ulSecureContextIndex ].pucStackStart = NULL;
- xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = NULL;
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
-{
- uint32_t ulIPSR, i;
- static uint32_t ulSecureContextsInitialized = 0;
-
- /* Read the Interrupt Program Status Register (IPSR) value. */
- secureportREAD_IPSR( ulIPSR );
-
- /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
- * when the processor is running in the Thread Mode. */
- if( ( ulIPSR != 0 ) && ( ulSecureContextsInitialized == 0 ) )
- {
- /* Ensure to initialize secure contexts only once. */
- ulSecureContextsInitialized = 1;
-
- /* No stack for thread mode until a task's context is loaded. */
- secureportSET_PSPLIM( securecontextNO_STACK );
- secureportSET_PSP( securecontextNO_STACK );
-
- /* Initialize all secure contexts. */
- for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ )
- {
- xSecureContexts[ i ].pucCurrentStackPointer = NULL;
- xSecureContexts[ i ].pucStackLimit = NULL;
- xSecureContexts[ i ].pucStackStart = NULL;
- xSecureContexts[ i ].pvTaskHandle = NULL;
- }
-
- #if ( configENABLE_MPU == 1 )
- {
- /* Configure thread mode to use PSP and to be unprivileged. */
- secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
- }
- #else /* configENABLE_MPU */
- {
- /* Configure thread mode to use PSP and to be privileged. */
- secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
- }
- #endif /* configENABLE_MPU */
- }
-}
-/*-----------------------------------------------------------*/
-
-#if ( configENABLE_MPU == 1 )
- secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
- uint32_t ulIsTaskPrivileged,
- void * pvTaskHandle )
-#else /* configENABLE_MPU */
- secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
- void * pvTaskHandle )
-#endif /* configENABLE_MPU */
-{
- uint8_t * pucStackMemory = NULL;
- uint8_t * pucStackLimit;
- uint32_t ulIPSR, ulSecureContextIndex;
- SecureContextHandle_t xSecureContextHandle = securecontextINVALID_CONTEXT_ID;
-
- #if ( configENABLE_MPU == 1 )
- uint32_t * pulCurrentStackPointer = NULL;
- #endif /* configENABLE_MPU */
-
- /* Read the Interrupt Program Status Register (IPSR) and Process Stack Limit
- * Register (PSPLIM) value. */
- secureportREAD_IPSR( ulIPSR );
- secureportREAD_PSPLIM( pucStackLimit );
-
- /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
- * when the processor is running in the Thread Mode.
- * Also do nothing, if a secure context us already loaded. PSPLIM is set to
- * securecontextNO_STACK when no secure context is loaded. */
- if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )
- {
- /* Ontain a free secure context. */
- ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );
-
- /* Were we able to get a free context? */
- if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS )
- {
- /* Allocate the stack space. */
- pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE );
-
- if( pucStackMemory != NULL )
- {
- /* Since stack grows down, the starting point will be the last
- * location. Note that this location is next to the last
- * allocated byte for stack (excluding the space for seal values)
- * because the hardware decrements the stack pointer before
- * writing i.e. if stack pointer is 0x2, a push operation will
- * decrement the stack pointer to 0x1 and then write at 0x1. */
- xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize;
-
- /* Seal the created secure process stack. */
- *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
- *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
-
- /* The stack cannot go beyond this location. This value is
- * programmed in the PSPLIM register on context switch.*/
- xSecureContexts[ ulSecureContextIndex ].pucStackLimit = pucStackMemory;
-
- xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle;
-
- #if ( configENABLE_MPU == 1 )
- {
- /* Store the correct CONTROL value for the task on the stack.
- * This value is programmed in the CONTROL register on
- * context switch. */
- pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
- pulCurrentStackPointer--;
-
- if( ulIsTaskPrivileged )
- {
- *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
- }
- else
- {
- *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
- }
-
- /* Store the current stack pointer. This value is programmed in
- * the PSP register on context switch. */
- xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
- }
- #else /* configENABLE_MPU */
- {
- /* Current SP is set to the starting of the stack. This
- * value programmed in the PSP register on context switch. */
- xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
- }
- #endif /* configENABLE_MPU */
-
- /* Ensure to never return 0 as a valid context handle. */
- xSecureContextHandle = ulSecureContextIndex + 1UL;
- }
- }
- }
-
- return xSecureContextHandle;
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
-{
- uint32_t ulIPSR, ulSecureContextIndex;
-
- /* Read the Interrupt Program Status Register (IPSR) value. */
- secureportREAD_IPSR( ulIPSR );
-
- /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
- * when the processor is running in the Thread Mode. */
- if( ulIPSR != 0 )
- {
- /* Only free if a valid context handle is passed. */
- if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )
- {
- ulSecureContextIndex = xSecureContextHandle - 1UL;
-
- /* Ensure that the secure context being deleted is associated with
- * the task. */
- if( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle )
- {
- /* Free the stack space. */
- vPortFree( xSecureContexts[ ulSecureContextIndex ].pucStackLimit );
-
- /* Return the secure context back to the free secure contexts pool. */
- vReturnSecureContext( ulSecureContextIndex );
- }
- }
- }
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
-{
- uint8_t * pucStackLimit;
- uint32_t ulSecureContextIndex;
-
- if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )
- {
- ulSecureContextIndex = xSecureContextHandle - 1UL;
-
- secureportREAD_PSPLIM( pucStackLimit );
-
- /* Ensure that no secure context is loaded and the task is loading it's
- * own context. */
- if( ( pucStackLimit == securecontextNO_STACK ) &&
- ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )
- {
- SecureContext_LoadContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) );
- }
- }
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
-{
- uint8_t * pucStackLimit;
- uint32_t ulSecureContextIndex;
-
- if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )
- {
- ulSecureContextIndex = xSecureContextHandle - 1UL;
-
- secureportREAD_PSPLIM( pucStackLimit );
-
- /* Ensure that task's context is loaded and the task is saving it's own
- * context. */
- if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) &&
- ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )
- {
- SecureContext_SaveContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) );
- }
- }
-}
-/*-----------------------------------------------------------*/
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief CONTROL value for privileged tasks.
+ *
+ * Bit[0] - 0 --> Thread mode is privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_PRIVILEGED 0x02
+
+/**
+ * @brief CONTROL value for un-privileged tasks.
+ *
+ * Bit[0] - 1 --> Thread mode is un-privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03
+
+/**
+ * @brief Size of stack seal values in bytes.
+ */
+#define securecontextSTACK_SEAL_SIZE 8
+
+/**
+ * @brief Stack seal value as recommended by ARM.
+ */
+#define securecontextSTACK_SEAL_VALUE 0xFEF5EDA5
+
+/**
+ * @brief Maximum number of secure contexts.
+ */
+#ifndef secureconfigMAX_SECURE_CONTEXTS
+ #define secureconfigMAX_SECURE_CONTEXTS 8UL
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Pre-allocated array of secure contexts.
+ */
+SecureContext_t xSecureContexts[ secureconfigMAX_SECURE_CONTEXTS ];
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Get a free secure context for a task from the secure context pool (xSecureContexts).
+ *
+ * This function ensures that only one secure context is allocated for a task.
+ *
+ * @param[in] pvTaskHandle The task handle for which the secure context is allocated.
+ *
+ * @return Index of a free secure context in the xSecureContexts array.
+ */
+static uint32_t ulGetSecureContext( void * pvTaskHandle );
+
+/**
+ * @brief Return the secure context to the secure context pool (xSecureContexts).
+ *
+ * @param[in] ulSecureContextIndex Index of the context in the xSecureContexts array.
+ */
+static void vReturnSecureContext( uint32_t ulSecureContextIndex );
+
+/* These are implemented in assembly. */
+extern void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext );
+extern void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext );
+/*-----------------------------------------------------------*/
+
+static uint32_t ulGetSecureContext( void * pvTaskHandle )
+{
+ /* Start with invalid index. */
+ uint32_t i, ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS;
+
+ for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ )
+ {
+ if( ( xSecureContexts[ i ].pucCurrentStackPointer == NULL ) &&
+ ( xSecureContexts[ i ].pucStackLimit == NULL ) &&
+ ( xSecureContexts[ i ].pucStackStart == NULL ) &&
+ ( xSecureContexts[ i ].pvTaskHandle == NULL ) &&
+ ( ulSecureContextIndex == secureconfigMAX_SECURE_CONTEXTS ) )
+ {
+ ulSecureContextIndex = i;
+ }
+ else if( xSecureContexts[ i ].pvTaskHandle == pvTaskHandle )
+ {
+ /* A task can only have one secure context. Do not allocate a second
+ * context for the same task. */
+ ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS;
+ break;
+ }
+ }
+
+ return ulSecureContextIndex;
+}
+/*-----------------------------------------------------------*/
+
+static void vReturnSecureContext( uint32_t ulSecureContextIndex )
+{
+ xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = NULL;
+ xSecureContexts[ ulSecureContextIndex ].pucStackLimit = NULL;
+ xSecureContexts[ ulSecureContextIndex ].pucStackStart = NULL;
+ xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = NULL;
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
+{
+ uint32_t ulIPSR, i;
+ static uint32_t ulSecureContextsInitialized = 0;
+
+ /* Read the Interrupt Program Status Register (IPSR) value. */
+ secureportREAD_IPSR( ulIPSR );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode. */
+ if( ( ulIPSR != 0 ) && ( ulSecureContextsInitialized == 0 ) )
+ {
+ /* Ensure to initialize secure contexts only once. */
+ ulSecureContextsInitialized = 1;
+
+ /* No stack for thread mode until a task's context is loaded. */
+ secureportSET_PSPLIM( securecontextNO_STACK );
+ secureportSET_PSP( securecontextNO_STACK );
+
+ /* Initialize all secure contexts. */
+ for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ )
+ {
+ xSecureContexts[ i ].pucCurrentStackPointer = NULL;
+ xSecureContexts[ i ].pucStackLimit = NULL;
+ xSecureContexts[ i ].pucStackStart = NULL;
+ xSecureContexts[ i ].pvTaskHandle = NULL;
+ }
+
+ #if ( configENABLE_MPU == 1 )
+ {
+ /* Configure thread mode to use PSP and to be unprivileged. */
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+ }
+ #else /* configENABLE_MPU */
+ {
+ /* Configure thread mode to use PSP and to be privileged. */
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+ }
+ #endif /* configENABLE_MPU */
+ }
+}
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+ secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
+ uint32_t ulIsTaskPrivileged,
+ void * pvTaskHandle )
+#else /* configENABLE_MPU */
+ secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
+ void * pvTaskHandle )
+#endif /* configENABLE_MPU */
+{
+ uint8_t * pucStackMemory = NULL;
+ uint8_t * pucStackLimit;
+ uint32_t ulIPSR, ulSecureContextIndex;
+ SecureContextHandle_t xSecureContextHandle = securecontextINVALID_CONTEXT_ID;
+
+ #if ( configENABLE_MPU == 1 )
+ uint32_t * pulCurrentStackPointer = NULL;
+ #endif /* configENABLE_MPU */
+
+ /* Read the Interrupt Program Status Register (IPSR) and Process Stack Limit
+ * Register (PSPLIM) value. */
+ secureportREAD_IPSR( ulIPSR );
+ secureportREAD_PSPLIM( pucStackLimit );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode.
+ * Also do nothing, if a secure context us already loaded. PSPLIM is set to
+ * securecontextNO_STACK when no secure context is loaded. */
+ if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )
+ {
+ /* Ontain a free secure context. */
+ ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );
+
+ /* Were we able to get a free context? */
+ if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS )
+ {
+ /* Allocate the stack space. */
+ pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE );
+
+ if( pucStackMemory != NULL )
+ {
+ /* Since stack grows down, the starting point will be the last
+ * location. Note that this location is next to the last
+ * allocated byte for stack (excluding the space for seal values)
+ * because the hardware decrements the stack pointer before
+ * writing i.e. if stack pointer is 0x2, a push operation will
+ * decrement the stack pointer to 0x1 and then write at 0x1. */
+ xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize;
+
+ /* Seal the created secure process stack. */
+ *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
+ *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
+
+ /* The stack cannot go beyond this location. This value is
+ * programmed in the PSPLIM register on context switch.*/
+ xSecureContexts[ ulSecureContextIndex ].pucStackLimit = pucStackMemory;
+
+ xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle;
+
+ #if ( configENABLE_MPU == 1 )
+ {
+ /* Store the correct CONTROL value for the task on the stack.
+ * This value is programmed in the CONTROL register on
+ * context switch. */
+ pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+ pulCurrentStackPointer--;
+
+ if( ulIsTaskPrivileged )
+ {
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
+ }
+ else
+ {
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+ }
+
+ /* Store the current stack pointer. This value is programmed in
+ * the PSP register on context switch. */
+ xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+ }
+ #else /* configENABLE_MPU */
+ {
+ /* Current SP is set to the starting of the stack. This
+ * value programmed in the PSP register on context switch. */
+ xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+ }
+ #endif /* configENABLE_MPU */
+
+ /* Ensure to never return 0 as a valid context handle. */
+ xSecureContextHandle = ulSecureContextIndex + 1UL;
+ }
+ }
+ }
+
+ return xSecureContextHandle;
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+{
+ uint32_t ulIPSR, ulSecureContextIndex;
+
+ /* Read the Interrupt Program Status Register (IPSR) value. */
+ secureportREAD_IPSR( ulIPSR );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode. */
+ if( ulIPSR != 0 )
+ {
+ /* Only free if a valid context handle is passed. */
+ if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )
+ {
+ ulSecureContextIndex = xSecureContextHandle - 1UL;
+
+ /* Ensure that the secure context being deleted is associated with
+ * the task. */
+ if( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle )
+ {
+ /* Free the stack space. */
+ vPortFree( xSecureContexts[ ulSecureContextIndex ].pucStackLimit );
+
+ /* Return the secure context back to the free secure contexts pool. */
+ vReturnSecureContext( ulSecureContextIndex );
+ }
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+{
+ uint8_t * pucStackLimit;
+ uint32_t ulSecureContextIndex;
+
+ if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )
+ {
+ ulSecureContextIndex = xSecureContextHandle - 1UL;
+
+ secureportREAD_PSPLIM( pucStackLimit );
+
+ /* Ensure that no secure context is loaded and the task is loading it's
+ * own context. */
+ if( ( pucStackLimit == securecontextNO_STACK ) &&
+ ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )
+ {
+ SecureContext_LoadContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) );
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+{
+ uint8_t * pucStackLimit;
+ uint32_t ulSecureContextIndex;
+
+ if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )
+ {
+ ulSecureContextIndex = xSecureContextHandle - 1UL;
+
+ secureportREAD_PSPLIM( pucStackLimit );
+
+ /* Ensure that task's context is loaded and the task is saving it's own
+ * context. */
+ if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) &&
+ ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )
+ {
+ SecureContext_SaveContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) );
+ }
+ }
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM23/secure/secure_context.h b/portable/GCC/ARM_CM23/secure/secure_context.h
index 57e390c..d0adbaf 100644
--- a/portable/GCC/ARM_CM23/secure/secure_context.h
+++ b/portable/GCC/ARM_CM23/secure/secure_context.h
@@ -1,135 +1,135 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef __SECURE_CONTEXT_H__
-#define __SECURE_CONTEXT_H__
-
-/* Standard includes. */
-#include <stdint.h>
-
-/* FreeRTOS includes. */
-#include "FreeRTOSConfig.h"
-
-/**
- * @brief PSP value when no secure context is loaded.
- */
-#define securecontextNO_STACK 0x0
-
-/**
- * @brief Invalid context ID.
- */
-#define securecontextINVALID_CONTEXT_ID 0UL
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Structure to represent a secure context.
- *
- * @note Since stack grows down, pucStackStart is the highest address while
- * pucStackLimit is the first address of the allocated memory.
- */
-typedef struct SecureContext
-{
- uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */
- uint8_t * pucStackLimit; /**< Last location of the stack memory (PSPLIM). */
- uint8_t * pucStackStart; /**< First location of the stack memory. */
- void * pvTaskHandle; /**< Task handle of the task this context is associated with. */
-} SecureContext_t;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Opaque handle for a secure context.
- */
-typedef uint32_t SecureContextHandle_t;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Initializes the secure context management system.
- *
- * PSP is set to NULL and therefore a task must allocate and load a context
- * before calling any secure side function in the thread mode.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- */
-void SecureContext_Init( void );
-
-/**
- * @brief Allocates a context on the secure side.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.
- * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.
- *
- * @return Opaque context handle if context is successfully allocated, NULL
- * otherwise.
- */
-#if ( configENABLE_MPU == 1 )
- SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
- uint32_t ulIsTaskPrivileged,
- void * pvTaskHandle );
-#else /* configENABLE_MPU */
- SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
- void * pvTaskHandle );
-#endif /* configENABLE_MPU */
-
-/**
- * @brief Frees the given context.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] xSecureContextHandle Context handle corresponding to the
- * context to be freed.
- */
-void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
-
-/**
- * @brief Loads the given context.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] xSecureContextHandle Context handle corresponding to the context
- * to be loaded.
- */
-void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
-
-/**
- * @brief Saves the given context.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] xSecureContextHandle Context handle corresponding to the context
- * to be saved.
- */
-void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
-
-#endif /* __SECURE_CONTEXT_H__ */
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef __SECURE_CONTEXT_H__
+#define __SECURE_CONTEXT_H__
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* FreeRTOS includes. */
+#include "FreeRTOSConfig.h"
+
+/**
+ * @brief PSP value when no secure context is loaded.
+ */
+#define securecontextNO_STACK 0x0
+
+/**
+ * @brief Invalid context ID.
+ */
+#define securecontextINVALID_CONTEXT_ID 0UL
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Structure to represent a secure context.
+ *
+ * @note Since stack grows down, pucStackStart is the highest address while
+ * pucStackLimit is the first address of the allocated memory.
+ */
+typedef struct SecureContext
+{
+ uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */
+ uint8_t * pucStackLimit; /**< Last location of the stack memory (PSPLIM). */
+ uint8_t * pucStackStart; /**< First location of the stack memory. */
+ void * pvTaskHandle; /**< Task handle of the task this context is associated with. */
+} SecureContext_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Opaque handle for a secure context.
+ */
+typedef uint32_t SecureContextHandle_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Initializes the secure context management system.
+ *
+ * PSP is set to NULL and therefore a task must allocate and load a context
+ * before calling any secure side function in the thread mode.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureContext_Init( void );
+
+/**
+ * @brief Allocates a context on the secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.
+ * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.
+ *
+ * @return Opaque context handle if context is successfully allocated, NULL
+ * otherwise.
+ */
+#if ( configENABLE_MPU == 1 )
+ SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
+ uint32_t ulIsTaskPrivileged,
+ void * pvTaskHandle );
+#else /* configENABLE_MPU */
+ SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
+ void * pvTaskHandle );
+#endif /* configENABLE_MPU */
+
+/**
+ * @brief Frees the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the
+ * context to be freed.
+ */
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+
+/**
+ * @brief Loads the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be loaded.
+ */
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+
+/**
+ * @brief Saves the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be saved.
+ */
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+
+#endif /* __SECURE_CONTEXT_H__ */
diff --git a/portable/GCC/ARM_CM23/secure/secure_context_port.c b/portable/GCC/ARM_CM23/secure/secure_context_port.c
index 0c87199..2d9eeea 100644
--- a/portable/GCC/ARM_CM23/secure/secure_context_port.c
+++ b/portable/GCC/ARM_CM23/secure/secure_context_port.c
@@ -1,99 +1,99 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/* Secure context includes. */
-#include "secure_context.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-#if ( configENABLE_FPU == 1 )
- #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
-#endif
-
-void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );
-void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );
-
-void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext )
-{
- /* pxSecureContext value is in r0. */
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " mrs r1, ipsr \n" /* r1 = IPSR. */
- " cbz r1, load_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */
- " ldmia r0!, {r1, r2} \n" /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */
- " \n"
- #if ( configENABLE_MPU == 1 )
- " ldmia r1!, {r3} \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */
- " msr control, r3 \n" /* CONTROL = r3. */
- #endif /* configENABLE_MPU */
- " \n"
- " msr psplim, r2 \n" /* PSPLIM = r2. */
- " msr psp, r1 \n" /* PSP = r1. */
- " \n"
- " load_ctx_therad_mode: \n"
- " bx lr \n"
- " \n"
- ::: "r0", "r1", "r2"
- );
-}
-/*-----------------------------------------------------------*/
-
-void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext )
-{
- /* pxSecureContext value is in r0. */
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " mrs r1, ipsr \n" /* r1 = IPSR. */
- " cbz r1, save_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */
- " mrs r1, psp \n" /* r1 = PSP. */
- " \n"
- #if ( configENABLE_MPU == 1 )
- " mrs r2, control \n" /* r2 = CONTROL. */
- " subs r1, r1, #4 \n" /* Make space for the CONTROL value on the stack. */
- " str r1, [r0] \n" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */
- " stmia r1!, {r2} \n" /* Store CONTROL value on the stack. */
- #else /* configENABLE_MPU */
- " str r1, [r0] \n" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */
- #endif /* configENABLE_MPU */
- " \n"
- " movs r1, %0 \n" /* r1 = securecontextNO_STACK. */
- " msr psplim, r1 \n" /* PSPLIM = securecontextNO_STACK. */
- " msr psp, r1 \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
- " \n"
- " save_ctx_therad_mode: \n"
- " bx lr \n"
- " \n"
- ::"i" ( securecontextNO_STACK ) : "r1", "memory"
- );
-}
-/*-----------------------------------------------------------*/
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+#if ( configENABLE_FPU == 1 )
+ #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
+#endif
+
+void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );
+void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );
+
+void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext )
+{
+ /* pxSecureContext value is in r0. */
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r1, ipsr \n" /* r1 = IPSR. */
+ " cbz r1, load_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */
+ " ldmia r0!, {r1, r2} \n" /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */
+ " \n"
+ #if ( configENABLE_MPU == 1 )
+ " ldmia r1!, {r3} \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */
+ " msr control, r3 \n" /* CONTROL = r3. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ " msr psplim, r2 \n" /* PSPLIM = r2. */
+ " msr psp, r1 \n" /* PSP = r1. */
+ " \n"
+ " load_ctx_therad_mode: \n"
+ " bx lr \n"
+ " \n"
+ ::: "r0", "r1", "r2"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext )
+{
+ /* pxSecureContext value is in r0. */
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r1, ipsr \n" /* r1 = IPSR. */
+ " cbz r1, save_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */
+ " mrs r1, psp \n" /* r1 = PSP. */
+ " \n"
+ #if ( configENABLE_MPU == 1 )
+ " mrs r2, control \n" /* r2 = CONTROL. */
+ " subs r1, r1, #4 \n" /* Make space for the CONTROL value on the stack. */
+ " str r1, [r0] \n" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */
+ " stmia r1!, {r2} \n" /* Store CONTROL value on the stack. */
+ #else /* configENABLE_MPU */
+ " str r1, [r0] \n" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ " movs r1, %0 \n" /* r1 = securecontextNO_STACK. */
+ " msr psplim, r1 \n" /* PSPLIM = securecontextNO_STACK. */
+ " msr psp, r1 \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
+ " \n"
+ " save_ctx_therad_mode: \n"
+ " bx lr \n"
+ " \n"
+ ::"i" ( securecontextNO_STACK ) : "r1", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM23/secure/secure_heap.c b/portable/GCC/ARM_CM23/secure/secure_heap.c
index 741b463..157fdbf 100644
--- a/portable/GCC/ARM_CM23/secure/secure_heap.c
+++ b/portable/GCC/ARM_CM23/secure/secure_heap.c
@@ -1,454 +1,454 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/* Standard includes. */
-#include <stdint.h>
-
-/* Secure context heap includes. */
-#include "secure_heap.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/**
- * @brief Total heap size.
- */
-#ifndef secureconfigTOTAL_HEAP_SIZE
- #define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) )
-#endif
-
-/* No test marker by default. */
-#ifndef mtCOVERAGE_TEST_MARKER
- #define mtCOVERAGE_TEST_MARKER()
-#endif
-
-/* No tracing by default. */
-#ifndef traceMALLOC
- #define traceMALLOC( pvReturn, xWantedSize )
-#endif
-
-/* No tracing by default. */
-#ifndef traceFREE
- #define traceFREE( pv, xBlockSize )
-#endif
-
-/* Block sizes must not get too small. */
-#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) )
-
-/* Assumes 8bit bytes! */
-#define secureheapBITS_PER_BYTE ( ( size_t ) 8 )
-/*-----------------------------------------------------------*/
-
-/* Allocate the memory for the heap. */
-#if ( configAPPLICATION_ALLOCATED_HEAP == 1 )
-
-/* The application writer has already defined the array used for the RTOS
-* heap - probably so it can be placed in a special segment or address. */
- extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
-#else /* configAPPLICATION_ALLOCATED_HEAP */
- static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
-#endif /* configAPPLICATION_ALLOCATED_HEAP */
-
-/**
- * @brief The linked list structure.
- *
- * This is used to link free blocks in order of their memory address.
- */
-typedef struct A_BLOCK_LINK
-{
- struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */
- size_t xBlockSize; /**< The size of the free block. */
-} BlockLink_t;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Called automatically to setup the required heap structures the first
- * time pvPortMalloc() is called.
- */
-static void prvHeapInit( void );
-
-/**
- * @brief Inserts a block of memory that is being freed into the correct
- * position in the list of free memory blocks.
- *
- * The block being freed will be merged with the block in front it and/or the
- * block behind it if the memory blocks are adjacent to each other.
- *
- * @param[in] pxBlockToInsert The block being freed.
- */
-static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert );
-/*-----------------------------------------------------------*/
-
-/**
- * @brief The size of the structure placed at the beginning of each allocated
- * memory block must by correctly byte aligned.
- */
-static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
-
-/**
- * @brief Create a couple of list links to mark the start and end of the list.
- */
-static BlockLink_t xStart;
-static BlockLink_t * pxEnd = NULL;
-
-/**
- * @brief Keeps track of the number of free bytes remaining, but says nothing
- * about fragmentation.
- */
-static size_t xFreeBytesRemaining = 0U;
-static size_t xMinimumEverFreeBytesRemaining = 0U;
-
-/**
- * @brief Gets set to the top bit of an size_t type.
- *
- * When this bit in the xBlockSize member of an BlockLink_t structure is set
- * then the block belongs to the application. When the bit is free the block is
- * still part of the free heap space.
- */
-static size_t xBlockAllocatedBit = 0;
-/*-----------------------------------------------------------*/
-
-static void prvHeapInit( void )
-{
- BlockLink_t * pxFirstFreeBlock;
- uint8_t * pucAlignedHeap;
- size_t uxAddress;
- size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;
-
- /* Ensure the heap starts on a correctly aligned boundary. */
- uxAddress = ( size_t ) ucHeap;
-
- if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )
- {
- uxAddress += ( secureportBYTE_ALIGNMENT - 1 );
- uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
- xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
- }
-
- pucAlignedHeap = ( uint8_t * ) uxAddress;
-
- /* xStart is used to hold a pointer to the first item in the list of free
- * blocks. The void cast is used to prevent compiler warnings. */
- xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
- xStart.xBlockSize = ( size_t ) 0;
-
- /* pxEnd is used to mark the end of the list of free blocks and is inserted
- * at the end of the heap space. */
- uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
- uxAddress -= xHeapStructSize;
- uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
- pxEnd = ( void * ) uxAddress;
- pxEnd->xBlockSize = 0;
- pxEnd->pxNextFreeBlock = NULL;
-
- /* To start with there is a single free block that is sized to take up the
- * entire heap space, minus the space taken by pxEnd. */
- pxFirstFreeBlock = ( void * ) pucAlignedHeap;
- pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
- pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
-
- /* Only one block exists - and it covers the entire usable heap space. */
- xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
- xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-
- /* Work out the position of the top bit in a size_t variable. */
- xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
-}
-/*-----------------------------------------------------------*/
-
-static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )
-{
- BlockLink_t * pxIterator;
- uint8_t * puc;
-
- /* Iterate through the list until a block is found that has a higher address
- * than the block being inserted. */
- for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
- {
- /* Nothing to do here, just iterate to the right position. */
- }
-
- /* Do the block being inserted, and the block it is being inserted after
- * make a contiguous block of memory? */
- puc = ( uint8_t * ) pxIterator;
-
- if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
- {
- pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
- pxBlockToInsert = pxIterator;
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
-
- /* Do the block being inserted, and the block it is being inserted before
- * make a contiguous block of memory? */
- puc = ( uint8_t * ) pxBlockToInsert;
-
- if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
- {
- if( pxIterator->pxNextFreeBlock != pxEnd )
- {
- /* Form one big block from the two blocks. */
- pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
- pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
- }
- else
- {
- pxBlockToInsert->pxNextFreeBlock = pxEnd;
- }
- }
- else
- {
- pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
- }
-
- /* If the block being inserted plugged a gab, so was merged with the block
- * before and the block after, then it's pxNextFreeBlock pointer will have
- * already been set, and should not be set here as that would make it point
- * to itself. */
- if( pxIterator != pxBlockToInsert )
- {
- pxIterator->pxNextFreeBlock = pxBlockToInsert;
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
-}
-/*-----------------------------------------------------------*/
-
-void * pvPortMalloc( size_t xWantedSize )
-{
- BlockLink_t * pxBlock;
- BlockLink_t * pxPreviousBlock;
- BlockLink_t * pxNewBlockLink;
- void * pvReturn = NULL;
-
- /* If this is the first call to malloc then the heap will require
- * initialisation to setup the list of free blocks. */
- if( pxEnd == NULL )
- {
- prvHeapInit();
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
-
- /* Check the requested block size is not so large that the top bit is set.
- * The top bit of the block size member of the BlockLink_t structure is used
- * to determine who owns the block - the application or the kernel, so it
- * must be free. */
- if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
- {
- /* The wanted size is increased so it can contain a BlockLink_t
- * structure in addition to the requested amount of bytes. */
- if( xWantedSize > 0 )
- {
- xWantedSize += xHeapStructSize;
-
- /* Ensure that blocks are always aligned to the required number of
- * bytes. */
- if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
- {
- /* Byte alignment required. */
- xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
- secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
-
- if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
- {
- /* Traverse the list from the start (lowest address) block until
- * one of adequate size is found. */
- pxPreviousBlock = &xStart;
- pxBlock = xStart.pxNextFreeBlock;
-
- while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
- {
- pxPreviousBlock = pxBlock;
- pxBlock = pxBlock->pxNextFreeBlock;
- }
-
- /* If the end marker was reached then a block of adequate size was
- * not found. */
- if( pxBlock != pxEnd )
- {
- /* Return the memory space pointed to - jumping over the
- * BlockLink_t structure at its start. */
- pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
-
- /* This block is being returned for use so must be taken out
- * of the list of free blocks. */
- pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
-
- /* If the block is larger than required it can be split into
- * two. */
- if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )
- {
- /* This block is to be split into two. Create a new
- * block following the number of bytes requested. The void
- * cast is used to prevent byte alignment warnings from the
- * compiler. */
- pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
- secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );
-
- /* Calculate the sizes of two blocks split from the single
- * block. */
- pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
- pxBlock->xBlockSize = xWantedSize;
-
- /* Insert the new block into the list of free blocks. */
- prvInsertBlockIntoFreeList( pxNewBlockLink );
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
-
- xFreeBytesRemaining -= pxBlock->xBlockSize;
-
- if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
- {
- xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
-
- /* The block is being returned - it is allocated and owned by
- * the application and has no "next" block. */
- pxBlock->xBlockSize |= xBlockAllocatedBit;
- pxBlock->pxNextFreeBlock = NULL;
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
-
- traceMALLOC( pvReturn, xWantedSize );
-
- #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
- {
- if( pvReturn == NULL )
- {
- extern void vApplicationMallocFailedHook( void );
- vApplicationMallocFailedHook();
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
- }
- #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */
-
- secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
- return pvReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vPortFree( void * pv )
-{
- uint8_t * puc = ( uint8_t * ) pv;
- BlockLink_t * pxLink;
-
- if( pv != NULL )
- {
- /* The memory being freed will have an BlockLink_t structure immediately
- * before it. */
- puc -= xHeapStructSize;
-
- /* This casting is to keep the compiler from issuing warnings. */
- pxLink = ( void * ) puc;
-
- /* Check the block is actually allocated. */
- secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
- secureportASSERT( pxLink->pxNextFreeBlock == NULL );
-
- if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
- {
- if( pxLink->pxNextFreeBlock == NULL )
- {
- /* The block is being returned to the heap - it is no longer
- * allocated. */
- pxLink->xBlockSize &= ~xBlockAllocatedBit;
-
- secureportDISABLE_NON_SECURE_INTERRUPTS();
- {
- /* Add this block to the list of free blocks. */
- xFreeBytesRemaining += pxLink->xBlockSize;
- traceFREE( pv, pxLink->xBlockSize );
- prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
- }
- secureportENABLE_NON_SECURE_INTERRUPTS();
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
- }
-}
-/*-----------------------------------------------------------*/
-
-size_t xPortGetFreeHeapSize( void )
-{
- return xFreeBytesRemaining;
-}
-/*-----------------------------------------------------------*/
-
-size_t xPortGetMinimumEverFreeHeapSize( void )
-{
- return xMinimumEverFreeBytesRemaining;
-}
-/*-----------------------------------------------------------*/
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Secure context heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Total heap size.
+ */
+#ifndef secureconfigTOTAL_HEAP_SIZE
+ #define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) )
+#endif
+
+/* No test marker by default. */
+#ifndef mtCOVERAGE_TEST_MARKER
+ #define mtCOVERAGE_TEST_MARKER()
+#endif
+
+/* No tracing by default. */
+#ifndef traceMALLOC
+ #define traceMALLOC( pvReturn, xWantedSize )
+#endif
+
+/* No tracing by default. */
+#ifndef traceFREE
+ #define traceFREE( pv, xBlockSize )
+#endif
+
+/* Block sizes must not get too small. */
+#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) )
+
+/* Assumes 8bit bytes! */
+#define secureheapBITS_PER_BYTE ( ( size_t ) 8 )
+/*-----------------------------------------------------------*/
+
+/* Allocate the memory for the heap. */
+#if ( configAPPLICATION_ALLOCATED_HEAP == 1 )
+
+/* The application writer has already defined the array used for the RTOS
+* heap - probably so it can be placed in a special segment or address. */
+ extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#else /* configAPPLICATION_ALLOCATED_HEAP */
+ static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+/**
+ * @brief The linked list structure.
+ *
+ * This is used to link free blocks in order of their memory address.
+ */
+typedef struct A_BLOCK_LINK
+{
+ struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */
+ size_t xBlockSize; /**< The size of the free block. */
+} BlockLink_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Called automatically to setup the required heap structures the first
+ * time pvPortMalloc() is called.
+ */
+static void prvHeapInit( void );
+
+/**
+ * @brief Inserts a block of memory that is being freed into the correct
+ * position in the list of free memory blocks.
+ *
+ * The block being freed will be merged with the block in front it and/or the
+ * block behind it if the memory blocks are adjacent to each other.
+ *
+ * @param[in] pxBlockToInsert The block being freed.
+ */
+static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert );
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief The size of the structure placed at the beginning of each allocated
+ * memory block must by correctly byte aligned.
+ */
+static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+
+/**
+ * @brief Create a couple of list links to mark the start and end of the list.
+ */
+static BlockLink_t xStart;
+static BlockLink_t * pxEnd = NULL;
+
+/**
+ * @brief Keeps track of the number of free bytes remaining, but says nothing
+ * about fragmentation.
+ */
+static size_t xFreeBytesRemaining = 0U;
+static size_t xMinimumEverFreeBytesRemaining = 0U;
+
+/**
+ * @brief Gets set to the top bit of an size_t type.
+ *
+ * When this bit in the xBlockSize member of an BlockLink_t structure is set
+ * then the block belongs to the application. When the bit is free the block is
+ * still part of the free heap space.
+ */
+static size_t xBlockAllocatedBit = 0;
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+ BlockLink_t * pxFirstFreeBlock;
+ uint8_t * pucAlignedHeap;
+ size_t uxAddress;
+ size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;
+
+ /* Ensure the heap starts on a correctly aligned boundary. */
+ uxAddress = ( size_t ) ucHeap;
+
+ if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )
+ {
+ uxAddress += ( secureportBYTE_ALIGNMENT - 1 );
+ uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+ xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
+ }
+
+ pucAlignedHeap = ( uint8_t * ) uxAddress;
+
+ /* xStart is used to hold a pointer to the first item in the list of free
+ * blocks. The void cast is used to prevent compiler warnings. */
+ xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+ xStart.xBlockSize = ( size_t ) 0;
+
+ /* pxEnd is used to mark the end of the list of free blocks and is inserted
+ * at the end of the heap space. */
+ uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
+ uxAddress -= xHeapStructSize;
+ uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+ pxEnd = ( void * ) uxAddress;
+ pxEnd->xBlockSize = 0;
+ pxEnd->pxNextFreeBlock = NULL;
+
+ /* To start with there is a single free block that is sized to take up the
+ * entire heap space, minus the space taken by pxEnd. */
+ pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+ pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
+ pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+
+ /* Only one block exists - and it covers the entire usable heap space. */
+ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+ xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+
+ /* Work out the position of the top bit in a size_t variable. */
+ xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )
+{
+ BlockLink_t * pxIterator;
+ uint8_t * puc;
+
+ /* Iterate through the list until a block is found that has a higher address
+ * than the block being inserted. */
+ for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+ {
+ /* Nothing to do here, just iterate to the right position. */
+ }
+
+ /* Do the block being inserted, and the block it is being inserted after
+ * make a contiguous block of memory? */
+ puc = ( uint8_t * ) pxIterator;
+
+ if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+ {
+ pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+ pxBlockToInsert = pxIterator;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Do the block being inserted, and the block it is being inserted before
+ * make a contiguous block of memory? */
+ puc = ( uint8_t * ) pxBlockToInsert;
+
+ if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+ {
+ if( pxIterator->pxNextFreeBlock != pxEnd )
+ {
+ /* Form one big block from the two blocks. */
+ pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+ }
+ else
+ {
+ pxBlockToInsert->pxNextFreeBlock = pxEnd;
+ }
+ }
+ else
+ {
+ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+ }
+
+ /* If the block being inserted plugged a gab, so was merged with the block
+ * before and the block after, then it's pxNextFreeBlock pointer will have
+ * already been set, and should not be set here as that would make it point
+ * to itself. */
+ if( pxIterator != pxBlockToInsert )
+ {
+ pxIterator->pxNextFreeBlock = pxBlockToInsert;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+}
+/*-----------------------------------------------------------*/
+
+void * pvPortMalloc( size_t xWantedSize )
+{
+ BlockLink_t * pxBlock;
+ BlockLink_t * pxPreviousBlock;
+ BlockLink_t * pxNewBlockLink;
+ void * pvReturn = NULL;
+
+ /* If this is the first call to malloc then the heap will require
+ * initialisation to setup the list of free blocks. */
+ if( pxEnd == NULL )
+ {
+ prvHeapInit();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Check the requested block size is not so large that the top bit is set.
+ * The top bit of the block size member of the BlockLink_t structure is used
+ * to determine who owns the block - the application or the kernel, so it
+ * must be free. */
+ if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+ {
+ /* The wanted size is increased so it can contain a BlockLink_t
+ * structure in addition to the requested amount of bytes. */
+ if( xWantedSize > 0 )
+ {
+ xWantedSize += xHeapStructSize;
+
+ /* Ensure that blocks are always aligned to the required number of
+ * bytes. */
+ if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
+ {
+ /* Byte alignment required. */
+ xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
+ secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+ {
+ /* Traverse the list from the start (lowest address) block until
+ * one of adequate size is found. */
+ pxPreviousBlock = &xStart;
+ pxBlock = xStart.pxNextFreeBlock;
+
+ while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+ {
+ pxPreviousBlock = pxBlock;
+ pxBlock = pxBlock->pxNextFreeBlock;
+ }
+
+ /* If the end marker was reached then a block of adequate size was
+ * not found. */
+ if( pxBlock != pxEnd )
+ {
+ /* Return the memory space pointed to - jumping over the
+ * BlockLink_t structure at its start. */
+ pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+
+ /* This block is being returned for use so must be taken out
+ * of the list of free blocks. */
+ pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+ /* If the block is larger than required it can be split into
+ * two. */
+ if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )
+ {
+ /* This block is to be split into two. Create a new
+ * block following the number of bytes requested. The void
+ * cast is used to prevent byte alignment warnings from the
+ * compiler. */
+ pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+ secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+
+ /* Calculate the sizes of two blocks split from the single
+ * block. */
+ pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+ pxBlock->xBlockSize = xWantedSize;
+
+ /* Insert the new block into the list of free blocks. */
+ prvInsertBlockIntoFreeList( pxNewBlockLink );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+ if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+ {
+ xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* The block is being returned - it is allocated and owned by
+ * the application and has no "next" block. */
+ pxBlock->xBlockSize |= xBlockAllocatedBit;
+ pxBlock->pxNextFreeBlock = NULL;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ traceMALLOC( pvReturn, xWantedSize );
+
+ #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+ {
+ if( pvReturn == NULL )
+ {
+ extern void vApplicationMallocFailedHook( void );
+ vApplicationMallocFailedHook();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */
+
+ secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
+ return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void * pv )
+{
+ uint8_t * puc = ( uint8_t * ) pv;
+ BlockLink_t * pxLink;
+
+ if( pv != NULL )
+ {
+ /* The memory being freed will have an BlockLink_t structure immediately
+ * before it. */
+ puc -= xHeapStructSize;
+
+ /* This casting is to keep the compiler from issuing warnings. */
+ pxLink = ( void * ) puc;
+
+ /* Check the block is actually allocated. */
+ secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+ secureportASSERT( pxLink->pxNextFreeBlock == NULL );
+
+ if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+ {
+ if( pxLink->pxNextFreeBlock == NULL )
+ {
+ /* The block is being returned to the heap - it is no longer
+ * allocated. */
+ pxLink->xBlockSize &= ~xBlockAllocatedBit;
+
+ secureportDISABLE_NON_SECURE_INTERRUPTS();
+ {
+ /* Add this block to the list of free blocks. */
+ xFreeBytesRemaining += pxLink->xBlockSize;
+ traceFREE( pv, pxLink->xBlockSize );
+ prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+ }
+ secureportENABLE_NON_SECURE_INTERRUPTS();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+ return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetMinimumEverFreeHeapSize( void )
+{
+ return xMinimumEverFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM23/secure/secure_heap.h b/portable/GCC/ARM_CM23/secure/secure_heap.h
index bd42ff9..c13590f 100644
--- a/portable/GCC/ARM_CM23/secure/secure_heap.h
+++ b/portable/GCC/ARM_CM23/secure/secure_heap.h
@@ -1,66 +1,66 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef __SECURE_HEAP_H__
-#define __SECURE_HEAP_H__
-
-/* Standard includes. */
-#include <stdlib.h>
-
-/**
- * @brief Allocates memory from heap.
- *
- * @param[in] xWantedSize The size of the memory to be allocated.
- *
- * @return Pointer to the memory region if the allocation is successful, NULL
- * otherwise.
- */
-void * pvPortMalloc( size_t xWantedSize );
-
-/**
- * @brief Frees the previously allocated memory.
- *
- * @param[in] pv Pointer to the memory to be freed.
- */
-void vPortFree( void * pv );
-
-/**
- * @brief Get the free heap size.
- *
- * @return Free heap size.
- */
-size_t xPortGetFreeHeapSize( void );
-
-/**
- * @brief Get the minimum ever free heap size.
- *
- * @return Minimum ever free heap size.
- */
-size_t xPortGetMinimumEverFreeHeapSize( void );
-
-#endif /* __SECURE_HEAP_H__ */
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef __SECURE_HEAP_H__
+#define __SECURE_HEAP_H__
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/**
+ * @brief Allocates memory from heap.
+ *
+ * @param[in] xWantedSize The size of the memory to be allocated.
+ *
+ * @return Pointer to the memory region if the allocation is successful, NULL
+ * otherwise.
+ */
+void * pvPortMalloc( size_t xWantedSize );
+
+/**
+ * @brief Frees the previously allocated memory.
+ *
+ * @param[in] pv Pointer to the memory to be freed.
+ */
+void vPortFree( void * pv );
+
+/**
+ * @brief Get the free heap size.
+ *
+ * @return Free heap size.
+ */
+size_t xPortGetFreeHeapSize( void );
+
+/**
+ * @brief Get the minimum ever free heap size.
+ *
+ * @return Minimum ever free heap size.
+ */
+size_t xPortGetMinimumEverFreeHeapSize( void );
+
+#endif /* __SECURE_HEAP_H__ */
diff --git a/portable/GCC/ARM_CM23/secure/secure_init.c b/portable/GCC/ARM_CM23/secure/secure_init.c
index d91695b..dc19ebc 100644
--- a/portable/GCC/ARM_CM23/secure/secure_init.c
+++ b/portable/GCC/ARM_CM23/secure/secure_init.c
@@ -1,106 +1,106 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/* Standard includes. */
-#include <stdint.h>
-
-/* Secure init includes. */
-#include "secure_init.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/**
- * @brief Constants required to manipulate the SCB.
- */
-#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */
-#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL )
-#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )
-#define secureinitSCB_AIRCR_PRIS_POS ( 14UL )
-#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS )
-
-/**
- * @brief Constants required to manipulate the FPU.
- */
-#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
-#define secureinitFPCCR_LSPENS_POS ( 29UL )
-#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS )
-#define secureinitFPCCR_TS_POS ( 26UL )
-#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS )
-
-#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */
-#define secureinitNSACR_CP10_POS ( 10UL )
-#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS )
-#define secureinitNSACR_CP11_POS ( 11UL )
-#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS )
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )
-{
- uint32_t ulIPSR;
-
- /* Read the Interrupt Program Status Register (IPSR) value. */
- secureportREAD_IPSR( ulIPSR );
-
- /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
- * when the processor is running in the Thread Mode. */
- if( ulIPSR != 0 )
- {
- *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |
- ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |
- ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK );
- }
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
-{
- uint32_t ulIPSR;
-
- /* Read the Interrupt Program Status Register (IPSR) value. */
- secureportREAD_IPSR( ulIPSR );
-
- /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
- * when the processor is running in the Thread Mode. */
- if( ulIPSR != 0 )
- {
- /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is
- * permitted. CP11 should be programmed to the same value as CP10. */
- *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
-
- /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
- * that we can enable/disable lazy stacking in port.c file. */
- *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );
-
- /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP
- * registers (S16-S31) are also pushed to stack on exception entry and
- * restored on exception return. */
- *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );
- }
-}
-/*-----------------------------------------------------------*/
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Secure init includes. */
+#include "secure_init.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */
+#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL )
+#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )
+#define secureinitSCB_AIRCR_PRIS_POS ( 14UL )
+#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS )
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
+#define secureinitFPCCR_LSPENS_POS ( 29UL )
+#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS )
+#define secureinitFPCCR_TS_POS ( 26UL )
+#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS )
+
+#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */
+#define secureinitNSACR_CP10_POS ( 10UL )
+#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS )
+#define secureinitNSACR_CP11_POS ( 11UL )
+#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS )
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )
+{
+ uint32_t ulIPSR;
+
+ /* Read the Interrupt Program Status Register (IPSR) value. */
+ secureportREAD_IPSR( ulIPSR );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode. */
+ if( ulIPSR != 0 )
+ {
+ *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |
+ ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |
+ ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK );
+ }
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
+{
+ uint32_t ulIPSR;
+
+ /* Read the Interrupt Program Status Register (IPSR) value. */
+ secureportREAD_IPSR( ulIPSR );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode. */
+ if( ulIPSR != 0 )
+ {
+ /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is
+ * permitted. CP11 should be programmed to the same value as CP10. */
+ *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
+
+ /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
+ * that we can enable/disable lazy stacking in port.c file. */
+ *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );
+
+ /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP
+ * registers (S16-S31) are also pushed to stack on exception entry and
+ * restored on exception return. */
+ *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );
+ }
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM23/secure/secure_init.h b/portable/GCC/ARM_CM23/secure/secure_init.h
index e18ba44..21daeda 100644
--- a/portable/GCC/ARM_CM23/secure/secure_init.h
+++ b/portable/GCC/ARM_CM23/secure/secure_init.h
@@ -1,54 +1,54 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef __SECURE_INIT_H__
-#define __SECURE_INIT_H__
-
-/**
- * @brief De-prioritizes the non-secure exceptions.
- *
- * This is needed to ensure that the non-secure PendSV runs at the lowest
- * priority. Context switch is done in the non-secure PendSV handler.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- */
-void SecureInit_DePrioritizeNSExceptions( void );
-
-/**
- * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.
- *
- * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point
- * Registers are not leaked to the non-secure side.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- */
-void SecureInit_EnableNSFPUAccess( void );
-
-#endif /* __SECURE_INIT_H__ */
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef __SECURE_INIT_H__
+#define __SECURE_INIT_H__
+
+/**
+ * @brief De-prioritizes the non-secure exceptions.
+ *
+ * This is needed to ensure that the non-secure PendSV runs at the lowest
+ * priority. Context switch is done in the non-secure PendSV handler.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_DePrioritizeNSExceptions( void );
+
+/**
+ * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.
+ *
+ * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point
+ * Registers are not leaked to the non-secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_EnableNSFPUAccess( void );
+
+#endif /* __SECURE_INIT_H__ */
diff --git a/portable/GCC/ARM_CM23/secure/secure_port_macros.h b/portable/GCC/ARM_CM23/secure/secure_port_macros.h
index 5499054..304913b 100644
--- a/portable/GCC/ARM_CM23/secure/secure_port_macros.h
+++ b/portable/GCC/ARM_CM23/secure/secure_port_macros.h
@@ -1,140 +1,140 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef __SECURE_PORT_MACROS_H__
-#define __SECURE_PORT_MACROS_H__
-
-/**
- * @brief Byte alignment requirements.
- */
-#define secureportBYTE_ALIGNMENT 8
-#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 )
-
-/**
- * @brief Macro to declare a function as non-secure callable.
- */
-#if defined( __IAR_SYSTEMS_ICC__ )
- #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry __root
-#else
- #define secureportNON_SECURE_CALLABLE __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) )
-#endif
-
-/**
- * @brief Set the secure PRIMASK value.
- */
-#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \
- __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )
-
-/**
- * @brief Set the non-secure PRIMASK value.
- */
-#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \
- __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )
-
-/**
- * @brief Read the PSP value in the given variable.
- */
-#define secureportREAD_PSP( pucOutCurrentStackPointer ) \
- __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) )
-
-/**
- * @brief Set the PSP to the given value.
- */
-#define secureportSET_PSP( pucCurrentStackPointer ) \
- __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )
-
-/**
- * @brief Read the PSPLIM value in the given variable.
- */
-#define secureportREAD_PSPLIM( pucOutStackLimit ) \
- __asm volatile ( "mrs %0, psplim" : "=r" ( pucOutStackLimit ) )
-
-/**
- * @brief Set the PSPLIM to the given value.
- */
-#define secureportSET_PSPLIM( pucStackLimit ) \
- __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )
-
-/**
- * @brief Set the NonSecure MSP to the given value.
- */
-#define secureportSET_MSP_NS( pucMainStackPointer ) \
- __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )
-
-/**
- * @brief Set the CONTROL register to the given value.
- */
-#define secureportSET_CONTROL( ulControl ) \
- __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )
-
-/**
- * @brief Read the Interrupt Program Status Register (IPSR) value in the given
- * variable.
- */
-#define secureportREAD_IPSR( ulIPSR ) \
- __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) )
-
-/**
- * @brief PRIMASK value to enable interrupts.
- */
-#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0
-
-/**
- * @brief PRIMASK value to disable interrupts.
- */
-#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1
-
-/**
- * @brief Disable secure interrupts.
- */
-#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
-
-/**
- * @brief Disable non-secure interrupts.
- *
- * This effectively disables context switches.
- */
-#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
-
-/**
- * @brief Enable non-secure interrupts.
- */
-#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )
-
-/**
- * @brief Assert definition.
- */
-#define secureportASSERT( x ) \
- if( ( x ) == 0 ) \
- { \
- secureportDISABLE_SECURE_INTERRUPTS(); \
- secureportDISABLE_NON_SECURE_INTERRUPTS(); \
- for( ; ; ) {; } \
- }
-
-#endif /* __SECURE_PORT_MACROS_H__ */
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef __SECURE_PORT_MACROS_H__
+#define __SECURE_PORT_MACROS_H__
+
+/**
+ * @brief Byte alignment requirements.
+ */
+#define secureportBYTE_ALIGNMENT 8
+#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 )
+
+/**
+ * @brief Macro to declare a function as non-secure callable.
+ */
+#if defined( __IAR_SYSTEMS_ICC__ )
+ #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry __root
+#else
+ #define secureportNON_SECURE_CALLABLE __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) )
+#endif
+
+/**
+ * @brief Set the secure PRIMASK value.
+ */
+#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \
+ __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Set the non-secure PRIMASK value.
+ */
+#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \
+ __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Read the PSP value in the given variable.
+ */
+#define secureportREAD_PSP( pucOutCurrentStackPointer ) \
+ __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSP to the given value.
+ */
+#define secureportSET_PSP( pucCurrentStackPointer ) \
+ __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )
+
+/**
+ * @brief Read the PSPLIM value in the given variable.
+ */
+#define secureportREAD_PSPLIM( pucOutStackLimit ) \
+ __asm volatile ( "mrs %0, psplim" : "=r" ( pucOutStackLimit ) )
+
+/**
+ * @brief Set the PSPLIM to the given value.
+ */
+#define secureportSET_PSPLIM( pucStackLimit ) \
+ __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )
+
+/**
+ * @brief Set the NonSecure MSP to the given value.
+ */
+#define secureportSET_MSP_NS( pucMainStackPointer ) \
+ __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )
+
+/**
+ * @brief Set the CONTROL register to the given value.
+ */
+#define secureportSET_CONTROL( ulControl ) \
+ __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )
+
+/**
+ * @brief Read the Interrupt Program Status Register (IPSR) value in the given
+ * variable.
+ */
+#define secureportREAD_IPSR( ulIPSR ) \
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) )
+
+/**
+ * @brief PRIMASK value to enable interrupts.
+ */
+#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0
+
+/**
+ * @brief PRIMASK value to disable interrupts.
+ */
+#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1
+
+/**
+ * @brief Disable secure interrupts.
+ */
+#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Disable non-secure interrupts.
+ *
+ * This effectively disables context switches.
+ */
+#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Enable non-secure interrupts.
+ */
+#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Assert definition.
+ */
+#define secureportASSERT( x ) \
+ if( ( x ) == 0 ) \
+ { \
+ secureportDISABLE_SECURE_INTERRUPTS(); \
+ secureportDISABLE_NON_SECURE_INTERRUPTS(); \
+ for( ; ; ) {; } \
+ }
+
+#endif /* __SECURE_PORT_MACROS_H__ */
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c
index 40141b4..7fb7b5a 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c
@@ -1,381 +1,381 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/* Standard includes. */
-#include <stdint.h>
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
- * is defined correctly and privileged functions are placed in correct sections. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Portasm includes. */
-#include "portasm.h"
-
-/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
- * header files. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#if ( configENABLE_FPU == 1 )
- #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
-#endif
-
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " ldr r2, pxCurrentTCBConst2 \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r2] \n"/* Read pxCurrentTCB. */
- " ldr r0, [r1] \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
- " \n"
- #if ( configENABLE_MPU == 1 )
- " dmb \n"/* Complete outstanding transfers before disabling MPU. */
- " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
- " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */
- " movs r4, #1 \n"/* r4 = 1. */
- " bics r3, r4 \n"/* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */
- " str r3, [r2] \n"/* Disable MPU. */
- " \n"
- " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
- " ldr r4, [r1] \n"/* r4 = *r1 i.e. r4 = MAIR0. */
- " ldr r2, xMAIR0Const2 \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
- " str r4, [r2] \n"/* Program MAIR0. */
- " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
- " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
- " movs r4, #4 \n"/* r4 = 4. */
- " str r4, [r2] \n"/* Program RNR = 4. */
- " ldmia r1!, {r5,r6} \n"/* Read first set of RBAR/RLAR from TCB. */
- " ldr r3, xRBARConst2 \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
- " stmia r3!, {r5,r6} \n"/* Write first set of RBAR/RLAR registers. */
- " movs r4, #5 \n"/* r4 = 5. */
- " str r4, [r2] \n"/* Program RNR = 5. */
- " ldmia r1!, {r5,r6} \n"/* Read second set of RBAR/RLAR from TCB. */
- " ldr r3, xRBARConst2 \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
- " stmia r3!, {r5,r6} \n"/* Write second set of RBAR/RLAR registers. */
- " movs r4, #6 \n"/* r4 = 6. */
- " str r4, [r2] \n"/* Program RNR = 6. */
- " ldmia r1!, {r5,r6} \n"/* Read third set of RBAR/RLAR from TCB. */
- " ldr r3, xRBARConst2 \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
- " stmia r3!, {r5,r6} \n"/* Write third set of RBAR/RLAR registers. */
- " movs r4, #7 \n"/* r4 = 7. */
- " str r4, [r2] \n"/* Program RNR = 7. */
- " ldmia r1!, {r5,r6} \n"/* Read fourth set of RBAR/RLAR from TCB. */
- " ldr r3, xRBARConst2 \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
- " stmia r3!, {r5,r6} \n"/* Write fourth set of RBAR/RLAR registers. */
- " \n"
- " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
- " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */
- " movs r4, #1 \n"/* r4 = 1. */
- " orrs r3, r4 \n"/* r3 = r3 | r4 i.e. Set the bit 0 in r3. */
- " str r3, [r2] \n"/* Enable MPU. */
- " dsb \n"/* Force memory writes before continuing. */
- #endif /* configENABLE_MPU */
- " \n"
- #if ( configENABLE_MPU == 1 )
- " ldm r0!, {r1-r3} \n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
- " msr psplim, r1 \n"/* Set this task's PSPLIM value. */
- " msr control, r2 \n"/* Set this task's CONTROL value. */
- " adds r0, #32 \n"/* Discard everything up to r0. */
- " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
- " isb \n"
- " bx r3 \n"/* Finally, branch to EXC_RETURN. */
- #else /* configENABLE_MPU */
- " ldm r0!, {r1-r2} \n"/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
- " msr psplim, r1 \n"/* Set this task's PSPLIM value. */
- " movs r1, #2 \n"/* r1 = 2. */
- " msr CONTROL, r1 \n"/* Switch to use PSP in the thread mode. */
- " adds r0, #32 \n"/* Discard everything up to r0. */
- " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
- " isb \n"
- " bx r2 \n"/* Finally, branch to EXC_RETURN. */
- #endif /* configENABLE_MPU */
- " \n"
- " .align 4 \n"
- "pxCurrentTCBConst2: .word pxCurrentTCB \n"
- #if ( configENABLE_MPU == 1 )
- "xMPUCTRLConst2: .word 0xe000ed94 \n"
- "xMAIR0Const2: .word 0xe000edc0 \n"
- "xRNRConst2: .word 0xe000ed98 \n"
- "xRBARConst2: .word 0xe000ed9c \n"
- #endif /* configENABLE_MPU */
- );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " mrs r0, control \n"/* r0 = CONTROL. */
- " movs r1, #1 \n"/* r1 = 1. */
- " tst r0, r1 \n"/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
- " beq running_privileged \n"/* If the result of previous AND operation was 0, branch. */
- " movs r0, #0 \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
- " bx lr \n"/* Return. */
- " running_privileged: \n"
- " movs r0, #1 \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
- " bx lr \n"/* Return. */
- " \n"
- " .align 4 \n"
- ::: "r0", "r1", "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " mrs r0, control \n"/* Read the CONTROL register. */
- " movs r1, #1 \n"/* r1 = 1. */
- " bics r0, r1 \n"/* Clear the bit 0. */
- " msr control, r0 \n"/* Write back the new CONTROL value. */
- " bx lr \n"/* Return to the caller. */
- ::: "r0", "r1", "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-void vResetPrivilege( void ) /* __attribute__ (( naked )) */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " mrs r0, control \n"/* r0 = CONTROL. */
- " movs r1, #1 \n"/* r1 = 1. */
- " orrs r0, r1 \n"/* r0 = r0 | r1. */
- " msr control, r0 \n"/* CONTROL = r0. */
- " bx lr \n"/* Return to the caller. */
- ::: "r0", "r1", "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " ldr r0, xVTORConst \n"/* Use the NVIC offset register to locate the stack. */
- " ldr r0, [r0] \n"/* Read the VTOR register which gives the address of vector table. */
- " ldr r0, [r0] \n"/* The first entry in vector table is stack pointer. */
- " msr msp, r0 \n"/* Set the MSP back to the start of the stack. */
- " cpsie i \n"/* Globally enable interrupts. */
- " dsb \n"
- " isb \n"
- " svc %0 \n"/* System call to start the first task. */
- " nop \n"
- " \n"
- " .align 4 \n"
- "xVTORConst: .word 0xe000ed08 \n"
- ::"i" ( portSVC_START_SCHEDULER ) : "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " mrs r0, PRIMASK \n"
- " cpsid i \n"
- " bx lr \n"
- ::: "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " msr PRIMASK, r0 \n"
- " bx lr \n"
- ::: "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " mrs r0, psp \n"/* Read PSP in r0. */
- " ldr r2, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r2] \n"/* Read pxCurrentTCB. */
- #if ( configENABLE_MPU == 1 )
- " subs r0, r0, #44 \n"/* Make space for PSPLIM, CONTROL, LR and the remaining registers on the stack. */
- " str r0, [r1] \n"/* Save the new top of stack in TCB. */
- " mrs r1, psplim \n"/* r1 = PSPLIM. */
- " mrs r2, control \n"/* r2 = CONTROL. */
- " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */
- " stmia r0!, {r1-r7} \n"/* Store on the stack - PSPLIM, CONTROL, LR and low registers that are not automatically saved. */
- " mov r4, r8 \n"/* r4 = r8. */
- " mov r5, r9 \n"/* r5 = r9. */
- " mov r6, r10 \n"/* r6 = r10. */
- " mov r7, r11 \n"/* r7 = r11. */
- " stmia r0!, {r4-r7} \n"/* Store the high registers that are not saved automatically. */
- #else /* configENABLE_MPU */
- " subs r0, r0, #40 \n"/* Make space for PSPLIM, LR and the remaining registers on the stack. */
- " str r0, [r1] \n"/* Save the new top of stack in TCB. */
- " mrs r2, psplim \n"/* r2 = PSPLIM. */
- " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */
- " stmia r0!, {r2-r7} \n"/* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */
- " mov r4, r8 \n"/* r4 = r8. */
- " mov r5, r9 \n"/* r5 = r9. */
- " mov r6, r10 \n"/* r6 = r10. */
- " mov r7, r11 \n"/* r7 = r11. */
- " stmia r0!, {r4-r7} \n"/* Store the high registers that are not saved automatically. */
- #endif /* configENABLE_MPU */
- " \n"
- " cpsid i \n"
- " bl vTaskSwitchContext \n"
- " cpsie i \n"
- " \n"
- " ldr r2, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r2] \n"/* Read pxCurrentTCB. */
- " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
- " \n"
- #if ( configENABLE_MPU == 1 )
- " dmb \n"/* Complete outstanding transfers before disabling MPU. */
- " ldr r2, xMPUCTRLConst \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
- " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */
- " movs r4, #1 \n"/* r4 = 1. */
- " bics r3, r4 \n"/* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */
- " str r3, [r2] \n"/* Disable MPU. */
- " \n"
- " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
- " ldr r4, [r1] \n"/* r4 = *r1 i.e. r4 = MAIR0. */
- " ldr r2, xMAIR0Const \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
- " str r4, [r2] \n"/* Program MAIR0. */
- " ldr r2, xRNRConst \n"/* r2 = 0xe000ed98 [Location of RNR]. */
- " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
- " movs r4, #4 \n"/* r4 = 4. */
- " str r4, [r2] \n"/* Program RNR = 4. */
- " ldmia r1!, {r5,r6} \n"/* Read first set of RBAR/RLAR from TCB. */
- " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
- " stmia r3!, {r5,r6} \n"/* Write first set of RBAR/RLAR registers. */
- " movs r4, #5 \n"/* r4 = 5. */
- " str r4, [r2] \n"/* Program RNR = 5. */
- " ldmia r1!, {r5,r6} \n"/* Read second set of RBAR/RLAR from TCB. */
- " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
- " stmia r3!, {r5,r6} \n"/* Write second set of RBAR/RLAR registers. */
- " movs r4, #6 \n"/* r4 = 6. */
- " str r4, [r2] \n"/* Program RNR = 6. */
- " ldmia r1!, {r5,r6} \n"/* Read third set of RBAR/RLAR from TCB. */
- " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
- " stmia r3!, {r5,r6} \n"/* Write third set of RBAR/RLAR registers. */
- " movs r4, #7 \n"/* r4 = 7. */
- " str r4, [r2] \n"/* Program RNR = 7. */
- " ldmia r1!, {r5,r6} \n"/* Read fourth set of RBAR/RLAR from TCB. */
- " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
- " stmia r3!, {r5,r6} \n"/* Write fourth set of RBAR/RLAR registers. */
- " \n"
- " ldr r2, xMPUCTRLConst \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
- " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */
- " movs r4, #1 \n"/* r4 = 1. */
- " orrs r3, r4 \n"/* r3 = r3 | r4 i.e. Set the bit 0 in r3. */
- " str r3, [r2] \n"/* Enable MPU. */
- " dsb \n"/* Force memory writes before continuing. */
- #endif /* configENABLE_MPU */
- " \n"
- #if ( configENABLE_MPU == 1 )
- " adds r0, r0, #28 \n"/* Move to the high registers. */
- " ldmia r0!, {r4-r7} \n"/* Restore the high registers that are not automatically restored. */
- " mov r8, r4 \n"/* r8 = r4. */
- " mov r9, r5 \n"/* r9 = r5. */
- " mov r10, r6 \n"/* r10 = r6. */
- " mov r11, r7 \n"/* r11 = r7. */
- " msr psp, r0 \n"/* Remember the new top of stack for the task. */
- " subs r0, r0, #44 \n"/* Move to the starting of the saved context. */
- " ldmia r0!, {r1-r7} \n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r7 restored. */
- " msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */
- " msr control, r2 \n"/* Restore the CONTROL register value for the task. */
- " bx r3 \n"
- #else /* configENABLE_MPU */
- " adds r0, r0, #24 \n"/* Move to the high registers. */
- " ldmia r0!, {r4-r7} \n"/* Restore the high registers that are not automatically restored. */
- " mov r8, r4 \n"/* r8 = r4. */
- " mov r9, r5 \n"/* r9 = r5. */
- " mov r10, r6 \n"/* r10 = r6. */
- " mov r11, r7 \n"/* r11 = r7. */
- " msr psp, r0 \n"/* Remember the new top of stack for the task. */
- " subs r0, r0, #40 \n"/* Move to the starting of the saved context. */
- " ldmia r0!, {r2-r7} \n"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */
- " msr psplim, r2 \n"/* Restore the PSPLIM register value for the task. */
- " bx r3 \n"
- #endif /* configENABLE_MPU */
- " \n"
- " .align 4 \n"
- "pxCurrentTCBConst: .word pxCurrentTCB \n"
- #if ( configENABLE_MPU == 1 )
- "xMPUCTRLConst: .word 0xe000ed94 \n"
- "xMAIR0Const: .word 0xe000edc0 \n"
- "xRNRConst: .word 0xe000ed98 \n"
- "xRBARConst: .word 0xe000ed9c \n"
- #endif /* configENABLE_MPU */
- );
-}
-/*-----------------------------------------------------------*/
-
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " movs r0, #4 \n"
- " mov r1, lr \n"
- " tst r0, r1 \n"
- " beq stacking_used_msp \n"
- " mrs r0, psp \n"
- " ldr r2, svchandler_address_const \n"
- " bx r2 \n"
- " stacking_used_msp: \n"
- " mrs r0, msp \n"
- " ldr r2, svchandler_address_const \n"
- " bx r2 \n"
- " \n"
- " .align 4 \n"
- "svchandler_address_const: .word vPortSVCHandler_C \n"
- );
-}
-/*-----------------------------------------------------------*/
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
+ * is defined correctly and privileged functions are placed in correct sections. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Portasm includes. */
+#include "portasm.h"
+
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
+ * header files. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#if ( configENABLE_FPU == 1 )
+ #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
+#endif
+
+void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " ldr r2, pxCurrentTCBConst2 \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r2] \n"/* Read pxCurrentTCB. */
+ " ldr r0, [r1] \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+ " \n"
+ #if ( configENABLE_MPU == 1 )
+ " dmb \n"/* Complete outstanding transfers before disabling MPU. */
+ " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */
+ " movs r4, #1 \n"/* r4 = 1. */
+ " bics r3, r4 \n"/* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */
+ " str r3, [r2] \n"/* Disable MPU. */
+ " \n"
+ " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+ " ldr r4, [r1] \n"/* r4 = *r1 i.e. r4 = MAIR0. */
+ " ldr r2, xMAIR0Const2 \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
+ " str r4, [r2] \n"/* Program MAIR0. */
+ " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
+ " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+ " movs r4, #4 \n"/* r4 = 4. */
+ " str r4, [r2] \n"/* Program RNR = 4. */
+ " ldmia r1!, {r5,r6} \n"/* Read first set of RBAR/RLAR from TCB. */
+ " ldr r3, xRBARConst2 \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+ " stmia r3!, {r5,r6} \n"/* Write first set of RBAR/RLAR registers. */
+ " movs r4, #5 \n"/* r4 = 5. */
+ " str r4, [r2] \n"/* Program RNR = 5. */
+ " ldmia r1!, {r5,r6} \n"/* Read second set of RBAR/RLAR from TCB. */
+ " ldr r3, xRBARConst2 \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+ " stmia r3!, {r5,r6} \n"/* Write second set of RBAR/RLAR registers. */
+ " movs r4, #6 \n"/* r4 = 6. */
+ " str r4, [r2] \n"/* Program RNR = 6. */
+ " ldmia r1!, {r5,r6} \n"/* Read third set of RBAR/RLAR from TCB. */
+ " ldr r3, xRBARConst2 \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+ " stmia r3!, {r5,r6} \n"/* Write third set of RBAR/RLAR registers. */
+ " movs r4, #7 \n"/* r4 = 7. */
+ " str r4, [r2] \n"/* Program RNR = 7. */
+ " ldmia r1!, {r5,r6} \n"/* Read fourth set of RBAR/RLAR from TCB. */
+ " ldr r3, xRBARConst2 \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+ " stmia r3!, {r5,r6} \n"/* Write fourth set of RBAR/RLAR registers. */
+ " \n"
+ " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */
+ " movs r4, #1 \n"/* r4 = 1. */
+ " orrs r3, r4 \n"/* r3 = r3 | r4 i.e. Set the bit 0 in r3. */
+ " str r3, [r2] \n"/* Enable MPU. */
+ " dsb \n"/* Force memory writes before continuing. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ #if ( configENABLE_MPU == 1 )
+ " ldm r0!, {r1-r3} \n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
+ " msr psplim, r1 \n"/* Set this task's PSPLIM value. */
+ " msr control, r2 \n"/* Set this task's CONTROL value. */
+ " adds r0, #32 \n"/* Discard everything up to r0. */
+ " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
+ " isb \n"
+ " bx r3 \n"/* Finally, branch to EXC_RETURN. */
+ #else /* configENABLE_MPU */
+ " ldm r0!, {r1-r2} \n"/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+ " msr psplim, r1 \n"/* Set this task's PSPLIM value. */
+ " movs r1, #2 \n"/* r1 = 2. */
+ " msr CONTROL, r1 \n"/* Switch to use PSP in the thread mode. */
+ " adds r0, #32 \n"/* Discard everything up to r0. */
+ " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
+ " isb \n"
+ " bx r2 \n"/* Finally, branch to EXC_RETURN. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ " .align 4 \n"
+ "pxCurrentTCBConst2: .word pxCurrentTCB \n"
+ #if ( configENABLE_MPU == 1 )
+ "xMPUCTRLConst2: .word 0xe000ed94 \n"
+ "xMAIR0Const2: .word 0xe000edc0 \n"
+ "xRNRConst2: .word 0xe000ed98 \n"
+ "xRBARConst2: .word 0xe000ed9c \n"
+ #endif /* configENABLE_MPU */
+ );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, control \n"/* r0 = CONTROL. */
+ " movs r1, #1 \n"/* r1 = 1. */
+ " tst r0, r1 \n"/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
+ " beq running_privileged \n"/* If the result of previous AND operation was 0, branch. */
+ " movs r0, #0 \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+ " bx lr \n"/* Return. */
+ " running_privileged: \n"
+ " movs r0, #1 \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+ " bx lr \n"/* Return. */
+ " \n"
+ " .align 4 \n"
+ ::: "r0", "r1", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, control \n"/* Read the CONTROL register. */
+ " movs r1, #1 \n"/* r1 = 1. */
+ " bics r0, r1 \n"/* Clear the bit 0. */
+ " msr control, r0 \n"/* Write back the new CONTROL value. */
+ " bx lr \n"/* Return to the caller. */
+ ::: "r0", "r1", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, control \n"/* r0 = CONTROL. */
+ " movs r1, #1 \n"/* r1 = 1. */
+ " orrs r0, r1 \n"/* r0 = r0 | r1. */
+ " msr control, r0 \n"/* CONTROL = r0. */
+ " bx lr \n"/* Return to the caller. */
+ ::: "r0", "r1", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " ldr r0, xVTORConst \n"/* Use the NVIC offset register to locate the stack. */
+ " ldr r0, [r0] \n"/* Read the VTOR register which gives the address of vector table. */
+ " ldr r0, [r0] \n"/* The first entry in vector table is stack pointer. */
+ " msr msp, r0 \n"/* Set the MSP back to the start of the stack. */
+ " cpsie i \n"/* Globally enable interrupts. */
+ " dsb \n"
+ " isb \n"
+ " svc %0 \n"/* System call to start the first task. */
+ " nop \n"
+ " \n"
+ " .align 4 \n"
+ "xVTORConst: .word 0xe000ed08 \n"
+ ::"i" ( portSVC_START_SCHEDULER ) : "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, PRIMASK \n"
+ " cpsid i \n"
+ " bx lr \n"
+ ::: "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " msr PRIMASK, r0 \n"
+ " bx lr \n"
+ ::: "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, psp \n"/* Read PSP in r0. */
+ " ldr r2, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r2] \n"/* Read pxCurrentTCB. */
+ #if ( configENABLE_MPU == 1 )
+ " subs r0, r0, #44 \n"/* Make space for PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+ " str r0, [r1] \n"/* Save the new top of stack in TCB. */
+ " mrs r1, psplim \n"/* r1 = PSPLIM. */
+ " mrs r2, control \n"/* r2 = CONTROL. */
+ " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */
+ " stmia r0!, {r1-r7} \n"/* Store on the stack - PSPLIM, CONTROL, LR and low registers that are not automatically saved. */
+ " mov r4, r8 \n"/* r4 = r8. */
+ " mov r5, r9 \n"/* r5 = r9. */
+ " mov r6, r10 \n"/* r6 = r10. */
+ " mov r7, r11 \n"/* r7 = r11. */
+ " stmia r0!, {r4-r7} \n"/* Store the high registers that are not saved automatically. */
+ #else /* configENABLE_MPU */
+ " subs r0, r0, #40 \n"/* Make space for PSPLIM, LR and the remaining registers on the stack. */
+ " str r0, [r1] \n"/* Save the new top of stack in TCB. */
+ " mrs r2, psplim \n"/* r2 = PSPLIM. */
+ " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */
+ " stmia r0!, {r2-r7} \n"/* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */
+ " mov r4, r8 \n"/* r4 = r8. */
+ " mov r5, r9 \n"/* r5 = r9. */
+ " mov r6, r10 \n"/* r6 = r10. */
+ " mov r7, r11 \n"/* r7 = r11. */
+ " stmia r0!, {r4-r7} \n"/* Store the high registers that are not saved automatically. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ " cpsid i \n"
+ " bl vTaskSwitchContext \n"
+ " cpsie i \n"
+ " \n"
+ " ldr r2, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r2] \n"/* Read pxCurrentTCB. */
+ " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+ " \n"
+ #if ( configENABLE_MPU == 1 )
+ " dmb \n"/* Complete outstanding transfers before disabling MPU. */
+ " ldr r2, xMPUCTRLConst \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */
+ " movs r4, #1 \n"/* r4 = 1. */
+ " bics r3, r4 \n"/* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */
+ " str r3, [r2] \n"/* Disable MPU. */
+ " \n"
+ " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+ " ldr r4, [r1] \n"/* r4 = *r1 i.e. r4 = MAIR0. */
+ " ldr r2, xMAIR0Const \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
+ " str r4, [r2] \n"/* Program MAIR0. */
+ " ldr r2, xRNRConst \n"/* r2 = 0xe000ed98 [Location of RNR]. */
+ " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+ " movs r4, #4 \n"/* r4 = 4. */
+ " str r4, [r2] \n"/* Program RNR = 4. */
+ " ldmia r1!, {r5,r6} \n"/* Read first set of RBAR/RLAR from TCB. */
+ " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+ " stmia r3!, {r5,r6} \n"/* Write first set of RBAR/RLAR registers. */
+ " movs r4, #5 \n"/* r4 = 5. */
+ " str r4, [r2] \n"/* Program RNR = 5. */
+ " ldmia r1!, {r5,r6} \n"/* Read second set of RBAR/RLAR from TCB. */
+ " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+ " stmia r3!, {r5,r6} \n"/* Write second set of RBAR/RLAR registers. */
+ " movs r4, #6 \n"/* r4 = 6. */
+ " str r4, [r2] \n"/* Program RNR = 6. */
+ " ldmia r1!, {r5,r6} \n"/* Read third set of RBAR/RLAR from TCB. */
+ " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+ " stmia r3!, {r5,r6} \n"/* Write third set of RBAR/RLAR registers. */
+ " movs r4, #7 \n"/* r4 = 7. */
+ " str r4, [r2] \n"/* Program RNR = 7. */
+ " ldmia r1!, {r5,r6} \n"/* Read fourth set of RBAR/RLAR from TCB. */
+ " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+ " stmia r3!, {r5,r6} \n"/* Write fourth set of RBAR/RLAR registers. */
+ " \n"
+ " ldr r2, xMPUCTRLConst \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */
+ " movs r4, #1 \n"/* r4 = 1. */
+ " orrs r3, r4 \n"/* r3 = r3 | r4 i.e. Set the bit 0 in r3. */
+ " str r3, [r2] \n"/* Enable MPU. */
+ " dsb \n"/* Force memory writes before continuing. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ #if ( configENABLE_MPU == 1 )
+ " adds r0, r0, #28 \n"/* Move to the high registers. */
+ " ldmia r0!, {r4-r7} \n"/* Restore the high registers that are not automatically restored. */
+ " mov r8, r4 \n"/* r8 = r4. */
+ " mov r9, r5 \n"/* r9 = r5. */
+ " mov r10, r6 \n"/* r10 = r6. */
+ " mov r11, r7 \n"/* r11 = r7. */
+ " msr psp, r0 \n"/* Remember the new top of stack for the task. */
+ " subs r0, r0, #44 \n"/* Move to the starting of the saved context. */
+ " ldmia r0!, {r1-r7} \n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r7 restored. */
+ " msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */
+ " msr control, r2 \n"/* Restore the CONTROL register value for the task. */
+ " bx r3 \n"
+ #else /* configENABLE_MPU */
+ " adds r0, r0, #24 \n"/* Move to the high registers. */
+ " ldmia r0!, {r4-r7} \n"/* Restore the high registers that are not automatically restored. */
+ " mov r8, r4 \n"/* r8 = r4. */
+ " mov r9, r5 \n"/* r9 = r5. */
+ " mov r10, r6 \n"/* r10 = r6. */
+ " mov r11, r7 \n"/* r11 = r7. */
+ " msr psp, r0 \n"/* Remember the new top of stack for the task. */
+ " subs r0, r0, #40 \n"/* Move to the starting of the saved context. */
+ " ldmia r0!, {r2-r7} \n"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */
+ " msr psplim, r2 \n"/* Restore the PSPLIM register value for the task. */
+ " bx r3 \n"
+ #endif /* configENABLE_MPU */
+ " \n"
+ " .align 4 \n"
+ "pxCurrentTCBConst: .word pxCurrentTCB \n"
+ #if ( configENABLE_MPU == 1 )
+ "xMPUCTRLConst: .word 0xe000ed94 \n"
+ "xMAIR0Const: .word 0xe000edc0 \n"
+ "xRNRConst: .word 0xe000ed98 \n"
+ "xRBARConst: .word 0xe000ed9c \n"
+ #endif /* configENABLE_MPU */
+ );
+}
+/*-----------------------------------------------------------*/
+
+void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " movs r0, #4 \n"
+ " mov r1, lr \n"
+ " tst r0, r1 \n"
+ " beq stacking_used_msp \n"
+ " mrs r0, psp \n"
+ " ldr r2, svchandler_address_const \n"
+ " bx r2 \n"
+ " stacking_used_msp: \n"
+ " mrs r0, msp \n"
+ " ldr r2, svchandler_address_const \n"
+ " bx r2 \n"
+ " \n"
+ " .align 4 \n"
+ "svchandler_address_const: .word vPortSVCHandler_C \n"
+ );
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h b/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h
index b37f6d1..ecd86b9 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h
@@ -1,114 +1,114 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef __PORT_ASM_H__
-#define __PORT_ASM_H__
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-
-/* MPU wrappers includes. */
-#include "mpu_wrappers.h"
-
-/**
- * @brief Restore the context of the first task so that the first task starts
- * executing.
- */
-void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
-BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
-
-/**
- * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
- * register.
- *
- * @note This is a privileged function and should only be called from the kenrel
- * code.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- * Bit[0] = 0 --> The processor is running privileged
- * Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- * Bit[0] = 0 --> The processor is running privileged
- * Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vResetPrivilege( void ) __attribute__( ( naked ) );
-
-/**
- * @brief Starts the first task.
- */
-void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Disables interrupts.
- */
-uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Enables interrupts.
- */
-void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief PendSV Exception handler.
- */
-void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief SVC Handler.
- */
-void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Allocate a Secure context for the calling task.
- *
- * @param[in] ulSecureStackSize The size of the stack to be allocated on the
- * secure side for the calling task.
- */
-void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );
-
-/**
- * @brief Free the task's secure context.
- *
- * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
- */
-void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-#endif /* __PORT_ASM_H__ */
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
index 3486481..f98b8f2 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
@@ -1,71 +1,71 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "portmacrocommon.h"
-
-/*------------------------------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *------------------------------------------------------------------------------
- */
-
-/**
- * Architecture specifics.
- */
-#define portARCH_NAME "Cortex-M23"
-#define portDONT_DISCARD __attribute__( ( used ) )
-/*-----------------------------------------------------------*/
-
-#if( configTOTAL_MPU_REGIONS == 16 )
- #error 16 MPU regions are not yet supported for this port.
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Critical section management.
- */
-#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
-#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )
-/*-----------------------------------------------------------*/
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* PORTMACRO_H */
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "portmacrocommon.h"
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME "Cortex-M23"
+#define portDONT_DISCARD __attribute__( ( used ) )
+/*-----------------------------------------------------------*/
+
+#if( configTOTAL_MPU_REGIONS == 16 )
+ #error 16 MPU regions are not yet supported for this port.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
index 4b1f99b..51e21ea 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
@@ -155,9 +155,9 @@
* 8-bit values encoded as follows:
* Bit[7:4] - 0000 - Device Memory
* Bit[3:2] - 00 --> Device-nGnRnE
- * 01 --> Device-nGnRE
- * 10 --> Device-nGRE
- * 11 --> Device-GRE
+ * 01 --> Device-nGnRE
+ * 10 --> Device-nGRE
+ * 11 --> Device-GRE
* Bit[1:0] - 00, Reserved.
*/
#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
diff --git a/portable/GCC/ARM_CM3/port.c b/portable/GCC/ARM_CM3/port.c
index f41f215..7f650fd 100644
--- a/portable/GCC/ARM_CM3/port.c
+++ b/portable/GCC/ARM_CM3/port.c
@@ -1,761 +1,761 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the ARM CM3 port.
-*----------------------------------------------------------*/
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is
- * defined. The value should also ensure backward compatibility.
- * FreeRTOS.org versions prior to V4.4.0 did not include this definition. */
-#ifndef configKERNEL_INTERRUPT_PRIORITY
- #define configKERNEL_INTERRUPT_PRIORITY 255
-#endif
-
-/* Constants required to manipulate the core. Registers first... */
-#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
-#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
-#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
-#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
-/* ...then bits in the registers. */
-#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
-#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
-#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
-#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
-#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
-#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
-#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
-
-#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
-
-/* Constants required to check the validity of an interrupt priority. */
-#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
-#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
-#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
-#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
-#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
-#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
-#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
-#define portPRIGROUP_SHIFT ( 8UL )
-
-/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
-#define portVECTACTIVE_MASK ( 0xFFUL )
-
-/* Constants required to set up the initial stack. */
-#define portINITIAL_XPSR ( 0x01000000UL )
-
-/* The systick is a 24-bit counter. */
-#define portMAX_24_BIT_NUMBER ( 0xffffffUL )
-
-/* A fiddle factor to estimate the number of SysTick counts that would have
- * occurred while the SysTick counter is stopped during tickless idle
- * calculations. */
-#define portMISSED_COUNTS_FACTOR ( 94UL )
-
-/* For strict compliance with the Cortex-M spec the task start address should
- * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
-#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
-
-/* Let the user override the default SysTick clock rate. If defined by the
- * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
- * configuration register. */
-#ifndef configSYSTICK_CLOCK_HZ
- #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ )
- /* Ensure the SysTick is clocked at the same frequency as the core. */
- #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT )
-#else
- /* Select the option to clock SysTick not at the same frequency as the core. */
- #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 )
-#endif
-
-/* Let the user override the pre-loading of the initial LR with the address of
- * prvTaskExitError() in case it messes up unwinding of the stack in the
- * debugger. */
-#ifdef configTASK_RETURN_ADDRESS
- #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
-#else
- #define portTASK_RETURN_ADDRESS prvTaskExitError
-#endif
-
-/*
- * Setup the timer to generate the tick interrupts. The implementation in this
- * file is weak to allow application writers to change the timer used to
- * generate the tick interrupt.
- */
-void vPortSetupTimerInterrupt( void );
-
-/*
- * Exception handlers.
- */
-void xPortPendSVHandler( void ) __attribute__( ( naked ) );
-void xPortSysTickHandler( void );
-void vPortSVCHandler( void ) __attribute__( ( naked ) );
-
-/*
- * Start first task is a separate function so it can be tested in isolation.
- */
-static void prvPortStartFirstTask( void ) __attribute__( ( naked ) );
-
-/*
- * Used to catch tasks that attempt to return from their implementing function.
- */
-static void prvTaskExitError( void );
-
-/*-----------------------------------------------------------*/
-
-/* Each task maintains its own interrupt status in the critical nesting
- * variable. */
-static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
-
-/*
- * The number of SysTick increments that make up one tick period.
- */
-#if ( configUSE_TICKLESS_IDLE == 1 )
- static uint32_t ulTimerCountsForOneTick = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * The maximum number of tick periods that can be suppressed is limited by the
- * 24 bit resolution of the SysTick timer.
- */
-#if ( configUSE_TICKLESS_IDLE == 1 )
- static uint32_t xMaximumPossibleSuppressedTicks = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * Compensate for the CPU cycles that pass while the SysTick is stopped (low
- * power functionality only.
- */
-#if ( configUSE_TICKLESS_IDLE == 1 )
- static uint32_t ulStoppedTimerCompensation = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
- * FreeRTOS API functions are not called from interrupts that have been assigned
- * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
- */
-#if ( configASSERT_DEFINED == 1 )
- static uint8_t ucMaxSysCallPriority = 0;
- static uint32_t ulMaxPRIGROUPValue = 0;
- static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
-#endif /* configASSERT_DEFINED */
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
-{
- /* Simulate the stack frame as it would be created by a context switch
- * interrupt. */
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
- *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
- pxTopOfStack--;
- *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
- pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
-
- return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
- volatile uint32_t ulDummy = 0UL;
-
- /* A function that implements a task must not exit or attempt to return to
- * its caller as there is nothing to return to. If a task wants to exit it
- * should instead call vTaskDelete( NULL ).
- *
- * Artificially force an assert() to be triggered if configASSERT() is
- * defined, then stop here so application writers can catch the error. */
- configASSERT( uxCriticalNesting == ~0UL );
- portDISABLE_INTERRUPTS();
-
- while( ulDummy == 0 )
- {
- /* This file calls prvTaskExitError() after the scheduler has been
- * started to remove a compiler warning about the function being defined
- * but never called. ulDummy is used purely to quieten other warnings
- * about code appearing after this function is called - making ulDummy
- * volatile makes the compiler think the function could return and
- * therefore not output an 'unreachable code' warning for code that appears
- * after it. */
- }
-}
-/*-----------------------------------------------------------*/
-
-void vPortSVCHandler( void )
-{
- __asm volatile (
- " ldr r3, pxCurrentTCBConst2 \n"/* Restore the context. */
- " ldr r1, [r3] \n"/* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
- " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. */
- " ldmia r0!, {r4-r11} \n"/* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
- " msr psp, r0 \n"/* Restore the task stack pointer. */
- " isb \n"
- " mov r0, #0 \n"
- " msr basepri, r0 \n"
- " orr r14, #0xd \n"
- " bx r14 \n"
- " \n"
- " .align 4 \n"
- "pxCurrentTCBConst2: .word pxCurrentTCB \n"
- );
-}
-/*-----------------------------------------------------------*/
-
-static void prvPortStartFirstTask( void )
-{
- __asm volatile (
- " ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */
- " ldr r0, [r0] \n"
- " ldr r0, [r0] \n"
- " msr msp, r0 \n"/* Set the msp back to the start of the stack. */
- " cpsie i \n"/* Globally enable interrupts. */
- " cpsie f \n"
- " dsb \n"
- " isb \n"
- " svc 0 \n"/* System call to start first task. */
- " nop \n"
- " .ltorg \n"
- );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-BaseType_t xPortStartScheduler( void )
-{
- /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
- * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
- configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
-
- #if ( configASSERT_DEFINED == 1 )
- {
- volatile uint32_t ulOriginalPriority;
- volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
- volatile uint8_t ucMaxPriorityValue;
-
- /* Determine the maximum priority from which ISR safe FreeRTOS API
- * functions can be called. ISR safe functions are those that end in
- * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
- * ensure interrupt entry is as fast and simple as possible.
- *
- * Save the interrupt priority value that is about to be clobbered. */
- ulOriginalPriority = *pucFirstUserPriorityRegister;
-
- /* Determine the number of priority bits available. First write to all
- * possible bits. */
- *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
-
- /* Read the value back to see how many bits stuck. */
- ucMaxPriorityValue = *pucFirstUserPriorityRegister;
-
- /* Use the same mask on the maximum system call priority. */
- ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
-
- /* Calculate the maximum acceptable priority group value for the number
- * of bits read back. */
- ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
-
- while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
- {
- ulMaxPRIGROUPValue--;
- ucMaxPriorityValue <<= ( uint8_t ) 0x01;
- }
-
- #ifdef __NVIC_PRIO_BITS
- {
- /* Check the CMSIS configuration that defines the number of
- * priority bits matches the number of priority bits actually queried
- * from the hardware. */
- configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
- }
- #endif
-
- #ifdef configPRIO_BITS
- {
- /* Check the FreeRTOS configuration that defines the number of
- * priority bits matches the number of priority bits actually queried
- * from the hardware. */
- configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
- }
- #endif
-
- /* Shift the priority group value back to its position within the AIRCR
- * register. */
- ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
- ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
- /* Restore the clobbered interrupt priority register to its original
- * value. */
- *pucFirstUserPriorityRegister = ulOriginalPriority;
- }
- #endif /* configASSERT_DEFINED */
-
- /* Make PendSV and SysTick the lowest priority interrupts. */
- portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
- portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
-
- /* Start the timer that generates the tick ISR. Interrupts are disabled
- * here already. */
- vPortSetupTimerInterrupt();
-
- /* Initialise the critical nesting count ready for the first task. */
- uxCriticalNesting = 0;
-
- /* Start the first task. */
- prvPortStartFirstTask();
-
- /* Should never get here as the tasks will now be executing! Call the task
- * exit error function to prevent compiler warnings about a static function
- * not being called in the case that the application writer overrides this
- * functionality by defining configTASK_RETURN_ADDRESS. Call
- * vTaskSwitchContext() so link time optimisation does not remove the
- * symbol. */
- vTaskSwitchContext();
- prvTaskExitError();
-
- /* Should not get here! */
- return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
- /* Not implemented in ports where there is nothing to return to.
- * Artificially force an assert. */
- configASSERT( uxCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
- portDISABLE_INTERRUPTS();
- uxCriticalNesting++;
-
- /* This is not the interrupt safe version of the enter critical function so
- * assert() if it is being called from an interrupt context. Only API
- * functions that end in "FromISR" can be used in an interrupt. Only assert if
- * the critical nesting count is 1 to protect against recursive calls if the
- * assert function also uses a critical section. */
- if( uxCriticalNesting == 1 )
- {
- configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
- }
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
- configASSERT( uxCriticalNesting );
- uxCriticalNesting--;
-
- if( uxCriticalNesting == 0 )
- {
- portENABLE_INTERRUPTS();
- }
-}
-/*-----------------------------------------------------------*/
-
-void xPortPendSVHandler( void )
-{
- /* This is a naked function. */
-
- __asm volatile
- (
- " mrs r0, psp \n"
- " isb \n"
- " \n"
- " ldr r3, pxCurrentTCBConst \n"/* Get the location of the current TCB. */
- " ldr r2, [r3] \n"
- " \n"
- " stmdb r0!, {r4-r11} \n"/* Save the remaining registers. */
- " str r0, [r2] \n"/* Save the new top of stack into the first member of the TCB. */
- " \n"
- " stmdb sp!, {r3, r14} \n"
- " mov r0, %0 \n"
- " msr basepri, r0 \n"
- " bl vTaskSwitchContext \n"
- " mov r0, #0 \n"
- " msr basepri, r0 \n"
- " ldmia sp!, {r3, r14} \n"
- " \n"/* Restore the context, including the critical nesting count. */
- " ldr r1, [r3] \n"
- " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. */
- " ldmia r0!, {r4-r11} \n"/* Pop the registers. */
- " msr psp, r0 \n"
- " isb \n"
- " bx r14 \n"
- " \n"
- " .align 4 \n"
- "pxCurrentTCBConst: .word pxCurrentTCB \n"
- ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
- );
-}
-/*-----------------------------------------------------------*/
-
-void xPortSysTickHandler( void )
-{
- /* The SysTick runs at the lowest interrupt priority, so when this interrupt
- * executes all interrupts must be unmasked. There is therefore no need to
- * save and then restore the interrupt mask value as its value is already
- * known. */
- portDISABLE_INTERRUPTS();
- {
- /* Increment the RTOS tick. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- /* A context switch is required. Context switching is performed in
- * the PendSV interrupt. Pend the PendSV interrupt. */
- portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
- }
- }
- portENABLE_INTERRUPTS();
-}
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TICKLESS_IDLE == 1 )
-
- __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
- {
- uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
- TickType_t xModifiableIdleTime;
-
- /* Make sure the SysTick reload value does not overflow the counter. */
- if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
- {
- xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
- }
-
- /* Enter a critical section but don't use the taskENTER_CRITICAL()
- * method as that will mask interrupts that should exit sleep mode. */
- __asm volatile ( "cpsid i" ::: "memory" );
- __asm volatile ( "dsb" );
- __asm volatile ( "isb" );
-
- /* If a context switch is pending or a task is waiting for the scheduler
- * to be unsuspended then abandon the low power entry. */
- if( eTaskConfirmSleepModeStatus() == eAbortSleep )
- {
- /* Re-enable interrupts - see comments above the cpsid instruction
- * above. */
- __asm volatile ( "cpsie i" ::: "memory" );
- }
- else
- {
- /* Stop the SysTick momentarily. The time the SysTick is stopped for
- * is accounted for as best it can be, but using the tickless mode will
- * inevitably result in some tiny drift of the time maintained by the
- * kernel with respect to calendar time. */
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
-
- /* Use the SysTick current-value register to determine the number of
- * SysTick decrements remaining until the next tick interrupt. If the
- * current-value register is zero, then there are actually
- * ulTimerCountsForOneTick decrements remaining, not zero, because the
- * SysTick requests the interrupt when decrementing from 1 to 0. */
- ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
- if( ulSysTickDecrementsLeft == 0 )
- {
- ulSysTickDecrementsLeft = ulTimerCountsForOneTick;
- }
-
- /* Calculate the reload value required to wait xExpectedIdleTime
- * tick periods. -1 is used because this code normally executes part
- * way through the first tick period. But if the SysTick IRQ is now
- * pending, then clear the IRQ, suppressing the first tick, and correct
- * the reload value to reflect that the second tick period is already
- * underway. The expected idle time is always at least two ticks. */
- ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
-
- if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )
- {
- portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;
- ulReloadValue -= ulTimerCountsForOneTick;
- }
-
- if( ulReloadValue > ulStoppedTimerCompensation )
- {
- ulReloadValue -= ulStoppedTimerCompensation;
- }
-
- /* Set the new reload value. */
- portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
-
- /* Clear the SysTick count flag and set the count value back to
- * zero. */
- portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
- /* Restart SysTick. */
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
- /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
- * set its parameter to 0 to indicate that its implementation contains
- * its own wait for interrupt or wait for event instruction, and so wfi
- * should not be executed again. However, the original expected idle
- * time variable must remain unmodified, so a copy is taken. */
- xModifiableIdleTime = xExpectedIdleTime;
- configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
-
- if( xModifiableIdleTime > 0 )
- {
- __asm volatile ( "dsb" ::: "memory" );
- __asm volatile ( "wfi" );
- __asm volatile ( "isb" );
- }
-
- configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
-
- /* Re-enable interrupts to allow the interrupt that brought the MCU
- * out of sleep mode to execute immediately. See comments above
- * the cpsid instruction above. */
- __asm volatile ( "cpsie i" ::: "memory" );
- __asm volatile ( "dsb" );
- __asm volatile ( "isb" );
-
- /* Disable interrupts again because the clock is about to be stopped
- * and interrupts that execute while the clock is stopped will increase
- * any slippage between the time maintained by the RTOS and calendar
- * time. */
- __asm volatile ( "cpsid i" ::: "memory" );
- __asm volatile ( "dsb" );
- __asm volatile ( "isb" );
-
- /* Disable the SysTick clock without reading the
- * portNVIC_SYSTICK_CTRL_REG register to ensure the
- * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
- * the time the SysTick is stopped for is accounted for as best it can
- * be, but using the tickless mode will inevitably result in some tiny
- * drift of the time maintained by the kernel with respect to calendar
- * time*/
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
-
- /* Determine whether the SysTick has already counted to zero. */
- if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
- {
- uint32_t ulCalculatedLoadValue;
-
- /* The tick interrupt ended the sleep (or is now pending), and
- * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG
- * with whatever remains of the new tick period. */
- ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
-
- /* Don't allow a tiny value, or values that have somehow
- * underflowed because the post sleep hook did something
- * that took too long or because the SysTick current-value register
- * is zero. */
- if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
- {
- ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
- }
-
- portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
-
- /* As the pending tick will be processed as soon as this
- * function exits, the tick value maintained by the tick is stepped
- * forward by one less than the time spent waiting. */
- ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
- }
- else
- {
- /* Something other than the tick interrupt ended the sleep. */
-
- /* Use the SysTick current-value register to determine the
- * number of SysTick decrements remaining until the expected idle
- * time would have ended. */
- ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
- #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )
- {
- /* If the SysTick is not using the core clock, the current-
- * value register might still be zero here. In that case, the
- * SysTick didn't load from the reload register, and there are
- * ulReloadValue decrements remaining in the expected idle
- * time, not zero. */
- if( ulSysTickDecrementsLeft == 0 )
- {
- ulSysTickDecrementsLeft = ulReloadValue;
- }
- }
- #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
-
- /* Work out how long the sleep lasted rounded to complete tick
- * periods (not the ulReload value which accounted for part
- * ticks). */
- ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;
-
- /* How many complete tick periods passed while the processor
- * was waiting? */
- ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
-
- /* The reload value is set to whatever fraction of a single tick
- * period remains. */
- portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
- }
-
- /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,
- * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If
- * the SysTick is not using the core clock, temporarily configure it to
- * use the core clock. This configuration forces the SysTick to load
- * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next
- * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready
- * to receive the standard value immediately. */
- portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
- portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
- #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )
- {
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
- }
- #else
- {
- /* The temporary usage of the core clock has served its purpose,
- * as described above. Resume usage of the other clock. */
- portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
-
- if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
- {
- /* The partial tick period already ended. Be sure the SysTick
- * counts it only once. */
- portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;
- }
-
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
- portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
- }
- #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
-
- /* Step the tick to account for any tick periods that elapsed. */
- vTaskStepTick( ulCompleteTickPeriods );
-
- /* Exit with interrupts enabled. */
- __asm volatile ( "cpsie i" ::: "memory" );
- }
- }
-
-#endif /* configUSE_TICKLESS_IDLE */
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the systick timer to generate the tick interrupts at the required
- * frequency.
- */
-__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
-{
- /* Calculate the constants required to configure the tick interrupt. */
- #if ( configUSE_TICKLESS_IDLE == 1 )
- {
- ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
- xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
- ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
- }
- #endif /* configUSE_TICKLESS_IDLE */
-
- /* Stop and clear the SysTick. */
- portNVIC_SYSTICK_CTRL_REG = 0UL;
- portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
- /* Configure SysTick to interrupt at the requested rate. */
- portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
-}
-/*-----------------------------------------------------------*/
-
-#if ( configASSERT_DEFINED == 1 )
-
- void vPortValidateInterruptPriority( void )
- {
- uint32_t ulCurrentInterrupt;
- uint8_t ucCurrentPriority;
-
- /* Obtain the number of the currently executing interrupt. */
- __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
-
- /* Is the interrupt number a user defined interrupt? */
- if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
- {
- /* Look up the interrupt's priority. */
- ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
-
- /* The following assertion will fail if a service routine (ISR) for
- * an interrupt that has been assigned a priority above
- * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
- * function. ISR safe FreeRTOS API functions must *only* be called
- * from interrupts that have been assigned a priority at or below
- * configMAX_SYSCALL_INTERRUPT_PRIORITY.
- *
- * Numerically low interrupt priority numbers represent logically high
- * interrupt priorities, therefore the priority of the interrupt must
- * be set to a value equal to or numerically *higher* than
- * configMAX_SYSCALL_INTERRUPT_PRIORITY.
- *
- * Interrupts that use the FreeRTOS API must not be left at their
- * default priority of zero as that is the highest possible priority,
- * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
- * and therefore also guaranteed to be invalid.
- *
- * FreeRTOS maintains separate thread and ISR API functions to ensure
- * interrupt entry is as fast and simple as possible.
- *
- * The following links provide detailed information:
- * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
- * https://www.FreeRTOS.org/FAQHelp.html */
- configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
- }
-
- /* Priority grouping: The interrupt controller (NVIC) allows the bits
- * that define each interrupt's priority to be split between bits that
- * define the interrupt's pre-emption priority bits and bits that define
- * the interrupt's sub-priority. For simplicity all bits must be defined
- * to be pre-emption priority bits. The following assertion will fail if
- * this is not the case (if some bits represent a sub-priority).
- *
- * If the application only uses CMSIS libraries for interrupt
- * configuration then the correct setting can be achieved on all Cortex-M
- * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
- * scheduler. Note however that some vendor specific peripheral libraries
- * assume a non-zero priority group setting, in which cases using a value
- * of zero will result in unpredictable behaviour. */
- configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
- }
-
-#endif /* configASSERT_DEFINED */
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*-----------------------------------------------------------
+* Implementation of functions defined in portable.h for the ARM CM3 port.
+*----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is
+ * defined. The value should also ensure backward compatibility.
+ * FreeRTOS.org versions prior to V4.4.0 did not include this definition. */
+#ifndef configKERNEL_INTERRUPT_PRIORITY
+ #define configKERNEL_INTERRUPT_PRIORITY 255
+#endif
+
+/* Constants required to manipulate the core. Registers first... */
+#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
+/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
+#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
+
+#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
+#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT ( 8UL )
+
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK ( 0xFFUL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR ( 0x01000000UL )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER ( 0xffffffUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+ * occurred while the SysTick counter is stopped during tickless idle
+ * calculations. */
+#define portMISSED_COUNTS_FACTOR ( 94UL )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+ * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
+
+/* Let the user override the default SysTick clock rate. If defined by the
+ * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
+ * configuration register. */
+#ifndef configSYSTICK_CLOCK_HZ
+ #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ )
+ /* Ensure the SysTick is clocked at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT )
+#else
+ /* Select the option to clock SysTick not at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 )
+#endif
+
+/* Let the user override the pre-loading of the initial LR with the address of
+ * prvTaskExitError() in case it messes up unwinding of the stack in the
+ * debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
+#else
+ #define portTASK_RETURN_ADDRESS prvTaskExitError
+#endif
+
+/*
+ * Setup the timer to generate the tick interrupts. The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortPendSVHandler( void ) __attribute__( ( naked ) );
+void xPortSysTickHandler( void );
+void vPortSVCHandler( void ) __attribute__( ( naked ) );
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+static void prvPortStartFirstTask( void ) __attribute__( ( naked ) );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+ * variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+ static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+ static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+ static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( configASSERT_DEFINED == 1 )
+ static uint8_t ucMaxSysCallPriority = 0;
+ static uint32_t ulMaxPRIGROUPValue = 0;
+ static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+ TaskFunction_t pxCode,
+ void * pvParameters )
+{
+ /* Simulate the stack frame as it would be created by a context switch
+ * interrupt. */
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+ volatile uint32_t ulDummy = 0UL;
+
+ /* A function that implements a task must not exit or attempt to return to
+ * its caller as there is nothing to return to. If a task wants to exit it
+ * should instead call vTaskDelete( NULL ).
+ *
+ * Artificially force an assert() to be triggered if configASSERT() is
+ * defined, then stop here so application writers can catch the error. */
+ configASSERT( uxCriticalNesting == ~0UL );
+ portDISABLE_INTERRUPTS();
+
+ while( ulDummy == 0 )
+ {
+ /* This file calls prvTaskExitError() after the scheduler has been
+ * started to remove a compiler warning about the function being defined
+ * but never called. ulDummy is used purely to quieten other warnings
+ * about code appearing after this function is called - making ulDummy
+ * volatile makes the compiler think the function could return and
+ * therefore not output an 'unreachable code' warning for code that appears
+ * after it. */
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler( void )
+{
+ __asm volatile (
+ " ldr r3, pxCurrentTCBConst2 \n"/* Restore the context. */
+ " ldr r1, [r3] \n"/* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
+ " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. */
+ " ldmia r0!, {r4-r11} \n"/* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
+ " msr psp, r0 \n"/* Restore the task stack pointer. */
+ " isb \n"
+ " mov r0, #0 \n"
+ " msr basepri, r0 \n"
+ " orr r14, #0xd \n"
+ " bx r14 \n"
+ " \n"
+ " .align 4 \n"
+ "pxCurrentTCBConst2: .word pxCurrentTCB \n"
+ );
+}
+/*-----------------------------------------------------------*/
+
+static void prvPortStartFirstTask( void )
+{
+ __asm volatile (
+ " ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */
+ " ldr r0, [r0] \n"
+ " ldr r0, [r0] \n"
+ " msr msp, r0 \n"/* Set the msp back to the start of the stack. */
+ " cpsie i \n"/* Globally enable interrupts. */
+ " cpsie f \n"
+ " dsb \n"
+ " isb \n"
+ " svc 0 \n"/* System call to start first task. */
+ " nop \n"
+ " .ltorg \n"
+ );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+ /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
+ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+
+ #if ( configASSERT_DEFINED == 1 )
+ {
+ volatile uint32_t ulOriginalPriority;
+ volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine the maximum priority from which ISR safe FreeRTOS API
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * ensure interrupt entry is as fast and simple as possible.
+ *
+ * Save the interrupt priority value that is about to be clobbered. */
+ ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+ /* Determine the number of priority bits available. First write to all
+ * possible bits. */
+ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+ /* Use the same mask on the maximum system call priority. */
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+ /* Calculate the maximum acceptable priority group value for the number
+ * of bits read back. */
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+ {
+ ulMaxPRIGROUPValue--;
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+ }
+
+ #ifdef __NVIC_PRIO_BITS
+ {
+ /* Check the CMSIS configuration that defines the number of
+ * priority bits matches the number of priority bits actually queried
+ * from the hardware. */
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+ }
+ #endif
+
+ #ifdef configPRIO_BITS
+ {
+ /* Check the FreeRTOS configuration that defines the number of
+ * priority bits matches the number of priority bits actually queried
+ * from the hardware. */
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+ }
+ #endif
+
+ /* Shift the priority group value back to its position within the AIRCR
+ * register. */
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+ /* Restore the clobbered interrupt priority register to its original
+ * value. */
+ *pucFirstUserPriorityRegister = ulOriginalPriority;
+ }
+ #endif /* configASSERT_DEFINED */
+
+ /* Make PendSV and SysTick the lowest priority interrupts. */
+ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
+ portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ * here already. */
+ vPortSetupTimerInterrupt();
+
+ /* Initialise the critical nesting count ready for the first task. */
+ uxCriticalNesting = 0;
+
+ /* Start the first task. */
+ prvPortStartFirstTask();
+
+ /* Should never get here as the tasks will now be executing! Call the task
+ * exit error function to prevent compiler warnings about a static function
+ * not being called in the case that the application writer overrides this
+ * functionality by defining configTASK_RETURN_ADDRESS. Call
+ * vTaskSwitchContext() so link time optimisation does not remove the
+ * symbol. */
+ vTaskSwitchContext();
+ prvTaskExitError();
+
+ /* Should not get here! */
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+ /* Not implemented in ports where there is nothing to return to.
+ * Artificially force an assert. */
+ configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+ portDISABLE_INTERRUPTS();
+ uxCriticalNesting++;
+
+ /* This is not the interrupt safe version of the enter critical function so
+ * assert() if it is being called from an interrupt context. Only API
+ * functions that end in "FromISR" can be used in an interrupt. Only assert if
+ * the critical nesting count is 1 to protect against recursive calls if the
+ * assert function also uses a critical section. */
+ if( uxCriticalNesting == 1 )
+ {
+ configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+ configASSERT( uxCriticalNesting );
+ uxCriticalNesting--;
+
+ if( uxCriticalNesting == 0 )
+ {
+ portENABLE_INTERRUPTS();
+ }
+}
+/*-----------------------------------------------------------*/
+
+void xPortPendSVHandler( void )
+{
+ /* This is a naked function. */
+
+ __asm volatile
+ (
+ " mrs r0, psp \n"
+ " isb \n"
+ " \n"
+ " ldr r3, pxCurrentTCBConst \n"/* Get the location of the current TCB. */
+ " ldr r2, [r3] \n"
+ " \n"
+ " stmdb r0!, {r4-r11} \n"/* Save the remaining registers. */
+ " str r0, [r2] \n"/* Save the new top of stack into the first member of the TCB. */
+ " \n"
+ " stmdb sp!, {r3, r14} \n"
+ " mov r0, %0 \n"
+ " msr basepri, r0 \n"
+ " bl vTaskSwitchContext \n"
+ " mov r0, #0 \n"
+ " msr basepri, r0 \n"
+ " ldmia sp!, {r3, r14} \n"
+ " \n"/* Restore the context, including the critical nesting count. */
+ " ldr r1, [r3] \n"
+ " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. */
+ " ldmia r0!, {r4-r11} \n"/* Pop the registers. */
+ " msr psp, r0 \n"
+ " isb \n"
+ " bx r14 \n"
+ " \n"
+ " .align 4 \n"
+ "pxCurrentTCBConst: .word pxCurrentTCB \n"
+ ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+ );
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+ /* The SysTick runs at the lowest interrupt priority, so when this interrupt
+ * executes all interrupts must be unmasked. There is therefore no need to
+ * save and then restore the interrupt mask value as its value is already
+ * known. */
+ portDISABLE_INTERRUPTS();
+ {
+ /* Increment the RTOS tick. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ /* A context switch is required. Context switching is performed in
+ * the PendSV interrupt. Pend the PendSV interrupt. */
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+ }
+ }
+ portENABLE_INTERRUPTS();
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+
+ __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+ {
+ uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
+ TickType_t xModifiableIdleTime;
+
+ /* Make sure the SysTick reload value does not overflow the counter. */
+ if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+ {
+ xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+ }
+
+ /* Enter a critical section but don't use the taskENTER_CRITICAL()
+ * method as that will mask interrupts that should exit sleep mode. */
+ __asm volatile ( "cpsid i" ::: "memory" );
+ __asm volatile ( "dsb" );
+ __asm volatile ( "isb" );
+
+ /* If a context switch is pending or a task is waiting for the scheduler
+ * to be unsuspended then abandon the low power entry. */
+ if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+ {
+ /* Re-enable interrupts - see comments above the cpsid instruction
+ * above. */
+ __asm volatile ( "cpsie i" ::: "memory" );
+ }
+ else
+ {
+ /* Stop the SysTick momentarily. The time the SysTick is stopped for
+ * is accounted for as best it can be, but using the tickless mode will
+ * inevitably result in some tiny drift of the time maintained by the
+ * kernel with respect to calendar time. */
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
+
+ /* Use the SysTick current-value register to determine the number of
+ * SysTick decrements remaining until the next tick interrupt. If the
+ * current-value register is zero, then there are actually
+ * ulTimerCountsForOneTick decrements remaining, not zero, because the
+ * SysTick requests the interrupt when decrementing from 1 to 0. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulTimerCountsForOneTick;
+ }
+
+ /* Calculate the reload value required to wait xExpectedIdleTime
+ * tick periods. -1 is used because this code normally executes part
+ * way through the first tick period. But if the SysTick IRQ is now
+ * pending, then clear the IRQ, suppressing the first tick, and correct
+ * the reload value to reflect that the second tick period is already
+ * underway. The expected idle time is always at least two ticks. */
+ ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+ if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )
+ {
+ portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;
+ ulReloadValue -= ulTimerCountsForOneTick;
+ }
+
+ if( ulReloadValue > ulStoppedTimerCompensation )
+ {
+ ulReloadValue -= ulStoppedTimerCompensation;
+ }
+
+ /* Set the new reload value. */
+ portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+ /* Clear the SysTick count flag and set the count value back to
+ * zero. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+ /* Restart SysTick. */
+ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+ /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
+ * set its parameter to 0 to indicate that its implementation contains
+ * its own wait for interrupt or wait for event instruction, and so wfi
+ * should not be executed again. However, the original expected idle
+ * time variable must remain unmodified, so a copy is taken. */
+ xModifiableIdleTime = xExpectedIdleTime;
+ configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+
+ if( xModifiableIdleTime > 0 )
+ {
+ __asm volatile ( "dsb" ::: "memory" );
+ __asm volatile ( "wfi" );
+ __asm volatile ( "isb" );
+ }
+
+ configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+ /* Re-enable interrupts to allow the interrupt that brought the MCU
+ * out of sleep mode to execute immediately. See comments above
+ * the cpsid instruction above. */
+ __asm volatile ( "cpsie i" ::: "memory" );
+ __asm volatile ( "dsb" );
+ __asm volatile ( "isb" );
+
+ /* Disable interrupts again because the clock is about to be stopped
+ * and interrupts that execute while the clock is stopped will increase
+ * any slippage between the time maintained by the RTOS and calendar
+ * time. */
+ __asm volatile ( "cpsid i" ::: "memory" );
+ __asm volatile ( "dsb" );
+ __asm volatile ( "isb" );
+
+ /* Disable the SysTick clock without reading the
+ * portNVIC_SYSTICK_CTRL_REG register to ensure the
+ * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
+ * the time the SysTick is stopped for is accounted for as best it can
+ * be, but using the tickless mode will inevitably result in some tiny
+ * drift of the time maintained by the kernel with respect to calendar
+ * time*/
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
+
+ /* Determine whether the SysTick has already counted to zero. */
+ if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+ {
+ uint32_t ulCalculatedLoadValue;
+
+ /* The tick interrupt ended the sleep (or is now pending), and
+ * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG
+ * with whatever remains of the new tick period. */
+ ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+ /* Don't allow a tiny value, or values that have somehow
+ * underflowed because the post sleep hook did something
+ * that took too long or because the SysTick current-value register
+ * is zero. */
+ if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+ {
+ ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+ }
+
+ portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+ /* As the pending tick will be processed as soon as this
+ * function exits, the tick value maintained by the tick is stepped
+ * forward by one less than the time spent waiting. */
+ ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+ }
+ else
+ {
+ /* Something other than the tick interrupt ended the sleep. */
+
+ /* Use the SysTick current-value register to determine the
+ * number of SysTick decrements remaining until the expected idle
+ * time would have ended. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )
+ {
+ /* If the SysTick is not using the core clock, the current-
+ * value register might still be zero here. In that case, the
+ * SysTick didn't load from the reload register, and there are
+ * ulReloadValue decrements remaining in the expected idle
+ * time, not zero. */
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulReloadValue;
+ }
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Work out how long the sleep lasted rounded to complete tick
+ * periods (not the ulReload value which accounted for part
+ * ticks). */
+ ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;
+
+ /* How many complete tick periods passed while the processor
+ * was waiting? */
+ ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+ /* The reload value is set to whatever fraction of a single tick
+ * period remains. */
+ portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+ }
+
+ /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,
+ * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If
+ * the SysTick is not using the core clock, temporarily configure it to
+ * use the core clock. This configuration forces the SysTick to load
+ * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next
+ * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready
+ * to receive the standard value immediately. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )
+ {
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ }
+ #else
+ {
+ /* The temporary usage of the core clock has served its purpose,
+ * as described above. Resume usage of the other clock. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
+
+ if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+ {
+ /* The partial tick period already ended. Be sure the SysTick
+ * counts it only once. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;
+ }
+
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Step the tick to account for any tick periods that elapsed. */
+ vTaskStepTick( ulCompleteTickPeriods );
+
+ /* Exit with interrupts enabled. */
+ __asm volatile ( "cpsie i" ::: "memory" );
+ }
+ }
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
+{
+ /* Calculate the constants required to configure the tick interrupt. */
+ #if ( configUSE_TICKLESS_IDLE == 1 )
+ {
+ ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+ xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+ ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+ }
+ #endif /* configUSE_TICKLESS_IDLE */
+
+ /* Stop and clear the SysTick. */
+ portNVIC_SYSTICK_CTRL_REG = 0UL;
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+ /* Configure SysTick to interrupt at the requested rate. */
+ portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+}
+/*-----------------------------------------------------------*/
+
+#if ( configASSERT_DEFINED == 1 )
+
+ void vPortValidateInterruptPriority( void )
+ {
+ uint32_t ulCurrentInterrupt;
+ uint8_t ucCurrentPriority;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ /* Is the interrupt number a user defined interrupt? */
+ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+ {
+ /* Look up the interrupt's priority. */
+ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+ /* The following assertion will fail if a service routine (ISR) for
+ * an interrupt that has been assigned a priority above
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+ * function. ISR safe FreeRTOS API functions must *only* be called
+ * from interrupts that have been assigned a priority at or below
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Numerically low interrupt priority numbers represent logically high
+ * interrupt priorities, therefore the priority of the interrupt must
+ * be set to a value equal to or numerically *higher* than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Interrupts that use the FreeRTOS API must not be left at their
+ * default priority of zero as that is the highest possible priority,
+ * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+ * and therefore also guaranteed to be invalid.
+ *
+ * FreeRTOS maintains separate thread and ISR API functions to ensure
+ * interrupt entry is as fast and simple as possible.
+ *
+ * The following links provide detailed information:
+ * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+ * https://www.FreeRTOS.org/FAQHelp.html */
+ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+ }
+
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits
+ * that define each interrupt's priority to be split between bits that
+ * define the interrupt's pre-emption priority bits and bits that define
+ * the interrupt's sub-priority. For simplicity all bits must be defined
+ * to be pre-emption priority bits. The following assertion will fail if
+ * this is not the case (if some bits represent a sub-priority).
+ *
+ * If the application only uses CMSIS libraries for interrupt
+ * configuration then the correct setting can be achieved on all Cortex-M
+ * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+ * scheduler. Note however that some vendor specific peripheral libraries
+ * assume a non-zero priority group setting, in which cases using a value
+ * of zero will result in unpredictable behaviour. */
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+ }
+
+#endif /* configASSERT_DEFINED */
diff --git a/portable/GCC/ARM_CM3/portmacro.h b/portable/GCC/ARM_CM3/portmacro.h
index cce38bc..a7b45a5 100644
--- a/portable/GCC/ARM_CM3/portmacro.h
+++ b/portable/GCC/ARM_CM3/portmacro.h
@@ -1,247 +1,247 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-
-#ifndef PORTMACRO_H
- #define PORTMACRO_H
-
- #ifdef __cplusplus
- extern "C" {
- #endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
-
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
-
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portDONT_DISCARD __attribute__( ( used ) )
-/*-----------------------------------------------------------*/
-
-/* Scheduler utilities. */
- #define portYIELD() \
- { \
- /* Set a PendSV to request a context switch. */ \
- portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
- \
- /* Barriers are normally not required but do ensure the code is completely \
- * within the specified behaviour for the architecture. */ \
- __asm volatile ( "dsb" ::: "memory" ); \
- __asm volatile ( "isb" ); \
- }
-
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 )
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/* Critical section management. */
- extern void vPortEnterCritical( void );
- extern void vPortExitCritical( void );
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x )
- #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
- #define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. These are
- * not necessary for to use this port. They are defined so the common demo files
- * (which build with all the ports) will build. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
-/*-----------------------------------------------------------*/
-
-/* Tickless idle/low power functionality. */
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specific optimisations. */
- #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
- #endif
-
- #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
-/* Generic helper function. */
- __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
- {
- uint8_t ucReturn;
-
- __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
-
- return ucReturn;
- }
-
-/* Check the configuration. */
- #if ( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
-
-/* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-/*-----------------------------------------------------------*/
-
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
-
- #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-/*-----------------------------------------------------------*/
-
- #ifdef configASSERT
- void vPortValidateInterruptPriority( void );
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
- #endif
-
-/* portNOP() is not required by this port. */
- #define portNOP()
-
- #define portINLINE __inline
-
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
- #endif
-
-/*-----------------------------------------------------------*/
-
- portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
- {
- uint32_t ulCurrentInterrupt;
- BaseType_t xReturn;
-
- /* Obtain the number of the currently executing interrupt. */
- __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
-
- if( ulCurrentInterrupt == 0 )
- {
- xReturn = pdFALSE;
- }
- else
- {
- xReturn = pdTRUE;
- }
-
- return xReturn;
- }
-
-/*-----------------------------------------------------------*/
-
- portFORCE_INLINE static void vPortRaiseBASEPRI( void )
- {
- uint32_t ulNewBASEPRI;
-
- __asm volatile
- (
- " mov %0, %1 \n"\
- " msr basepri, %0 \n"\
- " isb \n"\
- " dsb \n"\
- : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
- );
- }
-
-/*-----------------------------------------------------------*/
-
- portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
- {
- uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
-
- __asm volatile
- (
- " mrs %0, basepri \n"\
- " mov %1, %2 \n"\
- " msr basepri, %1 \n"\
- " isb \n"\
- " dsb \n"\
- : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
- );
-
- /* This return will not be reached but is necessary to prevent compiler
- * warnings. */
- return ulOriginalBASEPRI;
- }
-/*-----------------------------------------------------------*/
-
- portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
- {
- __asm volatile
- (
- " msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory"
- );
- }
-/*-----------------------------------------------------------*/
-
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
-
- #ifdef __cplusplus
- }
- #endif
-
-#endif /* PORTMACRO_H */
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+#ifndef PORTMACRO_H
+ #define PORTMACRO_H
+
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+ #define portCHAR char
+ #define portFLOAT float
+ #define portDOUBLE double
+ #define portLONG long
+ #define portSHORT short
+ #define portSTACK_TYPE uint32_t
+ #define portBASE_TYPE long
+
+ typedef portSTACK_TYPE StackType_t;
+ typedef long BaseType_t;
+ typedef unsigned long UBaseType_t;
+
+ #if ( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+ #else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+ #endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+ #define portSTACK_GROWTH ( -1 )
+ #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+ #define portBYTE_ALIGNMENT 8
+ #define portDONT_DISCARD __attribute__( ( used ) )
+/*-----------------------------------------------------------*/
+
+/* Scheduler utilities. */
+ #define portYIELD() \
+ { \
+ /* Set a PendSV to request a context switch. */ \
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+ \
+ /* Barriers are normally not required but do ensure the code is completely \
+ * within the specified behaviour for the architecture. */ \
+ __asm volatile ( "dsb" ::: "memory" ); \
+ __asm volatile ( "isb" ); \
+ }
+
+ #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+ #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+ #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 )
+ #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+ extern void vPortEnterCritical( void );
+ extern void vPortExitCritical( void );
+ #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
+ #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x )
+ #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
+ #define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )
+ #define portENTER_CRITICAL() vPortEnterCritical()
+ #define portEXIT_CRITICAL() vPortExitCritical()
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. These are
+ * not necessary for to use this port. They are defined so the common demo files
+ * (which build with all the ports) will build. */
+ #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+ #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+ #ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+ #endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+ #endif
+
+ #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+/* Generic helper function. */
+ __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+ {
+ uint8_t ucReturn;
+
+ __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
+
+ return ucReturn;
+ }
+
+/* Check the configuration. */
+ #if ( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
+
+/* Store/clear the ready priorities in a bit map. */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/*-----------------------------------------------------------*/
+
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+ #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+ #ifdef configASSERT
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+ #endif
+
+/* portNOP() is not required by this port. */
+ #define portNOP()
+
+ #define portINLINE __inline
+
+ #ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+ #endif
+
+/*-----------------------------------------------------------*/
+
+ portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+ {
+ uint32_t ulCurrentInterrupt;
+ BaseType_t xReturn;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ if( ulCurrentInterrupt == 0 )
+ {
+ xReturn = pdFALSE;
+ }
+ else
+ {
+ xReturn = pdTRUE;
+ }
+
+ return xReturn;
+ }
+
+/*-----------------------------------------------------------*/
+
+ portFORCE_INLINE static void vPortRaiseBASEPRI( void )
+ {
+ uint32_t ulNewBASEPRI;
+
+ __asm volatile
+ (
+ " mov %0, %1 \n"\
+ " msr basepri, %0 \n"\
+ " isb \n"\
+ " dsb \n"\
+ : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+ );
+ }
+
+/*-----------------------------------------------------------*/
+
+ portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
+ {
+ uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
+
+ __asm volatile
+ (
+ " mrs %0, basepri \n"\
+ " mov %1, %2 \n"\
+ " msr basepri, %1 \n"\
+ " isb \n"\
+ " dsb \n"\
+ : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+ );
+
+ /* This return will not be reached but is necessary to prevent compiler
+ * warnings. */
+ return ulOriginalBASEPRI;
+ }
+/*-----------------------------------------------------------*/
+
+ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
+ {
+ __asm volatile
+ (
+ " msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+
+ #ifdef __cplusplus
+ }
+ #endif
+
+#endif /* PORTMACRO_H */
diff --git a/portable/GCC/ARM_CM33/non_secure/portasm.c b/portable/GCC/ARM_CM33/non_secure/portasm.c
index 1e4f0c9..9f9b2e6 100644
--- a/portable/GCC/ARM_CM33/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM33/non_secure/portasm.c
@@ -1,470 +1,470 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/* Standard includes. */
-#include <stdint.h>
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
- * is defined correctly and privileged functions are placed in correct sections. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Portasm includes. */
-#include "portasm.h"
-
-/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
- * header files. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " ldr r2, pxCurrentTCBConst2 \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r3, [r2] \n"/* Read pxCurrentTCB. */
- " ldr r0, [r3] \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
- " \n"
- #if ( configENABLE_MPU == 1 )
- " dmb \n"/* Complete outstanding transfers before disabling MPU. */
- " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
- " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
- " bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
- " str r4, [r2] \n"/* Disable MPU. */
- " \n"
- " adds r3, #4 \n"/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
- " ldr r4, [r3] \n"/* r4 = *r3 i.e. r4 = MAIR0. */
- " ldr r2, xMAIR0Const2 \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
- " str r4, [r2] \n"/* Program MAIR0. */
- " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
- " movs r4, #4 \n"/* r4 = 4. */
- " str r4, [r2] \n"/* Program RNR = 4. */
- " adds r3, #4 \n"/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
- " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
- " ldmia r3!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
- " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
- " \n"
- #if ( configTOTAL_MPU_REGIONS == 16 )
- " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
- " movs r4, #8 \n"/* r4 = 8. */
- " str r4, [r2] \n"/* Program RNR = 8. */
- " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
- " ldmia r3!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
- " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
- " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
- " movs r4, #12 \n"/* r4 = 12. */
- " str r4, [r2] \n"/* Program RNR = 12. */
- " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
- " ldmia r3!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
- " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
- #endif /* configTOTAL_MPU_REGIONS == 16 */
- " \n"
- " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
- " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
- " orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
- " str r4, [r2] \n"/* Enable MPU. */
- " dsb \n"/* Force memory writes before continuing. */
- #endif /* configENABLE_MPU */
- " \n"
- #if ( configENABLE_MPU == 1 )
- " ldm r0!, {r1-r4} \n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
- " ldr r5, xSecureContextConst2 \n"
- " str r1, [r5] \n"/* Set xSecureContext to this task's value for the same. */
- " msr psplim, r2 \n"/* Set this task's PSPLIM value. */
- " msr control, r3 \n"/* Set this task's CONTROL value. */
- " adds r0, #32 \n"/* Discard everything up to r0. */
- " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
- " isb \n"
- " mov r0, #0 \n"
- " msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */
- " bx r4 \n"/* Finally, branch to EXC_RETURN. */
- #else /* configENABLE_MPU */
- " ldm r0!, {r1-r3} \n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
- " ldr r4, xSecureContextConst2 \n"
- " str r1, [r4] \n"/* Set xSecureContext to this task's value for the same. */
- " msr psplim, r2 \n"/* Set this task's PSPLIM value. */
- " movs r1, #2 \n"/* r1 = 2. */
- " msr CONTROL, r1 \n"/* Switch to use PSP in the thread mode. */
- " adds r0, #32 \n"/* Discard everything up to r0. */
- " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
- " isb \n"
- " mov r0, #0 \n"
- " msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */
- " bx r3 \n"/* Finally, branch to EXC_RETURN. */
- #endif /* configENABLE_MPU */
- " \n"
- " .align 4 \n"
- "pxCurrentTCBConst2: .word pxCurrentTCB \n"
- "xSecureContextConst2: .word xSecureContext \n"
- #if ( configENABLE_MPU == 1 )
- "xMPUCTRLConst2: .word 0xe000ed94 \n"
- "xMAIR0Const2: .word 0xe000edc0 \n"
- "xRNRConst2: .word 0xe000ed98 \n"
- "xRBARConst2: .word 0xe000ed9c \n"
- #endif /* configENABLE_MPU */
- );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " mrs r0, control \n"/* r0 = CONTROL. */
- " tst r0, #1 \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
- " ite ne \n"
- " movne r0, #0 \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
- " moveq r0, #1 \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
- " bx lr \n"/* Return. */
- " \n"
- " .align 4 \n"
- ::: "r0", "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " mrs r0, control \n"/* Read the CONTROL register. */
- " bic r0, #1 \n"/* Clear the bit 0. */
- " msr control, r0 \n"/* Write back the new CONTROL value. */
- " bx lr \n"/* Return to the caller. */
- ::: "r0", "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-void vResetPrivilege( void ) /* __attribute__ (( naked )) */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " mrs r0, control \n"/* r0 = CONTROL. */
- " orr r0, #1 \n"/* r0 = r0 | 1. */
- " msr control, r0 \n"/* CONTROL = r0. */
- " bx lr \n"/* Return to the caller. */
- ::: "r0", "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " ldr r0, xVTORConst \n"/* Use the NVIC offset register to locate the stack. */
- " ldr r0, [r0] \n"/* Read the VTOR register which gives the address of vector table. */
- " ldr r0, [r0] \n"/* The first entry in vector table is stack pointer. */
- " msr msp, r0 \n"/* Set the MSP back to the start of the stack. */
- " cpsie i \n"/* Globally enable interrupts. */
- " cpsie f \n"
- " dsb \n"
- " isb \n"
- " svc %0 \n"/* System call to start the first task. */
- " nop \n"
- " \n"
- " .align 4 \n"
- "xVTORConst: .word 0xe000ed08 \n"
- ::"i" ( portSVC_START_SCHEDULER ) : "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " mrs r0, basepri \n"/* r0 = basepri. Return original basepri value. */
- " mov r1, %0 \n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- " msr basepri, r1 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- " dsb \n"
- " isb \n"
- " bx lr \n"/* Return. */
- ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " msr basepri, r0 \n"/* basepri = ulMask. */
- " dsb \n"
- " isb \n"
- " bx lr \n"/* Return. */
- ::: "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " .extern SecureContext_SaveContext \n"
- " .extern SecureContext_LoadContext \n"
- " \n"
- " ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
- " ldr r0, [r3] \n"/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
- " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r3] \n"/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
- " mrs r2, psp \n"/* Read PSP in r2. */
- " \n"
- " cbz r0, save_ns_context \n"/* No secure context to save. */
- " push {r0-r2, r14} \n"
- " bl SecureContext_SaveContext \n"/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
- " pop {r0-r3} \n"/* LR is now in r3. */
- " mov lr, r3 \n"/* LR = r3. */
- " lsls r1, r3, #25 \n"/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
- " bpl save_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
- " \n"
- " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r3] \n"/* Read pxCurrentTCB.*/
- #if ( configENABLE_MPU == 1 )
- " subs r2, r2, #16 \n"/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
- " str r2, [r1] \n"/* Save the new top of stack in TCB. */
- " mrs r1, psplim \n"/* r1 = PSPLIM. */
- " mrs r3, control \n"/* r3 = CONTROL. */
- " mov r4, lr \n"/* r4 = LR/EXC_RETURN. */
- " stmia r2!, {r0, r1, r3, r4} \n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
- #else /* configENABLE_MPU */
- " subs r2, r2, #12 \n"/* Make space for xSecureContext, PSPLIM and LR on the stack. */
- " str r2, [r1] \n"/* Save the new top of stack in TCB. */
- " mrs r1, psplim \n"/* r1 = PSPLIM. */
- " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */
- " stmia r2!, {r0, r1, r3} \n"/* Store xSecureContext, PSPLIM and LR on the stack. */
- #endif /* configENABLE_MPU */
- " b select_next_task \n"
- " \n"
- " save_ns_context: \n"
- " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r3] \n"/* Read pxCurrentTCB. */
- #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
- " tst lr, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
- " it eq \n"
- " vstmdbeq r2!, {s16-s31} \n"/* Store the additional FP context registers which are not saved automatically. */
- #endif /* configENABLE_FPU || configENABLE_MVE */
- #if ( configENABLE_MPU == 1 )
- " subs r2, r2, #48 \n"/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
- " str r2, [r1] \n"/* Save the new top of stack in TCB. */
- " adds r2, r2, #16 \n"/* r2 = r2 + 16. */
- " stm r2, {r4-r11} \n"/* Store the registers that are not saved automatically. */
- " mrs r1, psplim \n"/* r1 = PSPLIM. */
- " mrs r3, control \n"/* r3 = CONTROL. */
- " mov r4, lr \n"/* r4 = LR/EXC_RETURN. */
- " subs r2, r2, #16 \n"/* r2 = r2 - 16. */
- " stmia r2!, {r0, r1, r3, r4} \n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
- #else /* configENABLE_MPU */
- " subs r2, r2, #44 \n"/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
- " str r2, [r1] \n"/* Save the new top of stack in TCB. */
- " adds r2, r2, #12 \n"/* r2 = r2 + 12. */
- " stm r2, {r4-r11} \n"/* Store the registers that are not saved automatically. */
- " mrs r1, psplim \n"/* r1 = PSPLIM. */
- " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */
- " subs r2, r2, #12 \n"/* r2 = r2 - 12. */
- " stmia r2!, {r0, r1, r3} \n"/* Store xSecureContext, PSPLIM and LR on the stack. */
- #endif /* configENABLE_MPU */
- " \n"
- " select_next_task: \n"
- " mov r0, %0 \n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
- " msr basepri, r0 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- " dsb \n"
- " isb \n"
- " bl vTaskSwitchContext \n"
- " mov r0, #0 \n"/* r0 = 0. */
- " msr basepri, r0 \n"/* Enable interrupts. */
- " \n"
- " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r3] \n"/* Read pxCurrentTCB. */
- " ldr r2, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
- " \n"
- #if ( configENABLE_MPU == 1 )
- " dmb \n"/* Complete outstanding transfers before disabling MPU. */
- " ldr r3, xMPUCTRLConst \n"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */
- " ldr r4, [r3] \n"/* Read the value of MPU_CTRL. */
- " bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
- " str r4, [r3] \n"/* Disable MPU. */
- " \n"
- " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
- " ldr r4, [r1] \n"/* r4 = *r1 i.e. r4 = MAIR0. */
- " ldr r3, xMAIR0Const \n"/* r3 = 0xe000edc0 [Location of MAIR0]. */
- " str r4, [r3] \n"/* Program MAIR0. */
- " ldr r3, xRNRConst \n"/* r3 = 0xe000ed98 [Location of RNR]. */
- " movs r4, #4 \n"/* r4 = 4. */
- " str r4, [r3] \n"/* Program RNR = 4. */
- " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
- " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
- " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
- " stmia r3!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
- " \n"
- #if ( configTOTAL_MPU_REGIONS == 16 )
- " ldr r3, xRNRConst \n"/* r3 = 0xe000ed98 [Location of RNR]. */
- " movs r4, #8 \n"/* r4 = 8. */
- " str r4, [r3] \n"/* Program RNR = 8. */
- " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
- " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
- " stmia r3!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
- " ldr r3, xRNRConst \n"/* r3 = 0xe000ed98 [Location of RNR]. */
- " movs r4, #12 \n"/* r4 = 12. */
- " str r4, [r3] \n"/* Program RNR = 12. */
- " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
- " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
- " stmia r3!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
- #endif /* configTOTAL_MPU_REGIONS == 16 */
- " \n"
- " ldr r3, xMPUCTRLConst \n"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */
- " ldr r4, [r3] \n"/* Read the value of MPU_CTRL. */
- " orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
- " str r4, [r3] \n"/* Enable MPU. */
- " dsb \n"/* Force memory writes before continuing. */
- #endif /* configENABLE_MPU */
- " \n"
- #if ( configENABLE_MPU == 1 )
- " ldmia r2!, {r0, r1, r3, r4} \n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */
- " msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */
- " msr control, r3 \n"/* Restore the CONTROL register value for the task. */
- " mov lr, r4 \n"/* LR = r4. */
- " ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
- " str r0, [r3] \n"/* Restore the task's xSecureContext. */
- " cbz r0, restore_ns_context \n"/* If there is no secure context for the task, restore the non-secure context. */
- " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r3] \n"/* Read pxCurrentTCB. */
- " push {r2, r4} \n"
- " bl SecureContext_LoadContext \n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
- " pop {r2, r4} \n"
- " mov lr, r4 \n"/* LR = r4. */
- " lsls r1, r4, #25 \n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
- " bpl restore_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
- " msr psp, r2 \n"/* Remember the new top of stack for the task. */
- " bx lr \n"
- #else /* configENABLE_MPU */
- " ldmia r2!, {r0, r1, r4} \n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
- " msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */
- " mov lr, r4 \n"/* LR = r4. */
- " ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
- " str r0, [r3] \n"/* Restore the task's xSecureContext. */
- " cbz r0, restore_ns_context \n"/* If there is no secure context for the task, restore the non-secure context. */
- " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r3] \n"/* Read pxCurrentTCB. */
- " push {r2, r4} \n"
- " bl SecureContext_LoadContext \n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
- " pop {r2, r4} \n"
- " mov lr, r4 \n"/* LR = r4. */
- " lsls r1, r4, #25 \n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
- " bpl restore_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
- " msr psp, r2 \n"/* Remember the new top of stack for the task. */
- " bx lr \n"
- #endif /* configENABLE_MPU */
- " \n"
- " restore_ns_context: \n"
- " ldmia r2!, {r4-r11} \n"/* Restore the registers that are not automatically restored. */
- #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
- " tst lr, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
- " it eq \n"
- " vldmiaeq r2!, {s16-s31} \n"/* Restore the additional FP context registers which are not restored automatically. */
- #endif /* configENABLE_FPU || configENABLE_MVE */
- " msr psp, r2 \n"/* Remember the new top of stack for the task. */
- " bx lr \n"
- " \n"
- " .align 4 \n"
- "pxCurrentTCBConst: .word pxCurrentTCB \n"
- "xSecureContextConst: .word xSecureContext \n"
- #if ( configENABLE_MPU == 1 )
- "xMPUCTRLConst: .word 0xe000ed94 \n"
- "xMAIR0Const: .word 0xe000edc0 \n"
- "xRNRConst: .word 0xe000ed98 \n"
- "xRBARConst: .word 0xe000ed9c \n"
- #endif /* configENABLE_MPU */
- ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
- );
-}
-/*-----------------------------------------------------------*/
-
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " tst lr, #4 \n"
- " ite eq \n"
- " mrseq r0, msp \n"
- " mrsne r0, psp \n"
- " ldr r1, svchandler_address_const \n"
- " bx r1 \n"
- " \n"
- " .align 4 \n"
- "svchandler_address_const: .word vPortSVCHandler_C \n"
- );
-}
-/*-----------------------------------------------------------*/
-
-void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " svc %0 \n"/* Secure context is allocated in the supervisor call. */
- " bx lr \n"/* Return. */
- ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " ldr r2, [r0] \n"/* The first item in the TCB is the top of the stack. */
- " ldr r1, [r2] \n"/* The first item on the stack is the task's xSecureContext. */
- " cmp r1, #0 \n"/* Raise svc if task's xSecureContext is not NULL. */
- " it ne \n"
- " svcne %0 \n"/* Secure context is freed in the supervisor call. */
- " bx lr \n"/* Return. */
- ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
- );
-}
-/*-----------------------------------------------------------*/
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
+ * is defined correctly and privileged functions are placed in correct sections. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Portasm includes. */
+#include "portasm.h"
+
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
+ * header files. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " ldr r2, pxCurrentTCBConst2 \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r3, [r2] \n"/* Read pxCurrentTCB. */
+ " ldr r0, [r3] \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+ " \n"
+ #if ( configENABLE_MPU == 1 )
+ " dmb \n"/* Complete outstanding transfers before disabling MPU. */
+ " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
+ " bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+ " str r4, [r2] \n"/* Disable MPU. */
+ " \n"
+ " adds r3, #4 \n"/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+ " ldr r4, [r3] \n"/* r4 = *r3 i.e. r4 = MAIR0. */
+ " ldr r2, xMAIR0Const2 \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
+ " str r4, [r2] \n"/* Program MAIR0. */
+ " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
+ " movs r4, #4 \n"/* r4 = 4. */
+ " str r4, [r2] \n"/* Program RNR = 4. */
+ " adds r3, #4 \n"/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+ " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r3!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
+ " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+ " \n"
+ #if ( configTOTAL_MPU_REGIONS == 16 )
+ " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
+ " movs r4, #8 \n"/* r4 = 8. */
+ " str r4, [r2] \n"/* Program RNR = 8. */
+ " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r3!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
+ " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+ " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
+ " movs r4, #12 \n"/* r4 = 12. */
+ " str r4, [r2] \n"/* Program RNR = 12. */
+ " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r3!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
+ " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+ #endif /* configTOTAL_MPU_REGIONS == 16 */
+ " \n"
+ " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
+ " orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+ " str r4, [r2] \n"/* Enable MPU. */
+ " dsb \n"/* Force memory writes before continuing. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ #if ( configENABLE_MPU == 1 )
+ " ldm r0!, {r1-r4} \n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
+ " ldr r5, xSecureContextConst2 \n"
+ " str r1, [r5] \n"/* Set xSecureContext to this task's value for the same. */
+ " msr psplim, r2 \n"/* Set this task's PSPLIM value. */
+ " msr control, r3 \n"/* Set this task's CONTROL value. */
+ " adds r0, #32 \n"/* Discard everything up to r0. */
+ " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
+ " isb \n"
+ " mov r0, #0 \n"
+ " msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */
+ " bx r4 \n"/* Finally, branch to EXC_RETURN. */
+ #else /* configENABLE_MPU */
+ " ldm r0!, {r1-r3} \n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
+ " ldr r4, xSecureContextConst2 \n"
+ " str r1, [r4] \n"/* Set xSecureContext to this task's value for the same. */
+ " msr psplim, r2 \n"/* Set this task's PSPLIM value. */
+ " movs r1, #2 \n"/* r1 = 2. */
+ " msr CONTROL, r1 \n"/* Switch to use PSP in the thread mode. */
+ " adds r0, #32 \n"/* Discard everything up to r0. */
+ " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
+ " isb \n"
+ " mov r0, #0 \n"
+ " msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */
+ " bx r3 \n"/* Finally, branch to EXC_RETURN. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ " .align 4 \n"
+ "pxCurrentTCBConst2: .word pxCurrentTCB \n"
+ "xSecureContextConst2: .word xSecureContext \n"
+ #if ( configENABLE_MPU == 1 )
+ "xMPUCTRLConst2: .word 0xe000ed94 \n"
+ "xMAIR0Const2: .word 0xe000edc0 \n"
+ "xRNRConst2: .word 0xe000ed98 \n"
+ "xRBARConst2: .word 0xe000ed9c \n"
+ #endif /* configENABLE_MPU */
+ );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, control \n"/* r0 = CONTROL. */
+ " tst r0, #1 \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+ " ite ne \n"
+ " movne r0, #0 \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+ " moveq r0, #1 \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+ " bx lr \n"/* Return. */
+ " \n"
+ " .align 4 \n"
+ ::: "r0", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, control \n"/* Read the CONTROL register. */
+ " bic r0, #1 \n"/* Clear the bit 0. */
+ " msr control, r0 \n"/* Write back the new CONTROL value. */
+ " bx lr \n"/* Return to the caller. */
+ ::: "r0", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, control \n"/* r0 = CONTROL. */
+ " orr r0, #1 \n"/* r0 = r0 | 1. */
+ " msr control, r0 \n"/* CONTROL = r0. */
+ " bx lr \n"/* Return to the caller. */
+ ::: "r0", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " ldr r0, xVTORConst \n"/* Use the NVIC offset register to locate the stack. */
+ " ldr r0, [r0] \n"/* Read the VTOR register which gives the address of vector table. */
+ " ldr r0, [r0] \n"/* The first entry in vector table is stack pointer. */
+ " msr msp, r0 \n"/* Set the MSP back to the start of the stack. */
+ " cpsie i \n"/* Globally enable interrupts. */
+ " cpsie f \n"
+ " dsb \n"
+ " isb \n"
+ " svc %0 \n"/* System call to start the first task. */
+ " nop \n"
+ " \n"
+ " .align 4 \n"
+ "xVTORConst: .word 0xe000ed08 \n"
+ ::"i" ( portSVC_START_SCHEDULER ) : "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, basepri \n"/* r0 = basepri. Return original basepri value. */
+ " mov r1, %0 \n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " msr basepri, r1 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " dsb \n"
+ " isb \n"
+ " bx lr \n"/* Return. */
+ ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " msr basepri, r0 \n"/* basepri = ulMask. */
+ " dsb \n"
+ " isb \n"
+ " bx lr \n"/* Return. */
+ ::: "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern SecureContext_SaveContext \n"
+ " .extern SecureContext_LoadContext \n"
+ " \n"
+ " ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ " ldr r0, [r3] \n"/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+ " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r3] \n"/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
+ " mrs r2, psp \n"/* Read PSP in r2. */
+ " \n"
+ " cbz r0, save_ns_context \n"/* No secure context to save. */
+ " push {r0-r2, r14} \n"
+ " bl SecureContext_SaveContext \n"/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+ " pop {r0-r3} \n"/* LR is now in r3. */
+ " mov lr, r3 \n"/* LR = r3. */
+ " lsls r1, r3, #25 \n"/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+ " bpl save_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+ " \n"
+ " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r3] \n"/* Read pxCurrentTCB.*/
+ #if ( configENABLE_MPU == 1 )
+ " subs r2, r2, #16 \n"/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+ " str r2, [r1] \n"/* Save the new top of stack in TCB. */
+ " mrs r1, psplim \n"/* r1 = PSPLIM. */
+ " mrs r3, control \n"/* r3 = CONTROL. */
+ " mov r4, lr \n"/* r4 = LR/EXC_RETURN. */
+ " stmia r2!, {r0, r1, r3, r4} \n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+ #else /* configENABLE_MPU */
+ " subs r2, r2, #12 \n"/* Make space for xSecureContext, PSPLIM and LR on the stack. */
+ " str r2, [r1] \n"/* Save the new top of stack in TCB. */
+ " mrs r1, psplim \n"/* r1 = PSPLIM. */
+ " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */
+ " stmia r2!, {r0, r1, r3} \n"/* Store xSecureContext, PSPLIM and LR on the stack. */
+ #endif /* configENABLE_MPU */
+ " b select_next_task \n"
+ " \n"
+ " save_ns_context: \n"
+ " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r3] \n"/* Read pxCurrentTCB. */
+ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ " tst lr, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+ " it eq \n"
+ " vstmdbeq r2!, {s16-s31} \n"/* Store the additional FP context registers which are not saved automatically. */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
+ #if ( configENABLE_MPU == 1 )
+ " subs r2, r2, #48 \n"/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+ " str r2, [r1] \n"/* Save the new top of stack in TCB. */
+ " adds r2, r2, #16 \n"/* r2 = r2 + 16. */
+ " stm r2, {r4-r11} \n"/* Store the registers that are not saved automatically. */
+ " mrs r1, psplim \n"/* r1 = PSPLIM. */
+ " mrs r3, control \n"/* r3 = CONTROL. */
+ " mov r4, lr \n"/* r4 = LR/EXC_RETURN. */
+ " subs r2, r2, #16 \n"/* r2 = r2 - 16. */
+ " stmia r2!, {r0, r1, r3, r4} \n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+ #else /* configENABLE_MPU */
+ " subs r2, r2, #44 \n"/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+ " str r2, [r1] \n"/* Save the new top of stack in TCB. */
+ " adds r2, r2, #12 \n"/* r2 = r2 + 12. */
+ " stm r2, {r4-r11} \n"/* Store the registers that are not saved automatically. */
+ " mrs r1, psplim \n"/* r1 = PSPLIM. */
+ " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */
+ " subs r2, r2, #12 \n"/* r2 = r2 - 12. */
+ " stmia r2!, {r0, r1, r3} \n"/* Store xSecureContext, PSPLIM and LR on the stack. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ " select_next_task: \n"
+ " mov r0, %0 \n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+ " msr basepri, r0 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " dsb \n"
+ " isb \n"
+ " bl vTaskSwitchContext \n"
+ " mov r0, #0 \n"/* r0 = 0. */
+ " msr basepri, r0 \n"/* Enable interrupts. */
+ " \n"
+ " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r3] \n"/* Read pxCurrentTCB. */
+ " ldr r2, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
+ " \n"
+ #if ( configENABLE_MPU == 1 )
+ " dmb \n"/* Complete outstanding transfers before disabling MPU. */
+ " ldr r3, xMPUCTRLConst \n"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r4, [r3] \n"/* Read the value of MPU_CTRL. */
+ " bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+ " str r4, [r3] \n"/* Disable MPU. */
+ " \n"
+ " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+ " ldr r4, [r1] \n"/* r4 = *r1 i.e. r4 = MAIR0. */
+ " ldr r3, xMAIR0Const \n"/* r3 = 0xe000edc0 [Location of MAIR0]. */
+ " str r4, [r3] \n"/* Program MAIR0. */
+ " ldr r3, xRNRConst \n"/* r3 = 0xe000ed98 [Location of RNR]. */
+ " movs r4, #4 \n"/* r4 = 4. */
+ " str r4, [r3] \n"/* Program RNR = 4. */
+ " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+ " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
+ " stmia r3!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+ " \n"
+ #if ( configTOTAL_MPU_REGIONS == 16 )
+ " ldr r3, xRNRConst \n"/* r3 = 0xe000ed98 [Location of RNR]. */
+ " movs r4, #8 \n"/* r4 = 8. */
+ " str r4, [r3] \n"/* Program RNR = 8. */
+ " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
+ " stmia r3!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+ " ldr r3, xRNRConst \n"/* r3 = 0xe000ed98 [Location of RNR]. */
+ " movs r4, #12 \n"/* r4 = 12. */
+ " str r4, [r3] \n"/* Program RNR = 12. */
+ " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
+ " stmia r3!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+ #endif /* configTOTAL_MPU_REGIONS == 16 */
+ " \n"
+ " ldr r3, xMPUCTRLConst \n"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r4, [r3] \n"/* Read the value of MPU_CTRL. */
+ " orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+ " str r4, [r3] \n"/* Enable MPU. */
+ " dsb \n"/* Force memory writes before continuing. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ #if ( configENABLE_MPU == 1 )
+ " ldmia r2!, {r0, r1, r3, r4} \n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */
+ " msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */
+ " msr control, r3 \n"/* Restore the CONTROL register value for the task. */
+ " mov lr, r4 \n"/* LR = r4. */
+ " ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ " str r0, [r3] \n"/* Restore the task's xSecureContext. */
+ " cbz r0, restore_ns_context \n"/* If there is no secure context for the task, restore the non-secure context. */
+ " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r3] \n"/* Read pxCurrentTCB. */
+ " push {r2, r4} \n"
+ " bl SecureContext_LoadContext \n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+ " pop {r2, r4} \n"
+ " mov lr, r4 \n"/* LR = r4. */
+ " lsls r1, r4, #25 \n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+ " bpl restore_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+ " msr psp, r2 \n"/* Remember the new top of stack for the task. */
+ " bx lr \n"
+ #else /* configENABLE_MPU */
+ " ldmia r2!, {r0, r1, r4} \n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
+ " msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */
+ " mov lr, r4 \n"/* LR = r4. */
+ " ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ " str r0, [r3] \n"/* Restore the task's xSecureContext. */
+ " cbz r0, restore_ns_context \n"/* If there is no secure context for the task, restore the non-secure context. */
+ " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r3] \n"/* Read pxCurrentTCB. */
+ " push {r2, r4} \n"
+ " bl SecureContext_LoadContext \n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+ " pop {r2, r4} \n"
+ " mov lr, r4 \n"/* LR = r4. */
+ " lsls r1, r4, #25 \n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+ " bpl restore_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+ " msr psp, r2 \n"/* Remember the new top of stack for the task. */
+ " bx lr \n"
+ #endif /* configENABLE_MPU */
+ " \n"
+ " restore_ns_context: \n"
+ " ldmia r2!, {r4-r11} \n"/* Restore the registers that are not automatically restored. */
+ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ " tst lr, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+ " it eq \n"
+ " vldmiaeq r2!, {s16-s31} \n"/* Restore the additional FP context registers which are not restored automatically. */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
+ " msr psp, r2 \n"/* Remember the new top of stack for the task. */
+ " bx lr \n"
+ " \n"
+ " .align 4 \n"
+ "pxCurrentTCBConst: .word pxCurrentTCB \n"
+ "xSecureContextConst: .word xSecureContext \n"
+ #if ( configENABLE_MPU == 1 )
+ "xMPUCTRLConst: .word 0xe000ed94 \n"
+ "xMAIR0Const: .word 0xe000edc0 \n"
+ "xRNRConst: .word 0xe000ed98 \n"
+ "xRBARConst: .word 0xe000ed9c \n"
+ #endif /* configENABLE_MPU */
+ ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+ );
+}
+/*-----------------------------------------------------------*/
+
+void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " tst lr, #4 \n"
+ " ite eq \n"
+ " mrseq r0, msp \n"
+ " mrsne r0, psp \n"
+ " ldr r1, svchandler_address_const \n"
+ " bx r1 \n"
+ " \n"
+ " .align 4 \n"
+ "svchandler_address_const: .word vPortSVCHandler_C \n"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " svc %0 \n"/* Secure context is allocated in the supervisor call. */
+ " bx lr \n"/* Return. */
+ ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " ldr r2, [r0] \n"/* The first item in the TCB is the top of the stack. */
+ " ldr r1, [r2] \n"/* The first item on the stack is the task's xSecureContext. */
+ " cmp r1, #0 \n"/* Raise svc if task's xSecureContext is not NULL. */
+ " it ne \n"
+ " svcne %0 \n"/* Secure context is freed in the supervisor call. */
+ " bx lr \n"/* Return. */
+ ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
+ );
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM33/non_secure/portasm.h b/portable/GCC/ARM_CM33/non_secure/portasm.h
index b37f6d1..ecd86b9 100644
--- a/portable/GCC/ARM_CM33/non_secure/portasm.h
+++ b/portable/GCC/ARM_CM33/non_secure/portasm.h
@@ -1,114 +1,114 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef __PORT_ASM_H__
-#define __PORT_ASM_H__
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-
-/* MPU wrappers includes. */
-#include "mpu_wrappers.h"
-
-/**
- * @brief Restore the context of the first task so that the first task starts
- * executing.
- */
-void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
-BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
-
-/**
- * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
- * register.
- *
- * @note This is a privileged function and should only be called from the kenrel
- * code.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- * Bit[0] = 0 --> The processor is running privileged
- * Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- * Bit[0] = 0 --> The processor is running privileged
- * Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vResetPrivilege( void ) __attribute__( ( naked ) );
-
-/**
- * @brief Starts the first task.
- */
-void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Disables interrupts.
- */
-uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Enables interrupts.
- */
-void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief PendSV Exception handler.
- */
-void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief SVC Handler.
- */
-void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Allocate a Secure context for the calling task.
- *
- * @param[in] ulSecureStackSize The size of the stack to be allocated on the
- * secure side for the calling task.
- */
-void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );
-
-/**
- * @brief Free the task's secure context.
- *
- * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
- */
-void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-#endif /* __PORT_ASM_H__ */
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/portable/GCC/ARM_CM33/non_secure/portmacro.h b/portable/GCC/ARM_CM33/non_secure/portmacro.h
index 766dfb0..943c665 100644
--- a/portable/GCC/ARM_CM33/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM33/non_secure/portmacro.h
@@ -1,66 +1,66 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "portmacrocommon.h"
-
-/*------------------------------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *------------------------------------------------------------------------------
- */
-
-/**
- * Architecture specifics.
- */
-#define portARCH_NAME "Cortex-M33"
-#define portDONT_DISCARD __attribute__( ( used ) )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Critical section management.
- */
-#define portDISABLE_INTERRUPTS() ulSetInterruptMask()
-#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
-/*-----------------------------------------------------------*/
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* PORTMACRO_H */
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "portmacrocommon.h"
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME "Cortex-M33"
+#define portDONT_DISCARD __attribute__( ( used ) )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portDISABLE_INTERRUPTS() ulSetInterruptMask()
+#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
index 4b1f99b..51e21ea 100644
--- a/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
@@ -155,9 +155,9 @@
* 8-bit values encoded as follows:
* Bit[7:4] - 0000 - Device Memory
* Bit[3:2] - 00 --> Device-nGnRnE
- * 01 --> Device-nGnRE
- * 10 --> Device-nGRE
- * 11 --> Device-GRE
+ * 01 --> Device-nGnRE
+ * 10 --> Device-nGRE
+ * 11 --> Device-GRE
* Bit[1:0] - 00, Reserved.
*/
#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
diff --git a/portable/GCC/ARM_CM33/secure/secure_context.c b/portable/GCC/ARM_CM33/secure/secure_context.c
index b1d5503..0730d57 100644
--- a/portable/GCC/ARM_CM33/secure/secure_context.c
+++ b/portable/GCC/ARM_CM33/secure/secure_context.c
@@ -1,351 +1,351 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/* Secure context includes. */
-#include "secure_context.h"
-
-/* Secure heap includes. */
-#include "secure_heap.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/**
- * @brief CONTROL value for privileged tasks.
- *
- * Bit[0] - 0 --> Thread mode is privileged.
- * Bit[1] - 1 --> Thread mode uses PSP.
- */
-#define securecontextCONTROL_VALUE_PRIVILEGED 0x02
-
-/**
- * @brief CONTROL value for un-privileged tasks.
- *
- * Bit[0] - 1 --> Thread mode is un-privileged.
- * Bit[1] - 1 --> Thread mode uses PSP.
- */
-#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03
-
-/**
- * @brief Size of stack seal values in bytes.
- */
-#define securecontextSTACK_SEAL_SIZE 8
-
-/**
- * @brief Stack seal value as recommended by ARM.
- */
-#define securecontextSTACK_SEAL_VALUE 0xFEF5EDA5
-
-/**
- * @brief Maximum number of secure contexts.
- */
-#ifndef secureconfigMAX_SECURE_CONTEXTS
- #define secureconfigMAX_SECURE_CONTEXTS 8UL
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Pre-allocated array of secure contexts.
- */
-SecureContext_t xSecureContexts[ secureconfigMAX_SECURE_CONTEXTS ];
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Get a free secure context for a task from the secure context pool (xSecureContexts).
- *
- * This function ensures that only one secure context is allocated for a task.
- *
- * @param[in] pvTaskHandle The task handle for which the secure context is allocated.
- *
- * @return Index of a free secure context in the xSecureContexts array.
- */
-static uint32_t ulGetSecureContext( void * pvTaskHandle );
-
-/**
- * @brief Return the secure context to the secure context pool (xSecureContexts).
- *
- * @param[in] ulSecureContextIndex Index of the context in the xSecureContexts array.
- */
-static void vReturnSecureContext( uint32_t ulSecureContextIndex );
-
-/* These are implemented in assembly. */
-extern void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext );
-extern void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext );
-/*-----------------------------------------------------------*/
-
-static uint32_t ulGetSecureContext( void * pvTaskHandle )
-{
- /* Start with invalid index. */
- uint32_t i, ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS;
-
- for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ )
- {
- if( ( xSecureContexts[ i ].pucCurrentStackPointer == NULL ) &&
- ( xSecureContexts[ i ].pucStackLimit == NULL ) &&
- ( xSecureContexts[ i ].pucStackStart == NULL ) &&
- ( xSecureContexts[ i ].pvTaskHandle == NULL ) &&
- ( ulSecureContextIndex == secureconfigMAX_SECURE_CONTEXTS ) )
- {
- ulSecureContextIndex = i;
- }
- else if( xSecureContexts[ i ].pvTaskHandle == pvTaskHandle )
- {
- /* A task can only have one secure context. Do not allocate a second
- * context for the same task. */
- ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS;
- break;
- }
- }
-
- return ulSecureContextIndex;
-}
-/*-----------------------------------------------------------*/
-
-static void vReturnSecureContext( uint32_t ulSecureContextIndex )
-{
- xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = NULL;
- xSecureContexts[ ulSecureContextIndex ].pucStackLimit = NULL;
- xSecureContexts[ ulSecureContextIndex ].pucStackStart = NULL;
- xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = NULL;
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
-{
- uint32_t ulIPSR, i;
- static uint32_t ulSecureContextsInitialized = 0;
-
- /* Read the Interrupt Program Status Register (IPSR) value. */
- secureportREAD_IPSR( ulIPSR );
-
- /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
- * when the processor is running in the Thread Mode. */
- if( ( ulIPSR != 0 ) && ( ulSecureContextsInitialized == 0 ) )
- {
- /* Ensure to initialize secure contexts only once. */
- ulSecureContextsInitialized = 1;
-
- /* No stack for thread mode until a task's context is loaded. */
- secureportSET_PSPLIM( securecontextNO_STACK );
- secureportSET_PSP( securecontextNO_STACK );
-
- /* Initialize all secure contexts. */
- for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ )
- {
- xSecureContexts[ i ].pucCurrentStackPointer = NULL;
- xSecureContexts[ i ].pucStackLimit = NULL;
- xSecureContexts[ i ].pucStackStart = NULL;
- xSecureContexts[ i ].pvTaskHandle = NULL;
- }
-
- #if ( configENABLE_MPU == 1 )
- {
- /* Configure thread mode to use PSP and to be unprivileged. */
- secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
- }
- #else /* configENABLE_MPU */
- {
- /* Configure thread mode to use PSP and to be privileged. */
- secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
- }
- #endif /* configENABLE_MPU */
- }
-}
-/*-----------------------------------------------------------*/
-
-#if ( configENABLE_MPU == 1 )
- secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
- uint32_t ulIsTaskPrivileged,
- void * pvTaskHandle )
-#else /* configENABLE_MPU */
- secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
- void * pvTaskHandle )
-#endif /* configENABLE_MPU */
-{
- uint8_t * pucStackMemory = NULL;
- uint8_t * pucStackLimit;
- uint32_t ulIPSR, ulSecureContextIndex;
- SecureContextHandle_t xSecureContextHandle = securecontextINVALID_CONTEXT_ID;
-
- #if ( configENABLE_MPU == 1 )
- uint32_t * pulCurrentStackPointer = NULL;
- #endif /* configENABLE_MPU */
-
- /* Read the Interrupt Program Status Register (IPSR) and Process Stack Limit
- * Register (PSPLIM) value. */
- secureportREAD_IPSR( ulIPSR );
- secureportREAD_PSPLIM( pucStackLimit );
-
- /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
- * when the processor is running in the Thread Mode.
- * Also do nothing, if a secure context us already loaded. PSPLIM is set to
- * securecontextNO_STACK when no secure context is loaded. */
- if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )
- {
- /* Ontain a free secure context. */
- ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );
-
- /* Were we able to get a free context? */
- if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS )
- {
- /* Allocate the stack space. */
- pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE );
-
- if( pucStackMemory != NULL )
- {
- /* Since stack grows down, the starting point will be the last
- * location. Note that this location is next to the last
- * allocated byte for stack (excluding the space for seal values)
- * because the hardware decrements the stack pointer before
- * writing i.e. if stack pointer is 0x2, a push operation will
- * decrement the stack pointer to 0x1 and then write at 0x1. */
- xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize;
-
- /* Seal the created secure process stack. */
- *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
- *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
-
- /* The stack cannot go beyond this location. This value is
- * programmed in the PSPLIM register on context switch.*/
- xSecureContexts[ ulSecureContextIndex ].pucStackLimit = pucStackMemory;
-
- xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle;
-
- #if ( configENABLE_MPU == 1 )
- {
- /* Store the correct CONTROL value for the task on the stack.
- * This value is programmed in the CONTROL register on
- * context switch. */
- pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
- pulCurrentStackPointer--;
-
- if( ulIsTaskPrivileged )
- {
- *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
- }
- else
- {
- *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
- }
-
- /* Store the current stack pointer. This value is programmed in
- * the PSP register on context switch. */
- xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
- }
- #else /* configENABLE_MPU */
- {
- /* Current SP is set to the starting of the stack. This
- * value programmed in the PSP register on context switch. */
- xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
- }
- #endif /* configENABLE_MPU */
-
- /* Ensure to never return 0 as a valid context handle. */
- xSecureContextHandle = ulSecureContextIndex + 1UL;
- }
- }
- }
-
- return xSecureContextHandle;
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
-{
- uint32_t ulIPSR, ulSecureContextIndex;
-
- /* Read the Interrupt Program Status Register (IPSR) value. */
- secureportREAD_IPSR( ulIPSR );
-
- /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
- * when the processor is running in the Thread Mode. */
- if( ulIPSR != 0 )
- {
- /* Only free if a valid context handle is passed. */
- if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )
- {
- ulSecureContextIndex = xSecureContextHandle - 1UL;
-
- /* Ensure that the secure context being deleted is associated with
- * the task. */
- if( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle )
- {
- /* Free the stack space. */
- vPortFree( xSecureContexts[ ulSecureContextIndex ].pucStackLimit );
-
- /* Return the secure context back to the free secure contexts pool. */
- vReturnSecureContext( ulSecureContextIndex );
- }
- }
- }
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
-{
- uint8_t * pucStackLimit;
- uint32_t ulSecureContextIndex;
-
- if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )
- {
- ulSecureContextIndex = xSecureContextHandle - 1UL;
-
- secureportREAD_PSPLIM( pucStackLimit );
-
- /* Ensure that no secure context is loaded and the task is loading it's
- * own context. */
- if( ( pucStackLimit == securecontextNO_STACK ) &&
- ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )
- {
- SecureContext_LoadContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) );
- }
- }
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
-{
- uint8_t * pucStackLimit;
- uint32_t ulSecureContextIndex;
-
- if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )
- {
- ulSecureContextIndex = xSecureContextHandle - 1UL;
-
- secureportREAD_PSPLIM( pucStackLimit );
-
- /* Ensure that task's context is loaded and the task is saving it's own
- * context. */
- if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) &&
- ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )
- {
- SecureContext_SaveContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) );
- }
- }
-}
-/*-----------------------------------------------------------*/
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief CONTROL value for privileged tasks.
+ *
+ * Bit[0] - 0 --> Thread mode is privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_PRIVILEGED 0x02
+
+/**
+ * @brief CONTROL value for un-privileged tasks.
+ *
+ * Bit[0] - 1 --> Thread mode is un-privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03
+
+/**
+ * @brief Size of stack seal values in bytes.
+ */
+#define securecontextSTACK_SEAL_SIZE 8
+
+/**
+ * @brief Stack seal value as recommended by ARM.
+ */
+#define securecontextSTACK_SEAL_VALUE 0xFEF5EDA5
+
+/**
+ * @brief Maximum number of secure contexts.
+ */
+#ifndef secureconfigMAX_SECURE_CONTEXTS
+ #define secureconfigMAX_SECURE_CONTEXTS 8UL
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Pre-allocated array of secure contexts.
+ */
+SecureContext_t xSecureContexts[ secureconfigMAX_SECURE_CONTEXTS ];
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Get a free secure context for a task from the secure context pool (xSecureContexts).
+ *
+ * This function ensures that only one secure context is allocated for a task.
+ *
+ * @param[in] pvTaskHandle The task handle for which the secure context is allocated.
+ *
+ * @return Index of a free secure context in the xSecureContexts array.
+ */
+static uint32_t ulGetSecureContext( void * pvTaskHandle );
+
+/**
+ * @brief Return the secure context to the secure context pool (xSecureContexts).
+ *
+ * @param[in] ulSecureContextIndex Index of the context in the xSecureContexts array.
+ */
+static void vReturnSecureContext( uint32_t ulSecureContextIndex );
+
+/* These are implemented in assembly. */
+extern void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext );
+extern void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext );
+/*-----------------------------------------------------------*/
+
+static uint32_t ulGetSecureContext( void * pvTaskHandle )
+{
+ /* Start with invalid index. */
+ uint32_t i, ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS;
+
+ for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ )
+ {
+ if( ( xSecureContexts[ i ].pucCurrentStackPointer == NULL ) &&
+ ( xSecureContexts[ i ].pucStackLimit == NULL ) &&
+ ( xSecureContexts[ i ].pucStackStart == NULL ) &&
+ ( xSecureContexts[ i ].pvTaskHandle == NULL ) &&
+ ( ulSecureContextIndex == secureconfigMAX_SECURE_CONTEXTS ) )
+ {
+ ulSecureContextIndex = i;
+ }
+ else if( xSecureContexts[ i ].pvTaskHandle == pvTaskHandle )
+ {
+ /* A task can only have one secure context. Do not allocate a second
+ * context for the same task. */
+ ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS;
+ break;
+ }
+ }
+
+ return ulSecureContextIndex;
+}
+/*-----------------------------------------------------------*/
+
+static void vReturnSecureContext( uint32_t ulSecureContextIndex )
+{
+ xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = NULL;
+ xSecureContexts[ ulSecureContextIndex ].pucStackLimit = NULL;
+ xSecureContexts[ ulSecureContextIndex ].pucStackStart = NULL;
+ xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = NULL;
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
+{
+ uint32_t ulIPSR, i;
+ static uint32_t ulSecureContextsInitialized = 0;
+
+ /* Read the Interrupt Program Status Register (IPSR) value. */
+ secureportREAD_IPSR( ulIPSR );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode. */
+ if( ( ulIPSR != 0 ) && ( ulSecureContextsInitialized == 0 ) )
+ {
+ /* Ensure to initialize secure contexts only once. */
+ ulSecureContextsInitialized = 1;
+
+ /* No stack for thread mode until a task's context is loaded. */
+ secureportSET_PSPLIM( securecontextNO_STACK );
+ secureportSET_PSP( securecontextNO_STACK );
+
+ /* Initialize all secure contexts. */
+ for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ )
+ {
+ xSecureContexts[ i ].pucCurrentStackPointer = NULL;
+ xSecureContexts[ i ].pucStackLimit = NULL;
+ xSecureContexts[ i ].pucStackStart = NULL;
+ xSecureContexts[ i ].pvTaskHandle = NULL;
+ }
+
+ #if ( configENABLE_MPU == 1 )
+ {
+ /* Configure thread mode to use PSP and to be unprivileged. */
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+ }
+ #else /* configENABLE_MPU */
+ {
+ /* Configure thread mode to use PSP and to be privileged. */
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+ }
+ #endif /* configENABLE_MPU */
+ }
+}
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+ secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
+ uint32_t ulIsTaskPrivileged,
+ void * pvTaskHandle )
+#else /* configENABLE_MPU */
+ secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
+ void * pvTaskHandle )
+#endif /* configENABLE_MPU */
+{
+ uint8_t * pucStackMemory = NULL;
+ uint8_t * pucStackLimit;
+ uint32_t ulIPSR, ulSecureContextIndex;
+ SecureContextHandle_t xSecureContextHandle = securecontextINVALID_CONTEXT_ID;
+
+ #if ( configENABLE_MPU == 1 )
+ uint32_t * pulCurrentStackPointer = NULL;
+ #endif /* configENABLE_MPU */
+
+ /* Read the Interrupt Program Status Register (IPSR) and Process Stack Limit
+ * Register (PSPLIM) value. */
+ secureportREAD_IPSR( ulIPSR );
+ secureportREAD_PSPLIM( pucStackLimit );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode.
+ * Also do nothing, if a secure context us already loaded. PSPLIM is set to
+ * securecontextNO_STACK when no secure context is loaded. */
+ if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )
+ {
+ /* Ontain a free secure context. */
+ ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );
+
+ /* Were we able to get a free context? */
+ if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS )
+ {
+ /* Allocate the stack space. */
+ pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE );
+
+ if( pucStackMemory != NULL )
+ {
+ /* Since stack grows down, the starting point will be the last
+ * location. Note that this location is next to the last
+ * allocated byte for stack (excluding the space for seal values)
+ * because the hardware decrements the stack pointer before
+ * writing i.e. if stack pointer is 0x2, a push operation will
+ * decrement the stack pointer to 0x1 and then write at 0x1. */
+ xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize;
+
+ /* Seal the created secure process stack. */
+ *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
+ *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
+
+ /* The stack cannot go beyond this location. This value is
+ * programmed in the PSPLIM register on context switch.*/
+ xSecureContexts[ ulSecureContextIndex ].pucStackLimit = pucStackMemory;
+
+ xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle;
+
+ #if ( configENABLE_MPU == 1 )
+ {
+ /* Store the correct CONTROL value for the task on the stack.
+ * This value is programmed in the CONTROL register on
+ * context switch. */
+ pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+ pulCurrentStackPointer--;
+
+ if( ulIsTaskPrivileged )
+ {
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
+ }
+ else
+ {
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+ }
+
+ /* Store the current stack pointer. This value is programmed in
+ * the PSP register on context switch. */
+ xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+ }
+ #else /* configENABLE_MPU */
+ {
+ /* Current SP is set to the starting of the stack. This
+ * value programmed in the PSP register on context switch. */
+ xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+ }
+ #endif /* configENABLE_MPU */
+
+ /* Ensure to never return 0 as a valid context handle. */
+ xSecureContextHandle = ulSecureContextIndex + 1UL;
+ }
+ }
+ }
+
+ return xSecureContextHandle;
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+{
+ uint32_t ulIPSR, ulSecureContextIndex;
+
+ /* Read the Interrupt Program Status Register (IPSR) value. */
+ secureportREAD_IPSR( ulIPSR );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode. */
+ if( ulIPSR != 0 )
+ {
+ /* Only free if a valid context handle is passed. */
+ if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )
+ {
+ ulSecureContextIndex = xSecureContextHandle - 1UL;
+
+ /* Ensure that the secure context being deleted is associated with
+ * the task. */
+ if( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle )
+ {
+ /* Free the stack space. */
+ vPortFree( xSecureContexts[ ulSecureContextIndex ].pucStackLimit );
+
+ /* Return the secure context back to the free secure contexts pool. */
+ vReturnSecureContext( ulSecureContextIndex );
+ }
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+{
+ uint8_t * pucStackLimit;
+ uint32_t ulSecureContextIndex;
+
+ if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )
+ {
+ ulSecureContextIndex = xSecureContextHandle - 1UL;
+
+ secureportREAD_PSPLIM( pucStackLimit );
+
+ /* Ensure that no secure context is loaded and the task is loading it's
+ * own context. */
+ if( ( pucStackLimit == securecontextNO_STACK ) &&
+ ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )
+ {
+ SecureContext_LoadContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) );
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+{
+ uint8_t * pucStackLimit;
+ uint32_t ulSecureContextIndex;
+
+ if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )
+ {
+ ulSecureContextIndex = xSecureContextHandle - 1UL;
+
+ secureportREAD_PSPLIM( pucStackLimit );
+
+ /* Ensure that task's context is loaded and the task is saving it's own
+ * context. */
+ if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) &&
+ ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )
+ {
+ SecureContext_SaveContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) );
+ }
+ }
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM33/secure/secure_context.h b/portable/GCC/ARM_CM33/secure/secure_context.h
index 57e390c..d0adbaf 100644
--- a/portable/GCC/ARM_CM33/secure/secure_context.h
+++ b/portable/GCC/ARM_CM33/secure/secure_context.h
@@ -1,135 +1,135 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef __SECURE_CONTEXT_H__
-#define __SECURE_CONTEXT_H__
-
-/* Standard includes. */
-#include <stdint.h>
-
-/* FreeRTOS includes. */
-#include "FreeRTOSConfig.h"
-
-/**
- * @brief PSP value when no secure context is loaded.
- */
-#define securecontextNO_STACK 0x0
-
-/**
- * @brief Invalid context ID.
- */
-#define securecontextINVALID_CONTEXT_ID 0UL
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Structure to represent a secure context.
- *
- * @note Since stack grows down, pucStackStart is the highest address while
- * pucStackLimit is the first address of the allocated memory.
- */
-typedef struct SecureContext
-{
- uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */
- uint8_t * pucStackLimit; /**< Last location of the stack memory (PSPLIM). */
- uint8_t * pucStackStart; /**< First location of the stack memory. */
- void * pvTaskHandle; /**< Task handle of the task this context is associated with. */
-} SecureContext_t;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Opaque handle for a secure context.
- */
-typedef uint32_t SecureContextHandle_t;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Initializes the secure context management system.
- *
- * PSP is set to NULL and therefore a task must allocate and load a context
- * before calling any secure side function in the thread mode.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- */
-void SecureContext_Init( void );
-
-/**
- * @brief Allocates a context on the secure side.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.
- * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.
- *
- * @return Opaque context handle if context is successfully allocated, NULL
- * otherwise.
- */
-#if ( configENABLE_MPU == 1 )
- SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
- uint32_t ulIsTaskPrivileged,
- void * pvTaskHandle );
-#else /* configENABLE_MPU */
- SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
- void * pvTaskHandle );
-#endif /* configENABLE_MPU */
-
-/**
- * @brief Frees the given context.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] xSecureContextHandle Context handle corresponding to the
- * context to be freed.
- */
-void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
-
-/**
- * @brief Loads the given context.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] xSecureContextHandle Context handle corresponding to the context
- * to be loaded.
- */
-void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
-
-/**
- * @brief Saves the given context.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] xSecureContextHandle Context handle corresponding to the context
- * to be saved.
- */
-void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
-
-#endif /* __SECURE_CONTEXT_H__ */
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef __SECURE_CONTEXT_H__
+#define __SECURE_CONTEXT_H__
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* FreeRTOS includes. */
+#include "FreeRTOSConfig.h"
+
+/**
+ * @brief PSP value when no secure context is loaded.
+ */
+#define securecontextNO_STACK 0x0
+
+/**
+ * @brief Invalid context ID.
+ */
+#define securecontextINVALID_CONTEXT_ID 0UL
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Structure to represent a secure context.
+ *
+ * @note Since stack grows down, pucStackStart is the highest address while
+ * pucStackLimit is the first address of the allocated memory.
+ */
+typedef struct SecureContext
+{
+ uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */
+ uint8_t * pucStackLimit; /**< Last location of the stack memory (PSPLIM). */
+ uint8_t * pucStackStart; /**< First location of the stack memory. */
+ void * pvTaskHandle; /**< Task handle of the task this context is associated with. */
+} SecureContext_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Opaque handle for a secure context.
+ */
+typedef uint32_t SecureContextHandle_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Initializes the secure context management system.
+ *
+ * PSP is set to NULL and therefore a task must allocate and load a context
+ * before calling any secure side function in the thread mode.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureContext_Init( void );
+
+/**
+ * @brief Allocates a context on the secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.
+ * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.
+ *
+ * @return Opaque context handle if context is successfully allocated, NULL
+ * otherwise.
+ */
+#if ( configENABLE_MPU == 1 )
+ SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
+ uint32_t ulIsTaskPrivileged,
+ void * pvTaskHandle );
+#else /* configENABLE_MPU */
+ SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
+ void * pvTaskHandle );
+#endif /* configENABLE_MPU */
+
+/**
+ * @brief Frees the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the
+ * context to be freed.
+ */
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+
+/**
+ * @brief Loads the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be loaded.
+ */
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+
+/**
+ * @brief Saves the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be saved.
+ */
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+
+#endif /* __SECURE_CONTEXT_H__ */
diff --git a/portable/GCC/ARM_CM33/secure/secure_context_port.c b/portable/GCC/ARM_CM33/secure/secure_context_port.c
index ebf0207..1352087 100644
--- a/portable/GCC/ARM_CM33/secure/secure_context_port.c
+++ b/portable/GCC/ARM_CM33/secure/secure_context_port.c
@@ -1,97 +1,97 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/* Secure context includes. */
-#include "secure_context.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );
-void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );
-
-void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext )
-{
- /* pxSecureContext value is in r0. */
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " mrs r1, ipsr \n" /* r1 = IPSR. */
- " cbz r1, load_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */
- " ldmia r0!, {r1, r2} \n" /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */
- " \n"
- #if ( configENABLE_MPU == 1 )
- " ldmia r1!, {r3} \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */
- " msr control, r3 \n" /* CONTROL = r3. */
- #endif /* configENABLE_MPU */
- " \n"
- " msr psplim, r2 \n" /* PSPLIM = r2. */
- " msr psp, r1 \n" /* PSP = r1. */
- " \n"
- " load_ctx_therad_mode: \n"
- " bx lr \n"
- " \n"
- ::: "r0", "r1", "r2"
- );
-}
-/*-----------------------------------------------------------*/
-
-void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext )
-{
- /* pxSecureContext value is in r0. */
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " mrs r1, ipsr \n" /* r1 = IPSR. */
- " cbz r1, save_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */
- " mrs r1, psp \n" /* r1 = PSP. */
- " \n"
- #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
- " vstmdb r1!, {s0} \n" /* Trigger the deferred stacking of FPU registers. */
- " vldmia r1!, {s0} \n" /* Nullify the effect of the previous statement. */
- #endif /* configENABLE_FPU || configENABLE_MVE */
- " \n"
- #if ( configENABLE_MPU == 1 )
- " mrs r2, control \n" /* r2 = CONTROL. */
- " stmdb r1!, {r2} \n" /* Store CONTROL value on the stack. */
- #endif /* configENABLE_MPU */
- " \n"
- " str r1, [r0] \n" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */
- " movs r1, %0 \n" /* r1 = securecontextNO_STACK. */
- " msr psplim, r1 \n" /* PSPLIM = securecontextNO_STACK. */
- " msr psp, r1 \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
- " \n"
- " save_ctx_therad_mode: \n"
- " bx lr \n"
- " \n"
- ::"i" ( securecontextNO_STACK ) : "r1", "memory"
- );
-}
-/*-----------------------------------------------------------*/
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );
+void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );
+
+void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext )
+{
+ /* pxSecureContext value is in r0. */
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r1, ipsr \n" /* r1 = IPSR. */
+ " cbz r1, load_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */
+ " ldmia r0!, {r1, r2} \n" /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */
+ " \n"
+ #if ( configENABLE_MPU == 1 )
+ " ldmia r1!, {r3} \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */
+ " msr control, r3 \n" /* CONTROL = r3. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ " msr psplim, r2 \n" /* PSPLIM = r2. */
+ " msr psp, r1 \n" /* PSP = r1. */
+ " \n"
+ " load_ctx_therad_mode: \n"
+ " bx lr \n"
+ " \n"
+ ::: "r0", "r1", "r2"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext )
+{
+ /* pxSecureContext value is in r0. */
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r1, ipsr \n" /* r1 = IPSR. */
+ " cbz r1, save_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */
+ " mrs r1, psp \n" /* r1 = PSP. */
+ " \n"
+ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ " vstmdb r1!, {s0} \n" /* Trigger the deferred stacking of FPU registers. */
+ " vldmia r1!, {s0} \n" /* Nullify the effect of the previous statement. */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
+ " \n"
+ #if ( configENABLE_MPU == 1 )
+ " mrs r2, control \n" /* r2 = CONTROL. */
+ " stmdb r1!, {r2} \n" /* Store CONTROL value on the stack. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ " str r1, [r0] \n" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */
+ " movs r1, %0 \n" /* r1 = securecontextNO_STACK. */
+ " msr psplim, r1 \n" /* PSPLIM = securecontextNO_STACK. */
+ " msr psp, r1 \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
+ " \n"
+ " save_ctx_therad_mode: \n"
+ " bx lr \n"
+ " \n"
+ ::"i" ( securecontextNO_STACK ) : "r1", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM33/secure/secure_heap.c b/portable/GCC/ARM_CM33/secure/secure_heap.c
index 741b463..157fdbf 100644
--- a/portable/GCC/ARM_CM33/secure/secure_heap.c
+++ b/portable/GCC/ARM_CM33/secure/secure_heap.c
@@ -1,454 +1,454 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/* Standard includes. */
-#include <stdint.h>
-
-/* Secure context heap includes. */
-#include "secure_heap.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/**
- * @brief Total heap size.
- */
-#ifndef secureconfigTOTAL_HEAP_SIZE
- #define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) )
-#endif
-
-/* No test marker by default. */
-#ifndef mtCOVERAGE_TEST_MARKER
- #define mtCOVERAGE_TEST_MARKER()
-#endif
-
-/* No tracing by default. */
-#ifndef traceMALLOC
- #define traceMALLOC( pvReturn, xWantedSize )
-#endif
-
-/* No tracing by default. */
-#ifndef traceFREE
- #define traceFREE( pv, xBlockSize )
-#endif
-
-/* Block sizes must not get too small. */
-#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) )
-
-/* Assumes 8bit bytes! */
-#define secureheapBITS_PER_BYTE ( ( size_t ) 8 )
-/*-----------------------------------------------------------*/
-
-/* Allocate the memory for the heap. */
-#if ( configAPPLICATION_ALLOCATED_HEAP == 1 )
-
-/* The application writer has already defined the array used for the RTOS
-* heap - probably so it can be placed in a special segment or address. */
- extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
-#else /* configAPPLICATION_ALLOCATED_HEAP */
- static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
-#endif /* configAPPLICATION_ALLOCATED_HEAP */
-
-/**
- * @brief The linked list structure.
- *
- * This is used to link free blocks in order of their memory address.
- */
-typedef struct A_BLOCK_LINK
-{
- struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */
- size_t xBlockSize; /**< The size of the free block. */
-} BlockLink_t;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Called automatically to setup the required heap structures the first
- * time pvPortMalloc() is called.
- */
-static void prvHeapInit( void );
-
-/**
- * @brief Inserts a block of memory that is being freed into the correct
- * position in the list of free memory blocks.
- *
- * The block being freed will be merged with the block in front it and/or the
- * block behind it if the memory blocks are adjacent to each other.
- *
- * @param[in] pxBlockToInsert The block being freed.
- */
-static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert );
-/*-----------------------------------------------------------*/
-
-/**
- * @brief The size of the structure placed at the beginning of each allocated
- * memory block must by correctly byte aligned.
- */
-static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
-
-/**
- * @brief Create a couple of list links to mark the start and end of the list.
- */
-static BlockLink_t xStart;
-static BlockLink_t * pxEnd = NULL;
-
-/**
- * @brief Keeps track of the number of free bytes remaining, but says nothing
- * about fragmentation.
- */
-static size_t xFreeBytesRemaining = 0U;
-static size_t xMinimumEverFreeBytesRemaining = 0U;
-
-/**
- * @brief Gets set to the top bit of an size_t type.
- *
- * When this bit in the xBlockSize member of an BlockLink_t structure is set
- * then the block belongs to the application. When the bit is free the block is
- * still part of the free heap space.
- */
-static size_t xBlockAllocatedBit = 0;
-/*-----------------------------------------------------------*/
-
-static void prvHeapInit( void )
-{
- BlockLink_t * pxFirstFreeBlock;
- uint8_t * pucAlignedHeap;
- size_t uxAddress;
- size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;
-
- /* Ensure the heap starts on a correctly aligned boundary. */
- uxAddress = ( size_t ) ucHeap;
-
- if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )
- {
- uxAddress += ( secureportBYTE_ALIGNMENT - 1 );
- uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
- xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
- }
-
- pucAlignedHeap = ( uint8_t * ) uxAddress;
-
- /* xStart is used to hold a pointer to the first item in the list of free
- * blocks. The void cast is used to prevent compiler warnings. */
- xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
- xStart.xBlockSize = ( size_t ) 0;
-
- /* pxEnd is used to mark the end of the list of free blocks and is inserted
- * at the end of the heap space. */
- uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
- uxAddress -= xHeapStructSize;
- uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
- pxEnd = ( void * ) uxAddress;
- pxEnd->xBlockSize = 0;
- pxEnd->pxNextFreeBlock = NULL;
-
- /* To start with there is a single free block that is sized to take up the
- * entire heap space, minus the space taken by pxEnd. */
- pxFirstFreeBlock = ( void * ) pucAlignedHeap;
- pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
- pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
-
- /* Only one block exists - and it covers the entire usable heap space. */
- xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
- xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-
- /* Work out the position of the top bit in a size_t variable. */
- xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
-}
-/*-----------------------------------------------------------*/
-
-static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )
-{
- BlockLink_t * pxIterator;
- uint8_t * puc;
-
- /* Iterate through the list until a block is found that has a higher address
- * than the block being inserted. */
- for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
- {
- /* Nothing to do here, just iterate to the right position. */
- }
-
- /* Do the block being inserted, and the block it is being inserted after
- * make a contiguous block of memory? */
- puc = ( uint8_t * ) pxIterator;
-
- if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
- {
- pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
- pxBlockToInsert = pxIterator;
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
-
- /* Do the block being inserted, and the block it is being inserted before
- * make a contiguous block of memory? */
- puc = ( uint8_t * ) pxBlockToInsert;
-
- if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
- {
- if( pxIterator->pxNextFreeBlock != pxEnd )
- {
- /* Form one big block from the two blocks. */
- pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
- pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
- }
- else
- {
- pxBlockToInsert->pxNextFreeBlock = pxEnd;
- }
- }
- else
- {
- pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
- }
-
- /* If the block being inserted plugged a gab, so was merged with the block
- * before and the block after, then it's pxNextFreeBlock pointer will have
- * already been set, and should not be set here as that would make it point
- * to itself. */
- if( pxIterator != pxBlockToInsert )
- {
- pxIterator->pxNextFreeBlock = pxBlockToInsert;
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
-}
-/*-----------------------------------------------------------*/
-
-void * pvPortMalloc( size_t xWantedSize )
-{
- BlockLink_t * pxBlock;
- BlockLink_t * pxPreviousBlock;
- BlockLink_t * pxNewBlockLink;
- void * pvReturn = NULL;
-
- /* If this is the first call to malloc then the heap will require
- * initialisation to setup the list of free blocks. */
- if( pxEnd == NULL )
- {
- prvHeapInit();
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
-
- /* Check the requested block size is not so large that the top bit is set.
- * The top bit of the block size member of the BlockLink_t structure is used
- * to determine who owns the block - the application or the kernel, so it
- * must be free. */
- if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
- {
- /* The wanted size is increased so it can contain a BlockLink_t
- * structure in addition to the requested amount of bytes. */
- if( xWantedSize > 0 )
- {
- xWantedSize += xHeapStructSize;
-
- /* Ensure that blocks are always aligned to the required number of
- * bytes. */
- if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
- {
- /* Byte alignment required. */
- xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
- secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
-
- if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
- {
- /* Traverse the list from the start (lowest address) block until
- * one of adequate size is found. */
- pxPreviousBlock = &xStart;
- pxBlock = xStart.pxNextFreeBlock;
-
- while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
- {
- pxPreviousBlock = pxBlock;
- pxBlock = pxBlock->pxNextFreeBlock;
- }
-
- /* If the end marker was reached then a block of adequate size was
- * not found. */
- if( pxBlock != pxEnd )
- {
- /* Return the memory space pointed to - jumping over the
- * BlockLink_t structure at its start. */
- pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
-
- /* This block is being returned for use so must be taken out
- * of the list of free blocks. */
- pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
-
- /* If the block is larger than required it can be split into
- * two. */
- if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )
- {
- /* This block is to be split into two. Create a new
- * block following the number of bytes requested. The void
- * cast is used to prevent byte alignment warnings from the
- * compiler. */
- pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
- secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );
-
- /* Calculate the sizes of two blocks split from the single
- * block. */
- pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
- pxBlock->xBlockSize = xWantedSize;
-
- /* Insert the new block into the list of free blocks. */
- prvInsertBlockIntoFreeList( pxNewBlockLink );
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
-
- xFreeBytesRemaining -= pxBlock->xBlockSize;
-
- if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
- {
- xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
-
- /* The block is being returned - it is allocated and owned by
- * the application and has no "next" block. */
- pxBlock->xBlockSize |= xBlockAllocatedBit;
- pxBlock->pxNextFreeBlock = NULL;
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
-
- traceMALLOC( pvReturn, xWantedSize );
-
- #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
- {
- if( pvReturn == NULL )
- {
- extern void vApplicationMallocFailedHook( void );
- vApplicationMallocFailedHook();
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
- }
- #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */
-
- secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
- return pvReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vPortFree( void * pv )
-{
- uint8_t * puc = ( uint8_t * ) pv;
- BlockLink_t * pxLink;
-
- if( pv != NULL )
- {
- /* The memory being freed will have an BlockLink_t structure immediately
- * before it. */
- puc -= xHeapStructSize;
-
- /* This casting is to keep the compiler from issuing warnings. */
- pxLink = ( void * ) puc;
-
- /* Check the block is actually allocated. */
- secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
- secureportASSERT( pxLink->pxNextFreeBlock == NULL );
-
- if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
- {
- if( pxLink->pxNextFreeBlock == NULL )
- {
- /* The block is being returned to the heap - it is no longer
- * allocated. */
- pxLink->xBlockSize &= ~xBlockAllocatedBit;
-
- secureportDISABLE_NON_SECURE_INTERRUPTS();
- {
- /* Add this block to the list of free blocks. */
- xFreeBytesRemaining += pxLink->xBlockSize;
- traceFREE( pv, pxLink->xBlockSize );
- prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
- }
- secureportENABLE_NON_SECURE_INTERRUPTS();
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
- }
-}
-/*-----------------------------------------------------------*/
-
-size_t xPortGetFreeHeapSize( void )
-{
- return xFreeBytesRemaining;
-}
-/*-----------------------------------------------------------*/
-
-size_t xPortGetMinimumEverFreeHeapSize( void )
-{
- return xMinimumEverFreeBytesRemaining;
-}
-/*-----------------------------------------------------------*/
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Secure context heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Total heap size.
+ */
+#ifndef secureconfigTOTAL_HEAP_SIZE
+ #define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) )
+#endif
+
+/* No test marker by default. */
+#ifndef mtCOVERAGE_TEST_MARKER
+ #define mtCOVERAGE_TEST_MARKER()
+#endif
+
+/* No tracing by default. */
+#ifndef traceMALLOC
+ #define traceMALLOC( pvReturn, xWantedSize )
+#endif
+
+/* No tracing by default. */
+#ifndef traceFREE
+ #define traceFREE( pv, xBlockSize )
+#endif
+
+/* Block sizes must not get too small. */
+#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) )
+
+/* Assumes 8bit bytes! */
+#define secureheapBITS_PER_BYTE ( ( size_t ) 8 )
+/*-----------------------------------------------------------*/
+
+/* Allocate the memory for the heap. */
+#if ( configAPPLICATION_ALLOCATED_HEAP == 1 )
+
+/* The application writer has already defined the array used for the RTOS
+* heap - probably so it can be placed in a special segment or address. */
+ extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#else /* configAPPLICATION_ALLOCATED_HEAP */
+ static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+/**
+ * @brief The linked list structure.
+ *
+ * This is used to link free blocks in order of their memory address.
+ */
+typedef struct A_BLOCK_LINK
+{
+ struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */
+ size_t xBlockSize; /**< The size of the free block. */
+} BlockLink_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Called automatically to setup the required heap structures the first
+ * time pvPortMalloc() is called.
+ */
+static void prvHeapInit( void );
+
+/**
+ * @brief Inserts a block of memory that is being freed into the correct
+ * position in the list of free memory blocks.
+ *
+ * The block being freed will be merged with the block in front it and/or the
+ * block behind it if the memory blocks are adjacent to each other.
+ *
+ * @param[in] pxBlockToInsert The block being freed.
+ */
+static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert );
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief The size of the structure placed at the beginning of each allocated
+ * memory block must by correctly byte aligned.
+ */
+static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+
+/**
+ * @brief Create a couple of list links to mark the start and end of the list.
+ */
+static BlockLink_t xStart;
+static BlockLink_t * pxEnd = NULL;
+
+/**
+ * @brief Keeps track of the number of free bytes remaining, but says nothing
+ * about fragmentation.
+ */
+static size_t xFreeBytesRemaining = 0U;
+static size_t xMinimumEverFreeBytesRemaining = 0U;
+
+/**
+ * @brief Gets set to the top bit of an size_t type.
+ *
+ * When this bit in the xBlockSize member of an BlockLink_t structure is set
+ * then the block belongs to the application. When the bit is free the block is
+ * still part of the free heap space.
+ */
+static size_t xBlockAllocatedBit = 0;
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+ BlockLink_t * pxFirstFreeBlock;
+ uint8_t * pucAlignedHeap;
+ size_t uxAddress;
+ size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;
+
+ /* Ensure the heap starts on a correctly aligned boundary. */
+ uxAddress = ( size_t ) ucHeap;
+
+ if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )
+ {
+ uxAddress += ( secureportBYTE_ALIGNMENT - 1 );
+ uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+ xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
+ }
+
+ pucAlignedHeap = ( uint8_t * ) uxAddress;
+
+ /* xStart is used to hold a pointer to the first item in the list of free
+ * blocks. The void cast is used to prevent compiler warnings. */
+ xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+ xStart.xBlockSize = ( size_t ) 0;
+
+ /* pxEnd is used to mark the end of the list of free blocks and is inserted
+ * at the end of the heap space. */
+ uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
+ uxAddress -= xHeapStructSize;
+ uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+ pxEnd = ( void * ) uxAddress;
+ pxEnd->xBlockSize = 0;
+ pxEnd->pxNextFreeBlock = NULL;
+
+ /* To start with there is a single free block that is sized to take up the
+ * entire heap space, minus the space taken by pxEnd. */
+ pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+ pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
+ pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+
+ /* Only one block exists - and it covers the entire usable heap space. */
+ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+ xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+
+ /* Work out the position of the top bit in a size_t variable. */
+ xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )
+{
+ BlockLink_t * pxIterator;
+ uint8_t * puc;
+
+ /* Iterate through the list until a block is found that has a higher address
+ * than the block being inserted. */
+ for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+ {
+ /* Nothing to do here, just iterate to the right position. */
+ }
+
+ /* Do the block being inserted, and the block it is being inserted after
+ * make a contiguous block of memory? */
+ puc = ( uint8_t * ) pxIterator;
+
+ if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+ {
+ pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+ pxBlockToInsert = pxIterator;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Do the block being inserted, and the block it is being inserted before
+ * make a contiguous block of memory? */
+ puc = ( uint8_t * ) pxBlockToInsert;
+
+ if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+ {
+ if( pxIterator->pxNextFreeBlock != pxEnd )
+ {
+ /* Form one big block from the two blocks. */
+ pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+ }
+ else
+ {
+ pxBlockToInsert->pxNextFreeBlock = pxEnd;
+ }
+ }
+ else
+ {
+ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+ }
+
+ /* If the block being inserted plugged a gab, so was merged with the block
+ * before and the block after, then it's pxNextFreeBlock pointer will have
+ * already been set, and should not be set here as that would make it point
+ * to itself. */
+ if( pxIterator != pxBlockToInsert )
+ {
+ pxIterator->pxNextFreeBlock = pxBlockToInsert;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+}
+/*-----------------------------------------------------------*/
+
+void * pvPortMalloc( size_t xWantedSize )
+{
+ BlockLink_t * pxBlock;
+ BlockLink_t * pxPreviousBlock;
+ BlockLink_t * pxNewBlockLink;
+ void * pvReturn = NULL;
+
+ /* If this is the first call to malloc then the heap will require
+ * initialisation to setup the list of free blocks. */
+ if( pxEnd == NULL )
+ {
+ prvHeapInit();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Check the requested block size is not so large that the top bit is set.
+ * The top bit of the block size member of the BlockLink_t structure is used
+ * to determine who owns the block - the application or the kernel, so it
+ * must be free. */
+ if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+ {
+ /* The wanted size is increased so it can contain a BlockLink_t
+ * structure in addition to the requested amount of bytes. */
+ if( xWantedSize > 0 )
+ {
+ xWantedSize += xHeapStructSize;
+
+ /* Ensure that blocks are always aligned to the required number of
+ * bytes. */
+ if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
+ {
+ /* Byte alignment required. */
+ xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
+ secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+ {
+ /* Traverse the list from the start (lowest address) block until
+ * one of adequate size is found. */
+ pxPreviousBlock = &xStart;
+ pxBlock = xStart.pxNextFreeBlock;
+
+ while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+ {
+ pxPreviousBlock = pxBlock;
+ pxBlock = pxBlock->pxNextFreeBlock;
+ }
+
+ /* If the end marker was reached then a block of adequate size was
+ * not found. */
+ if( pxBlock != pxEnd )
+ {
+ /* Return the memory space pointed to - jumping over the
+ * BlockLink_t structure at its start. */
+ pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+
+ /* This block is being returned for use so must be taken out
+ * of the list of free blocks. */
+ pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+ /* If the block is larger than required it can be split into
+ * two. */
+ if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )
+ {
+ /* This block is to be split into two. Create a new
+ * block following the number of bytes requested. The void
+ * cast is used to prevent byte alignment warnings from the
+ * compiler. */
+ pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+ secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+
+ /* Calculate the sizes of two blocks split from the single
+ * block. */
+ pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+ pxBlock->xBlockSize = xWantedSize;
+
+ /* Insert the new block into the list of free blocks. */
+ prvInsertBlockIntoFreeList( pxNewBlockLink );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+ if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+ {
+ xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* The block is being returned - it is allocated and owned by
+ * the application and has no "next" block. */
+ pxBlock->xBlockSize |= xBlockAllocatedBit;
+ pxBlock->pxNextFreeBlock = NULL;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ traceMALLOC( pvReturn, xWantedSize );
+
+ #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+ {
+ if( pvReturn == NULL )
+ {
+ extern void vApplicationMallocFailedHook( void );
+ vApplicationMallocFailedHook();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */
+
+ secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
+ return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void * pv )
+{
+ uint8_t * puc = ( uint8_t * ) pv;
+ BlockLink_t * pxLink;
+
+ if( pv != NULL )
+ {
+ /* The memory being freed will have an BlockLink_t structure immediately
+ * before it. */
+ puc -= xHeapStructSize;
+
+ /* This casting is to keep the compiler from issuing warnings. */
+ pxLink = ( void * ) puc;
+
+ /* Check the block is actually allocated. */
+ secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+ secureportASSERT( pxLink->pxNextFreeBlock == NULL );
+
+ if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+ {
+ if( pxLink->pxNextFreeBlock == NULL )
+ {
+ /* The block is being returned to the heap - it is no longer
+ * allocated. */
+ pxLink->xBlockSize &= ~xBlockAllocatedBit;
+
+ secureportDISABLE_NON_SECURE_INTERRUPTS();
+ {
+ /* Add this block to the list of free blocks. */
+ xFreeBytesRemaining += pxLink->xBlockSize;
+ traceFREE( pv, pxLink->xBlockSize );
+ prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+ }
+ secureportENABLE_NON_SECURE_INTERRUPTS();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+ return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetMinimumEverFreeHeapSize( void )
+{
+ return xMinimumEverFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM33/secure/secure_heap.h b/portable/GCC/ARM_CM33/secure/secure_heap.h
index bd42ff9..c13590f 100644
--- a/portable/GCC/ARM_CM33/secure/secure_heap.h
+++ b/portable/GCC/ARM_CM33/secure/secure_heap.h
@@ -1,66 +1,66 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef __SECURE_HEAP_H__
-#define __SECURE_HEAP_H__
-
-/* Standard includes. */
-#include <stdlib.h>
-
-/**
- * @brief Allocates memory from heap.
- *
- * @param[in] xWantedSize The size of the memory to be allocated.
- *
- * @return Pointer to the memory region if the allocation is successful, NULL
- * otherwise.
- */
-void * pvPortMalloc( size_t xWantedSize );
-
-/**
- * @brief Frees the previously allocated memory.
- *
- * @param[in] pv Pointer to the memory to be freed.
- */
-void vPortFree( void * pv );
-
-/**
- * @brief Get the free heap size.
- *
- * @return Free heap size.
- */
-size_t xPortGetFreeHeapSize( void );
-
-/**
- * @brief Get the minimum ever free heap size.
- *
- * @return Minimum ever free heap size.
- */
-size_t xPortGetMinimumEverFreeHeapSize( void );
-
-#endif /* __SECURE_HEAP_H__ */
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef __SECURE_HEAP_H__
+#define __SECURE_HEAP_H__
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/**
+ * @brief Allocates memory from heap.
+ *
+ * @param[in] xWantedSize The size of the memory to be allocated.
+ *
+ * @return Pointer to the memory region if the allocation is successful, NULL
+ * otherwise.
+ */
+void * pvPortMalloc( size_t xWantedSize );
+
+/**
+ * @brief Frees the previously allocated memory.
+ *
+ * @param[in] pv Pointer to the memory to be freed.
+ */
+void vPortFree( void * pv );
+
+/**
+ * @brief Get the free heap size.
+ *
+ * @return Free heap size.
+ */
+size_t xPortGetFreeHeapSize( void );
+
+/**
+ * @brief Get the minimum ever free heap size.
+ *
+ * @return Minimum ever free heap size.
+ */
+size_t xPortGetMinimumEverFreeHeapSize( void );
+
+#endif /* __SECURE_HEAP_H__ */
diff --git a/portable/GCC/ARM_CM33/secure/secure_init.c b/portable/GCC/ARM_CM33/secure/secure_init.c
index d91695b..dc19ebc 100644
--- a/portable/GCC/ARM_CM33/secure/secure_init.c
+++ b/portable/GCC/ARM_CM33/secure/secure_init.c
@@ -1,106 +1,106 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/* Standard includes. */
-#include <stdint.h>
-
-/* Secure init includes. */
-#include "secure_init.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/**
- * @brief Constants required to manipulate the SCB.
- */
-#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */
-#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL )
-#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )
-#define secureinitSCB_AIRCR_PRIS_POS ( 14UL )
-#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS )
-
-/**
- * @brief Constants required to manipulate the FPU.
- */
-#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
-#define secureinitFPCCR_LSPENS_POS ( 29UL )
-#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS )
-#define secureinitFPCCR_TS_POS ( 26UL )
-#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS )
-
-#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */
-#define secureinitNSACR_CP10_POS ( 10UL )
-#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS )
-#define secureinitNSACR_CP11_POS ( 11UL )
-#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS )
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )
-{
- uint32_t ulIPSR;
-
- /* Read the Interrupt Program Status Register (IPSR) value. */
- secureportREAD_IPSR( ulIPSR );
-
- /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
- * when the processor is running in the Thread Mode. */
- if( ulIPSR != 0 )
- {
- *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |
- ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |
- ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK );
- }
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
-{
- uint32_t ulIPSR;
-
- /* Read the Interrupt Program Status Register (IPSR) value. */
- secureportREAD_IPSR( ulIPSR );
-
- /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
- * when the processor is running in the Thread Mode. */
- if( ulIPSR != 0 )
- {
- /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is
- * permitted. CP11 should be programmed to the same value as CP10. */
- *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
-
- /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
- * that we can enable/disable lazy stacking in port.c file. */
- *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );
-
- /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP
- * registers (S16-S31) are also pushed to stack on exception entry and
- * restored on exception return. */
- *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );
- }
-}
-/*-----------------------------------------------------------*/
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Secure init includes. */
+#include "secure_init.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */
+#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL )
+#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )
+#define secureinitSCB_AIRCR_PRIS_POS ( 14UL )
+#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS )
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
+#define secureinitFPCCR_LSPENS_POS ( 29UL )
+#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS )
+#define secureinitFPCCR_TS_POS ( 26UL )
+#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS )
+
+#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */
+#define secureinitNSACR_CP10_POS ( 10UL )
+#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS )
+#define secureinitNSACR_CP11_POS ( 11UL )
+#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS )
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )
+{
+ uint32_t ulIPSR;
+
+ /* Read the Interrupt Program Status Register (IPSR) value. */
+ secureportREAD_IPSR( ulIPSR );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode. */
+ if( ulIPSR != 0 )
+ {
+ *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |
+ ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |
+ ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK );
+ }
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
+{
+ uint32_t ulIPSR;
+
+ /* Read the Interrupt Program Status Register (IPSR) value. */
+ secureportREAD_IPSR( ulIPSR );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode. */
+ if( ulIPSR != 0 )
+ {
+ /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is
+ * permitted. CP11 should be programmed to the same value as CP10. */
+ *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
+
+ /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
+ * that we can enable/disable lazy stacking in port.c file. */
+ *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );
+
+ /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP
+ * registers (S16-S31) are also pushed to stack on exception entry and
+ * restored on exception return. */
+ *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );
+ }
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM33/secure/secure_init.h b/portable/GCC/ARM_CM33/secure/secure_init.h
index e18ba44..21daeda 100644
--- a/portable/GCC/ARM_CM33/secure/secure_init.h
+++ b/portable/GCC/ARM_CM33/secure/secure_init.h
@@ -1,54 +1,54 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef __SECURE_INIT_H__
-#define __SECURE_INIT_H__
-
-/**
- * @brief De-prioritizes the non-secure exceptions.
- *
- * This is needed to ensure that the non-secure PendSV runs at the lowest
- * priority. Context switch is done in the non-secure PendSV handler.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- */
-void SecureInit_DePrioritizeNSExceptions( void );
-
-/**
- * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.
- *
- * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point
- * Registers are not leaked to the non-secure side.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- */
-void SecureInit_EnableNSFPUAccess( void );
-
-#endif /* __SECURE_INIT_H__ */
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef __SECURE_INIT_H__
+#define __SECURE_INIT_H__
+
+/**
+ * @brief De-prioritizes the non-secure exceptions.
+ *
+ * This is needed to ensure that the non-secure PendSV runs at the lowest
+ * priority. Context switch is done in the non-secure PendSV handler.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_DePrioritizeNSExceptions( void );
+
+/**
+ * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.
+ *
+ * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point
+ * Registers are not leaked to the non-secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_EnableNSFPUAccess( void );
+
+#endif /* __SECURE_INIT_H__ */
diff --git a/portable/GCC/ARM_CM33/secure/secure_port_macros.h b/portable/GCC/ARM_CM33/secure/secure_port_macros.h
index 5499054..304913b 100644
--- a/portable/GCC/ARM_CM33/secure/secure_port_macros.h
+++ b/portable/GCC/ARM_CM33/secure/secure_port_macros.h
@@ -1,140 +1,140 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef __SECURE_PORT_MACROS_H__
-#define __SECURE_PORT_MACROS_H__
-
-/**
- * @brief Byte alignment requirements.
- */
-#define secureportBYTE_ALIGNMENT 8
-#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 )
-
-/**
- * @brief Macro to declare a function as non-secure callable.
- */
-#if defined( __IAR_SYSTEMS_ICC__ )
- #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry __root
-#else
- #define secureportNON_SECURE_CALLABLE __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) )
-#endif
-
-/**
- * @brief Set the secure PRIMASK value.
- */
-#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \
- __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )
-
-/**
- * @brief Set the non-secure PRIMASK value.
- */
-#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \
- __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )
-
-/**
- * @brief Read the PSP value in the given variable.
- */
-#define secureportREAD_PSP( pucOutCurrentStackPointer ) \
- __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) )
-
-/**
- * @brief Set the PSP to the given value.
- */
-#define secureportSET_PSP( pucCurrentStackPointer ) \
- __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )
-
-/**
- * @brief Read the PSPLIM value in the given variable.
- */
-#define secureportREAD_PSPLIM( pucOutStackLimit ) \
- __asm volatile ( "mrs %0, psplim" : "=r" ( pucOutStackLimit ) )
-
-/**
- * @brief Set the PSPLIM to the given value.
- */
-#define secureportSET_PSPLIM( pucStackLimit ) \
- __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )
-
-/**
- * @brief Set the NonSecure MSP to the given value.
- */
-#define secureportSET_MSP_NS( pucMainStackPointer ) \
- __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )
-
-/**
- * @brief Set the CONTROL register to the given value.
- */
-#define secureportSET_CONTROL( ulControl ) \
- __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )
-
-/**
- * @brief Read the Interrupt Program Status Register (IPSR) value in the given
- * variable.
- */
-#define secureportREAD_IPSR( ulIPSR ) \
- __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) )
-
-/**
- * @brief PRIMASK value to enable interrupts.
- */
-#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0
-
-/**
- * @brief PRIMASK value to disable interrupts.
- */
-#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1
-
-/**
- * @brief Disable secure interrupts.
- */
-#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
-
-/**
- * @brief Disable non-secure interrupts.
- *
- * This effectively disables context switches.
- */
-#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
-
-/**
- * @brief Enable non-secure interrupts.
- */
-#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )
-
-/**
- * @brief Assert definition.
- */
-#define secureportASSERT( x ) \
- if( ( x ) == 0 ) \
- { \
- secureportDISABLE_SECURE_INTERRUPTS(); \
- secureportDISABLE_NON_SECURE_INTERRUPTS(); \
- for( ; ; ) {; } \
- }
-
-#endif /* __SECURE_PORT_MACROS_H__ */
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef __SECURE_PORT_MACROS_H__
+#define __SECURE_PORT_MACROS_H__
+
+/**
+ * @brief Byte alignment requirements.
+ */
+#define secureportBYTE_ALIGNMENT 8
+#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 )
+
+/**
+ * @brief Macro to declare a function as non-secure callable.
+ */
+#if defined( __IAR_SYSTEMS_ICC__ )
+ #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry __root
+#else
+ #define secureportNON_SECURE_CALLABLE __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) )
+#endif
+
+/**
+ * @brief Set the secure PRIMASK value.
+ */
+#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \
+ __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Set the non-secure PRIMASK value.
+ */
+#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \
+ __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Read the PSP value in the given variable.
+ */
+#define secureportREAD_PSP( pucOutCurrentStackPointer ) \
+ __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSP to the given value.
+ */
+#define secureportSET_PSP( pucCurrentStackPointer ) \
+ __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )
+
+/**
+ * @brief Read the PSPLIM value in the given variable.
+ */
+#define secureportREAD_PSPLIM( pucOutStackLimit ) \
+ __asm volatile ( "mrs %0, psplim" : "=r" ( pucOutStackLimit ) )
+
+/**
+ * @brief Set the PSPLIM to the given value.
+ */
+#define secureportSET_PSPLIM( pucStackLimit ) \
+ __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )
+
+/**
+ * @brief Set the NonSecure MSP to the given value.
+ */
+#define secureportSET_MSP_NS( pucMainStackPointer ) \
+ __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )
+
+/**
+ * @brief Set the CONTROL register to the given value.
+ */
+#define secureportSET_CONTROL( ulControl ) \
+ __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )
+
+/**
+ * @brief Read the Interrupt Program Status Register (IPSR) value in the given
+ * variable.
+ */
+#define secureportREAD_IPSR( ulIPSR ) \
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) )
+
+/**
+ * @brief PRIMASK value to enable interrupts.
+ */
+#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0
+
+/**
+ * @brief PRIMASK value to disable interrupts.
+ */
+#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1
+
+/**
+ * @brief Disable secure interrupts.
+ */
+#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Disable non-secure interrupts.
+ *
+ * This effectively disables context switches.
+ */
+#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Enable non-secure interrupts.
+ */
+#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Assert definition.
+ */
+#define secureportASSERT( x ) \
+ if( ( x ) == 0 ) \
+ { \
+ secureportDISABLE_SECURE_INTERRUPTS(); \
+ secureportDISABLE_NON_SECURE_INTERRUPTS(); \
+ for( ; ; ) {; } \
+ }
+
+#endif /* __SECURE_PORT_MACROS_H__ */
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
index 21b515e..a78529d 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
@@ -1,365 +1,365 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/* Standard includes. */
-#include <stdint.h>
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
- * is defined correctly and privileged functions are placed in correct sections. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Portasm includes. */
-#include "portasm.h"
-
-/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
- * header files. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " ldr r2, pxCurrentTCBConst2 \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r2] \n"/* Read pxCurrentTCB. */
- " ldr r0, [r1] \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
- " \n"
- #if ( configENABLE_MPU == 1 )
- " dmb \n"/* Complete outstanding transfers before disabling MPU. */
- " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
- " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
- " bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
- " str r4, [r2] \n"/* Disable MPU. */
- " \n"
- " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
- " ldr r3, [r1] \n"/* r3 = *r1 i.e. r3 = MAIR0. */
- " ldr r2, xMAIR0Const2 \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
- " str r3, [r2] \n"/* Program MAIR0. */
- " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
- " movs r3, #4 \n"/* r3 = 4. */
- " str r3, [r2] \n"/* Program RNR = 4. */
- " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
- " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
- " ldmia r1!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
- " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
- " \n"
- #if ( configTOTAL_MPU_REGIONS == 16 )
- " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
- " movs r3, #8 \n"/* r3 = 8. */
- " str r3, [r2] \n"/* Program RNR = 8. */
- " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
- " ldmia r1!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
- " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
- " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
- " movs r3, #12 \n"/* r3 = 12. */
- " str r3, [r2] \n"/* Program RNR = 12. */
- " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
- " ldmia r1!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
- " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
- #endif /* configTOTAL_MPU_REGIONS == 16 */
- " \n"
- " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
- " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
- " orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
- " str r4, [r2] \n"/* Enable MPU. */
- " dsb \n"/* Force memory writes before continuing. */
- #endif /* configENABLE_MPU */
- " \n"
- #if ( configENABLE_MPU == 1 )
- " ldm r0!, {r1-r3} \n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
- " msr psplim, r1 \n"/* Set this task's PSPLIM value. */
- " msr control, r2 \n"/* Set this task's CONTROL value. */
- " adds r0, #32 \n"/* Discard everything up to r0. */
- " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
- " isb \n"
- " mov r0, #0 \n"
- " msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */
- " bx r3 \n"/* Finally, branch to EXC_RETURN. */
- #else /* configENABLE_MPU */
- " ldm r0!, {r1-r2} \n"/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
- " msr psplim, r1 \n"/* Set this task's PSPLIM value. */
- " movs r1, #2 \n"/* r1 = 2. */
- " msr CONTROL, r1 \n"/* Switch to use PSP in the thread mode. */
- " adds r0, #32 \n"/* Discard everything up to r0. */
- " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
- " isb \n"
- " mov r0, #0 \n"
- " msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */
- " bx r2 \n"/* Finally, branch to EXC_RETURN. */
- #endif /* configENABLE_MPU */
- " \n"
- " .align 4 \n"
- "pxCurrentTCBConst2: .word pxCurrentTCB \n"
- #if ( configENABLE_MPU == 1 )
- "xMPUCTRLConst2: .word 0xe000ed94 \n"
- "xMAIR0Const2: .word 0xe000edc0 \n"
- "xRNRConst2: .word 0xe000ed98 \n"
- "xRBARConst2: .word 0xe000ed9c \n"
- #endif /* configENABLE_MPU */
- );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " mrs r0, control \n"/* r0 = CONTROL. */
- " tst r0, #1 \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
- " ite ne \n"
- " movne r0, #0 \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
- " moveq r0, #1 \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
- " bx lr \n"/* Return. */
- " \n"
- " .align 4 \n"
- ::: "r0", "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " mrs r0, control \n"/* Read the CONTROL register. */
- " bic r0, #1 \n"/* Clear the bit 0. */
- " msr control, r0 \n"/* Write back the new CONTROL value. */
- " bx lr \n"/* Return to the caller. */
- ::: "r0", "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-void vResetPrivilege( void ) /* __attribute__ (( naked )) */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " mrs r0, control \n"/* r0 = CONTROL. */
- " orr r0, #1 \n"/* r0 = r0 | 1. */
- " msr control, r0 \n"/* CONTROL = r0. */
- " bx lr \n"/* Return to the caller. */
- ::: "r0", "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " ldr r0, xVTORConst \n"/* Use the NVIC offset register to locate the stack. */
- " ldr r0, [r0] \n"/* Read the VTOR register which gives the address of vector table. */
- " ldr r0, [r0] \n"/* The first entry in vector table is stack pointer. */
- " msr msp, r0 \n"/* Set the MSP back to the start of the stack. */
- " cpsie i \n"/* Globally enable interrupts. */
- " cpsie f \n"
- " dsb \n"
- " isb \n"
- " svc %0 \n"/* System call to start the first task. */
- " nop \n"
- " \n"
- " .align 4 \n"
- "xVTORConst: .word 0xe000ed08 \n"
- ::"i" ( portSVC_START_SCHEDULER ) : "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " mrs r0, basepri \n"/* r0 = basepri. Return original basepri value. */
- " mov r1, %0 \n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- " msr basepri, r1 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- " dsb \n"
- " isb \n"
- " bx lr \n"/* Return. */
- ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " msr basepri, r0 \n"/* basepri = ulMask. */
- " dsb \n"
- " isb \n"
- " bx lr \n"/* Return. */
- ::: "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " mrs r0, psp \n"/* Read PSP in r0. */
- #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
- " tst lr, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
- " it eq \n"
- " vstmdbeq r0!, {s16-s31} \n"/* Store the additional FP context registers which are not saved automatically. */
- #endif /* configENABLE_FPU || configENABLE_MVE */
- #if ( configENABLE_MPU == 1 )
- " mrs r1, psplim \n"/* r1 = PSPLIM. */
- " mrs r2, control \n"/* r2 = CONTROL. */
- " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */
- " stmdb r0!, {r1-r11} \n"/* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */
- #else /* configENABLE_MPU */
- " mrs r2, psplim \n"/* r2 = PSPLIM. */
- " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */
- " stmdb r0!, {r2-r11} \n"/* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
- #endif /* configENABLE_MPU */
- " \n"
- " ldr r2, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r2] \n"/* Read pxCurrentTCB. */
- " str r0, [r1] \n"/* Save the new top of stack in TCB. */
- " \n"
- " mov r0, %0 \n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
- " msr basepri, r0 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- " dsb \n"
- " isb \n"
- " bl vTaskSwitchContext \n"
- " mov r0, #0 \n"/* r0 = 0. */
- " msr basepri, r0 \n"/* Enable interrupts. */
- " \n"
- " ldr r2, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r2] \n"/* Read pxCurrentTCB. */
- " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
- " \n"
- #if ( configENABLE_MPU == 1 )
- " dmb \n"/* Complete outstanding transfers before disabling MPU. */
- " ldr r2, xMPUCTRLConst \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
- " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
- " bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
- " str r4, [r2] \n"/* Disable MPU. */
- " \n"
- " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
- " ldr r3, [r1] \n"/* r3 = *r1 i.e. r3 = MAIR0. */
- " ldr r2, xMAIR0Const \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
- " str r3, [r2] \n"/* Program MAIR0. */
- " ldr r2, xRNRConst \n"/* r2 = 0xe000ed98 [Location of RNR]. */
- " movs r3, #4 \n"/* r3 = 4. */
- " str r3, [r2] \n"/* Program RNR = 4. */
- " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
- " ldr r2, xRBARConst \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
- " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
- " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
- " \n"
- #if ( configTOTAL_MPU_REGIONS == 16 )
- " ldr r2, xRNRConst \n"/* r2 = 0xe000ed98 [Location of RNR]. */
- " movs r3, #8 \n"/* r3 = 8. */
- " str r3, [r2] \n"/* Program RNR = 8. */
- " ldr r2, xRBARConst \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
- " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
- " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
- " ldr r2, xRNRConst \n"/* r2 = 0xe000ed98 [Location of RNR]. */
- " movs r3, #12 \n"/* r3 = 12. */
- " str r3, [r2] \n"/* Program RNR = 12. */
- " ldr r2, xRBARConst \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
- " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
- " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
- #endif /* configTOTAL_MPU_REGIONS == 16 */
- " \n"
- " ldr r2, xMPUCTRLConst \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
- " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
- " orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
- " str r4, [r2] \n"/* Enable MPU. */
- " dsb \n"/* Force memory writes before continuing. */
- #endif /* configENABLE_MPU */
- " \n"
- #if ( configENABLE_MPU == 1 )
- " ldmia r0!, {r1-r11} \n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */
- #else /* configENABLE_MPU */
- " ldmia r0!, {r2-r11} \n"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
- #endif /* configENABLE_MPU */
- " \n"
- #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
- " tst r3, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
- " it eq \n"
- " vldmiaeq r0!, {s16-s31} \n"/* Restore the additional FP context registers which are not restored automatically. */
- #endif /* configENABLE_FPU || configENABLE_MVE */
- " \n"
- #if ( configENABLE_MPU == 1 )
- " msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */
- " msr control, r2 \n"/* Restore the CONTROL register value for the task. */
- #else /* configENABLE_MPU */
- " msr psplim, r2 \n"/* Restore the PSPLIM register value for the task. */
- #endif /* configENABLE_MPU */
- " msr psp, r0 \n"/* Remember the new top of stack for the task. */
- " bx r3 \n"
- " \n"
- " .align 4 \n"
- "pxCurrentTCBConst: .word pxCurrentTCB \n"
- #if ( configENABLE_MPU == 1 )
- "xMPUCTRLConst: .word 0xe000ed94 \n"
- "xMAIR0Const: .word 0xe000edc0 \n"
- "xRNRConst: .word 0xe000ed98 \n"
- "xRBARConst: .word 0xe000ed9c \n"
- #endif /* configENABLE_MPU */
- ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
- );
-}
-/*-----------------------------------------------------------*/
-
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " tst lr, #4 \n"
- " ite eq \n"
- " mrseq r0, msp \n"
- " mrsne r0, psp \n"
- " ldr r1, svchandler_address_const \n"
- " bx r1 \n"
- " \n"
- " .align 4 \n"
- "svchandler_address_const: .word vPortSVCHandler_C \n"
- );
-}
-/*-----------------------------------------------------------*/
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
+ * is defined correctly and privileged functions are placed in correct sections. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Portasm includes. */
+#include "portasm.h"
+
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
+ * header files. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " ldr r2, pxCurrentTCBConst2 \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r2] \n"/* Read pxCurrentTCB. */
+ " ldr r0, [r1] \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+ " \n"
+ #if ( configENABLE_MPU == 1 )
+ " dmb \n"/* Complete outstanding transfers before disabling MPU. */
+ " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
+ " bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+ " str r4, [r2] \n"/* Disable MPU. */
+ " \n"
+ " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+ " ldr r3, [r1] \n"/* r3 = *r1 i.e. r3 = MAIR0. */
+ " ldr r2, xMAIR0Const2 \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
+ " str r3, [r2] \n"/* Program MAIR0. */
+ " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
+ " movs r3, #4 \n"/* r3 = 4. */
+ " str r3, [r2] \n"/* Program RNR = 4. */
+ " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+ " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
+ " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+ " \n"
+ #if ( configTOTAL_MPU_REGIONS == 16 )
+ " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
+ " movs r3, #8 \n"/* r3 = 8. */
+ " str r3, [r2] \n"/* Program RNR = 8. */
+ " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
+ " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+ " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
+ " movs r3, #12 \n"/* r3 = 12. */
+ " str r3, [r2] \n"/* Program RNR = 12. */
+ " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
+ " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+ #endif /* configTOTAL_MPU_REGIONS == 16 */
+ " \n"
+ " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
+ " orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+ " str r4, [r2] \n"/* Enable MPU. */
+ " dsb \n"/* Force memory writes before continuing. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ #if ( configENABLE_MPU == 1 )
+ " ldm r0!, {r1-r3} \n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
+ " msr psplim, r1 \n"/* Set this task's PSPLIM value. */
+ " msr control, r2 \n"/* Set this task's CONTROL value. */
+ " adds r0, #32 \n"/* Discard everything up to r0. */
+ " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
+ " isb \n"
+ " mov r0, #0 \n"
+ " msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */
+ " bx r3 \n"/* Finally, branch to EXC_RETURN. */
+ #else /* configENABLE_MPU */
+ " ldm r0!, {r1-r2} \n"/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+ " msr psplim, r1 \n"/* Set this task's PSPLIM value. */
+ " movs r1, #2 \n"/* r1 = 2. */
+ " msr CONTROL, r1 \n"/* Switch to use PSP in the thread mode. */
+ " adds r0, #32 \n"/* Discard everything up to r0. */
+ " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
+ " isb \n"
+ " mov r0, #0 \n"
+ " msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */
+ " bx r2 \n"/* Finally, branch to EXC_RETURN. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ " .align 4 \n"
+ "pxCurrentTCBConst2: .word pxCurrentTCB \n"
+ #if ( configENABLE_MPU == 1 )
+ "xMPUCTRLConst2: .word 0xe000ed94 \n"
+ "xMAIR0Const2: .word 0xe000edc0 \n"
+ "xRNRConst2: .word 0xe000ed98 \n"
+ "xRBARConst2: .word 0xe000ed9c \n"
+ #endif /* configENABLE_MPU */
+ );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, control \n"/* r0 = CONTROL. */
+ " tst r0, #1 \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+ " ite ne \n"
+ " movne r0, #0 \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+ " moveq r0, #1 \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+ " bx lr \n"/* Return. */
+ " \n"
+ " .align 4 \n"
+ ::: "r0", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, control \n"/* Read the CONTROL register. */
+ " bic r0, #1 \n"/* Clear the bit 0. */
+ " msr control, r0 \n"/* Write back the new CONTROL value. */
+ " bx lr \n"/* Return to the caller. */
+ ::: "r0", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, control \n"/* r0 = CONTROL. */
+ " orr r0, #1 \n"/* r0 = r0 | 1. */
+ " msr control, r0 \n"/* CONTROL = r0. */
+ " bx lr \n"/* Return to the caller. */
+ ::: "r0", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " ldr r0, xVTORConst \n"/* Use the NVIC offset register to locate the stack. */
+ " ldr r0, [r0] \n"/* Read the VTOR register which gives the address of vector table. */
+ " ldr r0, [r0] \n"/* The first entry in vector table is stack pointer. */
+ " msr msp, r0 \n"/* Set the MSP back to the start of the stack. */
+ " cpsie i \n"/* Globally enable interrupts. */
+ " cpsie f \n"
+ " dsb \n"
+ " isb \n"
+ " svc %0 \n"/* System call to start the first task. */
+ " nop \n"
+ " \n"
+ " .align 4 \n"
+ "xVTORConst: .word 0xe000ed08 \n"
+ ::"i" ( portSVC_START_SCHEDULER ) : "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, basepri \n"/* r0 = basepri. Return original basepri value. */
+ " mov r1, %0 \n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " msr basepri, r1 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " dsb \n"
+ " isb \n"
+ " bx lr \n"/* Return. */
+ ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " msr basepri, r0 \n"/* basepri = ulMask. */
+ " dsb \n"
+ " isb \n"
+ " bx lr \n"/* Return. */
+ ::: "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, psp \n"/* Read PSP in r0. */
+ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ " tst lr, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+ " it eq \n"
+ " vstmdbeq r0!, {s16-s31} \n"/* Store the additional FP context registers which are not saved automatically. */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
+ #if ( configENABLE_MPU == 1 )
+ " mrs r1, psplim \n"/* r1 = PSPLIM. */
+ " mrs r2, control \n"/* r2 = CONTROL. */
+ " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */
+ " stmdb r0!, {r1-r11} \n"/* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */
+ #else /* configENABLE_MPU */
+ " mrs r2, psplim \n"/* r2 = PSPLIM. */
+ " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */
+ " stmdb r0!, {r2-r11} \n"/* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ " ldr r2, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r2] \n"/* Read pxCurrentTCB. */
+ " str r0, [r1] \n"/* Save the new top of stack in TCB. */
+ " \n"
+ " mov r0, %0 \n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+ " msr basepri, r0 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " dsb \n"
+ " isb \n"
+ " bl vTaskSwitchContext \n"
+ " mov r0, #0 \n"/* r0 = 0. */
+ " msr basepri, r0 \n"/* Enable interrupts. */
+ " \n"
+ " ldr r2, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r2] \n"/* Read pxCurrentTCB. */
+ " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+ " \n"
+ #if ( configENABLE_MPU == 1 )
+ " dmb \n"/* Complete outstanding transfers before disabling MPU. */
+ " ldr r2, xMPUCTRLConst \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
+ " bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+ " str r4, [r2] \n"/* Disable MPU. */
+ " \n"
+ " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+ " ldr r3, [r1] \n"/* r3 = *r1 i.e. r3 = MAIR0. */
+ " ldr r2, xMAIR0Const \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
+ " str r3, [r2] \n"/* Program MAIR0. */
+ " ldr r2, xRNRConst \n"/* r2 = 0xe000ed98 [Location of RNR]. */
+ " movs r3, #4 \n"/* r3 = 4. */
+ " str r3, [r2] \n"/* Program RNR = 4. */
+ " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+ " ldr r2, xRBARConst \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
+ " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+ " \n"
+ #if ( configTOTAL_MPU_REGIONS == 16 )
+ " ldr r2, xRNRConst \n"/* r2 = 0xe000ed98 [Location of RNR]. */
+ " movs r3, #8 \n"/* r3 = 8. */
+ " str r3, [r2] \n"/* Program RNR = 8. */
+ " ldr r2, xRBARConst \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
+ " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+ " ldr r2, xRNRConst \n"/* r2 = 0xe000ed98 [Location of RNR]. */
+ " movs r3, #12 \n"/* r3 = 12. */
+ " str r3, [r2] \n"/* Program RNR = 12. */
+ " ldr r2, xRBARConst \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
+ " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+ #endif /* configTOTAL_MPU_REGIONS == 16 */
+ " \n"
+ " ldr r2, xMPUCTRLConst \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
+ " orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+ " str r4, [r2] \n"/* Enable MPU. */
+ " dsb \n"/* Force memory writes before continuing. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ #if ( configENABLE_MPU == 1 )
+ " ldmia r0!, {r1-r11} \n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */
+ #else /* configENABLE_MPU */
+ " ldmia r0!, {r2-r11} \n"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ " tst r3, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+ " it eq \n"
+ " vldmiaeq r0!, {s16-s31} \n"/* Restore the additional FP context registers which are not restored automatically. */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
+ " \n"
+ #if ( configENABLE_MPU == 1 )
+ " msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */
+ " msr control, r2 \n"/* Restore the CONTROL register value for the task. */
+ #else /* configENABLE_MPU */
+ " msr psplim, r2 \n"/* Restore the PSPLIM register value for the task. */
+ #endif /* configENABLE_MPU */
+ " msr psp, r0 \n"/* Remember the new top of stack for the task. */
+ " bx r3 \n"
+ " \n"
+ " .align 4 \n"
+ "pxCurrentTCBConst: .word pxCurrentTCB \n"
+ #if ( configENABLE_MPU == 1 )
+ "xMPUCTRLConst: .word 0xe000ed94 \n"
+ "xMAIR0Const: .word 0xe000edc0 \n"
+ "xRNRConst: .word 0xe000ed98 \n"
+ "xRBARConst: .word 0xe000ed9c \n"
+ #endif /* configENABLE_MPU */
+ ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+ );
+}
+/*-----------------------------------------------------------*/
+
+void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " tst lr, #4 \n"
+ " ite eq \n"
+ " mrseq r0, msp \n"
+ " mrsne r0, psp \n"
+ " ldr r1, svchandler_address_const \n"
+ " bx r1 \n"
+ " \n"
+ " .align 4 \n"
+ "svchandler_address_const: .word vPortSVCHandler_C \n"
+ );
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h b/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h
index b37f6d1..ecd86b9 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h
@@ -1,114 +1,114 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef __PORT_ASM_H__
-#define __PORT_ASM_H__
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-
-/* MPU wrappers includes. */
-#include "mpu_wrappers.h"
-
-/**
- * @brief Restore the context of the first task so that the first task starts
- * executing.
- */
-void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
-BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
-
-/**
- * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
- * register.
- *
- * @note This is a privileged function and should only be called from the kenrel
- * code.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- * Bit[0] = 0 --> The processor is running privileged
- * Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- * Bit[0] = 0 --> The processor is running privileged
- * Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vResetPrivilege( void ) __attribute__( ( naked ) );
-
-/**
- * @brief Starts the first task.
- */
-void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Disables interrupts.
- */
-uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Enables interrupts.
- */
-void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief PendSV Exception handler.
- */
-void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief SVC Handler.
- */
-void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Allocate a Secure context for the calling task.
- *
- * @param[in] ulSecureStackSize The size of the stack to be allocated on the
- * secure side for the calling task.
- */
-void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );
-
-/**
- * @brief Free the task's secure context.
- *
- * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
- */
-void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-#endif /* __PORT_ASM_H__ */
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
index 766dfb0..943c665 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
@@ -1,66 +1,66 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "portmacrocommon.h"
-
-/*------------------------------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *------------------------------------------------------------------------------
- */
-
-/**
- * Architecture specifics.
- */
-#define portARCH_NAME "Cortex-M33"
-#define portDONT_DISCARD __attribute__( ( used ) )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Critical section management.
- */
-#define portDISABLE_INTERRUPTS() ulSetInterruptMask()
-#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
-/*-----------------------------------------------------------*/
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* PORTMACRO_H */
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "portmacrocommon.h"
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME "Cortex-M33"
+#define portDONT_DISCARD __attribute__( ( used ) )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portDISABLE_INTERRUPTS() ulSetInterruptMask()
+#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
index 4b1f99b..51e21ea 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
@@ -155,9 +155,9 @@
* 8-bit values encoded as follows:
* Bit[7:4] - 0000 - Device Memory
* Bit[3:2] - 00 --> Device-nGnRnE
- * 01 --> Device-nGnRE
- * 10 --> Device-nGRE
- * 11 --> Device-GRE
+ * 01 --> Device-nGnRE
+ * 10 --> Device-nGRE
+ * 11 --> Device-GRE
* Bit[1:0] - 00, Reserved.
*/
#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
diff --git a/portable/GCC/ARM_CM3_MPU/port.c b/portable/GCC/ARM_CM3_MPU/port.c
index 7b61127..e0f1d17 100644
--- a/portable/GCC/ARM_CM3_MPU/port.c
+++ b/portable/GCC/ARM_CM3_MPU/port.c
@@ -1,921 +1,921 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the ARM CM3 MPU port.
-*----------------------------------------------------------*/
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
- * all the API functions to use the MPU wrappers. That should only be done when
- * task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#ifndef configSYSTICK_CLOCK_HZ
- #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
- /* Ensure the SysTick is clocked at the same frequency as the core. */
- #define portNVIC_SYSTICK_CLK ( 1UL << 2UL )
-#else
-
-/* The way the SysTick is clocked is not modified in case it is not the same
- * as the core. */
- #define portNVIC_SYSTICK_CLK ( 0 )
-#endif
-
-#ifndef configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS
- #warning "configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS is not defined. We recommend defining it to 0 in FreeRTOSConfig.h for better security."
- #define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS 1
-#endif
-
-/* Constants required to access and manipulate the NVIC. */
-#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
-#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
-#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
-#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
-#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) )
-#define portNVIC_SYS_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
-#define portNVIC_MEM_FAULT_ENABLE ( 1UL << 16UL )
-
-/* Constants required to access and manipulate the MPU. */
-#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_REGION_BASE_ADDRESS_REG ( *( ( volatile uint32_t * ) 0xe000ed9C ) )
-#define portMPU_REGION_ATTRIBUTE_REG ( *( ( volatile uint32_t * ) 0xe000edA0 ) )
-#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */
-#define portMPU_ENABLE ( 0x01UL )
-#define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL )
-#define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL )
-#define portMPU_REGION_VALID ( 0x10UL )
-#define portMPU_REGION_ENABLE ( 0x01UL )
-#define portPERIPHERALS_START_ADDRESS 0x40000000UL
-#define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL
-
-/* Constants required to access and manipulate the SysTick. */
-#define portNVIC_SYSTICK_INT ( 0x00000002UL )
-#define portNVIC_SYSTICK_ENABLE ( 0x00000001UL )
-#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
-#define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
-
-/* Constants required to set up the initial stack. */
-#define portINITIAL_XPSR ( 0x01000000 )
-#define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 )
-#define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 )
-
-/* Constants required to check the validity of an interrupt priority. */
-#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
-#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
-#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
-#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
-#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
-#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
-#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
-#define portPRIGROUP_SHIFT ( 8UL )
-
-/* Offsets in the stack to the parameters when inside the SVC handler. */
-#define portOFFSET_TO_PC ( 6 )
-
-/* For strict compliance with the Cortex-M spec the task start address should
- * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
-#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
-/*-----------------------------------------------------------*/
-
-/*
- * Configure a number of standard MPU regions that are used by all tasks.
- */
-static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Return the smallest MPU region size that a given number of bytes will fit
- * into. The region size is returned as the value that should be programmed
- * into the region attribute register for that region.
- */
-static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
-
-/*
- * Setup the timer to generate the tick interrupts. The implementation in this
- * file is weak to allow application writers to change the timer used to
- * generate the tick interrupt.
- */
-void vPortSetupTimerInterrupt( void );
-
-/*
- * Standard FreeRTOS exception handlers.
- */
-void xPortPendSVHandler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-void xPortSysTickHandler( void ) __attribute__( ( optimize( "3" ) ) ) PRIVILEGED_FUNCTION;
-void vPortSVCHandler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/*
- * Starts the scheduler by restoring the context of the first task to run.
- */
-static void prvRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/*
- * C portion of the SVC handler. The SVC handler is split between an asm entry
- * and a C wrapper for simplicity of coding and maintenance.
- */
-static void prvSVCHandler( uint32_t * pulRegisters ) __attribute__( ( noinline ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
-BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- * Bit[0] = 0 --> The processor is running privileged
- * Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vResetPrivilege( void ) __attribute__( ( naked ) );
-
-/**
- * @brief Enter critical section.
- */
-#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
- void vPortEnterCritical( void ) FREERTOS_SYSTEM_CALL;
-#else
- void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
-#endif
-
-/**
- * @brief Exit from critical section.
- */
-#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
- void vPortExitCritical( void ) FREERTOS_SYSTEM_CALL;
-#else
- void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
-#endif
-/*-----------------------------------------------------------*/
-
-/* Each task maintains its own interrupt status in the critical nesting
- * variable. Note this is not saved as part of the task context as context
- * switches can only occur when uxCriticalNesting is zero. */
-static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
-
-/*
- * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
- * FreeRTOS API functions are not called from interrupts that have been assigned
- * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
- */
-#if ( configASSERT_DEFINED == 1 )
- static uint8_t ucMaxSysCallPriority = 0;
- static uint32_t ulMaxPRIGROUPValue = 0;
- static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
-#endif /* configASSERT_DEFINED */
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters,
- BaseType_t xRunPrivileged )
-{
- /* Simulate the stack frame as it would be created by a context switch
- * interrupt. */
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
- *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
- pxTopOfStack--;
- *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
- pxTopOfStack--;
- *pxTopOfStack = 0; /* LR */
- pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
-
- if( xRunPrivileged == pdTRUE )
- {
- *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;
- }
- else
- {
- *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;
- }
-
- return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-void vPortSVCHandler( void )
-{
- /* Assumes psp was in use. */
- __asm volatile
- (
- #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */
- " tst lr, #4 \n"
- " ite eq \n"
- " mrseq r0, msp \n"
- " mrsne r0, psp \n"
- #else
- " mrs r0, psp \n"
- #endif
- " b %0 \n"
- ::"i" ( prvSVCHandler ) : "r0", "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-static void prvSVCHandler( uint32_t * pulParam )
-{
- uint8_t ucSVCNumber;
- uint32_t ulPC;
-
- #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
- #if defined( __ARMCC_VERSION )
-
- /* Declaration when these variable are defined in code instead of being
- * exported from linker scripts. */
- extern uint32_t * __syscalls_flash_start__;
- extern uint32_t * __syscalls_flash_end__;
- #else
- /* Declaration when these variable are exported from linker scripts. */
- extern uint32_t __syscalls_flash_start__[];
- extern uint32_t __syscalls_flash_end__[];
- #endif /* #if defined( __ARMCC_VERSION ) */
- #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
-
- /* The stack contains: r0, r1, r2, r3, r12, LR, PC and xPSR. The first
- * argument (r0) is pulParam[ 0 ]. */
- ulPC = pulParam[ portOFFSET_TO_PC ];
- ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
-
- switch( ucSVCNumber )
- {
- case portSVC_START_SCHEDULER:
- portNVIC_SHPR2_REG |= portNVIC_SVC_PRI;
- prvRestoreContextOfFirstTask();
- break;
-
- case portSVC_YIELD:
- portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
-
- /* Barriers are normally not required
- * but do ensure the code is completely
- * within the specified behaviour for the
- * architecture. */
- __asm volatile ( "dsb" ::: "memory" );
- __asm volatile ( "isb" );
-
- break;
-
-
- #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
- case portSVC_RAISE_PRIVILEGE: /* Only raise the privilege, if the
- * svc was raised from any of the
- * system calls. */
-
- if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
- ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
- {
- __asm volatile
- (
- " mrs r1, control \n"/* Obtain current control value. */
- " bic r1, #1 \n"/* Set privilege bit. */
- " msr control, r1 \n"/* Write back new control value. */
- ::: "r1", "memory"
- );
- }
-
- break;
- #else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
- case portSVC_RAISE_PRIVILEGE:
- __asm volatile
- (
- " mrs r1, control \n"/* Obtain current control value. */
- " bic r1, #1 \n"/* Set privilege bit. */
- " msr control, r1 \n"/* Write back new control value. */
- ::: "r1", "memory"
- );
- break;
- #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
-
- default: /* Unknown SVC call. */
- break;
- }
-}
-/*-----------------------------------------------------------*/
-
-static void prvRestoreContextOfFirstTask( void )
-{
- __asm volatile
- (
- " ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */
- " ldr r0, [r0] \n"
- " ldr r0, [r0] \n"
- " msr msp, r0 \n"/* Set the msp back to the start of the stack. */
- " ldr r3, pxCurrentTCBConst2 \n"/* Restore the context. */
- " ldr r1, [r3] \n"
- " ldr r0, [r1] \n"/* The first item in the TCB is the task top of stack. */
- " add r1, r1, #4 \n"/* Move onto the second item in the TCB... */
- " \n"
- " dmb \n"/* Complete outstanding transfers before disabling MPU. */
- " ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */
- " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */
- " bic r3, #1 \n"/* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
- " str r3, [r2] \n"/* Disable MPU. */
- " \n"
- " ldr r2, =0xe000ed9c \n"/* Region Base Address register. */
- " ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers. */
- " stmia r2!, {r4-r11} \n"/* Write 4 sets of MPU registers. */
- " \n"
- " ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */
- " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */
- " orr r3, #1 \n"/* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
- " str r3, [r2] \n"/* Enable MPU. */
- " dsb \n"/* Force memory writes before continuing. */
- " \n"
- " ldmia r0!, {r3, r4-r11} \n"/* Pop the registers that are not automatically saved on exception entry. */
- " msr control, r3 \n"
- " msr psp, r0 \n"/* Restore the task stack pointer. */
- " mov r0, #0 \n"
- " msr basepri, r0 \n"
- " ldr r14, =0xfffffffd \n"/* Load exec return code. */
- " bx r14 \n"
- " \n"
- " .ltorg \n"/* Assemble current literal pool to avoid offset-out-of-bound errors with lto. */
- " .align 4 \n"
- "pxCurrentTCBConst2: .word pxCurrentTCB \n"
- );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-BaseType_t xPortStartScheduler( void )
-{
- /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See
- * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
- configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
-
- #if ( configASSERT_DEFINED == 1 )
- {
- volatile uint32_t ulOriginalPriority;
- volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
- volatile uint8_t ucMaxPriorityValue;
-
- /* Determine the maximum priority from which ISR safe FreeRTOS API
- * functions can be called. ISR safe functions are those that end in
- * "FromISR". FreeRTOS maintains separate thread and ISR API functions
- * to ensure interrupt entry is as fast and simple as possible.
- *
- * Save the interrupt priority value that is about to be clobbered. */
- ulOriginalPriority = *pucFirstUserPriorityRegister;
-
- /* Determine the number of priority bits available. First write to all
- * possible bits. */
- *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
-
- /* Read the value back to see how many bits stuck. */
- ucMaxPriorityValue = *pucFirstUserPriorityRegister;
-
- /* Use the same mask on the maximum system call priority. */
- ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
-
- /* Calculate the maximum acceptable priority group value for the number
- * of bits read back. */
- ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
-
- while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
- {
- ulMaxPRIGROUPValue--;
- ucMaxPriorityValue <<= ( uint8_t ) 0x01;
- }
-
- #ifdef __NVIC_PRIO_BITS
- {
- /* Check the CMSIS configuration that defines the number of
- * priority bits matches the number of priority bits actually queried
- * from the hardware. */
- configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
- }
- #endif
-
- #ifdef configPRIO_BITS
- {
- /* Check the FreeRTOS configuration that defines the number of
- * priority bits matches the number of priority bits actually queried
- * from the hardware. */
- configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
- }
- #endif
-
- /* Shift the priority group value back to its position within the AIRCR
- * register. */
- ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
- ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
- /* Restore the clobbered interrupt priority register to its original
- * value. */
- *pucFirstUserPriorityRegister = ulOriginalPriority;
- }
- #endif /* configASSERT_DEFINED */
-
- /* Make PendSV and SysTick the same priority as the kernel, and the SVC
- * handler higher priority so it can be used to exit a critical section (where
- * lower priorities are masked). */
- portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
- portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
-
- /* Configure the regions in the MPU that are common to all tasks. */
- prvSetupMPU();
-
- /* Start the timer that generates the tick ISR. Interrupts are disabled
- * here already. */
- vPortSetupTimerInterrupt();
-
- /* Initialise the critical nesting count ready for the first task. */
- uxCriticalNesting = 0;
-
- /* Start the first task. */
- __asm volatile (
- " ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */
- " ldr r0, [r0] \n"
- " ldr r0, [r0] \n"
- " msr msp, r0 \n"/* Set the msp back to the start of the stack. */
- " cpsie i \n"/* Globally enable interrupts. */
- " cpsie f \n"
- " dsb \n"
- " isb \n"
- " svc %0 \n"/* System call to start first task. */
- " nop \n"
- " .ltorg \n"
- ::"i" ( portSVC_START_SCHEDULER ) : "memory" );
-
- /* Should not get here! */
- return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
- /* Not implemented in ports where there is nothing to return to.
- * Artificially force an assert. */
- configASSERT( uxCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
- if( portIS_PRIVILEGED() == pdFALSE )
- {
- portRAISE_PRIVILEGE();
- portMEMORY_BARRIER();
-
- portDISABLE_INTERRUPTS();
- uxCriticalNesting++;
- portMEMORY_BARRIER();
-
- portRESET_PRIVILEGE();
- portMEMORY_BARRIER();
- }
- else
- {
- portDISABLE_INTERRUPTS();
- uxCriticalNesting++;
- }
-#else
- portDISABLE_INTERRUPTS();
- uxCriticalNesting++;
-#endif
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
- if( portIS_PRIVILEGED() == pdFALSE )
- {
- portRAISE_PRIVILEGE();
- portMEMORY_BARRIER();
-
- configASSERT( uxCriticalNesting );
- uxCriticalNesting--;
-
- if( uxCriticalNesting == 0 )
- {
- portENABLE_INTERRUPTS();
- }
- portMEMORY_BARRIER();
-
- portRESET_PRIVILEGE();
- portMEMORY_BARRIER();
- }
- else
- {
- configASSERT( uxCriticalNesting );
- uxCriticalNesting--;
-
- if( uxCriticalNesting == 0 )
- {
- portENABLE_INTERRUPTS();
- }
- }
-#else
- configASSERT( uxCriticalNesting );
- uxCriticalNesting--;
-
- if( uxCriticalNesting == 0 )
- {
- portENABLE_INTERRUPTS();
- }
-#endif
-}
-/*-----------------------------------------------------------*/
-
-void xPortPendSVHandler( void )
-{
- /* This is a naked function. */
-
- __asm volatile
- (
- " mrs r0, psp \n"
- " \n"
- " ldr r3, pxCurrentTCBConst \n"/* Get the location of the current TCB. */
- " ldr r2, [r3] \n"
- " \n"
- " mrs r1, control \n"
- " stmdb r0!, {r1, r4-r11} \n"/* Save the remaining registers. */
- " str r0, [r2] \n"/* Save the new top of stack into the first member of the TCB. */
- " \n"
- " stmdb sp!, {r3, r14} \n"
- " mov r0, %0 \n"
- " msr basepri, r0 \n"
- " dsb \n"
- " isb \n"
- " bl vTaskSwitchContext \n"
- " mov r0, #0 \n"
- " msr basepri, r0 \n"
- " ldmia sp!, {r3, r14} \n"
- " \n"/* Restore the context. */
- " ldr r1, [r3] \n"
- " ldr r0, [r1] \n"/* The first item in the TCB is the task top of stack. */
- " add r1, r1, #4 \n"/* Move onto the second item in the TCB... */
- " \n"
- " dmb \n"/* Complete outstanding transfers before disabling MPU. */
- " ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */
- " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */
- " bic r3, #1 \n"/* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
- " str r3, [r2] \n"/* Disable MPU. */
- " \n"
- " ldr r2, =0xe000ed9c \n"/* Region Base Address register. */
- " ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers. */
- " stmia r2!, {r4-r11} \n"/* Write 4 sets of MPU registers. */
- " \n"
- " ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */
- " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */
- " orr r3, #1 \n"/* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
- " str r3, [r2] \n"/* Enable MPU. */
- " dsb \n"/* Force memory writes before continuing. */
- " \n"
- " ldmia r0!, {r3, r4-r11} \n"/* Pop the registers that are not automatically saved on exception entry. */
- " msr control, r3 \n"
- " \n"
- " msr psp, r0 \n"
- " bx r14 \n"
- " \n"
- " .ltorg \n"/* Assemble current literal pool to avoid offset-out-of-bound errors with lto. */
- " .align 4 \n"
- "pxCurrentTCBConst: .word pxCurrentTCB \n"
- ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
- );
-}
-/*-----------------------------------------------------------*/
-
-void xPortSysTickHandler( void )
-{
- uint32_t ulDummy;
-
- ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
- {
- /* Increment the RTOS tick. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- /* Pend a context switch. */
- portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
- }
- }
- portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the systick timer to generate the tick interrupts at the required
- * frequency.
- */
-__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
-{
- /* Stop and clear the SysTick. */
- portNVIC_SYSTICK_CTRL_REG = 0UL;
- portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
- /* Configure SysTick to interrupt at the requested rate. */
- portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE );
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupMPU( void )
-{
- extern uint32_t __privileged_functions_start__[];
- extern uint32_t __privileged_functions_end__[];
- extern uint32_t __FLASH_segment_start__[];
- extern uint32_t __FLASH_segment_end__[];
- extern uint32_t __privileged_data_start__[];
- extern uint32_t __privileged_data_end__[];
-
- /* Check the expected MPU is present. */
- if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
- {
- /* First setup the unprivileged flash for unprivileged read only access. */
- portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
- ( portMPU_REGION_VALID ) |
- ( portUNPRIVILEGED_FLASH_REGION );
-
- portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) |
- ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
- ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
- ( portMPU_REGION_ENABLE );
-
- /* Setup the privileged flash for privileged only access. This is where
- * the kernel code is * placed. */
- portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_functions_start__ ) | /* Base address. */
- ( portMPU_REGION_VALID ) |
- ( portPRIVILEGED_FLASH_REGION );
-
- portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |
- ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
- ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __privileged_functions_start__ ) ) |
- ( portMPU_REGION_ENABLE );
-
- /* Setup the privileged data RAM region. This is where the kernel data
- * is placed. */
- portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
- ( portMPU_REGION_VALID ) |
- ( portPRIVILEGED_RAM_REGION );
-
- portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
- ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
- ( portMPU_REGION_EXECUTE_NEVER ) |
- prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
- ( portMPU_REGION_ENABLE );
-
- /* By default allow everything to access the general peripherals. The
- * system peripherals and registers are protected. */
- portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) |
- ( portMPU_REGION_VALID ) |
- ( portGENERAL_PERIPHERALS_REGION );
-
- portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |
- ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |
- ( portMPU_REGION_ENABLE );
-
- /* Enable the memory fault exception. */
- portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;
-
- /* Enable the MPU with the background region configured. */
- portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
- }
-}
-/*-----------------------------------------------------------*/
-
-static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
-{
- uint32_t ulRegionSize, ulReturnValue = 4;
-
- /* 32 is the smallest region size, 31 is the largest valid value for
- * ulReturnValue. */
- for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )
- {
- if( ulActualSizeInBytes <= ulRegionSize )
- {
- break;
- }
- else
- {
- ulReturnValue++;
- }
- }
-
- /* Shift the code by one before returning so it can be written directly
- * into the the correct bit position of the attribute register. */
- return( ulReturnValue << 1UL );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
-{
- __asm volatile
- (
- " mrs r0, control \n"/* r0 = CONTROL. */
- " tst r0, #1 \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
- " ite ne \n"
- " movne r0, #0 \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
- " moveq r0, #1 \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
- " bx lr \n"/* Return. */
- " \n"
- " .align 4 \n"
- ::: "r0", "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-void vResetPrivilege( void ) /* __attribute__ (( naked )) */
-{
- __asm volatile
- (
- " mrs r0, control \n"/* r0 = CONTROL. */
- " orr r0, #1 \n"/* r0 = r0 | 1. */
- " msr control, r0 \n"/* CONTROL = r0. */
- " bx lr \n"/* Return to the caller. */
- ::: "r0", "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
- const struct xMEMORY_REGION * const xRegions,
- StackType_t * pxBottomOfStack,
- uint32_t ulStackDepth )
-{
- extern uint32_t __SRAM_segment_start__[];
- extern uint32_t __SRAM_segment_end__[];
- extern uint32_t __privileged_data_start__[];
- extern uint32_t __privileged_data_end__[];
- int32_t lIndex;
- uint32_t ul;
-
- if( xRegions == NULL )
- {
- /* No MPU regions are specified so allow access to all RAM. */
- xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
- ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
- ( portMPU_REGION_VALID ) |
- ( portSTACK_REGION ); /* Region number. */
-
- xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
- ( portMPU_REGION_READ_WRITE ) |
- ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
- ( portMPU_REGION_EXECUTE_NEVER ) |
- ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
- ( portMPU_REGION_ENABLE );
-
- /* Invalidate user configurable regions. */
- for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
- {
- xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );
- xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
- }
- }
- else
- {
- /* This function is called automatically when the task is created - in
- * which case the stack region parameters will be valid. At all other
- * times the stack parameters will not be valid and it is assumed that the
- * stack region has already been configured. */
- if( ulStackDepth > 0 )
- {
- /* Define the region that allows access to the stack. */
- xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
- ( ( uint32_t ) pxBottomOfStack ) |
- ( portMPU_REGION_VALID ) |
- ( portSTACK_REGION ); /* Region number. */
-
- xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
- ( portMPU_REGION_READ_WRITE ) |
- ( portMPU_REGION_EXECUTE_NEVER ) |
- ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
- ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
- ( portMPU_REGION_ENABLE );
- }
-
- lIndex = 0;
-
- for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
- {
- if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
- {
- /* Translate the generic region definition contained in
- * xRegions into the CM3 specific MPU settings that are then
- * stored in xMPUSettings. */
- xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
- ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
- ( portMPU_REGION_VALID ) |
- ( ul - 1UL ); /* Region number. */
-
- xMPUSettings->xRegion[ ul ].ulRegionAttribute =
- ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
- ( xRegions[ lIndex ].ulParameters ) |
- ( portMPU_REGION_ENABLE );
- }
- else
- {
- /* Invalidate the region. */
- xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );
- xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
- }
-
- lIndex++;
- }
- }
-}
-/*-----------------------------------------------------------*/
-
-#if ( configASSERT_DEFINED == 1 )
-
- void vPortValidateInterruptPriority( void )
- {
- uint32_t ulCurrentInterrupt;
- uint8_t ucCurrentPriority;
-
- /* Obtain the number of the currently executing interrupt. */
- __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
-
- /* Is the interrupt number a user defined interrupt? */
- if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
- {
- /* Look up the interrupt's priority. */
- ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
-
- /* The following assertion will fail if a service routine (ISR) for
- * an interrupt that has been assigned a priority above
- * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
- * function. ISR safe FreeRTOS API functions must *only* be called
- * from interrupts that have been assigned a priority at or below
- * configMAX_SYSCALL_INTERRUPT_PRIORITY.
- *
- * Numerically low interrupt priority numbers represent logically high
- * interrupt priorities, therefore the priority of the interrupt must
- * be set to a value equal to or numerically *higher* than
- * configMAX_SYSCALL_INTERRUPT_PRIORITY.
- *
- * Interrupts that use the FreeRTOS API must not be left at their
- * default priority of zero as that is the highest possible priority,
- * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
- * and therefore also guaranteed to be invalid.
- *
- * FreeRTOS maintains separate thread and ISR API functions to ensure
- * interrupt entry is as fast and simple as possible.
- *
- * The following links provide detailed information:
- * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
- * https://www.FreeRTOS.org/FAQHelp.html */
- configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
- }
-
- /* Priority grouping: The interrupt controller (NVIC) allows the bits
- * that define each interrupt's priority to be split between bits that
- * define the interrupt's pre-emption priority bits and bits that define
- * the interrupt's sub-priority. For simplicity all bits must be defined
- * to be pre-emption priority bits. The following assertion will fail if
- * this is not the case (if some bits represent a sub-priority).
- *
- * If the application only uses CMSIS libraries for interrupt
- * configuration then the correct setting can be achieved on all Cortex-M
- * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
- * scheduler. Note however that some vendor specific peripheral libraries
- * assume a non-zero priority group setting, in which cases using a value
- * of zero will result in unpredicable behaviour. */
- configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
- }
-
-#endif /* configASSERT_DEFINED */
-/*-----------------------------------------------------------*/
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*-----------------------------------------------------------
+* Implementation of functions defined in portable.h for the ARM CM3 MPU port.
+*----------------------------------------------------------*/
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#ifndef configSYSTICK_CLOCK_HZ
+ #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
+ /* Ensure the SysTick is clocked at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK ( 1UL << 2UL )
+#else
+
+/* The way the SysTick is clocked is not modified in case it is not the same
+ * as the core. */
+ #define portNVIC_SYSTICK_CLK ( 0 )
+#endif
+
+#ifndef configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS
+ #warning "configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS is not defined. We recommend defining it to 0 in FreeRTOSConfig.h for better security."
+ #define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS 1
+#endif
+
+/* Constants required to access and manipulate the NVIC. */
+#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
+#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) )
+#define portNVIC_SYS_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
+#define portNVIC_MEM_FAULT_ENABLE ( 1UL << 16UL )
+
+/* Constants required to access and manipulate the MPU. */
+#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_REGION_BASE_ADDRESS_REG ( *( ( volatile uint32_t * ) 0xe000ed9C ) )
+#define portMPU_REGION_ATTRIBUTE_REG ( *( ( volatile uint32_t * ) 0xe000edA0 ) )
+#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */
+#define portMPU_ENABLE ( 0x01UL )
+#define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL )
+#define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL )
+#define portMPU_REGION_VALID ( 0x10UL )
+#define portMPU_REGION_ENABLE ( 0x01UL )
+#define portPERIPHERALS_START_ADDRESS 0x40000000UL
+#define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL
+
+/* Constants required to access and manipulate the SysTick. */
+#define portNVIC_SYSTICK_INT ( 0x00000002UL )
+#define portNVIC_SYSTICK_ENABLE ( 0x00000001UL )
+#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+#define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR ( 0x01000000 )
+#define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 )
+#define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
+#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT ( 8UL )
+
+/* Offsets in the stack to the parameters when inside the SVC handler. */
+#define portOFFSET_TO_PC ( 6 )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+ * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
+/*-----------------------------------------------------------*/
+
+/*
+ * Configure a number of standard MPU regions that are used by all tasks.
+ */
+static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Return the smallest MPU region size that a given number of bytes will fit
+ * into. The region size is returned as the value that should be programmed
+ * into the region attribute register for that region.
+ */
+static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
+
+/*
+ * Setup the timer to generate the tick interrupts. The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Standard FreeRTOS exception handlers.
+ */
+void xPortPendSVHandler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+void xPortSysTickHandler( void ) __attribute__( ( optimize( "3" ) ) ) PRIVILEGED_FUNCTION;
+void vPortSVCHandler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/*
+ * Starts the scheduler by restoring the context of the first task to run.
+ */
+static void prvRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/*
+ * C portion of the SVC handler. The SVC handler is split between an asm entry
+ * and a C wrapper for simplicity of coding and maintenance.
+ */
+static void prvSVCHandler( uint32_t * pulRegisters ) __attribute__( ( noinline ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Enter critical section.
+ */
+#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
+ void vPortEnterCritical( void ) FREERTOS_SYSTEM_CALL;
+#else
+ void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * @brief Exit from critical section.
+ */
+#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
+ void vPortExitCritical( void ) FREERTOS_SYSTEM_CALL;
+#else
+ void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
+#endif
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+ * variable. Note this is not saved as part of the task context as context
+ * switches can only occur when uxCriticalNesting is zero. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( configASSERT_DEFINED == 1 )
+ static uint8_t ucMaxSysCallPriority = 0;
+ static uint32_t ulMaxPRIGROUPValue = 0;
+ static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+ TaskFunction_t pxCode,
+ void * pvParameters,
+ BaseType_t xRunPrivileged )
+{
+ /* Simulate the stack frame as it would be created by a context switch
+ * interrupt. */
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
+ pxTopOfStack--;
+ *pxTopOfStack = 0; /* LR */
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+ if( xRunPrivileged == pdTRUE )
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;
+ }
+ else
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;
+ }
+
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler( void )
+{
+ /* Assumes psp was in use. */
+ __asm volatile
+ (
+ #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */
+ " tst lr, #4 \n"
+ " ite eq \n"
+ " mrseq r0, msp \n"
+ " mrsne r0, psp \n"
+ #else
+ " mrs r0, psp \n"
+ #endif
+ " b %0 \n"
+ ::"i" ( prvSVCHandler ) : "r0", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+static void prvSVCHandler( uint32_t * pulParam )
+{
+ uint8_t ucSVCNumber;
+ uint32_t ulPC;
+
+ #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
+ #if defined( __ARMCC_VERSION )
+
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __syscalls_flash_start__;
+ extern uint32_t * __syscalls_flash_end__;
+ #else
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __syscalls_flash_start__[];
+ extern uint32_t __syscalls_flash_end__[];
+ #endif /* #if defined( __ARMCC_VERSION ) */
+ #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
+
+ /* The stack contains: r0, r1, r2, r3, r12, LR, PC and xPSR. The first
+ * argument (r0) is pulParam[ 0 ]. */
+ ulPC = pulParam[ portOFFSET_TO_PC ];
+ ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
+
+ switch( ucSVCNumber )
+ {
+ case portSVC_START_SCHEDULER:
+ portNVIC_SHPR2_REG |= portNVIC_SVC_PRI;
+ prvRestoreContextOfFirstTask();
+ break;
+
+ case portSVC_YIELD:
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+
+ /* Barriers are normally not required
+ * but do ensure the code is completely
+ * within the specified behaviour for the
+ * architecture. */
+ __asm volatile ( "dsb" ::: "memory" );
+ __asm volatile ( "isb" );
+
+ break;
+
+
+ #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
+ case portSVC_RAISE_PRIVILEGE: /* Only raise the privilege, if the
+ * svc was raised from any of the
+ * system calls. */
+
+ if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+ ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+ {
+ __asm volatile
+ (
+ " mrs r1, control \n"/* Obtain current control value. */
+ " bic r1, #1 \n"/* Set privilege bit. */
+ " msr control, r1 \n"/* Write back new control value. */
+ ::: "r1", "memory"
+ );
+ }
+
+ break;
+ #else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
+ case portSVC_RAISE_PRIVILEGE:
+ __asm volatile
+ (
+ " mrs r1, control \n"/* Obtain current control value. */
+ " bic r1, #1 \n"/* Set privilege bit. */
+ " msr control, r1 \n"/* Write back new control value. */
+ ::: "r1", "memory"
+ );
+ break;
+ #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
+
+ default: /* Unknown SVC call. */
+ break;
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void prvRestoreContextOfFirstTask( void )
+{
+ __asm volatile
+ (
+ " ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */
+ " ldr r0, [r0] \n"
+ " ldr r0, [r0] \n"
+ " msr msp, r0 \n"/* Set the msp back to the start of the stack. */
+ " ldr r3, pxCurrentTCBConst2 \n"/* Restore the context. */
+ " ldr r1, [r3] \n"
+ " ldr r0, [r1] \n"/* The first item in the TCB is the task top of stack. */
+ " add r1, r1, #4 \n"/* Move onto the second item in the TCB... */
+ " \n"
+ " dmb \n"/* Complete outstanding transfers before disabling MPU. */
+ " ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */
+ " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */
+ " bic r3, #1 \n"/* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
+ " str r3, [r2] \n"/* Disable MPU. */
+ " \n"
+ " ldr r2, =0xe000ed9c \n"/* Region Base Address register. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers. */
+ " stmia r2!, {r4-r11} \n"/* Write 4 sets of MPU registers. */
+ " \n"
+ " ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */
+ " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */
+ " orr r3, #1 \n"/* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
+ " str r3, [r2] \n"/* Enable MPU. */
+ " dsb \n"/* Force memory writes before continuing. */
+ " \n"
+ " ldmia r0!, {r3, r4-r11} \n"/* Pop the registers that are not automatically saved on exception entry. */
+ " msr control, r3 \n"
+ " msr psp, r0 \n"/* Restore the task stack pointer. */
+ " mov r0, #0 \n"
+ " msr basepri, r0 \n"
+ " ldr r14, =0xfffffffd \n"/* Load exec return code. */
+ " bx r14 \n"
+ " \n"
+ " .ltorg \n"/* Assemble current literal pool to avoid offset-out-of-bound errors with lto. */
+ " .align 4 \n"
+ "pxCurrentTCBConst2: .word pxCurrentTCB \n"
+ );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+ /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See
+ * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
+
+ #if ( configASSERT_DEFINED == 1 )
+ {
+ volatile uint32_t ulOriginalPriority;
+ volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine the maximum priority from which ISR safe FreeRTOS API
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions
+ * to ensure interrupt entry is as fast and simple as possible.
+ *
+ * Save the interrupt priority value that is about to be clobbered. */
+ ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+ /* Determine the number of priority bits available. First write to all
+ * possible bits. */
+ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+ /* Use the same mask on the maximum system call priority. */
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+ /* Calculate the maximum acceptable priority group value for the number
+ * of bits read back. */
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+ {
+ ulMaxPRIGROUPValue--;
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+ }
+
+ #ifdef __NVIC_PRIO_BITS
+ {
+ /* Check the CMSIS configuration that defines the number of
+ * priority bits matches the number of priority bits actually queried
+ * from the hardware. */
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+ }
+ #endif
+
+ #ifdef configPRIO_BITS
+ {
+ /* Check the FreeRTOS configuration that defines the number of
+ * priority bits matches the number of priority bits actually queried
+ * from the hardware. */
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+ }
+ #endif
+
+ /* Shift the priority group value back to its position within the AIRCR
+ * register. */
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+ /* Restore the clobbered interrupt priority register to its original
+ * value. */
+ *pucFirstUserPriorityRegister = ulOriginalPriority;
+ }
+ #endif /* configASSERT_DEFINED */
+
+ /* Make PendSV and SysTick the same priority as the kernel, and the SVC
+ * handler higher priority so it can be used to exit a critical section (where
+ * lower priorities are masked). */
+ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
+ portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+
+ /* Configure the regions in the MPU that are common to all tasks. */
+ prvSetupMPU();
+
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ * here already. */
+ vPortSetupTimerInterrupt();
+
+ /* Initialise the critical nesting count ready for the first task. */
+ uxCriticalNesting = 0;
+
+ /* Start the first task. */
+ __asm volatile (
+ " ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */
+ " ldr r0, [r0] \n"
+ " ldr r0, [r0] \n"
+ " msr msp, r0 \n"/* Set the msp back to the start of the stack. */
+ " cpsie i \n"/* Globally enable interrupts. */
+ " cpsie f \n"
+ " dsb \n"
+ " isb \n"
+ " svc %0 \n"/* System call to start first task. */
+ " nop \n"
+ " .ltorg \n"
+ ::"i" ( portSVC_START_SCHEDULER ) : "memory" );
+
+ /* Should not get here! */
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+ /* Not implemented in ports where there is nothing to return to.
+ * Artificially force an assert. */
+ configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ portDISABLE_INTERRUPTS();
+ uxCriticalNesting++;
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ portDISABLE_INTERRUPTS();
+ uxCriticalNesting++;
+ }
+#else
+ portDISABLE_INTERRUPTS();
+ uxCriticalNesting++;
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ configASSERT( uxCriticalNesting );
+ uxCriticalNesting--;
+
+ if( uxCriticalNesting == 0 )
+ {
+ portENABLE_INTERRUPTS();
+ }
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ configASSERT( uxCriticalNesting );
+ uxCriticalNesting--;
+
+ if( uxCriticalNesting == 0 )
+ {
+ portENABLE_INTERRUPTS();
+ }
+ }
+#else
+ configASSERT( uxCriticalNesting );
+ uxCriticalNesting--;
+
+ if( uxCriticalNesting == 0 )
+ {
+ portENABLE_INTERRUPTS();
+ }
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void xPortPendSVHandler( void )
+{
+ /* This is a naked function. */
+
+ __asm volatile
+ (
+ " mrs r0, psp \n"
+ " \n"
+ " ldr r3, pxCurrentTCBConst \n"/* Get the location of the current TCB. */
+ " ldr r2, [r3] \n"
+ " \n"
+ " mrs r1, control \n"
+ " stmdb r0!, {r1, r4-r11} \n"/* Save the remaining registers. */
+ " str r0, [r2] \n"/* Save the new top of stack into the first member of the TCB. */
+ " \n"
+ " stmdb sp!, {r3, r14} \n"
+ " mov r0, %0 \n"
+ " msr basepri, r0 \n"
+ " dsb \n"
+ " isb \n"
+ " bl vTaskSwitchContext \n"
+ " mov r0, #0 \n"
+ " msr basepri, r0 \n"
+ " ldmia sp!, {r3, r14} \n"
+ " \n"/* Restore the context. */
+ " ldr r1, [r3] \n"
+ " ldr r0, [r1] \n"/* The first item in the TCB is the task top of stack. */
+ " add r1, r1, #4 \n"/* Move onto the second item in the TCB... */
+ " \n"
+ " dmb \n"/* Complete outstanding transfers before disabling MPU. */
+ " ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */
+ " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */
+ " bic r3, #1 \n"/* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
+ " str r3, [r2] \n"/* Disable MPU. */
+ " \n"
+ " ldr r2, =0xe000ed9c \n"/* Region Base Address register. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers. */
+ " stmia r2!, {r4-r11} \n"/* Write 4 sets of MPU registers. */
+ " \n"
+ " ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */
+ " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */
+ " orr r3, #1 \n"/* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
+ " str r3, [r2] \n"/* Enable MPU. */
+ " dsb \n"/* Force memory writes before continuing. */
+ " \n"
+ " ldmia r0!, {r3, r4-r11} \n"/* Pop the registers that are not automatically saved on exception entry. */
+ " msr control, r3 \n"
+ " \n"
+ " msr psp, r0 \n"
+ " bx r14 \n"
+ " \n"
+ " .ltorg \n"/* Assemble current literal pool to avoid offset-out-of-bound errors with lto. */
+ " .align 4 \n"
+ "pxCurrentTCBConst: .word pxCurrentTCB \n"
+ ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+ );
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+ uint32_t ulDummy;
+
+ ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
+ {
+ /* Increment the RTOS tick. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ /* Pend a context switch. */
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+ }
+ }
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
+{
+ /* Stop and clear the SysTick. */
+ portNVIC_SYSTICK_CTRL_REG = 0UL;
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+ /* Configure SysTick to interrupt at the requested rate. */
+ portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE );
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupMPU( void )
+{
+ extern uint32_t __privileged_functions_start__[];
+ extern uint32_t __privileged_functions_end__[];
+ extern uint32_t __FLASH_segment_start__[];
+ extern uint32_t __FLASH_segment_end__[];
+ extern uint32_t __privileged_data_start__[];
+ extern uint32_t __privileged_data_end__[];
+
+ /* Check the expected MPU is present. */
+ if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+ {
+ /* First setup the unprivileged flash for unprivileged read only access. */
+ portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
+ ( portMPU_REGION_VALID ) |
+ ( portUNPRIVILEGED_FLASH_REGION );
+
+ portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) |
+ ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
+ ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
+ ( portMPU_REGION_ENABLE );
+
+ /* Setup the privileged flash for privileged only access. This is where
+ * the kernel code is * placed. */
+ portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_functions_start__ ) | /* Base address. */
+ ( portMPU_REGION_VALID ) |
+ ( portPRIVILEGED_FLASH_REGION );
+
+ portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |
+ ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
+ ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __privileged_functions_start__ ) ) |
+ ( portMPU_REGION_ENABLE );
+
+ /* Setup the privileged data RAM region. This is where the kernel data
+ * is placed. */
+ portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
+ ( portMPU_REGION_VALID ) |
+ ( portPRIVILEGED_RAM_REGION );
+
+ portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+ ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
+ ( portMPU_REGION_EXECUTE_NEVER ) |
+ prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
+ ( portMPU_REGION_ENABLE );
+
+ /* By default allow everything to access the general peripherals. The
+ * system peripherals and registers are protected. */
+ portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) |
+ ( portMPU_REGION_VALID ) |
+ ( portGENERAL_PERIPHERALS_REGION );
+
+ portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |
+ ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |
+ ( portMPU_REGION_ENABLE );
+
+ /* Enable the memory fault exception. */
+ portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;
+
+ /* Enable the MPU with the background region configured. */
+ portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
+ }
+}
+/*-----------------------------------------------------------*/
+
+static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
+{
+ uint32_t ulRegionSize, ulReturnValue = 4;
+
+ /* 32 is the smallest region size, 31 is the largest valid value for
+ * ulReturnValue. */
+ for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )
+ {
+ if( ulActualSizeInBytes <= ulRegionSize )
+ {
+ break;
+ }
+ else
+ {
+ ulReturnValue++;
+ }
+ }
+
+ /* Shift the code by one before returning so it can be written directly
+ * into the the correct bit position of the attribute register. */
+ return( ulReturnValue << 1UL );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+ __asm volatile
+ (
+ " mrs r0, control \n"/* r0 = CONTROL. */
+ " tst r0, #1 \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+ " ite ne \n"
+ " movne r0, #0 \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+ " moveq r0, #1 \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+ " bx lr \n"/* Return. */
+ " \n"
+ " .align 4 \n"
+ ::: "r0", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+ __asm volatile
+ (
+ " mrs r0, control \n"/* r0 = CONTROL. */
+ " orr r0, #1 \n"/* r0 = r0 | 1. */
+ " msr control, r0 \n"/* CONTROL = r0. */
+ " bx lr \n"/* Return to the caller. */
+ ::: "r0", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
+ const struct xMEMORY_REGION * const xRegions,
+ StackType_t * pxBottomOfStack,
+ uint32_t ulStackDepth )
+{
+ extern uint32_t __SRAM_segment_start__[];
+ extern uint32_t __SRAM_segment_end__[];
+ extern uint32_t __privileged_data_start__[];
+ extern uint32_t __privileged_data_end__[];
+ int32_t lIndex;
+ uint32_t ul;
+
+ if( xRegions == NULL )
+ {
+ /* No MPU regions are specified so allow access to all RAM. */
+ xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
+ ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
+ ( portMPU_REGION_VALID ) |
+ ( portSTACK_REGION ); /* Region number. */
+
+ xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
+ ( portMPU_REGION_READ_WRITE ) |
+ ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
+ ( portMPU_REGION_EXECUTE_NEVER ) |
+ ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
+ ( portMPU_REGION_ENABLE );
+
+ /* Invalidate user configurable regions. */
+ for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
+ {
+ xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );
+ xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
+ }
+ }
+ else
+ {
+ /* This function is called automatically when the task is created - in
+ * which case the stack region parameters will be valid. At all other
+ * times the stack parameters will not be valid and it is assumed that the
+ * stack region has already been configured. */
+ if( ulStackDepth > 0 )
+ {
+ /* Define the region that allows access to the stack. */
+ xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
+ ( ( uint32_t ) pxBottomOfStack ) |
+ ( portMPU_REGION_VALID ) |
+ ( portSTACK_REGION ); /* Region number. */
+
+ xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
+ ( portMPU_REGION_READ_WRITE ) |
+ ( portMPU_REGION_EXECUTE_NEVER ) |
+ ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
+ ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
+ ( portMPU_REGION_ENABLE );
+ }
+
+ lIndex = 0;
+
+ for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
+ {
+ if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
+ {
+ /* Translate the generic region definition contained in
+ * xRegions into the CM3 specific MPU settings that are then
+ * stored in xMPUSettings. */
+ xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
+ ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
+ ( portMPU_REGION_VALID ) |
+ ( ul - 1UL ); /* Region number. */
+
+ xMPUSettings->xRegion[ ul ].ulRegionAttribute =
+ ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
+ ( xRegions[ lIndex ].ulParameters ) |
+ ( portMPU_REGION_ENABLE );
+ }
+ else
+ {
+ /* Invalidate the region. */
+ xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );
+ xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
+ }
+
+ lIndex++;
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+#if ( configASSERT_DEFINED == 1 )
+
+ void vPortValidateInterruptPriority( void )
+ {
+ uint32_t ulCurrentInterrupt;
+ uint8_t ucCurrentPriority;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ /* Is the interrupt number a user defined interrupt? */
+ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+ {
+ /* Look up the interrupt's priority. */
+ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+ /* The following assertion will fail if a service routine (ISR) for
+ * an interrupt that has been assigned a priority above
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+ * function. ISR safe FreeRTOS API functions must *only* be called
+ * from interrupts that have been assigned a priority at or below
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Numerically low interrupt priority numbers represent logically high
+ * interrupt priorities, therefore the priority of the interrupt must
+ * be set to a value equal to or numerically *higher* than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Interrupts that use the FreeRTOS API must not be left at their
+ * default priority of zero as that is the highest possible priority,
+ * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+ * and therefore also guaranteed to be invalid.
+ *
+ * FreeRTOS maintains separate thread and ISR API functions to ensure
+ * interrupt entry is as fast and simple as possible.
+ *
+ * The following links provide detailed information:
+ * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+ * https://www.FreeRTOS.org/FAQHelp.html */
+ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+ }
+
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits
+ * that define each interrupt's priority to be split between bits that
+ * define the interrupt's pre-emption priority bits and bits that define
+ * the interrupt's sub-priority. For simplicity all bits must be defined
+ * to be pre-emption priority bits. The following assertion will fail if
+ * this is not the case (if some bits represent a sub-priority).
+ *
+ * If the application only uses CMSIS libraries for interrupt
+ * configuration then the correct setting can be achieved on all Cortex-M
+ * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+ * scheduler. Note however that some vendor specific peripheral libraries
+ * assume a non-zero priority group setting, in which cases using a value
+ * of zero will result in unpredicable behaviour. */
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+ }
+
+#endif /* configASSERT_DEFINED */
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM3_MPU/portmacro.h b/portable/GCC/ARM_CM3_MPU/portmacro.h
index c2a3549..693fc7b 100644
--- a/portable/GCC/ARM_CM3_MPU/portmacro.h
+++ b/portable/GCC/ARM_CM3_MPU/portmacro.h
@@ -1,309 +1,309 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-
-#ifndef PORTMACRO_H
- #define PORTMACRO_H
-
- #ifdef __cplusplus
- extern "C" {
- #endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
-
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
-
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #endif
-/*-----------------------------------------------------------*/
-
-/* MPU specific constants. */
- #define portUSING_MPU_WRAPPERS 1
- #define portPRIVILEGE_BIT ( 0x80000000UL )
-
- #define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL )
- #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL )
- #define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL )
- #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL )
- #define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ( 0x02UL << 24UL )
- #define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL )
- #define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL )
-
- #define portGENERAL_PERIPHERALS_REGION ( 3UL )
- #define portSTACK_REGION ( 4UL )
- #define portUNPRIVILEGED_FLASH_REGION ( 5UL )
- #define portPRIVILEGED_FLASH_REGION ( 6UL )
- #define portPRIVILEGED_RAM_REGION ( 7UL )
- #define portFIRST_CONFIGURABLE_REGION ( 0UL )
- #define portLAST_CONFIGURABLE_REGION ( 2UL )
- #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
- #define portTOTAL_NUM_REGIONS_IN_TCB ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
- #define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" )
-
- typedef struct MPU_REGION_REGISTERS
- {
- uint32_t ulRegionBaseAddress;
- uint32_t ulRegionAttribute;
- } xMPU_REGION_REGISTERS;
-
-/* Plus 1 to create space for the stack region. */
- typedef struct MPU_SETTINGS
- {
- xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS_IN_TCB ];
- } xMPU_SETTINGS;
-
-/* Architecture specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portDONT_DISCARD __attribute__( ( used ) )
-/*-----------------------------------------------------------*/
-
-/* SVC numbers for various services. */
- #define portSVC_START_SCHEDULER 0
- #define portSVC_YIELD 1
- #define portSVC_RAISE_PRIVILEGE 2
-
-/* Scheduler utilities. */
-
- #define portYIELD() __asm volatile ( " SVC %0 \n"::"i" ( portSVC_YIELD ) : "memory" )
- #define portYIELD_WITHIN_API() \
- { \
- /* Set a PendSV to request a context switch. */ \
- portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
- \
- /* Barriers are normally not required but do ensure the code is completely \
- * within the specified behaviour for the architecture. */ \
- __asm volatile ( "dsb" ::: "memory" ); \
- __asm volatile ( "isb" ); \
- }
-
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/* Critical section management. */
- extern void vPortEnterCritical( void );
- extern void vPortExitCritical( void );
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x )
- #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
- #define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. These are
- * not necessary for to use this port. They are defined so the common demo files
- * (which build with all the ports) will build. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
-/*-----------------------------------------------------------*/
-
-/* Architecture specific optimisations. */
- #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
- #endif
-
- #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
-/* Generic helper function. */
- __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
- {
- uint8_t ucReturn;
-
- __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
-
- return ucReturn;
- }
-
-/* Check the configuration. */
- #if ( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
-
-/* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-/*-----------------------------------------------------------*/
-
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
-
- #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-/*-----------------------------------------------------------*/
-
- #ifdef configASSERT
- void vPortValidateInterruptPriority( void );
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
- #endif
-
-/* portNOP() is not required by this port. */
- #define portNOP()
-
- #define portINLINE __inline
-
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
- #endif
-/*-----------------------------------------------------------*/
-
- extern BaseType_t xIsPrivileged( void );
- extern void vResetPrivilege( void );
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
- #define portIS_PRIVILEGED() xIsPrivileged()
-
-/**
- * @brief Raise an SVC request to raise privilege.
- */
- #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- */
- #define portRESET_PRIVILEGE() vResetPrivilege()
-/*-----------------------------------------------------------*/
-
- portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
- {
- uint32_t ulCurrentInterrupt;
- BaseType_t xReturn;
-
- /* Obtain the number of the currently executing interrupt. */
- __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
-
- if( ulCurrentInterrupt == 0 )
- {
- xReturn = pdFALSE;
- }
- else
- {
- xReturn = pdTRUE;
- }
-
- return xReturn;
- }
-
-/*-----------------------------------------------------------*/
-
- portFORCE_INLINE static void vPortRaiseBASEPRI( void )
- {
- uint32_t ulNewBASEPRI;
-
- __asm volatile
- (
- " mov %0, %1 \n"\
- " msr basepri, %0 \n"\
- " isb \n"\
- " dsb \n"\
- : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
- );
- }
-
-/*-----------------------------------------------------------*/
-
- portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
- {
- uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
-
- __asm volatile
- (
- " mrs %0, basepri \n"\
- " mov %1, %2 \n"\
- " msr basepri, %1 \n"\
- " isb \n"\
- " dsb \n"\
- : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
- );
-
- /* This return will not be reached but is necessary to prevent compiler
- * warnings. */
- return ulOriginalBASEPRI;
- }
-/*-----------------------------------------------------------*/
-
- portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
- {
- __asm volatile
- (
- " msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory"
- );
- }
-/*-----------------------------------------------------------*/
-
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
-
- #ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY
- #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html"
- #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0
- #endif
-/*-----------------------------------------------------------*/
- #ifdef __cplusplus
- }
- #endif
-
-#endif /* PORTMACRO_H */
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+#ifndef PORTMACRO_H
+ #define PORTMACRO_H
+
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+ #define portCHAR char
+ #define portFLOAT float
+ #define portDOUBLE double
+ #define portLONG long
+ #define portSHORT short
+ #define portSTACK_TYPE uint32_t
+ #define portBASE_TYPE long
+
+ typedef portSTACK_TYPE StackType_t;
+ typedef long BaseType_t;
+ typedef unsigned long UBaseType_t;
+
+ #if ( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+ #else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+ #endif
+/*-----------------------------------------------------------*/
+
+/* MPU specific constants. */
+ #define portUSING_MPU_WRAPPERS 1
+ #define portPRIVILEGE_BIT ( 0x80000000UL )
+
+ #define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL )
+ #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL )
+ #define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL )
+ #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL )
+ #define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ( 0x02UL << 24UL )
+ #define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL )
+ #define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL )
+
+ #define portGENERAL_PERIPHERALS_REGION ( 3UL )
+ #define portSTACK_REGION ( 4UL )
+ #define portUNPRIVILEGED_FLASH_REGION ( 5UL )
+ #define portPRIVILEGED_FLASH_REGION ( 6UL )
+ #define portPRIVILEGED_RAM_REGION ( 7UL )
+ #define portFIRST_CONFIGURABLE_REGION ( 0UL )
+ #define portLAST_CONFIGURABLE_REGION ( 2UL )
+ #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+ #define portTOTAL_NUM_REGIONS_IN_TCB ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+ #define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" )
+
+ typedef struct MPU_REGION_REGISTERS
+ {
+ uint32_t ulRegionBaseAddress;
+ uint32_t ulRegionAttribute;
+ } xMPU_REGION_REGISTERS;
+
+/* Plus 1 to create space for the stack region. */
+ typedef struct MPU_SETTINGS
+ {
+ xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS_IN_TCB ];
+ } xMPU_SETTINGS;
+
+/* Architecture specifics. */
+ #define portSTACK_GROWTH ( -1 )
+ #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+ #define portBYTE_ALIGNMENT 8
+ #define portDONT_DISCARD __attribute__( ( used ) )
+/*-----------------------------------------------------------*/
+
+/* SVC numbers for various services. */
+ #define portSVC_START_SCHEDULER 0
+ #define portSVC_YIELD 1
+ #define portSVC_RAISE_PRIVILEGE 2
+
+/* Scheduler utilities. */
+
+ #define portYIELD() __asm volatile ( " SVC %0 \n"::"i" ( portSVC_YIELD ) : "memory" )
+ #define portYIELD_WITHIN_API() \
+ { \
+ /* Set a PendSV to request a context switch. */ \
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+ \
+ /* Barriers are normally not required but do ensure the code is completely \
+ * within the specified behaviour for the architecture. */ \
+ __asm volatile ( "dsb" ::: "memory" ); \
+ __asm volatile ( "isb" ); \
+ }
+
+ #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+ #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+ #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
+ #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+ extern void vPortEnterCritical( void );
+ extern void vPortExitCritical( void );
+ #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
+ #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x )
+ #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
+ #define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )
+ #define portENTER_CRITICAL() vPortEnterCritical()
+ #define portEXIT_CRITICAL() vPortExitCritical()
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. These are
+ * not necessary for to use this port. They are defined so the common demo files
+ * (which build with all the ports) will build. */
+ #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+ #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+ #endif
+
+ #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+/* Generic helper function. */
+ __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+ {
+ uint8_t ucReturn;
+
+ __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
+
+ return ucReturn;
+ }
+
+/* Check the configuration. */
+ #if ( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
+
+/* Store/clear the ready priorities in a bit map. */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/*-----------------------------------------------------------*/
+
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+ #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+ #ifdef configASSERT
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+ #endif
+
+/* portNOP() is not required by this port. */
+ #define portNOP()
+
+ #define portINLINE __inline
+
+ #ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+ #endif
+/*-----------------------------------------------------------*/
+
+ extern BaseType_t xIsPrivileged( void );
+ extern void vResetPrivilege( void );
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+ #define portIS_PRIVILEGED() xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+ */
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+ #define portRESET_PRIVILEGE() vResetPrivilege()
+/*-----------------------------------------------------------*/
+
+ portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+ {
+ uint32_t ulCurrentInterrupt;
+ BaseType_t xReturn;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ if( ulCurrentInterrupt == 0 )
+ {
+ xReturn = pdFALSE;
+ }
+ else
+ {
+ xReturn = pdTRUE;
+ }
+
+ return xReturn;
+ }
+
+/*-----------------------------------------------------------*/
+
+ portFORCE_INLINE static void vPortRaiseBASEPRI( void )
+ {
+ uint32_t ulNewBASEPRI;
+
+ __asm volatile
+ (
+ " mov %0, %1 \n"\
+ " msr basepri, %0 \n"\
+ " isb \n"\
+ " dsb \n"\
+ : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+ );
+ }
+
+/*-----------------------------------------------------------*/
+
+ portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
+ {
+ uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
+
+ __asm volatile
+ (
+ " mrs %0, basepri \n"\
+ " mov %1, %2 \n"\
+ " msr basepri, %1 \n"\
+ " isb \n"\
+ " dsb \n"\
+ : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+ );
+
+ /* This return will not be reached but is necessary to prevent compiler
+ * warnings. */
+ return ulOriginalBASEPRI;
+ }
+/*-----------------------------------------------------------*/
+
+ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
+ {
+ __asm volatile
+ (
+ " msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+
+ #ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY
+ #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html"
+ #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0
+ #endif
+/*-----------------------------------------------------------*/
+ #ifdef __cplusplus
+ }
+ #endif
+
+#endif /* PORTMACRO_H */
diff --git a/portable/GCC/ARM_CM4F/port.c b/portable/GCC/ARM_CM4F/port.c
index c62d160..b946e6e 100644
--- a/portable/GCC/ARM_CM4F/port.c
+++ b/portable/GCC/ARM_CM4F/port.c
@@ -1,839 +1,839 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the ARM CM4F port.
-*----------------------------------------------------------*/
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-#ifndef __VFP_FP__
- #error This port can only be used when the project options are configured to enable hardware floating point support.
-#endif
-
-/* Constants required to manipulate the core. Registers first... */
-#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
-#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
-#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
-#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
-/* ...then bits in the registers. */
-#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
-#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
-#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
-#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
-#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
-#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
-#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
-
-/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
- * r0p1 port. */
-#define portCPUID ( *( ( volatile uint32_t * ) 0xE000ed00 ) )
-#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )
-#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )
-
-#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
-
-/* Constants required to check the validity of an interrupt priority. */
-#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
-#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
-#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
-#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
-#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
-#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
-#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
-#define portPRIGROUP_SHIFT ( 8UL )
-
-/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
-#define portVECTACTIVE_MASK ( 0xFFUL )
-
-/* Constants required to manipulate the VFP. */
-#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
-#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
-
-/* Constants required to set up the initial stack. */
-#define portINITIAL_XPSR ( 0x01000000 )
-#define portINITIAL_EXC_RETURN ( 0xfffffffd )
-
-/* The systick is a 24-bit counter. */
-#define portMAX_24_BIT_NUMBER ( 0xffffffUL )
-
-/* For strict compliance with the Cortex-M spec the task start address should
- * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
-#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
-
-/* A fiddle factor to estimate the number of SysTick counts that would have
- * occurred while the SysTick counter is stopped during tickless idle
- * calculations. */
-#define portMISSED_COUNTS_FACTOR ( 94UL )
-
-/* Let the user override the default SysTick clock rate. If defined by the
- * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
- * configuration register. */
-#ifndef configSYSTICK_CLOCK_HZ
- #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ )
- /* Ensure the SysTick is clocked at the same frequency as the core. */
- #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT )
-#else
- /* Select the option to clock SysTick not at the same frequency as the core. */
- #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 )
-#endif
-
-/* Let the user override the pre-loading of the initial LR with the address of
- * prvTaskExitError() in case it messes up unwinding of the stack in the
- * debugger. */
-#ifdef configTASK_RETURN_ADDRESS
- #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
-#else
- #define portTASK_RETURN_ADDRESS prvTaskExitError
-#endif
-
-/*
- * Setup the timer to generate the tick interrupts. The implementation in this
- * file is weak to allow application writers to change the timer used to
- * generate the tick interrupt.
- */
-void vPortSetupTimerInterrupt( void );
-
-/*
- * Exception handlers.
- */
-void xPortPendSVHandler( void ) __attribute__( ( naked ) );
-void xPortSysTickHandler( void );
-void vPortSVCHandler( void ) __attribute__( ( naked ) );
-
-/*
- * Start first task is a separate function so it can be tested in isolation.
- */
-static void prvPortStartFirstTask( void ) __attribute__( ( naked ) );
-
-/*
- * Function to enable the VFP.
- */
-static void vPortEnableVFP( void ) __attribute__( ( naked ) );
-
-/*
- * Used to catch tasks that attempt to return from their implementing function.
- */
-static void prvTaskExitError( void );
-
-/*-----------------------------------------------------------*/
-
-/* Each task maintains its own interrupt status in the critical nesting
- * variable. */
-static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
-
-/*
- * The number of SysTick increments that make up one tick period.
- */
-#if ( configUSE_TICKLESS_IDLE == 1 )
- static uint32_t ulTimerCountsForOneTick = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * The maximum number of tick periods that can be suppressed is limited by the
- * 24 bit resolution of the SysTick timer.
- */
-#if ( configUSE_TICKLESS_IDLE == 1 )
- static uint32_t xMaximumPossibleSuppressedTicks = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * Compensate for the CPU cycles that pass while the SysTick is stopped (low
- * power functionality only.
- */
-#if ( configUSE_TICKLESS_IDLE == 1 )
- static uint32_t ulStoppedTimerCompensation = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
- * FreeRTOS API functions are not called from interrupts that have been assigned
- * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
- */
-#if ( configASSERT_DEFINED == 1 )
- static uint8_t ucMaxSysCallPriority = 0;
- static uint32_t ulMaxPRIGROUPValue = 0;
- static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
-#endif /* configASSERT_DEFINED */
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
-{
- /* Simulate the stack frame as it would be created by a context switch
- * interrupt. */
-
- /* Offset added to account for the way the MCU uses the stack on entry/exit
- * of interrupts, and to ensure alignment. */
- pxTopOfStack--;
-
- *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
- pxTopOfStack--;
- *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
-
- /* Save code space by skipping register initialisation. */
- pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
-
- /* A save method is being used that requires each task to maintain its
- * own exec return value. */
- pxTopOfStack--;
- *pxTopOfStack = portINITIAL_EXC_RETURN;
-
- pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
-
- return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
- volatile uint32_t ulDummy = 0;
-
- /* A function that implements a task must not exit or attempt to return to
- * its caller as there is nothing to return to. If a task wants to exit it
- * should instead call vTaskDelete( NULL ).
- *
- * Artificially force an assert() to be triggered if configASSERT() is
- * defined, then stop here so application writers can catch the error. */
- configASSERT( uxCriticalNesting == ~0UL );
- portDISABLE_INTERRUPTS();
-
- while( ulDummy == 0 )
- {
- /* This file calls prvTaskExitError() after the scheduler has been
- * started to remove a compiler warning about the function being defined
- * but never called. ulDummy is used purely to quieten other warnings
- * about code appearing after this function is called - making ulDummy
- * volatile makes the compiler think the function could return and
- * therefore not output an 'unreachable code' warning for code that appears
- * after it. */
- }
-}
-/*-----------------------------------------------------------*/
-
-void vPortSVCHandler( void )
-{
- __asm volatile (
- " ldr r3, pxCurrentTCBConst2 \n"/* Restore the context. */
- " ldr r1, [r3] \n"/* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
- " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. */
- " ldmia r0!, {r4-r11, r14} \n"/* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
- " msr psp, r0 \n"/* Restore the task stack pointer. */
- " isb \n"
- " mov r0, #0 \n"
- " msr basepri, r0 \n"
- " bx r14 \n"
- " \n"
- " .align 4 \n"
- "pxCurrentTCBConst2: .word pxCurrentTCB \n"
- );
-}
-/*-----------------------------------------------------------*/
-
-static void prvPortStartFirstTask( void )
-{
- /* Start the first task. This also clears the bit that indicates the FPU is
- * in use in case the FPU was used before the scheduler was started - which
- * would otherwise result in the unnecessary leaving of space in the SVC stack
- * for lazy saving of FPU registers. */
- __asm volatile (
- " ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */
- " ldr r0, [r0] \n"
- " ldr r0, [r0] \n"
- " msr msp, r0 \n"/* Set the msp back to the start of the stack. */
- " mov r0, #0 \n"/* Clear the bit that indicates the FPU is in use, see comment above. */
- " msr control, r0 \n"
- " cpsie i \n"/* Globally enable interrupts. */
- " cpsie f \n"
- " dsb \n"
- " isb \n"
- " svc 0 \n"/* System call to start first task. */
- " nop \n"
- " .ltorg \n"
- );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-BaseType_t xPortStartScheduler( void )
-{
- /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
- * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
- configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
-
- /* This port can be used on all revisions of the Cortex-M7 core other than
- * the r0p1 parts. r0p1 parts should use the port from the
- * /source/portable/GCC/ARM_CM7/r0p1 directory. */
- configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
- configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
-
- #if ( configASSERT_DEFINED == 1 )
- {
- volatile uint32_t ulOriginalPriority;
- volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
- volatile uint8_t ucMaxPriorityValue;
-
- /* Determine the maximum priority from which ISR safe FreeRTOS API
- * functions can be called. ISR safe functions are those that end in
- * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
- * ensure interrupt entry is as fast and simple as possible.
- *
- * Save the interrupt priority value that is about to be clobbered. */
- ulOriginalPriority = *pucFirstUserPriorityRegister;
-
- /* Determine the number of priority bits available. First write to all
- * possible bits. */
- *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
-
- /* Read the value back to see how many bits stuck. */
- ucMaxPriorityValue = *pucFirstUserPriorityRegister;
-
- /* Use the same mask on the maximum system call priority. */
- ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
-
- /* Calculate the maximum acceptable priority group value for the number
- * of bits read back. */
- ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
-
- while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
- {
- ulMaxPRIGROUPValue--;
- ucMaxPriorityValue <<= ( uint8_t ) 0x01;
- }
-
- #ifdef __NVIC_PRIO_BITS
- {
- /* Check the CMSIS configuration that defines the number of
- * priority bits matches the number of priority bits actually queried
- * from the hardware. */
- configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
- }
- #endif
-
- #ifdef configPRIO_BITS
- {
- /* Check the FreeRTOS configuration that defines the number of
- * priority bits matches the number of priority bits actually queried
- * from the hardware. */
- configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
- }
- #endif
-
- /* Shift the priority group value back to its position within the AIRCR
- * register. */
- ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
- ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
- /* Restore the clobbered interrupt priority register to its original
- * value. */
- *pucFirstUserPriorityRegister = ulOriginalPriority;
- }
- #endif /* configASSERT_DEFINED */
-
- /* Make PendSV and SysTick the lowest priority interrupts. */
- portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
- portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
-
- /* Start the timer that generates the tick ISR. Interrupts are disabled
- * here already. */
- vPortSetupTimerInterrupt();
-
- /* Initialise the critical nesting count ready for the first task. */
- uxCriticalNesting = 0;
-
- /* Ensure the VFP is enabled - it should be anyway. */
- vPortEnableVFP();
-
- /* Lazy save always. */
- *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
-
- /* Start the first task. */
- prvPortStartFirstTask();
-
- /* Should never get here as the tasks will now be executing! Call the task
- * exit error function to prevent compiler warnings about a static function
- * not being called in the case that the application writer overrides this
- * functionality by defining configTASK_RETURN_ADDRESS. Call
- * vTaskSwitchContext() so link time optimisation does not remove the
- * symbol. */
- vTaskSwitchContext();
- prvTaskExitError();
-
- /* Should not get here! */
- return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
- /* Not implemented in ports where there is nothing to return to.
- * Artificially force an assert. */
- configASSERT( uxCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
- portDISABLE_INTERRUPTS();
- uxCriticalNesting++;
-
- /* This is not the interrupt safe version of the enter critical function so
- * assert() if it is being called from an interrupt context. Only API
- * functions that end in "FromISR" can be used in an interrupt. Only assert if
- * the critical nesting count is 1 to protect against recursive calls if the
- * assert function also uses a critical section. */
- if( uxCriticalNesting == 1 )
- {
- configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
- }
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
- configASSERT( uxCriticalNesting );
- uxCriticalNesting--;
-
- if( uxCriticalNesting == 0 )
- {
- portENABLE_INTERRUPTS();
- }
-}
-/*-----------------------------------------------------------*/
-
-void xPortPendSVHandler( void )
-{
- /* This is a naked function. */
-
- __asm volatile
- (
- " mrs r0, psp \n"
- " isb \n"
- " \n"
- " ldr r3, pxCurrentTCBConst \n"/* Get the location of the current TCB. */
- " ldr r2, [r3] \n"
- " \n"
- " tst r14, #0x10 \n"/* Is the task using the FPU context? If so, push high vfp registers. */
- " it eq \n"
- " vstmdbeq r0!, {s16-s31} \n"
- " \n"
- " stmdb r0!, {r4-r11, r14} \n"/* Save the core registers. */
- " str r0, [r2] \n"/* Save the new top of stack into the first member of the TCB. */
- " \n"
- " stmdb sp!, {r0, r3} \n"
- " mov r0, %0 \n"
- " msr basepri, r0 \n"
- " dsb \n"
- " isb \n"
- " bl vTaskSwitchContext \n"
- " mov r0, #0 \n"
- " msr basepri, r0 \n"
- " ldmia sp!, {r0, r3} \n"
- " \n"
- " ldr r1, [r3] \n"/* The first item in pxCurrentTCB is the task top of stack. */
- " ldr r0, [r1] \n"
- " \n"
- " ldmia r0!, {r4-r11, r14} \n"/* Pop the core registers. */
- " \n"
- " tst r14, #0x10 \n"/* Is the task using the FPU context? If so, pop the high vfp registers too. */
- " it eq \n"
- " vldmiaeq r0!, {s16-s31} \n"
- " \n"
- " msr psp, r0 \n"
- " isb \n"
- " \n"
- #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */
- #if WORKAROUND_PMU_CM001 == 1
- " push { r14 } \n"
- " pop { pc } \n"
- #endif
- #endif
- " \n"
- " bx r14 \n"
- " \n"
- " .align 4 \n"
- "pxCurrentTCBConst: .word pxCurrentTCB \n"
- ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
- );
-}
-/*-----------------------------------------------------------*/
-
-void xPortSysTickHandler( void )
-{
- /* The SysTick runs at the lowest interrupt priority, so when this interrupt
- * executes all interrupts must be unmasked. There is therefore no need to
- * save and then restore the interrupt mask value as its value is already
- * known. */
- portDISABLE_INTERRUPTS();
- {
- /* Increment the RTOS tick. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- /* A context switch is required. Context switching is performed in
- * the PendSV interrupt. Pend the PendSV interrupt. */
- portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
- }
- }
- portENABLE_INTERRUPTS();
-}
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TICKLESS_IDLE == 1 )
-
- __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
- {
- uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
- TickType_t xModifiableIdleTime;
-
- /* Make sure the SysTick reload value does not overflow the counter. */
- if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
- {
- xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
- }
-
- /* Enter a critical section but don't use the taskENTER_CRITICAL()
- * method as that will mask interrupts that should exit sleep mode. */
- __asm volatile ( "cpsid i" ::: "memory" );
- __asm volatile ( "dsb" );
- __asm volatile ( "isb" );
-
- /* If a context switch is pending or a task is waiting for the scheduler
- * to be unsuspended then abandon the low power entry. */
- if( eTaskConfirmSleepModeStatus() == eAbortSleep )
- {
- /* Re-enable interrupts - see comments above the cpsid instruction
- * above. */
- __asm volatile ( "cpsie i" ::: "memory" );
- }
- else
- {
- /* Stop the SysTick momentarily. The time the SysTick is stopped for
- * is accounted for as best it can be, but using the tickless mode will
- * inevitably result in some tiny drift of the time maintained by the
- * kernel with respect to calendar time. */
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
-
- /* Use the SysTick current-value register to determine the number of
- * SysTick decrements remaining until the next tick interrupt. If the
- * current-value register is zero, then there are actually
- * ulTimerCountsForOneTick decrements remaining, not zero, because the
- * SysTick requests the interrupt when decrementing from 1 to 0. */
- ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
- if( ulSysTickDecrementsLeft == 0 )
- {
- ulSysTickDecrementsLeft = ulTimerCountsForOneTick;
- }
-
- /* Calculate the reload value required to wait xExpectedIdleTime
- * tick periods. -1 is used because this code normally executes part
- * way through the first tick period. But if the SysTick IRQ is now
- * pending, then clear the IRQ, suppressing the first tick, and correct
- * the reload value to reflect that the second tick period is already
- * underway. The expected idle time is always at least two ticks. */
- ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
-
- if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )
- {
- portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;
- ulReloadValue -= ulTimerCountsForOneTick;
- }
-
- if( ulReloadValue > ulStoppedTimerCompensation )
- {
- ulReloadValue -= ulStoppedTimerCompensation;
- }
-
- /* Set the new reload value. */
- portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
-
- /* Clear the SysTick count flag and set the count value back to
- * zero. */
- portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
- /* Restart SysTick. */
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
- /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
- * set its parameter to 0 to indicate that its implementation contains
- * its own wait for interrupt or wait for event instruction, and so wfi
- * should not be executed again. However, the original expected idle
- * time variable must remain unmodified, so a copy is taken. */
- xModifiableIdleTime = xExpectedIdleTime;
- configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
-
- if( xModifiableIdleTime > 0 )
- {
- __asm volatile ( "dsb" ::: "memory" );
- __asm volatile ( "wfi" );
- __asm volatile ( "isb" );
- }
-
- configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
-
- /* Re-enable interrupts to allow the interrupt that brought the MCU
- * out of sleep mode to execute immediately. See comments above
- * the cpsid instruction above. */
- __asm volatile ( "cpsie i" ::: "memory" );
- __asm volatile ( "dsb" );
- __asm volatile ( "isb" );
-
- /* Disable interrupts again because the clock is about to be stopped
- * and interrupts that execute while the clock is stopped will increase
- * any slippage between the time maintained by the RTOS and calendar
- * time. */
- __asm volatile ( "cpsid i" ::: "memory" );
- __asm volatile ( "dsb" );
- __asm volatile ( "isb" );
-
- /* Disable the SysTick clock without reading the
- * portNVIC_SYSTICK_CTRL_REG register to ensure the
- * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
- * the time the SysTick is stopped for is accounted for as best it can
- * be, but using the tickless mode will inevitably result in some tiny
- * drift of the time maintained by the kernel with respect to calendar
- * time*/
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
-
- /* Determine whether the SysTick has already counted to zero. */
- if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
- {
- uint32_t ulCalculatedLoadValue;
-
- /* The tick interrupt ended the sleep (or is now pending), and
- * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG
- * with whatever remains of the new tick period. */
- ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
-
- /* Don't allow a tiny value, or values that have somehow
- * underflowed because the post sleep hook did something
- * that took too long or because the SysTick current-value register
- * is zero. */
- if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
- {
- ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
- }
-
- portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
-
- /* As the pending tick will be processed as soon as this
- * function exits, the tick value maintained by the tick is stepped
- * forward by one less than the time spent waiting. */
- ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
- }
- else
- {
- /* Something other than the tick interrupt ended the sleep. */
-
- /* Use the SysTick current-value register to determine the
- * number of SysTick decrements remaining until the expected idle
- * time would have ended. */
- ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
- #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )
- {
- /* If the SysTick is not using the core clock, the current-
- * value register might still be zero here. In that case, the
- * SysTick didn't load from the reload register, and there are
- * ulReloadValue decrements remaining in the expected idle
- * time, not zero. */
- if( ulSysTickDecrementsLeft == 0 )
- {
- ulSysTickDecrementsLeft = ulReloadValue;
- }
- }
- #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
-
- /* Work out how long the sleep lasted rounded to complete tick
- * periods (not the ulReload value which accounted for part
- * ticks). */
- ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;
-
- /* How many complete tick periods passed while the processor
- * was waiting? */
- ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
-
- /* The reload value is set to whatever fraction of a single tick
- * period remains. */
- portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
- }
-
- /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,
- * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If
- * the SysTick is not using the core clock, temporarily configure it to
- * use the core clock. This configuration forces the SysTick to load
- * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next
- * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready
- * to receive the standard value immediately. */
- portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
- portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
- #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )
- {
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
- }
- #else
- {
- /* The temporary usage of the core clock has served its purpose,
- * as described above. Resume usage of the other clock. */
- portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
-
- if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
- {
- /* The partial tick period already ended. Be sure the SysTick
- * counts it only once. */
- portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;
- }
-
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
- portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
- }
- #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
-
- /* Step the tick to account for any tick periods that elapsed. */
- vTaskStepTick( ulCompleteTickPeriods );
-
- /* Exit with interrupts enabled. */
- __asm volatile ( "cpsie i" ::: "memory" );
- }
- }
-
-#endif /* #if configUSE_TICKLESS_IDLE */
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the systick timer to generate the tick interrupts at the required
- * frequency.
- */
-__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
-{
- /* Calculate the constants required to configure the tick interrupt. */
- #if ( configUSE_TICKLESS_IDLE == 1 )
- {
- ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
- xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
- ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
- }
- #endif /* configUSE_TICKLESS_IDLE */
-
- /* Stop and clear the SysTick. */
- portNVIC_SYSTICK_CTRL_REG = 0UL;
- portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
- /* Configure SysTick to interrupt at the requested rate. */
- portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
-}
-/*-----------------------------------------------------------*/
-
-/* This is a naked function. */
-static void vPortEnableVFP( void )
-{
- __asm volatile
- (
- " ldr.w r0, =0xE000ED88 \n"/* The FPU enable bits are in the CPACR. */
- " ldr r1, [r0] \n"
- " \n"
- " orr r1, r1, #( 0xf << 20 ) \n"/* Enable CP10 and CP11 coprocessors, then save back. */
- " str r1, [r0] \n"
- " bx r14 \n"
- " .ltorg \n"
- );
-}
-/*-----------------------------------------------------------*/
-
-#if ( configASSERT_DEFINED == 1 )
-
- void vPortValidateInterruptPriority( void )
- {
- uint32_t ulCurrentInterrupt;
- uint8_t ucCurrentPriority;
-
- /* Obtain the number of the currently executing interrupt. */
- __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
-
- /* Is the interrupt number a user defined interrupt? */
- if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
- {
- /* Look up the interrupt's priority. */
- ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
-
- /* The following assertion will fail if a service routine (ISR) for
- * an interrupt that has been assigned a priority above
- * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
- * function. ISR safe FreeRTOS API functions must *only* be called
- * from interrupts that have been assigned a priority at or below
- * configMAX_SYSCALL_INTERRUPT_PRIORITY.
- *
- * Numerically low interrupt priority numbers represent logically high
- * interrupt priorities, therefore the priority of the interrupt must
- * be set to a value equal to or numerically *higher* than
- * configMAX_SYSCALL_INTERRUPT_PRIORITY.
- *
- * Interrupts that use the FreeRTOS API must not be left at their
- * default priority of zero as that is the highest possible priority,
- * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
- * and therefore also guaranteed to be invalid.
- *
- * FreeRTOS maintains separate thread and ISR API functions to ensure
- * interrupt entry is as fast and simple as possible.
- *
- * The following links provide detailed information:
- * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
- * https://www.FreeRTOS.org/FAQHelp.html */
- configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
- }
-
- /* Priority grouping: The interrupt controller (NVIC) allows the bits
- * that define each interrupt's priority to be split between bits that
- * define the interrupt's pre-emption priority bits and bits that define
- * the interrupt's sub-priority. For simplicity all bits must be defined
- * to be pre-emption priority bits. The following assertion will fail if
- * this is not the case (if some bits represent a sub-priority).
- *
- * If the application only uses CMSIS libraries for interrupt
- * configuration then the correct setting can be achieved on all Cortex-M
- * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
- * scheduler. Note however that some vendor specific peripheral libraries
- * assume a non-zero priority group setting, in which cases using a value
- * of zero will result in unpredictable behaviour. */
- configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
- }
-
-#endif /* configASSERT_DEFINED */
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*-----------------------------------------------------------
+* Implementation of functions defined in portable.h for the ARM CM4F port.
+*----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef __VFP_FP__
+ #error This port can only be used when the project options are configured to enable hardware floating point support.
+#endif
+
+/* Constants required to manipulate the core. Registers first... */
+#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
+/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
+#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
+
+/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
+ * r0p1 port. */
+#define portCPUID ( *( ( volatile uint32_t * ) 0xE000ed00 ) )
+#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )
+#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )
+
+#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
+#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT ( 8UL )
+
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK ( 0xFFUL )
+
+/* Constants required to manipulate the VFP. */
+#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
+#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR ( 0x01000000 )
+#define portINITIAL_EXC_RETURN ( 0xfffffffd )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER ( 0xffffffUL )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+ * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+ * occurred while the SysTick counter is stopped during tickless idle
+ * calculations. */
+#define portMISSED_COUNTS_FACTOR ( 94UL )
+
+/* Let the user override the default SysTick clock rate. If defined by the
+ * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
+ * configuration register. */
+#ifndef configSYSTICK_CLOCK_HZ
+ #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ )
+ /* Ensure the SysTick is clocked at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT )
+#else
+ /* Select the option to clock SysTick not at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 )
+#endif
+
+/* Let the user override the pre-loading of the initial LR with the address of
+ * prvTaskExitError() in case it messes up unwinding of the stack in the
+ * debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
+#else
+ #define portTASK_RETURN_ADDRESS prvTaskExitError
+#endif
+
+/*
+ * Setup the timer to generate the tick interrupts. The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortPendSVHandler( void ) __attribute__( ( naked ) );
+void xPortSysTickHandler( void );
+void vPortSVCHandler( void ) __attribute__( ( naked ) );
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+static void prvPortStartFirstTask( void ) __attribute__( ( naked ) );
+
+/*
+ * Function to enable the VFP.
+ */
+static void vPortEnableVFP( void ) __attribute__( ( naked ) );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+ * variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+ static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+ static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+ static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( configASSERT_DEFINED == 1 )
+ static uint8_t ucMaxSysCallPriority = 0;
+ static uint32_t ulMaxPRIGROUPValue = 0;
+ static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+ TaskFunction_t pxCode,
+ void * pvParameters )
+{
+ /* Simulate the stack frame as it would be created by a context switch
+ * interrupt. */
+
+ /* Offset added to account for the way the MCU uses the stack on entry/exit
+ * of interrupts, and to ensure alignment. */
+ pxTopOfStack--;
+
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+
+ /* Save code space by skipping register initialisation. */
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+
+ /* A save method is being used that requires each task to maintain its
+ * own exec return value. */
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_EXC_RETURN;
+
+ pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+ volatile uint32_t ulDummy = 0;
+
+ /* A function that implements a task must not exit or attempt to return to
+ * its caller as there is nothing to return to. If a task wants to exit it
+ * should instead call vTaskDelete( NULL ).
+ *
+ * Artificially force an assert() to be triggered if configASSERT() is
+ * defined, then stop here so application writers can catch the error. */
+ configASSERT( uxCriticalNesting == ~0UL );
+ portDISABLE_INTERRUPTS();
+
+ while( ulDummy == 0 )
+ {
+ /* This file calls prvTaskExitError() after the scheduler has been
+ * started to remove a compiler warning about the function being defined
+ * but never called. ulDummy is used purely to quieten other warnings
+ * about code appearing after this function is called - making ulDummy
+ * volatile makes the compiler think the function could return and
+ * therefore not output an 'unreachable code' warning for code that appears
+ * after it. */
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler( void )
+{
+ __asm volatile (
+ " ldr r3, pxCurrentTCBConst2 \n"/* Restore the context. */
+ " ldr r1, [r3] \n"/* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
+ " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. */
+ " ldmia r0!, {r4-r11, r14} \n"/* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
+ " msr psp, r0 \n"/* Restore the task stack pointer. */
+ " isb \n"
+ " mov r0, #0 \n"
+ " msr basepri, r0 \n"
+ " bx r14 \n"
+ " \n"
+ " .align 4 \n"
+ "pxCurrentTCBConst2: .word pxCurrentTCB \n"
+ );
+}
+/*-----------------------------------------------------------*/
+
+static void prvPortStartFirstTask( void )
+{
+ /* Start the first task. This also clears the bit that indicates the FPU is
+ * in use in case the FPU was used before the scheduler was started - which
+ * would otherwise result in the unnecessary leaving of space in the SVC stack
+ * for lazy saving of FPU registers. */
+ __asm volatile (
+ " ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */
+ " ldr r0, [r0] \n"
+ " ldr r0, [r0] \n"
+ " msr msp, r0 \n"/* Set the msp back to the start of the stack. */
+ " mov r0, #0 \n"/* Clear the bit that indicates the FPU is in use, see comment above. */
+ " msr control, r0 \n"
+ " cpsie i \n"/* Globally enable interrupts. */
+ " cpsie f \n"
+ " dsb \n"
+ " isb \n"
+ " svc 0 \n"/* System call to start first task. */
+ " nop \n"
+ " .ltorg \n"
+ );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+ /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
+ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+
+ /* This port can be used on all revisions of the Cortex-M7 core other than
+ * the r0p1 parts. r0p1 parts should use the port from the
+ * /source/portable/GCC/ARM_CM7/r0p1 directory. */
+ configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
+ configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
+
+ #if ( configASSERT_DEFINED == 1 )
+ {
+ volatile uint32_t ulOriginalPriority;
+ volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine the maximum priority from which ISR safe FreeRTOS API
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * ensure interrupt entry is as fast and simple as possible.
+ *
+ * Save the interrupt priority value that is about to be clobbered. */
+ ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+ /* Determine the number of priority bits available. First write to all
+ * possible bits. */
+ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+ /* Use the same mask on the maximum system call priority. */
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+ /* Calculate the maximum acceptable priority group value for the number
+ * of bits read back. */
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+ {
+ ulMaxPRIGROUPValue--;
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+ }
+
+ #ifdef __NVIC_PRIO_BITS
+ {
+ /* Check the CMSIS configuration that defines the number of
+ * priority bits matches the number of priority bits actually queried
+ * from the hardware. */
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+ }
+ #endif
+
+ #ifdef configPRIO_BITS
+ {
+ /* Check the FreeRTOS configuration that defines the number of
+ * priority bits matches the number of priority bits actually queried
+ * from the hardware. */
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+ }
+ #endif
+
+ /* Shift the priority group value back to its position within the AIRCR
+ * register. */
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+ /* Restore the clobbered interrupt priority register to its original
+ * value. */
+ *pucFirstUserPriorityRegister = ulOriginalPriority;
+ }
+ #endif /* configASSERT_DEFINED */
+
+ /* Make PendSV and SysTick the lowest priority interrupts. */
+ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
+ portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ * here already. */
+ vPortSetupTimerInterrupt();
+
+ /* Initialise the critical nesting count ready for the first task. */
+ uxCriticalNesting = 0;
+
+ /* Ensure the VFP is enabled - it should be anyway. */
+ vPortEnableVFP();
+
+ /* Lazy save always. */
+ *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
+
+ /* Start the first task. */
+ prvPortStartFirstTask();
+
+ /* Should never get here as the tasks will now be executing! Call the task
+ * exit error function to prevent compiler warnings about a static function
+ * not being called in the case that the application writer overrides this
+ * functionality by defining configTASK_RETURN_ADDRESS. Call
+ * vTaskSwitchContext() so link time optimisation does not remove the
+ * symbol. */
+ vTaskSwitchContext();
+ prvTaskExitError();
+
+ /* Should not get here! */
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+ /* Not implemented in ports where there is nothing to return to.
+ * Artificially force an assert. */
+ configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+ portDISABLE_INTERRUPTS();
+ uxCriticalNesting++;
+
+ /* This is not the interrupt safe version of the enter critical function so
+ * assert() if it is being called from an interrupt context. Only API
+ * functions that end in "FromISR" can be used in an interrupt. Only assert if
+ * the critical nesting count is 1 to protect against recursive calls if the
+ * assert function also uses a critical section. */
+ if( uxCriticalNesting == 1 )
+ {
+ configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+ configASSERT( uxCriticalNesting );
+ uxCriticalNesting--;
+
+ if( uxCriticalNesting == 0 )
+ {
+ portENABLE_INTERRUPTS();
+ }
+}
+/*-----------------------------------------------------------*/
+
+void xPortPendSVHandler( void )
+{
+ /* This is a naked function. */
+
+ __asm volatile
+ (
+ " mrs r0, psp \n"
+ " isb \n"
+ " \n"
+ " ldr r3, pxCurrentTCBConst \n"/* Get the location of the current TCB. */
+ " ldr r2, [r3] \n"
+ " \n"
+ " tst r14, #0x10 \n"/* Is the task using the FPU context? If so, push high vfp registers. */
+ " it eq \n"
+ " vstmdbeq r0!, {s16-s31} \n"
+ " \n"
+ " stmdb r0!, {r4-r11, r14} \n"/* Save the core registers. */
+ " str r0, [r2] \n"/* Save the new top of stack into the first member of the TCB. */
+ " \n"
+ " stmdb sp!, {r0, r3} \n"
+ " mov r0, %0 \n"
+ " msr basepri, r0 \n"
+ " dsb \n"
+ " isb \n"
+ " bl vTaskSwitchContext \n"
+ " mov r0, #0 \n"
+ " msr basepri, r0 \n"
+ " ldmia sp!, {r0, r3} \n"
+ " \n"
+ " ldr r1, [r3] \n"/* The first item in pxCurrentTCB is the task top of stack. */
+ " ldr r0, [r1] \n"
+ " \n"
+ " ldmia r0!, {r4-r11, r14} \n"/* Pop the core registers. */
+ " \n"
+ " tst r14, #0x10 \n"/* Is the task using the FPU context? If so, pop the high vfp registers too. */
+ " it eq \n"
+ " vldmiaeq r0!, {s16-s31} \n"
+ " \n"
+ " msr psp, r0 \n"
+ " isb \n"
+ " \n"
+ #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */
+ #if WORKAROUND_PMU_CM001 == 1
+ " push { r14 } \n"
+ " pop { pc } \n"
+ #endif
+ #endif
+ " \n"
+ " bx r14 \n"
+ " \n"
+ " .align 4 \n"
+ "pxCurrentTCBConst: .word pxCurrentTCB \n"
+ ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+ );
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+ /* The SysTick runs at the lowest interrupt priority, so when this interrupt
+ * executes all interrupts must be unmasked. There is therefore no need to
+ * save and then restore the interrupt mask value as its value is already
+ * known. */
+ portDISABLE_INTERRUPTS();
+ {
+ /* Increment the RTOS tick. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ /* A context switch is required. Context switching is performed in
+ * the PendSV interrupt. Pend the PendSV interrupt. */
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+ }
+ }
+ portENABLE_INTERRUPTS();
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+
+ __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+ {
+ uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
+ TickType_t xModifiableIdleTime;
+
+ /* Make sure the SysTick reload value does not overflow the counter. */
+ if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+ {
+ xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+ }
+
+ /* Enter a critical section but don't use the taskENTER_CRITICAL()
+ * method as that will mask interrupts that should exit sleep mode. */
+ __asm volatile ( "cpsid i" ::: "memory" );
+ __asm volatile ( "dsb" );
+ __asm volatile ( "isb" );
+
+ /* If a context switch is pending or a task is waiting for the scheduler
+ * to be unsuspended then abandon the low power entry. */
+ if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+ {
+ /* Re-enable interrupts - see comments above the cpsid instruction
+ * above. */
+ __asm volatile ( "cpsie i" ::: "memory" );
+ }
+ else
+ {
+ /* Stop the SysTick momentarily. The time the SysTick is stopped for
+ * is accounted for as best it can be, but using the tickless mode will
+ * inevitably result in some tiny drift of the time maintained by the
+ * kernel with respect to calendar time. */
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
+
+ /* Use the SysTick current-value register to determine the number of
+ * SysTick decrements remaining until the next tick interrupt. If the
+ * current-value register is zero, then there are actually
+ * ulTimerCountsForOneTick decrements remaining, not zero, because the
+ * SysTick requests the interrupt when decrementing from 1 to 0. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulTimerCountsForOneTick;
+ }
+
+ /* Calculate the reload value required to wait xExpectedIdleTime
+ * tick periods. -1 is used because this code normally executes part
+ * way through the first tick period. But if the SysTick IRQ is now
+ * pending, then clear the IRQ, suppressing the first tick, and correct
+ * the reload value to reflect that the second tick period is already
+ * underway. The expected idle time is always at least two ticks. */
+ ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+ if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )
+ {
+ portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;
+ ulReloadValue -= ulTimerCountsForOneTick;
+ }
+
+ if( ulReloadValue > ulStoppedTimerCompensation )
+ {
+ ulReloadValue -= ulStoppedTimerCompensation;
+ }
+
+ /* Set the new reload value. */
+ portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+ /* Clear the SysTick count flag and set the count value back to
+ * zero. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+ /* Restart SysTick. */
+ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+ /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
+ * set its parameter to 0 to indicate that its implementation contains
+ * its own wait for interrupt or wait for event instruction, and so wfi
+ * should not be executed again. However, the original expected idle
+ * time variable must remain unmodified, so a copy is taken. */
+ xModifiableIdleTime = xExpectedIdleTime;
+ configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+
+ if( xModifiableIdleTime > 0 )
+ {
+ __asm volatile ( "dsb" ::: "memory" );
+ __asm volatile ( "wfi" );
+ __asm volatile ( "isb" );
+ }
+
+ configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+ /* Re-enable interrupts to allow the interrupt that brought the MCU
+ * out of sleep mode to execute immediately. See comments above
+ * the cpsid instruction above. */
+ __asm volatile ( "cpsie i" ::: "memory" );
+ __asm volatile ( "dsb" );
+ __asm volatile ( "isb" );
+
+ /* Disable interrupts again because the clock is about to be stopped
+ * and interrupts that execute while the clock is stopped will increase
+ * any slippage between the time maintained by the RTOS and calendar
+ * time. */
+ __asm volatile ( "cpsid i" ::: "memory" );
+ __asm volatile ( "dsb" );
+ __asm volatile ( "isb" );
+
+ /* Disable the SysTick clock without reading the
+ * portNVIC_SYSTICK_CTRL_REG register to ensure the
+ * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
+ * the time the SysTick is stopped for is accounted for as best it can
+ * be, but using the tickless mode will inevitably result in some tiny
+ * drift of the time maintained by the kernel with respect to calendar
+ * time*/
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
+
+ /* Determine whether the SysTick has already counted to zero. */
+ if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+ {
+ uint32_t ulCalculatedLoadValue;
+
+ /* The tick interrupt ended the sleep (or is now pending), and
+ * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG
+ * with whatever remains of the new tick period. */
+ ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+ /* Don't allow a tiny value, or values that have somehow
+ * underflowed because the post sleep hook did something
+ * that took too long or because the SysTick current-value register
+ * is zero. */
+ if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+ {
+ ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+ }
+
+ portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+ /* As the pending tick will be processed as soon as this
+ * function exits, the tick value maintained by the tick is stepped
+ * forward by one less than the time spent waiting. */
+ ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+ }
+ else
+ {
+ /* Something other than the tick interrupt ended the sleep. */
+
+ /* Use the SysTick current-value register to determine the
+ * number of SysTick decrements remaining until the expected idle
+ * time would have ended. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )
+ {
+ /* If the SysTick is not using the core clock, the current-
+ * value register might still be zero here. In that case, the
+ * SysTick didn't load from the reload register, and there are
+ * ulReloadValue decrements remaining in the expected idle
+ * time, not zero. */
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulReloadValue;
+ }
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Work out how long the sleep lasted rounded to complete tick
+ * periods (not the ulReload value which accounted for part
+ * ticks). */
+ ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;
+
+ /* How many complete tick periods passed while the processor
+ * was waiting? */
+ ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+ /* The reload value is set to whatever fraction of a single tick
+ * period remains. */
+ portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+ }
+
+ /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,
+ * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If
+ * the SysTick is not using the core clock, temporarily configure it to
+ * use the core clock. This configuration forces the SysTick to load
+ * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next
+ * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready
+ * to receive the standard value immediately. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )
+ {
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ }
+ #else
+ {
+ /* The temporary usage of the core clock has served its purpose,
+ * as described above. Resume usage of the other clock. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
+
+ if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+ {
+ /* The partial tick period already ended. Be sure the SysTick
+ * counts it only once. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;
+ }
+
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Step the tick to account for any tick periods that elapsed. */
+ vTaskStepTick( ulCompleteTickPeriods );
+
+ /* Exit with interrupts enabled. */
+ __asm volatile ( "cpsie i" ::: "memory" );
+ }
+ }
+
+#endif /* #if configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
+{
+ /* Calculate the constants required to configure the tick interrupt. */
+ #if ( configUSE_TICKLESS_IDLE == 1 )
+ {
+ ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+ xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+ ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+ }
+ #endif /* configUSE_TICKLESS_IDLE */
+
+ /* Stop and clear the SysTick. */
+ portNVIC_SYSTICK_CTRL_REG = 0UL;
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+ /* Configure SysTick to interrupt at the requested rate. */
+ portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+}
+/*-----------------------------------------------------------*/
+
+/* This is a naked function. */
+static void vPortEnableVFP( void )
+{
+ __asm volatile
+ (
+ " ldr.w r0, =0xE000ED88 \n"/* The FPU enable bits are in the CPACR. */
+ " ldr r1, [r0] \n"
+ " \n"
+ " orr r1, r1, #( 0xf << 20 ) \n"/* Enable CP10 and CP11 coprocessors, then save back. */
+ " str r1, [r0] \n"
+ " bx r14 \n"
+ " .ltorg \n"
+ );
+}
+/*-----------------------------------------------------------*/
+
+#if ( configASSERT_DEFINED == 1 )
+
+ void vPortValidateInterruptPriority( void )
+ {
+ uint32_t ulCurrentInterrupt;
+ uint8_t ucCurrentPriority;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ /* Is the interrupt number a user defined interrupt? */
+ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+ {
+ /* Look up the interrupt's priority. */
+ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+ /* The following assertion will fail if a service routine (ISR) for
+ * an interrupt that has been assigned a priority above
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+ * function. ISR safe FreeRTOS API functions must *only* be called
+ * from interrupts that have been assigned a priority at or below
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Numerically low interrupt priority numbers represent logically high
+ * interrupt priorities, therefore the priority of the interrupt must
+ * be set to a value equal to or numerically *higher* than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Interrupts that use the FreeRTOS API must not be left at their
+ * default priority of zero as that is the highest possible priority,
+ * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+ * and therefore also guaranteed to be invalid.
+ *
+ * FreeRTOS maintains separate thread and ISR API functions to ensure
+ * interrupt entry is as fast and simple as possible.
+ *
+ * The following links provide detailed information:
+ * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+ * https://www.FreeRTOS.org/FAQHelp.html */
+ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+ }
+
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits
+ * that define each interrupt's priority to be split between bits that
+ * define the interrupt's pre-emption priority bits and bits that define
+ * the interrupt's sub-priority. For simplicity all bits must be defined
+ * to be pre-emption priority bits. The following assertion will fail if
+ * this is not the case (if some bits represent a sub-priority).
+ *
+ * If the application only uses CMSIS libraries for interrupt
+ * configuration then the correct setting can be achieved on all Cortex-M
+ * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+ * scheduler. Note however that some vendor specific peripheral libraries
+ * assume a non-zero priority group setting, in which cases using a value
+ * of zero will result in unpredictable behaviour. */
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+ }
+
+#endif /* configASSERT_DEFINED */
diff --git a/portable/GCC/ARM_CM4F/portmacro.h b/portable/GCC/ARM_CM4F/portmacro.h
index 818bb04..0ab47e0 100644
--- a/portable/GCC/ARM_CM4F/portmacro.h
+++ b/portable/GCC/ARM_CM4F/portmacro.h
@@ -1,245 +1,245 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-
-#ifndef PORTMACRO_H
- #define PORTMACRO_H
-
- #ifdef __cplusplus
- extern "C" {
- #endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
-
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
-
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portDONT_DISCARD __attribute__( ( used ) )
-/*-----------------------------------------------------------*/
-
-/* Scheduler utilities. */
- #define portYIELD() \
- { \
- /* Set a PendSV to request a context switch. */ \
- portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
- \
- /* Barriers are normally not required but do ensure the code is completely \
- * within the specified behaviour for the architecture. */ \
- __asm volatile ( "dsb" ::: "memory" ); \
- __asm volatile ( "isb" ); \
- }
-
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 )
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/* Critical section management. */
- extern void vPortEnterCritical( void );
- extern void vPortExitCritical( void );
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x )
- #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
- #define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. These are
- * not necessary for to use this port. They are defined so the common demo files
- * (which build with all the ports) will build. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
-/*-----------------------------------------------------------*/
-
-/* Tickless idle/low power functionality. */
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specific optimisations. */
- #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
- #endif
-
- #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
-/* Generic helper function. */
- __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
- {
- uint8_t ucReturn;
-
- __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
-
- return ucReturn;
- }
-
-/* Check the configuration. */
- #if ( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
-
-/* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-/*-----------------------------------------------------------*/
-
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
-
- #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-/*-----------------------------------------------------------*/
-
- #ifdef configASSERT
- void vPortValidateInterruptPriority( void );
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
- #endif
-
-/* portNOP() is not required by this port. */
- #define portNOP()
-
- #define portINLINE __inline
-
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
- #endif
-
- portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
- {
- uint32_t ulCurrentInterrupt;
- BaseType_t xReturn;
-
- /* Obtain the number of the currently executing interrupt. */
- __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
-
- if( ulCurrentInterrupt == 0 )
- {
- xReturn = pdFALSE;
- }
- else
- {
- xReturn = pdTRUE;
- }
-
- return xReturn;
- }
-
-/*-----------------------------------------------------------*/
-
- portFORCE_INLINE static void vPortRaiseBASEPRI( void )
- {
- uint32_t ulNewBASEPRI;
-
- __asm volatile
- (
- " mov %0, %1 \n"\
- " msr basepri, %0 \n"\
- " isb \n"\
- " dsb \n"\
- : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
- );
- }
-
-/*-----------------------------------------------------------*/
-
- portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
- {
- uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
-
- __asm volatile
- (
- " mrs %0, basepri \n"\
- " mov %1, %2 \n"\
- " msr basepri, %1 \n"\
- " isb \n"\
- " dsb \n"\
- : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
- );
-
- /* This return will not be reached but is necessary to prevent compiler
- * warnings. */
- return ulOriginalBASEPRI;
- }
-/*-----------------------------------------------------------*/
-
- portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
- {
- __asm volatile
- (
- " msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory"
- );
- }
-/*-----------------------------------------------------------*/
-
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
-
- #ifdef __cplusplus
- }
- #endif
-
-#endif /* PORTMACRO_H */
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+#ifndef PORTMACRO_H
+ #define PORTMACRO_H
+
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+ #define portCHAR char
+ #define portFLOAT float
+ #define portDOUBLE double
+ #define portLONG long
+ #define portSHORT short
+ #define portSTACK_TYPE uint32_t
+ #define portBASE_TYPE long
+
+ typedef portSTACK_TYPE StackType_t;
+ typedef long BaseType_t;
+ typedef unsigned long UBaseType_t;
+
+ #if ( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+ #else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+ #endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+ #define portSTACK_GROWTH ( -1 )
+ #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+ #define portBYTE_ALIGNMENT 8
+ #define portDONT_DISCARD __attribute__( ( used ) )
+/*-----------------------------------------------------------*/
+
+/* Scheduler utilities. */
+ #define portYIELD() \
+ { \
+ /* Set a PendSV to request a context switch. */ \
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+ \
+ /* Barriers are normally not required but do ensure the code is completely \
+ * within the specified behaviour for the architecture. */ \
+ __asm volatile ( "dsb" ::: "memory" ); \
+ __asm volatile ( "isb" ); \
+ }
+
+ #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+ #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+ #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 )
+ #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+ extern void vPortEnterCritical( void );
+ extern void vPortExitCritical( void );
+ #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
+ #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x )
+ #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
+ #define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )
+ #define portENTER_CRITICAL() vPortEnterCritical()
+ #define portEXIT_CRITICAL() vPortExitCritical()
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. These are
+ * not necessary for to use this port. They are defined so the common demo files
+ * (which build with all the ports) will build. */
+ #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+ #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+ #ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+ #endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+ #endif
+
+ #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+/* Generic helper function. */
+ __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+ {
+ uint8_t ucReturn;
+
+ __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
+
+ return ucReturn;
+ }
+
+/* Check the configuration. */
+ #if ( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
+
+/* Store/clear the ready priorities in a bit map. */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/*-----------------------------------------------------------*/
+
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+ #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+ #ifdef configASSERT
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+ #endif
+
+/* portNOP() is not required by this port. */
+ #define portNOP()
+
+ #define portINLINE __inline
+
+ #ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+ #endif
+
+ portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+ {
+ uint32_t ulCurrentInterrupt;
+ BaseType_t xReturn;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ if( ulCurrentInterrupt == 0 )
+ {
+ xReturn = pdFALSE;
+ }
+ else
+ {
+ xReturn = pdTRUE;
+ }
+
+ return xReturn;
+ }
+
+/*-----------------------------------------------------------*/
+
+ portFORCE_INLINE static void vPortRaiseBASEPRI( void )
+ {
+ uint32_t ulNewBASEPRI;
+
+ __asm volatile
+ (
+ " mov %0, %1 \n"\
+ " msr basepri, %0 \n"\
+ " isb \n"\
+ " dsb \n"\
+ : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+ );
+ }
+
+/*-----------------------------------------------------------*/
+
+ portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
+ {
+ uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
+
+ __asm volatile
+ (
+ " mrs %0, basepri \n"\
+ " mov %1, %2 \n"\
+ " msr basepri, %1 \n"\
+ " isb \n"\
+ " dsb \n"\
+ : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+ );
+
+ /* This return will not be reached but is necessary to prevent compiler
+ * warnings. */
+ return ulOriginalBASEPRI;
+ }
+/*-----------------------------------------------------------*/
+
+ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
+ {
+ __asm volatile
+ (
+ " msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+
+ #ifdef __cplusplus
+ }
+ #endif
+
+#endif /* PORTMACRO_H */
diff --git a/portable/GCC/ARM_CM4_MPU/port.c b/portable/GCC/ARM_CM4_MPU/port.c
index 97bef2b..3125f78 100644
--- a/portable/GCC/ARM_CM4_MPU/port.c
+++ b/portable/GCC/ARM_CM4_MPU/port.c
@@ -1,1044 +1,1044 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the ARM CM4 MPU port.
-*----------------------------------------------------------*/
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
- * all the API functions to use the MPU wrappers. That should only be done when
- * task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-#ifndef __VFP_FP__
- #error This port can only be used when the project options are configured to enable hardware floating point support.
-#endif
-
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#ifndef configSYSTICK_CLOCK_HZ
- #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
- /* Ensure the SysTick is clocked at the same frequency as the core. */
- #define portNVIC_SYSTICK_CLK ( 1UL << 2UL )
-#else
-
-/* The way the SysTick is clocked is not modified in case it is not the same
- * as the core. */
- #define portNVIC_SYSTICK_CLK ( 0 )
-#endif
-
-#ifndef configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS
- #warning "configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS is not defined. We recommend defining it to 0 in FreeRTOSConfig.h for better security."
- #define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS 1
-#endif
-
-/* Constants required to access and manipulate the NVIC. */
-#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
-#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
-#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
-#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
-#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) )
-#define portNVIC_SYS_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
-#define portNVIC_MEM_FAULT_ENABLE ( 1UL << 16UL )
-
-/* Constants used to detect Cortex-M7 r0p0 and r0p1 cores, and ensure
- * that a work around is active for errata 837070. */
-#define portCPUID ( *( ( volatile uint32_t * ) 0xE000ed00 ) )
-#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )
-#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )
-
-/* Constants required to access and manipulate the MPU. */
-#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_REGION_BASE_ADDRESS_REG ( *( ( volatile uint32_t * ) 0xe000ed9C ) )
-#define portMPU_REGION_ATTRIBUTE_REG ( *( ( volatile uint32_t * ) 0xe000edA0 ) )
-#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
-#define portMPU_ENABLE ( 0x01UL )
-#define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL )
-#define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL )
-#define portMPU_REGION_VALID ( 0x10UL )
-#define portMPU_REGION_ENABLE ( 0x01UL )
-#define portPERIPHERALS_START_ADDRESS 0x40000000UL
-#define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL
-
-/* Constants required to access and manipulate the SysTick. */
-#define portNVIC_SYSTICK_INT ( 0x00000002UL )
-#define portNVIC_SYSTICK_ENABLE ( 0x00000001UL )
-#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
-#define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
-
-/* Constants required to manipulate the VFP. */
-#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34UL ) /* Floating point context control register. */
-#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
-
-/* Constants required to set up the initial stack. */
-#define portINITIAL_XPSR ( 0x01000000UL )
-#define portINITIAL_EXC_RETURN ( 0xfffffffdUL )
-#define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 )
-#define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 )
-
-/* Constants required to check the validity of an interrupt priority. */
-#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
-#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
-#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
-#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
-#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
-#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
-#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
-#define portPRIGROUP_SHIFT ( 8UL )
-
-/* Offsets in the stack to the parameters when inside the SVC handler. */
-#define portOFFSET_TO_PC ( 6 )
-
-/* For strict compliance with the Cortex-M spec the task start address should
- * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
-#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
-
-/*
- * Configure a number of standard MPU regions that are used by all tasks.
- */
-static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Return the smallest MPU region size that a given number of bytes will fit
- * into. The region size is returned as the value that should be programmed
- * into the region attribute register for that region.
- */
-static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
-
-/*
- * Setup the timer to generate the tick interrupts. The implementation in this
- * file is weak to allow application writers to change the timer used to
- * generate the tick interrupt.
- */
-void vPortSetupTimerInterrupt( void );
-
-/*
- * Standard FreeRTOS exception handlers.
- */
-void xPortPendSVHandler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-void xPortSysTickHandler( void ) PRIVILEGED_FUNCTION;
-void vPortSVCHandler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/*
- * Starts the scheduler by restoring the context of the first task to run.
- */
-static void prvRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/*
- * C portion of the SVC handler. The SVC handler is split between an asm entry
- * and a C wrapper for simplicity of coding and maintenance.
- */
-static void prvSVCHandler( uint32_t * pulRegisters ) __attribute__( ( noinline ) ) PRIVILEGED_FUNCTION;
-
-/*
- * Function to enable the VFP.
- */
-static void vPortEnableVFP( void ) __attribute__( ( naked ) );
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
-BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- * Bit[0] = 0 --> The processor is running privileged
- * Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vResetPrivilege( void ) __attribute__( ( naked ) );
-
-/**
- * @brief Enter critical section.
- */
-#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
- void vPortEnterCritical( void ) FREERTOS_SYSTEM_CALL;
-#else
- void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
-#endif
-
-/**
- * @brief Exit from critical section.
- */
-#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
- void vPortExitCritical( void ) FREERTOS_SYSTEM_CALL;
-#else
- void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
-#endif
-/*-----------------------------------------------------------*/
-
-/* Each task maintains its own interrupt status in the critical nesting
- * variable. Note this is not saved as part of the task context as context
- * switches can only occur when uxCriticalNesting is zero. */
-static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
-
-/*
- * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
- * FreeRTOS API functions are not called from interrupts that have been assigned
- * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
- */
-#if ( configASSERT_DEFINED == 1 )
- static uint8_t ucMaxSysCallPriority = 0;
- static uint32_t ulMaxPRIGROUPValue = 0;
- static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
-#endif /* configASSERT_DEFINED */
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters,
- BaseType_t xRunPrivileged )
-{
- /* Simulate the stack frame as it would be created by a context switch
- * interrupt. */
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
- *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
- pxTopOfStack--;
- *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
- pxTopOfStack--;
- *pxTopOfStack = 0; /* LR */
- pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
-
- /* A save method is being used that requires each task to maintain its
- * own exec return value. */
- pxTopOfStack--;
- *pxTopOfStack = portINITIAL_EXC_RETURN;
-
- pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
-
- if( xRunPrivileged == pdTRUE )
- {
- *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;
- }
- else
- {
- *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;
- }
-
- return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-void vPortSVCHandler( void )
-{
- /* Assumes psp was in use. */
- __asm volatile
- (
- #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */
- " tst lr, #4 \n"
- " ite eq \n"
- " mrseq r0, msp \n"
- " mrsne r0, psp \n"
- #else
- " mrs r0, psp \n"
- #endif
- " b %0 \n"
- ::"i" ( prvSVCHandler ) : "r0", "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-static void prvSVCHandler( uint32_t * pulParam )
-{
- uint8_t ucSVCNumber;
- uint32_t ulPC;
-
- #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
- #if defined( __ARMCC_VERSION )
-
- /* Declaration when these variable are defined in code instead of being
- * exported from linker scripts. */
- extern uint32_t * __syscalls_flash_start__;
- extern uint32_t * __syscalls_flash_end__;
- #else
- /* Declaration when these variable are exported from linker scripts. */
- extern uint32_t __syscalls_flash_start__[];
- extern uint32_t __syscalls_flash_end__[];
- #endif /* #if defined( __ARMCC_VERSION ) */
- #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
-
- /* The stack contains: r0, r1, r2, r3, r12, LR, PC and xPSR. The first
- * argument (r0) is pulParam[ 0 ]. */
- ulPC = pulParam[ portOFFSET_TO_PC ];
- ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
-
- switch( ucSVCNumber )
- {
- case portSVC_START_SCHEDULER:
- portNVIC_SHPR2_REG |= portNVIC_SVC_PRI;
- prvRestoreContextOfFirstTask();
- break;
-
- case portSVC_YIELD:
- portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
-
- /* Barriers are normally not required
- * but do ensure the code is completely
- * within the specified behaviour for the
- * architecture. */
- __asm volatile ( "dsb" ::: "memory" );
- __asm volatile ( "isb" );
-
- break;
-
- #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
- case portSVC_RAISE_PRIVILEGE: /* Only raise the privilege, if the
- * svc was raised from any of the
- * system calls. */
-
- if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
- ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
- {
- __asm volatile
- (
- " mrs r1, control \n"/* Obtain current control value. */
- " bic r1, #1 \n"/* Set privilege bit. */
- " msr control, r1 \n"/* Write back new control value. */
- ::: "r1", "memory"
- );
- }
-
- break;
- #else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
- case portSVC_RAISE_PRIVILEGE:
- __asm volatile
- (
- " mrs r1, control \n"/* Obtain current control value. */
- " bic r1, #1 \n"/* Set privilege bit. */
- " msr control, r1 \n"/* Write back new control value. */
- ::: "r1", "memory"
- );
- break;
- #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
-
- default: /* Unknown SVC call. */
- break;
- }
-}
-/*-----------------------------------------------------------*/
-
-static void prvRestoreContextOfFirstTask( void )
-{
- __asm volatile
- (
- " ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */
- " ldr r0, [r0] \n"
- " ldr r0, [r0] \n"
- " msr msp, r0 \n"/* Set the msp back to the start of the stack. */
- " ldr r3, pxCurrentTCBConst2 \n"/* Restore the context. */
- " ldr r1, [r3] \n"
- " ldr r0, [r1] \n"/* The first item in the TCB is the task top of stack. */
- " add r1, r1, #4 \n"/* Move onto the second item in the TCB... */
- " \n"
- " dmb \n"/* Complete outstanding transfers before disabling MPU. */
- " ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */
- " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */
- " bic r3, #1 \n"/* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
- " str r3, [r2] \n"/* Disable MPU. */
- " \n"
- " ldr r2, =0xe000ed9c \n"/* Region Base Address register. */
- " ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
- " stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
- " \n"
- #if ( configTOTAL_MPU_REGIONS == 16 )
- " ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
- " stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
- " ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
- " stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
- #endif /* configTOTAL_MPU_REGIONS == 16. */
- " \n"
- " ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */
- " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */
- " orr r3, #1 \n"/* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
- " str r3, [r2] \n"/* Enable MPU. */
- " dsb \n"/* Force memory writes before continuing. */
- " \n"
- " ldmia r0!, {r3-r11, r14} \n"/* Pop the registers that are not automatically saved on exception entry. */
- " msr control, r3 \n"
- " msr psp, r0 \n"/* Restore the task stack pointer. */
- " mov r0, #0 \n"
- " msr basepri, r0 \n"
- " bx r14 \n"
- " \n"
- " .ltorg \n"/* Assemble current literal pool to avoid offset-out-of-bound errors with lto. */
- " .align 4 \n"
- "pxCurrentTCBConst2: .word pxCurrentTCB \n"
- );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-BaseType_t xPortStartScheduler( void )
-{
- /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See
- * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
- configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
-
- /* Errata 837070 workaround must only be enabled on Cortex-M7 r0p0
- * and r0p1 cores. */
- #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
- configASSERT( ( portCPUID == portCORTEX_M7_r0p1_ID ) || ( portCPUID == portCORTEX_M7_r0p0_ID ) );
- #else
- /* When using this port on a Cortex-M7 r0p0 or r0p1 core, define
- * configENABLE_ERRATA_837070_WORKAROUND to 1 in your
- * FreeRTOSConfig.h. */
- configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
- configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
- #endif
-
- #if ( configASSERT_DEFINED == 1 )
- {
- volatile uint32_t ulOriginalPriority;
- volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
- volatile uint8_t ucMaxPriorityValue;
-
- /* Determine the maximum priority from which ISR safe FreeRTOS API
- * functions can be called. ISR safe functions are those that end in
- * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
- * ensure interrupt entry is as fast and simple as possible.
- *
- * Save the interrupt priority value that is about to be clobbered. */
- ulOriginalPriority = *pucFirstUserPriorityRegister;
-
- /* Determine the number of priority bits available. First write to all
- * possible bits. */
- *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
-
- /* Read the value back to see how many bits stuck. */
- ucMaxPriorityValue = *pucFirstUserPriorityRegister;
-
- /* Use the same mask on the maximum system call priority. */
- ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
-
- /* Calculate the maximum acceptable priority group value for the number
- * of bits read back. */
- ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
-
- while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
- {
- ulMaxPRIGROUPValue--;
- ucMaxPriorityValue <<= ( uint8_t ) 0x01;
- }
-
- #ifdef __NVIC_PRIO_BITS
- {
- /* Check the CMSIS configuration that defines the number of
- * priority bits matches the number of priority bits actually queried
- * from the hardware. */
- configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
- }
- #endif
-
- #ifdef configPRIO_BITS
- {
- /* Check the FreeRTOS configuration that defines the number of
- * priority bits matches the number of priority bits actually queried
- * from the hardware. */
- configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
- }
- #endif
-
- /* Shift the priority group value back to its position within the AIRCR
- * register. */
- ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
- ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
- /* Restore the clobbered interrupt priority register to its original
- * value. */
- *pucFirstUserPriorityRegister = ulOriginalPriority;
- }
- #endif /* configASSERT_DEFINED */
-
- /* Make PendSV and SysTick the same priority as the kernel, and the SVC
- * handler higher priority so it can be used to exit a critical section (where
- * lower priorities are masked). */
- portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
- portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
-
- /* Configure the regions in the MPU that are common to all tasks. */
- prvSetupMPU();
-
- /* Start the timer that generates the tick ISR. Interrupts are disabled
- * here already. */
- vPortSetupTimerInterrupt();
-
- /* Initialise the critical nesting count ready for the first task. */
- uxCriticalNesting = 0;
-
- /* Ensure the VFP is enabled - it should be anyway. */
- vPortEnableVFP();
-
- /* Lazy save always. */
- *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
-
- /* Start the first task. This also clears the bit that indicates the FPU is
- * in use in case the FPU was used before the scheduler was started - which
- * would otherwise result in the unnecessary leaving of space in the SVC stack
- * for lazy saving of FPU registers. */
- __asm volatile (
- " ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */
- " ldr r0, [r0] \n"
- " ldr r0, [r0] \n"
- " msr msp, r0 \n"/* Set the msp back to the start of the stack. */
- " mov r0, #0 \n"/* Clear the bit that indicates the FPU is in use, see comment above. */
- " msr control, r0 \n"
- " cpsie i \n"/* Globally enable interrupts. */
- " cpsie f \n"
- " dsb \n"
- " isb \n"
- " svc %0 \n"/* System call to start first task. */
- " nop \n"
- " .ltorg \n"
- ::"i" ( portSVC_START_SCHEDULER ) : "memory" );
-
- /* Should not get here! */
- return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
- /* Not implemented in ports where there is nothing to return to.
- * Artificially force an assert. */
- configASSERT( uxCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
- if( portIS_PRIVILEGED() == pdFALSE )
- {
- portRAISE_PRIVILEGE();
- portMEMORY_BARRIER();
-
- portDISABLE_INTERRUPTS();
- uxCriticalNesting++;
- portMEMORY_BARRIER();
-
- portRESET_PRIVILEGE();
- portMEMORY_BARRIER();
- }
- else
- {
- portDISABLE_INTERRUPTS();
- uxCriticalNesting++;
- }
-#else
- portDISABLE_INTERRUPTS();
- uxCriticalNesting++;
-#endif
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
- if( portIS_PRIVILEGED() == pdFALSE )
- {
- portRAISE_PRIVILEGE();
- portMEMORY_BARRIER();
-
- configASSERT( uxCriticalNesting );
- uxCriticalNesting--;
-
- if( uxCriticalNesting == 0 )
- {
- portENABLE_INTERRUPTS();
- }
- portMEMORY_BARRIER();
-
- portRESET_PRIVILEGE();
- portMEMORY_BARRIER();
- }
- else
- {
- configASSERT( uxCriticalNesting );
- uxCriticalNesting--;
-
- if( uxCriticalNesting == 0 )
- {
- portENABLE_INTERRUPTS();
- }
- }
-#else
- configASSERT( uxCriticalNesting );
- uxCriticalNesting--;
-
- if( uxCriticalNesting == 0 )
- {
- portENABLE_INTERRUPTS();
- }
-#endif
-}
-/*-----------------------------------------------------------*/
-
-void xPortPendSVHandler( void )
-{
- /* This is a naked function. */
-
- __asm volatile
- (
- " mrs r0, psp \n"
- " isb \n"
- " \n"
- " ldr r3, pxCurrentTCBConst \n"/* Get the location of the current TCB. */
- " ldr r2, [r3] \n"
- " \n"
- " tst r14, #0x10 \n"/* Is the task using the FPU context? If so, push high vfp registers. */
- " it eq \n"
- " vstmdbeq r0!, {s16-s31} \n"
- " \n"
- " mrs r1, control \n"
- " stmdb r0!, {r1, r4-r11, r14} \n"/* Save the remaining registers. */
- " str r0, [r2] \n"/* Save the new top of stack into the first member of the TCB. */
- " \n"
- " stmdb sp!, {r0, r3} \n"
- " mov r0, %0 \n"
- #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
- " cpsid i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
- #endif
- " msr basepri, r0 \n"
- " dsb \n"
- " isb \n"
- #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
- " cpsie i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
- #endif
- " bl vTaskSwitchContext \n"
- " mov r0, #0 \n"
- " msr basepri, r0 \n"
- " ldmia sp!, {r0, r3} \n"
- " \n"/* Restore the context. */
- " ldr r1, [r3] \n"
- " ldr r0, [r1] \n"/* The first item in the TCB is the task top of stack. */
- " add r1, r1, #4 \n"/* Move onto the second item in the TCB... */
- " \n"
- " dmb \n"/* Complete outstanding transfers before disabling MPU. */
- " ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */
- " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */
- " bic r3, #1 \n"/* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
- " str r3, [r2] \n"/* Disable MPU. */
- " \n"
- " ldr r2, =0xe000ed9c \n"/* Region Base Address register. */
- " ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
- " stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
- " \n"
- #if ( configTOTAL_MPU_REGIONS == 16 )
- " ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
- " stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
- " ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
- " stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
- #endif /* configTOTAL_MPU_REGIONS == 16. */
- " \n"
- " ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */
- " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */
- " orr r3, #1 \n"/* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
- " str r3, [r2] \n"/* Enable MPU. */
- " dsb \n"/* Force memory writes before continuing. */
- " \n"
- " ldmia r0!, {r3-r11, r14} \n"/* Pop the registers that are not automatically saved on exception entry. */
- " msr control, r3 \n"
- " \n"
- " tst r14, #0x10 \n"/* Is the task using the FPU context? If so, pop the high vfp registers too. */
- " it eq \n"
- " vldmiaeq r0!, {s16-s31} \n"
- " \n"
- " msr psp, r0 \n"
- " bx r14 \n"
- " \n"
- " .ltorg \n"/* Assemble the current literal pool to avoid offset-out-of-bound errors with lto. */
- " .align 4 \n"
- "pxCurrentTCBConst: .word pxCurrentTCB \n"
- ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
- );
-}
-/*-----------------------------------------------------------*/
-
-void xPortSysTickHandler( void )
-{
- uint32_t ulDummy;
-
- ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
- {
- /* Increment the RTOS tick. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- /* Pend a context switch. */
- portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
- }
- }
- portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the systick timer to generate the tick interrupts at the required
- * frequency.
- */
-__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
-{
- /* Stop and clear the SysTick. */
- portNVIC_SYSTICK_CTRL_REG = 0UL;
- portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
- /* Configure SysTick to interrupt at the requested rate. */
- portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE );
-}
-/*-----------------------------------------------------------*/
-
-/* This is a naked function. */
-static void vPortEnableVFP( void )
-{
- __asm volatile
- (
- " ldr.w r0, =0xE000ED88 \n"/* The FPU enable bits are in the CPACR. */
- " ldr r1, [r0] \n"
- " \n"
- " orr r1, r1, #( 0xf << 20 ) \n"/* Enable CP10 and CP11 coprocessors, then save back. */
- " str r1, [r0] \n"
- " bx r14 \n"
- " .ltorg \n"
- );
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupMPU( void )
-{
- #if defined( __ARMCC_VERSION )
-
- /* Declaration when these variable are defined in code instead of being
- * exported from linker scripts. */
- extern uint32_t * __privileged_functions_start__;
- extern uint32_t * __privileged_functions_end__;
- extern uint32_t * __FLASH_segment_start__;
- extern uint32_t * __FLASH_segment_end__;
- extern uint32_t * __privileged_data_start__;
- extern uint32_t * __privileged_data_end__;
- #else
- /* Declaration when these variable are exported from linker scripts. */
- extern uint32_t __privileged_functions_start__[];
- extern uint32_t __privileged_functions_end__[];
- extern uint32_t __FLASH_segment_start__[];
- extern uint32_t __FLASH_segment_end__[];
- extern uint32_t __privileged_data_start__[];
- extern uint32_t __privileged_data_end__[];
- #endif /* if defined( __ARMCC_VERSION ) */
-
- /* The only permitted number of regions are 8 or 16. */
- configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
-
- /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
- configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
-
- /* Check the expected MPU is present. */
- if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
- {
- /* First setup the unprivileged flash for unprivileged read only access. */
- portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
- ( portMPU_REGION_VALID ) |
- ( portUNPRIVILEGED_FLASH_REGION );
-
- portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) |
- ( ( configTEX_S_C_B_FLASH & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
- ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
- ( portMPU_REGION_ENABLE );
-
- /* Setup the privileged flash for privileged only access. This is where
- * the kernel code is placed. */
- portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_functions_start__ ) | /* Base address. */
- ( portMPU_REGION_VALID ) |
- ( portPRIVILEGED_FLASH_REGION );
-
- portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |
- ( ( configTEX_S_C_B_FLASH & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
- ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __privileged_functions_start__ ) ) |
- ( portMPU_REGION_ENABLE );
-
- /* Setup the privileged data RAM region. This is where the kernel data
- * is placed. */
- portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
- ( portMPU_REGION_VALID ) |
- ( portPRIVILEGED_RAM_REGION );
-
- portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
- ( portMPU_REGION_EXECUTE_NEVER ) |
- ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
- prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
- ( portMPU_REGION_ENABLE );
-
- /* By default allow everything to access the general peripherals. The
- * system peripherals and registers are protected. */
- portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) |
- ( portMPU_REGION_VALID ) |
- ( portGENERAL_PERIPHERALS_REGION );
-
- portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |
- ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |
- ( portMPU_REGION_ENABLE );
-
- /* Enable the memory fault exception. */
- portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;
-
- /* Enable the MPU with the background region configured. */
- portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
- }
-}
-/*-----------------------------------------------------------*/
-
-static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
-{
- uint32_t ulRegionSize, ulReturnValue = 4;
-
- /* 32 is the smallest region size, 31 is the largest valid value for
- * ulReturnValue. */
- for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )
- {
- if( ulActualSizeInBytes <= ulRegionSize )
- {
- break;
- }
- else
- {
- ulReturnValue++;
- }
- }
-
- /* Shift the code by one before returning so it can be written directly
- * into the the correct bit position of the attribute register. */
- return( ulReturnValue << 1UL );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
-{
- __asm volatile
- (
- " mrs r0, control \n"/* r0 = CONTROL. */
- " tst r0, #1 \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
- " ite ne \n"
- " movne r0, #0 \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
- " moveq r0, #1 \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
- " bx lr \n"/* Return. */
- " \n"
- " .align 4 \n"
- ::: "r0", "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-void vResetPrivilege( void ) /* __attribute__ (( naked )) */
-{
- __asm volatile
- (
- " mrs r0, control \n"/* r0 = CONTROL. */
- " orr r0, #1 \n"/* r0 = r0 | 1. */
- " msr control, r0 \n"/* CONTROL = r0. */
- " bx lr \n"/* Return to the caller. */
- ::: "r0", "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
- const struct xMEMORY_REGION * const xRegions,
- StackType_t * pxBottomOfStack,
- uint32_t ulStackDepth )
-{
- #if defined( __ARMCC_VERSION )
-
- /* Declaration when these variable are defined in code instead of being
- * exported from linker scripts. */
- extern uint32_t * __SRAM_segment_start__;
- extern uint32_t * __SRAM_segment_end__;
- extern uint32_t * __privileged_data_start__;
- extern uint32_t * __privileged_data_end__;
- #else
- /* Declaration when these variable are exported from linker scripts. */
- extern uint32_t __SRAM_segment_start__[];
- extern uint32_t __SRAM_segment_end__[];
- extern uint32_t __privileged_data_start__[];
- extern uint32_t __privileged_data_end__[];
- #endif /* if defined( __ARMCC_VERSION ) */
-
- int32_t lIndex;
- uint32_t ul;
-
- if( xRegions == NULL )
- {
- /* No MPU regions are specified so allow access to all RAM. */
- xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
- ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
- ( portMPU_REGION_VALID ) |
- ( portSTACK_REGION ); /* Region number. */
-
- xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
- ( portMPU_REGION_READ_WRITE ) |
- ( portMPU_REGION_EXECUTE_NEVER ) |
- ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
- ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
- ( portMPU_REGION_ENABLE );
-
- /* Invalidate user configurable regions. */
- for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
- {
- xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );
- xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
- }
- }
- else
- {
- /* This function is called automatically when the task is created - in
- * which case the stack region parameters will be valid. At all other
- * times the stack parameters will not be valid and it is assumed that the
- * stack region has already been configured. */
- if( ulStackDepth > 0 )
- {
- /* Define the region that allows access to the stack. */
- xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
- ( ( uint32_t ) pxBottomOfStack ) |
- ( portMPU_REGION_VALID ) |
- ( portSTACK_REGION ); /* Region number. */
-
- xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
- ( portMPU_REGION_READ_WRITE ) |
- ( portMPU_REGION_EXECUTE_NEVER ) |
- ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
- ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
- ( portMPU_REGION_ENABLE );
- }
-
- lIndex = 0;
-
- for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
- {
- if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
- {
- /* Translate the generic region definition contained in
- * xRegions into the CM4 specific MPU settings that are then
- * stored in xMPUSettings. */
- xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
- ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
- ( portMPU_REGION_VALID ) |
- ( ul - 1UL ); /* Region number. */
-
- xMPUSettings->xRegion[ ul ].ulRegionAttribute =
- ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
- ( xRegions[ lIndex ].ulParameters ) |
- ( portMPU_REGION_ENABLE );
- }
- else
- {
- /* Invalidate the region. */
- xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );
- xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
- }
-
- lIndex++;
- }
- }
-}
-/*-----------------------------------------------------------*/
-
-#if ( configASSERT_DEFINED == 1 )
-
- void vPortValidateInterruptPriority( void )
- {
- uint32_t ulCurrentInterrupt;
- uint8_t ucCurrentPriority;
-
- /* Obtain the number of the currently executing interrupt. */
- __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
-
- /* Is the interrupt number a user defined interrupt? */
- if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
- {
- /* Look up the interrupt's priority. */
- ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
-
- /* The following assertion will fail if a service routine (ISR) for
- * an interrupt that has been assigned a priority above
- * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
- * function. ISR safe FreeRTOS API functions must *only* be called
- * from interrupts that have been assigned a priority at or below
- * configMAX_SYSCALL_INTERRUPT_PRIORITY.
- *
- * Numerically low interrupt priority numbers represent logically high
- * interrupt priorities, therefore the priority of the interrupt must
- * be set to a value equal to or numerically *higher* than
- * configMAX_SYSCALL_INTERRUPT_PRIORITY.
- *
- * Interrupts that use the FreeRTOS API must not be left at their
- * default priority of zero as that is the highest possible priority,
- * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
- * and therefore also guaranteed to be invalid.
- *
- * FreeRTOS maintains separate thread and ISR API functions to ensure
- * interrupt entry is as fast and simple as possible.
- *
- * The following links provide detailed information:
- * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
- * https://www.FreeRTOS.org/FAQHelp.html */
- configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
- }
-
- /* Priority grouping: The interrupt controller (NVIC) allows the bits
- * that define each interrupt's priority to be split between bits that
- * define the interrupt's pre-emption priority bits and bits that define
- * the interrupt's sub-priority. For simplicity all bits must be defined
- * to be pre-emption priority bits. The following assertion will fail if
- * this is not the case (if some bits represent a sub-priority).
- *
- * If the application only uses CMSIS libraries for interrupt
- * configuration then the correct setting can be achieved on all Cortex-M
- * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
- * scheduler. Note however that some vendor specific peripheral libraries
- * assume a non-zero priority group setting, in which cases using a value
- * of zero will result in unpredicable behaviour. */
- configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
- }
-
-#endif /* configASSERT_DEFINED */
-/*-----------------------------------------------------------*/
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*-----------------------------------------------------------
+* Implementation of functions defined in portable.h for the ARM CM4 MPU port.
+*----------------------------------------------------------*/
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef __VFP_FP__
+ #error This port can only be used when the project options are configured to enable hardware floating point support.
+#endif
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#ifndef configSYSTICK_CLOCK_HZ
+ #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
+ /* Ensure the SysTick is clocked at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK ( 1UL << 2UL )
+#else
+
+/* The way the SysTick is clocked is not modified in case it is not the same
+ * as the core. */
+ #define portNVIC_SYSTICK_CLK ( 0 )
+#endif
+
+#ifndef configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS
+ #warning "configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS is not defined. We recommend defining it to 0 in FreeRTOSConfig.h for better security."
+ #define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS 1
+#endif
+
+/* Constants required to access and manipulate the NVIC. */
+#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
+#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) )
+#define portNVIC_SYS_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
+#define portNVIC_MEM_FAULT_ENABLE ( 1UL << 16UL )
+
+/* Constants used to detect Cortex-M7 r0p0 and r0p1 cores, and ensure
+ * that a work around is active for errata 837070. */
+#define portCPUID ( *( ( volatile uint32_t * ) 0xE000ed00 ) )
+#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )
+#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )
+
+/* Constants required to access and manipulate the MPU. */
+#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_REGION_BASE_ADDRESS_REG ( *( ( volatile uint32_t * ) 0xe000ed9C ) )
+#define portMPU_REGION_ATTRIBUTE_REG ( *( ( volatile uint32_t * ) 0xe000edA0 ) )
+#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
+#define portMPU_ENABLE ( 0x01UL )
+#define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL )
+#define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL )
+#define portMPU_REGION_VALID ( 0x10UL )
+#define portMPU_REGION_ENABLE ( 0x01UL )
+#define portPERIPHERALS_START_ADDRESS 0x40000000UL
+#define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL
+
+/* Constants required to access and manipulate the SysTick. */
+#define portNVIC_SYSTICK_INT ( 0x00000002UL )
+#define portNVIC_SYSTICK_ENABLE ( 0x00000001UL )
+#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+#define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
+
+/* Constants required to manipulate the VFP. */
+#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34UL ) /* Floating point context control register. */
+#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR ( 0x01000000UL )
+#define portINITIAL_EXC_RETURN ( 0xfffffffdUL )
+#define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 )
+#define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
+#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT ( 8UL )
+
+/* Offsets in the stack to the parameters when inside the SVC handler. */
+#define portOFFSET_TO_PC ( 6 )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+ * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
+
+/*
+ * Configure a number of standard MPU regions that are used by all tasks.
+ */
+static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Return the smallest MPU region size that a given number of bytes will fit
+ * into. The region size is returned as the value that should be programmed
+ * into the region attribute register for that region.
+ */
+static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
+
+/*
+ * Setup the timer to generate the tick interrupts. The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Standard FreeRTOS exception handlers.
+ */
+void xPortPendSVHandler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+void xPortSysTickHandler( void ) PRIVILEGED_FUNCTION;
+void vPortSVCHandler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/*
+ * Starts the scheduler by restoring the context of the first task to run.
+ */
+static void prvRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/*
+ * C portion of the SVC handler. The SVC handler is split between an asm entry
+ * and a C wrapper for simplicity of coding and maintenance.
+ */
+static void prvSVCHandler( uint32_t * pulRegisters ) __attribute__( ( noinline ) ) PRIVILEGED_FUNCTION;
+
+/*
+ * Function to enable the VFP.
+ */
+static void vPortEnableVFP( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Enter critical section.
+ */
+#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
+ void vPortEnterCritical( void ) FREERTOS_SYSTEM_CALL;
+#else
+ void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * @brief Exit from critical section.
+ */
+#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
+ void vPortExitCritical( void ) FREERTOS_SYSTEM_CALL;
+#else
+ void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
+#endif
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+ * variable. Note this is not saved as part of the task context as context
+ * switches can only occur when uxCriticalNesting is zero. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( configASSERT_DEFINED == 1 )
+ static uint8_t ucMaxSysCallPriority = 0;
+ static uint32_t ulMaxPRIGROUPValue = 0;
+ static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+ TaskFunction_t pxCode,
+ void * pvParameters,
+ BaseType_t xRunPrivileged )
+{
+ /* Simulate the stack frame as it would be created by a context switch
+ * interrupt. */
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
+ pxTopOfStack--;
+ *pxTopOfStack = 0; /* LR */
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+
+ /* A save method is being used that requires each task to maintain its
+ * own exec return value. */
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_EXC_RETURN;
+
+ pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+ if( xRunPrivileged == pdTRUE )
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;
+ }
+ else
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;
+ }
+
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler( void )
+{
+ /* Assumes psp was in use. */
+ __asm volatile
+ (
+ #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */
+ " tst lr, #4 \n"
+ " ite eq \n"
+ " mrseq r0, msp \n"
+ " mrsne r0, psp \n"
+ #else
+ " mrs r0, psp \n"
+ #endif
+ " b %0 \n"
+ ::"i" ( prvSVCHandler ) : "r0", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+static void prvSVCHandler( uint32_t * pulParam )
+{
+ uint8_t ucSVCNumber;
+ uint32_t ulPC;
+
+ #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
+ #if defined( __ARMCC_VERSION )
+
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __syscalls_flash_start__;
+ extern uint32_t * __syscalls_flash_end__;
+ #else
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __syscalls_flash_start__[];
+ extern uint32_t __syscalls_flash_end__[];
+ #endif /* #if defined( __ARMCC_VERSION ) */
+ #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
+
+ /* The stack contains: r0, r1, r2, r3, r12, LR, PC and xPSR. The first
+ * argument (r0) is pulParam[ 0 ]. */
+ ulPC = pulParam[ portOFFSET_TO_PC ];
+ ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
+
+ switch( ucSVCNumber )
+ {
+ case portSVC_START_SCHEDULER:
+ portNVIC_SHPR2_REG |= portNVIC_SVC_PRI;
+ prvRestoreContextOfFirstTask();
+ break;
+
+ case portSVC_YIELD:
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+
+ /* Barriers are normally not required
+ * but do ensure the code is completely
+ * within the specified behaviour for the
+ * architecture. */
+ __asm volatile ( "dsb" ::: "memory" );
+ __asm volatile ( "isb" );
+
+ break;
+
+ #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
+ case portSVC_RAISE_PRIVILEGE: /* Only raise the privilege, if the
+ * svc was raised from any of the
+ * system calls. */
+
+ if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+ ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+ {
+ __asm volatile
+ (
+ " mrs r1, control \n"/* Obtain current control value. */
+ " bic r1, #1 \n"/* Set privilege bit. */
+ " msr control, r1 \n"/* Write back new control value. */
+ ::: "r1", "memory"
+ );
+ }
+
+ break;
+ #else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
+ case portSVC_RAISE_PRIVILEGE:
+ __asm volatile
+ (
+ " mrs r1, control \n"/* Obtain current control value. */
+ " bic r1, #1 \n"/* Set privilege bit. */
+ " msr control, r1 \n"/* Write back new control value. */
+ ::: "r1", "memory"
+ );
+ break;
+ #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
+
+ default: /* Unknown SVC call. */
+ break;
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void prvRestoreContextOfFirstTask( void )
+{
+ __asm volatile
+ (
+ " ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */
+ " ldr r0, [r0] \n"
+ " ldr r0, [r0] \n"
+ " msr msp, r0 \n"/* Set the msp back to the start of the stack. */
+ " ldr r3, pxCurrentTCBConst2 \n"/* Restore the context. */
+ " ldr r1, [r3] \n"
+ " ldr r0, [r1] \n"/* The first item in the TCB is the task top of stack. */
+ " add r1, r1, #4 \n"/* Move onto the second item in the TCB... */
+ " \n"
+ " dmb \n"/* Complete outstanding transfers before disabling MPU. */
+ " ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */
+ " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */
+ " bic r3, #1 \n"/* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
+ " str r3, [r2] \n"/* Disable MPU. */
+ " \n"
+ " ldr r2, =0xe000ed9c \n"/* Region Base Address register. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
+ " stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
+ " \n"
+ #if ( configTOTAL_MPU_REGIONS == 16 )
+ " ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
+ " stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
+ " stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
+ #endif /* configTOTAL_MPU_REGIONS == 16. */
+ " \n"
+ " ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */
+ " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */
+ " orr r3, #1 \n"/* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
+ " str r3, [r2] \n"/* Enable MPU. */
+ " dsb \n"/* Force memory writes before continuing. */
+ " \n"
+ " ldmia r0!, {r3-r11, r14} \n"/* Pop the registers that are not automatically saved on exception entry. */
+ " msr control, r3 \n"
+ " msr psp, r0 \n"/* Restore the task stack pointer. */
+ " mov r0, #0 \n"
+ " msr basepri, r0 \n"
+ " bx r14 \n"
+ " \n"
+ " .ltorg \n"/* Assemble current literal pool to avoid offset-out-of-bound errors with lto. */
+ " .align 4 \n"
+ "pxCurrentTCBConst2: .word pxCurrentTCB \n"
+ );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+ /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See
+ * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
+
+ /* Errata 837070 workaround must only be enabled on Cortex-M7 r0p0
+ * and r0p1 cores. */
+ #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
+ configASSERT( ( portCPUID == portCORTEX_M7_r0p1_ID ) || ( portCPUID == portCORTEX_M7_r0p0_ID ) );
+ #else
+ /* When using this port on a Cortex-M7 r0p0 or r0p1 core, define
+ * configENABLE_ERRATA_837070_WORKAROUND to 1 in your
+ * FreeRTOSConfig.h. */
+ configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
+ configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
+ #endif
+
+ #if ( configASSERT_DEFINED == 1 )
+ {
+ volatile uint32_t ulOriginalPriority;
+ volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine the maximum priority from which ISR safe FreeRTOS API
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * ensure interrupt entry is as fast and simple as possible.
+ *
+ * Save the interrupt priority value that is about to be clobbered. */
+ ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+ /* Determine the number of priority bits available. First write to all
+ * possible bits. */
+ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+ /* Use the same mask on the maximum system call priority. */
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+ /* Calculate the maximum acceptable priority group value for the number
+ * of bits read back. */
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+ {
+ ulMaxPRIGROUPValue--;
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+ }
+
+ #ifdef __NVIC_PRIO_BITS
+ {
+ /* Check the CMSIS configuration that defines the number of
+ * priority bits matches the number of priority bits actually queried
+ * from the hardware. */
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+ }
+ #endif
+
+ #ifdef configPRIO_BITS
+ {
+ /* Check the FreeRTOS configuration that defines the number of
+ * priority bits matches the number of priority bits actually queried
+ * from the hardware. */
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+ }
+ #endif
+
+ /* Shift the priority group value back to its position within the AIRCR
+ * register. */
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+ /* Restore the clobbered interrupt priority register to its original
+ * value. */
+ *pucFirstUserPriorityRegister = ulOriginalPriority;
+ }
+ #endif /* configASSERT_DEFINED */
+
+ /* Make PendSV and SysTick the same priority as the kernel, and the SVC
+ * handler higher priority so it can be used to exit a critical section (where
+ * lower priorities are masked). */
+ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
+ portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+
+ /* Configure the regions in the MPU that are common to all tasks. */
+ prvSetupMPU();
+
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ * here already. */
+ vPortSetupTimerInterrupt();
+
+ /* Initialise the critical nesting count ready for the first task. */
+ uxCriticalNesting = 0;
+
+ /* Ensure the VFP is enabled - it should be anyway. */
+ vPortEnableVFP();
+
+ /* Lazy save always. */
+ *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
+
+ /* Start the first task. This also clears the bit that indicates the FPU is
+ * in use in case the FPU was used before the scheduler was started - which
+ * would otherwise result in the unnecessary leaving of space in the SVC stack
+ * for lazy saving of FPU registers. */
+ __asm volatile (
+ " ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */
+ " ldr r0, [r0] \n"
+ " ldr r0, [r0] \n"
+ " msr msp, r0 \n"/* Set the msp back to the start of the stack. */
+ " mov r0, #0 \n"/* Clear the bit that indicates the FPU is in use, see comment above. */
+ " msr control, r0 \n"
+ " cpsie i \n"/* Globally enable interrupts. */
+ " cpsie f \n"
+ " dsb \n"
+ " isb \n"
+ " svc %0 \n"/* System call to start first task. */
+ " nop \n"
+ " .ltorg \n"
+ ::"i" ( portSVC_START_SCHEDULER ) : "memory" );
+
+ /* Should not get here! */
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+ /* Not implemented in ports where there is nothing to return to.
+ * Artificially force an assert. */
+ configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ portDISABLE_INTERRUPTS();
+ uxCriticalNesting++;
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ portDISABLE_INTERRUPTS();
+ uxCriticalNesting++;
+ }
+#else
+ portDISABLE_INTERRUPTS();
+ uxCriticalNesting++;
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ configASSERT( uxCriticalNesting );
+ uxCriticalNesting--;
+
+ if( uxCriticalNesting == 0 )
+ {
+ portENABLE_INTERRUPTS();
+ }
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ configASSERT( uxCriticalNesting );
+ uxCriticalNesting--;
+
+ if( uxCriticalNesting == 0 )
+ {
+ portENABLE_INTERRUPTS();
+ }
+ }
+#else
+ configASSERT( uxCriticalNesting );
+ uxCriticalNesting--;
+
+ if( uxCriticalNesting == 0 )
+ {
+ portENABLE_INTERRUPTS();
+ }
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void xPortPendSVHandler( void )
+{
+ /* This is a naked function. */
+
+ __asm volatile
+ (
+ " mrs r0, psp \n"
+ " isb \n"
+ " \n"
+ " ldr r3, pxCurrentTCBConst \n"/* Get the location of the current TCB. */
+ " ldr r2, [r3] \n"
+ " \n"
+ " tst r14, #0x10 \n"/* Is the task using the FPU context? If so, push high vfp registers. */
+ " it eq \n"
+ " vstmdbeq r0!, {s16-s31} \n"
+ " \n"
+ " mrs r1, control \n"
+ " stmdb r0!, {r1, r4-r11, r14} \n"/* Save the remaining registers. */
+ " str r0, [r2] \n"/* Save the new top of stack into the first member of the TCB. */
+ " \n"
+ " stmdb sp!, {r0, r3} \n"
+ " mov r0, %0 \n"
+ #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
+ " cpsid i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
+ #endif
+ " msr basepri, r0 \n"
+ " dsb \n"
+ " isb \n"
+ #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
+ " cpsie i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
+ #endif
+ " bl vTaskSwitchContext \n"
+ " mov r0, #0 \n"
+ " msr basepri, r0 \n"
+ " ldmia sp!, {r0, r3} \n"
+ " \n"/* Restore the context. */
+ " ldr r1, [r3] \n"
+ " ldr r0, [r1] \n"/* The first item in the TCB is the task top of stack. */
+ " add r1, r1, #4 \n"/* Move onto the second item in the TCB... */
+ " \n"
+ " dmb \n"/* Complete outstanding transfers before disabling MPU. */
+ " ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */
+ " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */
+ " bic r3, #1 \n"/* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
+ " str r3, [r2] \n"/* Disable MPU. */
+ " \n"
+ " ldr r2, =0xe000ed9c \n"/* Region Base Address register. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
+ " stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
+ " \n"
+ #if ( configTOTAL_MPU_REGIONS == 16 )
+ " ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
+ " stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
+ " stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
+ #endif /* configTOTAL_MPU_REGIONS == 16. */
+ " \n"
+ " ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */
+ " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */
+ " orr r3, #1 \n"/* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
+ " str r3, [r2] \n"/* Enable MPU. */
+ " dsb \n"/* Force memory writes before continuing. */
+ " \n"
+ " ldmia r0!, {r3-r11, r14} \n"/* Pop the registers that are not automatically saved on exception entry. */
+ " msr control, r3 \n"
+ " \n"
+ " tst r14, #0x10 \n"/* Is the task using the FPU context? If so, pop the high vfp registers too. */
+ " it eq \n"
+ " vldmiaeq r0!, {s16-s31} \n"
+ " \n"
+ " msr psp, r0 \n"
+ " bx r14 \n"
+ " \n"
+ " .ltorg \n"/* Assemble the current literal pool to avoid offset-out-of-bound errors with lto. */
+ " .align 4 \n"
+ "pxCurrentTCBConst: .word pxCurrentTCB \n"
+ ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+ );
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+ uint32_t ulDummy;
+
+ ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
+ {
+ /* Increment the RTOS tick. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ /* Pend a context switch. */
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+ }
+ }
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
+{
+ /* Stop and clear the SysTick. */
+ portNVIC_SYSTICK_CTRL_REG = 0UL;
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+ /* Configure SysTick to interrupt at the requested rate. */
+ portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE );
+}
+/*-----------------------------------------------------------*/
+
+/* This is a naked function. */
+static void vPortEnableVFP( void )
+{
+ __asm volatile
+ (
+ " ldr.w r0, =0xE000ED88 \n"/* The FPU enable bits are in the CPACR. */
+ " ldr r1, [r0] \n"
+ " \n"
+ " orr r1, r1, #( 0xf << 20 ) \n"/* Enable CP10 and CP11 coprocessors, then save back. */
+ " str r1, [r0] \n"
+ " bx r14 \n"
+ " .ltorg \n"
+ );
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupMPU( void )
+{
+ #if defined( __ARMCC_VERSION )
+
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __privileged_functions_start__;
+ extern uint32_t * __privileged_functions_end__;
+ extern uint32_t * __FLASH_segment_start__;
+ extern uint32_t * __FLASH_segment_end__;
+ extern uint32_t * __privileged_data_start__;
+ extern uint32_t * __privileged_data_end__;
+ #else
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __privileged_functions_start__[];
+ extern uint32_t __privileged_functions_end__[];
+ extern uint32_t __FLASH_segment_start__[];
+ extern uint32_t __FLASH_segment_end__[];
+ extern uint32_t __privileged_data_start__[];
+ extern uint32_t __privileged_data_end__[];
+ #endif /* if defined( __ARMCC_VERSION ) */
+
+ /* The only permitted number of regions are 8 or 16. */
+ configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
+
+ /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
+ configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
+
+ /* Check the expected MPU is present. */
+ if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+ {
+ /* First setup the unprivileged flash for unprivileged read only access. */
+ portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
+ ( portMPU_REGION_VALID ) |
+ ( portUNPRIVILEGED_FLASH_REGION );
+
+ portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) |
+ ( ( configTEX_S_C_B_FLASH & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
+ ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
+ ( portMPU_REGION_ENABLE );
+
+ /* Setup the privileged flash for privileged only access. This is where
+ * the kernel code is placed. */
+ portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_functions_start__ ) | /* Base address. */
+ ( portMPU_REGION_VALID ) |
+ ( portPRIVILEGED_FLASH_REGION );
+
+ portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |
+ ( ( configTEX_S_C_B_FLASH & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
+ ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __privileged_functions_start__ ) ) |
+ ( portMPU_REGION_ENABLE );
+
+ /* Setup the privileged data RAM region. This is where the kernel data
+ * is placed. */
+ portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
+ ( portMPU_REGION_VALID ) |
+ ( portPRIVILEGED_RAM_REGION );
+
+ portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+ ( portMPU_REGION_EXECUTE_NEVER ) |
+ ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
+ prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
+ ( portMPU_REGION_ENABLE );
+
+ /* By default allow everything to access the general peripherals. The
+ * system peripherals and registers are protected. */
+ portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) |
+ ( portMPU_REGION_VALID ) |
+ ( portGENERAL_PERIPHERALS_REGION );
+
+ portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |
+ ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |
+ ( portMPU_REGION_ENABLE );
+
+ /* Enable the memory fault exception. */
+ portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;
+
+ /* Enable the MPU with the background region configured. */
+ portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
+ }
+}
+/*-----------------------------------------------------------*/
+
+static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
+{
+ uint32_t ulRegionSize, ulReturnValue = 4;
+
+ /* 32 is the smallest region size, 31 is the largest valid value for
+ * ulReturnValue. */
+ for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )
+ {
+ if( ulActualSizeInBytes <= ulRegionSize )
+ {
+ break;
+ }
+ else
+ {
+ ulReturnValue++;
+ }
+ }
+
+ /* Shift the code by one before returning so it can be written directly
+ * into the the correct bit position of the attribute register. */
+ return( ulReturnValue << 1UL );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+ __asm volatile
+ (
+ " mrs r0, control \n"/* r0 = CONTROL. */
+ " tst r0, #1 \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+ " ite ne \n"
+ " movne r0, #0 \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+ " moveq r0, #1 \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+ " bx lr \n"/* Return. */
+ " \n"
+ " .align 4 \n"
+ ::: "r0", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+ __asm volatile
+ (
+ " mrs r0, control \n"/* r0 = CONTROL. */
+ " orr r0, #1 \n"/* r0 = r0 | 1. */
+ " msr control, r0 \n"/* CONTROL = r0. */
+ " bx lr \n"/* Return to the caller. */
+ ::: "r0", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
+ const struct xMEMORY_REGION * const xRegions,
+ StackType_t * pxBottomOfStack,
+ uint32_t ulStackDepth )
+{
+ #if defined( __ARMCC_VERSION )
+
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __SRAM_segment_start__;
+ extern uint32_t * __SRAM_segment_end__;
+ extern uint32_t * __privileged_data_start__;
+ extern uint32_t * __privileged_data_end__;
+ #else
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __SRAM_segment_start__[];
+ extern uint32_t __SRAM_segment_end__[];
+ extern uint32_t __privileged_data_start__[];
+ extern uint32_t __privileged_data_end__[];
+ #endif /* if defined( __ARMCC_VERSION ) */
+
+ int32_t lIndex;
+ uint32_t ul;
+
+ if( xRegions == NULL )
+ {
+ /* No MPU regions are specified so allow access to all RAM. */
+ xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
+ ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
+ ( portMPU_REGION_VALID ) |
+ ( portSTACK_REGION ); /* Region number. */
+
+ xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
+ ( portMPU_REGION_READ_WRITE ) |
+ ( portMPU_REGION_EXECUTE_NEVER ) |
+ ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
+ ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
+ ( portMPU_REGION_ENABLE );
+
+ /* Invalidate user configurable regions. */
+ for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
+ {
+ xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );
+ xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
+ }
+ }
+ else
+ {
+ /* This function is called automatically when the task is created - in
+ * which case the stack region parameters will be valid. At all other
+ * times the stack parameters will not be valid and it is assumed that the
+ * stack region has already been configured. */
+ if( ulStackDepth > 0 )
+ {
+ /* Define the region that allows access to the stack. */
+ xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
+ ( ( uint32_t ) pxBottomOfStack ) |
+ ( portMPU_REGION_VALID ) |
+ ( portSTACK_REGION ); /* Region number. */
+
+ xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
+ ( portMPU_REGION_READ_WRITE ) |
+ ( portMPU_REGION_EXECUTE_NEVER ) |
+ ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
+ ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
+ ( portMPU_REGION_ENABLE );
+ }
+
+ lIndex = 0;
+
+ for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
+ {
+ if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
+ {
+ /* Translate the generic region definition contained in
+ * xRegions into the CM4 specific MPU settings that are then
+ * stored in xMPUSettings. */
+ xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
+ ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
+ ( portMPU_REGION_VALID ) |
+ ( ul - 1UL ); /* Region number. */
+
+ xMPUSettings->xRegion[ ul ].ulRegionAttribute =
+ ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
+ ( xRegions[ lIndex ].ulParameters ) |
+ ( portMPU_REGION_ENABLE );
+ }
+ else
+ {
+ /* Invalidate the region. */
+ xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );
+ xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
+ }
+
+ lIndex++;
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+#if ( configASSERT_DEFINED == 1 )
+
+ void vPortValidateInterruptPriority( void )
+ {
+ uint32_t ulCurrentInterrupt;
+ uint8_t ucCurrentPriority;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ /* Is the interrupt number a user defined interrupt? */
+ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+ {
+ /* Look up the interrupt's priority. */
+ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+ /* The following assertion will fail if a service routine (ISR) for
+ * an interrupt that has been assigned a priority above
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+ * function. ISR safe FreeRTOS API functions must *only* be called
+ * from interrupts that have been assigned a priority at or below
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Numerically low interrupt priority numbers represent logically high
+ * interrupt priorities, therefore the priority of the interrupt must
+ * be set to a value equal to or numerically *higher* than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Interrupts that use the FreeRTOS API must not be left at their
+ * default priority of zero as that is the highest possible priority,
+ * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+ * and therefore also guaranteed to be invalid.
+ *
+ * FreeRTOS maintains separate thread and ISR API functions to ensure
+ * interrupt entry is as fast and simple as possible.
+ *
+ * The following links provide detailed information:
+ * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+ * https://www.FreeRTOS.org/FAQHelp.html */
+ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+ }
+
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits
+ * that define each interrupt's priority to be split between bits that
+ * define the interrupt's pre-emption priority bits and bits that define
+ * the interrupt's sub-priority. For simplicity all bits must be defined
+ * to be pre-emption priority bits. The following assertion will fail if
+ * this is not the case (if some bits represent a sub-priority).
+ *
+ * If the application only uses CMSIS libraries for interrupt
+ * configuration then the correct setting can be achieved on all Cortex-M
+ * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+ * scheduler. Note however that some vendor specific peripheral libraries
+ * assume a non-zero priority group setting, in which cases using a value
+ * of zero will result in unpredicable behaviour. */
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+ }
+
+#endif /* configASSERT_DEFINED */
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM4_MPU/portmacro.h b/portable/GCC/ARM_CM4_MPU/portmacro.h
index 31d198d..4620758 100644
--- a/portable/GCC/ARM_CM4_MPU/portmacro.h
+++ b/portable/GCC/ARM_CM4_MPU/portmacro.h
@@ -1,414 +1,414 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
- extern "C" {
-#endif
-/* *INDENT-ON* */
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT short
-#define portSTACK_TYPE uint32_t
-#define portBASE_TYPE long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
-#else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
-#endif
-
-/*-----------------------------------------------------------*/
-
-/* MPU specific constants. */
-#define portUSING_MPU_WRAPPERS 1
-#define portPRIVILEGE_BIT ( 0x80000000UL )
-
-#define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL )
-#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL )
-#define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL )
-#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL )
-#define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ( 0x02UL << 24UL )
-#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL )
-#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL )
-
-/* Location of the TEX,S,C,B bits in the MPU Region Attribute and Size
- * Register (RASR). */
-#define portMPU_RASR_TEX_S_C_B_LOCATION ( 16UL )
-#define portMPU_RASR_TEX_S_C_B_MASK ( 0x3FUL )
-
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
-#ifndef configTOTAL_MPU_REGIONS
- /* Define to 8 for backward compatibility. */
- #define configTOTAL_MPU_REGIONS ( 8UL )
-#endif
-
-/*
- * The TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits define the
- * memory type, and where necessary the cacheable and shareable properties
- * of the memory region.
- *
- * The TEX, C, and B bits together indicate the memory type of the region,
- * and:
- * - For Normal memory, the cacheable properties of the region.
- * - For Device memory, whether the region is shareable.
- *
- * For Normal memory regions, the S bit indicates whether the region is
- * shareable. For Strongly-ordered and Device memory, the S bit is ignored.
- *
- * See the following two tables for setting TEX, S, C and B bits for
- * unprivileged flash, privileged flash and privileged RAM regions.
- *
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | TEX | C | B | Memory type | Description or Normal region cacheability | Shareable? |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 000 | 0 | 0 | Strongly-ordered | Strongly ordered | Shareable |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 000 | 0 | 1 | Device | Shared device | Shareable |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 000 | 1 | 0 | Normal | Outer and inner write-through; no write allocate | S bit |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 000 | 1 | 1 | Normal | Outer and inner write-back; no write allocate | S bit |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 001 | 0 | 0 | Normal | Outer and inner Non-cacheable | S bit |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 001 | 0 | 1 | Reserved | Reserved | Reserved |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 001 | 1 | 0 | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 001 | 1 | 1 | Normal | Outer and inner write-back; write and read allocate | S bit |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 010 | 0 | 0 | Device | Non-shared device | Not shareable |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 010 | 0 | 1 | Reserved | Reserved | Reserved |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 010 | 1 | X | Reserved | Reserved | Reserved |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 011 | X | X | Reserved | Reserved | Reserved |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 1BB | A | A | Normal | Cached memory, with AA and BB indicating the inner and | Reserved |
- | | | | | outer cacheability rules that must be exported on the | |
- | | | | | bus. See the table below for the cacheability policy | |
- | | | | | encoding. memory, BB=Outer policy, AA=Inner policy. | |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- |
- +-----------------------------------------+----------------------------------------+
- | AA or BB subfield of {TEX,C,B} encoding | Cacheability policy |
- +-----------------------------------------+----------------------------------------+
- | 00 | Non-cacheable |
- +-----------------------------------------+----------------------------------------+
- | 01 | Write-back, write and read allocate |
- +-----------------------------------------+----------------------------------------+
- | 10 | Write-through, no write allocate |
- +-----------------------------------------+----------------------------------------+
- | 11 | Write-back, no write allocate |
- +-----------------------------------------+----------------------------------------+
- */
-
-/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for flash
- * region. */
-#ifndef configTEX_S_C_B_FLASH
- /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
- #define configTEX_S_C_B_FLASH ( 0x07UL )
-#endif
-
-/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for RAM
- * region. */
-#ifndef configTEX_S_C_B_SRAM
- /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
- #define configTEX_S_C_B_SRAM ( 0x07UL )
-#endif
-
-#define portGENERAL_PERIPHERALS_REGION ( configTOTAL_MPU_REGIONS - 5UL )
-#define portSTACK_REGION ( configTOTAL_MPU_REGIONS - 4UL )
-#define portUNPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 3UL )
-#define portPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 2UL )
-#define portPRIVILEGED_RAM_REGION ( configTOTAL_MPU_REGIONS - 1UL )
-#define portFIRST_CONFIGURABLE_REGION ( 0UL )
-#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 6UL )
-#define portNUM_CONFIGURABLE_REGIONS ( configTOTAL_MPU_REGIONS - 5UL )
-#define portTOTAL_NUM_REGIONS_IN_TCB ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus 1 to create space for the stack region. */
-
-#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" )
-
-typedef struct MPU_REGION_REGISTERS
-{
- uint32_t ulRegionBaseAddress;
- uint32_t ulRegionAttribute;
-} xMPU_REGION_REGISTERS;
-
-typedef struct MPU_SETTINGS
-{
- xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS_IN_TCB ];
-} xMPU_SETTINGS;
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH ( -1 )
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT 8
-#define portDONT_DISCARD __attribute__( ( used ) )
-/*-----------------------------------------------------------*/
-
-/* SVC numbers for various services. */
-#define portSVC_START_SCHEDULER 0
-#define portSVC_YIELD 1
-#define portSVC_RAISE_PRIVILEGE 2
-
-/* Scheduler utilities. */
-
-#define portYIELD() __asm volatile ( " SVC %0 \n"::"i" ( portSVC_YIELD ) : "memory" )
-#define portYIELD_WITHIN_API() \
- { \
- /* Set a PendSV to request a context switch. */ \
- portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
- \
- /* Barriers are normally not required but do ensure the code is completely \
- * within the specified behaviour for the architecture. */ \
- __asm volatile ( "dsb" ::: "memory" ); \
- __asm volatile ( "isb" ); \
- }
-
-#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/* Critical section management. */
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x )
-#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
-#define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )
-#define portENTER_CRITICAL() vPortEnterCritical()
-#define portEXIT_CRITICAL() vPortExitCritical()
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. These are
- * not necessary for to use this port. They are defined so the common demo files
- * (which build with all the ports) will build. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
-/*-----------------------------------------------------------*/
-
-/* Architecture specific optimisations. */
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-#endif
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
-/* Generic helper function. */
- __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
- {
- uint8_t ucReturn;
-
- __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
-
- return ucReturn;
- }
-
-/* Check the configuration. */
- #if ( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
-
-/* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-/*-----------------------------------------------------------*/
-
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
-
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-/*-----------------------------------------------------------*/
-
-#ifdef configASSERT
- void vPortValidateInterruptPriority( void );
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
-#endif
-
-/* portNOP() is not required by this port. */
-#define portNOP()
-
-#define portINLINE __inline
-
-#ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
-#endif
-/*-----------------------------------------------------------*/
-
-extern BaseType_t xIsPrivileged( void );
-extern void vResetPrivilege( void );
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
-#define portIS_PRIVILEGED() xIsPrivileged()
-
-/**
- * @brief Raise an SVC request to raise privilege.
- */
-#define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- */
-#define portRESET_PRIVILEGE() vResetPrivilege()
-/*-----------------------------------------------------------*/
-
-portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
-{
- uint32_t ulCurrentInterrupt;
- BaseType_t xReturn;
-
- /* Obtain the number of the currently executing interrupt. */
- __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
-
- if( ulCurrentInterrupt == 0 )
- {
- xReturn = pdFALSE;
- }
- else
- {
- xReturn = pdTRUE;
- }
-
- return xReturn;
-}
-
-/*-----------------------------------------------------------*/
-
-portFORCE_INLINE static void vPortRaiseBASEPRI( void )
-{
- uint32_t ulNewBASEPRI;
-
- __asm volatile
- (
- " mov %0, %1 \n"
- #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
- " cpsid i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
- #endif
- " msr basepri, %0 \n"
- " isb \n"
- " dsb \n"
- #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
- " cpsie i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
- #endif
- : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
- );
-}
-
-/*-----------------------------------------------------------*/
-
-portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
-{
- uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
-
- __asm volatile
- (
- " mrs %0, basepri \n"
- " mov %1, %2 \n"
- #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
- " cpsid i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
- #endif
- " msr basepri, %1 \n"
- " isb \n"
- " dsb \n"
- #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
- " cpsie i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
- #endif
- : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
- );
-
- /* This return will not be reached but is necessary to prevent compiler
- * warnings. */
- return ulOriginalBASEPRI;
-}
-/*-----------------------------------------------------------*/
-
-portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
-{
- __asm volatile
- (
- " msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
-
-#ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY
- #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html"
- #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0
-#endif
-/*-----------------------------------------------------------*/
-
-/* *INDENT-OFF* */
- #ifdef __cplusplus
- }
- #endif
-/* *INDENT-ON* */
-
-#endif /* PORTMACRO_H */
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+ extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if ( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+#endif
+
+/*-----------------------------------------------------------*/
+
+/* MPU specific constants. */
+#define portUSING_MPU_WRAPPERS 1
+#define portPRIVILEGE_BIT ( 0x80000000UL )
+
+#define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL )
+#define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL )
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL )
+#define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ( 0x02UL << 24UL )
+#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL )
+#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL )
+
+/* Location of the TEX,S,C,B bits in the MPU Region Attribute and Size
+ * Register (RASR). */
+#define portMPU_RASR_TEX_S_C_B_LOCATION ( 16UL )
+#define portMPU_RASR_TEX_S_C_B_MASK ( 0x3FUL )
+
+/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+#ifndef configTOTAL_MPU_REGIONS
+ /* Define to 8 for backward compatibility. */
+ #define configTOTAL_MPU_REGIONS ( 8UL )
+#endif
+
+/*
+ * The TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits define the
+ * memory type, and where necessary the cacheable and shareable properties
+ * of the memory region.
+ *
+ * The TEX, C, and B bits together indicate the memory type of the region,
+ * and:
+ * - For Normal memory, the cacheable properties of the region.
+ * - For Device memory, whether the region is shareable.
+ *
+ * For Normal memory regions, the S bit indicates whether the region is
+ * shareable. For Strongly-ordered and Device memory, the S bit is ignored.
+ *
+ * See the following two tables for setting TEX, S, C and B bits for
+ * unprivileged flash, privileged flash and privileged RAM regions.
+ *
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | TEX | C | B | Memory type | Description or Normal region cacheability | Shareable? |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 000 | 0 | 0 | Strongly-ordered | Strongly ordered | Shareable |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 000 | 0 | 1 | Device | Shared device | Shareable |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 000 | 1 | 0 | Normal | Outer and inner write-through; no write allocate | S bit |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 000 | 1 | 1 | Normal | Outer and inner write-back; no write allocate | S bit |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 001 | 0 | 0 | Normal | Outer and inner Non-cacheable | S bit |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 001 | 0 | 1 | Reserved | Reserved | Reserved |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 001 | 1 | 0 | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 001 | 1 | 1 | Normal | Outer and inner write-back; write and read allocate | S bit |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 010 | 0 | 0 | Device | Non-shared device | Not shareable |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 010 | 0 | 1 | Reserved | Reserved | Reserved |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 010 | 1 | X | Reserved | Reserved | Reserved |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 011 | X | X | Reserved | Reserved | Reserved |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 1BB | A | A | Normal | Cached memory, with AA and BB indicating the inner and | Reserved |
+ | | | | | outer cacheability rules that must be exported on the | |
+ | | | | | bus. See the table below for the cacheability policy | |
+ | | | | | encoding. memory, BB=Outer policy, AA=Inner policy. | |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ |
+ +-----------------------------------------+----------------------------------------+
+ | AA or BB subfield of {TEX,C,B} encoding | Cacheability policy |
+ +-----------------------------------------+----------------------------------------+
+ | 00 | Non-cacheable |
+ +-----------------------------------------+----------------------------------------+
+ | 01 | Write-back, write and read allocate |
+ +-----------------------------------------+----------------------------------------+
+ | 10 | Write-through, no write allocate |
+ +-----------------------------------------+----------------------------------------+
+ | 11 | Write-back, no write allocate |
+ +-----------------------------------------+----------------------------------------+
+ */
+
+/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for flash
+ * region. */
+#ifndef configTEX_S_C_B_FLASH
+ /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
+ #define configTEX_S_C_B_FLASH ( 0x07UL )
+#endif
+
+/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for RAM
+ * region. */
+#ifndef configTEX_S_C_B_SRAM
+ /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
+ #define configTEX_S_C_B_SRAM ( 0x07UL )
+#endif
+
+#define portGENERAL_PERIPHERALS_REGION ( configTOTAL_MPU_REGIONS - 5UL )
+#define portSTACK_REGION ( configTOTAL_MPU_REGIONS - 4UL )
+#define portUNPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 3UL )
+#define portPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 2UL )
+#define portPRIVILEGED_RAM_REGION ( configTOTAL_MPU_REGIONS - 1UL )
+#define portFIRST_CONFIGURABLE_REGION ( 0UL )
+#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 6UL )
+#define portNUM_CONFIGURABLE_REGIONS ( configTOTAL_MPU_REGIONS - 5UL )
+#define portTOTAL_NUM_REGIONS_IN_TCB ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus 1 to create space for the stack region. */
+
+#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" )
+
+typedef struct MPU_REGION_REGISTERS
+{
+ uint32_t ulRegionBaseAddress;
+ uint32_t ulRegionAttribute;
+} xMPU_REGION_REGISTERS;
+
+typedef struct MPU_SETTINGS
+{
+ xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS_IN_TCB ];
+} xMPU_SETTINGS;
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portDONT_DISCARD __attribute__( ( used ) )
+/*-----------------------------------------------------------*/
+
+/* SVC numbers for various services. */
+#define portSVC_START_SCHEDULER 0
+#define portSVC_YIELD 1
+#define portSVC_RAISE_PRIVILEGE 2
+
+/* Scheduler utilities. */
+
+#define portYIELD() __asm volatile ( " SVC %0 \n"::"i" ( portSVC_YIELD ) : "memory" )
+#define portYIELD_WITHIN_API() \
+ { \
+ /* Set a PendSV to request a context switch. */ \
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+ \
+ /* Barriers are normally not required but do ensure the code is completely \
+ * within the specified behaviour for the architecture. */ \
+ __asm volatile ( "dsb" ::: "memory" ); \
+ __asm volatile ( "isb" ); \
+ }
+
+#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x )
+#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
+#define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. These are
+ * not necessary for to use this port. They are defined so the common demo files
+ * (which build with all the ports) will build. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+/* Generic helper function. */
+ __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+ {
+ uint8_t ucReturn;
+
+ __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
+
+ return ucReturn;
+ }
+
+/* Check the configuration. */
+ #if ( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
+
+/* Store/clear the ready priorities in a bit map. */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/*-----------------------------------------------------------*/
+
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+#ifdef configASSERT
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+#endif
+
+/* portNOP() is not required by this port. */
+#define portNOP()
+
+#define portINLINE __inline
+
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+#endif
+/*-----------------------------------------------------------*/
+
+extern BaseType_t xIsPrivileged( void );
+extern void vResetPrivilege( void );
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+#define portIS_PRIVILEGED() xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+ */
+#define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+#define portRESET_PRIVILEGE() vResetPrivilege()
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+{
+ uint32_t ulCurrentInterrupt;
+ BaseType_t xReturn;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ if( ulCurrentInterrupt == 0 )
+ {
+ xReturn = pdFALSE;
+ }
+ else
+ {
+ xReturn = pdTRUE;
+ }
+
+ return xReturn;
+}
+
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static void vPortRaiseBASEPRI( void )
+{
+ uint32_t ulNewBASEPRI;
+
+ __asm volatile
+ (
+ " mov %0, %1 \n"
+ #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
+ " cpsid i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
+ #endif
+ " msr basepri, %0 \n"
+ " isb \n"
+ " dsb \n"
+ #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
+ " cpsie i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
+ #endif
+ : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+ );
+}
+
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
+{
+ uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
+
+ __asm volatile
+ (
+ " mrs %0, basepri \n"
+ " mov %1, %2 \n"
+ #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
+ " cpsid i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
+ #endif
+ " msr basepri, %1 \n"
+ " isb \n"
+ " dsb \n"
+ #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
+ " cpsie i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
+ #endif
+ : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+ );
+
+ /* This return will not be reached but is necessary to prevent compiler
+ * warnings. */
+ return ulOriginalBASEPRI;
+}
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
+{
+ __asm volatile
+ (
+ " msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+
+#ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY
+ #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html"
+ #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0
+#endif
+/*-----------------------------------------------------------*/
+
+/* *INDENT-OFF* */
+ #ifdef __cplusplus
+ }
+ #endif
+/* *INDENT-ON* */
+
+#endif /* PORTMACRO_H */
diff --git a/portable/GCC/ARM_CM55/non_secure/portasm.c b/portable/GCC/ARM_CM55/non_secure/portasm.c
index e3a97d5..9f9b2e6 100644
--- a/portable/GCC/ARM_CM55/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM55/non_secure/portasm.c
@@ -44,88 +44,88 @@
{
__asm volatile
(
- " .syntax unified \n"
- " \n"
- " ldr r2, pxCurrentTCBConst2 \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r3, [r2] \n"/* Read pxCurrentTCB. */
- " ldr r0, [r3] \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
- " \n"
+ " .syntax unified \n"
+ " \n"
+ " ldr r2, pxCurrentTCBConst2 \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r3, [r2] \n"/* Read pxCurrentTCB. */
+ " ldr r0, [r3] \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+ " \n"
#if ( configENABLE_MPU == 1 )
- " dmb \n"/* Complete outstanding transfers before disabling MPU. */
- " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
- " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
- " bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
- " str r4, [r2] \n"/* Disable MPU. */
- " \n"
- " adds r3, #4 \n"/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
- " ldr r4, [r3] \n"/* r4 = *r3 i.e. r4 = MAIR0. */
- " ldr r2, xMAIR0Const2 \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
- " str r4, [r2] \n"/* Program MAIR0. */
- " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
- " movs r4, #4 \n"/* r4 = 4. */
- " str r4, [r2] \n"/* Program RNR = 4. */
- " adds r3, #4 \n"/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
- " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
- " ldmia r3!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
- " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
- " \n"
+ " dmb \n"/* Complete outstanding transfers before disabling MPU. */
+ " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
+ " bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+ " str r4, [r2] \n"/* Disable MPU. */
+ " \n"
+ " adds r3, #4 \n"/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+ " ldr r4, [r3] \n"/* r4 = *r3 i.e. r4 = MAIR0. */
+ " ldr r2, xMAIR0Const2 \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
+ " str r4, [r2] \n"/* Program MAIR0. */
+ " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
+ " movs r4, #4 \n"/* r4 = 4. */
+ " str r4, [r2] \n"/* Program RNR = 4. */
+ " adds r3, #4 \n"/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+ " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r3!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
+ " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+ " \n"
#if ( configTOTAL_MPU_REGIONS == 16 )
- " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
- " movs r4, #8 \n"/* r4 = 8. */
- " str r4, [r2] \n"/* Program RNR = 8. */
- " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
- " ldmia r3!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
- " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
- " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
- " movs r4, #12 \n"/* r4 = 12. */
- " str r4, [r2] \n"/* Program RNR = 12. */
- " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
- " ldmia r3!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
- " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+ " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
+ " movs r4, #8 \n"/* r4 = 8. */
+ " str r4, [r2] \n"/* Program RNR = 8. */
+ " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r3!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
+ " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+ " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
+ " movs r4, #12 \n"/* r4 = 12. */
+ " str r4, [r2] \n"/* Program RNR = 12. */
+ " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r3!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
+ " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
#endif /* configTOTAL_MPU_REGIONS == 16 */
- " \n"
- " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
- " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
- " orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
- " str r4, [r2] \n"/* Enable MPU. */
- " dsb \n"/* Force memory writes before continuing. */
+ " \n"
+ " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
+ " orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+ " str r4, [r2] \n"/* Enable MPU. */
+ " dsb \n"/* Force memory writes before continuing. */
#endif /* configENABLE_MPU */
- " \n"
+ " \n"
#if ( configENABLE_MPU == 1 )
- " ldm r0!, {r1-r4} \n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
- " ldr r5, xSecureContextConst2 \n"
- " str r1, [r5] \n"/* Set xSecureContext to this task's value for the same. */
- " msr psplim, r2 \n"/* Set this task's PSPLIM value. */
- " msr control, r3 \n"/* Set this task's CONTROL value. */
- " adds r0, #32 \n"/* Discard everything up to r0. */
- " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
- " isb \n"
- " mov r0, #0 \n"
- " msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */
- " bx r4 \n"/* Finally, branch to EXC_RETURN. */
+ " ldm r0!, {r1-r4} \n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
+ " ldr r5, xSecureContextConst2 \n"
+ " str r1, [r5] \n"/* Set xSecureContext to this task's value for the same. */
+ " msr psplim, r2 \n"/* Set this task's PSPLIM value. */
+ " msr control, r3 \n"/* Set this task's CONTROL value. */
+ " adds r0, #32 \n"/* Discard everything up to r0. */
+ " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
+ " isb \n"
+ " mov r0, #0 \n"
+ " msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */
+ " bx r4 \n"/* Finally, branch to EXC_RETURN. */
#else /* configENABLE_MPU */
- " ldm r0!, {r1-r3} \n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
- " ldr r4, xSecureContextConst2 \n"
- " str r1, [r4] \n"/* Set xSecureContext to this task's value for the same. */
- " msr psplim, r2 \n"/* Set this task's PSPLIM value. */
- " movs r1, #2 \n"/* r1 = 2. */
- " msr CONTROL, r1 \n"/* Switch to use PSP in the thread mode. */
- " adds r0, #32 \n"/* Discard everything up to r0. */
- " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
- " isb \n"
- " mov r0, #0 \n"
- " msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */
- " bx r3 \n"/* Finally, branch to EXC_RETURN. */
+ " ldm r0!, {r1-r3} \n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
+ " ldr r4, xSecureContextConst2 \n"
+ " str r1, [r4] \n"/* Set xSecureContext to this task's value for the same. */
+ " msr psplim, r2 \n"/* Set this task's PSPLIM value. */
+ " movs r1, #2 \n"/* r1 = 2. */
+ " msr CONTROL, r1 \n"/* Switch to use PSP in the thread mode. */
+ " adds r0, #32 \n"/* Discard everything up to r0. */
+ " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
+ " isb \n"
+ " mov r0, #0 \n"
+ " msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */
+ " bx r3 \n"/* Finally, branch to EXC_RETURN. */
#endif /* configENABLE_MPU */
- " \n"
- " .align 4 \n"
- "pxCurrentTCBConst2: .word pxCurrentTCB \n"
- "xSecureContextConst2: .word xSecureContext \n"
+ " \n"
+ " .align 4 \n"
+ "pxCurrentTCBConst2: .word pxCurrentTCB \n"
+ "xSecureContextConst2: .word xSecureContext \n"
#if ( configENABLE_MPU == 1 )
- "xMPUCTRLConst2: .word 0xe000ed94 \n"
- "xMAIR0Const2: .word 0xe000edc0 \n"
- "xRNRConst2: .word 0xe000ed98 \n"
- "xRBARConst2: .word 0xe000ed9c \n"
+ "xMPUCTRLConst2: .word 0xe000ed94 \n"
+ "xMAIR0Const2: .word 0xe000edc0 \n"
+ "xRNRConst2: .word 0xe000ed98 \n"
+ "xRBARConst2: .word 0xe000ed9c \n"
#endif /* configENABLE_MPU */
);
}
@@ -135,16 +135,16 @@
{
__asm volatile
(
- " .syntax unified \n"
- " \n"
- " mrs r0, control \n"/* r0 = CONTROL. */
- " tst r0, #1 \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
- " ite ne \n"
- " movne r0, #0 \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
- " moveq r0, #1 \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
- " bx lr \n"/* Return. */
- " \n"
- " .align 4 \n"
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, control \n"/* r0 = CONTROL. */
+ " tst r0, #1 \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+ " ite ne \n"
+ " movne r0, #0 \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+ " moveq r0, #1 \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+ " bx lr \n"/* Return. */
+ " \n"
+ " .align 4 \n"
::: "r0", "memory"
);
}
@@ -154,12 +154,12 @@
{
__asm volatile
(
- " .syntax unified \n"
- " \n"
- " mrs r0, control \n"/* Read the CONTROL register. */
- " bic r0, #1 \n"/* Clear the bit 0. */
- " msr control, r0 \n"/* Write back the new CONTROL value. */
- " bx lr \n"/* Return to the caller. */
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, control \n"/* Read the CONTROL register. */
+ " bic r0, #1 \n"/* Clear the bit 0. */
+ " msr control, r0 \n"/* Write back the new CONTROL value. */
+ " bx lr \n"/* Return to the caller. */
::: "r0", "memory"
);
}
@@ -169,12 +169,12 @@
{
__asm volatile
(
- " .syntax unified \n"
- " \n"
- " mrs r0, control \n"/* r0 = CONTROL. */
- " orr r0, #1 \n"/* r0 = r0 | 1. */
- " msr control, r0 \n"/* CONTROL = r0. */
- " bx lr \n"/* Return to the caller. */
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, control \n"/* r0 = CONTROL. */
+ " orr r0, #1 \n"/* r0 = r0 | 1. */
+ " msr control, r0 \n"/* CONTROL = r0. */
+ " bx lr \n"/* Return to the caller. */
::: "r0", "memory"
);
}
@@ -184,21 +184,21 @@
{
__asm volatile
(
- " .syntax unified \n"
- " \n"
- " ldr r0, xVTORConst \n"/* Use the NVIC offset register to locate the stack. */
- " ldr r0, [r0] \n"/* Read the VTOR register which gives the address of vector table. */
- " ldr r0, [r0] \n"/* The first entry in vector table is stack pointer. */
- " msr msp, r0 \n"/* Set the MSP back to the start of the stack. */
- " cpsie i \n"/* Globally enable interrupts. */
- " cpsie f \n"
- " dsb \n"
- " isb \n"
- " svc %0 \n"/* System call to start the first task. */
- " nop \n"
- " \n"
- " .align 4 \n"
- "xVTORConst: .word 0xe000ed08 \n"
+ " .syntax unified \n"
+ " \n"
+ " ldr r0, xVTORConst \n"/* Use the NVIC offset register to locate the stack. */
+ " ldr r0, [r0] \n"/* Read the VTOR register which gives the address of vector table. */
+ " ldr r0, [r0] \n"/* The first entry in vector table is stack pointer. */
+ " msr msp, r0 \n"/* Set the MSP back to the start of the stack. */
+ " cpsie i \n"/* Globally enable interrupts. */
+ " cpsie f \n"
+ " dsb \n"
+ " isb \n"
+ " svc %0 \n"/* System call to start the first task. */
+ " nop \n"
+ " \n"
+ " .align 4 \n"
+ "xVTORConst: .word 0xe000ed08 \n"
::"i" ( portSVC_START_SCHEDULER ) : "memory"
);
}
@@ -208,14 +208,14 @@
{
__asm volatile
(
- " .syntax unified \n"
- " \n"
- " mrs r0, basepri \n"/* r0 = basepri. Return original basepri value. */
- " mov r1, %0 \n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- " msr basepri, r1 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- " dsb \n"
- " isb \n"
- " bx lr \n"/* Return. */
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, basepri \n"/* r0 = basepri. Return original basepri value. */
+ " mov r1, %0 \n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " msr basepri, r1 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " dsb \n"
+ " isb \n"
+ " bx lr \n"/* Return. */
::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
);
}
@@ -225,12 +225,12 @@
{
__asm volatile
(
- " .syntax unified \n"
- " \n"
- " msr basepri, r0 \n"/* basepri = ulMask. */
- " dsb \n"
- " isb \n"
- " bx lr \n"/* Return. */
+ " .syntax unified \n"
+ " \n"
+ " msr basepri, r0 \n"/* basepri = ulMask. */
+ " dsb \n"
+ " isb \n"
+ " bx lr \n"/* Return. */
::: "memory"
);
}
@@ -240,180 +240,180 @@
{
__asm volatile
(
- " .syntax unified \n"
- " .extern SecureContext_SaveContext \n"
- " .extern SecureContext_LoadContext \n"
- " \n"
- " ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
- " ldr r0, [r3] \n"/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
- " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r3] \n"/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
- " mrs r2, psp \n"/* Read PSP in r2. */
- " \n"
- " cbz r0, save_ns_context \n"/* No secure context to save. */
- " push {r0-r2, r14} \n"
- " bl SecureContext_SaveContext \n"/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
- " pop {r0-r3} \n"/* LR is now in r3. */
- " mov lr, r3 \n"/* LR = r3. */
- " lsls r1, r3, #25 \n"/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
- " bpl save_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
- " \n"
- " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r3] \n"/* Read pxCurrentTCB.*/
+ " .syntax unified \n"
+ " .extern SecureContext_SaveContext \n"
+ " .extern SecureContext_LoadContext \n"
+ " \n"
+ " ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ " ldr r0, [r3] \n"/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+ " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r3] \n"/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
+ " mrs r2, psp \n"/* Read PSP in r2. */
+ " \n"
+ " cbz r0, save_ns_context \n"/* No secure context to save. */
+ " push {r0-r2, r14} \n"
+ " bl SecureContext_SaveContext \n"/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+ " pop {r0-r3} \n"/* LR is now in r3. */
+ " mov lr, r3 \n"/* LR = r3. */
+ " lsls r1, r3, #25 \n"/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+ " bpl save_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+ " \n"
+ " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r3] \n"/* Read pxCurrentTCB.*/
#if ( configENABLE_MPU == 1 )
- " subs r2, r2, #16 \n"/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
- " str r2, [r1] \n"/* Save the new top of stack in TCB. */
- " mrs r1, psplim \n"/* r1 = PSPLIM. */
- " mrs r3, control \n"/* r3 = CONTROL. */
- " mov r4, lr \n"/* r4 = LR/EXC_RETURN. */
- " stmia r2!, {r0, r1, r3, r4} \n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+ " subs r2, r2, #16 \n"/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+ " str r2, [r1] \n"/* Save the new top of stack in TCB. */
+ " mrs r1, psplim \n"/* r1 = PSPLIM. */
+ " mrs r3, control \n"/* r3 = CONTROL. */
+ " mov r4, lr \n"/* r4 = LR/EXC_RETURN. */
+ " stmia r2!, {r0, r1, r3, r4} \n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
#else /* configENABLE_MPU */
- " subs r2, r2, #12 \n"/* Make space for xSecureContext, PSPLIM and LR on the stack. */
- " str r2, [r1] \n"/* Save the new top of stack in TCB. */
- " mrs r1, psplim \n"/* r1 = PSPLIM. */
- " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */
- " stmia r2!, {r0, r1, r3} \n"/* Store xSecureContext, PSPLIM and LR on the stack. */
+ " subs r2, r2, #12 \n"/* Make space for xSecureContext, PSPLIM and LR on the stack. */
+ " str r2, [r1] \n"/* Save the new top of stack in TCB. */
+ " mrs r1, psplim \n"/* r1 = PSPLIM. */
+ " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */
+ " stmia r2!, {r0, r1, r3} \n"/* Store xSecureContext, PSPLIM and LR on the stack. */
#endif /* configENABLE_MPU */
- " b select_next_task \n"
- " \n"
- " save_ns_context: \n"
- " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r3] \n"/* Read pxCurrentTCB. */
+ " b select_next_task \n"
+ " \n"
+ " save_ns_context: \n"
+ " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r3] \n"/* Read pxCurrentTCB. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
- " tst lr, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
- " it eq \n"
- " vstmdbeq r2!, {s16-s31} \n"/* Store the additional FP context registers which are not saved automatically. */
+ " tst lr, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+ " it eq \n"
+ " vstmdbeq r2!, {s16-s31} \n"/* Store the additional FP context registers which are not saved automatically. */
#endif /* configENABLE_FPU || configENABLE_MVE */
#if ( configENABLE_MPU == 1 )
- " subs r2, r2, #48 \n"/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
- " str r2, [r1] \n"/* Save the new top of stack in TCB. */
- " adds r2, r2, #16 \n"/* r2 = r2 + 16. */
- " stm r2, {r4-r11} \n"/* Store the registers that are not saved automatically. */
- " mrs r1, psplim \n"/* r1 = PSPLIM. */
- " mrs r3, control \n"/* r3 = CONTROL. */
- " mov r4, lr \n"/* r4 = LR/EXC_RETURN. */
- " subs r2, r2, #16 \n"/* r2 = r2 - 16. */
- " stmia r2!, {r0, r1, r3, r4} \n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+ " subs r2, r2, #48 \n"/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+ " str r2, [r1] \n"/* Save the new top of stack in TCB. */
+ " adds r2, r2, #16 \n"/* r2 = r2 + 16. */
+ " stm r2, {r4-r11} \n"/* Store the registers that are not saved automatically. */
+ " mrs r1, psplim \n"/* r1 = PSPLIM. */
+ " mrs r3, control \n"/* r3 = CONTROL. */
+ " mov r4, lr \n"/* r4 = LR/EXC_RETURN. */
+ " subs r2, r2, #16 \n"/* r2 = r2 - 16. */
+ " stmia r2!, {r0, r1, r3, r4} \n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
#else /* configENABLE_MPU */
- " subs r2, r2, #44 \n"/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
- " str r2, [r1] \n"/* Save the new top of stack in TCB. */
- " adds r2, r2, #12 \n"/* r2 = r2 + 12. */
- " stm r2, {r4-r11} \n"/* Store the registers that are not saved automatically. */
- " mrs r1, psplim \n"/* r1 = PSPLIM. */
- " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */
- " subs r2, r2, #12 \n"/* r2 = r2 - 12. */
- " stmia r2!, {r0, r1, r3} \n"/* Store xSecureContext, PSPLIM and LR on the stack. */
+ " subs r2, r2, #44 \n"/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+ " str r2, [r1] \n"/* Save the new top of stack in TCB. */
+ " adds r2, r2, #12 \n"/* r2 = r2 + 12. */
+ " stm r2, {r4-r11} \n"/* Store the registers that are not saved automatically. */
+ " mrs r1, psplim \n"/* r1 = PSPLIM. */
+ " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */
+ " subs r2, r2, #12 \n"/* r2 = r2 - 12. */
+ " stmia r2!, {r0, r1, r3} \n"/* Store xSecureContext, PSPLIM and LR on the stack. */
#endif /* configENABLE_MPU */
- " \n"
- " select_next_task: \n"
- " mov r0, %0 \n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
- " msr basepri, r0 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- " dsb \n"
- " isb \n"
- " bl vTaskSwitchContext \n"
- " mov r0, #0 \n"/* r0 = 0. */
- " msr basepri, r0 \n"/* Enable interrupts. */
- " \n"
- " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r3] \n"/* Read pxCurrentTCB. */
- " ldr r2, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
- " \n"
+ " \n"
+ " select_next_task: \n"
+ " mov r0, %0 \n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+ " msr basepri, r0 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " dsb \n"
+ " isb \n"
+ " bl vTaskSwitchContext \n"
+ " mov r0, #0 \n"/* r0 = 0. */
+ " msr basepri, r0 \n"/* Enable interrupts. */
+ " \n"
+ " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r3] \n"/* Read pxCurrentTCB. */
+ " ldr r2, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
+ " \n"
#if ( configENABLE_MPU == 1 )
- " dmb \n"/* Complete outstanding transfers before disabling MPU. */
- " ldr r3, xMPUCTRLConst \n"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */
- " ldr r4, [r3] \n"/* Read the value of MPU_CTRL. */
- " bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
- " str r4, [r3] \n"/* Disable MPU. */
- " \n"
- " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
- " ldr r4, [r1] \n"/* r4 = *r1 i.e. r4 = MAIR0. */
- " ldr r3, xMAIR0Const \n"/* r3 = 0xe000edc0 [Location of MAIR0]. */
- " str r4, [r3] \n"/* Program MAIR0. */
- " ldr r3, xRNRConst \n"/* r3 = 0xe000ed98 [Location of RNR]. */
- " movs r4, #4 \n"/* r4 = 4. */
- " str r4, [r3] \n"/* Program RNR = 4. */
- " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
- " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
- " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
- " stmia r3!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
- " \n"
+ " dmb \n"/* Complete outstanding transfers before disabling MPU. */
+ " ldr r3, xMPUCTRLConst \n"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r4, [r3] \n"/* Read the value of MPU_CTRL. */
+ " bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+ " str r4, [r3] \n"/* Disable MPU. */
+ " \n"
+ " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+ " ldr r4, [r1] \n"/* r4 = *r1 i.e. r4 = MAIR0. */
+ " ldr r3, xMAIR0Const \n"/* r3 = 0xe000edc0 [Location of MAIR0]. */
+ " str r4, [r3] \n"/* Program MAIR0. */
+ " ldr r3, xRNRConst \n"/* r3 = 0xe000ed98 [Location of RNR]. */
+ " movs r4, #4 \n"/* r4 = 4. */
+ " str r4, [r3] \n"/* Program RNR = 4. */
+ " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+ " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
+ " stmia r3!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+ " \n"
#if ( configTOTAL_MPU_REGIONS == 16 )
- " ldr r3, xRNRConst \n"/* r3 = 0xe000ed98 [Location of RNR]. */
- " movs r4, #8 \n"/* r4 = 8. */
- " str r4, [r3] \n"/* Program RNR = 8. */
- " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
- " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
- " stmia r3!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
- " ldr r3, xRNRConst \n"/* r3 = 0xe000ed98 [Location of RNR]. */
- " movs r4, #12 \n"/* r4 = 12. */
- " str r4, [r3] \n"/* Program RNR = 12. */
- " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
- " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
- " stmia r3!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+ " ldr r3, xRNRConst \n"/* r3 = 0xe000ed98 [Location of RNR]. */
+ " movs r4, #8 \n"/* r4 = 8. */
+ " str r4, [r3] \n"/* Program RNR = 8. */
+ " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
+ " stmia r3!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+ " ldr r3, xRNRConst \n"/* r3 = 0xe000ed98 [Location of RNR]. */
+ " movs r4, #12 \n"/* r4 = 12. */
+ " str r4, [r3] \n"/* Program RNR = 12. */
+ " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
+ " stmia r3!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
#endif /* configTOTAL_MPU_REGIONS == 16 */
- " \n"
- " ldr r3, xMPUCTRLConst \n"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */
- " ldr r4, [r3] \n"/* Read the value of MPU_CTRL. */
- " orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
- " str r4, [r3] \n"/* Enable MPU. */
- " dsb \n"/* Force memory writes before continuing. */
+ " \n"
+ " ldr r3, xMPUCTRLConst \n"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r4, [r3] \n"/* Read the value of MPU_CTRL. */
+ " orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+ " str r4, [r3] \n"/* Enable MPU. */
+ " dsb \n"/* Force memory writes before continuing. */
#endif /* configENABLE_MPU */
- " \n"
+ " \n"
#if ( configENABLE_MPU == 1 )
- " ldmia r2!, {r0, r1, r3, r4} \n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */
- " msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */
- " msr control, r3 \n"/* Restore the CONTROL register value for the task. */
- " mov lr, r4 \n"/* LR = r4. */
- " ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
- " str r0, [r3] \n"/* Restore the task's xSecureContext. */
- " cbz r0, restore_ns_context \n"/* If there is no secure context for the task, restore the non-secure context. */
- " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r3] \n"/* Read pxCurrentTCB. */
- " push {r2, r4} \n"
- " bl SecureContext_LoadContext \n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
- " pop {r2, r4} \n"
- " mov lr, r4 \n"/* LR = r4. */
- " lsls r1, r4, #25 \n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
- " bpl restore_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
- " msr psp, r2 \n"/* Remember the new top of stack for the task. */
- " bx lr \n"
+ " ldmia r2!, {r0, r1, r3, r4} \n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */
+ " msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */
+ " msr control, r3 \n"/* Restore the CONTROL register value for the task. */
+ " mov lr, r4 \n"/* LR = r4. */
+ " ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ " str r0, [r3] \n"/* Restore the task's xSecureContext. */
+ " cbz r0, restore_ns_context \n"/* If there is no secure context for the task, restore the non-secure context. */
+ " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r3] \n"/* Read pxCurrentTCB. */
+ " push {r2, r4} \n"
+ " bl SecureContext_LoadContext \n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+ " pop {r2, r4} \n"
+ " mov lr, r4 \n"/* LR = r4. */
+ " lsls r1, r4, #25 \n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+ " bpl restore_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+ " msr psp, r2 \n"/* Remember the new top of stack for the task. */
+ " bx lr \n"
#else /* configENABLE_MPU */
- " ldmia r2!, {r0, r1, r4} \n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
- " msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */
- " mov lr, r4 \n"/* LR = r4. */
- " ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
- " str r0, [r3] \n"/* Restore the task's xSecureContext. */
- " cbz r0, restore_ns_context \n"/* If there is no secure context for the task, restore the non-secure context. */
- " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r3] \n"/* Read pxCurrentTCB. */
- " push {r2, r4} \n"
- " bl SecureContext_LoadContext \n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
- " pop {r2, r4} \n"
- " mov lr, r4 \n"/* LR = r4. */
- " lsls r1, r4, #25 \n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
- " bpl restore_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
- " msr psp, r2 \n"/* Remember the new top of stack for the task. */
- " bx lr \n"
+ " ldmia r2!, {r0, r1, r4} \n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
+ " msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */
+ " mov lr, r4 \n"/* LR = r4. */
+ " ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ " str r0, [r3] \n"/* Restore the task's xSecureContext. */
+ " cbz r0, restore_ns_context \n"/* If there is no secure context for the task, restore the non-secure context. */
+ " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r3] \n"/* Read pxCurrentTCB. */
+ " push {r2, r4} \n"
+ " bl SecureContext_LoadContext \n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+ " pop {r2, r4} \n"
+ " mov lr, r4 \n"/* LR = r4. */
+ " lsls r1, r4, #25 \n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+ " bpl restore_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+ " msr psp, r2 \n"/* Remember the new top of stack for the task. */
+ " bx lr \n"
#endif /* configENABLE_MPU */
- " \n"
- " restore_ns_context: \n"
- " ldmia r2!, {r4-r11} \n"/* Restore the registers that are not automatically restored. */
+ " \n"
+ " restore_ns_context: \n"
+ " ldmia r2!, {r4-r11} \n"/* Restore the registers that are not automatically restored. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
- " tst lr, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
- " it eq \n"
- " vldmiaeq r2!, {s16-s31} \n"/* Restore the additional FP context registers which are not restored automatically. */
+ " tst lr, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+ " it eq \n"
+ " vldmiaeq r2!, {s16-s31} \n"/* Restore the additional FP context registers which are not restored automatically. */
#endif /* configENABLE_FPU || configENABLE_MVE */
- " msr psp, r2 \n"/* Remember the new top of stack for the task. */
- " bx lr \n"
- " \n"
- " .align 4 \n"
- "pxCurrentTCBConst: .word pxCurrentTCB \n"
- "xSecureContextConst: .word xSecureContext \n"
+ " msr psp, r2 \n"/* Remember the new top of stack for the task. */
+ " bx lr \n"
+ " \n"
+ " .align 4 \n"
+ "pxCurrentTCBConst: .word pxCurrentTCB \n"
+ "xSecureContextConst: .word xSecureContext \n"
#if ( configENABLE_MPU == 1 )
- "xMPUCTRLConst: .word 0xe000ed94 \n"
- "xMAIR0Const: .word 0xe000edc0 \n"
- "xRNRConst: .word 0xe000ed98 \n"
- "xRBARConst: .word 0xe000ed9c \n"
+ "xMPUCTRLConst: .word 0xe000ed94 \n"
+ "xMAIR0Const: .word 0xe000edc0 \n"
+ "xRNRConst: .word 0xe000ed98 \n"
+ "xRBARConst: .word 0xe000ed9c \n"
#endif /* configENABLE_MPU */
::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
);
@@ -424,17 +424,17 @@
{
__asm volatile
(
- " .syntax unified \n"
- " \n"
- " tst lr, #4 \n"
- " ite eq \n"
- " mrseq r0, msp \n"
- " mrsne r0, psp \n"
- " ldr r1, svchandler_address_const \n"
- " bx r1 \n"
- " \n"
- " .align 4 \n"
- "svchandler_address_const: .word vPortSVCHandler_C \n"
+ " .syntax unified \n"
+ " \n"
+ " tst lr, #4 \n"
+ " ite eq \n"
+ " mrseq r0, msp \n"
+ " mrsne r0, psp \n"
+ " ldr r1, svchandler_address_const \n"
+ " bx r1 \n"
+ " \n"
+ " .align 4 \n"
+ "svchandler_address_const: .word vPortSVCHandler_C \n"
);
}
/*-----------------------------------------------------------*/
@@ -443,10 +443,10 @@
{
__asm volatile
(
- " .syntax unified \n"
- " \n"
- " svc %0 \n"/* Secure context is allocated in the supervisor call. */
- " bx lr \n"/* Return. */
+ " .syntax unified \n"
+ " \n"
+ " svc %0 \n"/* Secure context is allocated in the supervisor call. */
+ " bx lr \n"/* Return. */
::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
);
}
@@ -456,14 +456,14 @@
{
__asm volatile
(
- " .syntax unified \n"
- " \n"
- " ldr r2, [r0] \n"/* The first item in the TCB is the top of the stack. */
- " ldr r1, [r2] \n"/* The first item on the stack is the task's xSecureContext. */
- " cmp r1, #0 \n"/* Raise svc if task's xSecureContext is not NULL. */
- " it ne \n"
- " svcne %0 \n"/* Secure context is freed in the supervisor call. */
- " bx lr \n"/* Return. */
+ " .syntax unified \n"
+ " \n"
+ " ldr r2, [r0] \n"/* The first item in the TCB is the top of the stack. */
+ " ldr r1, [r2] \n"/* The first item on the stack is the task's xSecureContext. */
+ " cmp r1, #0 \n"/* Raise svc if task's xSecureContext is not NULL. */
+ " it ne \n"
+ " svcne %0 \n"/* Secure context is freed in the supervisor call. */
+ " bx lr \n"/* Return. */
::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
);
}
diff --git a/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
index 4b1f99b..51e21ea 100644
--- a/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
@@ -155,9 +155,9 @@
* 8-bit values encoded as follows:
* Bit[7:4] - 0000 - Device Memory
* Bit[3:2] - 00 --> Device-nGnRnE
- * 01 --> Device-nGnRE
- * 10 --> Device-nGRE
- * 11 --> Device-GRE
+ * 01 --> Device-nGnRE
+ * 10 --> Device-nGRE
+ * 11 --> Device-GRE
* Bit[1:0] - 00, Reserved.
*/
#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c
index ab6fad6..a78529d 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c
@@ -44,83 +44,83 @@
{
__asm volatile
(
- " .syntax unified \n"
- " \n"
- " ldr r2, pxCurrentTCBConst2 \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r2] \n"/* Read pxCurrentTCB. */
- " ldr r0, [r1] \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
- " \n"
+ " .syntax unified \n"
+ " \n"
+ " ldr r2, pxCurrentTCBConst2 \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r2] \n"/* Read pxCurrentTCB. */
+ " ldr r0, [r1] \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+ " \n"
#if ( configENABLE_MPU == 1 )
- " dmb \n"/* Complete outstanding transfers before disabling MPU. */
- " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
- " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
- " bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
- " str r4, [r2] \n"/* Disable MPU. */
- " \n"
- " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
- " ldr r3, [r1] \n"/* r3 = *r1 i.e. r3 = MAIR0. */
- " ldr r2, xMAIR0Const2 \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
- " str r3, [r2] \n"/* Program MAIR0. */
- " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
- " movs r3, #4 \n"/* r3 = 4. */
- " str r3, [r2] \n"/* Program RNR = 4. */
- " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
- " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
- " ldmia r1!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
- " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
- " \n"
+ " dmb \n"/* Complete outstanding transfers before disabling MPU. */
+ " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
+ " bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+ " str r4, [r2] \n"/* Disable MPU. */
+ " \n"
+ " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+ " ldr r3, [r1] \n"/* r3 = *r1 i.e. r3 = MAIR0. */
+ " ldr r2, xMAIR0Const2 \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
+ " str r3, [r2] \n"/* Program MAIR0. */
+ " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
+ " movs r3, #4 \n"/* r3 = 4. */
+ " str r3, [r2] \n"/* Program RNR = 4. */
+ " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+ " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
+ " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+ " \n"
#if ( configTOTAL_MPU_REGIONS == 16 )
- " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
- " movs r3, #8 \n"/* r3 = 8. */
- " str r3, [r2] \n"/* Program RNR = 8. */
- " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
- " ldmia r1!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
- " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
- " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
- " movs r3, #12 \n"/* r3 = 12. */
- " str r3, [r2] \n"/* Program RNR = 12. */
- " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
- " ldmia r1!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
- " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+ " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
+ " movs r3, #8 \n"/* r3 = 8. */
+ " str r3, [r2] \n"/* Program RNR = 8. */
+ " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
+ " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+ " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
+ " movs r3, #12 \n"/* r3 = 12. */
+ " str r3, [r2] \n"/* Program RNR = 12. */
+ " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
+ " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
#endif /* configTOTAL_MPU_REGIONS == 16 */
- " \n"
- " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
- " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
- " orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
- " str r4, [r2] \n"/* Enable MPU. */
- " dsb \n"/* Force memory writes before continuing. */
+ " \n"
+ " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
+ " orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+ " str r4, [r2] \n"/* Enable MPU. */
+ " dsb \n"/* Force memory writes before continuing. */
#endif /* configENABLE_MPU */
- " \n"
+ " \n"
#if ( configENABLE_MPU == 1 )
- " ldm r0!, {r1-r3} \n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
- " msr psplim, r1 \n"/* Set this task's PSPLIM value. */
- " msr control, r2 \n"/* Set this task's CONTROL value. */
- " adds r0, #32 \n"/* Discard everything up to r0. */
- " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
- " isb \n"
- " mov r0, #0 \n"
- " msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */
- " bx r3 \n"/* Finally, branch to EXC_RETURN. */
+ " ldm r0!, {r1-r3} \n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
+ " msr psplim, r1 \n"/* Set this task's PSPLIM value. */
+ " msr control, r2 \n"/* Set this task's CONTROL value. */
+ " adds r0, #32 \n"/* Discard everything up to r0. */
+ " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
+ " isb \n"
+ " mov r0, #0 \n"
+ " msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */
+ " bx r3 \n"/* Finally, branch to EXC_RETURN. */
#else /* configENABLE_MPU */
- " ldm r0!, {r1-r2} \n"/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
- " msr psplim, r1 \n"/* Set this task's PSPLIM value. */
- " movs r1, #2 \n"/* r1 = 2. */
- " msr CONTROL, r1 \n"/* Switch to use PSP in the thread mode. */
- " adds r0, #32 \n"/* Discard everything up to r0. */
- " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
- " isb \n"
- " mov r0, #0 \n"
- " msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */
- " bx r2 \n"/* Finally, branch to EXC_RETURN. */
+ " ldm r0!, {r1-r2} \n"/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+ " msr psplim, r1 \n"/* Set this task's PSPLIM value. */
+ " movs r1, #2 \n"/* r1 = 2. */
+ " msr CONTROL, r1 \n"/* Switch to use PSP in the thread mode. */
+ " adds r0, #32 \n"/* Discard everything up to r0. */
+ " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
+ " isb \n"
+ " mov r0, #0 \n"
+ " msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */
+ " bx r2 \n"/* Finally, branch to EXC_RETURN. */
#endif /* configENABLE_MPU */
- " \n"
- " .align 4 \n"
- "pxCurrentTCBConst2: .word pxCurrentTCB \n"
+ " \n"
+ " .align 4 \n"
+ "pxCurrentTCBConst2: .word pxCurrentTCB \n"
#if ( configENABLE_MPU == 1 )
- "xMPUCTRLConst2: .word 0xe000ed94 \n"
- "xMAIR0Const2: .word 0xe000edc0 \n"
- "xRNRConst2: .word 0xe000ed98 \n"
- "xRBARConst2: .word 0xe000ed9c \n"
+ "xMPUCTRLConst2: .word 0xe000ed94 \n"
+ "xMAIR0Const2: .word 0xe000edc0 \n"
+ "xRNRConst2: .word 0xe000ed98 \n"
+ "xRBARConst2: .word 0xe000ed9c \n"
#endif /* configENABLE_MPU */
);
}
@@ -130,16 +130,16 @@
{
__asm volatile
(
- " .syntax unified \n"
- " \n"
- " mrs r0, control \n"/* r0 = CONTROL. */
- " tst r0, #1 \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
- " ite ne \n"
- " movne r0, #0 \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
- " moveq r0, #1 \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
- " bx lr \n"/* Return. */
- " \n"
- " .align 4 \n"
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, control \n"/* r0 = CONTROL. */
+ " tst r0, #1 \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+ " ite ne \n"
+ " movne r0, #0 \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+ " moveq r0, #1 \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+ " bx lr \n"/* Return. */
+ " \n"
+ " .align 4 \n"
::: "r0", "memory"
);
}
@@ -149,12 +149,12 @@
{
__asm volatile
(
- " .syntax unified \n"
- " \n"
- " mrs r0, control \n"/* Read the CONTROL register. */
- " bic r0, #1 \n"/* Clear the bit 0. */
- " msr control, r0 \n"/* Write back the new CONTROL value. */
- " bx lr \n"/* Return to the caller. */
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, control \n"/* Read the CONTROL register. */
+ " bic r0, #1 \n"/* Clear the bit 0. */
+ " msr control, r0 \n"/* Write back the new CONTROL value. */
+ " bx lr \n"/* Return to the caller. */
::: "r0", "memory"
);
}
@@ -164,12 +164,12 @@
{
__asm volatile
(
- " .syntax unified \n"
- " \n"
- " mrs r0, control \n"/* r0 = CONTROL. */
- " orr r0, #1 \n"/* r0 = r0 | 1. */
- " msr control, r0 \n"/* CONTROL = r0. */
- " bx lr \n"/* Return to the caller. */
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, control \n"/* r0 = CONTROL. */
+ " orr r0, #1 \n"/* r0 = r0 | 1. */
+ " msr control, r0 \n"/* CONTROL = r0. */
+ " bx lr \n"/* Return to the caller. */
::: "r0", "memory"
);
}
@@ -179,21 +179,21 @@
{
__asm volatile
(
- " .syntax unified \n"
- " \n"
- " ldr r0, xVTORConst \n"/* Use the NVIC offset register to locate the stack. */
- " ldr r0, [r0] \n"/* Read the VTOR register which gives the address of vector table. */
- " ldr r0, [r0] \n"/* The first entry in vector table is stack pointer. */
- " msr msp, r0 \n"/* Set the MSP back to the start of the stack. */
- " cpsie i \n"/* Globally enable interrupts. */
- " cpsie f \n"
- " dsb \n"
- " isb \n"
- " svc %0 \n"/* System call to start the first task. */
- " nop \n"
- " \n"
- " .align 4 \n"
- "xVTORConst: .word 0xe000ed08 \n"
+ " .syntax unified \n"
+ " \n"
+ " ldr r0, xVTORConst \n"/* Use the NVIC offset register to locate the stack. */
+ " ldr r0, [r0] \n"/* Read the VTOR register which gives the address of vector table. */
+ " ldr r0, [r0] \n"/* The first entry in vector table is stack pointer. */
+ " msr msp, r0 \n"/* Set the MSP back to the start of the stack. */
+ " cpsie i \n"/* Globally enable interrupts. */
+ " cpsie f \n"
+ " dsb \n"
+ " isb \n"
+ " svc %0 \n"/* System call to start the first task. */
+ " nop \n"
+ " \n"
+ " .align 4 \n"
+ "xVTORConst: .word 0xe000ed08 \n"
::"i" ( portSVC_START_SCHEDULER ) : "memory"
);
}
@@ -203,14 +203,14 @@
{
__asm volatile
(
- " .syntax unified \n"
- " \n"
- " mrs r0, basepri \n"/* r0 = basepri. Return original basepri value. */
- " mov r1, %0 \n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- " msr basepri, r1 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- " dsb \n"
- " isb \n"
- " bx lr \n"/* Return. */
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, basepri \n"/* r0 = basepri. Return original basepri value. */
+ " mov r1, %0 \n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " msr basepri, r1 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " dsb \n"
+ " isb \n"
+ " bx lr \n"/* Return. */
::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
);
}
@@ -220,12 +220,12 @@
{
__asm volatile
(
- " .syntax unified \n"
- " \n"
- " msr basepri, r0 \n"/* basepri = ulMask. */
- " dsb \n"
- " isb \n"
- " bx lr \n"/* Return. */
+ " .syntax unified \n"
+ " \n"
+ " msr basepri, r0 \n"/* basepri = ulMask. */
+ " dsb \n"
+ " isb \n"
+ " bx lr \n"/* Return. */
::: "memory"
);
}
@@ -235,110 +235,110 @@
{
__asm volatile
(
- " .syntax unified \n"
- " \n"
- " mrs r0, psp \n"/* Read PSP in r0. */
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, psp \n"/* Read PSP in r0. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
- " tst lr, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
- " it eq \n"
- " vstmdbeq r0!, {s16-s31} \n"/* Store the additional FP context registers which are not saved automatically. */
+ " tst lr, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+ " it eq \n"
+ " vstmdbeq r0!, {s16-s31} \n"/* Store the additional FP context registers which are not saved automatically. */
#endif /* configENABLE_FPU || configENABLE_MVE */
#if ( configENABLE_MPU == 1 )
- " mrs r1, psplim \n"/* r1 = PSPLIM. */
- " mrs r2, control \n"/* r2 = CONTROL. */
- " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */
- " stmdb r0!, {r1-r11} \n"/* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */
+ " mrs r1, psplim \n"/* r1 = PSPLIM. */
+ " mrs r2, control \n"/* r2 = CONTROL. */
+ " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */
+ " stmdb r0!, {r1-r11} \n"/* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */
#else /* configENABLE_MPU */
- " mrs r2, psplim \n"/* r2 = PSPLIM. */
- " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */
- " stmdb r0!, {r2-r11} \n"/* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
+ " mrs r2, psplim \n"/* r2 = PSPLIM. */
+ " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */
+ " stmdb r0!, {r2-r11} \n"/* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
#endif /* configENABLE_MPU */
- " \n"
- " ldr r2, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r2] \n"/* Read pxCurrentTCB. */
- " str r0, [r1] \n"/* Save the new top of stack in TCB. */
- " \n"
- " mov r0, %0 \n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
- " msr basepri, r0 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- " dsb \n"
- " isb \n"
- " bl vTaskSwitchContext \n"
- " mov r0, #0 \n"/* r0 = 0. */
- " msr basepri, r0 \n"/* Enable interrupts. */
- " \n"
- " ldr r2, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r2] \n"/* Read pxCurrentTCB. */
- " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
- " \n"
+ " \n"
+ " ldr r2, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r2] \n"/* Read pxCurrentTCB. */
+ " str r0, [r1] \n"/* Save the new top of stack in TCB. */
+ " \n"
+ " mov r0, %0 \n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+ " msr basepri, r0 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " dsb \n"
+ " isb \n"
+ " bl vTaskSwitchContext \n"
+ " mov r0, #0 \n"/* r0 = 0. */
+ " msr basepri, r0 \n"/* Enable interrupts. */
+ " \n"
+ " ldr r2, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r2] \n"/* Read pxCurrentTCB. */
+ " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+ " \n"
#if ( configENABLE_MPU == 1 )
- " dmb \n"/* Complete outstanding transfers before disabling MPU. */
- " ldr r2, xMPUCTRLConst \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
- " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
- " bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
- " str r4, [r2] \n"/* Disable MPU. */
- " \n"
- " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
- " ldr r3, [r1] \n"/* r3 = *r1 i.e. r3 = MAIR0. */
- " ldr r2, xMAIR0Const \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
- " str r3, [r2] \n"/* Program MAIR0. */
- " ldr r2, xRNRConst \n"/* r2 = 0xe000ed98 [Location of RNR]. */
- " movs r3, #4 \n"/* r3 = 4. */
- " str r3, [r2] \n"/* Program RNR = 4. */
- " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
- " ldr r2, xRBARConst \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
- " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
- " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
- " \n"
+ " dmb \n"/* Complete outstanding transfers before disabling MPU. */
+ " ldr r2, xMPUCTRLConst \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
+ " bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+ " str r4, [r2] \n"/* Disable MPU. */
+ " \n"
+ " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+ " ldr r3, [r1] \n"/* r3 = *r1 i.e. r3 = MAIR0. */
+ " ldr r2, xMAIR0Const \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
+ " str r3, [r2] \n"/* Program MAIR0. */
+ " ldr r2, xRNRConst \n"/* r2 = 0xe000ed98 [Location of RNR]. */
+ " movs r3, #4 \n"/* r3 = 4. */
+ " str r3, [r2] \n"/* Program RNR = 4. */
+ " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+ " ldr r2, xRBARConst \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
+ " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+ " \n"
#if ( configTOTAL_MPU_REGIONS == 16 )
- " ldr r2, xRNRConst \n"/* r2 = 0xe000ed98 [Location of RNR]. */
- " movs r3, #8 \n"/* r3 = 8. */
- " str r3, [r2] \n"/* Program RNR = 8. */
- " ldr r2, xRBARConst \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
- " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
- " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
- " ldr r2, xRNRConst \n"/* r2 = 0xe000ed98 [Location of RNR]. */
- " movs r3, #12 \n"/* r3 = 12. */
- " str r3, [r2] \n"/* Program RNR = 12. */
- " ldr r2, xRBARConst \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
- " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
- " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+ " ldr r2, xRNRConst \n"/* r2 = 0xe000ed98 [Location of RNR]. */
+ " movs r3, #8 \n"/* r3 = 8. */
+ " str r3, [r2] \n"/* Program RNR = 8. */
+ " ldr r2, xRBARConst \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
+ " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+ " ldr r2, xRNRConst \n"/* r2 = 0xe000ed98 [Location of RNR]. */
+ " movs r3, #12 \n"/* r3 = 12. */
+ " str r3, [r2] \n"/* Program RNR = 12. */
+ " ldr r2, xRBARConst \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
+ " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
#endif /* configTOTAL_MPU_REGIONS == 16 */
- " \n"
- " ldr r2, xMPUCTRLConst \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
- " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
- " orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
- " str r4, [r2] \n"/* Enable MPU. */
- " dsb \n"/* Force memory writes before continuing. */
+ " \n"
+ " ldr r2, xMPUCTRLConst \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
+ " orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+ " str r4, [r2] \n"/* Enable MPU. */
+ " dsb \n"/* Force memory writes before continuing. */
#endif /* configENABLE_MPU */
- " \n"
+ " \n"
#if ( configENABLE_MPU == 1 )
- " ldmia r0!, {r1-r11} \n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */
+ " ldmia r0!, {r1-r11} \n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */
#else /* configENABLE_MPU */
- " ldmia r0!, {r2-r11} \n"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
+ " ldmia r0!, {r2-r11} \n"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
#endif /* configENABLE_MPU */
- " \n"
+ " \n"
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
- " tst r3, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
- " it eq \n"
- " vldmiaeq r0!, {s16-s31} \n"/* Restore the additional FP context registers which are not restored automatically. */
+ " tst r3, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+ " it eq \n"
+ " vldmiaeq r0!, {s16-s31} \n"/* Restore the additional FP context registers which are not restored automatically. */
#endif /* configENABLE_FPU || configENABLE_MVE */
- " \n"
+ " \n"
#if ( configENABLE_MPU == 1 )
- " msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */
- " msr control, r2 \n"/* Restore the CONTROL register value for the task. */
+ " msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */
+ " msr control, r2 \n"/* Restore the CONTROL register value for the task. */
#else /* configENABLE_MPU */
- " msr psplim, r2 \n"/* Restore the PSPLIM register value for the task. */
+ " msr psplim, r2 \n"/* Restore the PSPLIM register value for the task. */
#endif /* configENABLE_MPU */
- " msr psp, r0 \n"/* Remember the new top of stack for the task. */
- " bx r3 \n"
- " \n"
- " .align 4 \n"
- "pxCurrentTCBConst: .word pxCurrentTCB \n"
+ " msr psp, r0 \n"/* Remember the new top of stack for the task. */
+ " bx r3 \n"
+ " \n"
+ " .align 4 \n"
+ "pxCurrentTCBConst: .word pxCurrentTCB \n"
#if ( configENABLE_MPU == 1 )
- "xMPUCTRLConst: .word 0xe000ed94 \n"
- "xMAIR0Const: .word 0xe000edc0 \n"
- "xRNRConst: .word 0xe000ed98 \n"
- "xRBARConst: .word 0xe000ed9c \n"
+ "xMPUCTRLConst: .word 0xe000ed94 \n"
+ "xMAIR0Const: .word 0xe000edc0 \n"
+ "xRNRConst: .word 0xe000ed98 \n"
+ "xRBARConst: .word 0xe000ed9c \n"
#endif /* configENABLE_MPU */
::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
);
@@ -349,17 +349,17 @@
{
__asm volatile
(
- " .syntax unified \n"
- " \n"
- " tst lr, #4 \n"
- " ite eq \n"
- " mrseq r0, msp \n"
- " mrsne r0, psp \n"
- " ldr r1, svchandler_address_const \n"
- " bx r1 \n"
- " \n"
- " .align 4 \n"
- "svchandler_address_const: .word vPortSVCHandler_C \n"
+ " .syntax unified \n"
+ " \n"
+ " tst lr, #4 \n"
+ " ite eq \n"
+ " mrseq r0, msp \n"
+ " mrsne r0, psp \n"
+ " ldr r1, svchandler_address_const \n"
+ " bx r1 \n"
+ " \n"
+ " .align 4 \n"
+ "svchandler_address_const: .word vPortSVCHandler_C \n"
);
}
/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
index 4b1f99b..51e21ea 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
@@ -155,9 +155,9 @@
* 8-bit values encoded as follows:
* Bit[7:4] - 0000 - Device Memory
* Bit[3:2] - 00 --> Device-nGnRnE
- * 01 --> Device-nGnRE
- * 10 --> Device-nGRE
- * 11 --> Device-GRE
+ * 01 --> Device-nGnRE
+ * 10 --> Device-nGRE
+ * 11 --> Device-GRE
* Bit[1:0] - 00, Reserved.
*/
#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
diff --git a/portable/GCC/ARM_CM7/ReadMe.txt b/portable/GCC/ARM_CM7/ReadMe.txt
index d661449..90be0b2 100644
--- a/portable/GCC/ARM_CM7/ReadMe.txt
+++ b/portable/GCC/ARM_CM7/ReadMe.txt
@@ -1,18 +1,18 @@
-There are two options for running FreeRTOS on ARM Cortex-M7 microcontrollers.
-The best option depends on the revision of the ARM Cortex-M7 core in use. The
-revision is specified by an 'r' number, and a 'p' number, so will look something
-like 'r0p1'. Check the documentation for the microcontroller in use to find the
-revision of the Cortex-M7 core used in that microcontroller. If in doubt, use
-the FreeRTOS port provided specifically for r0p1 revisions, as that can be used
-with all core revisions.
-
-The first option is to use the ARM Cortex-M4F port, and the second option is to
-use the Cortex-M7 r0p1 port - the latter containing a minor errata workaround.
-
-If the revision of the ARM Cortex-M7 core is not r0p1 then either option can be
-used, but it is recommended to use the FreeRTOS ARM Cortex-M4F port located in
-the /FreeRTOS/Source/portable/GCC/ARM_CM4F directory.
-
-If the revision of the ARM Cortex-M7 core is r0p1 then use the FreeRTOS ARM
-Cortex-M7 r0p1 port located in the /FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1
-directory.
\ No newline at end of file
+There are two options for running FreeRTOS on ARM Cortex-M7 microcontrollers.
+The best option depends on the revision of the ARM Cortex-M7 core in use. The
+revision is specified by an 'r' number, and a 'p' number, so will look something
+like 'r0p1'. Check the documentation for the microcontroller in use to find the
+revision of the Cortex-M7 core used in that microcontroller. If in doubt, use
+the FreeRTOS port provided specifically for r0p1 revisions, as that can be used
+with all core revisions.
+
+The first option is to use the ARM Cortex-M4F port, and the second option is to
+use the Cortex-M7 r0p1 port - the latter containing a minor errata workaround.
+
+If the revision of the ARM Cortex-M7 core is not r0p1 then either option can be
+used, but it is recommended to use the FreeRTOS ARM Cortex-M4F port located in
+the /FreeRTOS/Source/portable/GCC/ARM_CM4F directory.
+
+If the revision of the ARM Cortex-M7 core is r0p1 then use the FreeRTOS ARM
+Cortex-M7 r0p1 port located in the /FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1
+directory.
diff --git a/portable/GCC/ARM_CM7/r0p1/port.c b/portable/GCC/ARM_CM7/r0p1/port.c
index 7bfaa1c..a9c69aa 100644
--- a/portable/GCC/ARM_CM7/r0p1/port.c
+++ b/portable/GCC/ARM_CM7/r0p1/port.c
@@ -1,829 +1,829 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the ARM CM7 port.
-*----------------------------------------------------------*/
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-#ifndef __VFP_FP__
- #error This port can only be used when the project options are configured to enable hardware floating point support.
-#endif
-
-/* Constants required to manipulate the core. Registers first... */
-#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
-#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
-#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
-#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
-/* ...then bits in the registers. */
-#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
-#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
-#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
-#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
-#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
-#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
-#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
-
-#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
-
-/* Constants required to check the validity of an interrupt priority. */
-#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
-#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
-#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
-#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
-#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
-#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
-#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
-#define portPRIGROUP_SHIFT ( 8UL )
-
-/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
-#define portVECTACTIVE_MASK ( 0xFFUL )
-
-/* Constants required to manipulate the VFP. */
-#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
-#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
-
-/* Constants required to set up the initial stack. */
-#define portINITIAL_XPSR ( 0x01000000 )
-#define portINITIAL_EXC_RETURN ( 0xfffffffd )
-
-/* The systick is a 24-bit counter. */
-#define portMAX_24_BIT_NUMBER ( 0xffffffUL )
-
-/* For strict compliance with the Cortex-M spec the task start address should
- * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
-#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
-
-/* A fiddle factor to estimate the number of SysTick counts that would have
- * occurred while the SysTick counter is stopped during tickless idle
- * calculations. */
-#define portMISSED_COUNTS_FACTOR ( 94UL )
-
-/* Let the user override the default SysTick clock rate. If defined by the
- * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
- * configuration register. */
-#ifndef configSYSTICK_CLOCK_HZ
- #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ )
- /* Ensure the SysTick is clocked at the same frequency as the core. */
- #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT )
-#else
- /* Select the option to clock SysTick not at the same frequency as the core. */
- #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 )
-#endif
-
-/* Let the user override the pre-loading of the initial LR with the address of
- * prvTaskExitError() in case it messes up unwinding of the stack in the
- * debugger. */
-#ifdef configTASK_RETURN_ADDRESS
- #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
-#else
- #define portTASK_RETURN_ADDRESS prvTaskExitError
-#endif
-
-/*
- * Setup the timer to generate the tick interrupts. The implementation in this
- * file is weak to allow application writers to change the timer used to
- * generate the tick interrupt.
- */
-void vPortSetupTimerInterrupt( void );
-
-/*
- * Exception handlers.
- */
-void xPortPendSVHandler( void ) __attribute__( ( naked ) );
-void xPortSysTickHandler( void );
-void vPortSVCHandler( void ) __attribute__( ( naked ) );
-
-/*
- * Start first task is a separate function so it can be tested in isolation.
- */
-static void prvPortStartFirstTask( void ) __attribute__( ( naked ) );
-
-/*
- * Function to enable the VFP.
- */
-static void vPortEnableVFP( void ) __attribute__( ( naked ) );
-
-/*
- * Used to catch tasks that attempt to return from their implementing function.
- */
-static void prvTaskExitError( void );
-
-/*-----------------------------------------------------------*/
-
-/* Each task maintains its own interrupt status in the critical nesting
- * variable. */
-static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
-
-/*
- * The number of SysTick increments that make up one tick period.
- */
-#if ( configUSE_TICKLESS_IDLE == 1 )
- static uint32_t ulTimerCountsForOneTick = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * The maximum number of tick periods that can be suppressed is limited by the
- * 24 bit resolution of the SysTick timer.
- */
-#if ( configUSE_TICKLESS_IDLE == 1 )
- static uint32_t xMaximumPossibleSuppressedTicks = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * Compensate for the CPU cycles that pass while the SysTick is stopped (low
- * power functionality only.
- */
-#if ( configUSE_TICKLESS_IDLE == 1 )
- static uint32_t ulStoppedTimerCompensation = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
- * FreeRTOS API functions are not called from interrupts that have been assigned
- * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
- */
-#if ( configASSERT_DEFINED == 1 )
- static uint8_t ucMaxSysCallPriority = 0;
- static uint32_t ulMaxPRIGROUPValue = 0;
- static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
-#endif /* configASSERT_DEFINED */
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
-{
- /* Simulate the stack frame as it would be created by a context switch
- * interrupt. */
-
- /* Offset added to account for the way the MCU uses the stack on entry/exit
- * of interrupts, and to ensure alignment. */
- pxTopOfStack--;
-
- *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
- pxTopOfStack--;
- *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
-
- /* Save code space by skipping register initialisation. */
- pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
-
- /* A save method is being used that requires each task to maintain its
- * own exec return value. */
- pxTopOfStack--;
- *pxTopOfStack = portINITIAL_EXC_RETURN;
-
- pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
-
- return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
- volatile uint32_t ulDummy = 0;
-
- /* A function that implements a task must not exit or attempt to return to
- * its caller as there is nothing to return to. If a task wants to exit it
- * should instead call vTaskDelete( NULL ).
- *
- * Artificially force an assert() to be triggered if configASSERT() is
- * defined, then stop here so application writers can catch the error. */
- configASSERT( uxCriticalNesting == ~0UL );
- portDISABLE_INTERRUPTS();
-
- while( ulDummy == 0 )
- {
- /* This file calls prvTaskExitError() after the scheduler has been
- * started to remove a compiler warning about the function being defined
- * but never called. ulDummy is used purely to quieten other warnings
- * about code appearing after this function is called - making ulDummy
- * volatile makes the compiler think the function could return and
- * therefore not output an 'unreachable code' warning for code that appears
- * after it. */
- }
-}
-/*-----------------------------------------------------------*/
-
-void vPortSVCHandler( void )
-{
- __asm volatile (
- " ldr r3, pxCurrentTCBConst2 \n"/* Restore the context. */
- " ldr r1, [r3] \n"/* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
- " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. */
- " ldmia r0!, {r4-r11, r14} \n"/* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
- " msr psp, r0 \n"/* Restore the task stack pointer. */
- " isb \n"
- " mov r0, #0 \n"
- " msr basepri, r0 \n"
- " bx r14 \n"
- " \n"
- " .align 4 \n"
- "pxCurrentTCBConst2: .word pxCurrentTCB \n"
- );
-}
-/*-----------------------------------------------------------*/
-
-static void prvPortStartFirstTask( void )
-{
- /* Start the first task. This also clears the bit that indicates the FPU is
- * in use in case the FPU was used before the scheduler was started - which
- * would otherwise result in the unnecessary leaving of space in the SVC stack
- * for lazy saving of FPU registers. */
- __asm volatile (
- " ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */
- " ldr r0, [r0] \n"
- " ldr r0, [r0] \n"
- " msr msp, r0 \n"/* Set the msp back to the start of the stack. */
- " mov r0, #0 \n"/* Clear the bit that indicates the FPU is in use, see comment above. */
- " msr control, r0 \n"
- " cpsie i \n"/* Globally enable interrupts. */
- " cpsie f \n"
- " dsb \n"
- " isb \n"
- " svc 0 \n"/* System call to start first task. */
- " nop \n"
- " .ltorg \n"
- );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-BaseType_t xPortStartScheduler( void )
-{
- /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
- * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
- configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
-
- #if ( configASSERT_DEFINED == 1 )
- {
- volatile uint32_t ulOriginalPriority;
- volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
- volatile uint8_t ucMaxPriorityValue;
-
- /* Determine the maximum priority from which ISR safe FreeRTOS API
- * functions can be called. ISR safe functions are those that end in
- * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
- * ensure interrupt entry is as fast and simple as possible.
- *
- * Save the interrupt priority value that is about to be clobbered. */
- ulOriginalPriority = *pucFirstUserPriorityRegister;
-
- /* Determine the number of priority bits available. First write to all
- * possible bits. */
- *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
-
- /* Read the value back to see how many bits stuck. */
- ucMaxPriorityValue = *pucFirstUserPriorityRegister;
-
- /* Use the same mask on the maximum system call priority. */
- ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
-
- /* Calculate the maximum acceptable priority group value for the number
- * of bits read back. */
- ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
-
- while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
- {
- ulMaxPRIGROUPValue--;
- ucMaxPriorityValue <<= ( uint8_t ) 0x01;
- }
-
- #ifdef __NVIC_PRIO_BITS
- {
- /* Check the CMSIS configuration that defines the number of
- * priority bits matches the number of priority bits actually queried
- * from the hardware. */
- configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
- }
- #endif
-
- #ifdef configPRIO_BITS
- {
- /* Check the FreeRTOS configuration that defines the number of
- * priority bits matches the number of priority bits actually queried
- * from the hardware. */
- configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
- }
- #endif
-
- /* Shift the priority group value back to its position within the AIRCR
- * register. */
- ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
- ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
- /* Restore the clobbered interrupt priority register to its original
- * value. */
- *pucFirstUserPriorityRegister = ulOriginalPriority;
- }
- #endif /* configASSERT_DEFINED */
-
- /* Make PendSV and SysTick the lowest priority interrupts. */
- portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
- portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
-
- /* Start the timer that generates the tick ISR. Interrupts are disabled
- * here already. */
- vPortSetupTimerInterrupt();
-
- /* Initialise the critical nesting count ready for the first task. */
- uxCriticalNesting = 0;
-
- /* Ensure the VFP is enabled - it should be anyway. */
- vPortEnableVFP();
-
- /* Lazy save always. */
- *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
-
- /* Start the first task. */
- prvPortStartFirstTask();
-
- /* Should never get here as the tasks will now be executing! Call the task
- * exit error function to prevent compiler warnings about a static function
- * not being called in the case that the application writer overrides this
- * functionality by defining configTASK_RETURN_ADDRESS. Call
- * vTaskSwitchContext() so link time optimisation does not remove the
- * symbol. */
- vTaskSwitchContext();
- prvTaskExitError();
-
- /* Should not get here! */
- return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
- /* Not implemented in ports where there is nothing to return to.
- * Artificially force an assert. */
- configASSERT( uxCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
- portDISABLE_INTERRUPTS();
- uxCriticalNesting++;
-
- /* This is not the interrupt safe version of the enter critical function so
- * assert() if it is being called from an interrupt context. Only API
- * functions that end in "FromISR" can be used in an interrupt. Only assert if
- * the critical nesting count is 1 to protect against recursive calls if the
- * assert function also uses a critical section. */
- if( uxCriticalNesting == 1 )
- {
- configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
- }
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
- configASSERT( uxCriticalNesting );
- uxCriticalNesting--;
-
- if( uxCriticalNesting == 0 )
- {
- portENABLE_INTERRUPTS();
- }
-}
-/*-----------------------------------------------------------*/
-
-void xPortPendSVHandler( void )
-{
- /* This is a naked function. */
-
- __asm volatile
- (
- " mrs r0, psp \n"
- " isb \n"
- " \n"
- " ldr r3, pxCurrentTCBConst \n"/* Get the location of the current TCB. */
- " ldr r2, [r3] \n"
- " \n"
- " tst r14, #0x10 \n"/* Is the task using the FPU context? If so, push high vfp registers. */
- " it eq \n"
- " vstmdbeq r0!, {s16-s31} \n"
- " \n"
- " stmdb r0!, {r4-r11, r14} \n"/* Save the core registers. */
- " str r0, [r2] \n"/* Save the new top of stack into the first member of the TCB. */
- " \n"
- " stmdb sp!, {r0, r3} \n"
- " mov r0, %0 \n"
- " cpsid i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
- " msr basepri, r0 \n"
- " dsb \n"
- " isb \n"
- " cpsie i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
- " bl vTaskSwitchContext \n"
- " mov r0, #0 \n"
- " msr basepri, r0 \n"
- " ldmia sp!, {r0, r3} \n"
- " \n"
- " ldr r1, [r3] \n"/* The first item in pxCurrentTCB is the task top of stack. */
- " ldr r0, [r1] \n"
- " \n"
- " ldmia r0!, {r4-r11, r14} \n"/* Pop the core registers. */
- " \n"
- " tst r14, #0x10 \n"/* Is the task using the FPU context? If so, pop the high vfp registers too. */
- " it eq \n"
- " vldmiaeq r0!, {s16-s31} \n"
- " \n"
- " msr psp, r0 \n"
- " isb \n"
- " \n"
- #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */
- #if WORKAROUND_PMU_CM001 == 1
- " push { r14 } \n"
- " pop { pc } \n"
- #endif
- #endif
- " \n"
- " bx r14 \n"
- " \n"
- " .align 4 \n"
- "pxCurrentTCBConst: .word pxCurrentTCB \n"
- ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
- );
-}
-/*-----------------------------------------------------------*/
-
-void xPortSysTickHandler( void )
-{
- /* The SysTick runs at the lowest interrupt priority, so when this interrupt
- * executes all interrupts must be unmasked. There is therefore no need to
- * save and then restore the interrupt mask value as its value is already
- * known. */
- portDISABLE_INTERRUPTS();
- {
- /* Increment the RTOS tick. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- /* A context switch is required. Context switching is performed in
- * the PendSV interrupt. Pend the PendSV interrupt. */
- portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
- }
- }
- portENABLE_INTERRUPTS();
-}
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TICKLESS_IDLE == 1 )
-
- __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
- {
- uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
- TickType_t xModifiableIdleTime;
-
- /* Make sure the SysTick reload value does not overflow the counter. */
- if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
- {
- xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
- }
-
- /* Enter a critical section but don't use the taskENTER_CRITICAL()
- * method as that will mask interrupts that should exit sleep mode. */
- __asm volatile ( "cpsid i" ::: "memory" );
- __asm volatile ( "dsb" );
- __asm volatile ( "isb" );
-
- /* If a context switch is pending or a task is waiting for the scheduler
- * to be unsuspended then abandon the low power entry. */
- if( eTaskConfirmSleepModeStatus() == eAbortSleep )
- {
- /* Re-enable interrupts - see comments above the cpsid instruction
- * above. */
- __asm volatile ( "cpsie i" ::: "memory" );
- }
- else
- {
- /* Stop the SysTick momentarily. The time the SysTick is stopped for
- * is accounted for as best it can be, but using the tickless mode will
- * inevitably result in some tiny drift of the time maintained by the
- * kernel with respect to calendar time. */
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
-
- /* Use the SysTick current-value register to determine the number of
- * SysTick decrements remaining until the next tick interrupt. If the
- * current-value register is zero, then there are actually
- * ulTimerCountsForOneTick decrements remaining, not zero, because the
- * SysTick requests the interrupt when decrementing from 1 to 0. */
- ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
- if( ulSysTickDecrementsLeft == 0 )
- {
- ulSysTickDecrementsLeft = ulTimerCountsForOneTick;
- }
-
- /* Calculate the reload value required to wait xExpectedIdleTime
- * tick periods. -1 is used because this code normally executes part
- * way through the first tick period. But if the SysTick IRQ is now
- * pending, then clear the IRQ, suppressing the first tick, and correct
- * the reload value to reflect that the second tick period is already
- * underway. The expected idle time is always at least two ticks. */
- ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
-
- if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )
- {
- portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;
- ulReloadValue -= ulTimerCountsForOneTick;
- }
-
- if( ulReloadValue > ulStoppedTimerCompensation )
- {
- ulReloadValue -= ulStoppedTimerCompensation;
- }
-
- /* Set the new reload value. */
- portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
-
- /* Clear the SysTick count flag and set the count value back to
- * zero. */
- portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
- /* Restart SysTick. */
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
- /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
- * set its parameter to 0 to indicate that its implementation contains
- * its own wait for interrupt or wait for event instruction, and so wfi
- * should not be executed again. However, the original expected idle
- * time variable must remain unmodified, so a copy is taken. */
- xModifiableIdleTime = xExpectedIdleTime;
- configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
-
- if( xModifiableIdleTime > 0 )
- {
- __asm volatile ( "dsb" ::: "memory" );
- __asm volatile ( "wfi" );
- __asm volatile ( "isb" );
- }
-
- configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
-
- /* Re-enable interrupts to allow the interrupt that brought the MCU
- * out of sleep mode to execute immediately. See comments above
- * the cpsid instruction above. */
- __asm volatile ( "cpsie i" ::: "memory" );
- __asm volatile ( "dsb" );
- __asm volatile ( "isb" );
-
- /* Disable interrupts again because the clock is about to be stopped
- * and interrupts that execute while the clock is stopped will increase
- * any slippage between the time maintained by the RTOS and calendar
- * time. */
- __asm volatile ( "cpsid i" ::: "memory" );
- __asm volatile ( "dsb" );
- __asm volatile ( "isb" );
-
- /* Disable the SysTick clock without reading the
- * portNVIC_SYSTICK_CTRL_REG register to ensure the
- * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
- * the time the SysTick is stopped for is accounted for as best it can
- * be, but using the tickless mode will inevitably result in some tiny
- * drift of the time maintained by the kernel with respect to calendar
- * time*/
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
-
- /* Determine whether the SysTick has already counted to zero. */
- if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
- {
- uint32_t ulCalculatedLoadValue;
-
- /* The tick interrupt ended the sleep (or is now pending), and
- * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG
- * with whatever remains of the new tick period. */
- ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
-
- /* Don't allow a tiny value, or values that have somehow
- * underflowed because the post sleep hook did something
- * that took too long or because the SysTick current-value register
- * is zero. */
- if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
- {
- ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
- }
-
- portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
-
- /* As the pending tick will be processed as soon as this
- * function exits, the tick value maintained by the tick is stepped
- * forward by one less than the time spent waiting. */
- ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
- }
- else
- {
- /* Something other than the tick interrupt ended the sleep. */
-
- /* Use the SysTick current-value register to determine the
- * number of SysTick decrements remaining until the expected idle
- * time would have ended. */
- ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
- #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )
- {
- /* If the SysTick is not using the core clock, the current-
- * value register might still be zero here. In that case, the
- * SysTick didn't load from the reload register, and there are
- * ulReloadValue decrements remaining in the expected idle
- * time, not zero. */
- if( ulSysTickDecrementsLeft == 0 )
- {
- ulSysTickDecrementsLeft = ulReloadValue;
- }
- }
- #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
-
- /* Work out how long the sleep lasted rounded to complete tick
- * periods (not the ulReload value which accounted for part
- * ticks). */
- ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;
-
- /* How many complete tick periods passed while the processor
- * was waiting? */
- ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
-
- /* The reload value is set to whatever fraction of a single tick
- * period remains. */
- portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
- }
-
- /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,
- * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If
- * the SysTick is not using the core clock, temporarily configure it to
- * use the core clock. This configuration forces the SysTick to load
- * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next
- * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready
- * to receive the standard value immediately. */
- portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
- portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
- #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )
- {
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
- }
- #else
- {
- /* The temporary usage of the core clock has served its purpose,
- * as described above. Resume usage of the other clock. */
- portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
-
- if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
- {
- /* The partial tick period already ended. Be sure the SysTick
- * counts it only once. */
- portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;
- }
-
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
- portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
- }
- #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
-
- /* Step the tick to account for any tick periods that elapsed. */
- vTaskStepTick( ulCompleteTickPeriods );
-
- /* Exit with interrupts enabled. */
- __asm volatile ( "cpsie i" ::: "memory" );
- }
- }
-
-#endif /* #if configUSE_TICKLESS_IDLE */
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the systick timer to generate the tick interrupts at the required
- * frequency.
- */
-__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
-{
- /* Calculate the constants required to configure the tick interrupt. */
- #if ( configUSE_TICKLESS_IDLE == 1 )
- {
- ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
- xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
- ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
- }
- #endif /* configUSE_TICKLESS_IDLE */
-
- /* Stop and clear the SysTick. */
- portNVIC_SYSTICK_CTRL_REG = 0UL;
- portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
- /* Configure SysTick to interrupt at the requested rate. */
- portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
-}
-/*-----------------------------------------------------------*/
-
-/* This is a naked function. */
-static void vPortEnableVFP( void )
-{
- __asm volatile
- (
- " ldr.w r0, =0xE000ED88 \n"/* The FPU enable bits are in the CPACR. */
- " ldr r1, [r0] \n"
- " \n"
- " orr r1, r1, #( 0xf << 20 ) \n"/* Enable CP10 and CP11 coprocessors, then save back. */
- " str r1, [r0] \n"
- " bx r14 \n"
- " .ltorg \n"
- );
-}
-/*-----------------------------------------------------------*/
-
-#if ( configASSERT_DEFINED == 1 )
-
- void vPortValidateInterruptPriority( void )
- {
- uint32_t ulCurrentInterrupt;
- uint8_t ucCurrentPriority;
-
- /* Obtain the number of the currently executing interrupt. */
- __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
-
- /* Is the interrupt number a user defined interrupt? */
- if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
- {
- /* Look up the interrupt's priority. */
- ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
-
- /* The following assertion will fail if a service routine (ISR) for
- * an interrupt that has been assigned a priority above
- * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
- * function. ISR safe FreeRTOS API functions must *only* be called
- * from interrupts that have been assigned a priority at or below
- * configMAX_SYSCALL_INTERRUPT_PRIORITY.
- *
- * Numerically low interrupt priority numbers represent logically high
- * interrupt priorities, therefore the priority of the interrupt must
- * be set to a value equal to or numerically *higher* than
- * configMAX_SYSCALL_INTERRUPT_PRIORITY.
- *
- * Interrupts that use the FreeRTOS API must not be left at their
- * default priority of zero as that is the highest possible priority,
- * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
- * and therefore also guaranteed to be invalid.
- *
- * FreeRTOS maintains separate thread and ISR API functions to ensure
- * interrupt entry is as fast and simple as possible.
- *
- * The following links provide detailed information:
- * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
- * https://www.FreeRTOS.org/FAQHelp.html */
- configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
- }
-
- /* Priority grouping: The interrupt controller (NVIC) allows the bits
- * that define each interrupt's priority to be split between bits that
- * define the interrupt's pre-emption priority bits and bits that define
- * the interrupt's sub-priority. For simplicity all bits must be defined
- * to be pre-emption priority bits. The following assertion will fail if
- * this is not the case (if some bits represent a sub-priority).
- *
- * If the application only uses CMSIS libraries for interrupt
- * configuration then the correct setting can be achieved on all Cortex-M
- * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
- * scheduler. Note however that some vendor specific peripheral libraries
- * assume a non-zero priority group setting, in which cases using a value
- * of zero will result in unpredictable behaviour. */
- configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
- }
-
-#endif /* configASSERT_DEFINED */
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*-----------------------------------------------------------
+* Implementation of functions defined in portable.h for the ARM CM7 port.
+*----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef __VFP_FP__
+ #error This port can only be used when the project options are configured to enable hardware floating point support.
+#endif
+
+/* Constants required to manipulate the core. Registers first... */
+#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
+/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
+#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
+
+#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
+#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT ( 8UL )
+
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK ( 0xFFUL )
+
+/* Constants required to manipulate the VFP. */
+#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
+#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR ( 0x01000000 )
+#define portINITIAL_EXC_RETURN ( 0xfffffffd )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER ( 0xffffffUL )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+ * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+ * occurred while the SysTick counter is stopped during tickless idle
+ * calculations. */
+#define portMISSED_COUNTS_FACTOR ( 94UL )
+
+/* Let the user override the default SysTick clock rate. If defined by the
+ * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
+ * configuration register. */
+#ifndef configSYSTICK_CLOCK_HZ
+ #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ )
+ /* Ensure the SysTick is clocked at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT )
+#else
+ /* Select the option to clock SysTick not at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 )
+#endif
+
+/* Let the user override the pre-loading of the initial LR with the address of
+ * prvTaskExitError() in case it messes up unwinding of the stack in the
+ * debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
+#else
+ #define portTASK_RETURN_ADDRESS prvTaskExitError
+#endif
+
+/*
+ * Setup the timer to generate the tick interrupts. The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortPendSVHandler( void ) __attribute__( ( naked ) );
+void xPortSysTickHandler( void );
+void vPortSVCHandler( void ) __attribute__( ( naked ) );
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+static void prvPortStartFirstTask( void ) __attribute__( ( naked ) );
+
+/*
+ * Function to enable the VFP.
+ */
+static void vPortEnableVFP( void ) __attribute__( ( naked ) );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+ * variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+ static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+ static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+ static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( configASSERT_DEFINED == 1 )
+ static uint8_t ucMaxSysCallPriority = 0;
+ static uint32_t ulMaxPRIGROUPValue = 0;
+ static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+ TaskFunction_t pxCode,
+ void * pvParameters )
+{
+ /* Simulate the stack frame as it would be created by a context switch
+ * interrupt. */
+
+ /* Offset added to account for the way the MCU uses the stack on entry/exit
+ * of interrupts, and to ensure alignment. */
+ pxTopOfStack--;
+
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+
+ /* Save code space by skipping register initialisation. */
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+
+ /* A save method is being used that requires each task to maintain its
+ * own exec return value. */
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_EXC_RETURN;
+
+ pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+ volatile uint32_t ulDummy = 0;
+
+ /* A function that implements a task must not exit or attempt to return to
+ * its caller as there is nothing to return to. If a task wants to exit it
+ * should instead call vTaskDelete( NULL ).
+ *
+ * Artificially force an assert() to be triggered if configASSERT() is
+ * defined, then stop here so application writers can catch the error. */
+ configASSERT( uxCriticalNesting == ~0UL );
+ portDISABLE_INTERRUPTS();
+
+ while( ulDummy == 0 )
+ {
+ /* This file calls prvTaskExitError() after the scheduler has been
+ * started to remove a compiler warning about the function being defined
+ * but never called. ulDummy is used purely to quieten other warnings
+ * about code appearing after this function is called - making ulDummy
+ * volatile makes the compiler think the function could return and
+ * therefore not output an 'unreachable code' warning for code that appears
+ * after it. */
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler( void )
+{
+ __asm volatile (
+ " ldr r3, pxCurrentTCBConst2 \n"/* Restore the context. */
+ " ldr r1, [r3] \n"/* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
+ " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. */
+ " ldmia r0!, {r4-r11, r14} \n"/* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
+ " msr psp, r0 \n"/* Restore the task stack pointer. */
+ " isb \n"
+ " mov r0, #0 \n"
+ " msr basepri, r0 \n"
+ " bx r14 \n"
+ " \n"
+ " .align 4 \n"
+ "pxCurrentTCBConst2: .word pxCurrentTCB \n"
+ );
+}
+/*-----------------------------------------------------------*/
+
+static void prvPortStartFirstTask( void )
+{
+ /* Start the first task. This also clears the bit that indicates the FPU is
+ * in use in case the FPU was used before the scheduler was started - which
+ * would otherwise result in the unnecessary leaving of space in the SVC stack
+ * for lazy saving of FPU registers. */
+ __asm volatile (
+ " ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */
+ " ldr r0, [r0] \n"
+ " ldr r0, [r0] \n"
+ " msr msp, r0 \n"/* Set the msp back to the start of the stack. */
+ " mov r0, #0 \n"/* Clear the bit that indicates the FPU is in use, see comment above. */
+ " msr control, r0 \n"
+ " cpsie i \n"/* Globally enable interrupts. */
+ " cpsie f \n"
+ " dsb \n"
+ " isb \n"
+ " svc 0 \n"/* System call to start first task. */
+ " nop \n"
+ " .ltorg \n"
+ );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+ /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
+ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+
+ #if ( configASSERT_DEFINED == 1 )
+ {
+ volatile uint32_t ulOriginalPriority;
+ volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine the maximum priority from which ISR safe FreeRTOS API
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * ensure interrupt entry is as fast and simple as possible.
+ *
+ * Save the interrupt priority value that is about to be clobbered. */
+ ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+ /* Determine the number of priority bits available. First write to all
+ * possible bits. */
+ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+ /* Use the same mask on the maximum system call priority. */
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+ /* Calculate the maximum acceptable priority group value for the number
+ * of bits read back. */
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+ {
+ ulMaxPRIGROUPValue--;
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+ }
+
+ #ifdef __NVIC_PRIO_BITS
+ {
+ /* Check the CMSIS configuration that defines the number of
+ * priority bits matches the number of priority bits actually queried
+ * from the hardware. */
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+ }
+ #endif
+
+ #ifdef configPRIO_BITS
+ {
+ /* Check the FreeRTOS configuration that defines the number of
+ * priority bits matches the number of priority bits actually queried
+ * from the hardware. */
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+ }
+ #endif
+
+ /* Shift the priority group value back to its position within the AIRCR
+ * register. */
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+ /* Restore the clobbered interrupt priority register to its original
+ * value. */
+ *pucFirstUserPriorityRegister = ulOriginalPriority;
+ }
+ #endif /* configASSERT_DEFINED */
+
+ /* Make PendSV and SysTick the lowest priority interrupts. */
+ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
+ portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ * here already. */
+ vPortSetupTimerInterrupt();
+
+ /* Initialise the critical nesting count ready for the first task. */
+ uxCriticalNesting = 0;
+
+ /* Ensure the VFP is enabled - it should be anyway. */
+ vPortEnableVFP();
+
+ /* Lazy save always. */
+ *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
+
+ /* Start the first task. */
+ prvPortStartFirstTask();
+
+ /* Should never get here as the tasks will now be executing! Call the task
+ * exit error function to prevent compiler warnings about a static function
+ * not being called in the case that the application writer overrides this
+ * functionality by defining configTASK_RETURN_ADDRESS. Call
+ * vTaskSwitchContext() so link time optimisation does not remove the
+ * symbol. */
+ vTaskSwitchContext();
+ prvTaskExitError();
+
+ /* Should not get here! */
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+ /* Not implemented in ports where there is nothing to return to.
+ * Artificially force an assert. */
+ configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+ portDISABLE_INTERRUPTS();
+ uxCriticalNesting++;
+
+ /* This is not the interrupt safe version of the enter critical function so
+ * assert() if it is being called from an interrupt context. Only API
+ * functions that end in "FromISR" can be used in an interrupt. Only assert if
+ * the critical nesting count is 1 to protect against recursive calls if the
+ * assert function also uses a critical section. */
+ if( uxCriticalNesting == 1 )
+ {
+ configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+ configASSERT( uxCriticalNesting );
+ uxCriticalNesting--;
+
+ if( uxCriticalNesting == 0 )
+ {
+ portENABLE_INTERRUPTS();
+ }
+}
+/*-----------------------------------------------------------*/
+
+void xPortPendSVHandler( void )
+{
+ /* This is a naked function. */
+
+ __asm volatile
+ (
+ " mrs r0, psp \n"
+ " isb \n"
+ " \n"
+ " ldr r3, pxCurrentTCBConst \n"/* Get the location of the current TCB. */
+ " ldr r2, [r3] \n"
+ " \n"
+ " tst r14, #0x10 \n"/* Is the task using the FPU context? If so, push high vfp registers. */
+ " it eq \n"
+ " vstmdbeq r0!, {s16-s31} \n"
+ " \n"
+ " stmdb r0!, {r4-r11, r14} \n"/* Save the core registers. */
+ " str r0, [r2] \n"/* Save the new top of stack into the first member of the TCB. */
+ " \n"
+ " stmdb sp!, {r0, r3} \n"
+ " mov r0, %0 \n"
+ " cpsid i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
+ " msr basepri, r0 \n"
+ " dsb \n"
+ " isb \n"
+ " cpsie i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
+ " bl vTaskSwitchContext \n"
+ " mov r0, #0 \n"
+ " msr basepri, r0 \n"
+ " ldmia sp!, {r0, r3} \n"
+ " \n"
+ " ldr r1, [r3] \n"/* The first item in pxCurrentTCB is the task top of stack. */
+ " ldr r0, [r1] \n"
+ " \n"
+ " ldmia r0!, {r4-r11, r14} \n"/* Pop the core registers. */
+ " \n"
+ " tst r14, #0x10 \n"/* Is the task using the FPU context? If so, pop the high vfp registers too. */
+ " it eq \n"
+ " vldmiaeq r0!, {s16-s31} \n"
+ " \n"
+ " msr psp, r0 \n"
+ " isb \n"
+ " \n"
+ #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */
+ #if WORKAROUND_PMU_CM001 == 1
+ " push { r14 } \n"
+ " pop { pc } \n"
+ #endif
+ #endif
+ " \n"
+ " bx r14 \n"
+ " \n"
+ " .align 4 \n"
+ "pxCurrentTCBConst: .word pxCurrentTCB \n"
+ ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+ );
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+ /* The SysTick runs at the lowest interrupt priority, so when this interrupt
+ * executes all interrupts must be unmasked. There is therefore no need to
+ * save and then restore the interrupt mask value as its value is already
+ * known. */
+ portDISABLE_INTERRUPTS();
+ {
+ /* Increment the RTOS tick. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ /* A context switch is required. Context switching is performed in
+ * the PendSV interrupt. Pend the PendSV interrupt. */
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+ }
+ }
+ portENABLE_INTERRUPTS();
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+
+ __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+ {
+ uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
+ TickType_t xModifiableIdleTime;
+
+ /* Make sure the SysTick reload value does not overflow the counter. */
+ if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+ {
+ xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+ }
+
+ /* Enter a critical section but don't use the taskENTER_CRITICAL()
+ * method as that will mask interrupts that should exit sleep mode. */
+ __asm volatile ( "cpsid i" ::: "memory" );
+ __asm volatile ( "dsb" );
+ __asm volatile ( "isb" );
+
+ /* If a context switch is pending or a task is waiting for the scheduler
+ * to be unsuspended then abandon the low power entry. */
+ if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+ {
+ /* Re-enable interrupts - see comments above the cpsid instruction
+ * above. */
+ __asm volatile ( "cpsie i" ::: "memory" );
+ }
+ else
+ {
+ /* Stop the SysTick momentarily. The time the SysTick is stopped for
+ * is accounted for as best it can be, but using the tickless mode will
+ * inevitably result in some tiny drift of the time maintained by the
+ * kernel with respect to calendar time. */
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
+
+ /* Use the SysTick current-value register to determine the number of
+ * SysTick decrements remaining until the next tick interrupt. If the
+ * current-value register is zero, then there are actually
+ * ulTimerCountsForOneTick decrements remaining, not zero, because the
+ * SysTick requests the interrupt when decrementing from 1 to 0. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulTimerCountsForOneTick;
+ }
+
+ /* Calculate the reload value required to wait xExpectedIdleTime
+ * tick periods. -1 is used because this code normally executes part
+ * way through the first tick period. But if the SysTick IRQ is now
+ * pending, then clear the IRQ, suppressing the first tick, and correct
+ * the reload value to reflect that the second tick period is already
+ * underway. The expected idle time is always at least two ticks. */
+ ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+ if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )
+ {
+ portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;
+ ulReloadValue -= ulTimerCountsForOneTick;
+ }
+
+ if( ulReloadValue > ulStoppedTimerCompensation )
+ {
+ ulReloadValue -= ulStoppedTimerCompensation;
+ }
+
+ /* Set the new reload value. */
+ portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+ /* Clear the SysTick count flag and set the count value back to
+ * zero. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+ /* Restart SysTick. */
+ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+ /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
+ * set its parameter to 0 to indicate that its implementation contains
+ * its own wait for interrupt or wait for event instruction, and so wfi
+ * should not be executed again. However, the original expected idle
+ * time variable must remain unmodified, so a copy is taken. */
+ xModifiableIdleTime = xExpectedIdleTime;
+ configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+
+ if( xModifiableIdleTime > 0 )
+ {
+ __asm volatile ( "dsb" ::: "memory" );
+ __asm volatile ( "wfi" );
+ __asm volatile ( "isb" );
+ }
+
+ configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+ /* Re-enable interrupts to allow the interrupt that brought the MCU
+ * out of sleep mode to execute immediately. See comments above
+ * the cpsid instruction above. */
+ __asm volatile ( "cpsie i" ::: "memory" );
+ __asm volatile ( "dsb" );
+ __asm volatile ( "isb" );
+
+ /* Disable interrupts again because the clock is about to be stopped
+ * and interrupts that execute while the clock is stopped will increase
+ * any slippage between the time maintained by the RTOS and calendar
+ * time. */
+ __asm volatile ( "cpsid i" ::: "memory" );
+ __asm volatile ( "dsb" );
+ __asm volatile ( "isb" );
+
+ /* Disable the SysTick clock without reading the
+ * portNVIC_SYSTICK_CTRL_REG register to ensure the
+ * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
+ * the time the SysTick is stopped for is accounted for as best it can
+ * be, but using the tickless mode will inevitably result in some tiny
+ * drift of the time maintained by the kernel with respect to calendar
+ * time*/
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
+
+ /* Determine whether the SysTick has already counted to zero. */
+ if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+ {
+ uint32_t ulCalculatedLoadValue;
+
+ /* The tick interrupt ended the sleep (or is now pending), and
+ * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG
+ * with whatever remains of the new tick period. */
+ ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+ /* Don't allow a tiny value, or values that have somehow
+ * underflowed because the post sleep hook did something
+ * that took too long or because the SysTick current-value register
+ * is zero. */
+ if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+ {
+ ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+ }
+
+ portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+ /* As the pending tick will be processed as soon as this
+ * function exits, the tick value maintained by the tick is stepped
+ * forward by one less than the time spent waiting. */
+ ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+ }
+ else
+ {
+ /* Something other than the tick interrupt ended the sleep. */
+
+ /* Use the SysTick current-value register to determine the
+ * number of SysTick decrements remaining until the expected idle
+ * time would have ended. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )
+ {
+ /* If the SysTick is not using the core clock, the current-
+ * value register might still be zero here. In that case, the
+ * SysTick didn't load from the reload register, and there are
+ * ulReloadValue decrements remaining in the expected idle
+ * time, not zero. */
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulReloadValue;
+ }
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Work out how long the sleep lasted rounded to complete tick
+ * periods (not the ulReload value which accounted for part
+ * ticks). */
+ ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;
+
+ /* How many complete tick periods passed while the processor
+ * was waiting? */
+ ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+ /* The reload value is set to whatever fraction of a single tick
+ * period remains. */
+ portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+ }
+
+ /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,
+ * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If
+ * the SysTick is not using the core clock, temporarily configure it to
+ * use the core clock. This configuration forces the SysTick to load
+ * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next
+ * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready
+ * to receive the standard value immediately. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )
+ {
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ }
+ #else
+ {
+ /* The temporary usage of the core clock has served its purpose,
+ * as described above. Resume usage of the other clock. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
+
+ if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+ {
+ /* The partial tick period already ended. Be sure the SysTick
+ * counts it only once. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;
+ }
+
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Step the tick to account for any tick periods that elapsed. */
+ vTaskStepTick( ulCompleteTickPeriods );
+
+ /* Exit with interrupts enabled. */
+ __asm volatile ( "cpsie i" ::: "memory" );
+ }
+ }
+
+#endif /* #if configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
+{
+ /* Calculate the constants required to configure the tick interrupt. */
+ #if ( configUSE_TICKLESS_IDLE == 1 )
+ {
+ ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+ xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+ ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+ }
+ #endif /* configUSE_TICKLESS_IDLE */
+
+ /* Stop and clear the SysTick. */
+ portNVIC_SYSTICK_CTRL_REG = 0UL;
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+ /* Configure SysTick to interrupt at the requested rate. */
+ portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+}
+/*-----------------------------------------------------------*/
+
+/* This is a naked function. */
+static void vPortEnableVFP( void )
+{
+ __asm volatile
+ (
+ " ldr.w r0, =0xE000ED88 \n"/* The FPU enable bits are in the CPACR. */
+ " ldr r1, [r0] \n"
+ " \n"
+ " orr r1, r1, #( 0xf << 20 ) \n"/* Enable CP10 and CP11 coprocessors, then save back. */
+ " str r1, [r0] \n"
+ " bx r14 \n"
+ " .ltorg \n"
+ );
+}
+/*-----------------------------------------------------------*/
+
+#if ( configASSERT_DEFINED == 1 )
+
+ void vPortValidateInterruptPriority( void )
+ {
+ uint32_t ulCurrentInterrupt;
+ uint8_t ucCurrentPriority;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ /* Is the interrupt number a user defined interrupt? */
+ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+ {
+ /* Look up the interrupt's priority. */
+ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+ /* The following assertion will fail if a service routine (ISR) for
+ * an interrupt that has been assigned a priority above
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+ * function. ISR safe FreeRTOS API functions must *only* be called
+ * from interrupts that have been assigned a priority at or below
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Numerically low interrupt priority numbers represent logically high
+ * interrupt priorities, therefore the priority of the interrupt must
+ * be set to a value equal to or numerically *higher* than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Interrupts that use the FreeRTOS API must not be left at their
+ * default priority of zero as that is the highest possible priority,
+ * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+ * and therefore also guaranteed to be invalid.
+ *
+ * FreeRTOS maintains separate thread and ISR API functions to ensure
+ * interrupt entry is as fast and simple as possible.
+ *
+ * The following links provide detailed information:
+ * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+ * https://www.FreeRTOS.org/FAQHelp.html */
+ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+ }
+
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits
+ * that define each interrupt's priority to be split between bits that
+ * define the interrupt's pre-emption priority bits and bits that define
+ * the interrupt's sub-priority. For simplicity all bits must be defined
+ * to be pre-emption priority bits. The following assertion will fail if
+ * this is not the case (if some bits represent a sub-priority).
+ *
+ * If the application only uses CMSIS libraries for interrupt
+ * configuration then the correct setting can be achieved on all Cortex-M
+ * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+ * scheduler. Note however that some vendor specific peripheral libraries
+ * assume a non-zero priority group setting, in which cases using a value
+ * of zero will result in unpredictable behaviour. */
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+ }
+
+#endif /* configASSERT_DEFINED */
diff --git a/portable/GCC/ARM_CM7/r0p1/portmacro.h b/portable/GCC/ARM_CM7/r0p1/portmacro.h
index c772a14..214dc2b 100644
--- a/portable/GCC/ARM_CM7/r0p1/portmacro.h
+++ b/portable/GCC/ARM_CM7/r0p1/portmacro.h
@@ -1,249 +1,249 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-
-#ifndef PORTMACRO_H
- #define PORTMACRO_H
-
- #ifdef __cplusplus
- extern "C" {
- #endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
-
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
-
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portDONT_DISCARD __attribute__( ( used ) )
-/*-----------------------------------------------------------*/
-
-/* Scheduler utilities. */
- #define portYIELD() \
- { \
- /* Set a PendSV to request a context switch. */ \
- portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
- \
- /* Barriers are normally not required but do ensure the code is completely \
- * within the specified behaviour for the architecture. */ \
- __asm volatile ( "dsb" ::: "memory" ); \
- __asm volatile ( "isb" ); \
- }
-
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 )
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/* Critical section management. */
- extern void vPortEnterCritical( void );
- extern void vPortExitCritical( void );
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x )
- #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
- #define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. These are
- * not necessary for to use this port. They are defined so the common demo files
- * (which build with all the ports) will build. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
-/*-----------------------------------------------------------*/
-
-/* Tickless idle/low power functionality. */
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specific optimisations. */
- #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
- #endif
-
- #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
-/* Generic helper function. */
- __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
- {
- uint8_t ucReturn;
-
- __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
-
- return ucReturn;
- }
-
-/* Check the configuration. */
- #if ( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
-
-/* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-/*-----------------------------------------------------------*/
-
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
-
- #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-/*-----------------------------------------------------------*/
-
- #ifdef configASSERT
- void vPortValidateInterruptPriority( void );
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
- #endif
-
-/* portNOP() is not required by this port. */
- #define portNOP()
-
- #define portINLINE __inline
-
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
- #endif
-
- portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
- {
- uint32_t ulCurrentInterrupt;
- BaseType_t xReturn;
-
- /* Obtain the number of the currently executing interrupt. */
- __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
-
- if( ulCurrentInterrupt == 0 )
- {
- xReturn = pdFALSE;
- }
- else
- {
- xReturn = pdTRUE;
- }
-
- return xReturn;
- }
-
-/*-----------------------------------------------------------*/
-
- portFORCE_INLINE static void vPortRaiseBASEPRI( void )
- {
- uint32_t ulNewBASEPRI;
-
- __asm volatile
- (
- " mov %0, %1 \n"\
- " cpsid i \n"\
- " msr basepri, %0 \n"\
- " isb \n"\
- " dsb \n"\
- " cpsie i \n"\
- : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
- );
- }
-
-/*-----------------------------------------------------------*/
-
- portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
- {
- uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
-
- __asm volatile
- (
- " mrs %0, basepri \n"\
- " mov %1, %2 \n"\
- " cpsid i \n"\
- " msr basepri, %1 \n"\
- " isb \n"\
- " dsb \n"\
- " cpsie i \n"\
- : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
- );
-
- /* This return will not be reached but is necessary to prevent compiler
- * warnings. */
- return ulOriginalBASEPRI;
- }
-/*-----------------------------------------------------------*/
-
- portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
- {
- __asm volatile
- (
- " msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory"
- );
- }
-/*-----------------------------------------------------------*/
-
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
-
- #ifdef __cplusplus
- }
- #endif
-
-#endif /* PORTMACRO_H */
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+#ifndef PORTMACRO_H
+ #define PORTMACRO_H
+
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+ #define portCHAR char
+ #define portFLOAT float
+ #define portDOUBLE double
+ #define portLONG long
+ #define portSHORT short
+ #define portSTACK_TYPE uint32_t
+ #define portBASE_TYPE long
+
+ typedef portSTACK_TYPE StackType_t;
+ typedef long BaseType_t;
+ typedef unsigned long UBaseType_t;
+
+ #if ( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+ #else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+ #endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+ #define portSTACK_GROWTH ( -1 )
+ #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+ #define portBYTE_ALIGNMENT 8
+ #define portDONT_DISCARD __attribute__( ( used ) )
+/*-----------------------------------------------------------*/
+
+/* Scheduler utilities. */
+ #define portYIELD() \
+ { \
+ /* Set a PendSV to request a context switch. */ \
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+ \
+ /* Barriers are normally not required but do ensure the code is completely \
+ * within the specified behaviour for the architecture. */ \
+ __asm volatile ( "dsb" ::: "memory" ); \
+ __asm volatile ( "isb" ); \
+ }
+
+ #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+ #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+ #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 )
+ #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+ extern void vPortEnterCritical( void );
+ extern void vPortExitCritical( void );
+ #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
+ #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x )
+ #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
+ #define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )
+ #define portENTER_CRITICAL() vPortEnterCritical()
+ #define portEXIT_CRITICAL() vPortExitCritical()
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. These are
+ * not necessary for to use this port. They are defined so the common demo files
+ * (which build with all the ports) will build. */
+ #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+ #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+ #ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+ #endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+ #endif
+
+ #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+/* Generic helper function. */
+ __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+ {
+ uint8_t ucReturn;
+
+ __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
+
+ return ucReturn;
+ }
+
+/* Check the configuration. */
+ #if ( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
+
+/* Store/clear the ready priorities in a bit map. */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/*-----------------------------------------------------------*/
+
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+ #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+ #ifdef configASSERT
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+ #endif
+
+/* portNOP() is not required by this port. */
+ #define portNOP()
+
+ #define portINLINE __inline
+
+ #ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+ #endif
+
+ portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+ {
+ uint32_t ulCurrentInterrupt;
+ BaseType_t xReturn;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ if( ulCurrentInterrupt == 0 )
+ {
+ xReturn = pdFALSE;
+ }
+ else
+ {
+ xReturn = pdTRUE;
+ }
+
+ return xReturn;
+ }
+
+/*-----------------------------------------------------------*/
+
+ portFORCE_INLINE static void vPortRaiseBASEPRI( void )
+ {
+ uint32_t ulNewBASEPRI;
+
+ __asm volatile
+ (
+ " mov %0, %1 \n"\
+ " cpsid i \n"\
+ " msr basepri, %0 \n"\
+ " isb \n"\
+ " dsb \n"\
+ " cpsie i \n"\
+ : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+ );
+ }
+
+/*-----------------------------------------------------------*/
+
+ portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
+ {
+ uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
+
+ __asm volatile
+ (
+ " mrs %0, basepri \n"\
+ " mov %1, %2 \n"\
+ " cpsid i \n"\
+ " msr basepri, %1 \n"\
+ " isb \n"\
+ " dsb \n"\
+ " cpsie i \n"\
+ : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+ );
+
+ /* This return will not be reached but is necessary to prevent compiler
+ * warnings. */
+ return ulOriginalBASEPRI;
+ }
+/*-----------------------------------------------------------*/
+
+ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
+ {
+ __asm volatile
+ (
+ " msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+
+ #ifdef __cplusplus
+ }
+ #endif
+
+#endif /* PORTMACRO_H */
diff --git a/portable/GCC/ARM_CM85/non_secure/portasm.c b/portable/GCC/ARM_CM85/non_secure/portasm.c
index 1e4f0c9..9f9b2e6 100644
--- a/portable/GCC/ARM_CM85/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM85/non_secure/portasm.c
@@ -1,470 +1,470 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/* Standard includes. */
-#include <stdint.h>
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
- * is defined correctly and privileged functions are placed in correct sections. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Portasm includes. */
-#include "portasm.h"
-
-/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
- * header files. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " ldr r2, pxCurrentTCBConst2 \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r3, [r2] \n"/* Read pxCurrentTCB. */
- " ldr r0, [r3] \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
- " \n"
- #if ( configENABLE_MPU == 1 )
- " dmb \n"/* Complete outstanding transfers before disabling MPU. */
- " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
- " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
- " bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
- " str r4, [r2] \n"/* Disable MPU. */
- " \n"
- " adds r3, #4 \n"/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
- " ldr r4, [r3] \n"/* r4 = *r3 i.e. r4 = MAIR0. */
- " ldr r2, xMAIR0Const2 \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
- " str r4, [r2] \n"/* Program MAIR0. */
- " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
- " movs r4, #4 \n"/* r4 = 4. */
- " str r4, [r2] \n"/* Program RNR = 4. */
- " adds r3, #4 \n"/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
- " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
- " ldmia r3!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
- " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
- " \n"
- #if ( configTOTAL_MPU_REGIONS == 16 )
- " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
- " movs r4, #8 \n"/* r4 = 8. */
- " str r4, [r2] \n"/* Program RNR = 8. */
- " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
- " ldmia r3!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
- " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
- " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
- " movs r4, #12 \n"/* r4 = 12. */
- " str r4, [r2] \n"/* Program RNR = 12. */
- " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
- " ldmia r3!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
- " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
- #endif /* configTOTAL_MPU_REGIONS == 16 */
- " \n"
- " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
- " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
- " orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
- " str r4, [r2] \n"/* Enable MPU. */
- " dsb \n"/* Force memory writes before continuing. */
- #endif /* configENABLE_MPU */
- " \n"
- #if ( configENABLE_MPU == 1 )
- " ldm r0!, {r1-r4} \n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
- " ldr r5, xSecureContextConst2 \n"
- " str r1, [r5] \n"/* Set xSecureContext to this task's value for the same. */
- " msr psplim, r2 \n"/* Set this task's PSPLIM value. */
- " msr control, r3 \n"/* Set this task's CONTROL value. */
- " adds r0, #32 \n"/* Discard everything up to r0. */
- " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
- " isb \n"
- " mov r0, #0 \n"
- " msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */
- " bx r4 \n"/* Finally, branch to EXC_RETURN. */
- #else /* configENABLE_MPU */
- " ldm r0!, {r1-r3} \n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
- " ldr r4, xSecureContextConst2 \n"
- " str r1, [r4] \n"/* Set xSecureContext to this task's value for the same. */
- " msr psplim, r2 \n"/* Set this task's PSPLIM value. */
- " movs r1, #2 \n"/* r1 = 2. */
- " msr CONTROL, r1 \n"/* Switch to use PSP in the thread mode. */
- " adds r0, #32 \n"/* Discard everything up to r0. */
- " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
- " isb \n"
- " mov r0, #0 \n"
- " msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */
- " bx r3 \n"/* Finally, branch to EXC_RETURN. */
- #endif /* configENABLE_MPU */
- " \n"
- " .align 4 \n"
- "pxCurrentTCBConst2: .word pxCurrentTCB \n"
- "xSecureContextConst2: .word xSecureContext \n"
- #if ( configENABLE_MPU == 1 )
- "xMPUCTRLConst2: .word 0xe000ed94 \n"
- "xMAIR0Const2: .word 0xe000edc0 \n"
- "xRNRConst2: .word 0xe000ed98 \n"
- "xRBARConst2: .word 0xe000ed9c \n"
- #endif /* configENABLE_MPU */
- );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " mrs r0, control \n"/* r0 = CONTROL. */
- " tst r0, #1 \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
- " ite ne \n"
- " movne r0, #0 \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
- " moveq r0, #1 \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
- " bx lr \n"/* Return. */
- " \n"
- " .align 4 \n"
- ::: "r0", "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " mrs r0, control \n"/* Read the CONTROL register. */
- " bic r0, #1 \n"/* Clear the bit 0. */
- " msr control, r0 \n"/* Write back the new CONTROL value. */
- " bx lr \n"/* Return to the caller. */
- ::: "r0", "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-void vResetPrivilege( void ) /* __attribute__ (( naked )) */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " mrs r0, control \n"/* r0 = CONTROL. */
- " orr r0, #1 \n"/* r0 = r0 | 1. */
- " msr control, r0 \n"/* CONTROL = r0. */
- " bx lr \n"/* Return to the caller. */
- ::: "r0", "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " ldr r0, xVTORConst \n"/* Use the NVIC offset register to locate the stack. */
- " ldr r0, [r0] \n"/* Read the VTOR register which gives the address of vector table. */
- " ldr r0, [r0] \n"/* The first entry in vector table is stack pointer. */
- " msr msp, r0 \n"/* Set the MSP back to the start of the stack. */
- " cpsie i \n"/* Globally enable interrupts. */
- " cpsie f \n"
- " dsb \n"
- " isb \n"
- " svc %0 \n"/* System call to start the first task. */
- " nop \n"
- " \n"
- " .align 4 \n"
- "xVTORConst: .word 0xe000ed08 \n"
- ::"i" ( portSVC_START_SCHEDULER ) : "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " mrs r0, basepri \n"/* r0 = basepri. Return original basepri value. */
- " mov r1, %0 \n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- " msr basepri, r1 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- " dsb \n"
- " isb \n"
- " bx lr \n"/* Return. */
- ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " msr basepri, r0 \n"/* basepri = ulMask. */
- " dsb \n"
- " isb \n"
- " bx lr \n"/* Return. */
- ::: "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " .extern SecureContext_SaveContext \n"
- " .extern SecureContext_LoadContext \n"
- " \n"
- " ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
- " ldr r0, [r3] \n"/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
- " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r3] \n"/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
- " mrs r2, psp \n"/* Read PSP in r2. */
- " \n"
- " cbz r0, save_ns_context \n"/* No secure context to save. */
- " push {r0-r2, r14} \n"
- " bl SecureContext_SaveContext \n"/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
- " pop {r0-r3} \n"/* LR is now in r3. */
- " mov lr, r3 \n"/* LR = r3. */
- " lsls r1, r3, #25 \n"/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
- " bpl save_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
- " \n"
- " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r3] \n"/* Read pxCurrentTCB.*/
- #if ( configENABLE_MPU == 1 )
- " subs r2, r2, #16 \n"/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
- " str r2, [r1] \n"/* Save the new top of stack in TCB. */
- " mrs r1, psplim \n"/* r1 = PSPLIM. */
- " mrs r3, control \n"/* r3 = CONTROL. */
- " mov r4, lr \n"/* r4 = LR/EXC_RETURN. */
- " stmia r2!, {r0, r1, r3, r4} \n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
- #else /* configENABLE_MPU */
- " subs r2, r2, #12 \n"/* Make space for xSecureContext, PSPLIM and LR on the stack. */
- " str r2, [r1] \n"/* Save the new top of stack in TCB. */
- " mrs r1, psplim \n"/* r1 = PSPLIM. */
- " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */
- " stmia r2!, {r0, r1, r3} \n"/* Store xSecureContext, PSPLIM and LR on the stack. */
- #endif /* configENABLE_MPU */
- " b select_next_task \n"
- " \n"
- " save_ns_context: \n"
- " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r3] \n"/* Read pxCurrentTCB. */
- #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
- " tst lr, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
- " it eq \n"
- " vstmdbeq r2!, {s16-s31} \n"/* Store the additional FP context registers which are not saved automatically. */
- #endif /* configENABLE_FPU || configENABLE_MVE */
- #if ( configENABLE_MPU == 1 )
- " subs r2, r2, #48 \n"/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
- " str r2, [r1] \n"/* Save the new top of stack in TCB. */
- " adds r2, r2, #16 \n"/* r2 = r2 + 16. */
- " stm r2, {r4-r11} \n"/* Store the registers that are not saved automatically. */
- " mrs r1, psplim \n"/* r1 = PSPLIM. */
- " mrs r3, control \n"/* r3 = CONTROL. */
- " mov r4, lr \n"/* r4 = LR/EXC_RETURN. */
- " subs r2, r2, #16 \n"/* r2 = r2 - 16. */
- " stmia r2!, {r0, r1, r3, r4} \n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
- #else /* configENABLE_MPU */
- " subs r2, r2, #44 \n"/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
- " str r2, [r1] \n"/* Save the new top of stack in TCB. */
- " adds r2, r2, #12 \n"/* r2 = r2 + 12. */
- " stm r2, {r4-r11} \n"/* Store the registers that are not saved automatically. */
- " mrs r1, psplim \n"/* r1 = PSPLIM. */
- " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */
- " subs r2, r2, #12 \n"/* r2 = r2 - 12. */
- " stmia r2!, {r0, r1, r3} \n"/* Store xSecureContext, PSPLIM and LR on the stack. */
- #endif /* configENABLE_MPU */
- " \n"
- " select_next_task: \n"
- " mov r0, %0 \n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
- " msr basepri, r0 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- " dsb \n"
- " isb \n"
- " bl vTaskSwitchContext \n"
- " mov r0, #0 \n"/* r0 = 0. */
- " msr basepri, r0 \n"/* Enable interrupts. */
- " \n"
- " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r3] \n"/* Read pxCurrentTCB. */
- " ldr r2, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
- " \n"
- #if ( configENABLE_MPU == 1 )
- " dmb \n"/* Complete outstanding transfers before disabling MPU. */
- " ldr r3, xMPUCTRLConst \n"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */
- " ldr r4, [r3] \n"/* Read the value of MPU_CTRL. */
- " bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
- " str r4, [r3] \n"/* Disable MPU. */
- " \n"
- " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
- " ldr r4, [r1] \n"/* r4 = *r1 i.e. r4 = MAIR0. */
- " ldr r3, xMAIR0Const \n"/* r3 = 0xe000edc0 [Location of MAIR0]. */
- " str r4, [r3] \n"/* Program MAIR0. */
- " ldr r3, xRNRConst \n"/* r3 = 0xe000ed98 [Location of RNR]. */
- " movs r4, #4 \n"/* r4 = 4. */
- " str r4, [r3] \n"/* Program RNR = 4. */
- " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
- " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
- " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
- " stmia r3!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
- " \n"
- #if ( configTOTAL_MPU_REGIONS == 16 )
- " ldr r3, xRNRConst \n"/* r3 = 0xe000ed98 [Location of RNR]. */
- " movs r4, #8 \n"/* r4 = 8. */
- " str r4, [r3] \n"/* Program RNR = 8. */
- " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
- " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
- " stmia r3!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
- " ldr r3, xRNRConst \n"/* r3 = 0xe000ed98 [Location of RNR]. */
- " movs r4, #12 \n"/* r4 = 12. */
- " str r4, [r3] \n"/* Program RNR = 12. */
- " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
- " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
- " stmia r3!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
- #endif /* configTOTAL_MPU_REGIONS == 16 */
- " \n"
- " ldr r3, xMPUCTRLConst \n"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */
- " ldr r4, [r3] \n"/* Read the value of MPU_CTRL. */
- " orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
- " str r4, [r3] \n"/* Enable MPU. */
- " dsb \n"/* Force memory writes before continuing. */
- #endif /* configENABLE_MPU */
- " \n"
- #if ( configENABLE_MPU == 1 )
- " ldmia r2!, {r0, r1, r3, r4} \n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */
- " msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */
- " msr control, r3 \n"/* Restore the CONTROL register value for the task. */
- " mov lr, r4 \n"/* LR = r4. */
- " ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
- " str r0, [r3] \n"/* Restore the task's xSecureContext. */
- " cbz r0, restore_ns_context \n"/* If there is no secure context for the task, restore the non-secure context. */
- " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r3] \n"/* Read pxCurrentTCB. */
- " push {r2, r4} \n"
- " bl SecureContext_LoadContext \n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
- " pop {r2, r4} \n"
- " mov lr, r4 \n"/* LR = r4. */
- " lsls r1, r4, #25 \n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
- " bpl restore_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
- " msr psp, r2 \n"/* Remember the new top of stack for the task. */
- " bx lr \n"
- #else /* configENABLE_MPU */
- " ldmia r2!, {r0, r1, r4} \n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
- " msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */
- " mov lr, r4 \n"/* LR = r4. */
- " ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
- " str r0, [r3] \n"/* Restore the task's xSecureContext. */
- " cbz r0, restore_ns_context \n"/* If there is no secure context for the task, restore the non-secure context. */
- " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r3] \n"/* Read pxCurrentTCB. */
- " push {r2, r4} \n"
- " bl SecureContext_LoadContext \n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
- " pop {r2, r4} \n"
- " mov lr, r4 \n"/* LR = r4. */
- " lsls r1, r4, #25 \n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
- " bpl restore_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
- " msr psp, r2 \n"/* Remember the new top of stack for the task. */
- " bx lr \n"
- #endif /* configENABLE_MPU */
- " \n"
- " restore_ns_context: \n"
- " ldmia r2!, {r4-r11} \n"/* Restore the registers that are not automatically restored. */
- #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
- " tst lr, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
- " it eq \n"
- " vldmiaeq r2!, {s16-s31} \n"/* Restore the additional FP context registers which are not restored automatically. */
- #endif /* configENABLE_FPU || configENABLE_MVE */
- " msr psp, r2 \n"/* Remember the new top of stack for the task. */
- " bx lr \n"
- " \n"
- " .align 4 \n"
- "pxCurrentTCBConst: .word pxCurrentTCB \n"
- "xSecureContextConst: .word xSecureContext \n"
- #if ( configENABLE_MPU == 1 )
- "xMPUCTRLConst: .word 0xe000ed94 \n"
- "xMAIR0Const: .word 0xe000edc0 \n"
- "xRNRConst: .word 0xe000ed98 \n"
- "xRBARConst: .word 0xe000ed9c \n"
- #endif /* configENABLE_MPU */
- ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
- );
-}
-/*-----------------------------------------------------------*/
-
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " tst lr, #4 \n"
- " ite eq \n"
- " mrseq r0, msp \n"
- " mrsne r0, psp \n"
- " ldr r1, svchandler_address_const \n"
- " bx r1 \n"
- " \n"
- " .align 4 \n"
- "svchandler_address_const: .word vPortSVCHandler_C \n"
- );
-}
-/*-----------------------------------------------------------*/
-
-void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " svc %0 \n"/* Secure context is allocated in the supervisor call. */
- " bx lr \n"/* Return. */
- ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " ldr r2, [r0] \n"/* The first item in the TCB is the top of the stack. */
- " ldr r1, [r2] \n"/* The first item on the stack is the task's xSecureContext. */
- " cmp r1, #0 \n"/* Raise svc if task's xSecureContext is not NULL. */
- " it ne \n"
- " svcne %0 \n"/* Secure context is freed in the supervisor call. */
- " bx lr \n"/* Return. */
- ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
- );
-}
-/*-----------------------------------------------------------*/
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
+ * is defined correctly and privileged functions are placed in correct sections. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Portasm includes. */
+#include "portasm.h"
+
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
+ * header files. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " ldr r2, pxCurrentTCBConst2 \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r3, [r2] \n"/* Read pxCurrentTCB. */
+ " ldr r0, [r3] \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+ " \n"
+ #if ( configENABLE_MPU == 1 )
+ " dmb \n"/* Complete outstanding transfers before disabling MPU. */
+ " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
+ " bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+ " str r4, [r2] \n"/* Disable MPU. */
+ " \n"
+ " adds r3, #4 \n"/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+ " ldr r4, [r3] \n"/* r4 = *r3 i.e. r4 = MAIR0. */
+ " ldr r2, xMAIR0Const2 \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
+ " str r4, [r2] \n"/* Program MAIR0. */
+ " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
+ " movs r4, #4 \n"/* r4 = 4. */
+ " str r4, [r2] \n"/* Program RNR = 4. */
+ " adds r3, #4 \n"/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+ " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r3!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
+ " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+ " \n"
+ #if ( configTOTAL_MPU_REGIONS == 16 )
+ " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
+ " movs r4, #8 \n"/* r4 = 8. */
+ " str r4, [r2] \n"/* Program RNR = 8. */
+ " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r3!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
+ " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+ " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
+ " movs r4, #12 \n"/* r4 = 12. */
+ " str r4, [r2] \n"/* Program RNR = 12. */
+ " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r3!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
+ " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+ #endif /* configTOTAL_MPU_REGIONS == 16 */
+ " \n"
+ " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
+ " orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+ " str r4, [r2] \n"/* Enable MPU. */
+ " dsb \n"/* Force memory writes before continuing. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ #if ( configENABLE_MPU == 1 )
+ " ldm r0!, {r1-r4} \n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
+ " ldr r5, xSecureContextConst2 \n"
+ " str r1, [r5] \n"/* Set xSecureContext to this task's value for the same. */
+ " msr psplim, r2 \n"/* Set this task's PSPLIM value. */
+ " msr control, r3 \n"/* Set this task's CONTROL value. */
+ " adds r0, #32 \n"/* Discard everything up to r0. */
+ " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
+ " isb \n"
+ " mov r0, #0 \n"
+ " msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */
+ " bx r4 \n"/* Finally, branch to EXC_RETURN. */
+ #else /* configENABLE_MPU */
+ " ldm r0!, {r1-r3} \n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
+ " ldr r4, xSecureContextConst2 \n"
+ " str r1, [r4] \n"/* Set xSecureContext to this task's value for the same. */
+ " msr psplim, r2 \n"/* Set this task's PSPLIM value. */
+ " movs r1, #2 \n"/* r1 = 2. */
+ " msr CONTROL, r1 \n"/* Switch to use PSP in the thread mode. */
+ " adds r0, #32 \n"/* Discard everything up to r0. */
+ " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
+ " isb \n"
+ " mov r0, #0 \n"
+ " msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */
+ " bx r3 \n"/* Finally, branch to EXC_RETURN. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ " .align 4 \n"
+ "pxCurrentTCBConst2: .word pxCurrentTCB \n"
+ "xSecureContextConst2: .word xSecureContext \n"
+ #if ( configENABLE_MPU == 1 )
+ "xMPUCTRLConst2: .word 0xe000ed94 \n"
+ "xMAIR0Const2: .word 0xe000edc0 \n"
+ "xRNRConst2: .word 0xe000ed98 \n"
+ "xRBARConst2: .word 0xe000ed9c \n"
+ #endif /* configENABLE_MPU */
+ );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, control \n"/* r0 = CONTROL. */
+ " tst r0, #1 \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+ " ite ne \n"
+ " movne r0, #0 \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+ " moveq r0, #1 \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+ " bx lr \n"/* Return. */
+ " \n"
+ " .align 4 \n"
+ ::: "r0", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, control \n"/* Read the CONTROL register. */
+ " bic r0, #1 \n"/* Clear the bit 0. */
+ " msr control, r0 \n"/* Write back the new CONTROL value. */
+ " bx lr \n"/* Return to the caller. */
+ ::: "r0", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, control \n"/* r0 = CONTROL. */
+ " orr r0, #1 \n"/* r0 = r0 | 1. */
+ " msr control, r0 \n"/* CONTROL = r0. */
+ " bx lr \n"/* Return to the caller. */
+ ::: "r0", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " ldr r0, xVTORConst \n"/* Use the NVIC offset register to locate the stack. */
+ " ldr r0, [r0] \n"/* Read the VTOR register which gives the address of vector table. */
+ " ldr r0, [r0] \n"/* The first entry in vector table is stack pointer. */
+ " msr msp, r0 \n"/* Set the MSP back to the start of the stack. */
+ " cpsie i \n"/* Globally enable interrupts. */
+ " cpsie f \n"
+ " dsb \n"
+ " isb \n"
+ " svc %0 \n"/* System call to start the first task. */
+ " nop \n"
+ " \n"
+ " .align 4 \n"
+ "xVTORConst: .word 0xe000ed08 \n"
+ ::"i" ( portSVC_START_SCHEDULER ) : "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, basepri \n"/* r0 = basepri. Return original basepri value. */
+ " mov r1, %0 \n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " msr basepri, r1 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " dsb \n"
+ " isb \n"
+ " bx lr \n"/* Return. */
+ ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " msr basepri, r0 \n"/* basepri = ulMask. */
+ " dsb \n"
+ " isb \n"
+ " bx lr \n"/* Return. */
+ ::: "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern SecureContext_SaveContext \n"
+ " .extern SecureContext_LoadContext \n"
+ " \n"
+ " ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ " ldr r0, [r3] \n"/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+ " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r3] \n"/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
+ " mrs r2, psp \n"/* Read PSP in r2. */
+ " \n"
+ " cbz r0, save_ns_context \n"/* No secure context to save. */
+ " push {r0-r2, r14} \n"
+ " bl SecureContext_SaveContext \n"/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+ " pop {r0-r3} \n"/* LR is now in r3. */
+ " mov lr, r3 \n"/* LR = r3. */
+ " lsls r1, r3, #25 \n"/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+ " bpl save_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+ " \n"
+ " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r3] \n"/* Read pxCurrentTCB.*/
+ #if ( configENABLE_MPU == 1 )
+ " subs r2, r2, #16 \n"/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+ " str r2, [r1] \n"/* Save the new top of stack in TCB. */
+ " mrs r1, psplim \n"/* r1 = PSPLIM. */
+ " mrs r3, control \n"/* r3 = CONTROL. */
+ " mov r4, lr \n"/* r4 = LR/EXC_RETURN. */
+ " stmia r2!, {r0, r1, r3, r4} \n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+ #else /* configENABLE_MPU */
+ " subs r2, r2, #12 \n"/* Make space for xSecureContext, PSPLIM and LR on the stack. */
+ " str r2, [r1] \n"/* Save the new top of stack in TCB. */
+ " mrs r1, psplim \n"/* r1 = PSPLIM. */
+ " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */
+ " stmia r2!, {r0, r1, r3} \n"/* Store xSecureContext, PSPLIM and LR on the stack. */
+ #endif /* configENABLE_MPU */
+ " b select_next_task \n"
+ " \n"
+ " save_ns_context: \n"
+ " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r3] \n"/* Read pxCurrentTCB. */
+ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ " tst lr, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+ " it eq \n"
+ " vstmdbeq r2!, {s16-s31} \n"/* Store the additional FP context registers which are not saved automatically. */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
+ #if ( configENABLE_MPU == 1 )
+ " subs r2, r2, #48 \n"/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+ " str r2, [r1] \n"/* Save the new top of stack in TCB. */
+ " adds r2, r2, #16 \n"/* r2 = r2 + 16. */
+ " stm r2, {r4-r11} \n"/* Store the registers that are not saved automatically. */
+ " mrs r1, psplim \n"/* r1 = PSPLIM. */
+ " mrs r3, control \n"/* r3 = CONTROL. */
+ " mov r4, lr \n"/* r4 = LR/EXC_RETURN. */
+ " subs r2, r2, #16 \n"/* r2 = r2 - 16. */
+ " stmia r2!, {r0, r1, r3, r4} \n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+ #else /* configENABLE_MPU */
+ " subs r2, r2, #44 \n"/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+ " str r2, [r1] \n"/* Save the new top of stack in TCB. */
+ " adds r2, r2, #12 \n"/* r2 = r2 + 12. */
+ " stm r2, {r4-r11} \n"/* Store the registers that are not saved automatically. */
+ " mrs r1, psplim \n"/* r1 = PSPLIM. */
+ " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */
+ " subs r2, r2, #12 \n"/* r2 = r2 - 12. */
+ " stmia r2!, {r0, r1, r3} \n"/* Store xSecureContext, PSPLIM and LR on the stack. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ " select_next_task: \n"
+ " mov r0, %0 \n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+ " msr basepri, r0 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " dsb \n"
+ " isb \n"
+ " bl vTaskSwitchContext \n"
+ " mov r0, #0 \n"/* r0 = 0. */
+ " msr basepri, r0 \n"/* Enable interrupts. */
+ " \n"
+ " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r3] \n"/* Read pxCurrentTCB. */
+ " ldr r2, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
+ " \n"
+ #if ( configENABLE_MPU == 1 )
+ " dmb \n"/* Complete outstanding transfers before disabling MPU. */
+ " ldr r3, xMPUCTRLConst \n"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r4, [r3] \n"/* Read the value of MPU_CTRL. */
+ " bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+ " str r4, [r3] \n"/* Disable MPU. */
+ " \n"
+ " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+ " ldr r4, [r1] \n"/* r4 = *r1 i.e. r4 = MAIR0. */
+ " ldr r3, xMAIR0Const \n"/* r3 = 0xe000edc0 [Location of MAIR0]. */
+ " str r4, [r3] \n"/* Program MAIR0. */
+ " ldr r3, xRNRConst \n"/* r3 = 0xe000ed98 [Location of RNR]. */
+ " movs r4, #4 \n"/* r4 = 4. */
+ " str r4, [r3] \n"/* Program RNR = 4. */
+ " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+ " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
+ " stmia r3!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+ " \n"
+ #if ( configTOTAL_MPU_REGIONS == 16 )
+ " ldr r3, xRNRConst \n"/* r3 = 0xe000ed98 [Location of RNR]. */
+ " movs r4, #8 \n"/* r4 = 8. */
+ " str r4, [r3] \n"/* Program RNR = 8. */
+ " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
+ " stmia r3!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+ " ldr r3, xRNRConst \n"/* r3 = 0xe000ed98 [Location of RNR]. */
+ " movs r4, #12 \n"/* r4 = 12. */
+ " str r4, [r3] \n"/* Program RNR = 12. */
+ " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
+ " stmia r3!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+ #endif /* configTOTAL_MPU_REGIONS == 16 */
+ " \n"
+ " ldr r3, xMPUCTRLConst \n"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r4, [r3] \n"/* Read the value of MPU_CTRL. */
+ " orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+ " str r4, [r3] \n"/* Enable MPU. */
+ " dsb \n"/* Force memory writes before continuing. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ #if ( configENABLE_MPU == 1 )
+ " ldmia r2!, {r0, r1, r3, r4} \n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */
+ " msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */
+ " msr control, r3 \n"/* Restore the CONTROL register value for the task. */
+ " mov lr, r4 \n"/* LR = r4. */
+ " ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ " str r0, [r3] \n"/* Restore the task's xSecureContext. */
+ " cbz r0, restore_ns_context \n"/* If there is no secure context for the task, restore the non-secure context. */
+ " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r3] \n"/* Read pxCurrentTCB. */
+ " push {r2, r4} \n"
+ " bl SecureContext_LoadContext \n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+ " pop {r2, r4} \n"
+ " mov lr, r4 \n"/* LR = r4. */
+ " lsls r1, r4, #25 \n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+ " bpl restore_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+ " msr psp, r2 \n"/* Remember the new top of stack for the task. */
+ " bx lr \n"
+ #else /* configENABLE_MPU */
+ " ldmia r2!, {r0, r1, r4} \n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
+ " msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */
+ " mov lr, r4 \n"/* LR = r4. */
+ " ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ " str r0, [r3] \n"/* Restore the task's xSecureContext. */
+ " cbz r0, restore_ns_context \n"/* If there is no secure context for the task, restore the non-secure context. */
+ " ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r3] \n"/* Read pxCurrentTCB. */
+ " push {r2, r4} \n"
+ " bl SecureContext_LoadContext \n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+ " pop {r2, r4} \n"
+ " mov lr, r4 \n"/* LR = r4. */
+ " lsls r1, r4, #25 \n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+ " bpl restore_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+ " msr psp, r2 \n"/* Remember the new top of stack for the task. */
+ " bx lr \n"
+ #endif /* configENABLE_MPU */
+ " \n"
+ " restore_ns_context: \n"
+ " ldmia r2!, {r4-r11} \n"/* Restore the registers that are not automatically restored. */
+ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ " tst lr, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+ " it eq \n"
+ " vldmiaeq r2!, {s16-s31} \n"/* Restore the additional FP context registers which are not restored automatically. */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
+ " msr psp, r2 \n"/* Remember the new top of stack for the task. */
+ " bx lr \n"
+ " \n"
+ " .align 4 \n"
+ "pxCurrentTCBConst: .word pxCurrentTCB \n"
+ "xSecureContextConst: .word xSecureContext \n"
+ #if ( configENABLE_MPU == 1 )
+ "xMPUCTRLConst: .word 0xe000ed94 \n"
+ "xMAIR0Const: .word 0xe000edc0 \n"
+ "xRNRConst: .word 0xe000ed98 \n"
+ "xRBARConst: .word 0xe000ed9c \n"
+ #endif /* configENABLE_MPU */
+ ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+ );
+}
+/*-----------------------------------------------------------*/
+
+void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " tst lr, #4 \n"
+ " ite eq \n"
+ " mrseq r0, msp \n"
+ " mrsne r0, psp \n"
+ " ldr r1, svchandler_address_const \n"
+ " bx r1 \n"
+ " \n"
+ " .align 4 \n"
+ "svchandler_address_const: .word vPortSVCHandler_C \n"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " svc %0 \n"/* Secure context is allocated in the supervisor call. */
+ " bx lr \n"/* Return. */
+ ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " ldr r2, [r0] \n"/* The first item in the TCB is the top of the stack. */
+ " ldr r1, [r2] \n"/* The first item on the stack is the task's xSecureContext. */
+ " cmp r1, #0 \n"/* Raise svc if task's xSecureContext is not NULL. */
+ " it ne \n"
+ " svcne %0 \n"/* Secure context is freed in the supervisor call. */
+ " bx lr \n"/* Return. */
+ ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
+ );
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM85/non_secure/portasm.h b/portable/GCC/ARM_CM85/non_secure/portasm.h
index b37f6d1..ecd86b9 100644
--- a/portable/GCC/ARM_CM85/non_secure/portasm.h
+++ b/portable/GCC/ARM_CM85/non_secure/portasm.h
@@ -1,114 +1,114 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef __PORT_ASM_H__
-#define __PORT_ASM_H__
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-
-/* MPU wrappers includes. */
-#include "mpu_wrappers.h"
-
-/**
- * @brief Restore the context of the first task so that the first task starts
- * executing.
- */
-void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
-BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
-
-/**
- * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
- * register.
- *
- * @note This is a privileged function and should only be called from the kenrel
- * code.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- * Bit[0] = 0 --> The processor is running privileged
- * Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- * Bit[0] = 0 --> The processor is running privileged
- * Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vResetPrivilege( void ) __attribute__( ( naked ) );
-
-/**
- * @brief Starts the first task.
- */
-void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Disables interrupts.
- */
-uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Enables interrupts.
- */
-void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief PendSV Exception handler.
- */
-void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief SVC Handler.
- */
-void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Allocate a Secure context for the calling task.
- *
- * @param[in] ulSecureStackSize The size of the stack to be allocated on the
- * secure side for the calling task.
- */
-void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );
-
-/**
- * @brief Free the task's secure context.
- *
- * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
- */
-void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-#endif /* __PORT_ASM_H__ */
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
index 4b1f99b..51e21ea 100644
--- a/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
@@ -155,9 +155,9 @@
* 8-bit values encoded as follows:
* Bit[7:4] - 0000 - Device Memory
* Bit[3:2] - 00 --> Device-nGnRnE
- * 01 --> Device-nGnRE
- * 10 --> Device-nGRE
- * 11 --> Device-GRE
+ * 01 --> Device-nGnRE
+ * 10 --> Device-nGRE
+ * 11 --> Device-GRE
* Bit[1:0] - 00, Reserved.
*/
#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
diff --git a/portable/GCC/ARM_CM85/secure/secure_context.c b/portable/GCC/ARM_CM85/secure/secure_context.c
index b1d5503..0730d57 100644
--- a/portable/GCC/ARM_CM85/secure/secure_context.c
+++ b/portable/GCC/ARM_CM85/secure/secure_context.c
@@ -1,351 +1,351 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/* Secure context includes. */
-#include "secure_context.h"
-
-/* Secure heap includes. */
-#include "secure_heap.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/**
- * @brief CONTROL value for privileged tasks.
- *
- * Bit[0] - 0 --> Thread mode is privileged.
- * Bit[1] - 1 --> Thread mode uses PSP.
- */
-#define securecontextCONTROL_VALUE_PRIVILEGED 0x02
-
-/**
- * @brief CONTROL value for un-privileged tasks.
- *
- * Bit[0] - 1 --> Thread mode is un-privileged.
- * Bit[1] - 1 --> Thread mode uses PSP.
- */
-#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03
-
-/**
- * @brief Size of stack seal values in bytes.
- */
-#define securecontextSTACK_SEAL_SIZE 8
-
-/**
- * @brief Stack seal value as recommended by ARM.
- */
-#define securecontextSTACK_SEAL_VALUE 0xFEF5EDA5
-
-/**
- * @brief Maximum number of secure contexts.
- */
-#ifndef secureconfigMAX_SECURE_CONTEXTS
- #define secureconfigMAX_SECURE_CONTEXTS 8UL
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Pre-allocated array of secure contexts.
- */
-SecureContext_t xSecureContexts[ secureconfigMAX_SECURE_CONTEXTS ];
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Get a free secure context for a task from the secure context pool (xSecureContexts).
- *
- * This function ensures that only one secure context is allocated for a task.
- *
- * @param[in] pvTaskHandle The task handle for which the secure context is allocated.
- *
- * @return Index of a free secure context in the xSecureContexts array.
- */
-static uint32_t ulGetSecureContext( void * pvTaskHandle );
-
-/**
- * @brief Return the secure context to the secure context pool (xSecureContexts).
- *
- * @param[in] ulSecureContextIndex Index of the context in the xSecureContexts array.
- */
-static void vReturnSecureContext( uint32_t ulSecureContextIndex );
-
-/* These are implemented in assembly. */
-extern void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext );
-extern void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext );
-/*-----------------------------------------------------------*/
-
-static uint32_t ulGetSecureContext( void * pvTaskHandle )
-{
- /* Start with invalid index. */
- uint32_t i, ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS;
-
- for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ )
- {
- if( ( xSecureContexts[ i ].pucCurrentStackPointer == NULL ) &&
- ( xSecureContexts[ i ].pucStackLimit == NULL ) &&
- ( xSecureContexts[ i ].pucStackStart == NULL ) &&
- ( xSecureContexts[ i ].pvTaskHandle == NULL ) &&
- ( ulSecureContextIndex == secureconfigMAX_SECURE_CONTEXTS ) )
- {
- ulSecureContextIndex = i;
- }
- else if( xSecureContexts[ i ].pvTaskHandle == pvTaskHandle )
- {
- /* A task can only have one secure context. Do not allocate a second
- * context for the same task. */
- ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS;
- break;
- }
- }
-
- return ulSecureContextIndex;
-}
-/*-----------------------------------------------------------*/
-
-static void vReturnSecureContext( uint32_t ulSecureContextIndex )
-{
- xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = NULL;
- xSecureContexts[ ulSecureContextIndex ].pucStackLimit = NULL;
- xSecureContexts[ ulSecureContextIndex ].pucStackStart = NULL;
- xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = NULL;
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
-{
- uint32_t ulIPSR, i;
- static uint32_t ulSecureContextsInitialized = 0;
-
- /* Read the Interrupt Program Status Register (IPSR) value. */
- secureportREAD_IPSR( ulIPSR );
-
- /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
- * when the processor is running in the Thread Mode. */
- if( ( ulIPSR != 0 ) && ( ulSecureContextsInitialized == 0 ) )
- {
- /* Ensure to initialize secure contexts only once. */
- ulSecureContextsInitialized = 1;
-
- /* No stack for thread mode until a task's context is loaded. */
- secureportSET_PSPLIM( securecontextNO_STACK );
- secureportSET_PSP( securecontextNO_STACK );
-
- /* Initialize all secure contexts. */
- for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ )
- {
- xSecureContexts[ i ].pucCurrentStackPointer = NULL;
- xSecureContexts[ i ].pucStackLimit = NULL;
- xSecureContexts[ i ].pucStackStart = NULL;
- xSecureContexts[ i ].pvTaskHandle = NULL;
- }
-
- #if ( configENABLE_MPU == 1 )
- {
- /* Configure thread mode to use PSP and to be unprivileged. */
- secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
- }
- #else /* configENABLE_MPU */
- {
- /* Configure thread mode to use PSP and to be privileged. */
- secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
- }
- #endif /* configENABLE_MPU */
- }
-}
-/*-----------------------------------------------------------*/
-
-#if ( configENABLE_MPU == 1 )
- secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
- uint32_t ulIsTaskPrivileged,
- void * pvTaskHandle )
-#else /* configENABLE_MPU */
- secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
- void * pvTaskHandle )
-#endif /* configENABLE_MPU */
-{
- uint8_t * pucStackMemory = NULL;
- uint8_t * pucStackLimit;
- uint32_t ulIPSR, ulSecureContextIndex;
- SecureContextHandle_t xSecureContextHandle = securecontextINVALID_CONTEXT_ID;
-
- #if ( configENABLE_MPU == 1 )
- uint32_t * pulCurrentStackPointer = NULL;
- #endif /* configENABLE_MPU */
-
- /* Read the Interrupt Program Status Register (IPSR) and Process Stack Limit
- * Register (PSPLIM) value. */
- secureportREAD_IPSR( ulIPSR );
- secureportREAD_PSPLIM( pucStackLimit );
-
- /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
- * when the processor is running in the Thread Mode.
- * Also do nothing, if a secure context us already loaded. PSPLIM is set to
- * securecontextNO_STACK when no secure context is loaded. */
- if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )
- {
- /* Ontain a free secure context. */
- ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );
-
- /* Were we able to get a free context? */
- if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS )
- {
- /* Allocate the stack space. */
- pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE );
-
- if( pucStackMemory != NULL )
- {
- /* Since stack grows down, the starting point will be the last
- * location. Note that this location is next to the last
- * allocated byte for stack (excluding the space for seal values)
- * because the hardware decrements the stack pointer before
- * writing i.e. if stack pointer is 0x2, a push operation will
- * decrement the stack pointer to 0x1 and then write at 0x1. */
- xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize;
-
- /* Seal the created secure process stack. */
- *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
- *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
-
- /* The stack cannot go beyond this location. This value is
- * programmed in the PSPLIM register on context switch.*/
- xSecureContexts[ ulSecureContextIndex ].pucStackLimit = pucStackMemory;
-
- xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle;
-
- #if ( configENABLE_MPU == 1 )
- {
- /* Store the correct CONTROL value for the task on the stack.
- * This value is programmed in the CONTROL register on
- * context switch. */
- pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
- pulCurrentStackPointer--;
-
- if( ulIsTaskPrivileged )
- {
- *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
- }
- else
- {
- *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
- }
-
- /* Store the current stack pointer. This value is programmed in
- * the PSP register on context switch. */
- xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
- }
- #else /* configENABLE_MPU */
- {
- /* Current SP is set to the starting of the stack. This
- * value programmed in the PSP register on context switch. */
- xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
- }
- #endif /* configENABLE_MPU */
-
- /* Ensure to never return 0 as a valid context handle. */
- xSecureContextHandle = ulSecureContextIndex + 1UL;
- }
- }
- }
-
- return xSecureContextHandle;
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
-{
- uint32_t ulIPSR, ulSecureContextIndex;
-
- /* Read the Interrupt Program Status Register (IPSR) value. */
- secureportREAD_IPSR( ulIPSR );
-
- /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
- * when the processor is running in the Thread Mode. */
- if( ulIPSR != 0 )
- {
- /* Only free if a valid context handle is passed. */
- if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )
- {
- ulSecureContextIndex = xSecureContextHandle - 1UL;
-
- /* Ensure that the secure context being deleted is associated with
- * the task. */
- if( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle )
- {
- /* Free the stack space. */
- vPortFree( xSecureContexts[ ulSecureContextIndex ].pucStackLimit );
-
- /* Return the secure context back to the free secure contexts pool. */
- vReturnSecureContext( ulSecureContextIndex );
- }
- }
- }
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
-{
- uint8_t * pucStackLimit;
- uint32_t ulSecureContextIndex;
-
- if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )
- {
- ulSecureContextIndex = xSecureContextHandle - 1UL;
-
- secureportREAD_PSPLIM( pucStackLimit );
-
- /* Ensure that no secure context is loaded and the task is loading it's
- * own context. */
- if( ( pucStackLimit == securecontextNO_STACK ) &&
- ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )
- {
- SecureContext_LoadContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) );
- }
- }
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
-{
- uint8_t * pucStackLimit;
- uint32_t ulSecureContextIndex;
-
- if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )
- {
- ulSecureContextIndex = xSecureContextHandle - 1UL;
-
- secureportREAD_PSPLIM( pucStackLimit );
-
- /* Ensure that task's context is loaded and the task is saving it's own
- * context. */
- if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) &&
- ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )
- {
- SecureContext_SaveContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) );
- }
- }
-}
-/*-----------------------------------------------------------*/
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief CONTROL value for privileged tasks.
+ *
+ * Bit[0] - 0 --> Thread mode is privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_PRIVILEGED 0x02
+
+/**
+ * @brief CONTROL value for un-privileged tasks.
+ *
+ * Bit[0] - 1 --> Thread mode is un-privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03
+
+/**
+ * @brief Size of stack seal values in bytes.
+ */
+#define securecontextSTACK_SEAL_SIZE 8
+
+/**
+ * @brief Stack seal value as recommended by ARM.
+ */
+#define securecontextSTACK_SEAL_VALUE 0xFEF5EDA5
+
+/**
+ * @brief Maximum number of secure contexts.
+ */
+#ifndef secureconfigMAX_SECURE_CONTEXTS
+ #define secureconfigMAX_SECURE_CONTEXTS 8UL
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Pre-allocated array of secure contexts.
+ */
+SecureContext_t xSecureContexts[ secureconfigMAX_SECURE_CONTEXTS ];
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Get a free secure context for a task from the secure context pool (xSecureContexts).
+ *
+ * This function ensures that only one secure context is allocated for a task.
+ *
+ * @param[in] pvTaskHandle The task handle for which the secure context is allocated.
+ *
+ * @return Index of a free secure context in the xSecureContexts array.
+ */
+static uint32_t ulGetSecureContext( void * pvTaskHandle );
+
+/**
+ * @brief Return the secure context to the secure context pool (xSecureContexts).
+ *
+ * @param[in] ulSecureContextIndex Index of the context in the xSecureContexts array.
+ */
+static void vReturnSecureContext( uint32_t ulSecureContextIndex );
+
+/* These are implemented in assembly. */
+extern void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext );
+extern void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext );
+/*-----------------------------------------------------------*/
+
+static uint32_t ulGetSecureContext( void * pvTaskHandle )
+{
+ /* Start with invalid index. */
+ uint32_t i, ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS;
+
+ for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ )
+ {
+ if( ( xSecureContexts[ i ].pucCurrentStackPointer == NULL ) &&
+ ( xSecureContexts[ i ].pucStackLimit == NULL ) &&
+ ( xSecureContexts[ i ].pucStackStart == NULL ) &&
+ ( xSecureContexts[ i ].pvTaskHandle == NULL ) &&
+ ( ulSecureContextIndex == secureconfigMAX_SECURE_CONTEXTS ) )
+ {
+ ulSecureContextIndex = i;
+ }
+ else if( xSecureContexts[ i ].pvTaskHandle == pvTaskHandle )
+ {
+ /* A task can only have one secure context. Do not allocate a second
+ * context for the same task. */
+ ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS;
+ break;
+ }
+ }
+
+ return ulSecureContextIndex;
+}
+/*-----------------------------------------------------------*/
+
+static void vReturnSecureContext( uint32_t ulSecureContextIndex )
+{
+ xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = NULL;
+ xSecureContexts[ ulSecureContextIndex ].pucStackLimit = NULL;
+ xSecureContexts[ ulSecureContextIndex ].pucStackStart = NULL;
+ xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = NULL;
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
+{
+ uint32_t ulIPSR, i;
+ static uint32_t ulSecureContextsInitialized = 0;
+
+ /* Read the Interrupt Program Status Register (IPSR) value. */
+ secureportREAD_IPSR( ulIPSR );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode. */
+ if( ( ulIPSR != 0 ) && ( ulSecureContextsInitialized == 0 ) )
+ {
+ /* Ensure to initialize secure contexts only once. */
+ ulSecureContextsInitialized = 1;
+
+ /* No stack for thread mode until a task's context is loaded. */
+ secureportSET_PSPLIM( securecontextNO_STACK );
+ secureportSET_PSP( securecontextNO_STACK );
+
+ /* Initialize all secure contexts. */
+ for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ )
+ {
+ xSecureContexts[ i ].pucCurrentStackPointer = NULL;
+ xSecureContexts[ i ].pucStackLimit = NULL;
+ xSecureContexts[ i ].pucStackStart = NULL;
+ xSecureContexts[ i ].pvTaskHandle = NULL;
+ }
+
+ #if ( configENABLE_MPU == 1 )
+ {
+ /* Configure thread mode to use PSP and to be unprivileged. */
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+ }
+ #else /* configENABLE_MPU */
+ {
+ /* Configure thread mode to use PSP and to be privileged. */
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+ }
+ #endif /* configENABLE_MPU */
+ }
+}
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+ secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
+ uint32_t ulIsTaskPrivileged,
+ void * pvTaskHandle )
+#else /* configENABLE_MPU */
+ secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
+ void * pvTaskHandle )
+#endif /* configENABLE_MPU */
+{
+ uint8_t * pucStackMemory = NULL;
+ uint8_t * pucStackLimit;
+ uint32_t ulIPSR, ulSecureContextIndex;
+ SecureContextHandle_t xSecureContextHandle = securecontextINVALID_CONTEXT_ID;
+
+ #if ( configENABLE_MPU == 1 )
+ uint32_t * pulCurrentStackPointer = NULL;
+ #endif /* configENABLE_MPU */
+
+ /* Read the Interrupt Program Status Register (IPSR) and Process Stack Limit
+ * Register (PSPLIM) value. */
+ secureportREAD_IPSR( ulIPSR );
+ secureportREAD_PSPLIM( pucStackLimit );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode.
+ * Also do nothing, if a secure context us already loaded. PSPLIM is set to
+ * securecontextNO_STACK when no secure context is loaded. */
+ if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )
+ {
+ /* Ontain a free secure context. */
+ ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );
+
+ /* Were we able to get a free context? */
+ if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS )
+ {
+ /* Allocate the stack space. */
+ pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE );
+
+ if( pucStackMemory != NULL )
+ {
+ /* Since stack grows down, the starting point will be the last
+ * location. Note that this location is next to the last
+ * allocated byte for stack (excluding the space for seal values)
+ * because the hardware decrements the stack pointer before
+ * writing i.e. if stack pointer is 0x2, a push operation will
+ * decrement the stack pointer to 0x1 and then write at 0x1. */
+ xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize;
+
+ /* Seal the created secure process stack. */
+ *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
+ *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
+
+ /* The stack cannot go beyond this location. This value is
+ * programmed in the PSPLIM register on context switch.*/
+ xSecureContexts[ ulSecureContextIndex ].pucStackLimit = pucStackMemory;
+
+ xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle;
+
+ #if ( configENABLE_MPU == 1 )
+ {
+ /* Store the correct CONTROL value for the task on the stack.
+ * This value is programmed in the CONTROL register on
+ * context switch. */
+ pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+ pulCurrentStackPointer--;
+
+ if( ulIsTaskPrivileged )
+ {
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
+ }
+ else
+ {
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+ }
+
+ /* Store the current stack pointer. This value is programmed in
+ * the PSP register on context switch. */
+ xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+ }
+ #else /* configENABLE_MPU */
+ {
+ /* Current SP is set to the starting of the stack. This
+ * value programmed in the PSP register on context switch. */
+ xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+ }
+ #endif /* configENABLE_MPU */
+
+ /* Ensure to never return 0 as a valid context handle. */
+ xSecureContextHandle = ulSecureContextIndex + 1UL;
+ }
+ }
+ }
+
+ return xSecureContextHandle;
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+{
+ uint32_t ulIPSR, ulSecureContextIndex;
+
+ /* Read the Interrupt Program Status Register (IPSR) value. */
+ secureportREAD_IPSR( ulIPSR );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode. */
+ if( ulIPSR != 0 )
+ {
+ /* Only free if a valid context handle is passed. */
+ if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )
+ {
+ ulSecureContextIndex = xSecureContextHandle - 1UL;
+
+ /* Ensure that the secure context being deleted is associated with
+ * the task. */
+ if( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle )
+ {
+ /* Free the stack space. */
+ vPortFree( xSecureContexts[ ulSecureContextIndex ].pucStackLimit );
+
+ /* Return the secure context back to the free secure contexts pool. */
+ vReturnSecureContext( ulSecureContextIndex );
+ }
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+{
+ uint8_t * pucStackLimit;
+ uint32_t ulSecureContextIndex;
+
+ if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )
+ {
+ ulSecureContextIndex = xSecureContextHandle - 1UL;
+
+ secureportREAD_PSPLIM( pucStackLimit );
+
+ /* Ensure that no secure context is loaded and the task is loading it's
+ * own context. */
+ if( ( pucStackLimit == securecontextNO_STACK ) &&
+ ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )
+ {
+ SecureContext_LoadContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) );
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+{
+ uint8_t * pucStackLimit;
+ uint32_t ulSecureContextIndex;
+
+ if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )
+ {
+ ulSecureContextIndex = xSecureContextHandle - 1UL;
+
+ secureportREAD_PSPLIM( pucStackLimit );
+
+ /* Ensure that task's context is loaded and the task is saving it's own
+ * context. */
+ if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) &&
+ ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )
+ {
+ SecureContext_SaveContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) );
+ }
+ }
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM85/secure/secure_context.h b/portable/GCC/ARM_CM85/secure/secure_context.h
index 57e390c..d0adbaf 100644
--- a/portable/GCC/ARM_CM85/secure/secure_context.h
+++ b/portable/GCC/ARM_CM85/secure/secure_context.h
@@ -1,135 +1,135 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef __SECURE_CONTEXT_H__
-#define __SECURE_CONTEXT_H__
-
-/* Standard includes. */
-#include <stdint.h>
-
-/* FreeRTOS includes. */
-#include "FreeRTOSConfig.h"
-
-/**
- * @brief PSP value when no secure context is loaded.
- */
-#define securecontextNO_STACK 0x0
-
-/**
- * @brief Invalid context ID.
- */
-#define securecontextINVALID_CONTEXT_ID 0UL
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Structure to represent a secure context.
- *
- * @note Since stack grows down, pucStackStart is the highest address while
- * pucStackLimit is the first address of the allocated memory.
- */
-typedef struct SecureContext
-{
- uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */
- uint8_t * pucStackLimit; /**< Last location of the stack memory (PSPLIM). */
- uint8_t * pucStackStart; /**< First location of the stack memory. */
- void * pvTaskHandle; /**< Task handle of the task this context is associated with. */
-} SecureContext_t;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Opaque handle for a secure context.
- */
-typedef uint32_t SecureContextHandle_t;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Initializes the secure context management system.
- *
- * PSP is set to NULL and therefore a task must allocate and load a context
- * before calling any secure side function in the thread mode.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- */
-void SecureContext_Init( void );
-
-/**
- * @brief Allocates a context on the secure side.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.
- * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.
- *
- * @return Opaque context handle if context is successfully allocated, NULL
- * otherwise.
- */
-#if ( configENABLE_MPU == 1 )
- SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
- uint32_t ulIsTaskPrivileged,
- void * pvTaskHandle );
-#else /* configENABLE_MPU */
- SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
- void * pvTaskHandle );
-#endif /* configENABLE_MPU */
-
-/**
- * @brief Frees the given context.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] xSecureContextHandle Context handle corresponding to the
- * context to be freed.
- */
-void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
-
-/**
- * @brief Loads the given context.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] xSecureContextHandle Context handle corresponding to the context
- * to be loaded.
- */
-void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
-
-/**
- * @brief Saves the given context.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] xSecureContextHandle Context handle corresponding to the context
- * to be saved.
- */
-void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
-
-#endif /* __SECURE_CONTEXT_H__ */
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef __SECURE_CONTEXT_H__
+#define __SECURE_CONTEXT_H__
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* FreeRTOS includes. */
+#include "FreeRTOSConfig.h"
+
+/**
+ * @brief PSP value when no secure context is loaded.
+ */
+#define securecontextNO_STACK 0x0
+
+/**
+ * @brief Invalid context ID.
+ */
+#define securecontextINVALID_CONTEXT_ID 0UL
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Structure to represent a secure context.
+ *
+ * @note Since stack grows down, pucStackStart is the highest address while
+ * pucStackLimit is the first address of the allocated memory.
+ */
+typedef struct SecureContext
+{
+ uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */
+ uint8_t * pucStackLimit; /**< Last location of the stack memory (PSPLIM). */
+ uint8_t * pucStackStart; /**< First location of the stack memory. */
+ void * pvTaskHandle; /**< Task handle of the task this context is associated with. */
+} SecureContext_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Opaque handle for a secure context.
+ */
+typedef uint32_t SecureContextHandle_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Initializes the secure context management system.
+ *
+ * PSP is set to NULL and therefore a task must allocate and load a context
+ * before calling any secure side function in the thread mode.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureContext_Init( void );
+
+/**
+ * @brief Allocates a context on the secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.
+ * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.
+ *
+ * @return Opaque context handle if context is successfully allocated, NULL
+ * otherwise.
+ */
+#if ( configENABLE_MPU == 1 )
+ SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
+ uint32_t ulIsTaskPrivileged,
+ void * pvTaskHandle );
+#else /* configENABLE_MPU */
+ SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
+ void * pvTaskHandle );
+#endif /* configENABLE_MPU */
+
+/**
+ * @brief Frees the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the
+ * context to be freed.
+ */
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+
+/**
+ * @brief Loads the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be loaded.
+ */
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+
+/**
+ * @brief Saves the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be saved.
+ */
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+
+#endif /* __SECURE_CONTEXT_H__ */
diff --git a/portable/GCC/ARM_CM85/secure/secure_context_port.c b/portable/GCC/ARM_CM85/secure/secure_context_port.c
index ebf0207..1352087 100644
--- a/portable/GCC/ARM_CM85/secure/secure_context_port.c
+++ b/portable/GCC/ARM_CM85/secure/secure_context_port.c
@@ -1,97 +1,97 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/* Secure context includes. */
-#include "secure_context.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );
-void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );
-
-void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext )
-{
- /* pxSecureContext value is in r0. */
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " mrs r1, ipsr \n" /* r1 = IPSR. */
- " cbz r1, load_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */
- " ldmia r0!, {r1, r2} \n" /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */
- " \n"
- #if ( configENABLE_MPU == 1 )
- " ldmia r1!, {r3} \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */
- " msr control, r3 \n" /* CONTROL = r3. */
- #endif /* configENABLE_MPU */
- " \n"
- " msr psplim, r2 \n" /* PSPLIM = r2. */
- " msr psp, r1 \n" /* PSP = r1. */
- " \n"
- " load_ctx_therad_mode: \n"
- " bx lr \n"
- " \n"
- ::: "r0", "r1", "r2"
- );
-}
-/*-----------------------------------------------------------*/
-
-void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext )
-{
- /* pxSecureContext value is in r0. */
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " mrs r1, ipsr \n" /* r1 = IPSR. */
- " cbz r1, save_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */
- " mrs r1, psp \n" /* r1 = PSP. */
- " \n"
- #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
- " vstmdb r1!, {s0} \n" /* Trigger the deferred stacking of FPU registers. */
- " vldmia r1!, {s0} \n" /* Nullify the effect of the previous statement. */
- #endif /* configENABLE_FPU || configENABLE_MVE */
- " \n"
- #if ( configENABLE_MPU == 1 )
- " mrs r2, control \n" /* r2 = CONTROL. */
- " stmdb r1!, {r2} \n" /* Store CONTROL value on the stack. */
- #endif /* configENABLE_MPU */
- " \n"
- " str r1, [r0] \n" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */
- " movs r1, %0 \n" /* r1 = securecontextNO_STACK. */
- " msr psplim, r1 \n" /* PSPLIM = securecontextNO_STACK. */
- " msr psp, r1 \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
- " \n"
- " save_ctx_therad_mode: \n"
- " bx lr \n"
- " \n"
- ::"i" ( securecontextNO_STACK ) : "r1", "memory"
- );
-}
-/*-----------------------------------------------------------*/
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );
+void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );
+
+void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext )
+{
+ /* pxSecureContext value is in r0. */
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r1, ipsr \n" /* r1 = IPSR. */
+ " cbz r1, load_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */
+ " ldmia r0!, {r1, r2} \n" /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */
+ " \n"
+ #if ( configENABLE_MPU == 1 )
+ " ldmia r1!, {r3} \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */
+ " msr control, r3 \n" /* CONTROL = r3. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ " msr psplim, r2 \n" /* PSPLIM = r2. */
+ " msr psp, r1 \n" /* PSP = r1. */
+ " \n"
+ " load_ctx_therad_mode: \n"
+ " bx lr \n"
+ " \n"
+ ::: "r0", "r1", "r2"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext )
+{
+ /* pxSecureContext value is in r0. */
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r1, ipsr \n" /* r1 = IPSR. */
+ " cbz r1, save_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */
+ " mrs r1, psp \n" /* r1 = PSP. */
+ " \n"
+ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ " vstmdb r1!, {s0} \n" /* Trigger the deferred stacking of FPU registers. */
+ " vldmia r1!, {s0} \n" /* Nullify the effect of the previous statement. */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
+ " \n"
+ #if ( configENABLE_MPU == 1 )
+ " mrs r2, control \n" /* r2 = CONTROL. */
+ " stmdb r1!, {r2} \n" /* Store CONTROL value on the stack. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ " str r1, [r0] \n" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */
+ " movs r1, %0 \n" /* r1 = securecontextNO_STACK. */
+ " msr psplim, r1 \n" /* PSPLIM = securecontextNO_STACK. */
+ " msr psp, r1 \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
+ " \n"
+ " save_ctx_therad_mode: \n"
+ " bx lr \n"
+ " \n"
+ ::"i" ( securecontextNO_STACK ) : "r1", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM85/secure/secure_heap.c b/portable/GCC/ARM_CM85/secure/secure_heap.c
index 741b463..157fdbf 100644
--- a/portable/GCC/ARM_CM85/secure/secure_heap.c
+++ b/portable/GCC/ARM_CM85/secure/secure_heap.c
@@ -1,454 +1,454 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/* Standard includes. */
-#include <stdint.h>
-
-/* Secure context heap includes. */
-#include "secure_heap.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/**
- * @brief Total heap size.
- */
-#ifndef secureconfigTOTAL_HEAP_SIZE
- #define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) )
-#endif
-
-/* No test marker by default. */
-#ifndef mtCOVERAGE_TEST_MARKER
- #define mtCOVERAGE_TEST_MARKER()
-#endif
-
-/* No tracing by default. */
-#ifndef traceMALLOC
- #define traceMALLOC( pvReturn, xWantedSize )
-#endif
-
-/* No tracing by default. */
-#ifndef traceFREE
- #define traceFREE( pv, xBlockSize )
-#endif
-
-/* Block sizes must not get too small. */
-#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) )
-
-/* Assumes 8bit bytes! */
-#define secureheapBITS_PER_BYTE ( ( size_t ) 8 )
-/*-----------------------------------------------------------*/
-
-/* Allocate the memory for the heap. */
-#if ( configAPPLICATION_ALLOCATED_HEAP == 1 )
-
-/* The application writer has already defined the array used for the RTOS
-* heap - probably so it can be placed in a special segment or address. */
- extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
-#else /* configAPPLICATION_ALLOCATED_HEAP */
- static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
-#endif /* configAPPLICATION_ALLOCATED_HEAP */
-
-/**
- * @brief The linked list structure.
- *
- * This is used to link free blocks in order of their memory address.
- */
-typedef struct A_BLOCK_LINK
-{
- struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */
- size_t xBlockSize; /**< The size of the free block. */
-} BlockLink_t;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Called automatically to setup the required heap structures the first
- * time pvPortMalloc() is called.
- */
-static void prvHeapInit( void );
-
-/**
- * @brief Inserts a block of memory that is being freed into the correct
- * position in the list of free memory blocks.
- *
- * The block being freed will be merged with the block in front it and/or the
- * block behind it if the memory blocks are adjacent to each other.
- *
- * @param[in] pxBlockToInsert The block being freed.
- */
-static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert );
-/*-----------------------------------------------------------*/
-
-/**
- * @brief The size of the structure placed at the beginning of each allocated
- * memory block must by correctly byte aligned.
- */
-static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
-
-/**
- * @brief Create a couple of list links to mark the start and end of the list.
- */
-static BlockLink_t xStart;
-static BlockLink_t * pxEnd = NULL;
-
-/**
- * @brief Keeps track of the number of free bytes remaining, but says nothing
- * about fragmentation.
- */
-static size_t xFreeBytesRemaining = 0U;
-static size_t xMinimumEverFreeBytesRemaining = 0U;
-
-/**
- * @brief Gets set to the top bit of an size_t type.
- *
- * When this bit in the xBlockSize member of an BlockLink_t structure is set
- * then the block belongs to the application. When the bit is free the block is
- * still part of the free heap space.
- */
-static size_t xBlockAllocatedBit = 0;
-/*-----------------------------------------------------------*/
-
-static void prvHeapInit( void )
-{
- BlockLink_t * pxFirstFreeBlock;
- uint8_t * pucAlignedHeap;
- size_t uxAddress;
- size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;
-
- /* Ensure the heap starts on a correctly aligned boundary. */
- uxAddress = ( size_t ) ucHeap;
-
- if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )
- {
- uxAddress += ( secureportBYTE_ALIGNMENT - 1 );
- uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
- xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
- }
-
- pucAlignedHeap = ( uint8_t * ) uxAddress;
-
- /* xStart is used to hold a pointer to the first item in the list of free
- * blocks. The void cast is used to prevent compiler warnings. */
- xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
- xStart.xBlockSize = ( size_t ) 0;
-
- /* pxEnd is used to mark the end of the list of free blocks and is inserted
- * at the end of the heap space. */
- uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
- uxAddress -= xHeapStructSize;
- uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
- pxEnd = ( void * ) uxAddress;
- pxEnd->xBlockSize = 0;
- pxEnd->pxNextFreeBlock = NULL;
-
- /* To start with there is a single free block that is sized to take up the
- * entire heap space, minus the space taken by pxEnd. */
- pxFirstFreeBlock = ( void * ) pucAlignedHeap;
- pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
- pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
-
- /* Only one block exists - and it covers the entire usable heap space. */
- xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
- xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-
- /* Work out the position of the top bit in a size_t variable. */
- xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
-}
-/*-----------------------------------------------------------*/
-
-static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )
-{
- BlockLink_t * pxIterator;
- uint8_t * puc;
-
- /* Iterate through the list until a block is found that has a higher address
- * than the block being inserted. */
- for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
- {
- /* Nothing to do here, just iterate to the right position. */
- }
-
- /* Do the block being inserted, and the block it is being inserted after
- * make a contiguous block of memory? */
- puc = ( uint8_t * ) pxIterator;
-
- if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
- {
- pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
- pxBlockToInsert = pxIterator;
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
-
- /* Do the block being inserted, and the block it is being inserted before
- * make a contiguous block of memory? */
- puc = ( uint8_t * ) pxBlockToInsert;
-
- if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
- {
- if( pxIterator->pxNextFreeBlock != pxEnd )
- {
- /* Form one big block from the two blocks. */
- pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
- pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
- }
- else
- {
- pxBlockToInsert->pxNextFreeBlock = pxEnd;
- }
- }
- else
- {
- pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
- }
-
- /* If the block being inserted plugged a gab, so was merged with the block
- * before and the block after, then it's pxNextFreeBlock pointer will have
- * already been set, and should not be set here as that would make it point
- * to itself. */
- if( pxIterator != pxBlockToInsert )
- {
- pxIterator->pxNextFreeBlock = pxBlockToInsert;
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
-}
-/*-----------------------------------------------------------*/
-
-void * pvPortMalloc( size_t xWantedSize )
-{
- BlockLink_t * pxBlock;
- BlockLink_t * pxPreviousBlock;
- BlockLink_t * pxNewBlockLink;
- void * pvReturn = NULL;
-
- /* If this is the first call to malloc then the heap will require
- * initialisation to setup the list of free blocks. */
- if( pxEnd == NULL )
- {
- prvHeapInit();
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
-
- /* Check the requested block size is not so large that the top bit is set.
- * The top bit of the block size member of the BlockLink_t structure is used
- * to determine who owns the block - the application or the kernel, so it
- * must be free. */
- if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
- {
- /* The wanted size is increased so it can contain a BlockLink_t
- * structure in addition to the requested amount of bytes. */
- if( xWantedSize > 0 )
- {
- xWantedSize += xHeapStructSize;
-
- /* Ensure that blocks are always aligned to the required number of
- * bytes. */
- if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
- {
- /* Byte alignment required. */
- xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
- secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
-
- if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
- {
- /* Traverse the list from the start (lowest address) block until
- * one of adequate size is found. */
- pxPreviousBlock = &xStart;
- pxBlock = xStart.pxNextFreeBlock;
-
- while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
- {
- pxPreviousBlock = pxBlock;
- pxBlock = pxBlock->pxNextFreeBlock;
- }
-
- /* If the end marker was reached then a block of adequate size was
- * not found. */
- if( pxBlock != pxEnd )
- {
- /* Return the memory space pointed to - jumping over the
- * BlockLink_t structure at its start. */
- pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
-
- /* This block is being returned for use so must be taken out
- * of the list of free blocks. */
- pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
-
- /* If the block is larger than required it can be split into
- * two. */
- if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )
- {
- /* This block is to be split into two. Create a new
- * block following the number of bytes requested. The void
- * cast is used to prevent byte alignment warnings from the
- * compiler. */
- pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
- secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );
-
- /* Calculate the sizes of two blocks split from the single
- * block. */
- pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
- pxBlock->xBlockSize = xWantedSize;
-
- /* Insert the new block into the list of free blocks. */
- prvInsertBlockIntoFreeList( pxNewBlockLink );
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
-
- xFreeBytesRemaining -= pxBlock->xBlockSize;
-
- if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
- {
- xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
-
- /* The block is being returned - it is allocated and owned by
- * the application and has no "next" block. */
- pxBlock->xBlockSize |= xBlockAllocatedBit;
- pxBlock->pxNextFreeBlock = NULL;
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
-
- traceMALLOC( pvReturn, xWantedSize );
-
- #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
- {
- if( pvReturn == NULL )
- {
- extern void vApplicationMallocFailedHook( void );
- vApplicationMallocFailedHook();
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
- }
- #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */
-
- secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
- return pvReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vPortFree( void * pv )
-{
- uint8_t * puc = ( uint8_t * ) pv;
- BlockLink_t * pxLink;
-
- if( pv != NULL )
- {
- /* The memory being freed will have an BlockLink_t structure immediately
- * before it. */
- puc -= xHeapStructSize;
-
- /* This casting is to keep the compiler from issuing warnings. */
- pxLink = ( void * ) puc;
-
- /* Check the block is actually allocated. */
- secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
- secureportASSERT( pxLink->pxNextFreeBlock == NULL );
-
- if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
- {
- if( pxLink->pxNextFreeBlock == NULL )
- {
- /* The block is being returned to the heap - it is no longer
- * allocated. */
- pxLink->xBlockSize &= ~xBlockAllocatedBit;
-
- secureportDISABLE_NON_SECURE_INTERRUPTS();
- {
- /* Add this block to the list of free blocks. */
- xFreeBytesRemaining += pxLink->xBlockSize;
- traceFREE( pv, pxLink->xBlockSize );
- prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
- }
- secureportENABLE_NON_SECURE_INTERRUPTS();
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
- }
-}
-/*-----------------------------------------------------------*/
-
-size_t xPortGetFreeHeapSize( void )
-{
- return xFreeBytesRemaining;
-}
-/*-----------------------------------------------------------*/
-
-size_t xPortGetMinimumEverFreeHeapSize( void )
-{
- return xMinimumEverFreeBytesRemaining;
-}
-/*-----------------------------------------------------------*/
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Secure context heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Total heap size.
+ */
+#ifndef secureconfigTOTAL_HEAP_SIZE
+ #define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) )
+#endif
+
+/* No test marker by default. */
+#ifndef mtCOVERAGE_TEST_MARKER
+ #define mtCOVERAGE_TEST_MARKER()
+#endif
+
+/* No tracing by default. */
+#ifndef traceMALLOC
+ #define traceMALLOC( pvReturn, xWantedSize )
+#endif
+
+/* No tracing by default. */
+#ifndef traceFREE
+ #define traceFREE( pv, xBlockSize )
+#endif
+
+/* Block sizes must not get too small. */
+#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) )
+
+/* Assumes 8bit bytes! */
+#define secureheapBITS_PER_BYTE ( ( size_t ) 8 )
+/*-----------------------------------------------------------*/
+
+/* Allocate the memory for the heap. */
+#if ( configAPPLICATION_ALLOCATED_HEAP == 1 )
+
+/* The application writer has already defined the array used for the RTOS
+* heap - probably so it can be placed in a special segment or address. */
+ extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#else /* configAPPLICATION_ALLOCATED_HEAP */
+ static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+/**
+ * @brief The linked list structure.
+ *
+ * This is used to link free blocks in order of their memory address.
+ */
+typedef struct A_BLOCK_LINK
+{
+ struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */
+ size_t xBlockSize; /**< The size of the free block. */
+} BlockLink_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Called automatically to setup the required heap structures the first
+ * time pvPortMalloc() is called.
+ */
+static void prvHeapInit( void );
+
+/**
+ * @brief Inserts a block of memory that is being freed into the correct
+ * position in the list of free memory blocks.
+ *
+ * The block being freed will be merged with the block in front it and/or the
+ * block behind it if the memory blocks are adjacent to each other.
+ *
+ * @param[in] pxBlockToInsert The block being freed.
+ */
+static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert );
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief The size of the structure placed at the beginning of each allocated
+ * memory block must by correctly byte aligned.
+ */
+static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+
+/**
+ * @brief Create a couple of list links to mark the start and end of the list.
+ */
+static BlockLink_t xStart;
+static BlockLink_t * pxEnd = NULL;
+
+/**
+ * @brief Keeps track of the number of free bytes remaining, but says nothing
+ * about fragmentation.
+ */
+static size_t xFreeBytesRemaining = 0U;
+static size_t xMinimumEverFreeBytesRemaining = 0U;
+
+/**
+ * @brief Gets set to the top bit of an size_t type.
+ *
+ * When this bit in the xBlockSize member of an BlockLink_t structure is set
+ * then the block belongs to the application. When the bit is free the block is
+ * still part of the free heap space.
+ */
+static size_t xBlockAllocatedBit = 0;
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+ BlockLink_t * pxFirstFreeBlock;
+ uint8_t * pucAlignedHeap;
+ size_t uxAddress;
+ size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;
+
+ /* Ensure the heap starts on a correctly aligned boundary. */
+ uxAddress = ( size_t ) ucHeap;
+
+ if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )
+ {
+ uxAddress += ( secureportBYTE_ALIGNMENT - 1 );
+ uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+ xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
+ }
+
+ pucAlignedHeap = ( uint8_t * ) uxAddress;
+
+ /* xStart is used to hold a pointer to the first item in the list of free
+ * blocks. The void cast is used to prevent compiler warnings. */
+ xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+ xStart.xBlockSize = ( size_t ) 0;
+
+ /* pxEnd is used to mark the end of the list of free blocks and is inserted
+ * at the end of the heap space. */
+ uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
+ uxAddress -= xHeapStructSize;
+ uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+ pxEnd = ( void * ) uxAddress;
+ pxEnd->xBlockSize = 0;
+ pxEnd->pxNextFreeBlock = NULL;
+
+ /* To start with there is a single free block that is sized to take up the
+ * entire heap space, minus the space taken by pxEnd. */
+ pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+ pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
+ pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+
+ /* Only one block exists - and it covers the entire usable heap space. */
+ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+ xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+
+ /* Work out the position of the top bit in a size_t variable. */
+ xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )
+{
+ BlockLink_t * pxIterator;
+ uint8_t * puc;
+
+ /* Iterate through the list until a block is found that has a higher address
+ * than the block being inserted. */
+ for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+ {
+ /* Nothing to do here, just iterate to the right position. */
+ }
+
+ /* Do the block being inserted, and the block it is being inserted after
+ * make a contiguous block of memory? */
+ puc = ( uint8_t * ) pxIterator;
+
+ if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+ {
+ pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+ pxBlockToInsert = pxIterator;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Do the block being inserted, and the block it is being inserted before
+ * make a contiguous block of memory? */
+ puc = ( uint8_t * ) pxBlockToInsert;
+
+ if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+ {
+ if( pxIterator->pxNextFreeBlock != pxEnd )
+ {
+ /* Form one big block from the two blocks. */
+ pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+ }
+ else
+ {
+ pxBlockToInsert->pxNextFreeBlock = pxEnd;
+ }
+ }
+ else
+ {
+ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+ }
+
+ /* If the block being inserted plugged a gab, so was merged with the block
+ * before and the block after, then it's pxNextFreeBlock pointer will have
+ * already been set, and should not be set here as that would make it point
+ * to itself. */
+ if( pxIterator != pxBlockToInsert )
+ {
+ pxIterator->pxNextFreeBlock = pxBlockToInsert;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+}
+/*-----------------------------------------------------------*/
+
+void * pvPortMalloc( size_t xWantedSize )
+{
+ BlockLink_t * pxBlock;
+ BlockLink_t * pxPreviousBlock;
+ BlockLink_t * pxNewBlockLink;
+ void * pvReturn = NULL;
+
+ /* If this is the first call to malloc then the heap will require
+ * initialisation to setup the list of free blocks. */
+ if( pxEnd == NULL )
+ {
+ prvHeapInit();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Check the requested block size is not so large that the top bit is set.
+ * The top bit of the block size member of the BlockLink_t structure is used
+ * to determine who owns the block - the application or the kernel, so it
+ * must be free. */
+ if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+ {
+ /* The wanted size is increased so it can contain a BlockLink_t
+ * structure in addition to the requested amount of bytes. */
+ if( xWantedSize > 0 )
+ {
+ xWantedSize += xHeapStructSize;
+
+ /* Ensure that blocks are always aligned to the required number of
+ * bytes. */
+ if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
+ {
+ /* Byte alignment required. */
+ xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
+ secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+ {
+ /* Traverse the list from the start (lowest address) block until
+ * one of adequate size is found. */
+ pxPreviousBlock = &xStart;
+ pxBlock = xStart.pxNextFreeBlock;
+
+ while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+ {
+ pxPreviousBlock = pxBlock;
+ pxBlock = pxBlock->pxNextFreeBlock;
+ }
+
+ /* If the end marker was reached then a block of adequate size was
+ * not found. */
+ if( pxBlock != pxEnd )
+ {
+ /* Return the memory space pointed to - jumping over the
+ * BlockLink_t structure at its start. */
+ pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+
+ /* This block is being returned for use so must be taken out
+ * of the list of free blocks. */
+ pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+ /* If the block is larger than required it can be split into
+ * two. */
+ if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )
+ {
+ /* This block is to be split into two. Create a new
+ * block following the number of bytes requested. The void
+ * cast is used to prevent byte alignment warnings from the
+ * compiler. */
+ pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+ secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+
+ /* Calculate the sizes of two blocks split from the single
+ * block. */
+ pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+ pxBlock->xBlockSize = xWantedSize;
+
+ /* Insert the new block into the list of free blocks. */
+ prvInsertBlockIntoFreeList( pxNewBlockLink );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+ if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+ {
+ xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* The block is being returned - it is allocated and owned by
+ * the application and has no "next" block. */
+ pxBlock->xBlockSize |= xBlockAllocatedBit;
+ pxBlock->pxNextFreeBlock = NULL;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ traceMALLOC( pvReturn, xWantedSize );
+
+ #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+ {
+ if( pvReturn == NULL )
+ {
+ extern void vApplicationMallocFailedHook( void );
+ vApplicationMallocFailedHook();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */
+
+ secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
+ return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void * pv )
+{
+ uint8_t * puc = ( uint8_t * ) pv;
+ BlockLink_t * pxLink;
+
+ if( pv != NULL )
+ {
+ /* The memory being freed will have an BlockLink_t structure immediately
+ * before it. */
+ puc -= xHeapStructSize;
+
+ /* This casting is to keep the compiler from issuing warnings. */
+ pxLink = ( void * ) puc;
+
+ /* Check the block is actually allocated. */
+ secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+ secureportASSERT( pxLink->pxNextFreeBlock == NULL );
+
+ if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+ {
+ if( pxLink->pxNextFreeBlock == NULL )
+ {
+ /* The block is being returned to the heap - it is no longer
+ * allocated. */
+ pxLink->xBlockSize &= ~xBlockAllocatedBit;
+
+ secureportDISABLE_NON_SECURE_INTERRUPTS();
+ {
+ /* Add this block to the list of free blocks. */
+ xFreeBytesRemaining += pxLink->xBlockSize;
+ traceFREE( pv, pxLink->xBlockSize );
+ prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+ }
+ secureportENABLE_NON_SECURE_INTERRUPTS();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+ return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetMinimumEverFreeHeapSize( void )
+{
+ return xMinimumEverFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM85/secure/secure_heap.h b/portable/GCC/ARM_CM85/secure/secure_heap.h
index bd42ff9..c13590f 100644
--- a/portable/GCC/ARM_CM85/secure/secure_heap.h
+++ b/portable/GCC/ARM_CM85/secure/secure_heap.h
@@ -1,66 +1,66 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef __SECURE_HEAP_H__
-#define __SECURE_HEAP_H__
-
-/* Standard includes. */
-#include <stdlib.h>
-
-/**
- * @brief Allocates memory from heap.
- *
- * @param[in] xWantedSize The size of the memory to be allocated.
- *
- * @return Pointer to the memory region if the allocation is successful, NULL
- * otherwise.
- */
-void * pvPortMalloc( size_t xWantedSize );
-
-/**
- * @brief Frees the previously allocated memory.
- *
- * @param[in] pv Pointer to the memory to be freed.
- */
-void vPortFree( void * pv );
-
-/**
- * @brief Get the free heap size.
- *
- * @return Free heap size.
- */
-size_t xPortGetFreeHeapSize( void );
-
-/**
- * @brief Get the minimum ever free heap size.
- *
- * @return Minimum ever free heap size.
- */
-size_t xPortGetMinimumEverFreeHeapSize( void );
-
-#endif /* __SECURE_HEAP_H__ */
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef __SECURE_HEAP_H__
+#define __SECURE_HEAP_H__
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/**
+ * @brief Allocates memory from heap.
+ *
+ * @param[in] xWantedSize The size of the memory to be allocated.
+ *
+ * @return Pointer to the memory region if the allocation is successful, NULL
+ * otherwise.
+ */
+void * pvPortMalloc( size_t xWantedSize );
+
+/**
+ * @brief Frees the previously allocated memory.
+ *
+ * @param[in] pv Pointer to the memory to be freed.
+ */
+void vPortFree( void * pv );
+
+/**
+ * @brief Get the free heap size.
+ *
+ * @return Free heap size.
+ */
+size_t xPortGetFreeHeapSize( void );
+
+/**
+ * @brief Get the minimum ever free heap size.
+ *
+ * @return Minimum ever free heap size.
+ */
+size_t xPortGetMinimumEverFreeHeapSize( void );
+
+#endif /* __SECURE_HEAP_H__ */
diff --git a/portable/GCC/ARM_CM85/secure/secure_init.c b/portable/GCC/ARM_CM85/secure/secure_init.c
index d91695b..dc19ebc 100644
--- a/portable/GCC/ARM_CM85/secure/secure_init.c
+++ b/portable/GCC/ARM_CM85/secure/secure_init.c
@@ -1,106 +1,106 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/* Standard includes. */
-#include <stdint.h>
-
-/* Secure init includes. */
-#include "secure_init.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/**
- * @brief Constants required to manipulate the SCB.
- */
-#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */
-#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL )
-#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )
-#define secureinitSCB_AIRCR_PRIS_POS ( 14UL )
-#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS )
-
-/**
- * @brief Constants required to manipulate the FPU.
- */
-#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
-#define secureinitFPCCR_LSPENS_POS ( 29UL )
-#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS )
-#define secureinitFPCCR_TS_POS ( 26UL )
-#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS )
-
-#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */
-#define secureinitNSACR_CP10_POS ( 10UL )
-#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS )
-#define secureinitNSACR_CP11_POS ( 11UL )
-#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS )
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )
-{
- uint32_t ulIPSR;
-
- /* Read the Interrupt Program Status Register (IPSR) value. */
- secureportREAD_IPSR( ulIPSR );
-
- /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
- * when the processor is running in the Thread Mode. */
- if( ulIPSR != 0 )
- {
- *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |
- ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |
- ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK );
- }
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
-{
- uint32_t ulIPSR;
-
- /* Read the Interrupt Program Status Register (IPSR) value. */
- secureportREAD_IPSR( ulIPSR );
-
- /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
- * when the processor is running in the Thread Mode. */
- if( ulIPSR != 0 )
- {
- /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is
- * permitted. CP11 should be programmed to the same value as CP10. */
- *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
-
- /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
- * that we can enable/disable lazy stacking in port.c file. */
- *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );
-
- /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP
- * registers (S16-S31) are also pushed to stack on exception entry and
- * restored on exception return. */
- *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );
- }
-}
-/*-----------------------------------------------------------*/
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Secure init includes. */
+#include "secure_init.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */
+#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL )
+#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )
+#define secureinitSCB_AIRCR_PRIS_POS ( 14UL )
+#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS )
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
+#define secureinitFPCCR_LSPENS_POS ( 29UL )
+#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS )
+#define secureinitFPCCR_TS_POS ( 26UL )
+#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS )
+
+#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */
+#define secureinitNSACR_CP10_POS ( 10UL )
+#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS )
+#define secureinitNSACR_CP11_POS ( 11UL )
+#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS )
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )
+{
+ uint32_t ulIPSR;
+
+ /* Read the Interrupt Program Status Register (IPSR) value. */
+ secureportREAD_IPSR( ulIPSR );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode. */
+ if( ulIPSR != 0 )
+ {
+ *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |
+ ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |
+ ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK );
+ }
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
+{
+ uint32_t ulIPSR;
+
+ /* Read the Interrupt Program Status Register (IPSR) value. */
+ secureportREAD_IPSR( ulIPSR );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode. */
+ if( ulIPSR != 0 )
+ {
+ /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is
+ * permitted. CP11 should be programmed to the same value as CP10. */
+ *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
+
+ /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
+ * that we can enable/disable lazy stacking in port.c file. */
+ *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );
+
+ /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP
+ * registers (S16-S31) are also pushed to stack on exception entry and
+ * restored on exception return. */
+ *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );
+ }
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM85/secure/secure_init.h b/portable/GCC/ARM_CM85/secure/secure_init.h
index e18ba44..21daeda 100644
--- a/portable/GCC/ARM_CM85/secure/secure_init.h
+++ b/portable/GCC/ARM_CM85/secure/secure_init.h
@@ -1,54 +1,54 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef __SECURE_INIT_H__
-#define __SECURE_INIT_H__
-
-/**
- * @brief De-prioritizes the non-secure exceptions.
- *
- * This is needed to ensure that the non-secure PendSV runs at the lowest
- * priority. Context switch is done in the non-secure PendSV handler.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- */
-void SecureInit_DePrioritizeNSExceptions( void );
-
-/**
- * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.
- *
- * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point
- * Registers are not leaked to the non-secure side.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- */
-void SecureInit_EnableNSFPUAccess( void );
-
-#endif /* __SECURE_INIT_H__ */
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef __SECURE_INIT_H__
+#define __SECURE_INIT_H__
+
+/**
+ * @brief De-prioritizes the non-secure exceptions.
+ *
+ * This is needed to ensure that the non-secure PendSV runs at the lowest
+ * priority. Context switch is done in the non-secure PendSV handler.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_DePrioritizeNSExceptions( void );
+
+/**
+ * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.
+ *
+ * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point
+ * Registers are not leaked to the non-secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_EnableNSFPUAccess( void );
+
+#endif /* __SECURE_INIT_H__ */
diff --git a/portable/GCC/ARM_CM85/secure/secure_port_macros.h b/portable/GCC/ARM_CM85/secure/secure_port_macros.h
index 5499054..304913b 100644
--- a/portable/GCC/ARM_CM85/secure/secure_port_macros.h
+++ b/portable/GCC/ARM_CM85/secure/secure_port_macros.h
@@ -1,140 +1,140 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef __SECURE_PORT_MACROS_H__
-#define __SECURE_PORT_MACROS_H__
-
-/**
- * @brief Byte alignment requirements.
- */
-#define secureportBYTE_ALIGNMENT 8
-#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 )
-
-/**
- * @brief Macro to declare a function as non-secure callable.
- */
-#if defined( __IAR_SYSTEMS_ICC__ )
- #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry __root
-#else
- #define secureportNON_SECURE_CALLABLE __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) )
-#endif
-
-/**
- * @brief Set the secure PRIMASK value.
- */
-#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \
- __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )
-
-/**
- * @brief Set the non-secure PRIMASK value.
- */
-#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \
- __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )
-
-/**
- * @brief Read the PSP value in the given variable.
- */
-#define secureportREAD_PSP( pucOutCurrentStackPointer ) \
- __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) )
-
-/**
- * @brief Set the PSP to the given value.
- */
-#define secureportSET_PSP( pucCurrentStackPointer ) \
- __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )
-
-/**
- * @brief Read the PSPLIM value in the given variable.
- */
-#define secureportREAD_PSPLIM( pucOutStackLimit ) \
- __asm volatile ( "mrs %0, psplim" : "=r" ( pucOutStackLimit ) )
-
-/**
- * @brief Set the PSPLIM to the given value.
- */
-#define secureportSET_PSPLIM( pucStackLimit ) \
- __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )
-
-/**
- * @brief Set the NonSecure MSP to the given value.
- */
-#define secureportSET_MSP_NS( pucMainStackPointer ) \
- __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )
-
-/**
- * @brief Set the CONTROL register to the given value.
- */
-#define secureportSET_CONTROL( ulControl ) \
- __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )
-
-/**
- * @brief Read the Interrupt Program Status Register (IPSR) value in the given
- * variable.
- */
-#define secureportREAD_IPSR( ulIPSR ) \
- __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) )
-
-/**
- * @brief PRIMASK value to enable interrupts.
- */
-#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0
-
-/**
- * @brief PRIMASK value to disable interrupts.
- */
-#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1
-
-/**
- * @brief Disable secure interrupts.
- */
-#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
-
-/**
- * @brief Disable non-secure interrupts.
- *
- * This effectively disables context switches.
- */
-#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
-
-/**
- * @brief Enable non-secure interrupts.
- */
-#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )
-
-/**
- * @brief Assert definition.
- */
-#define secureportASSERT( x ) \
- if( ( x ) == 0 ) \
- { \
- secureportDISABLE_SECURE_INTERRUPTS(); \
- secureportDISABLE_NON_SECURE_INTERRUPTS(); \
- for( ; ; ) {; } \
- }
-
-#endif /* __SECURE_PORT_MACROS_H__ */
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef __SECURE_PORT_MACROS_H__
+#define __SECURE_PORT_MACROS_H__
+
+/**
+ * @brief Byte alignment requirements.
+ */
+#define secureportBYTE_ALIGNMENT 8
+#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 )
+
+/**
+ * @brief Macro to declare a function as non-secure callable.
+ */
+#if defined( __IAR_SYSTEMS_ICC__ )
+ #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry __root
+#else
+ #define secureportNON_SECURE_CALLABLE __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) )
+#endif
+
+/**
+ * @brief Set the secure PRIMASK value.
+ */
+#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \
+ __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Set the non-secure PRIMASK value.
+ */
+#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \
+ __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Read the PSP value in the given variable.
+ */
+#define secureportREAD_PSP( pucOutCurrentStackPointer ) \
+ __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSP to the given value.
+ */
+#define secureportSET_PSP( pucCurrentStackPointer ) \
+ __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )
+
+/**
+ * @brief Read the PSPLIM value in the given variable.
+ */
+#define secureportREAD_PSPLIM( pucOutStackLimit ) \
+ __asm volatile ( "mrs %0, psplim" : "=r" ( pucOutStackLimit ) )
+
+/**
+ * @brief Set the PSPLIM to the given value.
+ */
+#define secureportSET_PSPLIM( pucStackLimit ) \
+ __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )
+
+/**
+ * @brief Set the NonSecure MSP to the given value.
+ */
+#define secureportSET_MSP_NS( pucMainStackPointer ) \
+ __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )
+
+/**
+ * @brief Set the CONTROL register to the given value.
+ */
+#define secureportSET_CONTROL( ulControl ) \
+ __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )
+
+/**
+ * @brief Read the Interrupt Program Status Register (IPSR) value in the given
+ * variable.
+ */
+#define secureportREAD_IPSR( ulIPSR ) \
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) )
+
+/**
+ * @brief PRIMASK value to enable interrupts.
+ */
+#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0
+
+/**
+ * @brief PRIMASK value to disable interrupts.
+ */
+#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1
+
+/**
+ * @brief Disable secure interrupts.
+ */
+#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Disable non-secure interrupts.
+ *
+ * This effectively disables context switches.
+ */
+#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Enable non-secure interrupts.
+ */
+#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Assert definition.
+ */
+#define secureportASSERT( x ) \
+ if( ( x ) == 0 ) \
+ { \
+ secureportDISABLE_SECURE_INTERRUPTS(); \
+ secureportDISABLE_NON_SECURE_INTERRUPTS(); \
+ for( ; ; ) {; } \
+ }
+
+#endif /* __SECURE_PORT_MACROS_H__ */
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c
index 21b515e..a78529d 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c
@@ -1,365 +1,365 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/* Standard includes. */
-#include <stdint.h>
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
- * is defined correctly and privileged functions are placed in correct sections. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Portasm includes. */
-#include "portasm.h"
-
-/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
- * header files. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " ldr r2, pxCurrentTCBConst2 \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r2] \n"/* Read pxCurrentTCB. */
- " ldr r0, [r1] \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
- " \n"
- #if ( configENABLE_MPU == 1 )
- " dmb \n"/* Complete outstanding transfers before disabling MPU. */
- " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
- " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
- " bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
- " str r4, [r2] \n"/* Disable MPU. */
- " \n"
- " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
- " ldr r3, [r1] \n"/* r3 = *r1 i.e. r3 = MAIR0. */
- " ldr r2, xMAIR0Const2 \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
- " str r3, [r2] \n"/* Program MAIR0. */
- " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
- " movs r3, #4 \n"/* r3 = 4. */
- " str r3, [r2] \n"/* Program RNR = 4. */
- " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
- " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
- " ldmia r1!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
- " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
- " \n"
- #if ( configTOTAL_MPU_REGIONS == 16 )
- " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
- " movs r3, #8 \n"/* r3 = 8. */
- " str r3, [r2] \n"/* Program RNR = 8. */
- " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
- " ldmia r1!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
- " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
- " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
- " movs r3, #12 \n"/* r3 = 12. */
- " str r3, [r2] \n"/* Program RNR = 12. */
- " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
- " ldmia r1!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
- " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
- #endif /* configTOTAL_MPU_REGIONS == 16 */
- " \n"
- " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
- " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
- " orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
- " str r4, [r2] \n"/* Enable MPU. */
- " dsb \n"/* Force memory writes before continuing. */
- #endif /* configENABLE_MPU */
- " \n"
- #if ( configENABLE_MPU == 1 )
- " ldm r0!, {r1-r3} \n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
- " msr psplim, r1 \n"/* Set this task's PSPLIM value. */
- " msr control, r2 \n"/* Set this task's CONTROL value. */
- " adds r0, #32 \n"/* Discard everything up to r0. */
- " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
- " isb \n"
- " mov r0, #0 \n"
- " msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */
- " bx r3 \n"/* Finally, branch to EXC_RETURN. */
- #else /* configENABLE_MPU */
- " ldm r0!, {r1-r2} \n"/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
- " msr psplim, r1 \n"/* Set this task's PSPLIM value. */
- " movs r1, #2 \n"/* r1 = 2. */
- " msr CONTROL, r1 \n"/* Switch to use PSP in the thread mode. */
- " adds r0, #32 \n"/* Discard everything up to r0. */
- " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
- " isb \n"
- " mov r0, #0 \n"
- " msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */
- " bx r2 \n"/* Finally, branch to EXC_RETURN. */
- #endif /* configENABLE_MPU */
- " \n"
- " .align 4 \n"
- "pxCurrentTCBConst2: .word pxCurrentTCB \n"
- #if ( configENABLE_MPU == 1 )
- "xMPUCTRLConst2: .word 0xe000ed94 \n"
- "xMAIR0Const2: .word 0xe000edc0 \n"
- "xRNRConst2: .word 0xe000ed98 \n"
- "xRBARConst2: .word 0xe000ed9c \n"
- #endif /* configENABLE_MPU */
- );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " mrs r0, control \n"/* r0 = CONTROL. */
- " tst r0, #1 \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
- " ite ne \n"
- " movne r0, #0 \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
- " moveq r0, #1 \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
- " bx lr \n"/* Return. */
- " \n"
- " .align 4 \n"
- ::: "r0", "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " mrs r0, control \n"/* Read the CONTROL register. */
- " bic r0, #1 \n"/* Clear the bit 0. */
- " msr control, r0 \n"/* Write back the new CONTROL value. */
- " bx lr \n"/* Return to the caller. */
- ::: "r0", "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-void vResetPrivilege( void ) /* __attribute__ (( naked )) */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " mrs r0, control \n"/* r0 = CONTROL. */
- " orr r0, #1 \n"/* r0 = r0 | 1. */
- " msr control, r0 \n"/* CONTROL = r0. */
- " bx lr \n"/* Return to the caller. */
- ::: "r0", "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " ldr r0, xVTORConst \n"/* Use the NVIC offset register to locate the stack. */
- " ldr r0, [r0] \n"/* Read the VTOR register which gives the address of vector table. */
- " ldr r0, [r0] \n"/* The first entry in vector table is stack pointer. */
- " msr msp, r0 \n"/* Set the MSP back to the start of the stack. */
- " cpsie i \n"/* Globally enable interrupts. */
- " cpsie f \n"
- " dsb \n"
- " isb \n"
- " svc %0 \n"/* System call to start the first task. */
- " nop \n"
- " \n"
- " .align 4 \n"
- "xVTORConst: .word 0xe000ed08 \n"
- ::"i" ( portSVC_START_SCHEDULER ) : "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " mrs r0, basepri \n"/* r0 = basepri. Return original basepri value. */
- " mov r1, %0 \n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- " msr basepri, r1 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- " dsb \n"
- " isb \n"
- " bx lr \n"/* Return. */
- ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " msr basepri, r0 \n"/* basepri = ulMask. */
- " dsb \n"
- " isb \n"
- " bx lr \n"/* Return. */
- ::: "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " mrs r0, psp \n"/* Read PSP in r0. */
- #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
- " tst lr, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
- " it eq \n"
- " vstmdbeq r0!, {s16-s31} \n"/* Store the additional FP context registers which are not saved automatically. */
- #endif /* configENABLE_FPU || configENABLE_MVE */
- #if ( configENABLE_MPU == 1 )
- " mrs r1, psplim \n"/* r1 = PSPLIM. */
- " mrs r2, control \n"/* r2 = CONTROL. */
- " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */
- " stmdb r0!, {r1-r11} \n"/* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */
- #else /* configENABLE_MPU */
- " mrs r2, psplim \n"/* r2 = PSPLIM. */
- " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */
- " stmdb r0!, {r2-r11} \n"/* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
- #endif /* configENABLE_MPU */
- " \n"
- " ldr r2, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r2] \n"/* Read pxCurrentTCB. */
- " str r0, [r1] \n"/* Save the new top of stack in TCB. */
- " \n"
- " mov r0, %0 \n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
- " msr basepri, r0 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- " dsb \n"
- " isb \n"
- " bl vTaskSwitchContext \n"
- " mov r0, #0 \n"/* r0 = 0. */
- " msr basepri, r0 \n"/* Enable interrupts. */
- " \n"
- " ldr r2, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r2] \n"/* Read pxCurrentTCB. */
- " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
- " \n"
- #if ( configENABLE_MPU == 1 )
- " dmb \n"/* Complete outstanding transfers before disabling MPU. */
- " ldr r2, xMPUCTRLConst \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
- " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
- " bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
- " str r4, [r2] \n"/* Disable MPU. */
- " \n"
- " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
- " ldr r3, [r1] \n"/* r3 = *r1 i.e. r3 = MAIR0. */
- " ldr r2, xMAIR0Const \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
- " str r3, [r2] \n"/* Program MAIR0. */
- " ldr r2, xRNRConst \n"/* r2 = 0xe000ed98 [Location of RNR]. */
- " movs r3, #4 \n"/* r3 = 4. */
- " str r3, [r2] \n"/* Program RNR = 4. */
- " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
- " ldr r2, xRBARConst \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
- " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
- " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
- " \n"
- #if ( configTOTAL_MPU_REGIONS == 16 )
- " ldr r2, xRNRConst \n"/* r2 = 0xe000ed98 [Location of RNR]. */
- " movs r3, #8 \n"/* r3 = 8. */
- " str r3, [r2] \n"/* Program RNR = 8. */
- " ldr r2, xRBARConst \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
- " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
- " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
- " ldr r2, xRNRConst \n"/* r2 = 0xe000ed98 [Location of RNR]. */
- " movs r3, #12 \n"/* r3 = 12. */
- " str r3, [r2] \n"/* Program RNR = 12. */
- " ldr r2, xRBARConst \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
- " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
- " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
- #endif /* configTOTAL_MPU_REGIONS == 16 */
- " \n"
- " ldr r2, xMPUCTRLConst \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
- " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
- " orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
- " str r4, [r2] \n"/* Enable MPU. */
- " dsb \n"/* Force memory writes before continuing. */
- #endif /* configENABLE_MPU */
- " \n"
- #if ( configENABLE_MPU == 1 )
- " ldmia r0!, {r1-r11} \n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */
- #else /* configENABLE_MPU */
- " ldmia r0!, {r2-r11} \n"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
- #endif /* configENABLE_MPU */
- " \n"
- #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
- " tst r3, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
- " it eq \n"
- " vldmiaeq r0!, {s16-s31} \n"/* Restore the additional FP context registers which are not restored automatically. */
- #endif /* configENABLE_FPU || configENABLE_MVE */
- " \n"
- #if ( configENABLE_MPU == 1 )
- " msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */
- " msr control, r2 \n"/* Restore the CONTROL register value for the task. */
- #else /* configENABLE_MPU */
- " msr psplim, r2 \n"/* Restore the PSPLIM register value for the task. */
- #endif /* configENABLE_MPU */
- " msr psp, r0 \n"/* Remember the new top of stack for the task. */
- " bx r3 \n"
- " \n"
- " .align 4 \n"
- "pxCurrentTCBConst: .word pxCurrentTCB \n"
- #if ( configENABLE_MPU == 1 )
- "xMPUCTRLConst: .word 0xe000ed94 \n"
- "xMAIR0Const: .word 0xe000edc0 \n"
- "xRNRConst: .word 0xe000ed98 \n"
- "xRBARConst: .word 0xe000ed9c \n"
- #endif /* configENABLE_MPU */
- ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
- );
-}
-/*-----------------------------------------------------------*/
-
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
- __asm volatile
- (
- " .syntax unified \n"
- " \n"
- " tst lr, #4 \n"
- " ite eq \n"
- " mrseq r0, msp \n"
- " mrsne r0, psp \n"
- " ldr r1, svchandler_address_const \n"
- " bx r1 \n"
- " \n"
- " .align 4 \n"
- "svchandler_address_const: .word vPortSVCHandler_C \n"
- );
-}
-/*-----------------------------------------------------------*/
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
+ * is defined correctly and privileged functions are placed in correct sections. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Portasm includes. */
+#include "portasm.h"
+
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
+ * header files. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " ldr r2, pxCurrentTCBConst2 \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r2] \n"/* Read pxCurrentTCB. */
+ " ldr r0, [r1] \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+ " \n"
+ #if ( configENABLE_MPU == 1 )
+ " dmb \n"/* Complete outstanding transfers before disabling MPU. */
+ " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
+ " bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+ " str r4, [r2] \n"/* Disable MPU. */
+ " \n"
+ " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+ " ldr r3, [r1] \n"/* r3 = *r1 i.e. r3 = MAIR0. */
+ " ldr r2, xMAIR0Const2 \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
+ " str r3, [r2] \n"/* Program MAIR0. */
+ " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
+ " movs r3, #4 \n"/* r3 = 4. */
+ " str r3, [r2] \n"/* Program RNR = 4. */
+ " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+ " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
+ " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+ " \n"
+ #if ( configTOTAL_MPU_REGIONS == 16 )
+ " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
+ " movs r3, #8 \n"/* r3 = 8. */
+ " str r3, [r2] \n"/* Program RNR = 8. */
+ " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
+ " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+ " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
+ " movs r3, #12 \n"/* r3 = 12. */
+ " str r3, [r2] \n"/* Program RNR = 12. */
+ " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
+ " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+ #endif /* configTOTAL_MPU_REGIONS == 16 */
+ " \n"
+ " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
+ " orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+ " str r4, [r2] \n"/* Enable MPU. */
+ " dsb \n"/* Force memory writes before continuing. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ #if ( configENABLE_MPU == 1 )
+ " ldm r0!, {r1-r3} \n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
+ " msr psplim, r1 \n"/* Set this task's PSPLIM value. */
+ " msr control, r2 \n"/* Set this task's CONTROL value. */
+ " adds r0, #32 \n"/* Discard everything up to r0. */
+ " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
+ " isb \n"
+ " mov r0, #0 \n"
+ " msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */
+ " bx r3 \n"/* Finally, branch to EXC_RETURN. */
+ #else /* configENABLE_MPU */
+ " ldm r0!, {r1-r2} \n"/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+ " msr psplim, r1 \n"/* Set this task's PSPLIM value. */
+ " movs r1, #2 \n"/* r1 = 2. */
+ " msr CONTROL, r1 \n"/* Switch to use PSP in the thread mode. */
+ " adds r0, #32 \n"/* Discard everything up to r0. */
+ " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
+ " isb \n"
+ " mov r0, #0 \n"
+ " msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */
+ " bx r2 \n"/* Finally, branch to EXC_RETURN. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ " .align 4 \n"
+ "pxCurrentTCBConst2: .word pxCurrentTCB \n"
+ #if ( configENABLE_MPU == 1 )
+ "xMPUCTRLConst2: .word 0xe000ed94 \n"
+ "xMAIR0Const2: .word 0xe000edc0 \n"
+ "xRNRConst2: .word 0xe000ed98 \n"
+ "xRBARConst2: .word 0xe000ed9c \n"
+ #endif /* configENABLE_MPU */
+ );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, control \n"/* r0 = CONTROL. */
+ " tst r0, #1 \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+ " ite ne \n"
+ " movne r0, #0 \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+ " moveq r0, #1 \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+ " bx lr \n"/* Return. */
+ " \n"
+ " .align 4 \n"
+ ::: "r0", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, control \n"/* Read the CONTROL register. */
+ " bic r0, #1 \n"/* Clear the bit 0. */
+ " msr control, r0 \n"/* Write back the new CONTROL value. */
+ " bx lr \n"/* Return to the caller. */
+ ::: "r0", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, control \n"/* r0 = CONTROL. */
+ " orr r0, #1 \n"/* r0 = r0 | 1. */
+ " msr control, r0 \n"/* CONTROL = r0. */
+ " bx lr \n"/* Return to the caller. */
+ ::: "r0", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " ldr r0, xVTORConst \n"/* Use the NVIC offset register to locate the stack. */
+ " ldr r0, [r0] \n"/* Read the VTOR register which gives the address of vector table. */
+ " ldr r0, [r0] \n"/* The first entry in vector table is stack pointer. */
+ " msr msp, r0 \n"/* Set the MSP back to the start of the stack. */
+ " cpsie i \n"/* Globally enable interrupts. */
+ " cpsie f \n"
+ " dsb \n"
+ " isb \n"
+ " svc %0 \n"/* System call to start the first task. */
+ " nop \n"
+ " \n"
+ " .align 4 \n"
+ "xVTORConst: .word 0xe000ed08 \n"
+ ::"i" ( portSVC_START_SCHEDULER ) : "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, basepri \n"/* r0 = basepri. Return original basepri value. */
+ " mov r1, %0 \n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " msr basepri, r1 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " dsb \n"
+ " isb \n"
+ " bx lr \n"/* Return. */
+ ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " msr basepri, r0 \n"/* basepri = ulMask. */
+ " dsb \n"
+ " isb \n"
+ " bx lr \n"/* Return. */
+ ::: "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, psp \n"/* Read PSP in r0. */
+ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ " tst lr, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+ " it eq \n"
+ " vstmdbeq r0!, {s16-s31} \n"/* Store the additional FP context registers which are not saved automatically. */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
+ #if ( configENABLE_MPU == 1 )
+ " mrs r1, psplim \n"/* r1 = PSPLIM. */
+ " mrs r2, control \n"/* r2 = CONTROL. */
+ " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */
+ " stmdb r0!, {r1-r11} \n"/* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */
+ #else /* configENABLE_MPU */
+ " mrs r2, psplim \n"/* r2 = PSPLIM. */
+ " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */
+ " stmdb r0!, {r2-r11} \n"/* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ " ldr r2, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r2] \n"/* Read pxCurrentTCB. */
+ " str r0, [r1] \n"/* Save the new top of stack in TCB. */
+ " \n"
+ " mov r0, %0 \n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+ " msr basepri, r0 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " dsb \n"
+ " isb \n"
+ " bl vTaskSwitchContext \n"
+ " mov r0, #0 \n"/* r0 = 0. */
+ " msr basepri, r0 \n"/* Enable interrupts. */
+ " \n"
+ " ldr r2, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r2] \n"/* Read pxCurrentTCB. */
+ " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+ " \n"
+ #if ( configENABLE_MPU == 1 )
+ " dmb \n"/* Complete outstanding transfers before disabling MPU. */
+ " ldr r2, xMPUCTRLConst \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
+ " bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+ " str r4, [r2] \n"/* Disable MPU. */
+ " \n"
+ " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+ " ldr r3, [r1] \n"/* r3 = *r1 i.e. r3 = MAIR0. */
+ " ldr r2, xMAIR0Const \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
+ " str r3, [r2] \n"/* Program MAIR0. */
+ " ldr r2, xRNRConst \n"/* r2 = 0xe000ed98 [Location of RNR]. */
+ " movs r3, #4 \n"/* r3 = 4. */
+ " str r3, [r2] \n"/* Program RNR = 4. */
+ " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+ " ldr r2, xRBARConst \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
+ " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+ " \n"
+ #if ( configTOTAL_MPU_REGIONS == 16 )
+ " ldr r2, xRNRConst \n"/* r2 = 0xe000ed98 [Location of RNR]. */
+ " movs r3, #8 \n"/* r3 = 8. */
+ " str r3, [r2] \n"/* Program RNR = 8. */
+ " ldr r2, xRBARConst \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
+ " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+ " ldr r2, xRNRConst \n"/* r2 = 0xe000ed98 [Location of RNR]. */
+ " movs r3, #12 \n"/* r3 = 12. */
+ " str r3, [r2] \n"/* Program RNR = 12. */
+ " ldr r2, xRBARConst \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
+ " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+ #endif /* configTOTAL_MPU_REGIONS == 16 */
+ " \n"
+ " ldr r2, xMPUCTRLConst \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
+ " orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+ " str r4, [r2] \n"/* Enable MPU. */
+ " dsb \n"/* Force memory writes before continuing. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ #if ( configENABLE_MPU == 1 )
+ " ldmia r0!, {r1-r11} \n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */
+ #else /* configENABLE_MPU */
+ " ldmia r0!, {r2-r11} \n"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ " tst r3, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+ " it eq \n"
+ " vldmiaeq r0!, {s16-s31} \n"/* Restore the additional FP context registers which are not restored automatically. */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
+ " \n"
+ #if ( configENABLE_MPU == 1 )
+ " msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */
+ " msr control, r2 \n"/* Restore the CONTROL register value for the task. */
+ #else /* configENABLE_MPU */
+ " msr psplim, r2 \n"/* Restore the PSPLIM register value for the task. */
+ #endif /* configENABLE_MPU */
+ " msr psp, r0 \n"/* Remember the new top of stack for the task. */
+ " bx r3 \n"
+ " \n"
+ " .align 4 \n"
+ "pxCurrentTCBConst: .word pxCurrentTCB \n"
+ #if ( configENABLE_MPU == 1 )
+ "xMPUCTRLConst: .word 0xe000ed94 \n"
+ "xMAIR0Const: .word 0xe000edc0 \n"
+ "xRNRConst: .word 0xe000ed98 \n"
+ "xRBARConst: .word 0xe000ed9c \n"
+ #endif /* configENABLE_MPU */
+ ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+ );
+}
+/*-----------------------------------------------------------*/
+
+void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " tst lr, #4 \n"
+ " ite eq \n"
+ " mrseq r0, msp \n"
+ " mrsne r0, psp \n"
+ " ldr r1, svchandler_address_const \n"
+ " bx r1 \n"
+ " \n"
+ " .align 4 \n"
+ "svchandler_address_const: .word vPortSVCHandler_C \n"
+ );
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.h b/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.h
index b37f6d1..ecd86b9 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.h
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.h
@@ -1,114 +1,114 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef __PORT_ASM_H__
-#define __PORT_ASM_H__
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-
-/* MPU wrappers includes. */
-#include "mpu_wrappers.h"
-
-/**
- * @brief Restore the context of the first task so that the first task starts
- * executing.
- */
-void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
-BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
-
-/**
- * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
- * register.
- *
- * @note This is a privileged function and should only be called from the kenrel
- * code.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- * Bit[0] = 0 --> The processor is running privileged
- * Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- * Bit[0] = 0 --> The processor is running privileged
- * Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vResetPrivilege( void ) __attribute__( ( naked ) );
-
-/**
- * @brief Starts the first task.
- */
-void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Disables interrupts.
- */
-uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Enables interrupts.
- */
-void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief PendSV Exception handler.
- */
-void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief SVC Handler.
- */
-void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Allocate a Secure context for the calling task.
- *
- * @param[in] ulSecureStackSize The size of the stack to be allocated on the
- * secure side for the calling task.
- */
-void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );
-
-/**
- * @brief Free the task's secure context.
- *
- * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
- */
-void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-#endif /* __PORT_ASM_H__ */
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
index 4b1f99b..51e21ea 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
@@ -155,9 +155,9 @@
* 8-bit values encoded as follows:
* Bit[7:4] - 0000 - Device Memory
* Bit[3:2] - 00 --> Device-nGnRnE
- * 01 --> Device-nGnRE
- * 10 --> Device-nGRE
- * 11 --> Device-GRE
+ * 01 --> Device-nGnRE
+ * 10 --> Device-nGRE
+ * 11 --> Device-GRE
* Bit[1:0] - 00, Reserved.
*/
#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
diff --git a/portable/GCC/ARM_CR5/port.c b/portable/GCC/ARM_CR5/port.c
index 1641d00..8a9839c 100644
--- a/portable/GCC/ARM_CR5/port.c
+++ b/portable/GCC/ARM_CR5/port.c
@@ -1,596 +1,596 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/* Standard includes. */
-#include <stdlib.h>
-#include <string.h>
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
- #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. Refer to Cortex-A equivalent: http: /*www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
-#endif
-
-#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
- #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. Refer to Cortex-A equivalent: http: /*www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
-#endif
-
-#ifndef configUNIQUE_INTERRUPT_PRIORITIES
- #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. Refer to Cortex-A equivalent: http: /*www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
-#endif
-
-#ifndef configSETUP_TICK_INTERRUPT
- #error configSETUP_TICK_INTERRUPT() must be defined. Refer to Cortex-A equivalent: http: /*www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
-#endif /* configSETUP_TICK_INTERRUPT */
-
-#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. Refer to Cortex-A equivalent: http: /*www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
-#endif
-
-#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
-#endif
-
-#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
-#endif
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
- /* Check the configuration. */
- #if ( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-/* In case security extensions are implemented. */
-#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
-#endif
-
-/* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in
- * portmacro.h. */
-#ifndef configCLEAR_TICK_INTERRUPT
- #define configCLEAR_TICK_INTERRUPT()
-#endif
-
-/* A critical section is exited when the critical section nesting count reaches
- * this value. */
-#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
-
-/* In all GICs 255 can be written to the priority mask register to unmask all
- * (but the lowest) interrupt priority. */
-#define portUNMASK_VALUE ( 0xFFUL )
-
-/* Tasks are not created with a floating point context, but can be given a
- * floating point context after they have been created. A variable is stored as
- * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
- * does not have an FPU context, or any other value if the task does have an FPU
- * context. */
-#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
-
-/* Constants required to setup the initial task context. */
-#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
-#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
-#define portINTERRUPT_ENABLE_BIT ( 0x80UL )
-#define portTHUMB_MODE_ADDRESS ( 0x01UL )
-
-/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
- * point is zero. */
-#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 )
-
-/* Masks all bits in the APSR other than the mode bits. */
-#define portAPSR_MODE_BITS_MASK ( 0x1F )
-
-/* The value of the mode bits in the APSR when the CPU is executing in user
- * mode. */
-#define portAPSR_USER_MODE ( 0x10 )
-
-/* The critical section macros only mask interrupts up to an application
- * determined priority level. Sometimes it is necessary to turn interrupt off in
- * the CPU itself before modifying certain hardware registers. */
-#define portCPU_IRQ_DISABLE() \
- __asm volatile ( "CPSID i" ::: "memory" ); \
- __asm volatile ( "DSB" ); \
- __asm volatile ( "ISB" );
-
-#define portCPU_IRQ_ENABLE() \
- __asm volatile ( "CPSIE i" ::: "memory" ); \
- __asm volatile ( "DSB" ); \
- __asm volatile ( "ISB" );
-
-
-/* Macro to unmask all interrupt priorities. */
-#define portCLEAR_INTERRUPT_MASK() \
- { \
- portCPU_IRQ_DISABLE(); \
- portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
- __asm volatile ( "DSB \n" \
- "ISB \n"); \
- portCPU_IRQ_ENABLE(); \
- }
-
-#define portINTERRUPT_PRIORITY_REGISTER_OFFSET 0x400UL
-#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
-#define portBIT_0_SET ( ( uint8_t ) 0x01 )
-
-/* Let the user override the pre-loading of the initial LR with the address of
- * prvTaskExitError() in case is messes up unwinding of the stack in the
- * debugger. */
-#ifdef configTASK_RETURN_ADDRESS
- #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
-#else
- #define portTASK_RETURN_ADDRESS prvTaskExitError
-#endif
-
-/*
- * The space on the stack required to hold the FPU registers.
- *
- * The ARM Cortex R5 processor implements the VFPv3-D16 FPU
- * architecture. This includes only 16 double-precision registers,
- * instead of 32 as is in VFPv3. The register bank can be viewed
- * either as sixteen 64-bit double-word registers (D0-D15) or
- * thirty-two 32-bit single-word registers (S0-S31), in both cases
- * the size of the bank remains the same. The FPU has also a 32-bit
- * status register.
- */
-#define portFPU_REGISTER_WORDS ( ( 16 * 2 ) + 1 )
-
-/*-----------------------------------------------------------*/
-
-/*
- * Starts the first task executing. This function is necessarily written in
- * assembly code so is implemented in portASM.s.
- */
-extern void vPortRestoreTaskContext( void );
-
-/*
- * Used to catch tasks that attempt to return from their implementing function.
- */
-static void prvTaskExitError( void );
-
-/*
- * If the application provides an implementation of vApplicationIRQHandler(),
- * then it will get called directly without saving the FPU registers on
- * interrupt entry, and this weak implementation of
- * vApplicationFPUSafeIRQHandler() is just provided to remove linkage errors -
- * it should never actually get called so its implementation contains a
- * call to configASSERT() that will always fail.
- *
- * If the application provides its own implementation of
- * vApplicationFPUSafeIRQHandler() then the implementation of
- * vApplicationIRQHandler() provided in portASM.S will save the FPU registers
- * before calling it.
- *
- * Therefore, if the application writer wants FPU registers to be saved on
- * interrupt entry their IRQ handler must be called
- * vApplicationFPUSafeIRQHandler(), and if the application writer does not want
- * FPU registers to be saved on interrupt entry their IRQ handler must be
- * called vApplicationIRQHandler().
- */
-void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR ) __attribute__((weak) );
-
-/*-----------------------------------------------------------*/
-
-/* A variable is used to keep track of the critical section nesting. This
- * variable has to be stored as part of the task context and must be initialised to
- * a non zero value to ensure interrupts don't inadvertently become unmasked before
- * the scheduler starts. As it is stored as part of the task context it will
- * automatically be set to 0 when the first task is started. */
-volatile uint32_t ulCriticalNesting = 9999UL;
-
-/* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then
- * a floating point context must be saved and restored for the task. */
-uint32_t ulPortTaskHasFPUContext = pdFALSE;
-
-/* Set to 1 to pend a context switch from an ISR. */
-uint32_t ulPortYieldRequired = pdFALSE;
-
-/* Counts the interrupt nesting depth. A context switch is only performed if
- * if the nesting depth is 0. */
-uint32_t ulPortInterruptNesting = 0UL;
-
-/* Used in asm code. */
-__attribute__( ( used ) ) const uint32_t ulICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
-__attribute__( ( used ) ) const uint32_t ulICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
-__attribute__( ( used ) ) const uint32_t ulICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
-__attribute__( ( used ) ) const uint32_t ulMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
-{
- /* Setup the initial stack of the task. The stack is set exactly as
- * expected by the portRESTORE_CONTEXT() macro.
- *
- * The fist real value on the stack is the status register, which is set for
- * system mode, with interrupts enabled. A few NULLs are added first to ensure
- * GDB does not try decoding a non-existent return address. */
- *pxTopOfStack = ( StackType_t ) NULL;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) NULL;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) NULL;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
-
- if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
- {
- /* The task will start in THUMB mode. */
- *pxTopOfStack |= portTHUMB_MODE_BIT;
- }
-
- pxTopOfStack--;
-
- /* Next the return address, which in this case is the start of the task. */
- *pxTopOfStack = ( StackType_t ) pxCode;
- pxTopOfStack--;
-
- /* Next all the registers other than the stack pointer. */
- *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack--;
-
- /* The task will start with a critical nesting count of 0 as interrupts are
- * enabled. */
- *pxTopOfStack = portNO_CRITICAL_NESTING;
-
- #if( configUSE_TASK_FPU_SUPPORT == 1 )
- {
- /* The task will start without a floating point context. A task that
- uses the floating point hardware must call vPortTaskUsesFPU() before
- executing any floating point instructions. */
- pxTopOfStack--;
- *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
- }
- #elif( configUSE_TASK_FPU_SUPPORT == 2 )
- {
- /* The task will start with a floating point context. Leave enough
- space for the registers - and ensure they are initialized to 0. */
- pxTopOfStack -= portFPU_REGISTER_WORDS;
- memset( pxTopOfStack, 0x00, portFPU_REGISTER_WORDS * sizeof( StackType_t ) );
-
- pxTopOfStack--;
- *pxTopOfStack = pdTRUE;
- ulPortTaskHasFPUContext = pdTRUE;
- }
- #else
- {
- #error Invalid configUSE_TASK_FPU_SUPPORT setting - configUSE_TASK_FPU_SUPPORT must be set to 1, 2, or left undefined.
- }
- #endif /* configUSE_TASK_FPU_SUPPORT */
-
- return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
- /* A function that implements a task must not exit or attempt to return to
- * its caller as there is nothing to return to. If a task wants to exit it
- * should instead call vTaskDelete( NULL ).
- *
- * Artificially force an assert() to be triggered if configASSERT() is
- * defined, then stop here so application writers can catch the error. */
- configASSERT( ulPortInterruptNesting == ~0UL );
- portDISABLE_INTERRUPTS();
-
- for( ; ; )
- {
- }
-}
-/*-----------------------------------------------------------*/
-
-void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR )
-{
- ( void ) ulICCIAR;
- configASSERT( ( volatile void * ) NULL );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
- uint32_t ulAPSR, ulCycles = 8; /* 8 bits per byte. */
-
- #if ( configASSERT_DEFINED == 1 )
- {
- volatile uint32_t ulOriginalPriority;
- volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );
- volatile uint8_t ucMaxPriorityValue;
-
- /* Determine how many priority bits are implemented in the GIC.
- *
- * Save the interrupt priority value that is about to be clobbered. */
- ulOriginalPriority = *pucFirstUserPriorityRegister;
-
- /* Determine the number of priority bits available. First write to
- * all possible bits. */
- *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
-
- /* Read the value back to see how many bits stuck. */
- ucMaxPriorityValue = *pucFirstUserPriorityRegister;
-
- /* Shift to the least significant bits. */
- while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET )
- {
- ucMaxPriorityValue >>= ( uint8_t ) 0x01;
-
- /* If ulCycles reaches 0 then ucMaxPriorityValue must have been
- * read as 0, indicating a misconfiguration. */
- ulCycles--;
-
- if( ulCycles == 0 )
- {
- break;
- }
- }
-
- /* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
- * value. */
- configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY );
-
- /* Restore the clobbered interrupt priority register to its original
- * value. */
- *pucFirstUserPriorityRegister = ulOriginalPriority;
- }
- #endif /* configASSERT_DEFINED */
-
- /* Only continue if the CPU is not in User mode. The CPU must be in a
- * Privileged mode for the scheduler to start. */
- __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR )::"memory" );
- ulAPSR &= portAPSR_MODE_BITS_MASK;
- configASSERT( ulAPSR != portAPSR_USER_MODE );
-
- if( ulAPSR != portAPSR_USER_MODE )
- {
- /* Only continue if the binary point value is set to its lowest possible
- * setting. See the comments in vPortValidateInterruptPriority() below for
- * more information. */
- configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
-
- if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
- {
- /* Interrupts are turned off in the CPU itself to ensure tick does
- * not execute while the scheduler is being started. Interrupts are
- * automatically turned back on in the CPU when the first task starts
- * executing. */
- portCPU_IRQ_DISABLE();
-
- /* Start the timer that generates the tick ISR. */
- configSETUP_TICK_INTERRUPT();
-
- /* Start the first task executing. */
- vPortRestoreTaskContext();
- }
- }
-
- /* Will only get here if vTaskStartScheduler() was called with the CPU in
- * a non-privileged mode or the binary point register was not set to its lowest
- * possible value. prvTaskExitError() is referenced to prevent a compiler
- * warning about it being defined but not referenced in the case that the user
- * defines their own exit address. */
- ( void ) prvTaskExitError;
- return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
- /* Not implemented in ports where there is nothing to return to.
- * Artificially force an assert. */
- configASSERT( ulCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
- /* Mask interrupts up to the max syscall interrupt priority. */
- ulPortSetInterruptMask();
-
- /* Now interrupts are disabled ulCriticalNesting can be accessed
- * directly. Increment ulCriticalNesting to keep a count of how many times
- * portENTER_CRITICAL() has been called. */
- ulCriticalNesting++;
-
- /* This is not the interrupt safe version of the enter critical function so
- * assert() if it is being called from an interrupt context. Only API
- * functions that end in "FromISR" can be used in an interrupt. Only assert if
- * the critical nesting count is 1 to protect against recursive calls if the
- * assert function also uses a critical section. */
- if( ulCriticalNesting == 1 )
- {
- configASSERT( ulPortInterruptNesting == 0 );
- }
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
- if( ulCriticalNesting > portNO_CRITICAL_NESTING )
- {
- /* Decrement the nesting count as the critical section is being
- * exited. */
- ulCriticalNesting--;
-
- /* If the nesting level has reached zero then all interrupt
- * priorities must be re-enabled. */
- if( ulCriticalNesting == portNO_CRITICAL_NESTING )
- {
- /* Critical nesting has reached zero so all interrupt priorities
- * should be unmasked. */
- portCLEAR_INTERRUPT_MASK();
- }
- }
-}
-/*-----------------------------------------------------------*/
-
-void FreeRTOS_Tick_Handler( void )
-{
- /* Set interrupt mask before altering scheduler structures. The tick
- * handler runs at the lowest priority, so interrupts cannot already be masked,
- * so there is no need to save and restore the current mask value. It is
- * necessary to turn off interrupts in the CPU itself while the ICCPMR is being
- * updated. */
- portCPU_IRQ_DISABLE();
- portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
- __asm volatile ( "dsb \n"
- "isb \n"::: "memory" );
- portCPU_IRQ_ENABLE();
-
- /* Increment the RTOS tick. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- ulPortYieldRequired = pdTRUE;
- }
-
- /* Ensure all interrupt priorities are active again. */
- portCLEAR_INTERRUPT_MASK();
- configCLEAR_TICK_INTERRUPT();
-}
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TASK_FPU_SUPPORT != 2 )
-
- void vPortTaskUsesFPU( void )
- {
- uint32_t ulInitialFPSCR = 0;
-
- /* A task is registering the fact that it needs an FPU context. Set the
- * FPU flag (which is saved as part of the task context). */
- ulPortTaskHasFPUContext = pdTRUE;
-
- /* Initialise the floating point status register. */
- __asm volatile ( "FMXR FPSCR, %0" ::"r" ( ulInitialFPSCR ) : "memory" );
- }
-
-#endif /* configUSE_TASK_FPU_SUPPORT */
-/*-----------------------------------------------------------*/
-
-void vPortClearInterruptMask( uint32_t ulNewMaskValue )
-{
- if( ulNewMaskValue == pdFALSE )
- {
- portCLEAR_INTERRUPT_MASK();
- }
-}
-/*-----------------------------------------------------------*/
-
-uint32_t ulPortSetInterruptMask( void )
-{
- uint32_t ulReturn;
-
- /* Interrupt in the CPU must be turned off while the ICCPMR is being
- * updated. */
- portCPU_IRQ_DISABLE();
-
- if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
- {
- /* Interrupts were already masked. */
- ulReturn = pdTRUE;
- }
- else
- {
- ulReturn = pdFALSE;
- portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
- __asm volatile ( "dsb \n"
- "isb \n"::: "memory" );
- }
-
- portCPU_IRQ_ENABLE();
-
- return ulReturn;
-}
-/*-----------------------------------------------------------*/
-
-#if ( configASSERT_DEFINED == 1 )
-
- void vPortValidateInterruptPriority( void )
- {
- /* The following assertion will fail if a service routine (ISR) for
- * an interrupt that has been assigned a priority above
- * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
- * function. ISR safe FreeRTOS API functions must *only* be called
- * from interrupts that have been assigned a priority at or below
- * configMAX_SYSCALL_INTERRUPT_PRIORITY.
- *
- * Numerically low interrupt priority numbers represent logically high
- * interrupt priorities, therefore the priority of the interrupt must
- * be set to a value equal to or numerically *higher* than
- * configMAX_SYSCALL_INTERRUPT_PRIORITY.
- *
- * FreeRTOS maintains separate thread and ISR API functions to ensure
- * interrupt entry is as fast and simple as possible. */
-
- configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
-
- /* Priority grouping: The interrupt controller (GIC) allows the bits
- * that define each interrupt's priority to be split between bits that
- * define the interrupt's pre-emption priority bits and bits that define
- * the interrupt's sub-priority. For simplicity all bits must be defined
- * to be pre-emption priority bits. The following assertion will fail if
- * this is not the case (if some bits represent a sub-priority).
- *
- * The priority grouping is configured by the GIC's binary point register
- * (ICCBPR). Writing 0 to ICCBPR will ensure it is set to its lowest
- * possible value (which may be above 0). */
- configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
- }
-
-#endif /* configASSERT_DEFINED */
-/*-----------------------------------------------------------*/
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Standard includes. */
+#include <stdlib.h>
+#include <string.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
+ #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. Refer to Cortex-A equivalent: http: /*www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
+#endif
+
+#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
+ #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. Refer to Cortex-A equivalent: http: /*www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
+#endif
+
+#ifndef configUNIQUE_INTERRUPT_PRIORITIES
+ #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. Refer to Cortex-A equivalent: http: /*www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
+#endif
+
+#ifndef configSETUP_TICK_INTERRUPT
+ #error configSETUP_TICK_INTERRUPT() must be defined. Refer to Cortex-A equivalent: http: /*www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
+#endif /* configSETUP_TICK_INTERRUPT */
+
+#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. Refer to Cortex-A equivalent: http: /*www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
+#endif
+
+#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
+#endif
+
+#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+ /* Check the configuration. */
+ #if ( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/* In case security extensions are implemented. */
+#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
+#endif
+
+/* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in
+ * portmacro.h. */
+#ifndef configCLEAR_TICK_INTERRUPT
+ #define configCLEAR_TICK_INTERRUPT()
+#endif
+
+/* A critical section is exited when the critical section nesting count reaches
+ * this value. */
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
+
+/* In all GICs 255 can be written to the priority mask register to unmask all
+ * (but the lowest) interrupt priority. */
+#define portUNMASK_VALUE ( 0xFFUL )
+
+/* Tasks are not created with a floating point context, but can be given a
+ * floating point context after they have been created. A variable is stored as
+ * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+ * does not have an FPU context, or any other value if the task does have an FPU
+ * context. */
+#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
+
+/* Constants required to setup the initial task context. */
+#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
+#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
+#define portINTERRUPT_ENABLE_BIT ( 0x80UL )
+#define portTHUMB_MODE_ADDRESS ( 0x01UL )
+
+/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
+ * point is zero. */
+#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 )
+
+/* Masks all bits in the APSR other than the mode bits. */
+#define portAPSR_MODE_BITS_MASK ( 0x1F )
+
+/* The value of the mode bits in the APSR when the CPU is executing in user
+ * mode. */
+#define portAPSR_USER_MODE ( 0x10 )
+
+/* The critical section macros only mask interrupts up to an application
+ * determined priority level. Sometimes it is necessary to turn interrupt off in
+ * the CPU itself before modifying certain hardware registers. */
+#define portCPU_IRQ_DISABLE() \
+ __asm volatile ( "CPSID i" ::: "memory" ); \
+ __asm volatile ( "DSB" ); \
+ __asm volatile ( "ISB" );
+
+#define portCPU_IRQ_ENABLE() \
+ __asm volatile ( "CPSIE i" ::: "memory" ); \
+ __asm volatile ( "DSB" ); \
+ __asm volatile ( "ISB" );
+
+
+/* Macro to unmask all interrupt priorities. */
+#define portCLEAR_INTERRUPT_MASK() \
+ { \
+ portCPU_IRQ_DISABLE(); \
+ portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
+ __asm volatile ( "DSB \n" \
+ "ISB \n"); \
+ portCPU_IRQ_ENABLE(); \
+ }
+
+#define portINTERRUPT_PRIORITY_REGISTER_OFFSET 0x400UL
+#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
+#define portBIT_0_SET ( ( uint8_t ) 0x01 )
+
+/* Let the user override the pre-loading of the initial LR with the address of
+ * prvTaskExitError() in case is messes up unwinding of the stack in the
+ * debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
+#else
+ #define portTASK_RETURN_ADDRESS prvTaskExitError
+#endif
+
+/*
+ * The space on the stack required to hold the FPU registers.
+ *
+ * The ARM Cortex R5 processor implements the VFPv3-D16 FPU
+ * architecture. This includes only 16 double-precision registers,
+ * instead of 32 as is in VFPv3. The register bank can be viewed
+ * either as sixteen 64-bit double-word registers (D0-D15) or
+ * thirty-two 32-bit single-word registers (S0-S31), in both cases
+ * the size of the bank remains the same. The FPU has also a 32-bit
+ * status register.
+ */
+#define portFPU_REGISTER_WORDS ( ( 16 * 2 ) + 1 )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Starts the first task executing. This function is necessarily written in
+ * assembly code so is implemented in portASM.s.
+ */
+extern void vPortRestoreTaskContext( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*
+ * If the application provides an implementation of vApplicationIRQHandler(),
+ * then it will get called directly without saving the FPU registers on
+ * interrupt entry, and this weak implementation of
+ * vApplicationFPUSafeIRQHandler() is just provided to remove linkage errors -
+ * it should never actually get called so its implementation contains a
+ * call to configASSERT() that will always fail.
+ *
+ * If the application provides its own implementation of
+ * vApplicationFPUSafeIRQHandler() then the implementation of
+ * vApplicationIRQHandler() provided in portASM.S will save the FPU registers
+ * before calling it.
+ *
+ * Therefore, if the application writer wants FPU registers to be saved on
+ * interrupt entry their IRQ handler must be called
+ * vApplicationFPUSafeIRQHandler(), and if the application writer does not want
+ * FPU registers to be saved on interrupt entry their IRQ handler must be
+ * called vApplicationIRQHandler().
+ */
+void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR ) __attribute__((weak) );
+
+/*-----------------------------------------------------------*/
+
+/* A variable is used to keep track of the critical section nesting. This
+ * variable has to be stored as part of the task context and must be initialised to
+ * a non zero value to ensure interrupts don't inadvertently become unmasked before
+ * the scheduler starts. As it is stored as part of the task context it will
+ * automatically be set to 0 when the first task is started. */
+volatile uint32_t ulCriticalNesting = 9999UL;
+
+/* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then
+ * a floating point context must be saved and restored for the task. */
+uint32_t ulPortTaskHasFPUContext = pdFALSE;
+
+/* Set to 1 to pend a context switch from an ISR. */
+uint32_t ulPortYieldRequired = pdFALSE;
+
+/* Counts the interrupt nesting depth. A context switch is only performed if
+ * if the nesting depth is 0. */
+uint32_t ulPortInterruptNesting = 0UL;
+
+/* Used in asm code. */
+__attribute__( ( used ) ) const uint32_t ulICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
+__attribute__( ( used ) ) const uint32_t ulICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
+__attribute__( ( used ) ) const uint32_t ulICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
+__attribute__( ( used ) ) const uint32_t ulMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+ TaskFunction_t pxCode,
+ void * pvParameters )
+{
+ /* Setup the initial stack of the task. The stack is set exactly as
+ * expected by the portRESTORE_CONTEXT() macro.
+ *
+ * The fist real value on the stack is the status register, which is set for
+ * system mode, with interrupts enabled. A few NULLs are added first to ensure
+ * GDB does not try decoding a non-existent return address. */
+ *pxTopOfStack = ( StackType_t ) NULL;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) NULL;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) NULL;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+
+ if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
+ {
+ /* The task will start in THUMB mode. */
+ *pxTopOfStack |= portTHUMB_MODE_BIT;
+ }
+
+ pxTopOfStack--;
+
+ /* Next the return address, which in this case is the start of the task. */
+ *pxTopOfStack = ( StackType_t ) pxCode;
+ pxTopOfStack--;
+
+ /* Next all the registers other than the stack pointer. */
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
+
+ /* The task will start with a critical nesting count of 0 as interrupts are
+ * enabled. */
+ *pxTopOfStack = portNO_CRITICAL_NESTING;
+
+ #if( configUSE_TASK_FPU_SUPPORT == 1 )
+ {
+ /* The task will start without a floating point context. A task that
+ uses the floating point hardware must call vPortTaskUsesFPU() before
+ executing any floating point instructions. */
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+ }
+ #elif( configUSE_TASK_FPU_SUPPORT == 2 )
+ {
+ /* The task will start with a floating point context. Leave enough
+ space for the registers - and ensure they are initialized to 0. */
+ pxTopOfStack -= portFPU_REGISTER_WORDS;
+ memset( pxTopOfStack, 0x00, portFPU_REGISTER_WORDS * sizeof( StackType_t ) );
+
+ pxTopOfStack--;
+ *pxTopOfStack = pdTRUE;
+ ulPortTaskHasFPUContext = pdTRUE;
+ }
+ #else
+ {
+ #error Invalid configUSE_TASK_FPU_SUPPORT setting - configUSE_TASK_FPU_SUPPORT must be set to 1, 2, or left undefined.
+ }
+ #endif /* configUSE_TASK_FPU_SUPPORT */
+
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+ /* A function that implements a task must not exit or attempt to return to
+ * its caller as there is nothing to return to. If a task wants to exit it
+ * should instead call vTaskDelete( NULL ).
+ *
+ * Artificially force an assert() to be triggered if configASSERT() is
+ * defined, then stop here so application writers can catch the error. */
+ configASSERT( ulPortInterruptNesting == ~0UL );
+ portDISABLE_INTERRUPTS();
+
+ for( ; ; )
+ {
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR )
+{
+ ( void ) ulICCIAR;
+ configASSERT( ( volatile void * ) NULL );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+ uint32_t ulAPSR, ulCycles = 8; /* 8 bits per byte. */
+
+ #if ( configASSERT_DEFINED == 1 )
+ {
+ volatile uint32_t ulOriginalPriority;
+ volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine how many priority bits are implemented in the GIC.
+ *
+ * Save the interrupt priority value that is about to be clobbered. */
+ ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+ /* Determine the number of priority bits available. First write to
+ * all possible bits. */
+ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+ /* Shift to the least significant bits. */
+ while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET )
+ {
+ ucMaxPriorityValue >>= ( uint8_t ) 0x01;
+
+ /* If ulCycles reaches 0 then ucMaxPriorityValue must have been
+ * read as 0, indicating a misconfiguration. */
+ ulCycles--;
+
+ if( ulCycles == 0 )
+ {
+ break;
+ }
+ }
+
+ /* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
+ * value. */
+ configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY );
+
+ /* Restore the clobbered interrupt priority register to its original
+ * value. */
+ *pucFirstUserPriorityRegister = ulOriginalPriority;
+ }
+ #endif /* configASSERT_DEFINED */
+
+ /* Only continue if the CPU is not in User mode. The CPU must be in a
+ * Privileged mode for the scheduler to start. */
+ __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR )::"memory" );
+ ulAPSR &= portAPSR_MODE_BITS_MASK;
+ configASSERT( ulAPSR != portAPSR_USER_MODE );
+
+ if( ulAPSR != portAPSR_USER_MODE )
+ {
+ /* Only continue if the binary point value is set to its lowest possible
+ * setting. See the comments in vPortValidateInterruptPriority() below for
+ * more information. */
+ configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
+
+ if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
+ {
+ /* Interrupts are turned off in the CPU itself to ensure tick does
+ * not execute while the scheduler is being started. Interrupts are
+ * automatically turned back on in the CPU when the first task starts
+ * executing. */
+ portCPU_IRQ_DISABLE();
+
+ /* Start the timer that generates the tick ISR. */
+ configSETUP_TICK_INTERRUPT();
+
+ /* Start the first task executing. */
+ vPortRestoreTaskContext();
+ }
+ }
+
+ /* Will only get here if vTaskStartScheduler() was called with the CPU in
+ * a non-privileged mode or the binary point register was not set to its lowest
+ * possible value. prvTaskExitError() is referenced to prevent a compiler
+ * warning about it being defined but not referenced in the case that the user
+ * defines their own exit address. */
+ ( void ) prvTaskExitError;
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+ /* Not implemented in ports where there is nothing to return to.
+ * Artificially force an assert. */
+ configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+ /* Mask interrupts up to the max syscall interrupt priority. */
+ ulPortSetInterruptMask();
+
+ /* Now interrupts are disabled ulCriticalNesting can be accessed
+ * directly. Increment ulCriticalNesting to keep a count of how many times
+ * portENTER_CRITICAL() has been called. */
+ ulCriticalNesting++;
+
+ /* This is not the interrupt safe version of the enter critical function so
+ * assert() if it is being called from an interrupt context. Only API
+ * functions that end in "FromISR" can be used in an interrupt. Only assert if
+ * the critical nesting count is 1 to protect against recursive calls if the
+ * assert function also uses a critical section. */
+ if( ulCriticalNesting == 1 )
+ {
+ configASSERT( ulPortInterruptNesting == 0 );
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+ if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+ {
+ /* Decrement the nesting count as the critical section is being
+ * exited. */
+ ulCriticalNesting--;
+
+ /* If the nesting level has reached zero then all interrupt
+ * priorities must be re-enabled. */
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+ {
+ /* Critical nesting has reached zero so all interrupt priorities
+ * should be unmasked. */
+ portCLEAR_INTERRUPT_MASK();
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+void FreeRTOS_Tick_Handler( void )
+{
+ /* Set interrupt mask before altering scheduler structures. The tick
+ * handler runs at the lowest priority, so interrupts cannot already be masked,
+ * so there is no need to save and restore the current mask value. It is
+ * necessary to turn off interrupts in the CPU itself while the ICCPMR is being
+ * updated. */
+ portCPU_IRQ_DISABLE();
+ portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+ __asm volatile ( "dsb \n"
+ "isb \n"::: "memory" );
+ portCPU_IRQ_ENABLE();
+
+ /* Increment the RTOS tick. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ ulPortYieldRequired = pdTRUE;
+ }
+
+ /* Ensure all interrupt priorities are active again. */
+ portCLEAR_INTERRUPT_MASK();
+ configCLEAR_TICK_INTERRUPT();
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_FPU_SUPPORT != 2 )
+
+ void vPortTaskUsesFPU( void )
+ {
+ uint32_t ulInitialFPSCR = 0;
+
+ /* A task is registering the fact that it needs an FPU context. Set the
+ * FPU flag (which is saved as part of the task context). */
+ ulPortTaskHasFPUContext = pdTRUE;
+
+ /* Initialise the floating point status register. */
+ __asm volatile ( "FMXR FPSCR, %0" ::"r" ( ulInitialFPSCR ) : "memory" );
+ }
+
+#endif /* configUSE_TASK_FPU_SUPPORT */
+/*-----------------------------------------------------------*/
+
+void vPortClearInterruptMask( uint32_t ulNewMaskValue )
+{
+ if( ulNewMaskValue == pdFALSE )
+ {
+ portCLEAR_INTERRUPT_MASK();
+ }
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulPortSetInterruptMask( void )
+{
+ uint32_t ulReturn;
+
+ /* Interrupt in the CPU must be turned off while the ICCPMR is being
+ * updated. */
+ portCPU_IRQ_DISABLE();
+
+ if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
+ {
+ /* Interrupts were already masked. */
+ ulReturn = pdTRUE;
+ }
+ else
+ {
+ ulReturn = pdFALSE;
+ portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+ __asm volatile ( "dsb \n"
+ "isb \n"::: "memory" );
+ }
+
+ portCPU_IRQ_ENABLE();
+
+ return ulReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configASSERT_DEFINED == 1 )
+
+ void vPortValidateInterruptPriority( void )
+ {
+ /* The following assertion will fail if a service routine (ISR) for
+ * an interrupt that has been assigned a priority above
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+ * function. ISR safe FreeRTOS API functions must *only* be called
+ * from interrupts that have been assigned a priority at or below
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Numerically low interrupt priority numbers represent logically high
+ * interrupt priorities, therefore the priority of the interrupt must
+ * be set to a value equal to or numerically *higher* than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * FreeRTOS maintains separate thread and ISR API functions to ensure
+ * interrupt entry is as fast and simple as possible. */
+
+ configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
+
+ /* Priority grouping: The interrupt controller (GIC) allows the bits
+ * that define each interrupt's priority to be split between bits that
+ * define the interrupt's pre-emption priority bits and bits that define
+ * the interrupt's sub-priority. For simplicity all bits must be defined
+ * to be pre-emption priority bits. The following assertion will fail if
+ * this is not the case (if some bits represent a sub-priority).
+ *
+ * The priority grouping is configured by the GIC's binary point register
+ * (ICCBPR). Writing 0 to ICCBPR will ensure it is set to its lowest
+ * possible value (which may be above 0). */
+ configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
+ }
+
+#endif /* configASSERT_DEFINED */
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CR5/portASM.S b/portable/GCC/ARM_CR5/portASM.S
index 02d0457..c44ea6b 100644
--- a/portable/GCC/ARM_CR5/portASM.S
+++ b/portable/GCC/ARM_CR5/portASM.S
@@ -1,318 +1,313 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
- .text
- .arm
-
- .set SYS_MODE, 0x1f
- .set SVC_MODE, 0x13
- .set IRQ_MODE, 0x12
-
- /* Hardware registers. */
- .extern ulICCIAR
- .extern ulICCEOIR
- .extern ulICCPMR
-
- /* Variables and functions. */
- .extern ulMaxAPIPriorityMask
- .extern _freertos_vector_table
- .extern pxCurrentTCB
- .extern vTaskSwitchContext
- .extern vApplicationIRQHandler
- .extern ulPortInterruptNesting
- .extern ulPortTaskHasFPUContext
-
- .global FreeRTOS_IRQ_Handler
- .global FreeRTOS_SWI_Handler
- .global vPortRestoreTaskContext
-
-.macro portSAVE_CONTEXT
-
- /* Save the LR and SPSR onto the system mode stack before switching to
- system mode to save the remaining system mode registers. */
- SRSDB sp!, #SYS_MODE
- CPS #SYS_MODE
- PUSH {R0-R12, R14}
-
- /* Push the critical nesting count. */
- LDR R2, ulCriticalNestingConst
- LDR R1, [R2]
- PUSH {R1}
-
- /* Does the task have a floating point context that needs saving? If
- ulPortTaskHasFPUContext is 0 then no. */
- LDR R2, ulPortTaskHasFPUContextConst
- LDR R3, [R2]
- CMP R3, #0
-
- /* Save the floating point context, if any. */
- FMRXNE R1, FPSCR
- VPUSHNE {D0-D15}
- /*VPUSHNE {D16-D31}*/
- PUSHNE {R1}
-
- /* Save ulPortTaskHasFPUContext itself. */
- PUSH {R3}
-
- /* Save the stack pointer in the TCB. */
- LDR R0, pxCurrentTCBConst
- LDR R1, [R0]
- STR SP, [R1]
-
- .endm
-
-; /**********************************************************************/
-
-.macro portRESTORE_CONTEXT
-
- /* Set the SP to point to the stack of the task being restored. */
- LDR R0, pxCurrentTCBConst
- LDR R1, [R0]
- LDR SP, [R1]
-
- /* Is there a floating point context to restore? If the restored
- ulPortTaskHasFPUContext is zero then no. */
- LDR R0, ulPortTaskHasFPUContextConst
- POP {R1}
- STR R1, [R0]
- CMP R1, #0
-
- /* Restore the floating point context, if any. */
- POPNE {R0}
- /*VPOPNE {D16-D31}*/
- VPOPNE {D0-D15}
- VMSRNE FPSCR, R0
-
- /* Restore the critical section nesting depth. */
- LDR R0, ulCriticalNestingConst
- POP {R1}
- STR R1, [R0]
-
- /* Ensure the priority mask is correct for the critical nesting depth. */
- LDR R2, ulICCPMRConst
- LDR R2, [R2]
- CMP R1, #0
- MOVEQ R4, #255
- LDRNE R4, ulMaxAPIPriorityMaskConst
- LDRNE R4, [R4]
- STR R4, [R2]
-
- /* Restore all system mode registers other than the SP (which is already
- being used). */
- POP {R0-R12, R14}
-
- /* Return to the task code, loading CPSR on the way. */
- RFEIA sp!
-
- .endm
-
-
-
-
-/******************************************************************************
- * SVC handler is used to start the scheduler.
- *****************************************************************************/
-.align 4
-.type FreeRTOS_SWI_Handler, %function
-FreeRTOS_SWI_Handler:
- /* Save the context of the current task and select a new task to run. */
- portSAVE_CONTEXT
- LDR R0, vTaskSwitchContextConst
- BLX R0
- portRESTORE_CONTEXT
-
-
-/******************************************************************************
- * vPortRestoreTaskContext is used to start the scheduler.
- *****************************************************************************/
-.type vPortRestoreTaskContext, %function
-vPortRestoreTaskContext:
- /* Switch to system mode. */
- CPS #SYS_MODE
- portRESTORE_CONTEXT
-
-.align 4
-.type FreeRTOS_IRQ_Handler, %function
-FreeRTOS_IRQ_Handler:
-
- /* Return to the interrupted instruction. */
- SUB lr, lr, #4
-
- /* Push the return address and SPSR. */
- PUSH {lr}
- MRS lr, SPSR
- PUSH {lr}
-
- /* Change to supervisor mode to allow reentry. */
- CPS #SVC_MODE
-
- /* Push used registers. */
- PUSH {r0-r4, r12}
-
- /* Increment nesting count. r3 holds the address of ulPortInterruptNesting
- for future use. r1 holds the original ulPortInterruptNesting value for
- future use. */
- LDR r3, ulPortInterruptNestingConst
- LDR r1, [r3]
- ADD r4, r1, #1
- STR r4, [r3]
-
- /* Read value from the interrupt acknowledge register, which is stored in r0
- for future parameter and interrupt clearing use. */
- LDR r2, ulICCIARConst
- LDR r2, [r2]
- LDR r0, [r2]
-
- /* Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for
- future use. _RB_ Is this ever needed provided the start of the stack is
- alligned on an 8-byte boundary? */
- MOV r2, sp
- AND r2, r2, #4
- SUB sp, sp, r2
-
- /* Call the interrupt handler. */
- PUSH {r0-r4, lr}
- LDR r1, vApplicationIRQHandlerConst
- BLX r1
- POP {r0-r4, lr}
- ADD sp, sp, r2
-
- CPSID i
- DSB
- ISB
-
- /* Write the value read from ICCIAR to ICCEOIR. */
- LDR r4, ulICCEOIRConst
- LDR r4, [r4]
- STR r0, [r4]
-
- /* Restore the old nesting count. */
- STR r1, [r3]
-
- /* A context switch is never performed if the nesting count is not 0. */
- CMP r1, #0
- BNE exit_without_switch
-
- /* Did the interrupt request a context switch? r1 holds the address of
- ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
- use. */
- LDR r1, =ulPortYieldRequired
- LDR r0, [r1]
- CMP r0, #0
- BNE switch_before_exit
-
-exit_without_switch:
- /* No context switch. Restore used registers, LR_irq and SPSR before
- returning. */
- POP {r0-r4, r12}
- CPS #IRQ_MODE
- POP {LR}
- MSR SPSR_cxsf, LR
- POP {LR}
- MOVS PC, LR
-
-switch_before_exit:
- /* A context swtich is to be performed. Clear the context switch pending
- flag. */
- MOV r0, #0
- STR r0, [r1]
-
- /* Restore used registers, LR-irq and SPSR before saving the context
- to the task stack. */
- POP {r0-r4, r12}
- CPS #IRQ_MODE
- POP {LR}
- MSR SPSR_cxsf, LR
- POP {LR}
- portSAVE_CONTEXT
-
- /* Call the function that selects the new task to execute.
- vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
- instructions, or 8 byte aligned stack allocated data. LR does not need
- saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */
- LDR R0, vTaskSwitchContextConst
- BLX R0
-
- /* Restore the context of, and branch to, the task selected to execute
- next. */
- portRESTORE_CONTEXT
-
-/******************************************************************************
- * If the application provides an implementation of vApplicationIRQHandler(),
- * then it will get called directly without saving the FPU registers on
- * interrupt entry, and this weak implementation of
- * vApplicationIRQHandler() will not get called.
- *
- * If the application provides its own implementation of
- * vApplicationFPUSafeIRQHandler() then this implementation of
- * vApplicationIRQHandler() will be called, save the FPU registers, and then
- * call vApplicationFPUSafeIRQHandler().
- *
- * Therefore, if the application writer wants FPU registers to be saved on
- * interrupt entry their IRQ handler must be called
- * vApplicationFPUSafeIRQHandler(), and if the application writer does not want
- * FPU registers to be saved on interrupt entry their IRQ handler must be
- * called vApplicationIRQHandler().
- *****************************************************************************/
-
-.align 4
-.weak vApplicationIRQHandler
-.type vApplicationIRQHandler, %function
-vApplicationIRQHandler:
- PUSH {LR}
- FMRX R1, FPSCR
- VPUSH {D0-D15}
- PUSH {R1}
-
- LDR r1, vApplicationFPUSafeIRQHandlerConst
- BLX r1
-
- POP {R0}
- VPOP {D0-D15}
- VMSR FPSCR, R0
-
- POP {PC}
-
-ulICCIARConst: .word ulICCIAR
-ulICCEOIRConst: .word ulICCEOIR
-ulICCPMRConst: .word ulICCPMR
-pxCurrentTCBConst: .word pxCurrentTCB
-ulCriticalNestingConst: .word ulCriticalNesting
-ulPortTaskHasFPUContextConst: .word ulPortTaskHasFPUContext
-ulMaxAPIPriorityMaskConst: .word ulMaxAPIPriorityMask
-vTaskSwitchContextConst: .word vTaskSwitchContext
-vApplicationIRQHandlerConst: .word vApplicationIRQHandler
-ulPortInterruptNestingConst: .word ulPortInterruptNesting
-vApplicationFPUSafeIRQHandlerConst: .word vApplicationFPUSafeIRQHandler
-
-.end
-
-
-
-
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+ .text
+ .arm
+
+ .set SYS_MODE, 0x1f
+ .set SVC_MODE, 0x13
+ .set IRQ_MODE, 0x12
+
+ /* Hardware registers. */
+ .extern ulICCIAR
+ .extern ulICCEOIR
+ .extern ulICCPMR
+
+ /* Variables and functions. */
+ .extern ulMaxAPIPriorityMask
+ .extern _freertos_vector_table
+ .extern pxCurrentTCB
+ .extern vTaskSwitchContext
+ .extern vApplicationIRQHandler
+ .extern ulPortInterruptNesting
+ .extern ulPortTaskHasFPUContext
+
+ .global FreeRTOS_IRQ_Handler
+ .global FreeRTOS_SWI_Handler
+ .global vPortRestoreTaskContext
+
+.macro portSAVE_CONTEXT
+
+ /* Save the LR and SPSR onto the system mode stack before switching to
+ system mode to save the remaining system mode registers. */
+ SRSDB sp!, #SYS_MODE
+ CPS #SYS_MODE
+ PUSH {R0-R12, R14}
+
+ /* Push the critical nesting count. */
+ LDR R2, ulCriticalNestingConst
+ LDR R1, [R2]
+ PUSH {R1}
+
+ /* Does the task have a floating point context that needs saving? If
+ ulPortTaskHasFPUContext is 0 then no. */
+ LDR R2, ulPortTaskHasFPUContextConst
+ LDR R3, [R2]
+ CMP R3, #0
+
+ /* Save the floating point context, if any. */
+ FMRXNE R1, FPSCR
+ VPUSHNE {D0-D15}
+ /*VPUSHNE {D16-D31}*/
+ PUSHNE {R1}
+
+ /* Save ulPortTaskHasFPUContext itself. */
+ PUSH {R3}
+
+ /* Save the stack pointer in the TCB. */
+ LDR R0, pxCurrentTCBConst
+ LDR R1, [R0]
+ STR SP, [R1]
+
+ .endm
+
+; /**********************************************************************/
+
+.macro portRESTORE_CONTEXT
+
+ /* Set the SP to point to the stack of the task being restored. */
+ LDR R0, pxCurrentTCBConst
+ LDR R1, [R0]
+ LDR SP, [R1]
+
+ /* Is there a floating point context to restore? If the restored
+ ulPortTaskHasFPUContext is zero then no. */
+ LDR R0, ulPortTaskHasFPUContextConst
+ POP {R1}
+ STR R1, [R0]
+ CMP R1, #0
+
+ /* Restore the floating point context, if any. */
+ POPNE {R0}
+ /*VPOPNE {D16-D31}*/
+ VPOPNE {D0-D15}
+ VMSRNE FPSCR, R0
+
+ /* Restore the critical section nesting depth. */
+ LDR R0, ulCriticalNestingConst
+ POP {R1}
+ STR R1, [R0]
+
+ /* Ensure the priority mask is correct for the critical nesting depth. */
+ LDR R2, ulICCPMRConst
+ LDR R2, [R2]
+ CMP R1, #0
+ MOVEQ R4, #255
+ LDRNE R4, ulMaxAPIPriorityMaskConst
+ LDRNE R4, [R4]
+ STR R4, [R2]
+
+ /* Restore all system mode registers other than the SP (which is already
+ being used). */
+ POP {R0-R12, R14}
+
+ /* Return to the task code, loading CPSR on the way. */
+ RFEIA sp!
+
+ .endm
+
+
+
+
+/******************************************************************************
+ * SVC handler is used to start the scheduler.
+ *****************************************************************************/
+.align 4
+.type FreeRTOS_SWI_Handler, %function
+FreeRTOS_SWI_Handler:
+ /* Save the context of the current task and select a new task to run. */
+ portSAVE_CONTEXT
+ LDR R0, vTaskSwitchContextConst
+ BLX R0
+ portRESTORE_CONTEXT
+
+
+/******************************************************************************
+ * vPortRestoreTaskContext is used to start the scheduler.
+ *****************************************************************************/
+.type vPortRestoreTaskContext, %function
+vPortRestoreTaskContext:
+ /* Switch to system mode. */
+ CPS #SYS_MODE
+ portRESTORE_CONTEXT
+
+.align 4
+.type FreeRTOS_IRQ_Handler, %function
+FreeRTOS_IRQ_Handler:
+
+ /* Return to the interrupted instruction. */
+ SUB lr, lr, #4
+
+ /* Push the return address and SPSR. */
+ PUSH {lr}
+ MRS lr, SPSR
+ PUSH {lr}
+
+ /* Change to supervisor mode to allow reentry. */
+ CPS #SVC_MODE
+
+ /* Push used registers. */
+ PUSH {r0-r4, r12}
+
+ /* Increment nesting count. r3 holds the address of ulPortInterruptNesting
+ for future use. r1 holds the original ulPortInterruptNesting value for
+ future use. */
+ LDR r3, ulPortInterruptNestingConst
+ LDR r1, [r3]
+ ADD r4, r1, #1
+ STR r4, [r3]
+
+ /* Read value from the interrupt acknowledge register, which is stored in r0
+ for future parameter and interrupt clearing use. */
+ LDR r2, ulICCIARConst
+ LDR r2, [r2]
+ LDR r0, [r2]
+
+ /* Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for
+ future use. _RB_ Is this ever needed provided the start of the stack is
+ alligned on an 8-byte boundary? */
+ MOV r2, sp
+ AND r2, r2, #4
+ SUB sp, sp, r2
+
+ /* Call the interrupt handler. */
+ PUSH {r0-r4, lr}
+ LDR r1, vApplicationIRQHandlerConst
+ BLX r1
+ POP {r0-r4, lr}
+ ADD sp, sp, r2
+
+ CPSID i
+ DSB
+ ISB
+
+ /* Write the value read from ICCIAR to ICCEOIR. */
+ LDR r4, ulICCEOIRConst
+ LDR r4, [r4]
+ STR r0, [r4]
+
+ /* Restore the old nesting count. */
+ STR r1, [r3]
+
+ /* A context switch is never performed if the nesting count is not 0. */
+ CMP r1, #0
+ BNE exit_without_switch
+
+ /* Did the interrupt request a context switch? r1 holds the address of
+ ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
+ use. */
+ LDR r1, =ulPortYieldRequired
+ LDR r0, [r1]
+ CMP r0, #0
+ BNE switch_before_exit
+
+exit_without_switch:
+ /* No context switch. Restore used registers, LR_irq and SPSR before
+ returning. */
+ POP {r0-r4, r12}
+ CPS #IRQ_MODE
+ POP {LR}
+ MSR SPSR_cxsf, LR
+ POP {LR}
+ MOVS PC, LR
+
+switch_before_exit:
+ /* A context swtich is to be performed. Clear the context switch pending
+ flag. */
+ MOV r0, #0
+ STR r0, [r1]
+
+ /* Restore used registers, LR-irq and SPSR before saving the context
+ to the task stack. */
+ POP {r0-r4, r12}
+ CPS #IRQ_MODE
+ POP {LR}
+ MSR SPSR_cxsf, LR
+ POP {LR}
+ portSAVE_CONTEXT
+
+ /* Call the function that selects the new task to execute.
+ vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
+ instructions, or 8 byte aligned stack allocated data. LR does not need
+ saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */
+ LDR R0, vTaskSwitchContextConst
+ BLX R0
+
+ /* Restore the context of, and branch to, the task selected to execute
+ next. */
+ portRESTORE_CONTEXT
+
+/******************************************************************************
+ * If the application provides an implementation of vApplicationIRQHandler(),
+ * then it will get called directly without saving the FPU registers on
+ * interrupt entry, and this weak implementation of
+ * vApplicationIRQHandler() will not get called.
+ *
+ * If the application provides its own implementation of
+ * vApplicationFPUSafeIRQHandler() then this implementation of
+ * vApplicationIRQHandler() will be called, save the FPU registers, and then
+ * call vApplicationFPUSafeIRQHandler().
+ *
+ * Therefore, if the application writer wants FPU registers to be saved on
+ * interrupt entry their IRQ handler must be called
+ * vApplicationFPUSafeIRQHandler(), and if the application writer does not want
+ * FPU registers to be saved on interrupt entry their IRQ handler must be
+ * called vApplicationIRQHandler().
+ *****************************************************************************/
+
+.align 4
+.weak vApplicationIRQHandler
+.type vApplicationIRQHandler, %function
+vApplicationIRQHandler:
+ PUSH {LR}
+ FMRX R1, FPSCR
+ VPUSH {D0-D15}
+ PUSH {R1}
+
+ LDR r1, vApplicationFPUSafeIRQHandlerConst
+ BLX r1
+
+ POP {R0}
+ VPOP {D0-D15}
+ VMSR FPSCR, R0
+
+ POP {PC}
+
+ulICCIARConst: .word ulICCIAR
+ulICCEOIRConst: .word ulICCEOIR
+ulICCPMRConst: .word ulICCPMR
+pxCurrentTCBConst: .word pxCurrentTCB
+ulCriticalNestingConst: .word ulCriticalNesting
+ulPortTaskHasFPUContextConst: .word ulPortTaskHasFPUContext
+ulMaxAPIPriorityMaskConst: .word ulMaxAPIPriorityMask
+vTaskSwitchContextConst: .word vTaskSwitchContext
+vApplicationIRQHandlerConst: .word vApplicationIRQHandler
+ulPortInterruptNestingConst: .word ulPortInterruptNesting
+vApplicationFPUSafeIRQHandlerConst: .word vApplicationFPUSafeIRQHandler
+
+.end
diff --git a/portable/GCC/ARM_CR5/portmacro.h b/portable/GCC/ARM_CR5/portmacro.h
index 5cc4166..4bd25bb 100644
--- a/portable/GCC/ARM_CR5/portmacro.h
+++ b/portable/GCC/ARM_CR5/portmacro.h
@@ -1,204 +1,204 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef PORTMACRO_H
- #define PORTMACRO_H
-
- #ifdef __cplusplus
- extern "C" {
- #endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
-
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
-
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
-
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-
-/* Called at the end of an ISR that can cause a context switch. */
- #define portEND_SWITCHING_ISR( xSwitchRequired ) \
- { \
- extern uint32_t ulPortYieldRequired; \
- \
- if( xSwitchRequired != pdFALSE ) \
- { \
- ulPortYieldRequired = pdTRUE; \
- } \
- }
-
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
- #define portYIELD() __asm volatile ( "SWI 0" ::: "memory" );
-
-
-/*-----------------------------------------------------------
-* Critical section control
-*----------------------------------------------------------*/
-
- extern void vPortEnterCritical( void );
- extern void vPortExitCritical( void );
- extern uint32_t ulPortSetInterruptMask( void );
- extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
- extern void vPortInstallFreeRTOSVectorTable( void );
-
-/* These macros do not globally disable/enable interrupts. They do mask off
- * interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
- #define portENTER_CRITICAL() vPortEnterCritical();
- #define portEXIT_CRITICAL() vPortExitCritical();
- #define portDISABLE_INTERRUPTS() ulPortSetInterruptMask()
- #define portENABLE_INTERRUPTS() vPortClearInterruptMask( 0 )
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortClearInterruptMask( x )
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. These are
- * not required for this port but included in case common demo code that uses these
- * macros is used. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
-
-/* Prototype of the FreeRTOS tick handler. This must be installed as the
- * handler for whichever peripheral is used to generate the RTOS tick. */
- void FreeRTOS_Tick_Handler( void );
-
-/* If configUSE_TASK_FPU_SUPPORT is set to 1 (or left undefined) then tasks are
-created without an FPU context and must call vPortTaskUsesFPU() to give
-themselves an FPU context before using any FPU instructions. If
-configUSE_TASK_FPU_SUPPORT is set to 2 then all tasks will have an FPU context
-by default. */
-#if( configUSE_TASK_FPU_SUPPORT != 2 )
- void vPortTaskUsesFPU( void );
-#else
- /* Each task has an FPU context already, so define this function away to
- nothing to prevent it being called accidentally. */
- #define vPortTaskUsesFPU()
-#endif /* configUSE_TASK_FPU_SUPPORT */
- #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
-
- #define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
- #define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
-
-/* Architecture specific optimisations. */
- #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
- #endif
-
- #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
-/* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-/*-----------------------------------------------------------*/
-
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) )
-
- #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
- #ifdef configASSERT
- void vPortValidateInterruptPriority( void );
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
- #endif /* configASSERT */
-
- #define portNOP() __asm volatile ( "NOP" )
-
-
- #ifdef __cplusplus
- } /* extern C */
- #endif
-
-
-/* The number of bits to shift for an interrupt priority is dependent on the
- * number of bits implemented by the interrupt controller. */
- #if configUNIQUE_INTERRUPT_PRIORITIES == 16
- #define portPRIORITY_SHIFT 4
- #define portMAX_BINARY_POINT_VALUE 3
- #elif configUNIQUE_INTERRUPT_PRIORITIES == 32
- #define portPRIORITY_SHIFT 3
- #define portMAX_BINARY_POINT_VALUE 2
- #elif configUNIQUE_INTERRUPT_PRIORITIES == 64
- #define portPRIORITY_SHIFT 2
- #define portMAX_BINARY_POINT_VALUE 1
- #elif configUNIQUE_INTERRUPT_PRIORITIES == 128
- #define portPRIORITY_SHIFT 1
- #define portMAX_BINARY_POINT_VALUE 0
- #elif configUNIQUE_INTERRUPT_PRIORITIES == 256
- #define portPRIORITY_SHIFT 0
- #define portMAX_BINARY_POINT_VALUE 0
- #else /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */
- #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
- #endif /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */
-
-/* Interrupt controller access addresses. */
- #define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 )
- #define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C )
- #define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 )
- #define portICCBPR_BINARY_POINT_OFFSET ( 0x08 )
- #define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 )
-
- #define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
- #define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
- #define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
- #define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
- #define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
- #define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
- #define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
-
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
-
-#endif /* PORTMACRO_H */
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+ #define PORTMACRO_H
+
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+ #define portCHAR char
+ #define portFLOAT float
+ #define portDOUBLE double
+ #define portLONG long
+ #define portSHORT short
+ #define portSTACK_TYPE uint32_t
+ #define portBASE_TYPE long
+
+ typedef portSTACK_TYPE StackType_t;
+ typedef long BaseType_t;
+ typedef unsigned long UBaseType_t;
+
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+ #define portSTACK_GROWTH ( -1 )
+ #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+ #define portBYTE_ALIGNMENT 8
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+/* Called at the end of an ISR that can cause a context switch. */
+ #define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ { \
+ extern uint32_t ulPortYieldRequired; \
+ \
+ if( xSwitchRequired != pdFALSE ) \
+ { \
+ ulPortYieldRequired = pdTRUE; \
+ } \
+ }
+
+ #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+ #define portYIELD() __asm volatile ( "SWI 0" ::: "memory" );
+
+
+/*-----------------------------------------------------------
+* Critical section control
+*----------------------------------------------------------*/
+
+ extern void vPortEnterCritical( void );
+ extern void vPortExitCritical( void );
+ extern uint32_t ulPortSetInterruptMask( void );
+ extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
+ extern void vPortInstallFreeRTOSVectorTable( void );
+
+/* These macros do not globally disable/enable interrupts. They do mask off
+ * interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
+ #define portENTER_CRITICAL() vPortEnterCritical();
+ #define portEXIT_CRITICAL() vPortExitCritical();
+ #define portDISABLE_INTERRUPTS() ulPortSetInterruptMask()
+ #define portENABLE_INTERRUPTS() vPortClearInterruptMask( 0 )
+ #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask()
+ #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortClearInterruptMask( x )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. These are
+ * not required for this port but included in case common demo code that uses these
+ * macros is used. */
+ #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+ #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+
+/* Prototype of the FreeRTOS tick handler. This must be installed as the
+ * handler for whichever peripheral is used to generate the RTOS tick. */
+ void FreeRTOS_Tick_Handler( void );
+
+/* If configUSE_TASK_FPU_SUPPORT is set to 1 (or left undefined) then tasks are
+created without an FPU context and must call vPortTaskUsesFPU() to give
+themselves an FPU context before using any FPU instructions. If
+configUSE_TASK_FPU_SUPPORT is set to 2 then all tasks will have an FPU context
+by default. */
+#if( configUSE_TASK_FPU_SUPPORT != 2 )
+ void vPortTaskUsesFPU( void );
+#else
+ /* Each task has an FPU context already, so define this function away to
+ nothing to prevent it being called accidentally. */
+ #define vPortTaskUsesFPU()
+#endif /* configUSE_TASK_FPU_SUPPORT */
+ #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+
+ #define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
+ #define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
+
+/* Architecture specific optimisations. */
+ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+ #endif
+
+ #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+/* Store/clear the ready priorities in a bit map. */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/*-----------------------------------------------------------*/
+
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) )
+
+ #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+ #ifdef configASSERT
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+ #endif /* configASSERT */
+
+ #define portNOP() __asm volatile ( "NOP" )
+
+
+ #ifdef __cplusplus
+ } /* extern C */
+ #endif
+
+
+/* The number of bits to shift for an interrupt priority is dependent on the
+ * number of bits implemented by the interrupt controller. */
+ #if configUNIQUE_INTERRUPT_PRIORITIES == 16
+ #define portPRIORITY_SHIFT 4
+ #define portMAX_BINARY_POINT_VALUE 3
+ #elif configUNIQUE_INTERRUPT_PRIORITIES == 32
+ #define portPRIORITY_SHIFT 3
+ #define portMAX_BINARY_POINT_VALUE 2
+ #elif configUNIQUE_INTERRUPT_PRIORITIES == 64
+ #define portPRIORITY_SHIFT 2
+ #define portMAX_BINARY_POINT_VALUE 1
+ #elif configUNIQUE_INTERRUPT_PRIORITIES == 128
+ #define portPRIORITY_SHIFT 1
+ #define portMAX_BINARY_POINT_VALUE 0
+ #elif configUNIQUE_INTERRUPT_PRIORITIES == 256
+ #define portPRIORITY_SHIFT 0
+ #define portMAX_BINARY_POINT_VALUE 0
+ #else /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */
+ #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
+ #endif /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */
+
+/* Interrupt controller access addresses. */
+ #define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 )
+ #define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C )
+ #define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 )
+ #define portICCBPR_BINARY_POINT_OFFSET ( 0x08 )
+ #define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 )
+
+ #define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
+ #define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
+ #define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
+ #define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
+ #define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
+ #define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
+ #define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
+
+ #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+
+#endif /* PORTMACRO_H */
diff --git a/portable/GCC/ARM_CRx_No_GIC/port.c b/portable/GCC/ARM_CRx_No_GIC/port.c
index 6037a10..74d9563 100644
--- a/portable/GCC/ARM_CRx_No_GIC/port.c
+++ b/portable/GCC/ARM_CRx_No_GIC/port.c
@@ -1,320 +1,318 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/* Standard includes. */
-#include <stdlib.h>
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
- /* Check the configuration. */
- #if( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-#ifndef configSETUP_TICK_INTERRUPT
- #error configSETUP_TICK_INTERRUPT() must be defined in FreeRTOSConfig.h to call the function that sets up the tick interrupt.
-#endif
-
-#ifndef configCLEAR_TICK_INTERRUPT
- #error configCLEAR_TICK_INTERRUPT must be defined in FreeRTOSConfig.h to clear which ever interrupt was used to generate the tick interrupt.
-#endif
-
-/* A critical section is exited when the critical section nesting count reaches
-this value. */
-#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
-
-/* Tasks are not created with a floating point context, but can be given a
-floating point context after they have been created. A variable is stored as
-part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
-does not have an FPU context, or any other value if the task does have an FPU
-context. */
-#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
-
-/* Constants required to setup the initial task context. */
-#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
-#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
-#define portTHUMB_MODE_ADDRESS ( 0x01UL )
-
-/* Masks all bits in the APSR other than the mode bits. */
-#define portAPSR_MODE_BITS_MASK ( 0x1F )
-
-/* The value of the mode bits in the APSR when the CPU is executing in user
-mode. */
-#define portAPSR_USER_MODE ( 0x10 )
-
-/* Let the user override the pre-loading of the initial LR with the address of
-prvTaskExitError() in case it messes up unwinding of the stack in the
-debugger. */
-#ifdef configTASK_RETURN_ADDRESS
- #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
-#else
- #define portTASK_RETURN_ADDRESS prvTaskExitError
-#endif
-
-/*-----------------------------------------------------------*/
-
-/*
- * Starts the first task executing. This function is necessarily written in
- * assembly code so is implemented in portASM.s.
- */
-extern void vPortRestoreTaskContext( void );
-
-/*
- * Used to catch tasks that attempt to return from their implementing function.
- */
-static void prvTaskExitError( void );
-
-/*-----------------------------------------------------------*/
-
-/* A variable is used to keep track of the critical section nesting. This
-variable has to be stored as part of the task context and must be initialised to
-a non zero value to ensure interrupts don't inadvertently become unmasked before
-the scheduler starts. As it is stored as part of the task context it will
-automatically be set to 0 when the first task is started. */
-volatile uint32_t ulCriticalNesting = 9999UL;
-
-/* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then
-a floating point context must be saved and restored for the task. */
-volatile uint32_t ulPortTaskHasFPUContext = pdFALSE;
-
-/* Set to 1 to pend a context switch from an ISR. */
-volatile uint32_t ulPortYieldRequired = pdFALSE;
-
-/* Counts the interrupt nesting depth. A context switch is only performed if
-if the nesting depth is 0. */
-volatile uint32_t ulPortInterruptNesting = 0UL;
-
-/* Used in the asm file to clear an interrupt. */
-__attribute__(( used )) const uint32_t ulICCEOIR = configEOI_ADDRESS;
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
- /* Setup the initial stack of the task. The stack is set exactly as
- expected by the portRESTORE_CONTEXT() macro.
-
- The fist real value on the stack is the status register, which is set for
- system mode, with interrupts enabled. A few NULLs are added first to ensure
- GDB does not try decoding a non-existent return address. */
- *pxTopOfStack = ( StackType_t ) NULL;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) NULL;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) NULL;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
-
- if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
- {
- /* The task will start in THUMB mode. */
- *pxTopOfStack |= portTHUMB_MODE_BIT;
- }
-
- pxTopOfStack--;
-
- /* Next the return address, which in this case is the start of the task. */
- *pxTopOfStack = ( StackType_t ) pxCode;
- pxTopOfStack--;
-
- /* Next all the registers other than the stack pointer. */
- *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack--;
-
- /* The task will start with a critical nesting count of 0 as interrupts are
- enabled. */
- *pxTopOfStack = portNO_CRITICAL_NESTING;
- pxTopOfStack--;
-
- /* The task will start without a floating point context. A task that uses
- the floating point hardware must call vPortTaskUsesFPU() before executing
- any floating point instructions. */
- *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
-
- return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
- /* A function that implements a task must not exit or attempt to return to
- its caller as there is nothing to return to. If a task wants to exit it
- should instead call vTaskDelete( NULL ).
-
- Artificially force an assert() to be triggered if configASSERT() is
- defined, then stop here so application writers can catch the error. */
- configASSERT( ulPortInterruptNesting == ~0UL );
- portDISABLE_INTERRUPTS();
- for( ;; );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-uint32_t ulAPSR;
-
- /* Only continue if the CPU is not in User mode. The CPU must be in a
- Privileged mode for the scheduler to start. */
- __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) :: "memory" );
- ulAPSR &= portAPSR_MODE_BITS_MASK;
- configASSERT( ulAPSR != portAPSR_USER_MODE );
-
- if( ulAPSR != portAPSR_USER_MODE )
- {
- /* Start the timer that generates the tick ISR. */
- portDISABLE_INTERRUPTS();
- configSETUP_TICK_INTERRUPT();
-
- /* Start the first task executing. */
- vPortRestoreTaskContext();
- }
-
- /* Will only get here if vTaskStartScheduler() was called with the CPU in
- a non-privileged mode or the binary point register was not set to its lowest
- possible value. prvTaskExitError() is referenced to prevent a compiler
- warning about it being defined but not referenced in the case that the user
- defines their own exit address. */
- ( void ) prvTaskExitError;
- return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
- /* Not implemented in ports where there is nothing to return to.
- Artificially force an assert. */
- configASSERT( ulCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
- portDISABLE_INTERRUPTS();
-
- /* Now interrupts are disabled ulCriticalNesting can be accessed
- directly. Increment ulCriticalNesting to keep a count of how many times
- portENTER_CRITICAL() has been called. */
- ulCriticalNesting++;
-
- /* This is not the interrupt safe version of the enter critical function so
- assert() if it is being called from an interrupt context. Only API
- functions that end in "FromISR" can be used in an interrupt. Only assert if
- the critical nesting count is 1 to protect against recursive calls if the
- assert function also uses a critical section. */
- if( ulCriticalNesting == 1 )
- {
- configASSERT( ulPortInterruptNesting == 0 );
- }
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
- if( ulCriticalNesting > portNO_CRITICAL_NESTING )
- {
- /* Decrement the nesting count as the critical section is being
- exited. */
- ulCriticalNesting--;
-
- /* If the nesting level has reached zero then all interrupt
- priorities must be re-enabled. */
- if( ulCriticalNesting == portNO_CRITICAL_NESTING )
- {
- /* Critical nesting has reached zero so all interrupt priorities
- should be unmasked. */
- portENABLE_INTERRUPTS();
- }
- }
-}
-/*-----------------------------------------------------------*/
-
-void FreeRTOS_Tick_Handler( void )
-{
-uint32_t ulInterruptStatus;
-
- ulInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
-
- /* Increment the RTOS tick. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- ulPortYieldRequired = pdTRUE;
- }
-
- portCLEAR_INTERRUPT_MASK_FROM_ISR( ulInterruptStatus );
-
- configCLEAR_TICK_INTERRUPT();
-}
-/*-----------------------------------------------------------*/
-
-void vPortTaskUsesFPU( void )
-{
-uint32_t ulInitialFPSCR = 0;
-
- /* A task is registering the fact that it needs an FPU context. Set the
- FPU flag (which is saved as part of the task context). */
- ulPortTaskHasFPUContext = pdTRUE;
-
- /* Initialise the floating point status register. */
- __asm volatile ( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) : "memory" );
-}
-/*-----------------------------------------------------------*/
-
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+ /* Check the configuration. */
+ #if( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+#ifndef configSETUP_TICK_INTERRUPT
+ #error configSETUP_TICK_INTERRUPT() must be defined in FreeRTOSConfig.h to call the function that sets up the tick interrupt.
+#endif
+
+#ifndef configCLEAR_TICK_INTERRUPT
+ #error configCLEAR_TICK_INTERRUPT must be defined in FreeRTOSConfig.h to clear which ever interrupt was used to generate the tick interrupt.
+#endif
+
+/* A critical section is exited when the critical section nesting count reaches
+this value. */
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
+
+/* Tasks are not created with a floating point context, but can be given a
+floating point context after they have been created. A variable is stored as
+part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+does not have an FPU context, or any other value if the task does have an FPU
+context. */
+#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
+
+/* Constants required to setup the initial task context. */
+#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
+#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
+#define portTHUMB_MODE_ADDRESS ( 0x01UL )
+
+/* Masks all bits in the APSR other than the mode bits. */
+#define portAPSR_MODE_BITS_MASK ( 0x1F )
+
+/* The value of the mode bits in the APSR when the CPU is executing in user
+mode. */
+#define portAPSR_USER_MODE ( 0x10 )
+
+/* Let the user override the pre-loading of the initial LR with the address of
+prvTaskExitError() in case it messes up unwinding of the stack in the
+debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
+#else
+ #define portTASK_RETURN_ADDRESS prvTaskExitError
+#endif
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Starts the first task executing. This function is necessarily written in
+ * assembly code so is implemented in portASM.s.
+ */
+extern void vPortRestoreTaskContext( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* A variable is used to keep track of the critical section nesting. This
+variable has to be stored as part of the task context and must be initialised to
+a non zero value to ensure interrupts don't inadvertently become unmasked before
+the scheduler starts. As it is stored as part of the task context it will
+automatically be set to 0 when the first task is started. */
+volatile uint32_t ulCriticalNesting = 9999UL;
+
+/* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then
+a floating point context must be saved and restored for the task. */
+volatile uint32_t ulPortTaskHasFPUContext = pdFALSE;
+
+/* Set to 1 to pend a context switch from an ISR. */
+volatile uint32_t ulPortYieldRequired = pdFALSE;
+
+/* Counts the interrupt nesting depth. A context switch is only performed if
+if the nesting depth is 0. */
+volatile uint32_t ulPortInterruptNesting = 0UL;
+
+/* Used in the asm file to clear an interrupt. */
+__attribute__(( used )) const uint32_t ulICCEOIR = configEOI_ADDRESS;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+ /* Setup the initial stack of the task. The stack is set exactly as
+ expected by the portRESTORE_CONTEXT() macro.
+
+ The fist real value on the stack is the status register, which is set for
+ system mode, with interrupts enabled. A few NULLs are added first to ensure
+ GDB does not try decoding a non-existent return address. */
+ *pxTopOfStack = ( StackType_t ) NULL;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) NULL;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) NULL;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+
+ if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
+ {
+ /* The task will start in THUMB mode. */
+ *pxTopOfStack |= portTHUMB_MODE_BIT;
+ }
+
+ pxTopOfStack--;
+
+ /* Next the return address, which in this case is the start of the task. */
+ *pxTopOfStack = ( StackType_t ) pxCode;
+ pxTopOfStack--;
+
+ /* Next all the registers other than the stack pointer. */
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
+
+ /* The task will start with a critical nesting count of 0 as interrupts are
+ enabled. */
+ *pxTopOfStack = portNO_CRITICAL_NESTING;
+ pxTopOfStack--;
+
+ /* The task will start without a floating point context. A task that uses
+ the floating point hardware must call vPortTaskUsesFPU() before executing
+ any floating point instructions. */
+ *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+ /* A function that implements a task must not exit or attempt to return to
+ its caller as there is nothing to return to. If a task wants to exit it
+ should instead call vTaskDelete( NULL ).
+
+ Artificially force an assert() to be triggered if configASSERT() is
+ defined, then stop here so application writers can catch the error. */
+ configASSERT( ulPortInterruptNesting == ~0UL );
+ portDISABLE_INTERRUPTS();
+ for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+uint32_t ulAPSR;
+
+ /* Only continue if the CPU is not in User mode. The CPU must be in a
+ Privileged mode for the scheduler to start. */
+ __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) :: "memory" );
+ ulAPSR &= portAPSR_MODE_BITS_MASK;
+ configASSERT( ulAPSR != portAPSR_USER_MODE );
+
+ if( ulAPSR != portAPSR_USER_MODE )
+ {
+ /* Start the timer that generates the tick ISR. */
+ portDISABLE_INTERRUPTS();
+ configSETUP_TICK_INTERRUPT();
+
+ /* Start the first task executing. */
+ vPortRestoreTaskContext();
+ }
+
+ /* Will only get here if vTaskStartScheduler() was called with the CPU in
+ a non-privileged mode or the binary point register was not set to its lowest
+ possible value. prvTaskExitError() is referenced to prevent a compiler
+ warning about it being defined but not referenced in the case that the user
+ defines their own exit address. */
+ ( void ) prvTaskExitError;
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+ /* Not implemented in ports where there is nothing to return to.
+ Artificially force an assert. */
+ configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+ portDISABLE_INTERRUPTS();
+
+ /* Now interrupts are disabled ulCriticalNesting can be accessed
+ directly. Increment ulCriticalNesting to keep a count of how many times
+ portENTER_CRITICAL() has been called. */
+ ulCriticalNesting++;
+
+ /* This is not the interrupt safe version of the enter critical function so
+ assert() if it is being called from an interrupt context. Only API
+ functions that end in "FromISR" can be used in an interrupt. Only assert if
+ the critical nesting count is 1 to protect against recursive calls if the
+ assert function also uses a critical section. */
+ if( ulCriticalNesting == 1 )
+ {
+ configASSERT( ulPortInterruptNesting == 0 );
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+ if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+ {
+ /* Decrement the nesting count as the critical section is being
+ exited. */
+ ulCriticalNesting--;
+
+ /* If the nesting level has reached zero then all interrupt
+ priorities must be re-enabled. */
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+ {
+ /* Critical nesting has reached zero so all interrupt priorities
+ should be unmasked. */
+ portENABLE_INTERRUPTS();
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+void FreeRTOS_Tick_Handler( void )
+{
+uint32_t ulInterruptStatus;
+
+ ulInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+
+ /* Increment the RTOS tick. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ ulPortYieldRequired = pdTRUE;
+ }
+
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulInterruptStatus );
+
+ configCLEAR_TICK_INTERRUPT();
+}
+/*-----------------------------------------------------------*/
+
+void vPortTaskUsesFPU( void )
+{
+uint32_t ulInitialFPSCR = 0;
+
+ /* A task is registering the fact that it needs an FPU context. Set the
+ FPU flag (which is saved as part of the task context). */
+ ulPortTaskHasFPUContext = pdTRUE;
+
+ /* Initialise the floating point status register. */
+ __asm volatile ( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) : "memory" );
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CRx_No_GIC/portASM.S b/portable/GCC/ARM_CRx_No_GIC/portASM.S
index 9591146..bfb1573 100644
--- a/portable/GCC/ARM_CRx_No_GIC/portASM.S
+++ b/portable/GCC/ARM_CRx_No_GIC/portASM.S
@@ -1,265 +1,260 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
- .text
- .arm
-
- .set SYS_MODE, 0x1f
- .set SVC_MODE, 0x13
- .set IRQ_MODE, 0x12
-
- /* Variables and functions. */
- .extern ulMaxAPIPriorityMask
- .extern _freertos_vector_table
- .extern pxCurrentTCB
- .extern vTaskSwitchContext
- .extern vApplicationIRQHandler
- .extern ulPortInterruptNesting
- .extern ulPortTaskHasFPUContext
- .extern ulICCEOIR
- .extern ulPortYieldRequired
-
- .global FreeRTOS_IRQ_Handler
- .global FreeRTOS_SVC_Handler
- .global vPortRestoreTaskContext
-
-
-.macro portSAVE_CONTEXT
-
- /* Save the LR and SPSR onto the system mode stack before switching to
- system mode to save the remaining system mode registers. */
- SRSDB sp!, #SYS_MODE
- CPS #SYS_MODE
- PUSH {R0-R12, R14}
-
- /* Push the critical nesting count. */
- LDR R2, ulCriticalNestingConst
- LDR R1, [R2]
- PUSH {R1}
-
- /* Does the task have a floating point context that needs saving? If
- ulPortTaskHasFPUContext is 0 then no. */
- LDR R2, ulPortTaskHasFPUContextConst
- LDR R3, [R2]
- CMP R3, #0
-
- /* Save the floating point context, if any. */
- FMRXNE R1, FPSCR
- VPUSHNE {D0-D15}
-#if configFPU_D32 == 1
- VPUSHNE {D16-D31}
-#endif /* configFPU_D32 */
- PUSHNE {R1}
-
- /* Save ulPortTaskHasFPUContext itself. */
- PUSH {R3}
-
- /* Save the stack pointer in the TCB. */
- LDR R0, pxCurrentTCBConst
- LDR R1, [R0]
- STR SP, [R1]
-
- .endm
-
-; /**********************************************************************/
-
-.macro portRESTORE_CONTEXT
-
- /* Set the SP to point to the stack of the task being restored. */
- LDR R0, pxCurrentTCBConst
- LDR R1, [R0]
- LDR SP, [R1]
-
- /* Is there a floating point context to restore? If the restored
- ulPortTaskHasFPUContext is zero then no. */
- LDR R0, ulPortTaskHasFPUContextConst
- POP {R1}
- STR R1, [R0]
- CMP R1, #0
-
- /* Restore the floating point context, if any. */
- POPNE {R0}
-#if configFPU_D32 == 1
- VPOPNE {D16-D31}
-#endif /* configFPU_D32 */
- VPOPNE {D0-D15}
- VMSRNE FPSCR, R0
-
- /* Restore the critical section nesting depth. */
- LDR R0, ulCriticalNestingConst
- POP {R1}
- STR R1, [R0]
-
- /* Restore all system mode registers other than the SP (which is already
- being used). */
- POP {R0-R12, R14}
-
- /* Return to the task code, loading CPSR on the way. */
- RFEIA sp!
-
- .endm
-
-
-
-
-/******************************************************************************
- * SVC handler is used to yield.
- *****************************************************************************/
-.align 4
-.type FreeRTOS_SVC_Handler, %function
-FreeRTOS_SVC_Handler:
- /* Save the context of the current task and select a new task to run. */
- portSAVE_CONTEXT
- LDR R0, vTaskSwitchContextConst
- BLX R0
- portRESTORE_CONTEXT
-
-
-/******************************************************************************
- * vPortRestoreTaskContext is used to start the scheduler.
- *****************************************************************************/
-.align 4
-.type vPortRestoreTaskContext, %function
-vPortRestoreTaskContext:
- /* Switch to system mode. */
- CPS #SYS_MODE
- portRESTORE_CONTEXT
-
-.align 4
-.type FreeRTOS_IRQ_Handler, %function
-FreeRTOS_IRQ_Handler:
- /* Return to the interrupted instruction. */
- SUB lr, lr, #4
-
- /* Push the return address and SPSR. */
- PUSH {lr}
- MRS lr, SPSR
- PUSH {lr}
-
- /* Change to supervisor mode to allow reentry. */
- CPS #0x13
-
- /* Push used registers. */
- PUSH {r0-r3, r12}
-
- /* Increment nesting count. r3 holds the address of ulPortInterruptNesting
- for future use. r1 holds the original ulPortInterruptNesting value for
- future use. */
- LDR r3, ulPortInterruptNestingConst
- LDR r1, [r3]
- ADD r0, r1, #1
- STR r0, [r3]
-
- /* Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for
- future use. */
- MOV r0, sp
- AND r2, r0, #4
- SUB sp, sp, r2
-
- /* Call the interrupt handler. */
- PUSH {r0-r3, lr}
- LDR r1, vApplicationIRQHandlerConst
- BLX r1
- POP {r0-r3, lr}
- ADD sp, sp, r2
-
- CPSID i
- DSB
- ISB
-
- /* Write to the EOI register. */
- LDR r0, ulICCEOIRConst
- LDR r2, [r0]
- STR r0, [r2]
-
- /* Restore the old nesting count. */
- STR r1, [r3]
-
- /* A context switch is never performed if the nesting count is not 0. */
- CMP r1, #0
- BNE exit_without_switch
-
- /* Did the interrupt request a context switch? r1 holds the address of
- ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
- use. */
- LDR r1, ulPortYieldRequiredConst
- LDR r0, [r1]
- CMP r0, #0
- BNE switch_before_exit
-
-exit_without_switch:
- /* No context switch. Restore used registers, LR_irq and SPSR before
- returning. */
- POP {r0-r3, r12}
- CPS #IRQ_MODE
- POP {LR}
- MSR SPSR_cxsf, LR
- POP {LR}
- MOVS PC, LR
-
-switch_before_exit:
- /* A context swtich is to be performed. Clear the context switch pending
- flag. */
- MOV r0, #0
- STR r0, [r1]
-
- /* Restore used registers, LR-irq and SPSR before saving the context
- to the task stack. */
- POP {r0-r3, r12}
- CPS #IRQ_MODE
- POP {LR}
- MSR SPSR_cxsf, LR
- POP {LR}
- portSAVE_CONTEXT
-
- /* Call the function that selects the new task to execute.
- vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
- instructions, or 8 byte aligned stack allocated data. LR does not need
- saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */
- LDR R0, vTaskSwitchContextConst
- BLX R0
-
- /* Restore the context of, and branch to, the task selected to execute
- next. */
- portRESTORE_CONTEXT
-
-ulICCEOIRConst: .word ulICCEOIR
-pxCurrentTCBConst: .word pxCurrentTCB
-ulCriticalNestingConst: .word ulCriticalNesting
-ulPortTaskHasFPUContextConst: .word ulPortTaskHasFPUContext
-vTaskSwitchContextConst: .word vTaskSwitchContext
-vApplicationIRQHandlerConst: .word vApplicationIRQHandler
-ulPortInterruptNestingConst: .word ulPortInterruptNesting
-ulPortYieldRequiredConst: .word ulPortYieldRequired
-
-.end
-
-
-
-
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+ .text
+ .arm
+
+ .set SYS_MODE, 0x1f
+ .set SVC_MODE, 0x13
+ .set IRQ_MODE, 0x12
+
+ /* Variables and functions. */
+ .extern ulMaxAPIPriorityMask
+ .extern _freertos_vector_table
+ .extern pxCurrentTCB
+ .extern vTaskSwitchContext
+ .extern vApplicationIRQHandler
+ .extern ulPortInterruptNesting
+ .extern ulPortTaskHasFPUContext
+ .extern ulICCEOIR
+ .extern ulPortYieldRequired
+
+ .global FreeRTOS_IRQ_Handler
+ .global FreeRTOS_SVC_Handler
+ .global vPortRestoreTaskContext
+
+
+.macro portSAVE_CONTEXT
+
+ /* Save the LR and SPSR onto the system mode stack before switching to
+ system mode to save the remaining system mode registers. */
+ SRSDB sp!, #SYS_MODE
+ CPS #SYS_MODE
+ PUSH {R0-R12, R14}
+
+ /* Push the critical nesting count. */
+ LDR R2, ulCriticalNestingConst
+ LDR R1, [R2]
+ PUSH {R1}
+
+ /* Does the task have a floating point context that needs saving? If
+ ulPortTaskHasFPUContext is 0 then no. */
+ LDR R2, ulPortTaskHasFPUContextConst
+ LDR R3, [R2]
+ CMP R3, #0
+
+ /* Save the floating point context, if any. */
+ FMRXNE R1, FPSCR
+ VPUSHNE {D0-D15}
+#if configFPU_D32 == 1
+ VPUSHNE {D16-D31}
+#endif /* configFPU_D32 */
+ PUSHNE {R1}
+
+ /* Save ulPortTaskHasFPUContext itself. */
+ PUSH {R3}
+
+ /* Save the stack pointer in the TCB. */
+ LDR R0, pxCurrentTCBConst
+ LDR R1, [R0]
+ STR SP, [R1]
+
+ .endm
+
+; /**********************************************************************/
+
+.macro portRESTORE_CONTEXT
+
+ /* Set the SP to point to the stack of the task being restored. */
+ LDR R0, pxCurrentTCBConst
+ LDR R1, [R0]
+ LDR SP, [R1]
+
+ /* Is there a floating point context to restore? If the restored
+ ulPortTaskHasFPUContext is zero then no. */
+ LDR R0, ulPortTaskHasFPUContextConst
+ POP {R1}
+ STR R1, [R0]
+ CMP R1, #0
+
+ /* Restore the floating point context, if any. */
+ POPNE {R0}
+#if configFPU_D32 == 1
+ VPOPNE {D16-D31}
+#endif /* configFPU_D32 */
+ VPOPNE {D0-D15}
+ VMSRNE FPSCR, R0
+
+ /* Restore the critical section nesting depth. */
+ LDR R0, ulCriticalNestingConst
+ POP {R1}
+ STR R1, [R0]
+
+ /* Restore all system mode registers other than the SP (which is already
+ being used). */
+ POP {R0-R12, R14}
+
+ /* Return to the task code, loading CPSR on the way. */
+ RFEIA sp!
+
+ .endm
+
+
+
+
+/******************************************************************************
+ * SVC handler is used to yield.
+ *****************************************************************************/
+.align 4
+.type FreeRTOS_SVC_Handler, %function
+FreeRTOS_SVC_Handler:
+ /* Save the context of the current task and select a new task to run. */
+ portSAVE_CONTEXT
+ LDR R0, vTaskSwitchContextConst
+ BLX R0
+ portRESTORE_CONTEXT
+
+
+/******************************************************************************
+ * vPortRestoreTaskContext is used to start the scheduler.
+ *****************************************************************************/
+.align 4
+.type vPortRestoreTaskContext, %function
+vPortRestoreTaskContext:
+ /* Switch to system mode. */
+ CPS #SYS_MODE
+ portRESTORE_CONTEXT
+
+.align 4
+.type FreeRTOS_IRQ_Handler, %function
+FreeRTOS_IRQ_Handler:
+ /* Return to the interrupted instruction. */
+ SUB lr, lr, #4
+
+ /* Push the return address and SPSR. */
+ PUSH {lr}
+ MRS lr, SPSR
+ PUSH {lr}
+
+ /* Change to supervisor mode to allow reentry. */
+ CPS #0x13
+
+ /* Push used registers. */
+ PUSH {r0-r3, r12}
+
+ /* Increment nesting count. r3 holds the address of ulPortInterruptNesting
+ for future use. r1 holds the original ulPortInterruptNesting value for
+ future use. */
+ LDR r3, ulPortInterruptNestingConst
+ LDR r1, [r3]
+ ADD r0, r1, #1
+ STR r0, [r3]
+
+ /* Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for
+ future use. */
+ MOV r0, sp
+ AND r2, r0, #4
+ SUB sp, sp, r2
+
+ /* Call the interrupt handler. */
+ PUSH {r0-r3, lr}
+ LDR r1, vApplicationIRQHandlerConst
+ BLX r1
+ POP {r0-r3, lr}
+ ADD sp, sp, r2
+
+ CPSID i
+ DSB
+ ISB
+
+ /* Write to the EOI register. */
+ LDR r0, ulICCEOIRConst
+ LDR r2, [r0]
+ STR r0, [r2]
+
+ /* Restore the old nesting count. */
+ STR r1, [r3]
+
+ /* A context switch is never performed if the nesting count is not 0. */
+ CMP r1, #0
+ BNE exit_without_switch
+
+ /* Did the interrupt request a context switch? r1 holds the address of
+ ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
+ use. */
+ LDR r1, ulPortYieldRequiredConst
+ LDR r0, [r1]
+ CMP r0, #0
+ BNE switch_before_exit
+
+exit_without_switch:
+ /* No context switch. Restore used registers, LR_irq and SPSR before
+ returning. */
+ POP {r0-r3, r12}
+ CPS #IRQ_MODE
+ POP {LR}
+ MSR SPSR_cxsf, LR
+ POP {LR}
+ MOVS PC, LR
+
+switch_before_exit:
+ /* A context swtich is to be performed. Clear the context switch pending
+ flag. */
+ MOV r0, #0
+ STR r0, [r1]
+
+ /* Restore used registers, LR-irq and SPSR before saving the context
+ to the task stack. */
+ POP {r0-r3, r12}
+ CPS #IRQ_MODE
+ POP {LR}
+ MSR SPSR_cxsf, LR
+ POP {LR}
+ portSAVE_CONTEXT
+
+ /* Call the function that selects the new task to execute.
+ vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
+ instructions, or 8 byte aligned stack allocated data. LR does not need
+ saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */
+ LDR R0, vTaskSwitchContextConst
+ BLX R0
+
+ /* Restore the context of, and branch to, the task selected to execute
+ next. */
+ portRESTORE_CONTEXT
+
+ulICCEOIRConst: .word ulICCEOIR
+pxCurrentTCBConst: .word pxCurrentTCB
+ulCriticalNestingConst: .word ulCriticalNesting
+ulPortTaskHasFPUContextConst: .word ulPortTaskHasFPUContext
+vTaskSwitchContextConst: .word vTaskSwitchContext
+vApplicationIRQHandlerConst: .word vApplicationIRQHandler
+ulPortInterruptNestingConst: .word ulPortInterruptNesting
+ulPortYieldRequiredConst: .word ulPortYieldRequired
+
+.end
diff --git a/portable/GCC/ARM_CRx_No_GIC/portmacro.h b/portable/GCC/ARM_CRx_No_GIC/portmacro.h
index 7dc9243..be5c612 100644
--- a/portable/GCC/ARM_CRx_No_GIC/portmacro.h
+++ b/portable/GCC/ARM_CRx_No_GIC/portmacro.h
@@ -1,182 +1,181 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT short
-#define portSTACK_TYPE uint32_t
-#define portBASE_TYPE long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-typedef uint32_t TickType_t;
-#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-not need to be guarded with a critical section. */
-#define portTICK_TYPE_IS_ATOMIC 1
-
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portSTACK_GROWTH ( -1 )
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT 8
-
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-
-/* Called at the end of an ISR that can cause a context switch. */
-#define portEND_SWITCHING_ISR( xSwitchRequired )\
-{ \
-extern volatile uint32_t ulPortYieldRequired; \
- \
- if( xSwitchRequired != pdFALSE ) \
- { \
- ulPortYieldRequired = pdTRUE; \
- } \
-}
-
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-#define portYIELD() __asm volatile ( "SWI 0 \n" \
- "ISB " ::: "memory" );
-
-
-/*-----------------------------------------------------------
- * Critical section control
- *----------------------------------------------------------*/
-
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-extern uint32_t ulPortSetInterruptMask( void );
-extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
-extern void vPortInstallFreeRTOSVectorTable( void );
-
-/* The I bit within the CPSR. */
-#define portINTERRUPT_ENABLE_BIT ( 1 << 7 )
-
-/* In the absence of a priority mask register, these functions and macros
-globally enable and disable interrupts. */
-#define portENTER_CRITICAL() vPortEnterCritical();
-#define portEXIT_CRITICAL() vPortExitCritical();
-#define portENABLE_INTERRUPTS() __asm volatile ( "CPSIE i \n" ::: "memory" );
-#define portDISABLE_INTERRUPTS() __asm volatile ( "CPSID i \n" \
- "DSB \n" \
- "ISB " ::: "memory" );
-
-__attribute__( ( always_inline ) ) static __inline uint32_t portINLINE_SET_INTERRUPT_MASK_FROM_ISR( void )
-{
-volatile uint32_t ulCPSR;
-
- __asm volatile ( "MRS %0, CPSR" : "=r" (ulCPSR) :: "memory" );
- ulCPSR &= portINTERRUPT_ENABLE_BIT;
- portDISABLE_INTERRUPTS();
- return ulCPSR;
-}
-
-#define portSET_INTERRUPT_MASK_FROM_ISR() portINLINE_SET_INTERRUPT_MASK_FROM_ISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) do { if( x == 0 ) portENABLE_INTERRUPTS(); } while( 0 )
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. These are
-not required for this port but included in case common demo code that uses these
-macros is used. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-/* Tickless idle/low power functionality. */
-#ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
-#endif
-
-/* Prototype of the FreeRTOS tick handler. This must be installed as the
-handler for whichever peripheral is used to generate the RTOS tick. */
-void FreeRTOS_Tick_Handler( void );
-
-/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
-before any floating point instructions are executed. */
-void vPortTaskUsesFPU( void );
-#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
-
-#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
-#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
-
-/* Architecture specific optimisations. */
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-#endif
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
- /* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
- /*-----------------------------------------------------------*/
-
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __builtin_clz( uxReadyPriorities ) )
-
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-#define portNOP() __asm volatile( "NOP" )
-#define portINLINE __inline
-
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
-
-#ifdef __cplusplus
- } /* extern C */
-#endif
-
-
-#endif /* PORTMACRO_H */
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+typedef uint32_t TickType_t;
+#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+not need to be guarded with a critical section. */
+#define portTICK_TYPE_IS_ATOMIC 1
+
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+/* Called at the end of an ISR that can cause a context switch. */
+#define portEND_SWITCHING_ISR( xSwitchRequired )\
+{ \
+extern volatile uint32_t ulPortYieldRequired; \
+ \
+ if( xSwitchRequired != pdFALSE ) \
+ { \
+ ulPortYieldRequired = pdTRUE; \
+ } \
+}
+
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD() __asm volatile ( "SWI 0 \n" \
+ "ISB " ::: "memory" );
+
+
+/*-----------------------------------------------------------
+ * Critical section control
+ *----------------------------------------------------------*/
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+extern uint32_t ulPortSetInterruptMask( void );
+extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
+extern void vPortInstallFreeRTOSVectorTable( void );
+
+/* The I bit within the CPSR. */
+#define portINTERRUPT_ENABLE_BIT ( 1 << 7 )
+
+/* In the absence of a priority mask register, these functions and macros
+globally enable and disable interrupts. */
+#define portENTER_CRITICAL() vPortEnterCritical();
+#define portEXIT_CRITICAL() vPortExitCritical();
+#define portENABLE_INTERRUPTS() __asm volatile ( "CPSIE i \n" ::: "memory" );
+#define portDISABLE_INTERRUPTS() __asm volatile ( "CPSID i \n" \
+ "DSB \n" \
+ "ISB " ::: "memory" );
+
+__attribute__( ( always_inline ) ) static __inline uint32_t portINLINE_SET_INTERRUPT_MASK_FROM_ISR( void )
+{
+volatile uint32_t ulCPSR;
+
+ __asm volatile ( "MRS %0, CPSR" : "=r" (ulCPSR) :: "memory" );
+ ulCPSR &= portINTERRUPT_ENABLE_BIT;
+ portDISABLE_INTERRUPTS();
+ return ulCPSR;
+}
+
+#define portSET_INTERRUPT_MASK_FROM_ISR() portINLINE_SET_INTERRUPT_MASK_FROM_ISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) do { if( x == 0 ) portENABLE_INTERRUPTS(); } while( 0 )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. These are
+not required for this port but included in case common demo code that uses these
+macros is used. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+/* Tickless idle/low power functionality. */
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
+
+/* Prototype of the FreeRTOS tick handler. This must be installed as the
+handler for whichever peripheral is used to generate the RTOS tick. */
+void FreeRTOS_Tick_Handler( void );
+
+/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
+before any floating point instructions are executed. */
+void vPortTaskUsesFPU( void );
+#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+
+#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
+#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+ /* Store/clear the ready priorities in a bit map. */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+ /*-----------------------------------------------------------*/
+
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __builtin_clz( uxReadyPriorities ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+#define portNOP() __asm volatile( "NOP" )
+#define portINLINE __inline
+
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+
+#ifdef __cplusplus
+ } /* extern C */
+#endif
+
+
+#endif /* PORTMACRO_H */
diff --git a/portable/GCC/ATMega323/port.c b/portable/GCC/ATMega323/port.c
index ab0a9ea..c27910c 100644
--- a/portable/GCC/ATMega323/port.c
+++ b/portable/GCC/ATMega323/port.c
@@ -1,427 +1,427 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*
-
-Changes from V2.6.0
-
- + AVR port - Replaced the inb() and outb() functions with direct memory
- access. This allows the port to be built with the 20050414 build of
- WinAVR.
-*/
-
-#include <stdlib.h>
-#include <avr/interrupt.h>
-
-#include "FreeRTOS.h"
-#include "task.h"
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the AVR port.
- *----------------------------------------------------------*/
-
-/* Start tasks with interrupts enables. */
-#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x80 )
-
-/* Hardware constants for timer 1. */
-#define portCLEAR_COUNTER_ON_MATCH ( ( uint8_t ) 0x08 )
-#define portPRESCALE_64 ( ( uint8_t ) 0x03 )
-#define portCLOCK_PRESCALER ( ( uint32_t ) 64 )
-#define portCOMPARE_MATCH_A_INTERRUPT_ENABLE ( ( uint8_t ) 0x10 )
-
-/*-----------------------------------------------------------*/
-
-/* We require the address of the pxCurrentTCB variable, but don't want to know
-any details of its type. */
-typedef void TCB_t;
-extern volatile TCB_t * volatile pxCurrentTCB;
-
-/*-----------------------------------------------------------*/
-
-/*
- * Macro to save all the general purpose registers, the save the stack pointer
- * into the TCB.
- *
- * The first thing we do is save the flags then disable interrupts. This is to
- * guard our stack against having a context switch interrupt after we have already
- * pushed the registers onto the stack - causing the 32 registers to be on the
- * stack twice.
- *
- * r1 is set to zero as the compiler expects it to be thus, however some
- * of the math routines make use of R1.
- *
- * The interrupts will have been disabled during the call to portSAVE_CONTEXT()
- * so we need not worry about reading/writing to the stack pointer.
- */
-
-#define portSAVE_CONTEXT() \
- asm volatile ( "push r0 \n\t" \
- "in r0, __SREG__ \n\t" \
- "cli \n\t" \
- "push r0 \n\t" \
- "push r1 \n\t" \
- "clr r1 \n\t" \
- "push r2 \n\t" \
- "push r3 \n\t" \
- "push r4 \n\t" \
- "push r5 \n\t" \
- "push r6 \n\t" \
- "push r7 \n\t" \
- "push r8 \n\t" \
- "push r9 \n\t" \
- "push r10 \n\t" \
- "push r11 \n\t" \
- "push r12 \n\t" \
- "push r13 \n\t" \
- "push r14 \n\t" \
- "push r15 \n\t" \
- "push r16 \n\t" \
- "push r17 \n\t" \
- "push r18 \n\t" \
- "push r19 \n\t" \
- "push r20 \n\t" \
- "push r21 \n\t" \
- "push r22 \n\t" \
- "push r23 \n\t" \
- "push r24 \n\t" \
- "push r25 \n\t" \
- "push r26 \n\t" \
- "push r27 \n\t" \
- "push r28 \n\t" \
- "push r29 \n\t" \
- "push r30 \n\t" \
- "push r31 \n\t" \
- "lds r26, pxCurrentTCB \n\t" \
- "lds r27, pxCurrentTCB + 1 \n\t" \
- "in r0, 0x3d \n\t" \
- "st x+, r0 \n\t" \
- "in r0, 0x3e \n\t" \
- "st x+, r0 \n\t" \
- );
-
-/*
- * Opposite to portSAVE_CONTEXT(). Interrupts will have been disabled during
- * the context save so we can write to the stack pointer.
- */
-
-#define portRESTORE_CONTEXT() \
- asm volatile ( "lds r26, pxCurrentTCB \n\t" \
- "lds r27, pxCurrentTCB + 1 \n\t" \
- "ld r28, x+ \n\t" \
- "out __SP_L__, r28 \n\t" \
- "ld r29, x+ \n\t" \
- "out __SP_H__, r29 \n\t" \
- "pop r31 \n\t" \
- "pop r30 \n\t" \
- "pop r29 \n\t" \
- "pop r28 \n\t" \
- "pop r27 \n\t" \
- "pop r26 \n\t" \
- "pop r25 \n\t" \
- "pop r24 \n\t" \
- "pop r23 \n\t" \
- "pop r22 \n\t" \
- "pop r21 \n\t" \
- "pop r20 \n\t" \
- "pop r19 \n\t" \
- "pop r18 \n\t" \
- "pop r17 \n\t" \
- "pop r16 \n\t" \
- "pop r15 \n\t" \
- "pop r14 \n\t" \
- "pop r13 \n\t" \
- "pop r12 \n\t" \
- "pop r11 \n\t" \
- "pop r10 \n\t" \
- "pop r9 \n\t" \
- "pop r8 \n\t" \
- "pop r7 \n\t" \
- "pop r6 \n\t" \
- "pop r5 \n\t" \
- "pop r4 \n\t" \
- "pop r3 \n\t" \
- "pop r2 \n\t" \
- "pop r1 \n\t" \
- "pop r0 \n\t" \
- "out __SREG__, r0 \n\t" \
- "pop r0 \n\t" \
- );
-
-/*-----------------------------------------------------------*/
-
-/*
- * Perform hardware setup to enable ticks from timer 1, compare match A.
- */
-static void prvSetupTimerInterrupt( void );
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-uint16_t usAddress;
-
- /* Place a few bytes of known values on the bottom of the stack.
- This is just useful for debugging. */
-
- *pxTopOfStack = 0x11;
- pxTopOfStack--;
- *pxTopOfStack = 0x22;
- pxTopOfStack--;
- *pxTopOfStack = 0x33;
- pxTopOfStack--;
-
- /* Simulate how the stack would look after a call to vPortYield() generated by
- the compiler. */
-
- /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */
-
- /* The start of the task code will be popped off the stack last, so place
- it on first. */
- usAddress = ( uint16_t ) pxCode;
- *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
- pxTopOfStack--;
-
- usAddress >>= 8;
- *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
- pxTopOfStack--;
-
- /* Next simulate the stack as if after a call to portSAVE_CONTEXT().
- portSAVE_CONTEXT places the flags on the stack immediately after r0
- to ensure the interrupts get disabled as soon as possible, and so ensuring
- the stack use is minimal should a context switch interrupt occur. */
- *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */
- pxTopOfStack--;
- *pxTopOfStack = portFLAGS_INT_ENABLED;
- pxTopOfStack--;
-
-
- /* Now the remaining registers. The compiler expects R1 to be 0. */
- *pxTopOfStack = ( StackType_t ) 0x00; /* R1 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x02; /* R2 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03; /* R3 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04; /* R4 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x05; /* R5 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06; /* R6 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07; /* R7 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08; /* R8 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09; /* R9 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10; /* R10 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11; /* R11 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12; /* R12 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x13; /* R13 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x14; /* R14 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x15; /* R15 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x16; /* R16 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x17; /* R17 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x18; /* R18 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x19; /* R19 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x20; /* R20 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x21; /* R21 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x22; /* R22 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x23; /* R23 */
- pxTopOfStack--;
-
- /* Place the parameter on the stack in the expected location. */
- usAddress = ( uint16_t ) pvParameters;
- *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
- pxTopOfStack--;
-
- usAddress >>= 8;
- *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
- pxTopOfStack--;
-
- *pxTopOfStack = ( StackType_t ) 0x26; /* R26 X */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x27; /* R27 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x28; /* R28 Y */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x29; /* R29 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x30; /* R30 Z */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x031; /* R31 */
- pxTopOfStack--;
-
- /*lint +e950 +e611 +e923 */
-
- return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
- /* Setup the hardware to generate the tick. */
- prvSetupTimerInterrupt();
-
- /* Restore the context of the first task that is going to run. */
- portRESTORE_CONTEXT();
-
- /* Simulate a function call end as generated by the compiler. We will now
- jump to the start of the task the context of which we have just restored. */
- asm volatile ( "ret" );
-
- /* Should not get here. */
- return pdTRUE;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
- /* It is unlikely that the AVR port will get stopped. If required simply
- disable the tick interrupt here. */
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Manual context switch. The first thing we do is save the registers so we
- * can use a naked attribute.
- */
-void vPortYield( void ) __attribute__ ( ( naked ) );
-void vPortYield( void )
-{
- portSAVE_CONTEXT();
- vTaskSwitchContext();
- portRESTORE_CONTEXT();
-
- asm volatile ( "ret" );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Context switch function used by the tick. This must be identical to
- * vPortYield() from the call to vTaskSwitchContext() onwards. The only
- * difference from vPortYield() is the tick count is incremented as the
- * call comes from the tick ISR.
- */
-void vPortYieldFromTick( void ) __attribute__ ( ( naked ) );
-void vPortYieldFromTick( void )
-{
- portSAVE_CONTEXT();
- if( xTaskIncrementTick() != pdFALSE )
- {
- vTaskSwitchContext();
- }
- portRESTORE_CONTEXT();
-
- asm volatile ( "ret" );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Setup timer 1 compare match A to generate a tick interrupt.
- */
-static void prvSetupTimerInterrupt( void )
-{
-uint32_t ulCompareMatch;
-uint8_t ucHighByte, ucLowByte;
-
- /* Using 16bit timer 1 to generate the tick. Correct fuses must be
- selected for the configCPU_CLOCK_HZ clock. */
-
- ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
-
- /* We only have 16 bits so have to scale to get our required tick rate. */
- ulCompareMatch /= portCLOCK_PRESCALER;
-
- /* Adjust for correct value. */
- ulCompareMatch -= ( uint32_t ) 1;
-
- /* Setup compare match value for compare match A. Interrupts are disabled
- before this is called so we need not worry here. */
- ucLowByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
- ulCompareMatch >>= 8;
- ucHighByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
- OCR1AH = ucHighByte;
- OCR1AL = ucLowByte;
-
- /* Setup clock source and compare match behaviour. */
- ucLowByte = portCLEAR_COUNTER_ON_MATCH | portPRESCALE_64;
- TCCR1B = ucLowByte;
-
- /* Enable the interrupt - this is okay as interrupt are currently globally
- disabled. */
- ucLowByte = TIMSK;
- ucLowByte |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE;
- TIMSK = ucLowByte;
-}
-/*-----------------------------------------------------------*/
-
-#if configUSE_PREEMPTION == 1
-
- /*
- * Tick ISR for preemptive scheduler. We can use a naked attribute as
- * the context is saved at the start of vPortYieldFromTick(). The tick
- * count is incremented after the context is saved.
- */
- void TIMER1_COMPA_vect( void ) __attribute__ ( ( signal, naked ) );
- void TIMER1_COMPA_vect( void )
- {
- vPortYieldFromTick();
- asm volatile ( "reti" );
- }
-#else
-
- /*
- * Tick ISR for the cooperative scheduler. All this does is increment the
- * tick count. We don't need to switch context, this can only be done by
- * manual calls to taskYIELD();
- */
- void TIMER1_COMPA_vect( void ) __attribute__ ( ( signal ) );
- void TIMER1_COMPA_vect( void )
- {
- xTaskIncrementTick();
- }
-#endif
-
-
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*
+
+Changes from V2.6.0
+
+ + AVR port - Replaced the inb() and outb() functions with direct memory
+ access. This allows the port to be built with the 20050414 build of
+ WinAVR.
+*/
+
+#include <stdlib.h>
+#include <avr/interrupt.h>
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the AVR port.
+ *----------------------------------------------------------*/
+
+/* Start tasks with interrupts enables. */
+#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x80 )
+
+/* Hardware constants for timer 1. */
+#define portCLEAR_COUNTER_ON_MATCH ( ( uint8_t ) 0x08 )
+#define portPRESCALE_64 ( ( uint8_t ) 0x03 )
+#define portCLOCK_PRESCALER ( ( uint32_t ) 64 )
+#define portCOMPARE_MATCH_A_INTERRUPT_ENABLE ( ( uint8_t ) 0x10 )
+
+/*-----------------------------------------------------------*/
+
+/* We require the address of the pxCurrentTCB variable, but don't want to know
+any details of its type. */
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Macro to save all the general purpose registers, the save the stack pointer
+ * into the TCB.
+ *
+ * The first thing we do is save the flags then disable interrupts. This is to
+ * guard our stack against having a context switch interrupt after we have already
+ * pushed the registers onto the stack - causing the 32 registers to be on the
+ * stack twice.
+ *
+ * r1 is set to zero as the compiler expects it to be thus, however some
+ * of the math routines make use of R1.
+ *
+ * The interrupts will have been disabled during the call to portSAVE_CONTEXT()
+ * so we need not worry about reading/writing to the stack pointer.
+ */
+
+#define portSAVE_CONTEXT() \
+ asm volatile ( "push r0 \n\t" \
+ "in r0, __SREG__ \n\t" \
+ "cli \n\t" \
+ "push r0 \n\t" \
+ "push r1 \n\t" \
+ "clr r1 \n\t" \
+ "push r2 \n\t" \
+ "push r3 \n\t" \
+ "push r4 \n\t" \
+ "push r5 \n\t" \
+ "push r6 \n\t" \
+ "push r7 \n\t" \
+ "push r8 \n\t" \
+ "push r9 \n\t" \
+ "push r10 \n\t" \
+ "push r11 \n\t" \
+ "push r12 \n\t" \
+ "push r13 \n\t" \
+ "push r14 \n\t" \
+ "push r15 \n\t" \
+ "push r16 \n\t" \
+ "push r17 \n\t" \
+ "push r18 \n\t" \
+ "push r19 \n\t" \
+ "push r20 \n\t" \
+ "push r21 \n\t" \
+ "push r22 \n\t" \
+ "push r23 \n\t" \
+ "push r24 \n\t" \
+ "push r25 \n\t" \
+ "push r26 \n\t" \
+ "push r27 \n\t" \
+ "push r28 \n\t" \
+ "push r29 \n\t" \
+ "push r30 \n\t" \
+ "push r31 \n\t" \
+ "lds r26, pxCurrentTCB \n\t" \
+ "lds r27, pxCurrentTCB + 1 \n\t" \
+ "in r0, 0x3d \n\t" \
+ "st x+, r0 \n\t" \
+ "in r0, 0x3e \n\t" \
+ "st x+, r0 \n\t" \
+ );
+
+/*
+ * Opposite to portSAVE_CONTEXT(). Interrupts will have been disabled during
+ * the context save so we can write to the stack pointer.
+ */
+
+#define portRESTORE_CONTEXT() \
+ asm volatile ( "lds r26, pxCurrentTCB \n\t" \
+ "lds r27, pxCurrentTCB + 1 \n\t" \
+ "ld r28, x+ \n\t" \
+ "out __SP_L__, r28 \n\t" \
+ "ld r29, x+ \n\t" \
+ "out __SP_H__, r29 \n\t" \
+ "pop r31 \n\t" \
+ "pop r30 \n\t" \
+ "pop r29 \n\t" \
+ "pop r28 \n\t" \
+ "pop r27 \n\t" \
+ "pop r26 \n\t" \
+ "pop r25 \n\t" \
+ "pop r24 \n\t" \
+ "pop r23 \n\t" \
+ "pop r22 \n\t" \
+ "pop r21 \n\t" \
+ "pop r20 \n\t" \
+ "pop r19 \n\t" \
+ "pop r18 \n\t" \
+ "pop r17 \n\t" \
+ "pop r16 \n\t" \
+ "pop r15 \n\t" \
+ "pop r14 \n\t" \
+ "pop r13 \n\t" \
+ "pop r12 \n\t" \
+ "pop r11 \n\t" \
+ "pop r10 \n\t" \
+ "pop r9 \n\t" \
+ "pop r8 \n\t" \
+ "pop r7 \n\t" \
+ "pop r6 \n\t" \
+ "pop r5 \n\t" \
+ "pop r4 \n\t" \
+ "pop r3 \n\t" \
+ "pop r2 \n\t" \
+ "pop r1 \n\t" \
+ "pop r0 \n\t" \
+ "out __SREG__, r0 \n\t" \
+ "pop r0 \n\t" \
+ );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Perform hardware setup to enable ticks from timer 1, compare match A.
+ */
+static void prvSetupTimerInterrupt( void );
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+uint16_t usAddress;
+
+ /* Place a few bytes of known values on the bottom of the stack.
+ This is just useful for debugging. */
+
+ *pxTopOfStack = 0x11;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x22;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x33;
+ pxTopOfStack--;
+
+ /* Simulate how the stack would look after a call to vPortYield() generated by
+ the compiler. */
+
+ /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */
+
+ /* The start of the task code will be popped off the stack last, so place
+ it on first. */
+ usAddress = ( uint16_t ) pxCode;
+ *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+ pxTopOfStack--;
+
+ usAddress >>= 8;
+ *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+ pxTopOfStack--;
+
+ /* Next simulate the stack as if after a call to portSAVE_CONTEXT().
+ portSAVE_CONTEXT places the flags on the stack immediately after r0
+ to ensure the interrupts get disabled as soon as possible, and so ensuring
+ the stack use is minimal should a context switch interrupt occur. */
+ *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */
+ pxTopOfStack--;
+ *pxTopOfStack = portFLAGS_INT_ENABLED;
+ pxTopOfStack--;
+
+
+ /* Now the remaining registers. The compiler expects R1 to be 0. */
+ *pxTopOfStack = ( StackType_t ) 0x00; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04; /* R4 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05; /* R5 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06; /* R6 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07; /* R7 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08; /* R8 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09; /* R9 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x13; /* R13 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x14; /* R14 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x15; /* R15 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x16; /* R16 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x17; /* R17 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x18; /* R18 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x19; /* R19 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x20; /* R20 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x21; /* R21 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x22; /* R22 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x23; /* R23 */
+ pxTopOfStack--;
+
+ /* Place the parameter on the stack in the expected location. */
+ usAddress = ( uint16_t ) pvParameters;
+ *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+ pxTopOfStack--;
+
+ usAddress >>= 8;
+ *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+ pxTopOfStack--;
+
+ *pxTopOfStack = ( StackType_t ) 0x26; /* R26 X */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x27; /* R27 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x28; /* R28 Y */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x29; /* R29 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x30; /* R30 Z */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x031; /* R31 */
+ pxTopOfStack--;
+
+ /*lint +e950 +e611 +e923 */
+
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+ /* Setup the hardware to generate the tick. */
+ prvSetupTimerInterrupt();
+
+ /* Restore the context of the first task that is going to run. */
+ portRESTORE_CONTEXT();
+
+ /* Simulate a function call end as generated by the compiler. We will now
+ jump to the start of the task the context of which we have just restored. */
+ asm volatile ( "ret" );
+
+ /* Should not get here. */
+ return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+ /* It is unlikely that the AVR port will get stopped. If required simply
+ disable the tick interrupt here. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch. The first thing we do is save the registers so we
+ * can use a naked attribute.
+ */
+void vPortYield( void ) __attribute__ ( ( naked ) );
+void vPortYield( void )
+{
+ portSAVE_CONTEXT();
+ vTaskSwitchContext();
+ portRESTORE_CONTEXT();
+
+ asm volatile ( "ret" );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Context switch function used by the tick. This must be identical to
+ * vPortYield() from the call to vTaskSwitchContext() onwards. The only
+ * difference from vPortYield() is the tick count is incremented as the
+ * call comes from the tick ISR.
+ */
+void vPortYieldFromTick( void ) __attribute__ ( ( naked ) );
+void vPortYieldFromTick( void )
+{
+ portSAVE_CONTEXT();
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ vTaskSwitchContext();
+ }
+ portRESTORE_CONTEXT();
+
+ asm volatile ( "ret" );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup timer 1 compare match A to generate a tick interrupt.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+uint32_t ulCompareMatch;
+uint8_t ucHighByte, ucLowByte;
+
+ /* Using 16bit timer 1 to generate the tick. Correct fuses must be
+ selected for the configCPU_CLOCK_HZ clock. */
+
+ ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+
+ /* We only have 16 bits so have to scale to get our required tick rate. */
+ ulCompareMatch /= portCLOCK_PRESCALER;
+
+ /* Adjust for correct value. */
+ ulCompareMatch -= ( uint32_t ) 1;
+
+ /* Setup compare match value for compare match A. Interrupts are disabled
+ before this is called so we need not worry here. */
+ ucLowByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
+ ulCompareMatch >>= 8;
+ ucHighByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
+ OCR1AH = ucHighByte;
+ OCR1AL = ucLowByte;
+
+ /* Setup clock source and compare match behaviour. */
+ ucLowByte = portCLEAR_COUNTER_ON_MATCH | portPRESCALE_64;
+ TCCR1B = ucLowByte;
+
+ /* Enable the interrupt - this is okay as interrupt are currently globally
+ disabled. */
+ ucLowByte = TIMSK;
+ ucLowByte |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE;
+ TIMSK = ucLowByte;
+}
+/*-----------------------------------------------------------*/
+
+#if configUSE_PREEMPTION == 1
+
+ /*
+ * Tick ISR for preemptive scheduler. We can use a naked attribute as
+ * the context is saved at the start of vPortYieldFromTick(). The tick
+ * count is incremented after the context is saved.
+ */
+ void TIMER1_COMPA_vect( void ) __attribute__ ( ( signal, naked ) );
+ void TIMER1_COMPA_vect( void )
+ {
+ vPortYieldFromTick();
+ asm volatile ( "reti" );
+ }
+#else
+
+ /*
+ * Tick ISR for the cooperative scheduler. All this does is increment the
+ * tick count. We don't need to switch context, this can only be done by
+ * manual calls to taskYIELD();
+ */
+ void TIMER1_COMPA_vect( void ) __attribute__ ( ( signal ) );
+ void TIMER1_COMPA_vect( void )
+ {
+ xTaskIncrementTick();
+ }
+#endif
+
+
+
diff --git a/portable/GCC/ATMega323/portmacro.h b/portable/GCC/ATMega323/portmacro.h
index d5bf98d..7afdef9 100644
--- a/portable/GCC/ATMega323/portmacro.h
+++ b/portable/GCC/ATMega323/portmacro.h
@@ -1,110 +1,109 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*
-Changes from V1.2.3
-
- + portCPU_CLOSK_HZ definition changed to 8MHz base 10, previously it
- base 16.
-*/
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT int
-#define portSTACK_TYPE uint8_t
-#define portBASE_TYPE char
-
-#define portPOINTER_SIZE_TYPE uint16_t
-
-typedef portSTACK_TYPE StackType_t;
-typedef signed char BaseType_t;
-typedef unsigned char UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
-#else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Critical section management. */
-#define portENTER_CRITICAL() asm volatile ( "in __tmp_reg__, __SREG__" :: ); \
- asm volatile ( "cli" :: ); \
- asm volatile ( "push __tmp_reg__" :: )
-
-#define portEXIT_CRITICAL() asm volatile ( "pop __tmp_reg__" :: ); \
- asm volatile ( "out __SREG__, __tmp_reg__" :: )
-
-#define portDISABLE_INTERRUPTS() asm volatile ( "cli" :: );
-#define portENABLE_INTERRUPTS() asm volatile ( "sei" :: );
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH ( -1 )
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT 1
-#define portNOP() asm volatile ( "nop" );
-/*-----------------------------------------------------------*/
-
-/* Kernel utilities. */
-extern void vPortYield( void ) __attribute__ ( ( naked ) );
-#define portYIELD() vPortYield()
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*
+Changes from V1.2.3
+
+ + portCPU_CLOSK_HZ definition changed to 8MHz base 10, previously it
+ base 16.
+*/
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT int
+#define portSTACK_TYPE uint8_t
+#define portBASE_TYPE char
+
+#define portPOINTER_SIZE_TYPE uint16_t
+
+typedef portSTACK_TYPE StackType_t;
+typedef signed char BaseType_t;
+typedef unsigned char UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+#define portENTER_CRITICAL() asm volatile ( "in __tmp_reg__, __SREG__" :: ); \
+ asm volatile ( "cli" :: ); \
+ asm volatile ( "push __tmp_reg__" :: )
+
+#define portEXIT_CRITICAL() asm volatile ( "pop __tmp_reg__" :: ); \
+ asm volatile ( "out __SREG__, __tmp_reg__" :: )
+
+#define portDISABLE_INTERRUPTS() asm volatile ( "cli" :: );
+#define portENABLE_INTERRUPTS() asm volatile ( "sei" :: );
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 1
+#define portNOP() asm volatile ( "nop" );
+/*-----------------------------------------------------------*/
+
+/* Kernel utilities. */
+extern void vPortYield( void ) __attribute__ ( ( naked ) );
+#define portYIELD() vPortYield()
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/portable/GCC/AVR32_UC3/exception.S b/portable/GCC/AVR32_UC3/exception.S
index 69e0e02..9d46489 100644
--- a/portable/GCC/AVR32_UC3/exception.S
+++ b/portable/GCC/AVR32_UC3/exception.S
@@ -1,327 +1,327 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT AND BSD-3-Clause
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*This file is prepared for Doxygen automatic documentation generation.*/
-/*! \file *********************************************************************
- *
- * \brief Exception and interrupt vectors.
- *
- * This file maps all events supported by an AVR32UC.
- *
- * - Compiler: GNU GCC for AVR32
- * - Supported devices: All AVR32UC devices with an INTC module can be used.
- * - AppNote:
- *
- * \author Atmel Corporation (Now Microchip):
- * https://www.microchip.com \n
- * Support and FAQ: https://www.microchip.com/support/
- *
- ******************************************************************************/
-
-/*
- * Copyright (c) 2007, Atmel Corporation All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of ATMEL may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
- * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-#include <avr32/io.h>
-#include "intc.h"
-
-
-//! @{
-//! \verbatim
-
-
- .section .exception, "ax", @progbits
-
-
-// Start of Exception Vector Table.
-
- // EVBA must be aligned with a power of two strictly greater than the EVBA-
- // relative offset of the last vector.
- .balign 0x200
-
- // Export symbol.
- .global _evba
- .type _evba, @function
-_evba:
-
- .org 0x000
- // Unrecoverable Exception.
-_handle_Unrecoverable_Exception:
- rjmp $
-
- .org 0x004
- // TLB Multiple Hit: UNUSED IN AVR32UC.
-_handle_TLB_Multiple_Hit:
- rjmp $
-
- .org 0x008
- // Bus Error Data Fetch.
-_handle_Bus_Error_Data_Fetch:
- rjmp $
-
- .org 0x00C
- // Bus Error Instruction Fetch.
-_handle_Bus_Error_Instruction_Fetch:
- rjmp $
-
- .org 0x010
- // NMI.
-_handle_NMI:
- rjmp $
-
- .org 0x014
- // Instruction Address.
-_handle_Instruction_Address:
- rjmp $
-
- .org 0x018
- // ITLB Protection.
-_handle_ITLB_Protection:
- rjmp $
-
- .org 0x01C
- // Breakpoint.
-_handle_Breakpoint:
- rjmp $
-
- .org 0x020
- // Illegal Opcode.
-_handle_Illegal_Opcode:
- rjmp $
-
- .org 0x024
- // Unimplemented Instruction.
-_handle_Unimplemented_Instruction:
- rjmp $
-
- .org 0x028
- // Privilege Violation.
-_handle_Privilege_Violation:
- rjmp $
-
- .org 0x02C
- // Floating-Point: UNUSED IN AVR32UC.
-_handle_Floating_Point:
- rjmp $
-
- .org 0x030
- // Coprocessor Absent: UNUSED IN AVR32UC.
-_handle_Coprocessor_Absent:
- rjmp $
-
- .org 0x034
- // Data Address (Read).
-_handle_Data_Address_Read:
- rjmp $
-
- .org 0x038
- // Data Address (Write).
-_handle_Data_Address_Write:
- rjmp $
-
- .org 0x03C
- // DTLB Protection (Read).
-_handle_DTLB_Protection_Read:
- rjmp $
-
- .org 0x040
- // DTLB Protection (Write).
-_handle_DTLB_Protection_Write:
- rjmp $
-
- .org 0x044
- // DTLB Modified: UNUSED IN AVR32UC.
-_handle_DTLB_Modified:
- rjmp $
-
- .org 0x050
- // ITLB Miss: UNUSED IN AVR32UC.
-_handle_ITLB_Miss:
- rjmp $
-
- .org 0x060
- // DTLB Miss (Read): UNUSED IN AVR32UC.
-_handle_DTLB_Miss_Read:
- rjmp $
-
- .org 0x070
- // DTLB Miss (Write): UNUSED IN AVR32UC.
-_handle_DTLB_Miss_Write:
- rjmp $
-
- .org 0x100
- // Supervisor Call.
-_handle_Supervisor_Call:
- lda.w pc, SCALLYield
-
-
-// Interrupt support.
-// The interrupt controller must provide the offset address relative to EVBA.
-// Important note:
-// All interrupts call a C function named _get_interrupt_handler.
-// This function will read group and interrupt line number to then return in
-// R12 a pointer to a user-provided interrupt handler.
-
- .balign 4
-
-_int0:
- // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
- // CPU upon interrupt entry.
-#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
- mfsr r12, AVR32_SR
- bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
- cp.w r12, 0b110
- brlo _int0_normal
- lddsp r12, sp[0 * 4]
- stdsp sp[6 * 4], r12
- lddsp r12, sp[1 * 4]
- stdsp sp[7 * 4], r12
- lddsp r12, sp[3 * 4]
- sub sp, -6 * 4
- rete
-_int0_normal:
-#endif
- mov r12, 0 // Pass the int_lev parameter to the _get_interrupt_handler function.
- call _get_interrupt_handler
- cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
- movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
- rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
-
-_int1:
- // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
- // CPU upon interrupt entry.
-#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
- mfsr r12, AVR32_SR
- bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
- cp.w r12, 0b110
- brlo _int1_normal
- lddsp r12, sp[0 * 4]
- stdsp sp[6 * 4], r12
- lddsp r12, sp[1 * 4]
- stdsp sp[7 * 4], r12
- lddsp r12, sp[3 * 4]
- sub sp, -6 * 4
- rete
-_int1_normal:
-#endif
- mov r12, 1 // Pass the int_lev parameter to the _get_interrupt_handler function.
- call _get_interrupt_handler
- cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
- movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
- rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
-
-_int2:
- // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
- // CPU upon interrupt entry.
-#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
- mfsr r12, AVR32_SR
- bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
- cp.w r12, 0b110
- brlo _int2_normal
- lddsp r12, sp[0 * 4]
- stdsp sp[6 * 4], r12
- lddsp r12, sp[1 * 4]
- stdsp sp[7 * 4], r12
- lddsp r12, sp[3 * 4]
- sub sp, -6 * 4
- rete
-_int2_normal:
-#endif
- mov r12, 2 // Pass the int_lev parameter to the _get_interrupt_handler function.
- call _get_interrupt_handler
- cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
- movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
- rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
-
-_int3:
- // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
- // CPU upon interrupt entry.
-#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
- mfsr r12, AVR32_SR
- bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
- cp.w r12, 0b110
- brlo _int3_normal
- lddsp r12, sp[0 * 4]
- stdsp sp[6 * 4], r12
- lddsp r12, sp[1 * 4]
- stdsp sp[7 * 4], r12
- lddsp r12, sp[3 * 4]
- sub sp, -6 * 4
- rete
-_int3_normal:
-#endif
- mov r12, 3 // Pass the int_lev parameter to the _get_interrupt_handler function.
- call _get_interrupt_handler
- cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
- movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
- rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
-
-
-// Constant data area.
-
- .balign 4
-
- // Values to store in the interrupt priority registers for the various interrupt priority levels.
- // The interrupt priority registers contain the interrupt priority level and
- // the EVBA-relative interrupt vector offset.
- .global ipr_val
- .type ipr_val, @object
-ipr_val:
- .word (INT0 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int0 - _evba),\
- (INT1 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int1 - _evba),\
- (INT2 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int2 - _evba),\
- (INT3 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int3 - _evba)
-
-
-//! \endverbatim
-//! @}
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT AND BSD-3-Clause
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief Exception and interrupt vectors.
+ *
+ * This file maps all events supported by an AVR32UC.
+ *
+ * - Compiler: GNU GCC for AVR32
+ * - Supported devices: All AVR32UC devices with an INTC module can be used.
+ * - AppNote:
+ *
+ * \author Atmel Corporation (Now Microchip):
+ * https://www.microchip.com \n
+ * Support and FAQ: https://www.microchip.com/support/
+ *
+ ******************************************************************************/
+
+/*
+ * Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#include <avr32/io.h>
+#include "intc.h"
+
+
+//! @{
+//! \verbatim
+
+
+ .section .exception, "ax", @progbits
+
+
+// Start of Exception Vector Table.
+
+ // EVBA must be aligned with a power of two strictly greater than the EVBA-
+ // relative offset of the last vector.
+ .balign 0x200
+
+ // Export symbol.
+ .global _evba
+ .type _evba, @function
+_evba:
+
+ .org 0x000
+ // Unrecoverable Exception.
+_handle_Unrecoverable_Exception:
+ rjmp $
+
+ .org 0x004
+ // TLB Multiple Hit: UNUSED IN AVR32UC.
+_handle_TLB_Multiple_Hit:
+ rjmp $
+
+ .org 0x008
+ // Bus Error Data Fetch.
+_handle_Bus_Error_Data_Fetch:
+ rjmp $
+
+ .org 0x00C
+ // Bus Error Instruction Fetch.
+_handle_Bus_Error_Instruction_Fetch:
+ rjmp $
+
+ .org 0x010
+ // NMI.
+_handle_NMI:
+ rjmp $
+
+ .org 0x014
+ // Instruction Address.
+_handle_Instruction_Address:
+ rjmp $
+
+ .org 0x018
+ // ITLB Protection.
+_handle_ITLB_Protection:
+ rjmp $
+
+ .org 0x01C
+ // Breakpoint.
+_handle_Breakpoint:
+ rjmp $
+
+ .org 0x020
+ // Illegal Opcode.
+_handle_Illegal_Opcode:
+ rjmp $
+
+ .org 0x024
+ // Unimplemented Instruction.
+_handle_Unimplemented_Instruction:
+ rjmp $
+
+ .org 0x028
+ // Privilege Violation.
+_handle_Privilege_Violation:
+ rjmp $
+
+ .org 0x02C
+ // Floating-Point: UNUSED IN AVR32UC.
+_handle_Floating_Point:
+ rjmp $
+
+ .org 0x030
+ // Coprocessor Absent: UNUSED IN AVR32UC.
+_handle_Coprocessor_Absent:
+ rjmp $
+
+ .org 0x034
+ // Data Address (Read).
+_handle_Data_Address_Read:
+ rjmp $
+
+ .org 0x038
+ // Data Address (Write).
+_handle_Data_Address_Write:
+ rjmp $
+
+ .org 0x03C
+ // DTLB Protection (Read).
+_handle_DTLB_Protection_Read:
+ rjmp $
+
+ .org 0x040
+ // DTLB Protection (Write).
+_handle_DTLB_Protection_Write:
+ rjmp $
+
+ .org 0x044
+ // DTLB Modified: UNUSED IN AVR32UC.
+_handle_DTLB_Modified:
+ rjmp $
+
+ .org 0x050
+ // ITLB Miss: UNUSED IN AVR32UC.
+_handle_ITLB_Miss:
+ rjmp $
+
+ .org 0x060
+ // DTLB Miss (Read): UNUSED IN AVR32UC.
+_handle_DTLB_Miss_Read:
+ rjmp $
+
+ .org 0x070
+ // DTLB Miss (Write): UNUSED IN AVR32UC.
+_handle_DTLB_Miss_Write:
+ rjmp $
+
+ .org 0x100
+ // Supervisor Call.
+_handle_Supervisor_Call:
+ lda.w pc, SCALLYield
+
+
+// Interrupt support.
+// The interrupt controller must provide the offset address relative to EVBA.
+// Important note:
+// All interrupts call a C function named _get_interrupt_handler.
+// This function will read group and interrupt line number to then return in
+// R12 a pointer to a user-provided interrupt handler.
+
+ .balign 4
+
+_int0:
+ // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
+ // CPU upon interrupt entry.
+#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
+ mfsr r12, AVR32_SR
+ bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
+ cp.w r12, 0b110
+ brlo _int0_normal
+ lddsp r12, sp[0 * 4]
+ stdsp sp[6 * 4], r12
+ lddsp r12, sp[1 * 4]
+ stdsp sp[7 * 4], r12
+ lddsp r12, sp[3 * 4]
+ sub sp, -6 * 4
+ rete
+_int0_normal:
+#endif
+ mov r12, 0 // Pass the int_lev parameter to the _get_interrupt_handler function.
+ call _get_interrupt_handler
+ cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
+ movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
+ rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
+
+_int1:
+ // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
+ // CPU upon interrupt entry.
+#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
+ mfsr r12, AVR32_SR
+ bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
+ cp.w r12, 0b110
+ brlo _int1_normal
+ lddsp r12, sp[0 * 4]
+ stdsp sp[6 * 4], r12
+ lddsp r12, sp[1 * 4]
+ stdsp sp[7 * 4], r12
+ lddsp r12, sp[3 * 4]
+ sub sp, -6 * 4
+ rete
+_int1_normal:
+#endif
+ mov r12, 1 // Pass the int_lev parameter to the _get_interrupt_handler function.
+ call _get_interrupt_handler
+ cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
+ movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
+ rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
+
+_int2:
+ // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
+ // CPU upon interrupt entry.
+#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
+ mfsr r12, AVR32_SR
+ bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
+ cp.w r12, 0b110
+ brlo _int2_normal
+ lddsp r12, sp[0 * 4]
+ stdsp sp[6 * 4], r12
+ lddsp r12, sp[1 * 4]
+ stdsp sp[7 * 4], r12
+ lddsp r12, sp[3 * 4]
+ sub sp, -6 * 4
+ rete
+_int2_normal:
+#endif
+ mov r12, 2 // Pass the int_lev parameter to the _get_interrupt_handler function.
+ call _get_interrupt_handler
+ cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
+ movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
+ rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
+
+_int3:
+ // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
+ // CPU upon interrupt entry.
+#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
+ mfsr r12, AVR32_SR
+ bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
+ cp.w r12, 0b110
+ brlo _int3_normal
+ lddsp r12, sp[0 * 4]
+ stdsp sp[6 * 4], r12
+ lddsp r12, sp[1 * 4]
+ stdsp sp[7 * 4], r12
+ lddsp r12, sp[3 * 4]
+ sub sp, -6 * 4
+ rete
+_int3_normal:
+#endif
+ mov r12, 3 // Pass the int_lev parameter to the _get_interrupt_handler function.
+ call _get_interrupt_handler
+ cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
+ movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
+ rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
+
+
+// Constant data area.
+
+ .balign 4
+
+ // Values to store in the interrupt priority registers for the various interrupt priority levels.
+ // The interrupt priority registers contain the interrupt priority level and
+ // the EVBA-relative interrupt vector offset.
+ .global ipr_val
+ .type ipr_val, @object
+ipr_val:
+ .word (INT0 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int0 - _evba),\
+ (INT1 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int1 - _evba),\
+ (INT2 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int2 - _evba),\
+ (INT3 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int3 - _evba)
+
+
+//! \endverbatim
+//! @}
diff --git a/portable/GCC/AVR32_UC3/port.c b/portable/GCC/AVR32_UC3/port.c
index 37ada91..8d78fe0 100644
--- a/portable/GCC/AVR32_UC3/port.c
+++ b/portable/GCC/AVR32_UC3/port.c
@@ -1,464 +1,464 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT AND BSD-3-Clause
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*This file has been prepared for Doxygen automatic documentation generation.*/
-/*! \file *********************************************************************
- *
- * \brief FreeRTOS port source for AVR32 UC3.
- *
- * - Compiler: GNU GCC for AVR32
- * - Supported devices: All AVR32 devices can be used.
- * - AppNote:
- *
- * \author Atmel Corporation (Now Microchip):
- * https://www.microchip.com \n
- * Support and FAQ: https://www.microchip.com/support/
- *
- *****************************************************************************/
-
-/*
- * Copyright (c) 2007, Atmel Corporation All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of ATMEL may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
- * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/* Standard includes. */
-#include <sys/cpu.h>
-#include <sys/usart.h>
-#include <malloc.h>
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* AVR32 UC3 includes. */
-#include <avr32/io.h>
-#include "gpio.h"
-#if( configTICK_USE_TC==1 )
- #include "tc.h"
-#endif
-
-
-/* Constants required to setup the task context. */
-#define portINITIAL_SR ( ( StackType_t ) 0x00400000 ) /* AVR32 : [M2:M0]=001 I1M=0 I0M=0, GM=0 */
-#define portINSTRUCTION_SIZE ( ( StackType_t ) 0 )
-
-/* Each task maintains its own critical nesting variable. */
-#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
-volatile uint32_t ulCriticalNesting = 9999UL;
-
-#if( configTICK_USE_TC==0 )
- static void prvScheduleNextTick( void );
-#else
- static void prvClearTcInt( void );
-#endif
-
-/* Setup the timer to generate the tick interrupts. */
-static void prvSetupTimerInterrupt( void );
-
-/*-----------------------------------------------------------*/
-
-/*
- * Low-level initialization routine called during startup, before the main
- * function.
- * This version comes in replacement to the default one provided by Newlib.
- * Newlib's _init_startup only calls init_exceptions, but Newlib's exception
- * vectors are not compatible with the SCALL management in the current FreeRTOS
- * port. More low-level initializations are besides added here.
- */
-void _init_startup(void)
-{
- /* Import the Exception Vector Base Address. */
- extern void _evba;
-
- #if configHEAP_INIT
- extern void __heap_start__;
- extern void __heap_end__;
- BaseType_t *pxMem;
- #endif
-
- /* Load the Exception Vector Base Address in the corresponding system register. */
- Set_system_register( AVR32_EVBA, ( int ) &_evba );
-
- /* Enable exceptions. */
- ENABLE_ALL_EXCEPTIONS();
-
- /* Initialize interrupt handling. */
- INTC_init_interrupts();
-
- #if configHEAP_INIT
-
- /* Initialize the heap used by malloc. */
- for( pxMem = &__heap_start__; pxMem < ( BaseType_t * )&__heap_end__; )
- {
- *pxMem++ = 0xA5A5A5A5;
- }
-
- #endif
-
- /* Give the used CPU clock frequency to Newlib, so it can work properly. */
- set_cpu_hz( configCPU_CLOCK_HZ );
-
- /* Code section present if and only if the debug trace is activated. */
- #if configDBG
- {
- static const gpio_map_t DBG_USART_GPIO_MAP =
- {
- { configDBG_USART_RX_PIN, configDBG_USART_RX_FUNCTION },
- { configDBG_USART_TX_PIN, configDBG_USART_TX_FUNCTION }
- };
-
- /* Initialize the USART used for the debug trace with the configured parameters. */
- set_usart_base( ( void * ) configDBG_USART );
- gpio_enable_module( DBG_USART_GPIO_MAP,
- sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[0] ) );
- usart_init( configDBG_USART_BAUDRATE );
- }
- #endif
-}
-/*-----------------------------------------------------------*/
-
-/*
- * malloc, realloc and free are meant to be called through respectively
- * pvPortMalloc, pvPortRealloc and vPortFree.
- * The latter functions call the former ones from within sections where tasks
- * are suspended, so the latter functions are task-safe. __malloc_lock and
- * __malloc_unlock use the same mechanism to also keep the former functions
- * task-safe as they may be called directly from Newlib's functions.
- * However, all these functions are interrupt-unsafe and SHALL THEREFORE NOT BE
- * CALLED FROM WITHIN AN INTERRUPT, because __malloc_lock and __malloc_unlock do
- * not call portENTER_CRITICAL and portEXIT_CRITICAL in order not to disable
- * interrupts during memory allocation management as this may be a very time-
- * consuming process.
- */
-
-/*
- * Lock routine called by Newlib on malloc / realloc / free entry to guarantee a
- * safe section as memory allocation management uses global data.
- * See the aforementioned details.
- */
-void __malloc_lock(struct _reent *ptr)
-{
- vTaskSuspendAll();
-}
-
-/*
- * Unlock routine called by Newlib on malloc / realloc / free exit to guarantee
- * a safe section as memory allocation management uses global data.
- * See the aforementioned details.
- */
-void __malloc_unlock(struct _reent *ptr)
-{
- xTaskResumeAll();
-}
-/*-----------------------------------------------------------*/
-
-/* Added as there is no such function in FreeRTOS. */
-void *pvPortRealloc( void *pv, size_t xWantedSize )
-{
-void *pvReturn;
-
- vTaskSuspendAll();
- {
- pvReturn = realloc( pv, xWantedSize );
- }
- xTaskResumeAll();
-
- return pvReturn;
-}
-/*-----------------------------------------------------------*/
-
-/* The cooperative scheduler requires a normal IRQ service routine to
-simply increment the system tick. */
-/* The preemptive scheduler is defined as "naked" as the full context is saved
-on entry as part of the context switch. */
-__attribute__((__naked__)) static void vTick( void )
-{
- /* Save the context of the interrupted task. */
- portSAVE_CONTEXT_OS_INT();
-
- #if( configTICK_USE_TC==1 )
- /* Clear the interrupt flag. */
- prvClearTcInt();
- #else
- /* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
- clock cycles from now. */
- prvScheduleNextTick();
- #endif
-
- /* Because FreeRTOS is not supposed to run with nested interrupts, put all OS
- calls in a critical section . */
- portENTER_CRITICAL();
- xTaskIncrementTick();
- portEXIT_CRITICAL();
-
- /* Restore the context of the "elected task". */
- portRESTORE_CONTEXT_OS_INT();
-}
-/*-----------------------------------------------------------*/
-
-__attribute__((__naked__)) void SCALLYield( void )
-{
- /* Save the context of the interrupted task. */
- portSAVE_CONTEXT_SCALL();
- vTaskSwitchContext();
- portRESTORE_CONTEXT_SCALL();
-}
-/*-----------------------------------------------------------*/
-
-/* The code generated by the GCC compiler uses the stack in different ways at
-different optimisation levels. The interrupt flags can therefore not always
-be saved to the stack. Instead the critical section nesting level is stored
-in a variable, which is then saved as part of the stack context. */
-__attribute__((__noinline__)) void vPortEnterCritical( void )
-{
- /* Disable interrupts */
- portDISABLE_INTERRUPTS();
-
- /* Now interrupts are disabled ulCriticalNesting can be accessed
- directly. Increment ulCriticalNesting to keep a count of how many times
- portENTER_CRITICAL() has been called. */
- ulCriticalNesting++;
-}
-/*-----------------------------------------------------------*/
-
-__attribute__((__noinline__)) void vPortExitCritical( void )
-{
- if(ulCriticalNesting > portNO_CRITICAL_NESTING)
- {
- ulCriticalNesting--;
- if( ulCriticalNesting == portNO_CRITICAL_NESTING )
- {
- /* Enable all interrupt/exception. */
- portENABLE_INTERRUPTS();
- }
- }
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Initialise the stack of a task to look exactly as if a call to
- * portSAVE_CONTEXT had been called.
- *
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
- /* Setup the initial stack of the task. The stack is set exactly as
- expected by the portRESTORE_CONTEXT() macro. */
-
- /* When the task starts, it will expect to find the function parameter in R12. */
- pxTopOfStack--;
- *pxTopOfStack-- = ( StackType_t ) 0x08080808; /* R8 */
- *pxTopOfStack-- = ( StackType_t ) 0x09090909; /* R9 */
- *pxTopOfStack-- = ( StackType_t ) 0x0A0A0A0A; /* R10 */
- *pxTopOfStack-- = ( StackType_t ) 0x0B0B0B0B; /* R11 */
- *pxTopOfStack-- = ( StackType_t ) pvParameters; /* R12 */
- *pxTopOfStack-- = ( StackType_t ) 0xDEADBEEF; /* R14/LR */
- *pxTopOfStack-- = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; /* R15/PC */
- *pxTopOfStack-- = ( StackType_t ) portINITIAL_SR; /* SR */
- *pxTopOfStack-- = ( StackType_t ) 0xFF0000FF; /* R0 */
- *pxTopOfStack-- = ( StackType_t ) 0x01010101; /* R1 */
- *pxTopOfStack-- = ( StackType_t ) 0x02020202; /* R2 */
- *pxTopOfStack-- = ( StackType_t ) 0x03030303; /* R3 */
- *pxTopOfStack-- = ( StackType_t ) 0x04040404; /* R4 */
- *pxTopOfStack-- = ( StackType_t ) 0x05050505; /* R5 */
- *pxTopOfStack-- = ( StackType_t ) 0x06060606; /* R6 */
- *pxTopOfStack-- = ( StackType_t ) 0x07070707; /* R7 */
- *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_NESTING; /* ulCriticalNesting */
-
- return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
- /* Start the timer that generates the tick ISR. Interrupts are disabled
- here already. */
- prvSetupTimerInterrupt();
-
- /* Start the first task. */
- portRESTORE_CONTEXT();
-
- /* Should not get here! */
- return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
- /* It is unlikely that the AVR32 port will require this function as there
- is nothing to return to. */
-}
-/*-----------------------------------------------------------*/
-
-/* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
-clock cycles from now. */
-#if( configTICK_USE_TC==0 )
- static void prvScheduleFirstTick(void)
- {
- uint32_t lCycles;
-
- lCycles = Get_system_register(AVR32_COUNT);
- lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
- // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception
- // generation feature does not get disabled.
- if(0 == lCycles)
- {
- lCycles++;
- }
- Set_system_register(AVR32_COMPARE, lCycles);
- }
-
- __attribute__((__noinline__)) static void prvScheduleNextTick(void)
- {
- uint32_t lCycles, lCount;
-
- lCycles = Get_system_register(AVR32_COMPARE);
- lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
- // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception
- // generation feature does not get disabled.
- if(0 == lCycles)
- {
- lCycles++;
- }
- lCount = Get_system_register(AVR32_COUNT);
- if( lCycles < lCount )
- { // We missed a tick, recover for the next.
- lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
- }
- Set_system_register(AVR32_COMPARE, lCycles);
- }
-#else
- __attribute__((__noinline__)) static void prvClearTcInt(void)
- {
- AVR32_TC.channel[configTICK_TC_CHANNEL].sr;
- }
-#endif
-/*-----------------------------------------------------------*/
-
-/* Setup the timer to generate the tick interrupts. */
-static void prvSetupTimerInterrupt(void)
-{
-#if( configTICK_USE_TC==1 )
-
- volatile avr32_tc_t *tc = &AVR32_TC;
-
- // Options for waveform genration.
- tc_waveform_opt_t waveform_opt =
- {
- .channel = configTICK_TC_CHANNEL, /* Channel selection. */
-
- .bswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOB. */
- .beevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOB. */
- .bcpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOB. */
- .bcpb = TC_EVT_EFFECT_NOOP, /* RB compare effect on TIOB. */
-
- .aswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOA. */
- .aeevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOA. */
- .acpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOA: toggle. */
- .acpa = TC_EVT_EFFECT_NOOP, /* RA compare effect on TIOA: toggle (other possibilities are none, set and clear). */
-
- .wavsel = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER,/* Waveform selection: Up mode without automatic trigger on RC compare. */
- .enetrg = FALSE, /* External event trigger enable. */
- .eevt = 0, /* External event selection. */
- .eevtedg = TC_SEL_NO_EDGE, /* External event edge selection. */
- .cpcdis = FALSE, /* Counter disable when RC compare. */
- .cpcstop = FALSE, /* Counter clock stopped with RC compare. */
-
- .burst = FALSE, /* Burst signal selection. */
- .clki = FALSE, /* Clock inversion. */
- .tcclks = TC_CLOCK_SOURCE_TC2 /* Internal source clock 2. */
- };
-
- tc_interrupt_t tc_interrupt =
- {
- .etrgs=0,
- .ldrbs=0,
- .ldras=0,
- .cpcs =1,
- .cpbs =0,
- .cpas =0,
- .lovrs=0,
- .covfs=0,
- };
-
-#endif
-
- /* Disable all interrupt/exception. */
- portDISABLE_INTERRUPTS();
-
- /* Register the compare interrupt handler to the interrupt controller and
- enable the compare interrupt. */
-
- #if( configTICK_USE_TC==1 )
- {
- INTC_register_interrupt(&vTick, configTICK_TC_IRQ, INT0);
-
- /* Initialize the timer/counter. */
- tc_init_waveform(tc, &waveform_opt);
-
- /* Set the compare triggers.
- Remember TC counter is 16-bits, so counting second is not possible!
- That's why we configure it to count ms. */
- tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4) / configTICK_RATE_HZ );
-
- tc_configure_interrupts( tc, configTICK_TC_CHANNEL, &tc_interrupt );
-
- /* Start the timer/counter. */
- tc_start(tc, configTICK_TC_CHANNEL);
- }
- #else
- {
- INTC_register_interrupt(&vTick, AVR32_CORE_COMPARE_IRQ, INT0);
- prvScheduleFirstTick();
- }
- #endif
-}
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT AND BSD-3-Clause
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief FreeRTOS port source for AVR32 UC3.
+ *
+ * - Compiler: GNU GCC for AVR32
+ * - Supported devices: All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author Atmel Corporation (Now Microchip):
+ * https://www.microchip.com \n
+ * Support and FAQ: https://www.microchip.com/support/
+ *
+ *****************************************************************************/
+
+/*
+ * Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Standard includes. */
+#include <sys/cpu.h>
+#include <sys/usart.h>
+#include <malloc.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* AVR32 UC3 includes. */
+#include <avr32/io.h>
+#include "gpio.h"
+#if( configTICK_USE_TC==1 )
+ #include "tc.h"
+#endif
+
+
+/* Constants required to setup the task context. */
+#define portINITIAL_SR ( ( StackType_t ) 0x00400000 ) /* AVR32 : [M2:M0]=001 I1M=0 I0M=0, GM=0 */
+#define portINSTRUCTION_SIZE ( ( StackType_t ) 0 )
+
+/* Each task maintains its own critical nesting variable. */
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
+volatile uint32_t ulCriticalNesting = 9999UL;
+
+#if( configTICK_USE_TC==0 )
+ static void prvScheduleNextTick( void );
+#else
+ static void prvClearTcInt( void );
+#endif
+
+/* Setup the timer to generate the tick interrupts. */
+static void prvSetupTimerInterrupt( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Low-level initialization routine called during startup, before the main
+ * function.
+ * This version comes in replacement to the default one provided by Newlib.
+ * Newlib's _init_startup only calls init_exceptions, but Newlib's exception
+ * vectors are not compatible with the SCALL management in the current FreeRTOS
+ * port. More low-level initializations are besides added here.
+ */
+void _init_startup(void)
+{
+ /* Import the Exception Vector Base Address. */
+ extern void _evba;
+
+ #if configHEAP_INIT
+ extern void __heap_start__;
+ extern void __heap_end__;
+ BaseType_t *pxMem;
+ #endif
+
+ /* Load the Exception Vector Base Address in the corresponding system register. */
+ Set_system_register( AVR32_EVBA, ( int ) &_evba );
+
+ /* Enable exceptions. */
+ ENABLE_ALL_EXCEPTIONS();
+
+ /* Initialize interrupt handling. */
+ INTC_init_interrupts();
+
+ #if configHEAP_INIT
+
+ /* Initialize the heap used by malloc. */
+ for( pxMem = &__heap_start__; pxMem < ( BaseType_t * )&__heap_end__; )
+ {
+ *pxMem++ = 0xA5A5A5A5;
+ }
+
+ #endif
+
+ /* Give the used CPU clock frequency to Newlib, so it can work properly. */
+ set_cpu_hz( configCPU_CLOCK_HZ );
+
+ /* Code section present if and only if the debug trace is activated. */
+ #if configDBG
+ {
+ static const gpio_map_t DBG_USART_GPIO_MAP =
+ {
+ { configDBG_USART_RX_PIN, configDBG_USART_RX_FUNCTION },
+ { configDBG_USART_TX_PIN, configDBG_USART_TX_FUNCTION }
+ };
+
+ /* Initialize the USART used for the debug trace with the configured parameters. */
+ set_usart_base( ( void * ) configDBG_USART );
+ gpio_enable_module( DBG_USART_GPIO_MAP,
+ sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[0] ) );
+ usart_init( configDBG_USART_BAUDRATE );
+ }
+ #endif
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * malloc, realloc and free are meant to be called through respectively
+ * pvPortMalloc, pvPortRealloc and vPortFree.
+ * The latter functions call the former ones from within sections where tasks
+ * are suspended, so the latter functions are task-safe. __malloc_lock and
+ * __malloc_unlock use the same mechanism to also keep the former functions
+ * task-safe as they may be called directly from Newlib's functions.
+ * However, all these functions are interrupt-unsafe and SHALL THEREFORE NOT BE
+ * CALLED FROM WITHIN AN INTERRUPT, because __malloc_lock and __malloc_unlock do
+ * not call portENTER_CRITICAL and portEXIT_CRITICAL in order not to disable
+ * interrupts during memory allocation management as this may be a very time-
+ * consuming process.
+ */
+
+/*
+ * Lock routine called by Newlib on malloc / realloc / free entry to guarantee a
+ * safe section as memory allocation management uses global data.
+ * See the aforementioned details.
+ */
+void __malloc_lock(struct _reent *ptr)
+{
+ vTaskSuspendAll();
+}
+
+/*
+ * Unlock routine called by Newlib on malloc / realloc / free exit to guarantee
+ * a safe section as memory allocation management uses global data.
+ * See the aforementioned details.
+ */
+void __malloc_unlock(struct _reent *ptr)
+{
+ xTaskResumeAll();
+}
+/*-----------------------------------------------------------*/
+
+/* Added as there is no such function in FreeRTOS. */
+void *pvPortRealloc( void *pv, size_t xWantedSize )
+{
+void *pvReturn;
+
+ vTaskSuspendAll();
+ {
+ pvReturn = realloc( pv, xWantedSize );
+ }
+ xTaskResumeAll();
+
+ return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+/* The cooperative scheduler requires a normal IRQ service routine to
+simply increment the system tick. */
+/* The preemptive scheduler is defined as "naked" as the full context is saved
+on entry as part of the context switch. */
+__attribute__((__naked__)) static void vTick( void )
+{
+ /* Save the context of the interrupted task. */
+ portSAVE_CONTEXT_OS_INT();
+
+ #if( configTICK_USE_TC==1 )
+ /* Clear the interrupt flag. */
+ prvClearTcInt();
+ #else
+ /* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
+ clock cycles from now. */
+ prvScheduleNextTick();
+ #endif
+
+ /* Because FreeRTOS is not supposed to run with nested interrupts, put all OS
+ calls in a critical section . */
+ portENTER_CRITICAL();
+ xTaskIncrementTick();
+ portEXIT_CRITICAL();
+
+ /* Restore the context of the "elected task". */
+ portRESTORE_CONTEXT_OS_INT();
+}
+/*-----------------------------------------------------------*/
+
+__attribute__((__naked__)) void SCALLYield( void )
+{
+ /* Save the context of the interrupted task. */
+ portSAVE_CONTEXT_SCALL();
+ vTaskSwitchContext();
+ portRESTORE_CONTEXT_SCALL();
+}
+/*-----------------------------------------------------------*/
+
+/* The code generated by the GCC compiler uses the stack in different ways at
+different optimisation levels. The interrupt flags can therefore not always
+be saved to the stack. Instead the critical section nesting level is stored
+in a variable, which is then saved as part of the stack context. */
+__attribute__((__noinline__)) void vPortEnterCritical( void )
+{
+ /* Disable interrupts */
+ portDISABLE_INTERRUPTS();
+
+ /* Now interrupts are disabled ulCriticalNesting can be accessed
+ directly. Increment ulCriticalNesting to keep a count of how many times
+ portENTER_CRITICAL() has been called. */
+ ulCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+__attribute__((__noinline__)) void vPortExitCritical( void )
+{
+ if(ulCriticalNesting > portNO_CRITICAL_NESTING)
+ {
+ ulCriticalNesting--;
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+ {
+ /* Enable all interrupt/exception. */
+ portENABLE_INTERRUPTS();
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been called.
+ *
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+ /* Setup the initial stack of the task. The stack is set exactly as
+ expected by the portRESTORE_CONTEXT() macro. */
+
+ /* When the task starts, it will expect to find the function parameter in R12. */
+ pxTopOfStack--;
+ *pxTopOfStack-- = ( StackType_t ) 0x08080808; /* R8 */
+ *pxTopOfStack-- = ( StackType_t ) 0x09090909; /* R9 */
+ *pxTopOfStack-- = ( StackType_t ) 0x0A0A0A0A; /* R10 */
+ *pxTopOfStack-- = ( StackType_t ) 0x0B0B0B0B; /* R11 */
+ *pxTopOfStack-- = ( StackType_t ) pvParameters; /* R12 */
+ *pxTopOfStack-- = ( StackType_t ) 0xDEADBEEF; /* R14/LR */
+ *pxTopOfStack-- = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; /* R15/PC */
+ *pxTopOfStack-- = ( StackType_t ) portINITIAL_SR; /* SR */
+ *pxTopOfStack-- = ( StackType_t ) 0xFF0000FF; /* R0 */
+ *pxTopOfStack-- = ( StackType_t ) 0x01010101; /* R1 */
+ *pxTopOfStack-- = ( StackType_t ) 0x02020202; /* R2 */
+ *pxTopOfStack-- = ( StackType_t ) 0x03030303; /* R3 */
+ *pxTopOfStack-- = ( StackType_t ) 0x04040404; /* R4 */
+ *pxTopOfStack-- = ( StackType_t ) 0x05050505; /* R5 */
+ *pxTopOfStack-- = ( StackType_t ) 0x06060606; /* R6 */
+ *pxTopOfStack-- = ( StackType_t ) 0x07070707; /* R7 */
+ *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_NESTING; /* ulCriticalNesting */
+
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ here already. */
+ prvSetupTimerInterrupt();
+
+ /* Start the first task. */
+ portRESTORE_CONTEXT();
+
+ /* Should not get here! */
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+ /* It is unlikely that the AVR32 port will require this function as there
+ is nothing to return to. */
+}
+/*-----------------------------------------------------------*/
+
+/* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
+clock cycles from now. */
+#if( configTICK_USE_TC==0 )
+ static void prvScheduleFirstTick(void)
+ {
+ uint32_t lCycles;
+
+ lCycles = Get_system_register(AVR32_COUNT);
+ lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
+ // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception
+ // generation feature does not get disabled.
+ if(0 == lCycles)
+ {
+ lCycles++;
+ }
+ Set_system_register(AVR32_COMPARE, lCycles);
+ }
+
+ __attribute__((__noinline__)) static void prvScheduleNextTick(void)
+ {
+ uint32_t lCycles, lCount;
+
+ lCycles = Get_system_register(AVR32_COMPARE);
+ lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
+ // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception
+ // generation feature does not get disabled.
+ if(0 == lCycles)
+ {
+ lCycles++;
+ }
+ lCount = Get_system_register(AVR32_COUNT);
+ if( lCycles < lCount )
+ { // We missed a tick, recover for the next.
+ lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
+ }
+ Set_system_register(AVR32_COMPARE, lCycles);
+ }
+#else
+ __attribute__((__noinline__)) static void prvClearTcInt(void)
+ {
+ AVR32_TC.channel[configTICK_TC_CHANNEL].sr;
+ }
+#endif
+/*-----------------------------------------------------------*/
+
+/* Setup the timer to generate the tick interrupts. */
+static void prvSetupTimerInterrupt(void)
+{
+#if( configTICK_USE_TC==1 )
+
+ volatile avr32_tc_t *tc = &AVR32_TC;
+
+ // Options for waveform genration.
+ tc_waveform_opt_t waveform_opt =
+ {
+ .channel = configTICK_TC_CHANNEL, /* Channel selection. */
+
+ .bswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOB. */
+ .beevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOB. */
+ .bcpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOB. */
+ .bcpb = TC_EVT_EFFECT_NOOP, /* RB compare effect on TIOB. */
+
+ .aswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOA. */
+ .aeevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOA. */
+ .acpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOA: toggle. */
+ .acpa = TC_EVT_EFFECT_NOOP, /* RA compare effect on TIOA: toggle (other possibilities are none, set and clear). */
+
+ .wavsel = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER,/* Waveform selection: Up mode without automatic trigger on RC compare. */
+ .enetrg = FALSE, /* External event trigger enable. */
+ .eevt = 0, /* External event selection. */
+ .eevtedg = TC_SEL_NO_EDGE, /* External event edge selection. */
+ .cpcdis = FALSE, /* Counter disable when RC compare. */
+ .cpcstop = FALSE, /* Counter clock stopped with RC compare. */
+
+ .burst = FALSE, /* Burst signal selection. */
+ .clki = FALSE, /* Clock inversion. */
+ .tcclks = TC_CLOCK_SOURCE_TC2 /* Internal source clock 2. */
+ };
+
+ tc_interrupt_t tc_interrupt =
+ {
+ .etrgs=0,
+ .ldrbs=0,
+ .ldras=0,
+ .cpcs =1,
+ .cpbs =0,
+ .cpas =0,
+ .lovrs=0,
+ .covfs=0,
+ };
+
+#endif
+
+ /* Disable all interrupt/exception. */
+ portDISABLE_INTERRUPTS();
+
+ /* Register the compare interrupt handler to the interrupt controller and
+ enable the compare interrupt. */
+
+ #if( configTICK_USE_TC==1 )
+ {
+ INTC_register_interrupt(&vTick, configTICK_TC_IRQ, INT0);
+
+ /* Initialize the timer/counter. */
+ tc_init_waveform(tc, &waveform_opt);
+
+ /* Set the compare triggers.
+ Remember TC counter is 16-bits, so counting second is not possible!
+ That's why we configure it to count ms. */
+ tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4) / configTICK_RATE_HZ );
+
+ tc_configure_interrupts( tc, configTICK_TC_CHANNEL, &tc_interrupt );
+
+ /* Start the timer/counter. */
+ tc_start(tc, configTICK_TC_CHANNEL);
+ }
+ #else
+ {
+ INTC_register_interrupt(&vTick, AVR32_CORE_COMPARE_IRQ, INT0);
+ prvScheduleFirstTick();
+ }
+ #endif
+}
diff --git a/portable/GCC/AVR32_UC3/portmacro.h b/portable/GCC/AVR32_UC3/portmacro.h
index f372508..2ebc711 100644
--- a/portable/GCC/AVR32_UC3/portmacro.h
+++ b/portable/GCC/AVR32_UC3/portmacro.h
@@ -1,696 +1,696 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT AND BSD-3-Clause
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*This file has been prepared for Doxygen automatic documentation generation.*/
-/*! \file *********************************************************************
- *
- * \brief FreeRTOS port source for AVR32 UC3.
- *
- * - Compiler: GNU GCC for AVR32
- * - Supported devices: All AVR32 devices can be used.
- * - AppNote:
- *
- * \author Atmel Corporation (Now Microchip):
- * https://www.microchip.com \n
- * Support and FAQ: https://www.microchip.com/support/
- *
- *****************************************************************************/
-
-/*
- * Copyright (c) 2007, Atmel Corporation All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of ATMEL may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
- * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-#include <avr32/io.h>
-#include "intc.h"
-#include "compiler.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT short
-#define portSTACK_TYPE uint32_t
-#define portBASE_TYPE long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#define TASK_DELAY_MS(x) ( (x) /portTICK_PERIOD_MS )
-#define TASK_DELAY_S(x) ( (x)*1000 /portTICK_PERIOD_MS )
-#define TASK_DELAY_MIN(x) ( (x)*60*1000/portTICK_PERIOD_MS )
-
-#define configTICK_TC_IRQ ATPASTE2(AVR32_TC_IRQ, configTICK_TC_CHANNEL)
-
-#if( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
-#else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH ( -1 )
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT 4
-#define portNOP() {__asm__ __volatile__ ("nop");}
-/*-----------------------------------------------------------*/
-
-
-/*-----------------------------------------------------------*/
-
-/* INTC-specific. */
-#define DISABLE_ALL_EXCEPTIONS() Disable_global_exception()
-#define ENABLE_ALL_EXCEPTIONS() Enable_global_exception()
-
-#define DISABLE_ALL_INTERRUPTS() Disable_global_interrupt()
-#define ENABLE_ALL_INTERRUPTS() Enable_global_interrupt()
-
-#define DISABLE_INT_LEVEL(int_lev) Disable_interrupt_level(int_lev)
-#define ENABLE_INT_LEVEL(int_lev) Enable_interrupt_level(int_lev)
-
-
-/*
- * Debug trace.
- * Activated if and only if configDBG is nonzero.
- * Prints a formatted string to stdout.
- * The current source file name and line number are output with a colon before
- * the formatted string.
- * A carriage return and a linefeed are appended to the output.
- * stdout is redirected to the USART configured by configDBG_USART.
- * The parameters are the same as for the standard printf function.
- * There is no return value.
- * SHALL NOT BE CALLED FROM WITHIN AN INTERRUPT as fputs and printf use malloc,
- * which is interrupt-unsafe with the current __malloc_lock and __malloc_unlock.
- */
-#if configDBG
-#define portDBG_TRACE(...) \
-{\
- fputs(__FILE__ ":" ASTRINGZ(__LINE__) ": ", stdout);\
- printf(__VA_ARGS__);\
- fputs("\r\n", stdout);\
-}
-#else
-#define portDBG_TRACE(...)
-#endif
-
-
-/* Critical section management. */
-#define portDISABLE_INTERRUPTS() DISABLE_ALL_INTERRUPTS()
-#define portENABLE_INTERRUPTS() ENABLE_ALL_INTERRUPTS()
-
-
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-
-#define portENTER_CRITICAL() vPortEnterCritical();
-#define portEXIT_CRITICAL() vPortExitCritical();
-
-
-/* Added as there is no such function in FreeRTOS. */
-extern void *pvPortRealloc( void *pv, size_t xSize );
-/*-----------------------------------------------------------*/
-
-
-/*=============================================================================================*/
-
-/*
- * Restore Context for cases other than INTi.
- */
-#define portRESTORE_CONTEXT() \
-{ \
- extern volatile uint32_t ulCriticalNesting; \
- extern volatile void *volatile pxCurrentTCB; \
- \
- __asm__ __volatile__ ( \
- /* Set SP to point to new stack */ \
- "mov r8, LO(%[pxCurrentTCB]) \n\t"\
- "orh r8, HI(%[pxCurrentTCB]) \n\t"\
- "ld.w r0, r8[0] \n\t"\
- "ld.w sp, r0[0] \n\t"\
- \
- /* Restore ulCriticalNesting variable */ \
- "ld.w r0, sp++ \n\t"\
- "mov r8, LO(%[ulCriticalNesting]) \n\t"\
- "orh r8, HI(%[ulCriticalNesting]) \n\t"\
- "st.w r8[0], r0 \n\t"\
- \
- /* Restore R0..R7 */ \
- "ldm sp++, r0-r7 \n\t"\
- /* R0-R7 should not be used below this line */ \
- /* Skip PC and SR (will do it at the end) */ \
- "sub sp, -2*4 \n\t"\
- /* Restore R8..R12 and LR */ \
- "ldm sp++, r8-r12, lr \n\t"\
- /* Restore SR */ \
- "ld.w r0, sp[-8*4]\n\t" /* R0 is modified, is restored later. */ \
- "mtsr %[SR], r0 \n\t"\
- /* Restore r0 */ \
- "ld.w r0, sp[-9*4] \n\t"\
- /* Restore PC */ \
- "ld.w pc, sp[-7*4]" /* Get PC from stack - PC is the 7th register saved */ \
- : \
- : [ulCriticalNesting] "i" (&ulCriticalNesting), \
- [pxCurrentTCB] "i" (&pxCurrentTCB), \
- [SR] "i" (AVR32_SR) \
- ); \
-}
-
-
-/*
- * portSAVE_CONTEXT_INT() and portRESTORE_CONTEXT_INT(): for INT0..3 exceptions.
- * portSAVE_CONTEXT_SCALL() and portRESTORE_CONTEXT_SCALL(): for the scall exception.
- *
- * Had to make different versions because registers saved on the system stack
- * are not the same between INT0..3 exceptions and the scall exception.
- */
-
-// Task context stack layout:
- // R8 (*)
- // R9 (*)
- // R10 (*)
- // R11 (*)
- // R12 (*)
- // R14/LR (*)
- // R15/PC (*)
- // SR (*)
- // R0
- // R1
- // R2
- // R3
- // R4
- // R5
- // R6
- // R7
- // ulCriticalNesting
-// (*) automatically done for INT0..INT3, but not for SCALL
-
-/*
- * The ISR used for the scheduler tick depends on whether the cooperative or
- * the preemptive scheduler is being used.
- */
-#if configUSE_PREEMPTION == 0
-
-/*
- * portSAVE_CONTEXT_OS_INT() for OS Tick exception.
- */
-#define portSAVE_CONTEXT_OS_INT() \
-{ \
- /* Save R0..R7 */ \
- __asm__ __volatile__ ("stm --sp, r0-r7"); \
- \
- /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
- /* there is also no context save. */ \
-}
-
-/*
- * portRESTORE_CONTEXT_OS_INT() for Tick exception.
- */
-#define portRESTORE_CONTEXT_OS_INT() \
-{ \
- __asm__ __volatile__ ( \
- /* Restore R0..R7 */ \
- "ldm sp++, r0-r7\n\t" \
- \
- /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
- /* there is also no context restore. */ \
- "rete" \
- ); \
-}
-
-#else
-
-/*
- * portSAVE_CONTEXT_OS_INT() for OS Tick exception.
- */
-#define portSAVE_CONTEXT_OS_INT() \
-{ \
- extern volatile uint32_t ulCriticalNesting; \
- extern volatile void *volatile pxCurrentTCB; \
- \
- /* When we come here */ \
- /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \
- \
- __asm__ __volatile__ ( \
- /* Save R0..R7 */ \
- "stm --sp, r0-r7 \n\t"\
- \
- /* Save ulCriticalNesting variable - R0 is overwritten */ \
- "mov r8, LO(%[ulCriticalNesting])\n\t" \
- "orh r8, HI(%[ulCriticalNesting])\n\t" \
- "ld.w r0, r8[0] \n\t"\
- "st.w --sp, r0 \n\t"\
- \
- /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
- /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
- /* level and allow other lower interrupt level to occur). */ \
- /* In this case we don't want to do a task switch because we don't know what the stack */ \
- /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
- /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
- /* will just be restoring the interrupt handler, no way!!! */ \
- /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
- "ld.w r0, sp[9*4]\n\t" /* Read SR in stack */ \
- "bfextu r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */ \
- "cp.w r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */ \
- "brhi LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE] \n\t"\
- \
- /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
- /* NOTE: we don't enter a critical section here because all interrupt handlers */ \
- /* MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as */ \
- /* portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. */ \
- /* => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. */ \
- "mov r8, LO(%[pxCurrentTCB])\n\t" \
- "orh r8, HI(%[pxCurrentTCB])\n\t" \
- "ld.w r0, r8[0]\n\t" \
- "st.w r0[0], sp\n" \
- \
- "LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE]:" \
- : \
- : [ulCriticalNesting] "i" (&ulCriticalNesting), \
- [pxCurrentTCB] "i" (&pxCurrentTCB), \
- [LINE] "i" (__LINE__) \
- ); \
-}
-
-/*
- * portRESTORE_CONTEXT_OS_INT() for Tick exception.
- */
-#define portRESTORE_CONTEXT_OS_INT() \
-{ \
- extern volatile uint32_t ulCriticalNesting; \
- extern volatile void *volatile pxCurrentTCB; \
- \
- /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
- /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
- /* level and allow other lower interrupt level to occur). */ \
- /* In this case we don't want to do a task switch because we don't know what the stack */ \
- /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
- /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
- /* will just be restoring the interrupt handler, no way!!! */ \
- __asm__ __volatile__ ( \
- "ld.w r0, sp[9*4]\n\t" /* Read SR in stack */ \
- "bfextu r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */ \
- "cp.w r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */ \
- "brhi LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]" \
- : \
- : [LINE] "i" (__LINE__) \
- ); \
- \
- /* Else */ \
- /* because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. */ \
- /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\
- portENTER_CRITICAL(); \
- vTaskSwitchContext(); \
- portEXIT_CRITICAL(); \
- \
- /* Restore all registers */ \
- \
- __asm__ __volatile__ ( \
- /* Set SP to point to new stack */ \
- "mov r8, LO(%[pxCurrentTCB]) \n\t"\
- "orh r8, HI(%[pxCurrentTCB]) \n\t"\
- "ld.w r0, r8[0] \n\t"\
- "ld.w sp, r0[0] \n"\
- \
- "LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]: \n\t"\
- \
- /* Restore ulCriticalNesting variable */ \
- "ld.w r0, sp++ \n\t" \
- "mov r8, LO(%[ulCriticalNesting]) \n\t"\
- "orh r8, HI(%[ulCriticalNesting]) \n\t"\
- "st.w r8[0], r0 \n\t"\
- \
- /* Restore R0..R7 */ \
- "ldm sp++, r0-r7 \n\t"\
- \
- /* Now, the stack should be R8..R12, LR, PC and SR */ \
- "rete" \
- : \
- : [ulCriticalNesting] "i" (&ulCriticalNesting), \
- [pxCurrentTCB] "i" (&pxCurrentTCB), \
- [LINE] "i" (__LINE__) \
- ); \
-}
-
-#endif
-
-
-/*
- * portSAVE_CONTEXT_SCALL() for SupervisorCALL exception.
- *
- * NOTE: taskYIELD()(== SCALL) MUST NOT be called in a mode > supervisor mode.
- *
- */
-#define portSAVE_CONTEXT_SCALL() \
-{ \
- extern volatile uint32_t ulCriticalNesting; \
- extern volatile void *volatile pxCurrentTCB; \
- \
- /* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */ \
- /* If SR[M2:M0] == 001 */ \
- /* PC and SR are on the stack. */ \
- /* Else (other modes) */ \
- /* Nothing on the stack. */ \
- \
- /* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */ \
- /* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */ \
- /* in an interrupt|exception handler. */ \
- \
- __asm__ __volatile__ ( \
- /* in order to save R0-R7 */ \
- "sub sp, 6*4 \n\t"\
- /* Save R0..R7 */ \
- "stm --sp, r0-r7 \n\t"\
- \
- /* in order to save R8-R12 and LR */ \
- /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
- "sub r7, sp,-16*4 \n\t"\
- /* Copy PC and SR in other places in the stack. */ \
- "ld.w r0, r7[-2*4] \n\t" /* Read SR */\
- "st.w r7[-8*4], r0 \n\t" /* Copy SR */\
- "ld.w r0, r7[-1*4] \n\t" /* Read PC */\
- "st.w r7[-7*4], r0 \n\t" /* Copy PC */\
- \
- /* Save R8..R12 and LR on the stack. */ \
- "stm --r7, r8-r12, lr \n\t"\
- \
- /* Arriving here we have the following stack organizations: */ \
- /* R8..R12, LR, PC, SR, R0..R7. */ \
- \
- /* Now we can finalize the save. */ \
- \
- /* Save ulCriticalNesting variable - R0 is overwritten */ \
- "mov r8, LO(%[ulCriticalNesting]) \n\t"\
- "orh r8, HI(%[ulCriticalNesting]) \n\t"\
- "ld.w r0, r8[0] \n\t"\
- "st.w --sp, r0" \
- : \
- : [ulCriticalNesting] "i" (&ulCriticalNesting) \
- ); \
- \
- /* Disable the its which may cause a context switch (i.e. cause a change of */ \
- /* pxCurrentTCB). */ \
- /* Basically, all accesses to the pxCurrentTCB structure should be put in a */ \
- /* critical section because it is a global structure. */ \
- portENTER_CRITICAL(); \
- \
- /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
- __asm__ __volatile__ ( \
- "mov r8, LO(%[pxCurrentTCB]) \n\t"\
- "orh r8, HI(%[pxCurrentTCB]) \n\t"\
- "ld.w r0, r8[0] \n\t"\
- "st.w r0[0], sp" \
- : \
- : [pxCurrentTCB] "i" (&pxCurrentTCB) \
- ); \
-}
-
-/*
- * portRESTORE_CONTEXT() for SupervisorCALL exception.
- */
-#define portRESTORE_CONTEXT_SCALL() \
-{ \
- extern volatile uint32_t ulCriticalNesting; \
- extern volatile void *volatile pxCurrentTCB; \
- \
- /* Restore all registers */ \
- \
- /* Set SP to point to new stack */ \
- __asm__ __volatile__ ( \
- "mov r8, LO(%[pxCurrentTCB]) \n\t"\
- "orh r8, HI(%[pxCurrentTCB]) \n\t"\
- "ld.w r0, r8[0] \n\t"\
- "ld.w sp, r0[0]" \
- : \
- : [pxCurrentTCB] "i" (&pxCurrentTCB) \
- ); \
- \
- /* Leave pxCurrentTCB variable access critical section */ \
- portEXIT_CRITICAL(); \
- \
- __asm__ __volatile__ ( \
- /* Restore ulCriticalNesting variable */ \
- "ld.w r0, sp++ \n\t"\
- "mov r8, LO(%[ulCriticalNesting]) \n\t"\
- "orh r8, HI(%[ulCriticalNesting]) \n\t"\
- "st.w r8[0], r0 \n\t"\
- \
- /* skip PC and SR */ \
- /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
- "sub r7, sp, -10*4 \n\t"\
- /* Restore r8-r12 and LR */ \
- "ldm r7++, r8-r12, lr \n\t"\
- \
- /* RETS will take care of the extra PC and SR restore. */ \
- /* So, we have to prepare the stack for this. */ \
- "ld.w r0, r7[-8*4] \n\t" /* Read SR */\
- "st.w r7[-2*4], r0 \n\t" /* Copy SR */\
- "ld.w r0, r7[-7*4] \n\t" /* Read PC */\
- "st.w r7[-1*4], r0 \n\t" /* Copy PC */\
- \
- /* Restore R0..R7 */ \
- "ldm sp++, r0-r7 \n\t"\
- \
- "sub sp, -6*4 \n\t"\
- \
- "rets" \
- : \
- : [ulCriticalNesting] "i" (&ulCriticalNesting) \
- ); \
-}
-
-
-/*
- * The ISR used depends on whether the cooperative or
- * the preemptive scheduler is being used.
- */
-#if configUSE_PREEMPTION == 0
-
-/*
- * ISR entry and exit macros. These are only required if a task switch
- * is required from the ISR.
- */
-#define portENTER_SWITCHING_ISR() \
-{ \
- /* Save R0..R7 */ \
- __asm__ __volatile__ ("stm --sp, r0-r7"); \
- \
- /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
- /* there is also no context save. */ \
-}
-
-/*
- * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
- */
-#define portEXIT_SWITCHING_ISR() \
-{ \
- __asm__ __volatile__ ( \
- /* Restore R0..R7 */ \
- "ldm sp++, r0-r7 \n\t"\
- \
- /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
- /* there is also no context restore. */ \
- "rete" \
- ); \
-}
-
-#else
-
-/*
- * ISR entry and exit macros. These are only required if a task switch
- * is required from the ISR.
- */
-#define portENTER_SWITCHING_ISR() \
-{ \
- extern volatile uint32_t ulCriticalNesting; \
- extern volatile void *volatile pxCurrentTCB; \
- \
- /* When we come here */ \
- /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \
- \
- __asm__ __volatile__ ( \
- /* Save R0..R7 */ \
- "stm --sp, r0-r7 \n\t"\
- \
- /* Save ulCriticalNesting variable - R0 is overwritten */ \
- "mov r8, LO(%[ulCriticalNesting]) \n\t"\
- "orh r8, HI(%[ulCriticalNesting]) \n\t"\
- "ld.w r0, r8[0] \n\t"\
- "st.w --sp, r0 \n\t"\
- \
- /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
- /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
- /* level and allow other lower interrupt level to occur). */ \
- /* In this case we don't want to do a task switch because we don't know what the stack */ \
- /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
- /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
- /* will just be restoring the interrupt handler, no way!!! */ \
- /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
- "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
- "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
- "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
- "brhi LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE] \n\t"\
- \
- /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
- "mov r8, LO(%[pxCurrentTCB]) \n\t"\
- "orh r8, HI(%[pxCurrentTCB]) \n\t"\
- "ld.w r0, r8[0] \n\t"\
- "st.w r0[0], sp \n"\
- \
- "LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE]:" \
- : \
- : [ulCriticalNesting] "i" (&ulCriticalNesting), \
- [pxCurrentTCB] "i" (&pxCurrentTCB), \
- [LINE] "i" (__LINE__) \
- ); \
-}
-
-/*
- * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
- */
-#define portEXIT_SWITCHING_ISR() \
-{ \
- extern volatile uint32_t ulCriticalNesting; \
- extern volatile void *volatile pxCurrentTCB; \
- \
- __asm__ __volatile__ ( \
- /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
- /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
- /* level and allow other lower interrupt level to occur). */ \
- /* In this case it's of no use to switch context and restore a new SP because we purposedly */ \
- /* did not previously save SP in its TCB. */ \
- "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
- "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
- "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
- "brhi LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE] \n\t"\
- \
- /* If a switch is required then we just need to call */ \
- /* vTaskSwitchContext() as the context has already been */ \
- /* saved. */ \
- "cp.w r12, 1 \n\t" /* Check if Switch context is required. */\
- "brne LABEL_ISR_RESTORE_CONTEXT_%[LINE]" \
- : \
- : [LINE] "i" (__LINE__) \
- ); \
- \
- /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */ \
- portENTER_CRITICAL(); \
- vTaskSwitchContext(); \
- portEXIT_CRITICAL(); \
- \
- __asm__ __volatile__ ( \
- "LABEL_ISR_RESTORE_CONTEXT_%[LINE]: \n\t"\
- /* Restore the context of which ever task is now the highest */ \
- /* priority that is ready to run. */ \
- \
- /* Restore all registers */ \
- \
- /* Set SP to point to new stack */ \
- "mov r8, LO(%[pxCurrentTCB]) \n\t"\
- "orh r8, HI(%[pxCurrentTCB]) \n\t"\
- "ld.w r0, r8[0] \n\t"\
- "ld.w sp, r0[0] \n"\
- \
- "LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE]: \n\t"\
- \
- /* Restore ulCriticalNesting variable */ \
- "ld.w r0, sp++ \n\t"\
- "mov r8, LO(%[ulCriticalNesting]) \n\t"\
- "orh r8, HI(%[ulCriticalNesting]) \n\t"\
- "st.w r8[0], r0 \n\t"\
- \
- /* Restore R0..R7 */ \
- "ldm sp++, r0-r7 \n\t"\
- \
- /* Now, the stack should be R8..R12, LR, PC and SR */ \
- "rete" \
- : \
- : [ulCriticalNesting] "i" (&ulCriticalNesting), \
- [pxCurrentTCB] "i" (&pxCurrentTCB), \
- [LINE] "i" (__LINE__) \
- ); \
-}
-
-#endif
-
-
-#define portYIELD() {__asm__ __volatile__ ("scall");}
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT AND BSD-3-Clause
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief FreeRTOS port source for AVR32 UC3.
+ *
+ * - Compiler: GNU GCC for AVR32
+ * - Supported devices: All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author Atmel Corporation (Now Microchip):
+ * https://www.microchip.com \n
+ * Support and FAQ: https://www.microchip.com/support/
+ *
+ *****************************************************************************/
+
+/*
+ * Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+#include <avr32/io.h>
+#include "intc.h"
+#include "compiler.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Type definitions. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#define TASK_DELAY_MS(x) ( (x) /portTICK_PERIOD_MS )
+#define TASK_DELAY_S(x) ( (x)*1000 /portTICK_PERIOD_MS )
+#define TASK_DELAY_MIN(x) ( (x)*60*1000/portTICK_PERIOD_MS )
+
+#define configTICK_TC_IRQ ATPASTE2(AVR32_TC_IRQ, configTICK_TC_CHANNEL)
+
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 4
+#define portNOP() {__asm__ __volatile__ ("nop");}
+/*-----------------------------------------------------------*/
+
+
+/*-----------------------------------------------------------*/
+
+/* INTC-specific. */
+#define DISABLE_ALL_EXCEPTIONS() Disable_global_exception()
+#define ENABLE_ALL_EXCEPTIONS() Enable_global_exception()
+
+#define DISABLE_ALL_INTERRUPTS() Disable_global_interrupt()
+#define ENABLE_ALL_INTERRUPTS() Enable_global_interrupt()
+
+#define DISABLE_INT_LEVEL(int_lev) Disable_interrupt_level(int_lev)
+#define ENABLE_INT_LEVEL(int_lev) Enable_interrupt_level(int_lev)
+
+
+/*
+ * Debug trace.
+ * Activated if and only if configDBG is nonzero.
+ * Prints a formatted string to stdout.
+ * The current source file name and line number are output with a colon before
+ * the formatted string.
+ * A carriage return and a linefeed are appended to the output.
+ * stdout is redirected to the USART configured by configDBG_USART.
+ * The parameters are the same as for the standard printf function.
+ * There is no return value.
+ * SHALL NOT BE CALLED FROM WITHIN AN INTERRUPT as fputs and printf use malloc,
+ * which is interrupt-unsafe with the current __malloc_lock and __malloc_unlock.
+ */
+#if configDBG
+#define portDBG_TRACE(...) \
+{\
+ fputs(__FILE__ ":" ASTRINGZ(__LINE__) ": ", stdout);\
+ printf(__VA_ARGS__);\
+ fputs("\r\n", stdout);\
+}
+#else
+#define portDBG_TRACE(...)
+#endif
+
+
+/* Critical section management. */
+#define portDISABLE_INTERRUPTS() DISABLE_ALL_INTERRUPTS()
+#define portENABLE_INTERRUPTS() ENABLE_ALL_INTERRUPTS()
+
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portENTER_CRITICAL() vPortEnterCritical();
+#define portEXIT_CRITICAL() vPortExitCritical();
+
+
+/* Added as there is no such function in FreeRTOS. */
+extern void *pvPortRealloc( void *pv, size_t xSize );
+/*-----------------------------------------------------------*/
+
+
+/*=============================================================================================*/
+
+/*
+ * Restore Context for cases other than INTi.
+ */
+#define portRESTORE_CONTEXT() \
+{ \
+ extern volatile uint32_t ulCriticalNesting; \
+ extern volatile void *volatile pxCurrentTCB; \
+ \
+ __asm__ __volatile__ ( \
+ /* Set SP to point to new stack */ \
+ "mov r8, LO(%[pxCurrentTCB]) \n\t"\
+ "orh r8, HI(%[pxCurrentTCB]) \n\t"\
+ "ld.w r0, r8[0] \n\t"\
+ "ld.w sp, r0[0] \n\t"\
+ \
+ /* Restore ulCriticalNesting variable */ \
+ "ld.w r0, sp++ \n\t"\
+ "mov r8, LO(%[ulCriticalNesting]) \n\t"\
+ "orh r8, HI(%[ulCriticalNesting]) \n\t"\
+ "st.w r8[0], r0 \n\t"\
+ \
+ /* Restore R0..R7 */ \
+ "ldm sp++, r0-r7 \n\t"\
+ /* R0-R7 should not be used below this line */ \
+ /* Skip PC and SR (will do it at the end) */ \
+ "sub sp, -2*4 \n\t"\
+ /* Restore R8..R12 and LR */ \
+ "ldm sp++, r8-r12, lr \n\t"\
+ /* Restore SR */ \
+ "ld.w r0, sp[-8*4]\n\t" /* R0 is modified, is restored later. */ \
+ "mtsr %[SR], r0 \n\t"\
+ /* Restore r0 */ \
+ "ld.w r0, sp[-9*4] \n\t"\
+ /* Restore PC */ \
+ "ld.w pc, sp[-7*4]" /* Get PC from stack - PC is the 7th register saved */ \
+ : \
+ : [ulCriticalNesting] "i" (&ulCriticalNesting), \
+ [pxCurrentTCB] "i" (&pxCurrentTCB), \
+ [SR] "i" (AVR32_SR) \
+ ); \
+}
+
+
+/*
+ * portSAVE_CONTEXT_INT() and portRESTORE_CONTEXT_INT(): for INT0..3 exceptions.
+ * portSAVE_CONTEXT_SCALL() and portRESTORE_CONTEXT_SCALL(): for the scall exception.
+ *
+ * Had to make different versions because registers saved on the system stack
+ * are not the same between INT0..3 exceptions and the scall exception.
+ */
+
+// Task context stack layout:
+ // R8 (*)
+ // R9 (*)
+ // R10 (*)
+ // R11 (*)
+ // R12 (*)
+ // R14/LR (*)
+ // R15/PC (*)
+ // SR (*)
+ // R0
+ // R1
+ // R2
+ // R3
+ // R4
+ // R5
+ // R6
+ // R7
+ // ulCriticalNesting
+// (*) automatically done for INT0..INT3, but not for SCALL
+
+/*
+ * The ISR used for the scheduler tick depends on whether the cooperative or
+ * the preemptive scheduler is being used.
+ */
+#if configUSE_PREEMPTION == 0
+
+/*
+ * portSAVE_CONTEXT_OS_INT() for OS Tick exception.
+ */
+#define portSAVE_CONTEXT_OS_INT() \
+{ \
+ /* Save R0..R7 */ \
+ __asm__ __volatile__ ("stm --sp, r0-r7"); \
+ \
+ /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
+ /* there is also no context save. */ \
+}
+
+/*
+ * portRESTORE_CONTEXT_OS_INT() for Tick exception.
+ */
+#define portRESTORE_CONTEXT_OS_INT() \
+{ \
+ __asm__ __volatile__ ( \
+ /* Restore R0..R7 */ \
+ "ldm sp++, r0-r7\n\t" \
+ \
+ /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
+ /* there is also no context restore. */ \
+ "rete" \
+ ); \
+}
+
+#else
+
+/*
+ * portSAVE_CONTEXT_OS_INT() for OS Tick exception.
+ */
+#define portSAVE_CONTEXT_OS_INT() \
+{ \
+ extern volatile uint32_t ulCriticalNesting; \
+ extern volatile void *volatile pxCurrentTCB; \
+ \
+ /* When we come here */ \
+ /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \
+ \
+ __asm__ __volatile__ ( \
+ /* Save R0..R7 */ \
+ "stm --sp, r0-r7 \n\t"\
+ \
+ /* Save ulCriticalNesting variable - R0 is overwritten */ \
+ "mov r8, LO(%[ulCriticalNesting])\n\t" \
+ "orh r8, HI(%[ulCriticalNesting])\n\t" \
+ "ld.w r0, r8[0] \n\t"\
+ "st.w --sp, r0 \n\t"\
+ \
+ /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
+ /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
+ /* level and allow other lower interrupt level to occur). */ \
+ /* In this case we don't want to do a task switch because we don't know what the stack */ \
+ /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
+ /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
+ /* will just be restoring the interrupt handler, no way!!! */ \
+ /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
+ "ld.w r0, sp[9*4]\n\t" /* Read SR in stack */ \
+ "bfextu r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */ \
+ "cp.w r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */ \
+ "brhi LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE] \n\t"\
+ \
+ /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
+ /* NOTE: we don't enter a critical section here because all interrupt handlers */ \
+ /* MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as */ \
+ /* portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. */ \
+ /* => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. */ \
+ "mov r8, LO(%[pxCurrentTCB])\n\t" \
+ "orh r8, HI(%[pxCurrentTCB])\n\t" \
+ "ld.w r0, r8[0]\n\t" \
+ "st.w r0[0], sp\n" \
+ \
+ "LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE]:" \
+ : \
+ : [ulCriticalNesting] "i" (&ulCriticalNesting), \
+ [pxCurrentTCB] "i" (&pxCurrentTCB), \
+ [LINE] "i" (__LINE__) \
+ ); \
+}
+
+/*
+ * portRESTORE_CONTEXT_OS_INT() for Tick exception.
+ */
+#define portRESTORE_CONTEXT_OS_INT() \
+{ \
+ extern volatile uint32_t ulCriticalNesting; \
+ extern volatile void *volatile pxCurrentTCB; \
+ \
+ /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
+ /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
+ /* level and allow other lower interrupt level to occur). */ \
+ /* In this case we don't want to do a task switch because we don't know what the stack */ \
+ /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
+ /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
+ /* will just be restoring the interrupt handler, no way!!! */ \
+ __asm__ __volatile__ ( \
+ "ld.w r0, sp[9*4]\n\t" /* Read SR in stack */ \
+ "bfextu r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */ \
+ "cp.w r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */ \
+ "brhi LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]" \
+ : \
+ : [LINE] "i" (__LINE__) \
+ ); \
+ \
+ /* Else */ \
+ /* because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. */ \
+ /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\
+ portENTER_CRITICAL(); \
+ vTaskSwitchContext(); \
+ portEXIT_CRITICAL(); \
+ \
+ /* Restore all registers */ \
+ \
+ __asm__ __volatile__ ( \
+ /* Set SP to point to new stack */ \
+ "mov r8, LO(%[pxCurrentTCB]) \n\t"\
+ "orh r8, HI(%[pxCurrentTCB]) \n\t"\
+ "ld.w r0, r8[0] \n\t"\
+ "ld.w sp, r0[0] \n"\
+ \
+ "LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]: \n\t"\
+ \
+ /* Restore ulCriticalNesting variable */ \
+ "ld.w r0, sp++ \n\t" \
+ "mov r8, LO(%[ulCriticalNesting]) \n\t"\
+ "orh r8, HI(%[ulCriticalNesting]) \n\t"\
+ "st.w r8[0], r0 \n\t"\
+ \
+ /* Restore R0..R7 */ \
+ "ldm sp++, r0-r7 \n\t"\
+ \
+ /* Now, the stack should be R8..R12, LR, PC and SR */ \
+ "rete" \
+ : \
+ : [ulCriticalNesting] "i" (&ulCriticalNesting), \
+ [pxCurrentTCB] "i" (&pxCurrentTCB), \
+ [LINE] "i" (__LINE__) \
+ ); \
+}
+
+#endif
+
+
+/*
+ * portSAVE_CONTEXT_SCALL() for SupervisorCALL exception.
+ *
+ * NOTE: taskYIELD()(== SCALL) MUST NOT be called in a mode > supervisor mode.
+ *
+ */
+#define portSAVE_CONTEXT_SCALL() \
+{ \
+ extern volatile uint32_t ulCriticalNesting; \
+ extern volatile void *volatile pxCurrentTCB; \
+ \
+ /* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */ \
+ /* If SR[M2:M0] == 001 */ \
+ /* PC and SR are on the stack. */ \
+ /* Else (other modes) */ \
+ /* Nothing on the stack. */ \
+ \
+ /* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */ \
+ /* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */ \
+ /* in an interrupt|exception handler. */ \
+ \
+ __asm__ __volatile__ ( \
+ /* in order to save R0-R7 */ \
+ "sub sp, 6*4 \n\t"\
+ /* Save R0..R7 */ \
+ "stm --sp, r0-r7 \n\t"\
+ \
+ /* in order to save R8-R12 and LR */ \
+ /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
+ "sub r7, sp,-16*4 \n\t"\
+ /* Copy PC and SR in other places in the stack. */ \
+ "ld.w r0, r7[-2*4] \n\t" /* Read SR */\
+ "st.w r7[-8*4], r0 \n\t" /* Copy SR */\
+ "ld.w r0, r7[-1*4] \n\t" /* Read PC */\
+ "st.w r7[-7*4], r0 \n\t" /* Copy PC */\
+ \
+ /* Save R8..R12 and LR on the stack. */ \
+ "stm --r7, r8-r12, lr \n\t"\
+ \
+ /* Arriving here we have the following stack organizations: */ \
+ /* R8..R12, LR, PC, SR, R0..R7. */ \
+ \
+ /* Now we can finalize the save. */ \
+ \
+ /* Save ulCriticalNesting variable - R0 is overwritten */ \
+ "mov r8, LO(%[ulCriticalNesting]) \n\t"\
+ "orh r8, HI(%[ulCriticalNesting]) \n\t"\
+ "ld.w r0, r8[0] \n\t"\
+ "st.w --sp, r0" \
+ : \
+ : [ulCriticalNesting] "i" (&ulCriticalNesting) \
+ ); \
+ \
+ /* Disable the its which may cause a context switch (i.e. cause a change of */ \
+ /* pxCurrentTCB). */ \
+ /* Basically, all accesses to the pxCurrentTCB structure should be put in a */ \
+ /* critical section because it is a global structure. */ \
+ portENTER_CRITICAL(); \
+ \
+ /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
+ __asm__ __volatile__ ( \
+ "mov r8, LO(%[pxCurrentTCB]) \n\t"\
+ "orh r8, HI(%[pxCurrentTCB]) \n\t"\
+ "ld.w r0, r8[0] \n\t"\
+ "st.w r0[0], sp" \
+ : \
+ : [pxCurrentTCB] "i" (&pxCurrentTCB) \
+ ); \
+}
+
+/*
+ * portRESTORE_CONTEXT() for SupervisorCALL exception.
+ */
+#define portRESTORE_CONTEXT_SCALL() \
+{ \
+ extern volatile uint32_t ulCriticalNesting; \
+ extern volatile void *volatile pxCurrentTCB; \
+ \
+ /* Restore all registers */ \
+ \
+ /* Set SP to point to new stack */ \
+ __asm__ __volatile__ ( \
+ "mov r8, LO(%[pxCurrentTCB]) \n\t"\
+ "orh r8, HI(%[pxCurrentTCB]) \n\t"\
+ "ld.w r0, r8[0] \n\t"\
+ "ld.w sp, r0[0]" \
+ : \
+ : [pxCurrentTCB] "i" (&pxCurrentTCB) \
+ ); \
+ \
+ /* Leave pxCurrentTCB variable access critical section */ \
+ portEXIT_CRITICAL(); \
+ \
+ __asm__ __volatile__ ( \
+ /* Restore ulCriticalNesting variable */ \
+ "ld.w r0, sp++ \n\t"\
+ "mov r8, LO(%[ulCriticalNesting]) \n\t"\
+ "orh r8, HI(%[ulCriticalNesting]) \n\t"\
+ "st.w r8[0], r0 \n\t"\
+ \
+ /* skip PC and SR */ \
+ /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
+ "sub r7, sp, -10*4 \n\t"\
+ /* Restore r8-r12 and LR */ \
+ "ldm r7++, r8-r12, lr \n\t"\
+ \
+ /* RETS will take care of the extra PC and SR restore. */ \
+ /* So, we have to prepare the stack for this. */ \
+ "ld.w r0, r7[-8*4] \n\t" /* Read SR */\
+ "st.w r7[-2*4], r0 \n\t" /* Copy SR */\
+ "ld.w r0, r7[-7*4] \n\t" /* Read PC */\
+ "st.w r7[-1*4], r0 \n\t" /* Copy PC */\
+ \
+ /* Restore R0..R7 */ \
+ "ldm sp++, r0-r7 \n\t"\
+ \
+ "sub sp, -6*4 \n\t"\
+ \
+ "rets" \
+ : \
+ : [ulCriticalNesting] "i" (&ulCriticalNesting) \
+ ); \
+}
+
+
+/*
+ * The ISR used depends on whether the cooperative or
+ * the preemptive scheduler is being used.
+ */
+#if configUSE_PREEMPTION == 0
+
+/*
+ * ISR entry and exit macros. These are only required if a task switch
+ * is required from the ISR.
+ */
+#define portENTER_SWITCHING_ISR() \
+{ \
+ /* Save R0..R7 */ \
+ __asm__ __volatile__ ("stm --sp, r0-r7"); \
+ \
+ /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
+ /* there is also no context save. */ \
+}
+
+/*
+ * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
+ */
+#define portEXIT_SWITCHING_ISR() \
+{ \
+ __asm__ __volatile__ ( \
+ /* Restore R0..R7 */ \
+ "ldm sp++, r0-r7 \n\t"\
+ \
+ /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
+ /* there is also no context restore. */ \
+ "rete" \
+ ); \
+}
+
+#else
+
+/*
+ * ISR entry and exit macros. These are only required if a task switch
+ * is required from the ISR.
+ */
+#define portENTER_SWITCHING_ISR() \
+{ \
+ extern volatile uint32_t ulCriticalNesting; \
+ extern volatile void *volatile pxCurrentTCB; \
+ \
+ /* When we come here */ \
+ /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \
+ \
+ __asm__ __volatile__ ( \
+ /* Save R0..R7 */ \
+ "stm --sp, r0-r7 \n\t"\
+ \
+ /* Save ulCriticalNesting variable - R0 is overwritten */ \
+ "mov r8, LO(%[ulCriticalNesting]) \n\t"\
+ "orh r8, HI(%[ulCriticalNesting]) \n\t"\
+ "ld.w r0, r8[0] \n\t"\
+ "st.w --sp, r0 \n\t"\
+ \
+ /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
+ /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
+ /* level and allow other lower interrupt level to occur). */ \
+ /* In this case we don't want to do a task switch because we don't know what the stack */ \
+ /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
+ /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
+ /* will just be restoring the interrupt handler, no way!!! */ \
+ /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
+ "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
+ "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
+ "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
+ "brhi LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE] \n\t"\
+ \
+ /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
+ "mov r8, LO(%[pxCurrentTCB]) \n\t"\
+ "orh r8, HI(%[pxCurrentTCB]) \n\t"\
+ "ld.w r0, r8[0] \n\t"\
+ "st.w r0[0], sp \n"\
+ \
+ "LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE]:" \
+ : \
+ : [ulCriticalNesting] "i" (&ulCriticalNesting), \
+ [pxCurrentTCB] "i" (&pxCurrentTCB), \
+ [LINE] "i" (__LINE__) \
+ ); \
+}
+
+/*
+ * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
+ */
+#define portEXIT_SWITCHING_ISR() \
+{ \
+ extern volatile uint32_t ulCriticalNesting; \
+ extern volatile void *volatile pxCurrentTCB; \
+ \
+ __asm__ __volatile__ ( \
+ /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
+ /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
+ /* level and allow other lower interrupt level to occur). */ \
+ /* In this case it's of no use to switch context and restore a new SP because we purposedly */ \
+ /* did not previously save SP in its TCB. */ \
+ "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
+ "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
+ "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
+ "brhi LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE] \n\t"\
+ \
+ /* If a switch is required then we just need to call */ \
+ /* vTaskSwitchContext() as the context has already been */ \
+ /* saved. */ \
+ "cp.w r12, 1 \n\t" /* Check if Switch context is required. */\
+ "brne LABEL_ISR_RESTORE_CONTEXT_%[LINE]" \
+ : \
+ : [LINE] "i" (__LINE__) \
+ ); \
+ \
+ /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */ \
+ portENTER_CRITICAL(); \
+ vTaskSwitchContext(); \
+ portEXIT_CRITICAL(); \
+ \
+ __asm__ __volatile__ ( \
+ "LABEL_ISR_RESTORE_CONTEXT_%[LINE]: \n\t"\
+ /* Restore the context of which ever task is now the highest */ \
+ /* priority that is ready to run. */ \
+ \
+ /* Restore all registers */ \
+ \
+ /* Set SP to point to new stack */ \
+ "mov r8, LO(%[pxCurrentTCB]) \n\t"\
+ "orh r8, HI(%[pxCurrentTCB]) \n\t"\
+ "ld.w r0, r8[0] \n\t"\
+ "ld.w sp, r0[0] \n"\
+ \
+ "LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE]: \n\t"\
+ \
+ /* Restore ulCriticalNesting variable */ \
+ "ld.w r0, sp++ \n\t"\
+ "mov r8, LO(%[ulCriticalNesting]) \n\t"\
+ "orh r8, HI(%[ulCriticalNesting]) \n\t"\
+ "st.w r8[0], r0 \n\t"\
+ \
+ /* Restore R0..R7 */ \
+ "ldm sp++, r0-r7 \n\t"\
+ \
+ /* Now, the stack should be R8..R12, LR, PC and SR */ \
+ "rete" \
+ : \
+ : [ulCriticalNesting] "i" (&ulCriticalNesting), \
+ [pxCurrentTCB] "i" (&pxCurrentTCB), \
+ [LINE] "i" (__LINE__) \
+ ); \
+}
+
+#endif
+
+
+#define portYIELD() {__asm__ __volatile__ ("scall");}
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/portable/GCC/CORTUS_APS3/port.c b/portable/GCC/CORTUS_APS3/port.c
index 0d7110b..e2ada1a 100644
--- a/portable/GCC/CORTUS_APS3/port.c
+++ b/portable/GCC/CORTUS_APS3/port.c
@@ -1,146 +1,146 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/* Standard includes. */
-#include <stdlib.h>
-
-/* Kernel includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Machine includes */
-#include <machine/counter.h>
-#include <machine/ic.h>
-/*-----------------------------------------------------------*/
-
-/* The initial PSR has the Previous Interrupt Enabled (PIEN) flag set. */
-#define portINITIAL_PSR ( 0x00020000 )
-
-/*-----------------------------------------------------------*/
-
-/*
- * Perform any hardware configuration necessary to generate the tick interrupt.
- */
-static void prvSetupTimerInterrupt( void );
-/*-----------------------------------------------------------*/
-
-StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
- /* Make space on the stack for the context - this leaves a couple of spaces
- empty. */
- pxTopOfStack -= 20;
-
- /* Fill the registers with known values to assist debugging. */
- pxTopOfStack[ 16 ] = 0;
- pxTopOfStack[ 15 ] = portINITIAL_PSR;
- pxTopOfStack[ 14 ] = ( uint32_t ) pxCode;
- pxTopOfStack[ 13 ] = 0x00000000UL; /* R15. */
- pxTopOfStack[ 12 ] = 0x00000000UL; /* R14. */
- pxTopOfStack[ 11 ] = 0x0d0d0d0dUL;
- pxTopOfStack[ 10 ] = 0x0c0c0c0cUL;
- pxTopOfStack[ 9 ] = 0x0b0b0b0bUL;
- pxTopOfStack[ 8 ] = 0x0a0a0a0aUL;
- pxTopOfStack[ 7 ] = 0x09090909UL;
- pxTopOfStack[ 6 ] = 0x08080808UL;
- pxTopOfStack[ 5 ] = 0x07070707UL;
- pxTopOfStack[ 4 ] = 0x06060606UL;
- pxTopOfStack[ 3 ] = 0x05050505UL;
- pxTopOfStack[ 2 ] = 0x04040404UL;
- pxTopOfStack[ 1 ] = 0x03030303UL;
- pxTopOfStack[ 0 ] = ( uint32_t ) pvParameters;
-
- return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
- /* Set-up the timer interrupt. */
- prvSetupTimerInterrupt();
-
- /* Integrated Interrupt Controller: Enable all interrupts. */
- ic->ien = 1;
-
- /* Restore callee saved registers. */
- portRESTORE_CONTEXT();
-
- /* Should not get here. */
- return 0;
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupTimerInterrupt( void )
-{
- /* Enable timer interrupts */
- counter1->reload = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1;
- counter1->value = counter1->reload;
- counter1->mask = 1;
-
- /* Set the IRQ Handler priority and enable it. */
- irq[ IRQ_COUNTER1 ].ien = 1;
-}
-/*-----------------------------------------------------------*/
-
-/* Trap 31 handler. */
-void interrupt31_handler( void ) __attribute__((naked));
-void interrupt31_handler( void )
-{
- portSAVE_CONTEXT();
- __asm volatile ( "call vTaskSwitchContext" );
- portRESTORE_CONTEXT();
-}
-/*-----------------------------------------------------------*/
-
-static void prvProcessTick( void ) __attribute__((noinline));
-static void prvProcessTick( void )
-{
- if( xTaskIncrementTick() != pdFALSE )
- {
- vTaskSwitchContext();
- }
-
- /* Clear the Tick Interrupt. */
- counter1->expired = 0;
-}
-/*-----------------------------------------------------------*/
-
-/* Timer 1 interrupt handler, used for tick interrupt. */
-void interrupt7_handler( void ) __attribute__((naked));
-void interrupt7_handler( void )
-{
- portSAVE_CONTEXT();
- prvProcessTick();
- portRESTORE_CONTEXT();
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
- /* Nothing to do. Unlikely to want to end. */
-}
-/*-----------------------------------------------------------*/
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Machine includes */
+#include <machine/counter.h>
+#include <machine/ic.h>
+/*-----------------------------------------------------------*/
+
+/* The initial PSR has the Previous Interrupt Enabled (PIEN) flag set. */
+#define portINITIAL_PSR ( 0x00020000 )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Perform any hardware configuration necessary to generate the tick interrupt.
+ */
+static void prvSetupTimerInterrupt( void );
+/*-----------------------------------------------------------*/
+
+StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+ /* Make space on the stack for the context - this leaves a couple of spaces
+ empty. */
+ pxTopOfStack -= 20;
+
+ /* Fill the registers with known values to assist debugging. */
+ pxTopOfStack[ 16 ] = 0;
+ pxTopOfStack[ 15 ] = portINITIAL_PSR;
+ pxTopOfStack[ 14 ] = ( uint32_t ) pxCode;
+ pxTopOfStack[ 13 ] = 0x00000000UL; /* R15. */
+ pxTopOfStack[ 12 ] = 0x00000000UL; /* R14. */
+ pxTopOfStack[ 11 ] = 0x0d0d0d0dUL;
+ pxTopOfStack[ 10 ] = 0x0c0c0c0cUL;
+ pxTopOfStack[ 9 ] = 0x0b0b0b0bUL;
+ pxTopOfStack[ 8 ] = 0x0a0a0a0aUL;
+ pxTopOfStack[ 7 ] = 0x09090909UL;
+ pxTopOfStack[ 6 ] = 0x08080808UL;
+ pxTopOfStack[ 5 ] = 0x07070707UL;
+ pxTopOfStack[ 4 ] = 0x06060606UL;
+ pxTopOfStack[ 3 ] = 0x05050505UL;
+ pxTopOfStack[ 2 ] = 0x04040404UL;
+ pxTopOfStack[ 1 ] = 0x03030303UL;
+ pxTopOfStack[ 0 ] = ( uint32_t ) pvParameters;
+
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+ /* Set-up the timer interrupt. */
+ prvSetupTimerInterrupt();
+
+ /* Integrated Interrupt Controller: Enable all interrupts. */
+ ic->ien = 1;
+
+ /* Restore callee saved registers. */
+ portRESTORE_CONTEXT();
+
+ /* Should not get here. */
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+ /* Enable timer interrupts */
+ counter1->reload = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1;
+ counter1->value = counter1->reload;
+ counter1->mask = 1;
+
+ /* Set the IRQ Handler priority and enable it. */
+ irq[ IRQ_COUNTER1 ].ien = 1;
+}
+/*-----------------------------------------------------------*/
+
+/* Trap 31 handler. */
+void interrupt31_handler( void ) __attribute__((naked));
+void interrupt31_handler( void )
+{
+ portSAVE_CONTEXT();
+ __asm volatile ( "call vTaskSwitchContext" );
+ portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+static void prvProcessTick( void ) __attribute__((noinline));
+static void prvProcessTick( void )
+{
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ vTaskSwitchContext();
+ }
+
+ /* Clear the Tick Interrupt. */
+ counter1->expired = 0;
+}
+/*-----------------------------------------------------------*/
+
+/* Timer 1 interrupt handler, used for tick interrupt. */
+void interrupt7_handler( void ) __attribute__((naked));
+void interrupt7_handler( void )
+{
+ portSAVE_CONTEXT();
+ prvProcessTick();
+ portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+ /* Nothing to do. Unlikely to want to end. */
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/CORTUS_APS3/portmacro.h b/portable/GCC/CORTUS_APS3/portmacro.h
index 210cbc1..486db87 100644
--- a/portable/GCC/CORTUS_APS3/portmacro.h
+++ b/portable/GCC/CORTUS_APS3/portmacro.h
@@ -1,153 +1,153 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <machine/cpu.h>
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT short
-#define portSTACK_TYPE uint32_t
-#define portBASE_TYPE long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
-#else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH ( -1 )
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT 4
-#define portNOP() __asm__ volatile ( "mov r0, r0" )
-#define portCRITICAL_NESTING_IN_TCB 1
-#define portIRQ_TRAP_YIELD 31
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-
-extern void vPortYield( void );
-
-/*---------------------------------------------------------------------------*/
-
-#define portYIELD() asm __volatile__( " trap #%0 "::"i"(portIRQ_TRAP_YIELD):"memory")
-/*---------------------------------------------------------------------------*/
-
-extern void vTaskEnterCritical( void );
-extern void vTaskExitCritical( void );
-#define portENTER_CRITICAL() vTaskEnterCritical()
-#define portEXIT_CRITICAL() vTaskExitCritical()
-/*---------------------------------------------------------------------------*/
-
-/* Critical section management. */
-#define portDISABLE_INTERRUPTS() cpu_int_disable()
-#define portENABLE_INTERRUPTS() cpu_int_enable()
-
-/*---------------------------------------------------------------------------*/
-
-#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) do { if( xHigherPriorityTaskWoken != pdFALSE ) vTaskSwitchContext(); } while( 0 )
-
-/*---------------------------------------------------------------------------*/
-
-#define portSAVE_CONTEXT() \
- asm __volatile__ \
- ( \
- "sub r1, #68 \n" /* Make space on the stack for the context. */ \
- "std r2, [r1] + 0 \n" \
- "stq r4, [r1] + 8 \n" \
- "stq r8, [r1] + 24 \n" \
- "stq r12, [r1] + 40 \n" \
- "mov r6, rtt \n" \
- "mov r7, psr \n" \
- "std r6, [r1] + 56 \n" \
- "movhi r2, #16384 \n" /* Set the pointer to the IC. */ \
- "ldub r3, [r2] + 2 \n" /* Load the current interrupt mask. */ \
- "st r3, [r1]+ 64 \n" /* Store the interrupt mask on the stack. */ \
- "ld r2, [r0]+short(pxCurrentTCB) \n" /* Load the pointer to the TCB. */ \
- "st r1, [r2] \n" /* Save the stack pointer into the TCB. */ \
- "mov r14, r1 \n" /* Compiler expects r14 to be set to the function stack. */ \
- );
-/*---------------------------------------------------------------------------*/
-
-#define portRESTORE_CONTEXT() \
- asm __volatile__( \
- "ld r2, [r0]+short(pxCurrentTCB) \n" /* Load the TCB to find the stack pointer and context. */ \
- "ld r1, [r2] \n" \
- "movhi r2, #16384 \n" /* Set the pointer to the IC. */ \
- "ld r3, [r1] + 64 \n" /* Load the previous interrupt mask. */ \
- "stb r3, [r2] + 2 \n" /* Set the current interrupt mask to be the previous. */ \
- "ldd r6, [r1] + 56 \n" /* Restore context. */ \
- "mov rtt, r6 \n" \
- "mov psr, r7 \n" \
- "ldd r2, [r1] + 0 \n" \
- "ldq r4, [r1] + 8 \n" \
- "ldq r8, [r1] + 24 \n" \
- "ldq r12, [r1] + 40 \n" \
- "add r1, #68 \n" \
- "rti \n" \
- );
-
-/*---------------------------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-/*---------------------------------------------------------------------------*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <machine/cpu.h>
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 4
+#define portNOP() __asm__ volatile ( "mov r0, r0" )
+#define portCRITICAL_NESTING_IN_TCB 1
+#define portIRQ_TRAP_YIELD 31
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+extern void vPortYield( void );
+
+/*---------------------------------------------------------------------------*/
+
+#define portYIELD() asm __volatile__( " trap #%0 "::"i"(portIRQ_TRAP_YIELD):"memory")
+/*---------------------------------------------------------------------------*/
+
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL() vTaskEnterCritical()
+#define portEXIT_CRITICAL() vTaskExitCritical()
+/*---------------------------------------------------------------------------*/
+
+/* Critical section management. */
+#define portDISABLE_INTERRUPTS() cpu_int_disable()
+#define portENABLE_INTERRUPTS() cpu_int_enable()
+
+/*---------------------------------------------------------------------------*/
+
+#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) do { if( xHigherPriorityTaskWoken != pdFALSE ) vTaskSwitchContext(); } while( 0 )
+
+/*---------------------------------------------------------------------------*/
+
+#define portSAVE_CONTEXT() \
+ asm __volatile__ \
+ ( \
+ "sub r1, #68 \n" /* Make space on the stack for the context. */ \
+ "std r2, [r1] + 0 \n" \
+ "stq r4, [r1] + 8 \n" \
+ "stq r8, [r1] + 24 \n" \
+ "stq r12, [r1] + 40 \n" \
+ "mov r6, rtt \n" \
+ "mov r7, psr \n" \
+ "std r6, [r1] + 56 \n" \
+ "movhi r2, #16384 \n" /* Set the pointer to the IC. */ \
+ "ldub r3, [r2] + 2 \n" /* Load the current interrupt mask. */ \
+ "st r3, [r1]+ 64 \n" /* Store the interrupt mask on the stack. */ \
+ "ld r2, [r0]+short(pxCurrentTCB) \n" /* Load the pointer to the TCB. */ \
+ "st r1, [r2] \n" /* Save the stack pointer into the TCB. */ \
+ "mov r14, r1 \n" /* Compiler expects r14 to be set to the function stack. */ \
+ );
+/*---------------------------------------------------------------------------*/
+
+#define portRESTORE_CONTEXT() \
+ asm __volatile__( \
+ "ld r2, [r0]+short(pxCurrentTCB) \n" /* Load the TCB to find the stack pointer and context. */ \
+ "ld r1, [r2] \n" \
+ "movhi r2, #16384 \n" /* Set the pointer to the IC. */ \
+ "ld r3, [r1] + 64 \n" /* Load the previous interrupt mask. */ \
+ "stb r3, [r2] + 2 \n" /* Set the current interrupt mask to be the previous. */ \
+ "ldd r6, [r1] + 56 \n" /* Restore context. */ \
+ "mov rtt, r6 \n" \
+ "mov psr, r7 \n" \
+ "ldd r2, [r1] + 0 \n" \
+ "ldq r4, [r1] + 8 \n" \
+ "ldq r8, [r1] + 24 \n" \
+ "ldq r12, [r1] + 40 \n" \
+ "add r1, #68 \n" \
+ "rti \n" \
+ );
+
+/*---------------------------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*---------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/portable/GCC/ColdFire_V2/port.c b/portable/GCC/ColdFire_V2/port.c
index 2db9afe..cbf5693 100644
--- a/portable/GCC/ColdFire_V2/port.c
+++ b/portable/GCC/ColdFire_V2/port.c
@@ -1,135 +1,129 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/* Kernel includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-#define portINITIAL_FORMAT_VECTOR ( ( StackType_t ) 0x4000 )
-
-/* Supervisor mode set. */
-#define portINITIAL_STATUS_REGISTER ( ( StackType_t ) 0x2000)
-
-/* Used to keep track of the number of nested calls to taskENTER_CRITICAL(). This
-will be set to 0 prior to the first task being started. */
-static uint32_t ulCriticalNesting = 0x9999UL;
-
-/*-----------------------------------------------------------*/
-
-StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
- *pxTopOfStack = ( StackType_t ) pvParameters;
- pxTopOfStack--;
-
- *pxTopOfStack = (StackType_t) 0xDEADBEEF;
- pxTopOfStack--;
-
- /* Exception stack frame starts with the return address. */
- *pxTopOfStack = ( StackType_t ) pxCode;
- pxTopOfStack--;
-
- *pxTopOfStack = ( portINITIAL_FORMAT_VECTOR << 16UL ) | ( portINITIAL_STATUS_REGISTER );
- pxTopOfStack--;
-
- *pxTopOfStack = ( StackType_t ) 0x0; /*FP*/
- pxTopOfStack -= 14; /* A5 to D0. */
-
- return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-extern void vPortStartFirstTask( void );
-
- ulCriticalNesting = 0UL;
-
- /* Configure the interrupts used by this port. */
- vApplicationSetupInterrupts();
-
- /* Start the first task executing. */
- vPortStartFirstTask();
-
- return pdFALSE;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
- /* Not implemented as there is nothing to return to. */
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
- if( ulCriticalNesting == 0UL )
- {
- /* Guard against context switches being pended simultaneously with a
- critical section being entered. */
- do
- {
- portDISABLE_INTERRUPTS();
- if( MCF_INTC0_INTFRCL == 0UL )
- {
- break;
- }
-
- portENABLE_INTERRUPTS();
-
- } while( 1 );
- }
- ulCriticalNesting++;
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
- ulCriticalNesting--;
- if( ulCriticalNesting == 0 )
- {
- portENABLE_INTERRUPTS();
- }
-}
-/*-----------------------------------------------------------*/
-
-void vPortYieldHandler( void )
-{
-uint32_t ulSavedInterruptMask;
-
- ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
- /* Note this will clear all forced interrupts - this is done for speed. */
- MCF_INTC0_INTFRCL = 0;
- vTaskSwitchContext();
- portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
-}
-
-
-
-
-
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#define portINITIAL_FORMAT_VECTOR ( ( StackType_t ) 0x4000 )
+
+/* Supervisor mode set. */
+#define portINITIAL_STATUS_REGISTER ( ( StackType_t ) 0x2000)
+
+/* Used to keep track of the number of nested calls to taskENTER_CRITICAL(). This
+will be set to 0 prior to the first task being started. */
+static uint32_t ulCriticalNesting = 0x9999UL;
+
+/*-----------------------------------------------------------*/
+
+StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+ *pxTopOfStack = ( StackType_t ) pvParameters;
+ pxTopOfStack--;
+
+ *pxTopOfStack = (StackType_t) 0xDEADBEEF;
+ pxTopOfStack--;
+
+ /* Exception stack frame starts with the return address. */
+ *pxTopOfStack = ( StackType_t ) pxCode;
+ pxTopOfStack--;
+
+ *pxTopOfStack = ( portINITIAL_FORMAT_VECTOR << 16UL ) | ( portINITIAL_STATUS_REGISTER );
+ pxTopOfStack--;
+
+ *pxTopOfStack = ( StackType_t ) 0x0; /*FP*/
+ pxTopOfStack -= 14; /* A5 to D0. */
+
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vPortStartFirstTask( void );
+
+ ulCriticalNesting = 0UL;
+
+ /* Configure the interrupts used by this port. */
+ vApplicationSetupInterrupts();
+
+ /* Start the first task executing. */
+ vPortStartFirstTask();
+
+ return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+ /* Not implemented as there is nothing to return to. */
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+ if( ulCriticalNesting == 0UL )
+ {
+ /* Guard against context switches being pended simultaneously with a
+ critical section being entered. */
+ do
+ {
+ portDISABLE_INTERRUPTS();
+ if( MCF_INTC0_INTFRCL == 0UL )
+ {
+ break;
+ }
+
+ portENABLE_INTERRUPTS();
+
+ } while( 1 );
+ }
+ ulCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+ ulCriticalNesting--;
+ if( ulCriticalNesting == 0 )
+ {
+ portENABLE_INTERRUPTS();
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vPortYieldHandler( void )
+{
+uint32_t ulSavedInterruptMask;
+
+ ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
+ /* Note this will clear all forced interrupts - this is done for speed. */
+ MCF_INTC0_INTFRCL = 0;
+ vTaskSwitchContext();
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
+}
diff --git a/portable/GCC/ColdFire_V2/portasm.S b/portable/GCC/ColdFire_V2/portasm.S
index 66c40f8..a3c6aca 100644
--- a/portable/GCC/ColdFire_V2/portasm.S
+++ b/portable/GCC/ColdFire_V2/portasm.S
@@ -1,121 +1,119 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*
- * Purpose: Lowest level routines for all ColdFire processors.
- *
- * Notes:
- *
- * ulPortSetIPL() and mcf5xxx_wr_cacr() copied with permission from FreeScale
- * supplied source files.
- */
-
- .global ulPortSetIPL
- .global mcf5xxx_wr_cacr
- .global __cs3_isr_interrupt_80
- .global vPortStartFirstTask
-
- .text
-
-.macro portSAVE_CONTEXT
-
- lea.l (-60, %sp), %sp
- movem.l %d0-%fp, (%sp)
- move.l pxCurrentTCB, %a0
- move.l %sp, (%a0)
-
- .endm
-
-.macro portRESTORE_CONTEXT
-
- move.l pxCurrentTCB, %a0
- move.l (%a0), %sp
- movem.l (%sp), %d0-%fp
- lea.l %sp@(60), %sp
- rte
-
- .endm
-
-/********************************************************************/
-/*
- * This routines changes the IPL to the value passed into the routine.
- * It also returns the old IPL value back.
- * Calling convention from C:
- * old_ipl = asm_set_ipl(new_ipl);
- * For the Diab Data C compiler, it passes return value thru D0.
- * Note that only the least significant three bits of the passed
- * value are used.
- */
-
-ulPortSetIPL:
- link A6,#-8
- movem.l D6-D7,(SP)
-
- move.w SR,D7 /* current sr */
-
- move.l D7,D0 /* prepare return value */
- andi.l #0x0700,D0 /* mask out IPL */
- lsr.l #8,D0 /* IPL */
-
- move.l 8(A6),D6 /* get argument */
- andi.l #0x07,D6 /* least significant three bits */
- lsl.l #8,D6 /* move over to make mask */
-
- andi.l #0x0000F8FF,D7 /* zero out current IPL */
- or.l D6,D7 /* place new IPL in sr */
- move.w D7,SR
-
- movem.l (SP),D6-D7
- lea 8(SP),SP
- unlk A6
- rts
-/********************************************************************/
-
-mcf5xxx_wr_cacr:
- move.l 4(sp),d0
- .long 0x4e7b0002 /* movec d0,cacr */
- nop
- rts
-
-/********************************************************************/
-
-/* Yield interrupt. */
-__cs3_isr_interrupt_80:
- portSAVE_CONTEXT
- jsr vPortYieldHandler
- portRESTORE_CONTEXT
-
-/********************************************************************/
-
-
-vPortStartFirstTask:
- portRESTORE_CONTEXT
-
- .end
-
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*
+ * Purpose: Lowest level routines for all ColdFire processors.
+ *
+ * Notes:
+ *
+ * ulPortSetIPL() and mcf5xxx_wr_cacr() copied with permission from FreeScale
+ * supplied source files.
+ */
+
+ .global ulPortSetIPL
+ .global mcf5xxx_wr_cacr
+ .global __cs3_isr_interrupt_80
+ .global vPortStartFirstTask
+
+ .text
+
+.macro portSAVE_CONTEXT
+
+ lea.l (-60, %sp), %sp
+ movem.l %d0-%fp, (%sp)
+ move.l pxCurrentTCB, %a0
+ move.l %sp, (%a0)
+
+ .endm
+
+.macro portRESTORE_CONTEXT
+
+ move.l pxCurrentTCB, %a0
+ move.l (%a0), %sp
+ movem.l (%sp), %d0-%fp
+ lea.l %sp@(60), %sp
+ rte
+
+ .endm
+
+/********************************************************************/
+/*
+ * This routines changes the IPL to the value passed into the routine.
+ * It also returns the old IPL value back.
+ * Calling convention from C:
+ * old_ipl = asm_set_ipl(new_ipl);
+ * For the Diab Data C compiler, it passes return value thru D0.
+ * Note that only the least significant three bits of the passed
+ * value are used.
+ */
+
+ulPortSetIPL:
+ link A6,#-8
+ movem.l D6-D7,(SP)
+
+ move.w SR,D7 /* current sr */
+
+ move.l D7,D0 /* prepare return value */
+ andi.l #0x0700,D0 /* mask out IPL */
+ lsr.l #8,D0 /* IPL */
+
+ move.l 8(A6),D6 /* get argument */
+ andi.l #0x07,D6 /* least significant three bits */
+ lsl.l #8,D6 /* move over to make mask */
+
+ andi.l #0x0000F8FF,D7 /* zero out current IPL */
+ or.l D6,D7 /* place new IPL in sr */
+ move.w D7,SR
+
+ movem.l (SP),D6-D7
+ lea 8(SP),SP
+ unlk A6
+ rts
+/********************************************************************/
+
+mcf5xxx_wr_cacr:
+ move.l 4(sp),d0
+ .long 0x4e7b0002 /* movec d0,cacr */
+ nop
+ rts
+
+/********************************************************************/
+
+/* Yield interrupt. */
+__cs3_isr_interrupt_80:
+ portSAVE_CONTEXT
+ jsr vPortYieldHandler
+ portRESTORE_CONTEXT
+
+/********************************************************************/
+
+
+vPortStartFirstTask:
+ portRESTORE_CONTEXT
+
+ .end
diff --git a/portable/GCC/ColdFire_V2/portmacro.h b/portable/GCC/ColdFire_V2/portmacro.h
index 819e4a6..8792cd9 100644
--- a/portable/GCC/ColdFire_V2/portmacro.h
+++ b/portable/GCC/ColdFire_V2/portmacro.h
@@ -1,112 +1,111 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT short
-#define portSTACK_TYPE uint32_t
-#define portBASE_TYPE long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
-#else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portBYTE_ALIGNMENT 4
-#define portSTACK_GROWTH -1
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-/*-----------------------------------------------------------*/
-uint32_t ulPortSetIPL( uint32_t );
-#define portDISABLE_INTERRUPTS() ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-#define portENABLE_INTERRUPTS() ulPortSetIPL( 0 )
-
-
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-#define portENTER_CRITICAL() vPortEnterCritical()
-#define portEXIT_CRITICAL() vPortExitCritical()
-
-extern UBaseType_t uxPortSetInterruptMaskFromISR( void );
-extern void vPortClearInterruptMaskFromISR( UBaseType_t );
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) ulPortSetIPL( uxSavedStatusRegister )
-
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-
-#define portNOP() asm volatile ( "nop" )
-
-/* Note this will overwrite all other bits in the force register, it is done this way for speed. */
-#define portYIELD() MCF_INTC0_INTFRCL = ( 1UL << configYIELD_INTERRUPT_VECTOR ); portNOP(); portNOP()
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) { portYIELD(); } } while( 0 )
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT 4
+#define portSTACK_GROWTH -1
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+/*-----------------------------------------------------------*/
+uint32_t ulPortSetIPL( uint32_t );
+#define portDISABLE_INTERRUPTS() ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portENABLE_INTERRUPTS() ulPortSetIPL( 0 )
+
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
+
+extern UBaseType_t uxPortSetInterruptMaskFromISR( void );
+extern void vPortClearInterruptMaskFromISR( UBaseType_t );
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) ulPortSetIPL( uxSavedStatusRegister )
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+#define portNOP() asm volatile ( "nop" )
+
+/* Note this will overwrite all other bits in the force register, it is done this way for speed. */
+#define portYIELD() MCF_INTC0_INTFRCL = ( 1UL << configYIELD_INTERRUPT_VECTOR ); portNOP(); portNOP()
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) { portYIELD(); } } while( 0 )
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/portable/GCC/H8S2329/port.c b/portable/GCC/H8S2329/port.c
index f3fad3a..660cb81 100644
--- a/portable/GCC/H8S2329/port.c
+++ b/portable/GCC/H8S2329/port.c
@@ -1,304 +1,301 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the H8S port.
- *----------------------------------------------------------*/
-
-
-/*-----------------------------------------------------------*/
-
-/* When the task starts interrupts should be enabled. */
-#define portINITIAL_CCR ( ( StackType_t ) 0x00 )
-
-/* Hardware specific constants used to generate the RTOS tick from the TPU. */
-#define portCLEAR_ON_TGRA_COMPARE_MATCH ( ( uint8_t ) 0x20 )
-#define portCLOCK_DIV_64 ( ( uint8_t ) 0x03 )
-#define portCLOCK_DIV ( ( uint32_t ) 64 )
-#define portTGRA_INTERRUPT_ENABLE ( ( uint8_t ) 0x01 )
-#define portTIMER_CHANNEL ( ( uint8_t ) 0x02 )
-#define portMSTP13 ( ( uint16_t ) 0x2000 )
-
-/*
- * Setup TPU channel one for the RTOS tick at the requested frequency.
- */
-static void prvSetupTimerInterrupt( void );
-
-/*
- * The ISR used by portYIELD(). This is installed as a trap handler.
- */
-void vPortYield( void ) __attribute__ ( ( saveall, interrupt_handler ) );
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-uint32_t ulValue;
-
- /* This requires an even address. */
- ulValue = ( uint32_t ) pxTopOfStack;
- if( ulValue & 1UL )
- {
- pxTopOfStack = pxTopOfStack - 1;
- }
-
- /* Place a few bytes of known values on the bottom of the stack.
- This is just useful for debugging. */
- pxTopOfStack--;
- *pxTopOfStack = 0xaa;
- pxTopOfStack--;
- *pxTopOfStack = 0xbb;
- pxTopOfStack--;
- *pxTopOfStack = 0xcc;
- pxTopOfStack--;
- *pxTopOfStack = 0xdd;
-
- /* The initial stack mimics an interrupt stack. First there is the program
- counter (24 bits). */
- ulValue = ( uint32_t ) pxCode;
-
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
- pxTopOfStack--;
- ulValue >>= 8UL;
- *pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
- pxTopOfStack--;
- ulValue >>= 8UL;
- *pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
-
- /* Followed by the CCR. */
- pxTopOfStack--;
- *pxTopOfStack = portINITIAL_CCR;
-
- /* Next all the general purpose registers - with the parameters being passed
- in ER0. The parameter order must match that used by the compiler when the
- "saveall" function attribute is used. */
-
- /* ER6 */
- pxTopOfStack--;
- *pxTopOfStack = 0x66;
- pxTopOfStack--;
- *pxTopOfStack = 0x66;
- pxTopOfStack--;
- *pxTopOfStack = 0x66;
- pxTopOfStack--;
- *pxTopOfStack = 0x66;
-
- /* ER0 */
- ulValue = ( uint32_t ) pvParameters;
-
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
- pxTopOfStack--;
- ulValue >>= 8UL;
- *pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
- pxTopOfStack--;
- ulValue >>= 8UL;
- *pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
- pxTopOfStack--;
- ulValue >>= 8UL;
- *pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
-
- /* ER1 */
- pxTopOfStack--;
- *pxTopOfStack = 0x11;
- pxTopOfStack--;
- *pxTopOfStack = 0x11;
- pxTopOfStack--;
- *pxTopOfStack = 0x11;
- pxTopOfStack--;
- *pxTopOfStack = 0x11;
-
- /* ER2 */
- pxTopOfStack--;
- *pxTopOfStack = 0x22;
- pxTopOfStack--;
- *pxTopOfStack = 0x22;
- pxTopOfStack--;
- *pxTopOfStack = 0x22;
- pxTopOfStack--;
- *pxTopOfStack = 0x22;
-
- /* ER3 */
- pxTopOfStack--;
- *pxTopOfStack = 0x33;
- pxTopOfStack--;
- *pxTopOfStack = 0x33;
- pxTopOfStack--;
- *pxTopOfStack = 0x33;
- pxTopOfStack--;
- *pxTopOfStack = 0x33;
-
- /* ER4 */
- pxTopOfStack--;
- *pxTopOfStack = 0x44;
- pxTopOfStack--;
- *pxTopOfStack = 0x44;
- pxTopOfStack--;
- *pxTopOfStack = 0x44;
- pxTopOfStack--;
- *pxTopOfStack = 0x44;
-
- /* ER5 */
- pxTopOfStack--;
- *pxTopOfStack = 0x55;
- pxTopOfStack--;
- *pxTopOfStack = 0x55;
- pxTopOfStack--;
- *pxTopOfStack = 0x55;
- pxTopOfStack--;
- *pxTopOfStack = 0x55;
-
- return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-extern void * pxCurrentTCB;
-
- /* Setup the hardware to generate the tick. */
- prvSetupTimerInterrupt();
-
- /* Restore the context of the first task that is going to run. This
- mirrors the function epilogue code generated by the compiler when the
- "saveall" function attribute is used. */
- asm volatile (
- "MOV.L @_pxCurrentTCB, ER6 \n\t"
- "MOV.L @ER6, ER7 \n\t"
- "LDM.L @SP+, (ER4-ER5) \n\t"
- "LDM.L @SP+, (ER0-ER3) \n\t"
- "MOV.L @ER7+, ER6 \n\t"
- "RTE \n\t"
- );
-
- ( void ) pxCurrentTCB;
-
- /* Should not get here. */
- return pdTRUE;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
- /* It is unlikely that the h8 port will get stopped. */
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Manual context switch. This is a trap handler. The "saveall" function
- * attribute is used so the context is saved by the compiler prologue. All
- * we have to do is save the stack pointer.
- */
-void vPortYield( void )
-{
- portSAVE_STACK_POINTER();
- vTaskSwitchContext();
- portRESTORE_STACK_POINTER();
-}
-/*-----------------------------------------------------------*/
-
-/*
- * The interrupt handler installed for the RTOS tick depends on whether the
- * preemptive or cooperative scheduler is being used.
- */
-#if( configUSE_PREEMPTION == 1 )
-
- /*
- * The preemptive scheduler is used so the ISR calls vTaskSwitchContext().
- * The function prologue saves the context so all we have to do is save
- * the stack pointer.
- */
- void vTickISR( void ) __attribute__ ( ( saveall, interrupt_handler ) );
- void vTickISR( void )
- {
- portSAVE_STACK_POINTER();
-
- if( xTaskIncrementTick() != pdFALSE )
- {
- vTaskSwitchContext();
- }
-
- /* Clear the interrupt. */
- TSR1 &= ~0x01;
-
- portRESTORE_STACK_POINTER();
- }
-
-#else
-
- /*
- * The cooperative scheduler is being used so all we have to do is
- * periodically increment the tick. This can just be a normal ISR and
- * the "saveall" attribute is not required.
- */
- void vTickISR( void ) __attribute__ ( ( interrupt_handler ) );
- void vTickISR( void )
- {
- xTaskIncrementTick();
-
- /* Clear the interrupt. */
- TSR1 &= ~0x01;
- }
-
-#endif
-/*-----------------------------------------------------------*/
-
-/*
- * Setup timer 1 compare match to generate a tick interrupt.
- */
-static void prvSetupTimerInterrupt( void )
-{
-const uint32_t ulCompareMatch = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) / portCLOCK_DIV;
-
- /* Turn the module on. */
- MSTPCR &= ~portMSTP13;
-
- /* Configure timer 1. */
- TCR1 = portCLEAR_ON_TGRA_COMPARE_MATCH | portCLOCK_DIV_64;
-
- /* Configure the compare match value for a tick of configTICK_RATE_HZ. */
- TGR1A = ulCompareMatch;
-
- /* Start the timer and enable the interrupt - we can do this here as
- interrupts are globally disabled when this function is called. */
- TIER1 |= portTGRA_INTERRUPT_ENABLE;
- TSTR |= portTIMER_CHANNEL;
-}
-/*-----------------------------------------------------------*/
-
-
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the H8S port.
+ *----------------------------------------------------------*/
+
+
+/*-----------------------------------------------------------*/
+
+/* When the task starts interrupts should be enabled. */
+#define portINITIAL_CCR ( ( StackType_t ) 0x00 )
+
+/* Hardware specific constants used to generate the RTOS tick from the TPU. */
+#define portCLEAR_ON_TGRA_COMPARE_MATCH ( ( uint8_t ) 0x20 )
+#define portCLOCK_DIV_64 ( ( uint8_t ) 0x03 )
+#define portCLOCK_DIV ( ( uint32_t ) 64 )
+#define portTGRA_INTERRUPT_ENABLE ( ( uint8_t ) 0x01 )
+#define portTIMER_CHANNEL ( ( uint8_t ) 0x02 )
+#define portMSTP13 ( ( uint16_t ) 0x2000 )
+
+/*
+ * Setup TPU channel one for the RTOS tick at the requested frequency.
+ */
+static void prvSetupTimerInterrupt( void );
+
+/*
+ * The ISR used by portYIELD(). This is installed as a trap handler.
+ */
+void vPortYield( void ) __attribute__ ( ( saveall, interrupt_handler ) );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+uint32_t ulValue;
+
+ /* This requires an even address. */
+ ulValue = ( uint32_t ) pxTopOfStack;
+ if( ulValue & 1UL )
+ {
+ pxTopOfStack = pxTopOfStack - 1;
+ }
+
+ /* Place a few bytes of known values on the bottom of the stack.
+ This is just useful for debugging. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0xaa;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xbb;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xcc;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xdd;
+
+ /* The initial stack mimics an interrupt stack. First there is the program
+ counter (24 bits). */
+ ulValue = ( uint32_t ) pxCode;
+
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
+ pxTopOfStack--;
+ ulValue >>= 8UL;
+ *pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
+ pxTopOfStack--;
+ ulValue >>= 8UL;
+ *pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
+
+ /* Followed by the CCR. */
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_CCR;
+
+ /* Next all the general purpose registers - with the parameters being passed
+ in ER0. The parameter order must match that used by the compiler when the
+ "saveall" function attribute is used. */
+
+ /* ER6 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x66;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x66;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x66;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x66;
+
+ /* ER0 */
+ ulValue = ( uint32_t ) pvParameters;
+
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
+ pxTopOfStack--;
+ ulValue >>= 8UL;
+ *pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
+ pxTopOfStack--;
+ ulValue >>= 8UL;
+ *pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
+ pxTopOfStack--;
+ ulValue >>= 8UL;
+ *pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
+
+ /* ER1 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x11;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x11;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x11;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x11;
+
+ /* ER2 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x22;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x22;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x22;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x22;
+
+ /* ER3 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x33;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x33;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x33;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x33;
+
+ /* ER4 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x44;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x44;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x44;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x44;
+
+ /* ER5 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x55;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x55;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x55;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x55;
+
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void * pxCurrentTCB;
+
+ /* Setup the hardware to generate the tick. */
+ prvSetupTimerInterrupt();
+
+ /* Restore the context of the first task that is going to run. This
+ mirrors the function epilogue code generated by the compiler when the
+ "saveall" function attribute is used. */
+ asm volatile (
+ "MOV.L @_pxCurrentTCB, ER6 \n\t"
+ "MOV.L @ER6, ER7 \n\t"
+ "LDM.L @SP+, (ER4-ER5) \n\t"
+ "LDM.L @SP+, (ER0-ER3) \n\t"
+ "MOV.L @ER7+, ER6 \n\t"
+ "RTE \n\t"
+ );
+
+ ( void ) pxCurrentTCB;
+
+ /* Should not get here. */
+ return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+ /* It is unlikely that the h8 port will get stopped. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch. This is a trap handler. The "saveall" function
+ * attribute is used so the context is saved by the compiler prologue. All
+ * we have to do is save the stack pointer.
+ */
+void vPortYield( void )
+{
+ portSAVE_STACK_POINTER();
+ vTaskSwitchContext();
+ portRESTORE_STACK_POINTER();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * The interrupt handler installed for the RTOS tick depends on whether the
+ * preemptive or cooperative scheduler is being used.
+ */
+#if( configUSE_PREEMPTION == 1 )
+
+ /*
+ * The preemptive scheduler is used so the ISR calls vTaskSwitchContext().
+ * The function prologue saves the context so all we have to do is save
+ * the stack pointer.
+ */
+ void vTickISR( void ) __attribute__ ( ( saveall, interrupt_handler ) );
+ void vTickISR( void )
+ {
+ portSAVE_STACK_POINTER();
+
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ vTaskSwitchContext();
+ }
+
+ /* Clear the interrupt. */
+ TSR1 &= ~0x01;
+
+ portRESTORE_STACK_POINTER();
+ }
+
+#else
+
+ /*
+ * The cooperative scheduler is being used so all we have to do is
+ * periodically increment the tick. This can just be a normal ISR and
+ * the "saveall" attribute is not required.
+ */
+ void vTickISR( void ) __attribute__ ( ( interrupt_handler ) );
+ void vTickISR( void )
+ {
+ xTaskIncrementTick();
+
+ /* Clear the interrupt. */
+ TSR1 &= ~0x01;
+ }
+
+#endif
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup timer 1 compare match to generate a tick interrupt.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+const uint32_t ulCompareMatch = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) / portCLOCK_DIV;
+
+ /* Turn the module on. */
+ MSTPCR &= ~portMSTP13;
+
+ /* Configure timer 1. */
+ TCR1 = portCLEAR_ON_TGRA_COMPARE_MATCH | portCLOCK_DIV_64;
+
+ /* Configure the compare match value for a tick of configTICK_RATE_HZ. */
+ TGR1A = ulCompareMatch;
+
+ /* Start the timer and enable the interrupt - we can do this here as
+ interrupts are globally disabled when this function is called. */
+ TIER1 |= portTGRA_INTERRUPT_ENABLE;
+ TSTR |= portTIMER_CHANNEL;
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/H8S2329/portmacro.h b/portable/GCC/H8S2329/portmacro.h
index 9a89051..f568853 100644
--- a/portable/GCC/H8S2329/portmacro.h
+++ b/portable/GCC/H8S2329/portmacro.h
@@ -1,139 +1,138 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT short
-#define portSTACK_TYPE uint8_t
-#define portBASE_TYPE char
-
-typedef portSTACK_TYPE StackType_t;
-typedef signed char BaseType_t;
-typedef unsigned char UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
-#else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portBYTE_ALIGNMENT 2
-#define portSTACK_GROWTH ( -1 )
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portYIELD() asm volatile( "TRAPA #0" )
-#define portNOP() asm volatile( "NOP" )
-/*-----------------------------------------------------------*/
-
-/* Critical section handling. */
-#define portENABLE_INTERRUPTS() asm volatile( "ANDC #0x7F, CCR" );
-#define portDISABLE_INTERRUPTS() asm volatile( "ORC #0x80, CCR" );
-
-/* Push the CCR then disable interrupts. */
-#define portENTER_CRITICAL() asm volatile( "STC CCR, @-ER7" ); \
- portDISABLE_INTERRUPTS();
-
-/* Pop the CCR to set the interrupt masking back to its previous state. */
-#define portEXIT_CRITICAL() asm volatile( "LDC @ER7+, CCR" );
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-
-/* Context switch macros. These macros are very simple as the context
-is saved simply by selecting the saveall attribute of the context switch
-interrupt service routines. These macros save and restore the stack
-pointer to the TCB. */
-
-#define portSAVE_STACK_POINTER() \
-extern void* pxCurrentTCB; \
- \
- asm volatile( \
- "MOV.L @_pxCurrentTCB, ER5 \n\t" \
- "MOV.L ER7, @ER5 \n\t" \
- ); \
- ( void ) pxCurrentTCB;
-
-
-#define portRESTORE_STACK_POINTER() \
-extern void* pxCurrentTCB; \
- \
- asm volatile( \
- "MOV.L @_pxCurrentTCB, ER5 \n\t" \
- "MOV.L @ER5, ER7 \n\t" \
- ); \
- ( void ) pxCurrentTCB;
-
-/*-----------------------------------------------------------*/
-
-/* Macros to allow a context switch from within an application ISR. */
-
-#define portENTER_SWITCHING_ISR() portSAVE_STACK_POINTER(); {
-
-#define portEXIT_SWITCHING_ISR( x ) \
- if( x ) \
- { \
- extern void vTaskSwitchContext( void ); \
- vTaskSwitchContext(); \
- } \
- } portRESTORE_STACK_POINTER();
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint8_t
+#define portBASE_TYPE char
+
+typedef portSTACK_TYPE StackType_t;
+typedef signed char BaseType_t;
+typedef unsigned char UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT 2
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portYIELD() asm volatile( "TRAPA #0" )
+#define portNOP() asm volatile( "NOP" )
+/*-----------------------------------------------------------*/
+
+/* Critical section handling. */
+#define portENABLE_INTERRUPTS() asm volatile( "ANDC #0x7F, CCR" );
+#define portDISABLE_INTERRUPTS() asm volatile( "ORC #0x80, CCR" );
+
+/* Push the CCR then disable interrupts. */
+#define portENTER_CRITICAL() asm volatile( "STC CCR, @-ER7" ); \
+ portDISABLE_INTERRUPTS();
+
+/* Pop the CCR to set the interrupt masking back to its previous state. */
+#define portEXIT_CRITICAL() asm volatile( "LDC @ER7+, CCR" );
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+/* Context switch macros. These macros are very simple as the context
+is saved simply by selecting the saveall attribute of the context switch
+interrupt service routines. These macros save and restore the stack
+pointer to the TCB. */
+
+#define portSAVE_STACK_POINTER() \
+extern void* pxCurrentTCB; \
+ \
+ asm volatile( \
+ "MOV.L @_pxCurrentTCB, ER5 \n\t" \
+ "MOV.L ER7, @ER5 \n\t" \
+ ); \
+ ( void ) pxCurrentTCB;
+
+
+#define portRESTORE_STACK_POINTER() \
+extern void* pxCurrentTCB; \
+ \
+ asm volatile( \
+ "MOV.L @_pxCurrentTCB, ER5 \n\t" \
+ "MOV.L @ER5, ER7 \n\t" \
+ ); \
+ ( void ) pxCurrentTCB;
+
+/*-----------------------------------------------------------*/
+
+/* Macros to allow a context switch from within an application ISR. */
+
+#define portENTER_SWITCHING_ISR() portSAVE_STACK_POINTER(); {
+
+#define portEXIT_SWITCHING_ISR( x ) \
+ if( x ) \
+ { \
+ extern void vTaskSwitchContext( void ); \
+ vTaskSwitchContext(); \
+ } \
+ } portRESTORE_STACK_POINTER();
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/portable/GCC/HCS12/port.c b/portable/GCC/HCS12/port.c
index b82c6ce..8ee3e10 100644
--- a/portable/GCC/HCS12/port.c
+++ b/portable/GCC/HCS12/port.c
@@ -1,238 +1,237 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/* GCC/HCS12 port by Jefferson L Smith, 2005 */
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Port includes */
-#include <sys/ports_def.h>
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the HCS12 port.
- *----------------------------------------------------------*/
-
-
-/*
- * Configure a timer to generate the RTOS tick at the frequency specified
- * within FreeRTOSConfig.h.
- */
-static void prvSetupTimerInterrupt( void );
-
-/* NOTE: Interrupt service routines must be in non-banked memory - as does the
-scheduler startup function. */
-#define ATTR_NEAR __attribute__((near))
-
-/* Manual context switch function. This is the SWI ISR. */
-// __attribute__((interrupt))
-void ATTR_NEAR vPortYield( void );
-
-/* Tick context switch function. This is the timer ISR. */
-// __attribute__((interrupt))
-void ATTR_NEAR vPortTickInterrupt( void );
-
-/* Function in non-banked memory which actually switches to first task. */
-BaseType_t ATTR_NEAR xStartSchedulerNear( void );
-
-/* Calls to portENTER_CRITICAL() can be nested. When they are nested the
-critical section should not be left (i.e. interrupts should not be re-enabled)
-until the nesting depth reaches 0. This variable simply tracks the nesting
-depth. Each task maintains it's own critical nesting depth variable so
-uxCriticalNesting is saved and restored from the task stack during a context
-switch. */
-volatile UBaseType_t uxCriticalNesting = 0x80; // un-initialized
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-
-
- /* Setup the initial stack of the task. The stack is set exactly as
- expected by the portRESTORE_CONTEXT() macro. In this case the stack as
- expected by the HCS12 RTI instruction. */
-
-
- /* The address of the task function is placed in the stack byte at a time. */
- *pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pxCode) ) + 1 );
- *--pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pxCode) ) + 0 );
-
- /* Next are all the registers that form part of the task context. */
-
- /* Y register */
- *--pxTopOfStack = ( StackType_t ) 0xff;
- *--pxTopOfStack = ( StackType_t ) 0xee;
-
- /* X register */
- *--pxTopOfStack = ( StackType_t ) 0xdd;
- *--pxTopOfStack = ( StackType_t ) 0xcc;
-
- /* A register contains parameter high byte. */
- *--pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pvParameters) ) + 0 );
-
- /* B register contains parameter low byte. */
- *--pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pvParameters) ) + 1 );
-
- /* CCR: Note that when the task starts interrupts will be enabled since
- "I" bit of CCR is cleared */
- *--pxTopOfStack = ( StackType_t ) 0x80; // keeps Stop disabled (MCU default)
-
- /* tmp softregs used by GCC. Values right now don't matter. */
- __asm("\n\
- movw _.frame, 2,-%0 \n\
- movw _.tmp, 2,-%0 \n\
- movw _.z, 2,-%0 \n\
- movw _.xy, 2,-%0 \n\
- ;movw _.d2, 2,-%0 \n\
- ;movw _.d1, 2,-%0 \n\
- ": "=A"(pxTopOfStack) : "0"(pxTopOfStack) );
-
- #ifdef BANKED_MODEL
- /* The page of the task. */
- *--pxTopOfStack = 0x30; // can only directly start in PPAGE 0x30
- #endif
-
- /* The critical nesting depth is initialised with 0 (meaning not in
- a critical section). */
- *--pxTopOfStack = ( StackType_t ) 0x00;
-
-
- return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
- /* It is unlikely that the HCS12 port will get stopped. */
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupTimerInterrupt( void )
-{
- /* Enable hardware RTI timer */
- /* Ignores configTICK_RATE_HZ */
- RTICTL = 0x50; // 16 MHz xtal: 976.56 Hz, 1024mS
- CRGINT |= 0x80; // RTIE
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
- /* xPortStartScheduler() does not start the scheduler directly because
- the header file containing the xPortStartScheduler() prototype is part
- of the common kernel code, and therefore cannot use the CODE_SEG pragma.
- Instead it simply calls the locally defined xNearStartScheduler() -
- which does use the CODE_SEG pragma. */
-
- int16_t register d;
- __asm ("jmp xStartSchedulerNear ; will never return": "=d"(d));
- return d;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xStartSchedulerNear( void )
-{
- /* Configure the timer that will generate the RTOS tick. Interrupts are
- disabled when this function is called. */
- prvSetupTimerInterrupt();
-
- /* Restore the context of the first task. */
- portRESTORE_CONTEXT();
-
- portISR_TAIL();
-
- /* Should not get here! */
- return pdFALSE;
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Context switch functions. These are interrupt service routines.
- */
-
-/*
- * Manual context switch forced by calling portYIELD(). This is the SWI
- * handler.
- */
-void vPortYield( void )
-{
- portISR_HEAD();
- /* NOTE: This is the trap routine (swi) although not defined as a trap.
- It will fill the stack the same way as an ISR in order to mix preemtion
- and cooperative yield. */
-
- portSAVE_CONTEXT();
- vTaskSwitchContext();
- portRESTORE_CONTEXT();
-
- portISR_TAIL();
-}
-/*-----------------------------------------------------------*/
-
-/*
- * RTOS tick interrupt service routine. If the cooperative scheduler is
- * being used then this simply increments the tick count. If the
- * preemptive scheduler is being used a context switch can occur.
- */
-void vPortTickInterrupt( void )
-{
- portISR_HEAD();
-
- /* Clear tick timer flag */
- CRGFLG = 0x80;
-
- #if configUSE_PREEMPTION == 1
- {
- /* A context switch might happen so save the context. */
- portSAVE_CONTEXT();
-
- /* Increment the tick ... */
- if( xTaskIncrementTick() != pdFALSE )
- {
- /* A context switch is necessary. */
- vTaskSwitchContext();
- }
-
- /* Restore the context of a task - which may be a different task
- to that interrupted. */
- portRESTORE_CONTEXT();
- }
- #else
- {
- xTaskIncrementTick();
- }
- #endif
-
- portISR_TAIL();
-}
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* GCC/HCS12 port by Jefferson L Smith, 2005 */
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Port includes */
+#include <sys/ports_def.h>
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the HCS12 port.
+ *----------------------------------------------------------*/
+
+
+/*
+ * Configure a timer to generate the RTOS tick at the frequency specified
+ * within FreeRTOSConfig.h.
+ */
+static void prvSetupTimerInterrupt( void );
+
+/* NOTE: Interrupt service routines must be in non-banked memory - as does the
+scheduler startup function. */
+#define ATTR_NEAR __attribute__((near))
+
+/* Manual context switch function. This is the SWI ISR. */
+// __attribute__((interrupt))
+void ATTR_NEAR vPortYield( void );
+
+/* Tick context switch function. This is the timer ISR. */
+// __attribute__((interrupt))
+void ATTR_NEAR vPortTickInterrupt( void );
+
+/* Function in non-banked memory which actually switches to first task. */
+BaseType_t ATTR_NEAR xStartSchedulerNear( void );
+
+/* Calls to portENTER_CRITICAL() can be nested. When they are nested the
+critical section should not be left (i.e. interrupts should not be re-enabled)
+until the nesting depth reaches 0. This variable simply tracks the nesting
+depth. Each task maintains it's own critical nesting depth variable so
+uxCriticalNesting is saved and restored from the task stack during a context
+switch. */
+volatile UBaseType_t uxCriticalNesting = 0x80; // un-initialized
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+
+
+ /* Setup the initial stack of the task. The stack is set exactly as
+ expected by the portRESTORE_CONTEXT() macro. In this case the stack as
+ expected by the HCS12 RTI instruction. */
+
+
+ /* The address of the task function is placed in the stack byte at a time. */
+ *pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pxCode) ) + 1 );
+ *--pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pxCode) ) + 0 );
+
+ /* Next are all the registers that form part of the task context. */
+
+ /* Y register */
+ *--pxTopOfStack = ( StackType_t ) 0xff;
+ *--pxTopOfStack = ( StackType_t ) 0xee;
+
+ /* X register */
+ *--pxTopOfStack = ( StackType_t ) 0xdd;
+ *--pxTopOfStack = ( StackType_t ) 0xcc;
+
+ /* A register contains parameter high byte. */
+ *--pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pvParameters) ) + 0 );
+
+ /* B register contains parameter low byte. */
+ *--pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pvParameters) ) + 1 );
+
+ /* CCR: Note that when the task starts interrupts will be enabled since
+ "I" bit of CCR is cleared */
+ *--pxTopOfStack = ( StackType_t ) 0x80; // keeps Stop disabled (MCU default)
+
+ /* tmp softregs used by GCC. Values right now don't matter. */
+ __asm("\n\
+ movw _.frame, 2,-%0 \n\
+ movw _.tmp, 2,-%0 \n\
+ movw _.z, 2,-%0 \n\
+ movw _.xy, 2,-%0 \n\
+ ;movw _.d2, 2,-%0 \n\
+ ;movw _.d1, 2,-%0 \n\
+ ": "=A"(pxTopOfStack) : "0"(pxTopOfStack) );
+
+ #ifdef BANKED_MODEL
+ /* The page of the task. */
+ *--pxTopOfStack = 0x30; // can only directly start in PPAGE 0x30
+ #endif
+
+ /* The critical nesting depth is initialised with 0 (meaning not in
+ a critical section). */
+ *--pxTopOfStack = ( StackType_t ) 0x00;
+
+
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+ /* It is unlikely that the HCS12 port will get stopped. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+ /* Enable hardware RTI timer */
+ /* Ignores configTICK_RATE_HZ */
+ RTICTL = 0x50; // 16 MHz xtal: 976.56 Hz, 1024mS
+ CRGINT |= 0x80; // RTIE
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+ /* xPortStartScheduler() does not start the scheduler directly because
+ the header file containing the xPortStartScheduler() prototype is part
+ of the common kernel code, and therefore cannot use the CODE_SEG pragma.
+ Instead it simply calls the locally defined xNearStartScheduler() -
+ which does use the CODE_SEG pragma. */
+
+ int16_t register d;
+ __asm ("jmp xStartSchedulerNear ; will never return": "=d"(d));
+ return d;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStartSchedulerNear( void )
+{
+ /* Configure the timer that will generate the RTOS tick. Interrupts are
+ disabled when this function is called. */
+ prvSetupTimerInterrupt();
+
+ /* Restore the context of the first task. */
+ portRESTORE_CONTEXT();
+
+ portISR_TAIL();
+
+ /* Should not get here! */
+ return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Context switch functions. These are interrupt service routines.
+ */
+
+/*
+ * Manual context switch forced by calling portYIELD(). This is the SWI
+ * handler.
+ */
+void vPortYield( void )
+{
+ portISR_HEAD();
+ /* NOTE: This is the trap routine (swi) although not defined as a trap.
+ It will fill the stack the same way as an ISR in order to mix preemtion
+ and cooperative yield. */
+
+ portSAVE_CONTEXT();
+ vTaskSwitchContext();
+ portRESTORE_CONTEXT();
+
+ portISR_TAIL();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * RTOS tick interrupt service routine. If the cooperative scheduler is
+ * being used then this simply increments the tick count. If the
+ * preemptive scheduler is being used a context switch can occur.
+ */
+void vPortTickInterrupt( void )
+{
+ portISR_HEAD();
+
+ /* Clear tick timer flag */
+ CRGFLG = 0x80;
+
+ #if configUSE_PREEMPTION == 1
+ {
+ /* A context switch might happen so save the context. */
+ portSAVE_CONTEXT();
+
+ /* Increment the tick ... */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ /* A context switch is necessary. */
+ vTaskSwitchContext();
+ }
+
+ /* Restore the context of a task - which may be a different task
+ to that interrupted. */
+ portRESTORE_CONTEXT();
+ }
+ #else
+ {
+ xTaskIncrementTick();
+ }
+ #endif
+
+ portISR_TAIL();
+}
diff --git a/portable/GCC/HCS12/portmacro.h b/portable/GCC/HCS12/portmacro.h
index 3005db3..1a458f9 100644
--- a/portable/GCC/HCS12/portmacro.h
+++ b/portable/GCC/HCS12/portmacro.h
@@ -1,247 +1,246 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT short
-#define portSTACK_TYPE uint8_t
-#define portBASE_TYPE char
-
-typedef portSTACK_TYPE StackType_t;
-typedef signed char BaseType_t;
-typedef unsigned char UBaseType_t;
-
-
-#if( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
-#else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portBYTE_ALIGNMENT 1
-#define portSTACK_GROWTH ( -1 )
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portYIELD() __asm( "swi" );
-/*-----------------------------------------------------------*/
-
-/* Critical section handling. */
-#define portENABLE_INTERRUPTS() __asm( "cli" )
-#define portDISABLE_INTERRUPTS() __asm( "sei" )
-
-/*
- * Disable interrupts before incrementing the count of critical section nesting.
- * The nesting count is maintained so we know when interrupts should be
- * re-enabled. Once interrupts are disabled the nesting count can be accessed
- * directly. Each task maintains its own nesting count.
- */
-#define portENTER_CRITICAL() \
-{ \
- extern volatile UBaseType_t uxCriticalNesting; \
- \
- portDISABLE_INTERRUPTS(); \
- uxCriticalNesting++; \
-}
-
-/*
- * Interrupts are disabled so we can access the nesting count directly. If the
- * nesting is found to be 0 (no nesting) then we are leaving the critical
- * section and interrupts can be re-enabled.
- */
-#define portEXIT_CRITICAL() \
-{ \
- extern volatile UBaseType_t uxCriticalNesting; \
- \
- uxCriticalNesting--; \
- if( uxCriticalNesting == 0 ) \
- { \
- portENABLE_INTERRUPTS(); \
- } \
-}
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-
-/*
- * These macros are very simple as the processor automatically saves and
- * restores its registers as interrupts are entered and exited. In
- * addition to the (automatically stacked) registers we also stack the
- * critical nesting count. Each task maintains its own critical nesting
- * count as it is legitimate for a task to yield from within a critical
- * section. If the banked memory model is being used then the PPAGE
- * register is also stored as part of the tasks context.
- */
-
-#ifdef BANKED_MODEL
- /*
- * Load the stack pointer for the task, then pull the critical nesting
- * count and PPAGE register from the stack. The remains of the
- * context are restored by the RTI instruction.
- */
- #define portRESTORE_CONTEXT() \
- { \
- __asm( " \n\
- .globl pxCurrentTCB ; void * \n\
- .globl uxCriticalNesting ; char \n\
- \n\
- ldx pxCurrentTCB \n\
- lds 0,x ; Stack \n\
- \n\
- movb 1,sp+,uxCriticalNesting \n\
- movb 1,sp+,0x30 ; PPAGE \n\
- " ); \
- }
-
- /*
- * By the time this macro is called the processor has already stacked the
- * registers. Simply stack the nesting count and PPAGE value, then save
- * the task stack pointer.
- */
- #define portSAVE_CONTEXT() \
- { \
- __asm( " \n\
- .globl pxCurrentTCB ; void * \n\
- .globl uxCriticalNesting ; char \n\
- \n\
- movb 0x30, 1,-sp ; PPAGE \n\
- movb uxCriticalNesting, 1,-sp \n\
- \n\
- ldx pxCurrentTCB \n\
- sts 0,x ; Stack \n\
- " ); \
- }
-#else
-
- /*
- * These macros are as per the BANKED versions above, but without saving
- * and restoring the PPAGE register.
- */
-
- #define portRESTORE_CONTEXT() \
- { \
- __asm( " \n\
- .globl pxCurrentTCB ; void * \n\
- .globl uxCriticalNesting ; char \n\
- \n\
- ldx pxCurrentTCB \n\
- lds 0,x ; Stack \n\
- \n\
- movb 1,sp+,uxCriticalNesting \n\
- " ); \
- }
-
- #define portSAVE_CONTEXT() \
- { \
- __asm( " \n\
- .globl pxCurrentTCB ; void * \n\
- .globl uxCriticalNesting ; char \n\
- \n\
- movb uxCriticalNesting, 1,-sp \n\
- \n\
- ldx pxCurrentTCB \n\
- sts 0,x ; Stack \n\
- " ); \
- }
-#endif
-
-/*
- * Utility macros to save/restore correct software registers for GCC. This is
- * useful when GCC does not generate appropriate ISR head/tail code.
- */
-#define portISR_HEAD() \
-{ \
- __asm(" \n\
- movw _.frame, 2,-sp \n\
- movw _.tmp, 2,-sp \n\
- movw _.z, 2,-sp \n\
- movw _.xy, 2,-sp \n\
- ;movw _.d2, 2,-sp \n\
- ;movw _.d1, 2,-sp \n\
- "); \
-}
-
-#define portISR_TAIL() \
-{ \
- __asm(" \n\
- movw 2,sp+, _.xy \n\
- movw 2,sp+, _.z \n\
- movw 2,sp+, _.tmp \n\
- movw 2,sp+, _.frame \n\
- ;movw 2,sp+, _.d1 \n\
- ;movw 2,sp+, _.d2 \n\
- rti \n\
- "); \
-}
-
-/*
- * Utility macro to call macros above in correct order in order to perform a
- * task switch from within a standard ISR. This macro can only be used if
- * the ISR does not use any local (stack) variables. If the ISR uses stack
- * variables portYIELD() should be used in it's place.
- */
-
-#define portTASK_SWITCH_FROM_ISR() \
- portSAVE_CONTEXT(); \
- vTaskSwitchContext(); \
- portRESTORE_CONTEXT();
-
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint8_t
+#define portBASE_TYPE char
+
+typedef portSTACK_TYPE StackType_t;
+typedef signed char BaseType_t;
+typedef unsigned char UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT 1
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portYIELD() __asm( "swi" );
+/*-----------------------------------------------------------*/
+
+/* Critical section handling. */
+#define portENABLE_INTERRUPTS() __asm( "cli" )
+#define portDISABLE_INTERRUPTS() __asm( "sei" )
+
+/*
+ * Disable interrupts before incrementing the count of critical section nesting.
+ * The nesting count is maintained so we know when interrupts should be
+ * re-enabled. Once interrupts are disabled the nesting count can be accessed
+ * directly. Each task maintains its own nesting count.
+ */
+#define portENTER_CRITICAL() \
+{ \
+ extern volatile UBaseType_t uxCriticalNesting; \
+ \
+ portDISABLE_INTERRUPTS(); \
+ uxCriticalNesting++; \
+}
+
+/*
+ * Interrupts are disabled so we can access the nesting count directly. If the
+ * nesting is found to be 0 (no nesting) then we are leaving the critical
+ * section and interrupts can be re-enabled.
+ */
+#define portEXIT_CRITICAL() \
+{ \
+ extern volatile UBaseType_t uxCriticalNesting; \
+ \
+ uxCriticalNesting--; \
+ if( uxCriticalNesting == 0 ) \
+ { \
+ portENABLE_INTERRUPTS(); \
+ } \
+}
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+/*
+ * These macros are very simple as the processor automatically saves and
+ * restores its registers as interrupts are entered and exited. In
+ * addition to the (automatically stacked) registers we also stack the
+ * critical nesting count. Each task maintains its own critical nesting
+ * count as it is legitimate for a task to yield from within a critical
+ * section. If the banked memory model is being used then the PPAGE
+ * register is also stored as part of the tasks context.
+ */
+
+#ifdef BANKED_MODEL
+ /*
+ * Load the stack pointer for the task, then pull the critical nesting
+ * count and PPAGE register from the stack. The remains of the
+ * context are restored by the RTI instruction.
+ */
+ #define portRESTORE_CONTEXT() \
+ { \
+ __asm( " \n\
+ .globl pxCurrentTCB ; void * \n\
+ .globl uxCriticalNesting ; char \n\
+ \n\
+ ldx pxCurrentTCB \n\
+ lds 0,x ; Stack \n\
+ \n\
+ movb 1,sp+,uxCriticalNesting \n\
+ movb 1,sp+,0x30 ; PPAGE \n\
+ " ); \
+ }
+
+ /*
+ * By the time this macro is called the processor has already stacked the
+ * registers. Simply stack the nesting count and PPAGE value, then save
+ * the task stack pointer.
+ */
+ #define portSAVE_CONTEXT() \
+ { \
+ __asm( " \n\
+ .globl pxCurrentTCB ; void * \n\
+ .globl uxCriticalNesting ; char \n\
+ \n\
+ movb 0x30, 1,-sp ; PPAGE \n\
+ movb uxCriticalNesting, 1,-sp \n\
+ \n\
+ ldx pxCurrentTCB \n\
+ sts 0,x ; Stack \n\
+ " ); \
+ }
+#else
+
+ /*
+ * These macros are as per the BANKED versions above, but without saving
+ * and restoring the PPAGE register.
+ */
+
+ #define portRESTORE_CONTEXT() \
+ { \
+ __asm( " \n\
+ .globl pxCurrentTCB ; void * \n\
+ .globl uxCriticalNesting ; char \n\
+ \n\
+ ldx pxCurrentTCB \n\
+ lds 0,x ; Stack \n\
+ \n\
+ movb 1,sp+,uxCriticalNesting \n\
+ " ); \
+ }
+
+ #define portSAVE_CONTEXT() \
+ { \
+ __asm( " \n\
+ .globl pxCurrentTCB ; void * \n\
+ .globl uxCriticalNesting ; char \n\
+ \n\
+ movb uxCriticalNesting, 1,-sp \n\
+ \n\
+ ldx pxCurrentTCB \n\
+ sts 0,x ; Stack \n\
+ " ); \
+ }
+#endif
+
+/*
+ * Utility macros to save/restore correct software registers for GCC. This is
+ * useful when GCC does not generate appropriate ISR head/tail code.
+ */
+#define portISR_HEAD() \
+{ \
+ __asm(" \n\
+ movw _.frame, 2,-sp \n\
+ movw _.tmp, 2,-sp \n\
+ movw _.z, 2,-sp \n\
+ movw _.xy, 2,-sp \n\
+ ;movw _.d2, 2,-sp \n\
+ ;movw _.d1, 2,-sp \n\
+ "); \
+}
+
+#define portISR_TAIL() \
+{ \
+ __asm(" \n\
+ movw 2,sp+, _.xy \n\
+ movw 2,sp+, _.z \n\
+ movw 2,sp+, _.tmp \n\
+ movw 2,sp+, _.frame \n\
+ ;movw 2,sp+, _.d1 \n\
+ ;movw 2,sp+, _.d2 \n\
+ rti \n\
+ "); \
+}
+
+/*
+ * Utility macro to call macros above in correct order in order to perform a
+ * task switch from within a standard ISR. This macro can only be used if
+ * the ISR does not use any local (stack) variables. If the ISR uses stack
+ * variables portYIELD() should be used in it's place.
+ */
+
+#define portTASK_SWITCH_FROM_ISR() \
+ portSAVE_CONTEXT(); \
+ vTaskSwitchContext(); \
+ portRESTORE_CONTEXT();
+
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/portable/GCC/IA32_flat/ISR_Support.h b/portable/GCC/IA32_flat/ISR_Support.h
index 2ab7d15..6ee4f24 100644
--- a/portable/GCC/IA32_flat/ISR_Support.h
+++ b/portable/GCC/IA32_flat/ISR_Support.h
@@ -1,128 +1,128 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
- .extern ulTopOfSystemStack
- .extern ulInterruptNesting
-
-/*-----------------------------------------------------------*/
-
-.macro portFREERTOS_INTERRUPT_ENTRY
-
- /* Save general purpose registers. */
- pusha
-
- /* If ulInterruptNesting is zero the rest of the task context will need
- saving and a stack switch might be required. */
- movl ulInterruptNesting, %eax
- test %eax, %eax
- jne 2f
-
- /* Interrupts are not nested, so save the rest of the task context. */
- .if configSUPPORT_FPU == 1
-
- /* If the task has a buffer allocated to save the FPU context then
- save the FPU context now. */
- movl pucPortTaskFPUContextBuffer, %eax
- test %eax, %eax
- je 1f
- fnsave ( %eax ) /* Save FLOP context into ucTempFPUBuffer array. */
- fwait
-
- 1:
- /* Save the address of the FPU context, if any. */
- push pucPortTaskFPUContextBuffer
-
- .endif /* configSUPPORT_FPU */
-
- /* Find the TCB. */
- movl pxCurrentTCB, %eax
-
- /* Stack location is first item in the TCB. */
- movl %esp, (%eax)
-
- /* Switch stacks. */
- movl ulTopOfSystemStack, %esp
- movl %esp, %ebp
-
- 2:
- /* Increment nesting count. */
- add $1, ulInterruptNesting
-
-.endm
-/*-----------------------------------------------------------*/
-
-.macro portINTERRUPT_EPILOGUE
-
- cli
- sub $1, ulInterruptNesting
-
- /* If the nesting has unwound to zero. */
- movl ulInterruptNesting, %eax
- test %eax, %eax
- jne 2f
-
- /* If a yield was requested then select a new TCB now. */
- movl ulPortYieldPending, %eax
- test %eax, %eax
- je 1f
- movl $0, ulPortYieldPending
- call vTaskSwitchContext
-
- 1:
- /* Stack location is first item in the TCB. */
- movl pxCurrentTCB, %eax
- movl (%eax), %esp
-
- .if configSUPPORT_FPU == 1
-
- /* Restore address of task's FPU context buffer. */
- pop pucPortTaskFPUContextBuffer
-
- /* If the task has a buffer allocated in which its FPU context is saved,
- then restore it now. */
- movl pucPortTaskFPUContextBuffer, %eax
- test %eax, %eax
- je 1f
- frstor ( %eax )
- 1:
- .endif
-
- 2:
- popa
-
-.endm
-/*-----------------------------------------------------------*/
-
-.macro portFREERTOS_INTERRUPT_EXIT
-
- portINTERRUPT_EPILOGUE
- /* EOI. */
- movl $0x00, (0xFEE000B0)
- iret
-
-.endm
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+ .extern ulTopOfSystemStack
+ .extern ulInterruptNesting
+
+/*-----------------------------------------------------------*/
+
+.macro portFREERTOS_INTERRUPT_ENTRY
+
+ /* Save general purpose registers. */
+ pusha
+
+ /* If ulInterruptNesting is zero the rest of the task context will need
+ saving and a stack switch might be required. */
+ movl ulInterruptNesting, %eax
+ test %eax, %eax
+ jne 2f
+
+ /* Interrupts are not nested, so save the rest of the task context. */
+ .if configSUPPORT_FPU == 1
+
+ /* If the task has a buffer allocated to save the FPU context then
+ save the FPU context now. */
+ movl pucPortTaskFPUContextBuffer, %eax
+ test %eax, %eax
+ je 1f
+ fnsave ( %eax ) /* Save FLOP context into ucTempFPUBuffer array. */
+ fwait
+
+ 1:
+ /* Save the address of the FPU context, if any. */
+ push pucPortTaskFPUContextBuffer
+
+ .endif /* configSUPPORT_FPU */
+
+ /* Find the TCB. */
+ movl pxCurrentTCB, %eax
+
+ /* Stack location is first item in the TCB. */
+ movl %esp, (%eax)
+
+ /* Switch stacks. */
+ movl ulTopOfSystemStack, %esp
+ movl %esp, %ebp
+
+ 2:
+ /* Increment nesting count. */
+ add $1, ulInterruptNesting
+
+.endm
+/*-----------------------------------------------------------*/
+
+.macro portINTERRUPT_EPILOGUE
+
+ cli
+ sub $1, ulInterruptNesting
+
+ /* If the nesting has unwound to zero. */
+ movl ulInterruptNesting, %eax
+ test %eax, %eax
+ jne 2f
+
+ /* If a yield was requested then select a new TCB now. */
+ movl ulPortYieldPending, %eax
+ test %eax, %eax
+ je 1f
+ movl $0, ulPortYieldPending
+ call vTaskSwitchContext
+
+ 1:
+ /* Stack location is first item in the TCB. */
+ movl pxCurrentTCB, %eax
+ movl (%eax), %esp
+
+ .if configSUPPORT_FPU == 1
+
+ /* Restore address of task's FPU context buffer. */
+ pop pucPortTaskFPUContextBuffer
+
+ /* If the task has a buffer allocated in which its FPU context is saved,
+ then restore it now. */
+ movl pucPortTaskFPUContextBuffer, %eax
+ test %eax, %eax
+ je 1f
+ frstor ( %eax )
+ 1:
+ .endif
+
+ 2:
+ popa
+
+.endm
+/*-----------------------------------------------------------*/
+
+.macro portFREERTOS_INTERRUPT_EXIT
+
+ portINTERRUPT_EPILOGUE
+ /* EOI. */
+ movl $0x00, (0xFEE000B0)
+ iret
+
+.endm
diff --git a/portable/GCC/IA32_flat/port.c b/portable/GCC/IA32_flat/port.c
index 440e40f..52cac31 100644
--- a/portable/GCC/IA32_flat/port.c
+++ b/portable/GCC/IA32_flat/port.c
@@ -1,687 +1,673 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/* Standard includes. */
-#include <limits.h>
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
- /* Check the configuration. */
- #if( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-#if( configISR_STACK_SIZE < ( configMINIMAL_STACK_SIZE * 2 ) )
- #warning configISR_STACK_SIZE is probably too small!
-#endif /* ( configISR_STACK_SIZE < configMINIMAL_STACK_SIZE * 2 ) */
-
-#if( ( configMAX_API_CALL_INTERRUPT_PRIORITY > portMAX_PRIORITY ) || ( configMAX_API_CALL_INTERRUPT_PRIORITY < 2 ) )
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must be between 2 and 15
-#endif
-
-#if( ( configSUPPORT_FPU == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) )
- #error configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 to use this port with an FPU
-#endif
-
-/* A critical section is exited when the critical section nesting count reaches
-this value. */
-#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
-
-/* Tasks are not created with a floating point context, but can be given a
-floating point context after they have been created. A variable is stored as
-part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
-does not have an FPU context, or any other value if the task does have an FPU
-context. */
-#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
-
-/* Only the IF bit is set so tasks start with interrupts enabled. */
-#define portINITIAL_EFLAGS ( 0x200UL )
-
-/* Error interrupts are at the highest priority vectors. */
-#define portAPIC_LVT_ERROR_VECTOR ( 0xfe )
-#define portAPIC_SPURIOUS_INT_VECTOR ( 0xff )
-
-/* EFLAGS bits. */
-#define portEFLAGS_IF ( 0x200UL )
-
-/* FPU context size if FSAVE is used. */
-#define portFPU_CONTEXT_SIZE_BYTES 108
-
-/* The expected size of each entry in the IDT. Used to check structure packing
- is set correctly. */
-#define portEXPECTED_IDT_ENTRY_SIZE 8
-
-/* Default flags setting for entries in the IDT. */
-#define portIDT_FLAGS ( 0x8E )
-
-/* This is the lowest possible ISR vector available to application code. */
-#define portAPIC_MIN_ALLOWABLE_VECTOR ( 0x20 )
-
-/* If configASSERT() is defined then the system stack is filled with this value
-to allow for a crude stack overflow check. */
-#define portSTACK_WORD ( 0xecececec )
-/*-----------------------------------------------------------*/
-
-/*
- * Starts the first task executing.
- */
-extern void vPortStartFirstTask( void );
-
-/*
- * Used to catch tasks that attempt to return from their implementing function.
- */
-static void prvTaskExitError( void );
-
-/*
- * Complete one descriptor in the IDT.
- */
-static void prvSetInterruptGate( uint8_t ucNumber, ISR_Handler_t pxHandlerFunction, uint8_t ucFlags );
-
-/*
- * The default handler installed in each IDT position.
- */
-extern void vPortCentralInterruptWrapper( void );
-
-/*
- * Handler for portYIELD().
- */
-extern void vPortYieldCall( void );
-
-/*
- * Configure the APIC to generate the RTOS tick.
- */
-static void prvSetupTimerInterrupt( void );
-
-/*
- * Tick interrupt handler.
- */
-extern void vPortTimerHandler( void );
-
-/*
- * Check an interrupt vector is not too high, too low, in use by FreeRTOS, or
- * already in use by the application.
- */
-static BaseType_t prvCheckValidityOfVectorNumber( uint32_t ulVectorNumber );
-
-/*-----------------------------------------------------------*/
-
-/* A variable is used to keep track of the critical section nesting. This
-variable must be initialised to a non zero value to ensure interrupts don't
-inadvertently become unmasked before the scheduler starts. It is set to zero
-before the first task starts executing. */
-volatile uint32_t ulCriticalNesting = 9999UL;
-
-/* A structure used to map the various fields of an IDT entry into separate
-structure members. */
-struct IDTEntry
-{
- uint16_t usISRLow; /* Low 16 bits of handler address. */
- uint16_t usSegmentSelector; /* Flat model means this is not changed. */
- uint8_t ucZero; /* Must be set to zero. */
- uint8_t ucFlags; /* Flags for this entry. */
- uint16_t usISRHigh; /* High 16 bits of handler address. */
-} __attribute__( ( packed ) );
-typedef struct IDTEntry IDTEntry_t;
-
-
-/* Use to pass the location of the IDT to the CPU. */
-struct IDTPointer
-{
- uint16_t usTableLimit;
- uint32_t ulTableBase; /* The address of the first entry in xInterruptDescriptorTable. */
-} __attribute__( ( __packed__ ) );
-typedef struct IDTPointer IDTPointer_t;
-
-/* The IDT itself. */
-static __attribute__ ( ( aligned( 32 ) ) ) IDTEntry_t xInterruptDescriptorTable[ portNUM_VECTORS ];
-
-#if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 )
-
- /* A table in which application defined interrupt handlers are stored. These
- are called by the central interrupt handler if a common interrupt entry
- point it used. */
- static ISR_Handler_t xInterruptHandlerTable[ portNUM_VECTORS ] = { NULL };
-
-#endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */
-
-#if ( configSUPPORT_FPU == 1 )
-
- /* Saved as part of the task context. If pucPortTaskFPUContextBuffer is NULL
- then the task does not have an FPU context. If pucPortTaskFPUContextBuffer is
- not NULL then it points to a buffer into which the FPU context can be saved. */
- uint8_t *pucPortTaskFPUContextBuffer __attribute__((used)) = pdFALSE;
-
-#endif /* configSUPPORT_FPU */
-
-/* The stack used by interrupt handlers. */
-static uint32_t ulSystemStack[ configISR_STACK_SIZE ] __attribute__((used)) = { 0 };
-
-/* Don't use the very top of the system stack so the return address
-appears as 0 if the debugger tries to unwind the stack. */
-volatile uint32_t ulTopOfSystemStack __attribute__((used)) = ( uint32_t ) &( ulSystemStack[ configISR_STACK_SIZE - 5 ] );
-
-/* If a yield is requested from an interrupt or from a critical section then
-the yield is not performed immediately, and ulPortYieldPending is set to pdTRUE
-instead to indicate the yield should be performed at the end of the interrupt
-when the critical section is exited. */
-volatile uint32_t ulPortYieldPending __attribute__((used)) = pdFALSE;
-
-/* Counts the interrupt nesting depth. Used to know when to switch to the
-interrupt/system stack and when to save/restore a complete context. */
-volatile uint32_t ulInterruptNesting __attribute__((used)) = 0;
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-uint32_t ulCodeSegment;
-
- /* Setup the initial stack as expected by the portFREERTOS_INTERRUPT_EXIT macro. */
-
- *pxTopOfStack = 0x00;
- pxTopOfStack--;
- *pxTopOfStack = 0x00;
- pxTopOfStack--;
-
- /* Parameters first. */
- *pxTopOfStack = ( StackType_t ) pvParameters;
- pxTopOfStack--;
-
- /* There is nothing to return to so assert if attempting to use the return
- address. */
- *pxTopOfStack = ( StackType_t ) prvTaskExitError;
- pxTopOfStack--;
-
- /* iret used to start the task pops up to here. */
- *pxTopOfStack = portINITIAL_EFLAGS;
- pxTopOfStack--;
-
- /* CS */
- __asm volatile( "movl %%cs, %0" : "=r" ( ulCodeSegment ) );
- *pxTopOfStack = ulCodeSegment;
- pxTopOfStack--;
-
- /* First instruction in the task. */
- *pxTopOfStack = ( StackType_t ) pxCode;
- pxTopOfStack--;
-
- /* General purpose registers as expected by a POPA instruction. */
- *pxTopOfStack = 0xEA;
- pxTopOfStack--;
-
- *pxTopOfStack = 0xEC;
- pxTopOfStack--;
-
- *pxTopOfStack = 0xED1; /* EDX */
- pxTopOfStack--;
-
- *pxTopOfStack = 0xEB1; /* EBX */
- pxTopOfStack--;
-
- /* Hole for ESP. */
- pxTopOfStack--;
-
- *pxTopOfStack = 0x00; /* EBP */
- pxTopOfStack--;
-
- *pxTopOfStack = 0xE5; /* ESI */
- pxTopOfStack--;
-
- *pxTopOfStack = 0xeeeeeeee; /* EDI */
-
- #if ( configSUPPORT_FPU == 1 )
- {
- pxTopOfStack--;
-
- /* Buffer for FPU context, which is initialised to NULL as tasks are not
- created with an FPU context. */
- *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
- }
- #endif /* configSUPPORT_FPU */
-
- return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetInterruptGate( uint8_t ucNumber, ISR_Handler_t pxHandlerFunction, uint8_t ucFlags )
-{
-uint16_t usCodeSegment;
-uint32_t ulBase = ( uint32_t ) pxHandlerFunction;
-
- xInterruptDescriptorTable[ ucNumber ].usISRLow = ( uint16_t ) ( ulBase & USHRT_MAX );
- xInterruptDescriptorTable[ ucNumber ].usISRHigh = ( uint16_t ) ( ( ulBase >> 16UL ) & USHRT_MAX );
-
- /* When the flat model is used the CS will never change. */
- __asm volatile( "mov %%cs, %0" : "=r" ( usCodeSegment ) );
- xInterruptDescriptorTable[ ucNumber ].usSegmentSelector = usCodeSegment;
- xInterruptDescriptorTable[ ucNumber ].ucZero = 0;
- xInterruptDescriptorTable[ ucNumber ].ucFlags = ucFlags;
-}
-/*-----------------------------------------------------------*/
-
-void vPortSetupIDT( void )
-{
-uint32_t ulNum;
-IDTPointer_t xIDT;
-
- #if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 )
- {
- for( ulNum = 0; ulNum < portNUM_VECTORS; ulNum++ )
- {
- /* If a handler has not already been installed on this vector. */
- if( ( xInterruptDescriptorTable[ ulNum ].usISRLow == 0x00 ) && ( xInterruptDescriptorTable[ ulNum ].usISRHigh == 0x00 ) )
- {
- prvSetInterruptGate( ( uint8_t ) ulNum, vPortCentralInterruptWrapper, portIDT_FLAGS );
- }
- }
- }
- #endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */
-
- /* Set IDT address. */
- xIDT.ulTableBase = ( uint32_t ) xInterruptDescriptorTable;
- xIDT.usTableLimit = sizeof( xInterruptDescriptorTable ) - 1;
-
- /* Set IDT in CPU. */
- __asm volatile( "lidt %0" :: "m" (xIDT) );
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
- /* A function that implements a task must not exit or attempt to return to
- its caller as there is nothing to return to. If a task wants to exit it
- should instead call vTaskDelete( NULL ).
-
- Artificially force an assert() to be triggered if configASSERT() is
- defined, then stop here so application writers can catch the error. */
- configASSERT( ulCriticalNesting == ~0UL );
- portDISABLE_INTERRUPTS();
- for( ;; );
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupTimerInterrupt( void )
-{
-extern void vPortAPICErrorHandlerWrapper( void );
-extern void vPortAPICSpuriousHandler( void );
-
- /* Initialise LAPIC to a well known state. */
- portAPIC_LDR = 0xFFFFFFFF;
- portAPIC_LDR = ( ( portAPIC_LDR & 0x00FFFFFF ) | 0x00000001 );
- portAPIC_LVT_TIMER = portAPIC_DISABLE;
- portAPIC_LVT_PERF = portAPIC_NMI;
- portAPIC_LVT_LINT0 = portAPIC_DISABLE;
- portAPIC_LVT_LINT1 = portAPIC_DISABLE;
- portAPIC_TASK_PRIORITY = 0;
-
- /* Install APIC timer ISR vector. */
- prvSetInterruptGate( ( uint8_t ) portAPIC_TIMER_INT_VECTOR, vPortTimerHandler, portIDT_FLAGS );
-
- /* Install API error handler. */
- prvSetInterruptGate( ( uint8_t ) portAPIC_LVT_ERROR_VECTOR, vPortAPICErrorHandlerWrapper, portIDT_FLAGS );
-
- /* Install Yield handler. */
- prvSetInterruptGate( ( uint8_t ) portAPIC_YIELD_INT_VECTOR, vPortYieldCall, portIDT_FLAGS );
-
- /* Install spurious interrupt vector. */
- prvSetInterruptGate( ( uint8_t ) portAPIC_SPURIOUS_INT_VECTOR, vPortAPICSpuriousHandler, portIDT_FLAGS );
-
- /* Enable the APIC, mapping the spurious interrupt at the same time. */
- portAPIC_SPURIOUS_INT = portAPIC_SPURIOUS_INT_VECTOR | portAPIC_ENABLE_BIT;
-
- /* Set timer error vector. */
- portAPIC_LVT_ERROR = portAPIC_LVT_ERROR_VECTOR;
-
- /* Set the interrupt frequency. */
- portAPIC_TMRDIV = portAPIC_DIV_16;
- portAPIC_TIMER_INITIAL_COUNT = ( ( configCPU_CLOCK_HZ >> 4UL ) / configTICK_RATE_HZ ) - 1UL;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-BaseType_t xWord;
-
- /* Some versions of GCC require the -mno-ms-bitfields command line option
- for packing to work. */
- configASSERT( sizeof( struct IDTEntry ) == portEXPECTED_IDT_ENTRY_SIZE );
-
- /* Fill part of the system stack with a known value to help detect stack
- overflow. A few zeros are left so GDB doesn't get confused unwinding
- the stack. */
- for( xWord = 0; xWord < configISR_STACK_SIZE - 20; xWord++ )
- {
- ulSystemStack[ xWord ] = portSTACK_WORD;
- }
-
- /* Initialise Interrupt Descriptor Table (IDT). */
- vPortSetupIDT();
-
- /* Initialise LAPIC and install system handlers. */
- prvSetupTimerInterrupt();
-
- /* Make sure the stack used by interrupts is aligned. */
- ulTopOfSystemStack &= ~portBYTE_ALIGNMENT_MASK;
-
- ulCriticalNesting = 0;
-
- /* Enable LAPIC Counter.*/
- portAPIC_LVT_TIMER = portAPIC_TIMER_PERIODIC | portAPIC_TIMER_INT_VECTOR;
-
- /* Sometimes needed. */
- portAPIC_TMRDIV = portAPIC_DIV_16;
-
- /* Should not return from the following function as the scheduler will then
- be executing the tasks. */
- vPortStartFirstTask();
-
- return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
- /* Not implemented in ports where there is nothing to return to.
- Artificially force an assert. */
- configASSERT( ulCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
- if( ulCriticalNesting == 0 )
- {
- #if( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )
- {
- __asm volatile( "cli" );
- }
- #else
- {
- portAPIC_TASK_PRIORITY = portMAX_API_CALL_PRIORITY;
- configASSERT( portAPIC_TASK_PRIORITY == portMAX_API_CALL_PRIORITY );
- }
- #endif
- }
-
- /* Now interrupts are disabled ulCriticalNesting can be accessed
- directly. Increment ulCriticalNesting to keep a count of how many times
- portENTER_CRITICAL() has been called. */
- ulCriticalNesting++;
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
- if( ulCriticalNesting > portNO_CRITICAL_NESTING )
- {
- /* Decrement the nesting count as the critical section is being
- exited. */
- ulCriticalNesting--;
-
- /* If the nesting level has reached zero then all interrupt
- priorities must be re-enabled. */
- if( ulCriticalNesting == portNO_CRITICAL_NESTING )
- {
- /* Critical nesting has reached zero so all interrupt priorities
- should be unmasked. */
- #if( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )
- {
- __asm volatile( "sti" );
- }
- #else
- {
- portAPIC_TASK_PRIORITY = 0;
- }
- #endif
-
- /* If a yield was pended from within the critical section then
- perform the yield now. */
- if( ulPortYieldPending != pdFALSE )
- {
- ulPortYieldPending = pdFALSE;
- __asm volatile( portYIELD_INTERRUPT );
- }
- }
- }
-}
-/*-----------------------------------------------------------*/
-
-uint32_t ulPortSetInterruptMask( void )
-{
-volatile uint32_t ulOriginalMask;
-
- /* Set mask to max syscall priority. */
- #if( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )
- {
- /* Return whether interrupts were already enabled or not. Pop adjusts
- the stack first. */
- __asm volatile( "pushf \t\n"
- "pop %0 \t\n"
- "cli "
- : "=rm" (ulOriginalMask) :: "memory" );
-
- ulOriginalMask &= portEFLAGS_IF;
- }
- #else
- {
- /* Return original mask. */
- ulOriginalMask = portAPIC_TASK_PRIORITY;
- portAPIC_TASK_PRIORITY = portMAX_API_CALL_PRIORITY;
- configASSERT( portAPIC_TASK_PRIORITY == portMAX_API_CALL_PRIORITY );
- }
- #endif
-
- return ulOriginalMask;
-}
-/*-----------------------------------------------------------*/
-
-void vPortClearInterruptMask( uint32_t ulNewMaskValue )
-{
- #if( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )
- {
- if( ulNewMaskValue != pdFALSE )
- {
- __asm volatile( "sti" );
- }
- }
- #else
- {
- portAPIC_TASK_PRIORITY = ulNewMaskValue;
- configASSERT( portAPIC_TASK_PRIORITY == ulNewMaskValue );
- }
- #endif
-}
-/*-----------------------------------------------------------*/
-
-#if ( configSUPPORT_FPU == 1 )
-
- void vPortTaskUsesFPU( void )
- {
- /* A task is registering the fact that it needs an FPU context. Allocate a
- buffer into which the context can be saved. */
- pucPortTaskFPUContextBuffer = ( uint8_t * ) pvPortMalloc( portFPU_CONTEXT_SIZE_BYTES );
- configASSERT( pucPortTaskFPUContextBuffer );
-
- /* Initialise the floating point registers. */
- __asm volatile( "fninit" );
- }
-
-#endif /* configSUPPORT_FPU */
-/*-----------------------------------------------------------*/
-
-void vPortAPICErrorHandler( void )
-{
-/* Variable to hold the APIC error status for viewing in the debugger. */
-volatile uint32_t ulErrorStatus = 0;
-
- portAPIC_ERROR_STATUS = 0;
- ulErrorStatus = portAPIC_ERROR_STATUS;
- ( void ) ulErrorStatus;
-
- /* Force an assert. */
- configASSERT( ulCriticalNesting == ~0UL );
-}
-/*-----------------------------------------------------------*/
-
-#if( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 )
-
- void vPortCentralInterruptHandler( uint32_t ulVector )
- {
- if( ulVector < portNUM_VECTORS )
- {
- if( xInterruptHandlerTable[ ulVector ] != NULL )
- {
- ( xInterruptHandlerTable[ ulVector ] )();
- }
- }
-
- /* Check for a system stack overflow. */
- configASSERT( ulSystemStack[ 10 ] == portSTACK_WORD );
- configASSERT( ulSystemStack[ 12 ] == portSTACK_WORD );
- configASSERT( ulSystemStack[ 14 ] == portSTACK_WORD );
- }
-
-#endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 )
-
- BaseType_t xPortRegisterCInterruptHandler( ISR_Handler_t pxHandler, uint32_t ulVectorNumber )
- {
- BaseType_t xReturn;
-
- xReturn = prvCheckValidityOfVectorNumber( ulVectorNumber );
-
- if( xReturn != pdFAIL )
- {
- /* Save the handler passed in by the application in the vector number
- passed in. The addresses are then called from the central interrupt
- handler. */
- xInterruptHandlerTable[ ulVectorNumber ] = pxHandler;
- }
-
- return xReturn;
- }
-
-#endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortInstallInterruptHandler( ISR_Handler_t pxHandler, uint32_t ulVectorNumber )
-{
-BaseType_t xReturn;
-
- xReturn = prvCheckValidityOfVectorNumber( ulVectorNumber );
-
- if( xReturn != pdFAIL )
- {
- taskENTER_CRITICAL();
- {
- /* Update the IDT to include the application defined handler. */
- prvSetInterruptGate( ( uint8_t ) ulVectorNumber, ( ISR_Handler_t ) pxHandler, portIDT_FLAGS );
- }
- taskEXIT_CRITICAL();
- }
-
- return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-static BaseType_t prvCheckValidityOfVectorNumber( uint32_t ulVectorNumber )
-{
-BaseType_t xReturn;
-
- /* Check validity of vector number. */
- if( ulVectorNumber >= portNUM_VECTORS )
- {
- /* Too high. */
- xReturn = pdFAIL;
- }
- else if( ulVectorNumber < portAPIC_MIN_ALLOWABLE_VECTOR )
- {
- /* Too low. */
- xReturn = pdFAIL;
- }
- else if( ulVectorNumber == portAPIC_TIMER_INT_VECTOR )
- {
- /* In use by FreeRTOS. */
- xReturn = pdFAIL;
- }
- else if( ulVectorNumber == portAPIC_YIELD_INT_VECTOR )
- {
- /* In use by FreeRTOS. */
- xReturn = pdFAIL;
- }
- else if( ulVectorNumber == portAPIC_LVT_ERROR_VECTOR )
- {
- /* In use by FreeRTOS. */
- xReturn = pdFAIL;
- }
- else if( ulVectorNumber == portAPIC_SPURIOUS_INT_VECTOR )
- {
- /* In use by FreeRTOS. */
- xReturn = pdFAIL;
- }
- else if( xInterruptHandlerTable[ ulVectorNumber ] != NULL )
- {
- /* Already in use by the application. */
- xReturn = pdFAIL;
- }
- else
- {
- xReturn = pdPASS;
- }
-
- return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vGenerateYieldInterrupt( void )
-{
- __asm volatile( portYIELD_INTERRUPT );
-}
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Standard includes. */
+#include <limits.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+ /* Check the configuration. */
+ #if( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+#if( configISR_STACK_SIZE < ( configMINIMAL_STACK_SIZE * 2 ) )
+ #warning configISR_STACK_SIZE is probably too small!
+#endif /* ( configISR_STACK_SIZE < configMINIMAL_STACK_SIZE * 2 ) */
+
+#if( ( configMAX_API_CALL_INTERRUPT_PRIORITY > portMAX_PRIORITY ) || ( configMAX_API_CALL_INTERRUPT_PRIORITY < 2 ) )
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must be between 2 and 15
+#endif
+
+#if( ( configSUPPORT_FPU == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) )
+ #error configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 to use this port with an FPU
+#endif
+
+/* A critical section is exited when the critical section nesting count reaches
+this value. */
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
+
+/* Tasks are not created with a floating point context, but can be given a
+floating point context after they have been created. A variable is stored as
+part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+does not have an FPU context, or any other value if the task does have an FPU
+context. */
+#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
+
+/* Only the IF bit is set so tasks start with interrupts enabled. */
+#define portINITIAL_EFLAGS ( 0x200UL )
+
+/* Error interrupts are at the highest priority vectors. */
+#define portAPIC_LVT_ERROR_VECTOR ( 0xfe )
+#define portAPIC_SPURIOUS_INT_VECTOR ( 0xff )
+
+/* EFLAGS bits. */
+#define portEFLAGS_IF ( 0x200UL )
+
+/* FPU context size if FSAVE is used. */
+#define portFPU_CONTEXT_SIZE_BYTES 108
+
+/* The expected size of each entry in the IDT. Used to check structure packing
+ is set correctly. */
+#define portEXPECTED_IDT_ENTRY_SIZE 8
+
+/* Default flags setting for entries in the IDT. */
+#define portIDT_FLAGS ( 0x8E )
+
+/* This is the lowest possible ISR vector available to application code. */
+#define portAPIC_MIN_ALLOWABLE_VECTOR ( 0x20 )
+
+/* If configASSERT() is defined then the system stack is filled with this value
+to allow for a crude stack overflow check. */
+#define portSTACK_WORD ( 0xecececec )
+/*-----------------------------------------------------------*/
+
+/*
+ * Starts the first task executing.
+ */
+extern void vPortStartFirstTask( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*
+ * Complete one descriptor in the IDT.
+ */
+static void prvSetInterruptGate( uint8_t ucNumber, ISR_Handler_t pxHandlerFunction, uint8_t ucFlags );
+
+/*
+ * The default handler installed in each IDT position.
+ */
+extern void vPortCentralInterruptWrapper( void );
+
+/*
+ * Handler for portYIELD().
+ */
+extern void vPortYieldCall( void );
+
+/*
+ * Configure the APIC to generate the RTOS tick.
+ */
+static void prvSetupTimerInterrupt( void );
+
+/*
+ * Tick interrupt handler.
+ */
+extern void vPortTimerHandler( void );
+
+/*
+ * Check an interrupt vector is not too high, too low, in use by FreeRTOS, or
+ * already in use by the application.
+ */
+static BaseType_t prvCheckValidityOfVectorNumber( uint32_t ulVectorNumber );
+
+/*-----------------------------------------------------------*/
+
+/* A variable is used to keep track of the critical section nesting. This
+variable must be initialised to a non zero value to ensure interrupts don't
+inadvertently become unmasked before the scheduler starts. It is set to zero
+before the first task starts executing. */
+volatile uint32_t ulCriticalNesting = 9999UL;
+
+/* A structure used to map the various fields of an IDT entry into separate
+structure members. */
+struct IDTEntry
+{
+ uint16_t usISRLow; /* Low 16 bits of handler address. */
+ uint16_t usSegmentSelector; /* Flat model means this is not changed. */
+ uint8_t ucZero; /* Must be set to zero. */
+ uint8_t ucFlags; /* Flags for this entry. */
+ uint16_t usISRHigh; /* High 16 bits of handler address. */
+} __attribute__( ( packed ) );
+typedef struct IDTEntry IDTEntry_t;
+
+
+/* Use to pass the location of the IDT to the CPU. */
+struct IDTPointer
+{
+ uint16_t usTableLimit;
+ uint32_t ulTableBase; /* The address of the first entry in xInterruptDescriptorTable. */
+} __attribute__( ( __packed__ ) );
+typedef struct IDTPointer IDTPointer_t;
+
+/* The IDT itself. */
+static __attribute__ ( ( aligned( 32 ) ) ) IDTEntry_t xInterruptDescriptorTable[ portNUM_VECTORS ];
+
+#if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 )
+
+ /* A table in which application defined interrupt handlers are stored. These
+ are called by the central interrupt handler if a common interrupt entry
+ point it used. */
+ static ISR_Handler_t xInterruptHandlerTable[ portNUM_VECTORS ] = { NULL };
+
+#endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */
+
+#if ( configSUPPORT_FPU == 1 )
+
+ /* Saved as part of the task context. If pucPortTaskFPUContextBuffer is NULL
+ then the task does not have an FPU context. If pucPortTaskFPUContextBuffer is
+ not NULL then it points to a buffer into which the FPU context can be saved. */
+ uint8_t *pucPortTaskFPUContextBuffer __attribute__((used)) = pdFALSE;
+
+#endif /* configSUPPORT_FPU */
+
+/* The stack used by interrupt handlers. */
+static uint32_t ulSystemStack[ configISR_STACK_SIZE ] __attribute__((used)) = { 0 };
+
+/* Don't use the very top of the system stack so the return address
+appears as 0 if the debugger tries to unwind the stack. */
+volatile uint32_t ulTopOfSystemStack __attribute__((used)) = ( uint32_t ) &( ulSystemStack[ configISR_STACK_SIZE - 5 ] );
+
+/* If a yield is requested from an interrupt or from a critical section then
+the yield is not performed immediately, and ulPortYieldPending is set to pdTRUE
+instead to indicate the yield should be performed at the end of the interrupt
+when the critical section is exited. */
+volatile uint32_t ulPortYieldPending __attribute__((used)) = pdFALSE;
+
+/* Counts the interrupt nesting depth. Used to know when to switch to the
+interrupt/system stack and when to save/restore a complete context. */
+volatile uint32_t ulInterruptNesting __attribute__((used)) = 0;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+uint32_t ulCodeSegment;
+
+ /* Setup the initial stack as expected by the portFREERTOS_INTERRUPT_EXIT macro. */
+
+ *pxTopOfStack = 0x00;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x00;
+ pxTopOfStack--;
+
+ /* Parameters first. */
+ *pxTopOfStack = ( StackType_t ) pvParameters;
+ pxTopOfStack--;
+
+ /* There is nothing to return to so assert if attempting to use the return
+ address. */
+ *pxTopOfStack = ( StackType_t ) prvTaskExitError;
+ pxTopOfStack--;
+
+ /* iret used to start the task pops up to here. */
+ *pxTopOfStack = portINITIAL_EFLAGS;
+ pxTopOfStack--;
+
+ /* CS */
+ __asm volatile( "movl %%cs, %0" : "=r" ( ulCodeSegment ) );
+ *pxTopOfStack = ulCodeSegment;
+ pxTopOfStack--;
+
+ /* First instruction in the task. */
+ *pxTopOfStack = ( StackType_t ) pxCode;
+ pxTopOfStack--;
+
+ /* General purpose registers as expected by a POPA instruction. */
+ *pxTopOfStack = 0xEA;
+ pxTopOfStack--;
+
+ *pxTopOfStack = 0xEC;
+ pxTopOfStack--;
+
+ *pxTopOfStack = 0xED1; /* EDX */
+ pxTopOfStack--;
+
+ *pxTopOfStack = 0xEB1; /* EBX */
+ pxTopOfStack--;
+
+ /* Hole for ESP. */
+ pxTopOfStack--;
+
+ *pxTopOfStack = 0x00; /* EBP */
+ pxTopOfStack--;
+
+ *pxTopOfStack = 0xE5; /* ESI */
+ pxTopOfStack--;
+
+ *pxTopOfStack = 0xeeeeeeee; /* EDI */
+
+ #if ( configSUPPORT_FPU == 1 )
+ {
+ pxTopOfStack--;
+
+ /* Buffer for FPU context, which is initialised to NULL as tasks are not
+ created with an FPU context. */
+ *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+ }
+ #endif /* configSUPPORT_FPU */
+
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetInterruptGate( uint8_t ucNumber, ISR_Handler_t pxHandlerFunction, uint8_t ucFlags )
+{
+uint16_t usCodeSegment;
+uint32_t ulBase = ( uint32_t ) pxHandlerFunction;
+
+ xInterruptDescriptorTable[ ucNumber ].usISRLow = ( uint16_t ) ( ulBase & USHRT_MAX );
+ xInterruptDescriptorTable[ ucNumber ].usISRHigh = ( uint16_t ) ( ( ulBase >> 16UL ) & USHRT_MAX );
+
+ /* When the flat model is used the CS will never change. */
+ __asm volatile( "mov %%cs, %0" : "=r" ( usCodeSegment ) );
+ xInterruptDescriptorTable[ ucNumber ].usSegmentSelector = usCodeSegment;
+ xInterruptDescriptorTable[ ucNumber ].ucZero = 0;
+ xInterruptDescriptorTable[ ucNumber ].ucFlags = ucFlags;
+}
+/*-----------------------------------------------------------*/
+
+void vPortSetupIDT( void )
+{
+uint32_t ulNum;
+IDTPointer_t xIDT;
+
+ #if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 )
+ {
+ for( ulNum = 0; ulNum < portNUM_VECTORS; ulNum++ )
+ {
+ /* If a handler has not already been installed on this vector. */
+ if( ( xInterruptDescriptorTable[ ulNum ].usISRLow == 0x00 ) && ( xInterruptDescriptorTable[ ulNum ].usISRHigh == 0x00 ) )
+ {
+ prvSetInterruptGate( ( uint8_t ) ulNum, vPortCentralInterruptWrapper, portIDT_FLAGS );
+ }
+ }
+ }
+ #endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */
+
+ /* Set IDT address. */
+ xIDT.ulTableBase = ( uint32_t ) xInterruptDescriptorTable;
+ xIDT.usTableLimit = sizeof( xInterruptDescriptorTable ) - 1;
+
+ /* Set IDT in CPU. */
+ __asm volatile( "lidt %0" :: "m" (xIDT) );
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+ /* A function that implements a task must not exit or attempt to return to
+ its caller as there is nothing to return to. If a task wants to exit it
+ should instead call vTaskDelete( NULL ).
+
+ Artificially force an assert() to be triggered if configASSERT() is
+ defined, then stop here so application writers can catch the error. */
+ configASSERT( ulCriticalNesting == ~0UL );
+ portDISABLE_INTERRUPTS();
+ for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+extern void vPortAPICErrorHandlerWrapper( void );
+extern void vPortAPICSpuriousHandler( void );
+
+ /* Initialise LAPIC to a well known state. */
+ portAPIC_LDR = 0xFFFFFFFF;
+ portAPIC_LDR = ( ( portAPIC_LDR & 0x00FFFFFF ) | 0x00000001 );
+ portAPIC_LVT_TIMER = portAPIC_DISABLE;
+ portAPIC_LVT_PERF = portAPIC_NMI;
+ portAPIC_LVT_LINT0 = portAPIC_DISABLE;
+ portAPIC_LVT_LINT1 = portAPIC_DISABLE;
+ portAPIC_TASK_PRIORITY = 0;
+
+ /* Install APIC timer ISR vector. */
+ prvSetInterruptGate( ( uint8_t ) portAPIC_TIMER_INT_VECTOR, vPortTimerHandler, portIDT_FLAGS );
+
+ /* Install API error handler. */
+ prvSetInterruptGate( ( uint8_t ) portAPIC_LVT_ERROR_VECTOR, vPortAPICErrorHandlerWrapper, portIDT_FLAGS );
+
+ /* Install Yield handler. */
+ prvSetInterruptGate( ( uint8_t ) portAPIC_YIELD_INT_VECTOR, vPortYieldCall, portIDT_FLAGS );
+
+ /* Install spurious interrupt vector. */
+ prvSetInterruptGate( ( uint8_t ) portAPIC_SPURIOUS_INT_VECTOR, vPortAPICSpuriousHandler, portIDT_FLAGS );
+
+ /* Enable the APIC, mapping the spurious interrupt at the same time. */
+ portAPIC_SPURIOUS_INT = portAPIC_SPURIOUS_INT_VECTOR | portAPIC_ENABLE_BIT;
+
+ /* Set timer error vector. */
+ portAPIC_LVT_ERROR = portAPIC_LVT_ERROR_VECTOR;
+
+ /* Set the interrupt frequency. */
+ portAPIC_TMRDIV = portAPIC_DIV_16;
+ portAPIC_TIMER_INITIAL_COUNT = ( ( configCPU_CLOCK_HZ >> 4UL ) / configTICK_RATE_HZ ) - 1UL;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+BaseType_t xWord;
+
+ /* Some versions of GCC require the -mno-ms-bitfields command line option
+ for packing to work. */
+ configASSERT( sizeof( struct IDTEntry ) == portEXPECTED_IDT_ENTRY_SIZE );
+
+ /* Fill part of the system stack with a known value to help detect stack
+ overflow. A few zeros are left so GDB doesn't get confused unwinding
+ the stack. */
+ for( xWord = 0; xWord < configISR_STACK_SIZE - 20; xWord++ )
+ {
+ ulSystemStack[ xWord ] = portSTACK_WORD;
+ }
+
+ /* Initialise Interrupt Descriptor Table (IDT). */
+ vPortSetupIDT();
+
+ /* Initialise LAPIC and install system handlers. */
+ prvSetupTimerInterrupt();
+
+ /* Make sure the stack used by interrupts is aligned. */
+ ulTopOfSystemStack &= ~portBYTE_ALIGNMENT_MASK;
+
+ ulCriticalNesting = 0;
+
+ /* Enable LAPIC Counter.*/
+ portAPIC_LVT_TIMER = portAPIC_TIMER_PERIODIC | portAPIC_TIMER_INT_VECTOR;
+
+ /* Sometimes needed. */
+ portAPIC_TMRDIV = portAPIC_DIV_16;
+
+ /* Should not return from the following function as the scheduler will then
+ be executing the tasks. */
+ vPortStartFirstTask();
+
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+ /* Not implemented in ports where there is nothing to return to.
+ Artificially force an assert. */
+ configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+ if( ulCriticalNesting == 0 )
+ {
+ #if( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )
+ {
+ __asm volatile( "cli" );
+ }
+ #else
+ {
+ portAPIC_TASK_PRIORITY = portMAX_API_CALL_PRIORITY;
+ configASSERT( portAPIC_TASK_PRIORITY == portMAX_API_CALL_PRIORITY );
+ }
+ #endif
+ }
+
+ /* Now interrupts are disabled ulCriticalNesting can be accessed
+ directly. Increment ulCriticalNesting to keep a count of how many times
+ portENTER_CRITICAL() has been called. */
+ ulCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+ if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+ {
+ /* Decrement the nesting count as the critical section is being
+ exited. */
+ ulCriticalNesting--;
+
+ /* If the nesting level has reached zero then all interrupt
+ priorities must be re-enabled. */
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+ {
+ /* Critical nesting has reached zero so all interrupt priorities
+ should be unmasked. */
+ #if( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )
+ {
+ __asm volatile( "sti" );
+ }
+ #else
+ {
+ portAPIC_TASK_PRIORITY = 0;
+ }
+ #endif
+
+ /* If a yield was pended from within the critical section then
+ perform the yield now. */
+ if( ulPortYieldPending != pdFALSE )
+ {
+ ulPortYieldPending = pdFALSE;
+ __asm volatile( portYIELD_INTERRUPT );
+ }
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulPortSetInterruptMask( void )
+{
+volatile uint32_t ulOriginalMask;
+
+ /* Set mask to max syscall priority. */
+ #if( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )
+ {
+ /* Return whether interrupts were already enabled or not. Pop adjusts
+ the stack first. */
+ __asm volatile( "pushf \t\n"
+ "pop %0 \t\n"
+ "cli "
+ : "=rm" (ulOriginalMask) :: "memory" );
+
+ ulOriginalMask &= portEFLAGS_IF;
+ }
+ #else
+ {
+ /* Return original mask. */
+ ulOriginalMask = portAPIC_TASK_PRIORITY;
+ portAPIC_TASK_PRIORITY = portMAX_API_CALL_PRIORITY;
+ configASSERT( portAPIC_TASK_PRIORITY == portMAX_API_CALL_PRIORITY );
+ }
+ #endif
+
+ return ulOriginalMask;
+}
+/*-----------------------------------------------------------*/
+
+void vPortClearInterruptMask( uint32_t ulNewMaskValue )
+{
+ #if( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )
+ {
+ if( ulNewMaskValue != pdFALSE )
+ {
+ __asm volatile( "sti" );
+ }
+ }
+ #else
+ {
+ portAPIC_TASK_PRIORITY = ulNewMaskValue;
+ configASSERT( portAPIC_TASK_PRIORITY == ulNewMaskValue );
+ }
+ #endif
+}
+/*-----------------------------------------------------------*/
+
+#if ( configSUPPORT_FPU == 1 )
+
+ void vPortTaskUsesFPU( void )
+ {
+ /* A task is registering the fact that it needs an FPU context. Allocate a
+ buffer into which the context can be saved. */
+ pucPortTaskFPUContextBuffer = ( uint8_t * ) pvPortMalloc( portFPU_CONTEXT_SIZE_BYTES );
+ configASSERT( pucPortTaskFPUContextBuffer );
+
+ /* Initialise the floating point registers. */
+ __asm volatile( "fninit" );
+ }
+
+#endif /* configSUPPORT_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortAPICErrorHandler( void )
+{
+/* Variable to hold the APIC error status for viewing in the debugger. */
+volatile uint32_t ulErrorStatus = 0;
+
+ portAPIC_ERROR_STATUS = 0;
+ ulErrorStatus = portAPIC_ERROR_STATUS;
+ ( void ) ulErrorStatus;
+
+ /* Force an assert. */
+ configASSERT( ulCriticalNesting == ~0UL );
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 )
+
+ void vPortCentralInterruptHandler( uint32_t ulVector )
+ {
+ if( ulVector < portNUM_VECTORS )
+ {
+ if( xInterruptHandlerTable[ ulVector ] != NULL )
+ {
+ ( xInterruptHandlerTable[ ulVector ] )();
+ }
+ }
+
+ /* Check for a system stack overflow. */
+ configASSERT( ulSystemStack[ 10 ] == portSTACK_WORD );
+ configASSERT( ulSystemStack[ 12 ] == portSTACK_WORD );
+ configASSERT( ulSystemStack[ 14 ] == portSTACK_WORD );
+ }
+
+#endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 )
+
+ BaseType_t xPortRegisterCInterruptHandler( ISR_Handler_t pxHandler, uint32_t ulVectorNumber )
+ {
+ BaseType_t xReturn;
+
+ xReturn = prvCheckValidityOfVectorNumber( ulVectorNumber );
+
+ if( xReturn != pdFAIL )
+ {
+ /* Save the handler passed in by the application in the vector number
+ passed in. The addresses are then called from the central interrupt
+ handler. */
+ xInterruptHandlerTable[ ulVectorNumber ] = pxHandler;
+ }
+
+ return xReturn;
+ }
+
+#endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortInstallInterruptHandler( ISR_Handler_t pxHandler, uint32_t ulVectorNumber )
+{
+BaseType_t xReturn;
+
+ xReturn = prvCheckValidityOfVectorNumber( ulVectorNumber );
+
+ if( xReturn != pdFAIL )
+ {
+ taskENTER_CRITICAL();
+ {
+ /* Update the IDT to include the application defined handler. */
+ prvSetInterruptGate( ( uint8_t ) ulVectorNumber, ( ISR_Handler_t ) pxHandler, portIDT_FLAGS );
+ }
+ taskEXIT_CRITICAL();
+ }
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvCheckValidityOfVectorNumber( uint32_t ulVectorNumber )
+{
+BaseType_t xReturn;
+
+ /* Check validity of vector number. */
+ if( ulVectorNumber >= portNUM_VECTORS )
+ {
+ /* Too high. */
+ xReturn = pdFAIL;
+ }
+ else if( ulVectorNumber < portAPIC_MIN_ALLOWABLE_VECTOR )
+ {
+ /* Too low. */
+ xReturn = pdFAIL;
+ }
+ else if( ulVectorNumber == portAPIC_TIMER_INT_VECTOR )
+ {
+ /* In use by FreeRTOS. */
+ xReturn = pdFAIL;
+ }
+ else if( ulVectorNumber == portAPIC_YIELD_INT_VECTOR )
+ {
+ /* In use by FreeRTOS. */
+ xReturn = pdFAIL;
+ }
+ else if( ulVectorNumber == portAPIC_LVT_ERROR_VECTOR )
+ {
+ /* In use by FreeRTOS. */
+ xReturn = pdFAIL;
+ }
+ else if( ulVectorNumber == portAPIC_SPURIOUS_INT_VECTOR )
+ {
+ /* In use by FreeRTOS. */
+ xReturn = pdFAIL;
+ }
+ else if( xInterruptHandlerTable[ ulVectorNumber ] != NULL )
+ {
+ /* Already in use by the application. */
+ xReturn = pdFAIL;
+ }
+ else
+ {
+ xReturn = pdPASS;
+ }
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vGenerateYieldInterrupt( void )
+{
+ __asm volatile( portYIELD_INTERRUPT );
+}
diff --git a/portable/GCC/IA32_flat/portASM.S b/portable/GCC/IA32_flat/portASM.S
index 1387c2c..4dac1af 100644
--- a/portable/GCC/IA32_flat/portASM.S
+++ b/portable/GCC/IA32_flat/portASM.S
@@ -1,275 +1,268 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-.file "portASM.S"
-#include "FreeRTOSConfig.h"
-#include "ISR_Support.h"
-
- .extern pxCurrentTCB
- .extern vTaskSwitchContext
- .extern vPortCentralInterruptHandler
- .extern xTaskIncrementTick
- .extern vPortAPICErrorHandler
- .extern pucPortTaskFPUContextBuffer
- .extern ulPortYieldPending
-
- .global vPortStartFirstTask
- .global vPortCentralInterruptWrapper
- .global vPortAPICErrorHandlerWrapper
- .global vPortTimerHandler
- .global vPortYieldCall
- .global vPortAPICSpuriousHandler
-
- .text
-
-/*-----------------------------------------------------------*/
-
-.align 4
-.func vPortYieldCall
-vPortYieldCall:
- /* Save general purpose registers. */
- pusha
-
- .if configSUPPORT_FPU == 1
-
- /* If the task has a buffer allocated to save the FPU context then save
- the FPU context now. */
- movl pucPortTaskFPUContextBuffer, %eax
- test %eax, %eax
- je 1f
- fnsave ( %eax )
- fwait
-
- 1:
-
- /* Save the address of the FPU context, if any. */
- push pucPortTaskFPUContextBuffer
-
- .endif /* configSUPPORT_FPU */
-
- /* Find the TCB. */
- movl pxCurrentTCB, %eax
-
- /* Stack location is first item in the TCB. */
- movl %esp, (%eax)
-
- call vTaskSwitchContext
-
- /* Find the location of pxCurrentTCB again - a callee saved register could
- be used in place of eax to prevent this second load, but that then relies
- on the compiler and other asm code. */
- movl pxCurrentTCB, %eax
- movl (%eax), %esp
-
- .if configSUPPORT_FPU == 1
-
- /* Restore address of task's FPU context buffer. */
- pop pucPortTaskFPUContextBuffer
-
- /* If the task has a buffer allocated in which its FPU context is saved,
- then restore it now. */
- movl pucPortTaskFPUContextBuffer, %eax
- test %eax, %eax
- je 1f
- frstor ( %eax )
- 1:
- .endif
-
- popa
- iret
-
-.endfunc
-/*-----------------------------------------------------------*/
-
-.align 4
-.func vPortStartFirstTask
-vPortStartFirstTask:
-
- /* Find the TCB. */
- movl pxCurrentTCB, %eax
-
- /* Stack location is first item in the TCB. */
- movl (%eax), %esp
-
- /* Restore FPU context flag. */
- .if configSUPPORT_FPU == 1
-
- pop pucPortTaskFPUContextBuffer
-
- .endif /* configSUPPORT_FPU */
-
- /* Restore general purpose registers. */
- popa
- iret
-.endfunc
-/*-----------------------------------------------------------*/
-
-.align 4
-.func vPortAPICErrorHandlerWrapper
-vPortAPICErrorHandlerWrapper:
- pusha
- call vPortAPICErrorHandler
- popa
- /* EOI. */
- movl $0x00, (0xFEE000B0)
- iret
-.endfunc
-/*-----------------------------------------------------------*/
-
-.align 4
-.func vPortTimerHandler
-vPortTimerHandler:
-
- /* Save general purpose registers. */
- pusha
-
- /* Interrupts are not nested, so save the rest of the task context. */
- .if configSUPPORT_FPU == 1
-
- /* If the task has a buffer allocated to save the FPU context then save the
- FPU context now. */
- movl pucPortTaskFPUContextBuffer, %eax
- test %eax, %eax
- je 1f
- fnsave ( %eax ) /* Save FLOP context into ucTempFPUBuffer array. */
- fwait
-
- 1:
- /* Save the address of the FPU context, if any. */
- push pucPortTaskFPUContextBuffer
-
- .endif /* configSUPPORT_FPU */
-
- /* Find the TCB. */
- movl pxCurrentTCB, %eax
-
- /* Stack location is first item in the TCB. */
- movl %esp, (%eax)
-
- /* Switch stacks. */
- movl ulTopOfSystemStack, %esp
- movl %esp, %ebp
-
- /* Increment nesting count. */
- add $1, ulInterruptNesting
-
- call xTaskIncrementTick
-
- sti
-
- /* Is a switch to another task required? */
- test %eax, %eax
- je _skip_context_switch
- cli
- call vTaskSwitchContext
-
-_skip_context_switch:
- cli
-
- /* Decrement the variable used to determine if a switch to a system
- stack is necessary. */
- sub $1, ulInterruptNesting
-
- /* Stack location is first item in the TCB. */
- movl pxCurrentTCB, %eax
- movl (%eax), %esp
-
- .if configSUPPORT_FPU == 1
-
- /* Restore address of task's FPU context buffer. */
- pop pucPortTaskFPUContextBuffer
-
- /* If the task has a buffer allocated in which its FPU context is saved,
- then restore it now. */
- movl pucPortTaskFPUContextBuffer, %eax
- test %eax, %eax
- je 1f
- frstor ( %eax )
- 1:
- .endif
-
- popa
-
- /* EOI. */
- movl $0x00, (0xFEE000B0)
- iret
-
-.endfunc
-/*-----------------------------------------------------------*/
-
-.if configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1
-
- .align 4
- .func vPortCentralInterruptWrapper
- vPortCentralInterruptWrapper:
-
- portFREERTOS_INTERRUPT_ENTRY
-
- movl $0xFEE00170, %eax /* Highest In Service Register (ISR) long word. */
- movl $8, %ecx /* Loop counter. */
-
- next_isr_long_word:
- test %ecx, %ecx /* Loop counter reached 0? */
- je wrapper_epilogue /* Looked at all ISR registers without finding a bit set. */
- sub $1, %ecx /* Sub 1 from loop counter. */
- movl (%eax), %ebx /* Load next ISR long word. */
- sub $0x10, %eax /* Point to next ISR long word in case no bits are set in the current long word. */
- test %ebx, %ebx /* Are there any bits set? */
- je next_isr_long_word /* Look at next ISR long word if no bits were set. */
- sti
- bsr %ebx, %ebx /* A bit was set, which one? */
- movl $32, %eax /* Destination operand for following multiplication. */
- mul %ecx /* Calculate base vector for current register, 32 vectors per register. */
- add %ebx, %eax /* Add bit offset into register to get final vector number. */
- push %eax /* Vector number is function parameter. */
- call vPortCentralInterruptHandler
- pop %eax /* Remove parameter. */
-
- wrapper_epilogue:
- portFREERTOS_INTERRUPT_EXIT
-
- .endfunc
-
-.endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */
-/*-----------------------------------------------------------*/
-
-.align 4
-.func vPortAPISpuriousHandler
-vPortAPICSpuriousHandler:
- iret
-
-.endfunc
-
-.end
-
-
-
-
-
-
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+.file "portASM.S"
+#include "FreeRTOSConfig.h"
+#include "ISR_Support.h"
+
+ .extern pxCurrentTCB
+ .extern vTaskSwitchContext
+ .extern vPortCentralInterruptHandler
+ .extern xTaskIncrementTick
+ .extern vPortAPICErrorHandler
+ .extern pucPortTaskFPUContextBuffer
+ .extern ulPortYieldPending
+
+ .global vPortStartFirstTask
+ .global vPortCentralInterruptWrapper
+ .global vPortAPICErrorHandlerWrapper
+ .global vPortTimerHandler
+ .global vPortYieldCall
+ .global vPortAPICSpuriousHandler
+
+ .text
+
+/*-----------------------------------------------------------*/
+
+.align 4
+.func vPortYieldCall
+vPortYieldCall:
+ /* Save general purpose registers. */
+ pusha
+
+ .if configSUPPORT_FPU == 1
+
+ /* If the task has a buffer allocated to save the FPU context then save
+ the FPU context now. */
+ movl pucPortTaskFPUContextBuffer, %eax
+ test %eax, %eax
+ je 1f
+ fnsave ( %eax )
+ fwait
+
+ 1:
+
+ /* Save the address of the FPU context, if any. */
+ push pucPortTaskFPUContextBuffer
+
+ .endif /* configSUPPORT_FPU */
+
+ /* Find the TCB. */
+ movl pxCurrentTCB, %eax
+
+ /* Stack location is first item in the TCB. */
+ movl %esp, (%eax)
+
+ call vTaskSwitchContext
+
+ /* Find the location of pxCurrentTCB again - a callee saved register could
+ be used in place of eax to prevent this second load, but that then relies
+ on the compiler and other asm code. */
+ movl pxCurrentTCB, %eax
+ movl (%eax), %esp
+
+ .if configSUPPORT_FPU == 1
+
+ /* Restore address of task's FPU context buffer. */
+ pop pucPortTaskFPUContextBuffer
+
+ /* If the task has a buffer allocated in which its FPU context is saved,
+ then restore it now. */
+ movl pucPortTaskFPUContextBuffer, %eax
+ test %eax, %eax
+ je 1f
+ frstor ( %eax )
+ 1:
+ .endif
+
+ popa
+ iret
+
+.endfunc
+/*-----------------------------------------------------------*/
+
+.align 4
+.func vPortStartFirstTask
+vPortStartFirstTask:
+
+ /* Find the TCB. */
+ movl pxCurrentTCB, %eax
+
+ /* Stack location is first item in the TCB. */
+ movl (%eax), %esp
+
+ /* Restore FPU context flag. */
+ .if configSUPPORT_FPU == 1
+
+ pop pucPortTaskFPUContextBuffer
+
+ .endif /* configSUPPORT_FPU */
+
+ /* Restore general purpose registers. */
+ popa
+ iret
+.endfunc
+/*-----------------------------------------------------------*/
+
+.align 4
+.func vPortAPICErrorHandlerWrapper
+vPortAPICErrorHandlerWrapper:
+ pusha
+ call vPortAPICErrorHandler
+ popa
+ /* EOI. */
+ movl $0x00, (0xFEE000B0)
+ iret
+.endfunc
+/*-----------------------------------------------------------*/
+
+.align 4
+.func vPortTimerHandler
+vPortTimerHandler:
+
+ /* Save general purpose registers. */
+ pusha
+
+ /* Interrupts are not nested, so save the rest of the task context. */
+ .if configSUPPORT_FPU == 1
+
+ /* If the task has a buffer allocated to save the FPU context then save the
+ FPU context now. */
+ movl pucPortTaskFPUContextBuffer, %eax
+ test %eax, %eax
+ je 1f
+ fnsave ( %eax ) /* Save FLOP context into ucTempFPUBuffer array. */
+ fwait
+
+ 1:
+ /* Save the address of the FPU context, if any. */
+ push pucPortTaskFPUContextBuffer
+
+ .endif /* configSUPPORT_FPU */
+
+ /* Find the TCB. */
+ movl pxCurrentTCB, %eax
+
+ /* Stack location is first item in the TCB. */
+ movl %esp, (%eax)
+
+ /* Switch stacks. */
+ movl ulTopOfSystemStack, %esp
+ movl %esp, %ebp
+
+ /* Increment nesting count. */
+ add $1, ulInterruptNesting
+
+ call xTaskIncrementTick
+
+ sti
+
+ /* Is a switch to another task required? */
+ test %eax, %eax
+ je _skip_context_switch
+ cli
+ call vTaskSwitchContext
+
+_skip_context_switch:
+ cli
+
+ /* Decrement the variable used to determine if a switch to a system
+ stack is necessary. */
+ sub $1, ulInterruptNesting
+
+ /* Stack location is first item in the TCB. */
+ movl pxCurrentTCB, %eax
+ movl (%eax), %esp
+
+ .if configSUPPORT_FPU == 1
+
+ /* Restore address of task's FPU context buffer. */
+ pop pucPortTaskFPUContextBuffer
+
+ /* If the task has a buffer allocated in which its FPU context is saved,
+ then restore it now. */
+ movl pucPortTaskFPUContextBuffer, %eax
+ test %eax, %eax
+ je 1f
+ frstor ( %eax )
+ 1:
+ .endif
+
+ popa
+
+ /* EOI. */
+ movl $0x00, (0xFEE000B0)
+ iret
+
+.endfunc
+/*-----------------------------------------------------------*/
+
+.if configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1
+
+ .align 4
+ .func vPortCentralInterruptWrapper
+ vPortCentralInterruptWrapper:
+
+ portFREERTOS_INTERRUPT_ENTRY
+
+ movl $0xFEE00170, %eax /* Highest In Service Register (ISR) long word. */
+ movl $8, %ecx /* Loop counter. */
+
+ next_isr_long_word:
+ test %ecx, %ecx /* Loop counter reached 0? */
+ je wrapper_epilogue /* Looked at all ISR registers without finding a bit set. */
+ sub $1, %ecx /* Sub 1 from loop counter. */
+ movl (%eax), %ebx /* Load next ISR long word. */
+ sub $0x10, %eax /* Point to next ISR long word in case no bits are set in the current long word. */
+ test %ebx, %ebx /* Are there any bits set? */
+ je next_isr_long_word /* Look at next ISR long word if no bits were set. */
+ sti
+ bsr %ebx, %ebx /* A bit was set, which one? */
+ movl $32, %eax /* Destination operand for following multiplication. */
+ mul %ecx /* Calculate base vector for current register, 32 vectors per register. */
+ add %ebx, %eax /* Add bit offset into register to get final vector number. */
+ push %eax /* Vector number is function parameter. */
+ call vPortCentralInterruptHandler
+ pop %eax /* Remove parameter. */
+
+ wrapper_epilogue:
+ portFREERTOS_INTERRUPT_EXIT
+
+ .endfunc
+
+.endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */
+/*-----------------------------------------------------------*/
+
+.align 4
+.func vPortAPISpuriousHandler
+vPortAPICSpuriousHandler:
+ iret
+
+.endfunc
+
+.end
diff --git a/portable/GCC/IA32_flat/portmacro.h b/portable/GCC/IA32_flat/portmacro.h
index 7809fd7..060eb4d 100644
--- a/portable/GCC/IA32_flat/portmacro.h
+++ b/portable/GCC/IA32_flat/portmacro.h
@@ -1,292 +1,291 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT short
-#define portSTACK_TYPE uint32_t
-#define portBASE_TYPE long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-typedef uint32_t TickType_t;
-#define portMAX_DELAY ( ( TickType_t ) 0xffffffffUL )
-
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portSTACK_GROWTH ( -1 )
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT 32
-
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-
-/* The interrupt priority (for vectors 16 to 255) is determined using vector/16.
-The quotient is rounded to the nearest integer with 1 being the lowest priority
-and 15 is the highest. Therefore the following two interrupts are at the lowest
-priority. *NOTE 1* If the yield vector is changed then it must also be changed
-in the portYIELD_INTERRUPT definition immediately below. */
-#define portAPIC_TIMER_INT_VECTOR ( 0x21 )
-#define portAPIC_YIELD_INT_VECTOR ( 0x20 )
-
-/* Build yield interrupt instruction. */
-#define portYIELD_INTERRUPT "int $0x20"
-
-/* APIC register addresses. */
-#define portAPIC_EOI ( *( ( volatile uint32_t * ) 0xFEE000B0UL ) )
-
-/* APIC bit definitions. */
-#define portAPIC_ENABLE_BIT ( 1UL << 8UL )
-#define portAPIC_TIMER_PERIODIC ( 1UL << 17UL )
-#define portAPIC_DISABLE ( 1UL << 16UL )
-#define portAPIC_NMI ( 4 << 8)
-#define portAPIC_DIV_16 ( 0x03 )
-
-/* Define local API register addresses. */
-#define portAPIC_ID_REGISTER ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x20UL ) ) )
-#define portAPIC_SPURIOUS_INT ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0xF0UL ) ) )
-#define portAPIC_LVT_TIMER ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x320UL ) ) )
-#define portAPIC_TIMER_INITIAL_COUNT ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x380UL ) ) )
-#define portAPIC_TIMER_CURRENT_COUNT ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x390UL ) ) )
-#define portAPIC_TASK_PRIORITY ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x80UL ) ) )
-#define portAPIC_LVT_ERROR ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x370UL ) ) )
-#define portAPIC_ERROR_STATUS ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x280UL ) ) )
-#define portAPIC_LDR ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0xD0UL ) ) )
-#define portAPIC_TMRDIV ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x3E0UL ) ) )
-#define portAPIC_LVT_PERF ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x340UL ) ) )
-#define portAPIC_LVT_LINT0 ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x350UL ) ) )
-#define portAPIC_LVT_LINT1 ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x360UL ) ) )
-
-/* Don't yield if inside a critical section - instead hold the yield pending
-so it is performed when the critical section is exited. */
-#define portYIELD() \
-{ \
-extern volatile uint32_t ulCriticalNesting; \
-extern volatile uint32_t ulPortYieldPending; \
- if( ulCriticalNesting != 0 ) \
- { \
- ulPortYieldPending = pdTRUE; \
- } \
- else \
- { \
- __asm volatile( portYIELD_INTERRUPT ); \
- } \
-}
-
-/* Called at the end of an ISR that can cause a context switch - pend a yield if
-xSwithcRequired is not false. */
-#define portEND_SWITCHING_ISR( xSwitchRequired ) \
-{ \
-extern volatile uint32_t ulPortYieldPending; \
- if( xSwitchRequired != pdFALSE ) \
- { \
- ulPortYieldPending = 1; \
- } \
-}
-
-/* Same as portEND_SWITCHING_ISR() - take your pick which name to use. */
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-
-/*-----------------------------------------------------------
- * Critical section control
- *----------------------------------------------------------*/
-
-/* Critical sections for use in interrupts. */
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask( x )
-
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-extern uint32_t ulPortSetInterruptMask( void );
-extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
-
-/* These macros do not globally disable/enable interrupts. They do mask off
-interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
-#define portENTER_CRITICAL() vPortEnterCritical()
-#define portEXIT_CRITICAL() vPortExitCritical()
-#define portDISABLE_INTERRUPTS() __asm volatile( "cli" )
-#define portENABLE_INTERRUPTS() __asm volatile( "sti" )
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. These are
-not required for this port but included in case common demo code that uses these
-macros is used. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-/* Architecture specific optimisations. */
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
- /* Store/clear the ready priorities in a bit map. */
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) \
- __asm volatile( "bsr %1, %0\n\t" \
- :"=r"(uxTopPriority) : "rm"(uxReadyPriorities) : "cc" )
-
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-#define portNOP() __asm volatile( "NOP" )
-
-/*-----------------------------------------------------------
- * Misc
- *----------------------------------------------------------*/
-
-#define portNUM_VECTORS 256
-#define portMAX_PRIORITY 15
-typedef void ( *ISR_Handler_t ) ( void );
-
-/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
-before any floating point instructions are executed. */
-#ifndef configSUPPORT_FPU
- #define configSUPPORT_FPU 0
-#endif
-
-#if configSUPPORT_FPU == 1
- void vPortTaskUsesFPU( void );
- #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
-#endif
-
-/* See the comments under the configUSE_COMMON_INTERRUPT_ENTRY_POINT definition
-below. */
-BaseType_t xPortRegisterCInterruptHandler( ISR_Handler_t pxHandler, uint32_t ulVectorNumber );
-BaseType_t xPortInstallInterruptHandler( ISR_Handler_t pxHandler, uint32_t ulVectorNumber );
-
-#ifndef configAPIC_BASE
- /* configAPIC_BASE_ADDRESS sets the base address of the local APIC. It can
- be overridden in FreeRTOSConfig.h should it not be constant. */
- #define configAPIC_BASE 0xFEE00000UL
-#endif
-
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
- /* The FreeRTOS scheduling algorithm selects the task that will enter the
- Running state. configUSE_PORT_OPTIMISED_TASK_SELECTION is used to set how
- that is done.
-
- If configUSE_PORT_OPTIMISED_TASK_SELECTION is set to 0 then the task to
- enter the Running state is selected using a portable algorithm written in
- C. This is the slowest method, but the algorithm does not restrict the
- maximum number of unique RTOS task priorities that are available.
-
- If configUSE_PORT_OPTIMISED_TASK_SELECTION is set to 1 then the task to
- enter the Running state is selected using a single assembly instruction.
- This is the fastest method, but restricts the maximum number of unique RTOS
- task priorities to 32 (the same task priority can be assigned to any number
- of RTOS tasks). */
- #warning configUSE_PORT_OPTIMISED_TASK_SELECTION was not defined in FreeRTOSConfig.h and has been defaulted to 1
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-#endif
-
-#ifndef configUSE_COMMON_INTERRUPT_ENTRY_POINT
- /* There are two ways of implementing interrupt handlers:
-
- 1) As standard C functions -
-
- This method can only be used if configUSE_COMMON_INTERRUPT_ENTRY_POINT
- is set to 1. The C function is installed using
- xPortRegisterCInterruptHandler().
-
- This is the simplest of the two methods but incurs a slightly longer
- interrupt entry time.
-
- 2) By using an assembly stub that wraps the handler in the FreeRTOS
- portFREERTOS_INTERRUPT_ENTRY and portFREERTOS_INTERRUPT_EXIT macros.
-
- This method can always be used. It is slightly more complex than
- method 1 but benefits from a faster interrupt entry time. */
- #warning configUSE_COMMON_INTERRUPT_ENTRY_POINT was not defined in FreeRTOSConfig.h and has been defaulted to 1.
- #define configUSE_COMMON_INTERRUPT_ENTRY_POINT 1
-#endif
-
-#ifndef configISR_STACK_SIZE
- /* Interrupt entry code will switch the stack in use to a dedicated system
- stack.
-
- configISR_STACK_SIZE defines the number of 32-bit values that can be stored
- on the system stack, and must be large enough to hold a potentially nested
- interrupt stack frame. */
-
- #error configISR_STACK_SIZE was not defined in FreeRTOSConfig.h.
-#endif
-
-#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
- /* Interrupt safe FreeRTOS functions (those that end in "FromISR" must not
- be called from an interrupt that has a priority above that set by
- configMAX_API_CALL_INTERRUPT_PRIORITY. */
- #warning configMAX_API_CALL_INTERRUPT_PRIORITY was not defined in FreeRTOSConfig.h and has been defaulted to 10
- #define configMAX_API_CALL_INTERRUPT_PRIORITY 10
-#endif
-
-#ifndef configSUPPORT_FPU
- #warning configSUPPORT_FPU was not defined in FreeRTOSConfig.h and has been defaulted to 0
- #define configSUPPORT_FPU 0
-#endif
-
-/* The value written to the task priority register to raise the interrupt mask
-to the maximum from which FreeRTOS API calls can be made. */
-#define portAPIC_PRIORITY_SHIFT ( 4UL )
-#define portAPIC_MAX_SUB_PRIORITY ( 0x0fUL )
-#define portMAX_API_CALL_PRIORITY ( ( configMAX_API_CALL_INTERRUPT_PRIORITY << portAPIC_PRIORITY_SHIFT ) | portAPIC_MAX_SUB_PRIORITY )
-
-/* Asserts if interrupt safe FreeRTOS functions are called from a priority
-above the max system call interrupt priority. */
-#define portAPIC_PROCESSOR_PRIORITY ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0xA0UL ) ) )
-#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( portAPIC_PROCESSOR_PRIORITY ) <= ( portMAX_API_CALL_PRIORITY ) )
-
-#ifdef __cplusplus
- } /* extern C */
-#endif
-
-#endif /* PORTMACRO_H */
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+typedef uint32_t TickType_t;
+#define portMAX_DELAY ( ( TickType_t ) 0xffffffffUL )
+
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 32
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+/* The interrupt priority (for vectors 16 to 255) is determined using vector/16.
+The quotient is rounded to the nearest integer with 1 being the lowest priority
+and 15 is the highest. Therefore the following two interrupts are at the lowest
+priority. *NOTE 1* If the yield vector is changed then it must also be changed
+in the portYIELD_INTERRUPT definition immediately below. */
+#define portAPIC_TIMER_INT_VECTOR ( 0x21 )
+#define portAPIC_YIELD_INT_VECTOR ( 0x20 )
+
+/* Build yield interrupt instruction. */
+#define portYIELD_INTERRUPT "int $0x20"
+
+/* APIC register addresses. */
+#define portAPIC_EOI ( *( ( volatile uint32_t * ) 0xFEE000B0UL ) )
+
+/* APIC bit definitions. */
+#define portAPIC_ENABLE_BIT ( 1UL << 8UL )
+#define portAPIC_TIMER_PERIODIC ( 1UL << 17UL )
+#define portAPIC_DISABLE ( 1UL << 16UL )
+#define portAPIC_NMI ( 4 << 8)
+#define portAPIC_DIV_16 ( 0x03 )
+
+/* Define local API register addresses. */
+#define portAPIC_ID_REGISTER ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x20UL ) ) )
+#define portAPIC_SPURIOUS_INT ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0xF0UL ) ) )
+#define portAPIC_LVT_TIMER ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x320UL ) ) )
+#define portAPIC_TIMER_INITIAL_COUNT ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x380UL ) ) )
+#define portAPIC_TIMER_CURRENT_COUNT ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x390UL ) ) )
+#define portAPIC_TASK_PRIORITY ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x80UL ) ) )
+#define portAPIC_LVT_ERROR ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x370UL ) ) )
+#define portAPIC_ERROR_STATUS ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x280UL ) ) )
+#define portAPIC_LDR ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0xD0UL ) ) )
+#define portAPIC_TMRDIV ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x3E0UL ) ) )
+#define portAPIC_LVT_PERF ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x340UL ) ) )
+#define portAPIC_LVT_LINT0 ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x350UL ) ) )
+#define portAPIC_LVT_LINT1 ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x360UL ) ) )
+
+/* Don't yield if inside a critical section - instead hold the yield pending
+so it is performed when the critical section is exited. */
+#define portYIELD() \
+{ \
+extern volatile uint32_t ulCriticalNesting; \
+extern volatile uint32_t ulPortYieldPending; \
+ if( ulCriticalNesting != 0 ) \
+ { \
+ ulPortYieldPending = pdTRUE; \
+ } \
+ else \
+ { \
+ __asm volatile( portYIELD_INTERRUPT ); \
+ } \
+}
+
+/* Called at the end of an ISR that can cause a context switch - pend a yield if
+xSwithcRequired is not false. */
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+{ \
+extern volatile uint32_t ulPortYieldPending; \
+ if( xSwitchRequired != pdFALSE ) \
+ { \
+ ulPortYieldPending = 1; \
+ } \
+}
+
+/* Same as portEND_SWITCHING_ISR() - take your pick which name to use. */
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+
+/*-----------------------------------------------------------
+ * Critical section control
+ *----------------------------------------------------------*/
+
+/* Critical sections for use in interrupts. */
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask( x )
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+extern uint32_t ulPortSetInterruptMask( void );
+extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
+
+/* These macros do not globally disable/enable interrupts. They do mask off
+interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
+#define portDISABLE_INTERRUPTS() __asm volatile( "cli" )
+#define portENABLE_INTERRUPTS() __asm volatile( "sti" )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. These are
+not required for this port but included in case common demo code that uses these
+macros is used. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+/* Architecture specific optimisations. */
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+ /* Store/clear the ready priorities in a bit map. */
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) \
+ __asm volatile( "bsr %1, %0\n\t" \
+ :"=r"(uxTopPriority) : "rm"(uxReadyPriorities) : "cc" )
+
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+#define portNOP() __asm volatile( "NOP" )
+
+/*-----------------------------------------------------------
+ * Misc
+ *----------------------------------------------------------*/
+
+#define portNUM_VECTORS 256
+#define portMAX_PRIORITY 15
+typedef void ( *ISR_Handler_t ) ( void );
+
+/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
+before any floating point instructions are executed. */
+#ifndef configSUPPORT_FPU
+ #define configSUPPORT_FPU 0
+#endif
+
+#if configSUPPORT_FPU == 1
+ void vPortTaskUsesFPU( void );
+ #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+#endif
+
+/* See the comments under the configUSE_COMMON_INTERRUPT_ENTRY_POINT definition
+below. */
+BaseType_t xPortRegisterCInterruptHandler( ISR_Handler_t pxHandler, uint32_t ulVectorNumber );
+BaseType_t xPortInstallInterruptHandler( ISR_Handler_t pxHandler, uint32_t ulVectorNumber );
+
+#ifndef configAPIC_BASE
+ /* configAPIC_BASE_ADDRESS sets the base address of the local APIC. It can
+ be overridden in FreeRTOSConfig.h should it not be constant. */
+ #define configAPIC_BASE 0xFEE00000UL
+#endif
+
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ /* The FreeRTOS scheduling algorithm selects the task that will enter the
+ Running state. configUSE_PORT_OPTIMISED_TASK_SELECTION is used to set how
+ that is done.
+
+ If configUSE_PORT_OPTIMISED_TASK_SELECTION is set to 0 then the task to
+ enter the Running state is selected using a portable algorithm written in
+ C. This is the slowest method, but the algorithm does not restrict the
+ maximum number of unique RTOS task priorities that are available.
+
+ If configUSE_PORT_OPTIMISED_TASK_SELECTION is set to 1 then the task to
+ enter the Running state is selected using a single assembly instruction.
+ This is the fastest method, but restricts the maximum number of unique RTOS
+ task priorities to 32 (the same task priority can be assigned to any number
+ of RTOS tasks). */
+ #warning configUSE_PORT_OPTIMISED_TASK_SELECTION was not defined in FreeRTOSConfig.h and has been defaulted to 1
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#ifndef configUSE_COMMON_INTERRUPT_ENTRY_POINT
+ /* There are two ways of implementing interrupt handlers:
+
+ 1) As standard C functions -
+
+ This method can only be used if configUSE_COMMON_INTERRUPT_ENTRY_POINT
+ is set to 1. The C function is installed using
+ xPortRegisterCInterruptHandler().
+
+ This is the simplest of the two methods but incurs a slightly longer
+ interrupt entry time.
+
+ 2) By using an assembly stub that wraps the handler in the FreeRTOS
+ portFREERTOS_INTERRUPT_ENTRY and portFREERTOS_INTERRUPT_EXIT macros.
+
+ This method can always be used. It is slightly more complex than
+ method 1 but benefits from a faster interrupt entry time. */
+ #warning configUSE_COMMON_INTERRUPT_ENTRY_POINT was not defined in FreeRTOSConfig.h and has been defaulted to 1.
+ #define configUSE_COMMON_INTERRUPT_ENTRY_POINT 1
+#endif
+
+#ifndef configISR_STACK_SIZE
+ /* Interrupt entry code will switch the stack in use to a dedicated system
+ stack.
+
+ configISR_STACK_SIZE defines the number of 32-bit values that can be stored
+ on the system stack, and must be large enough to hold a potentially nested
+ interrupt stack frame. */
+
+ #error configISR_STACK_SIZE was not defined in FreeRTOSConfig.h.
+#endif
+
+#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
+ /* Interrupt safe FreeRTOS functions (those that end in "FromISR" must not
+ be called from an interrupt that has a priority above that set by
+ configMAX_API_CALL_INTERRUPT_PRIORITY. */
+ #warning configMAX_API_CALL_INTERRUPT_PRIORITY was not defined in FreeRTOSConfig.h and has been defaulted to 10
+ #define configMAX_API_CALL_INTERRUPT_PRIORITY 10
+#endif
+
+#ifndef configSUPPORT_FPU
+ #warning configSUPPORT_FPU was not defined in FreeRTOSConfig.h and has been defaulted to 0
+ #define configSUPPORT_FPU 0
+#endif
+
+/* The value written to the task priority register to raise the interrupt mask
+to the maximum from which FreeRTOS API calls can be made. */
+#define portAPIC_PRIORITY_SHIFT ( 4UL )
+#define portAPIC_MAX_SUB_PRIORITY ( 0x0fUL )
+#define portMAX_API_CALL_PRIORITY ( ( configMAX_API_CALL_INTERRUPT_PRIORITY << portAPIC_PRIORITY_SHIFT ) | portAPIC_MAX_SUB_PRIORITY )
+
+/* Asserts if interrupt safe FreeRTOS functions are called from a priority
+above the max system call interrupt priority. */
+#define portAPIC_PROCESSOR_PRIORITY ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0xA0UL ) ) )
+#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( portAPIC_PROCESSOR_PRIORITY ) <= ( portMAX_API_CALL_PRIORITY ) )
+
+#ifdef __cplusplus
+ } /* extern C */
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/portable/GCC/MSP430F449/port.c b/portable/GCC/MSP430F449/port.c
index c8dd45a..ca5d0c5 100644
--- a/portable/GCC/MSP430F449/port.c
+++ b/portable/GCC/MSP430F449/port.c
@@ -1,329 +1,329 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*
- Changes from V2.5.2
-
- + usCriticalNesting now has a volatile qualifier.
-*/
-
-/* Standard includes. */
-#include <stdlib.h>
-#include <signal.h>
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the MSP430 port.
- *----------------------------------------------------------*/
-
-/* Constants required for hardware setup. The tick ISR runs off the ACLK,
-not the MCLK. */
-#define portACLK_FREQUENCY_HZ ( ( TickType_t ) 32768 )
-#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 )
-#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x08 )
-
-/* We require the address of the pxCurrentTCB variable, but don't want to know
-any details of its type. */
-typedef void TCB_t;
-extern volatile TCB_t * volatile pxCurrentTCB;
-
-/* Most ports implement critical sections by placing the interrupt flags on
-the stack before disabling interrupts. Exiting the critical section is then
-simply a case of popping the flags from the stack. As mspgcc does not use
-a frame pointer this cannot be done as modifying the stack will clobber all
-the stack variables. Instead each task maintains a count of the critical
-section nesting depth. Each time a critical section is entered the count is
-incremented. Each time a critical section is left the count is decremented -
-with interrupts only being re-enabled if the count is zero.
-
-usCriticalNesting will get set to zero when the scheduler starts, but must
-not be initialised to zero as this will cause problems during the startup
-sequence. */
-volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
-/*-----------------------------------------------------------*/
-
-/*
- * Macro to save a task context to the task stack. This simply pushes all the
- * general purpose msp430 registers onto the stack, followed by the
- * usCriticalNesting value used by the task. Finally the resultant stack
- * pointer value is saved into the task control block so it can be retrieved
- * the next time the task executes.
- */
-#define portSAVE_CONTEXT() \
- asm volatile ( "push r4 \n\t" \
- "push r5 \n\t" \
- "push r6 \n\t" \
- "push r7 \n\t" \
- "push r8 \n\t" \
- "push r9 \n\t" \
- "push r10 \n\t" \
- "push r11 \n\t" \
- "push r12 \n\t" \
- "push r13 \n\t" \
- "push r14 \n\t" \
- "push r15 \n\t" \
- "mov.w usCriticalNesting, r14 \n\t" \
- "push r14 \n\t" \
- "mov.w pxCurrentTCB, r12 \n\t" \
- "mov.w r1, @r12 \n\t" \
- );
-
-/*
- * Macro to restore a task context from the task stack. This is effectively
- * the reverse of portSAVE_CONTEXT(). First the stack pointer value is
- * loaded from the task control block. Next the value for usCriticalNesting
- * used by the task is retrieved from the stack - followed by the value of all
- * the general purpose msp430 registers.
- *
- * The bic instruction ensures there are no low power bits set in the status
- * register that is about to be popped from the stack.
- */
-#define portRESTORE_CONTEXT() \
- asm volatile ( "mov.w pxCurrentTCB, r12 \n\t" \
- "mov.w @r12, r1 \n\t" \
- "pop r15 \n\t" \
- "mov.w r15, usCriticalNesting \n\t" \
- "pop r15 \n\t" \
- "pop r14 \n\t" \
- "pop r13 \n\t" \
- "pop r12 \n\t" \
- "pop r11 \n\t" \
- "pop r10 \n\t" \
- "pop r9 \n\t" \
- "pop r8 \n\t" \
- "pop r7 \n\t" \
- "pop r6 \n\t" \
- "pop r5 \n\t" \
- "pop r4 \n\t" \
- "bic #(0xf0),0(r1) \n\t" \
- "reti \n\t" \
- );
-/*-----------------------------------------------------------*/
-
-/*
- * Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but
- * could have alternatively used the watchdog timer or timer 1.
- */
-static void prvSetupTimerInterrupt( void );
-/*-----------------------------------------------------------*/
-
-/*
- * Initialise the stack of a task to look exactly as if a call to
- * portSAVE_CONTEXT had been called.
- *
- * See the header file portable.h.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
- /*
- Place a few bytes of known values on the bottom of the stack.
- This is just useful for debugging and can be included if required.
-
- *pxTopOfStack = ( StackType_t ) 0x1111;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x2222;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x3333;
- pxTopOfStack--;
- */
-
- /* The msp430 automatically pushes the PC then SR onto the stack before
- executing an ISR. We want the stack to look just as if this has happened
- so place a pointer to the start of the task on the stack first - followed
- by the flags we want the task to use when it starts up. */
- *pxTopOfStack = ( StackType_t ) pxCode;
- pxTopOfStack--;
- *pxTopOfStack = portFLAGS_INT_ENABLED;
- pxTopOfStack--;
-
- /* Next the general purpose registers. */
- *pxTopOfStack = ( StackType_t ) 0x4444;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x5555;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x6666;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x7777;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x8888;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x9999;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xaaaa;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xbbbb;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xcccc;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xdddd;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0xeeee;
- pxTopOfStack--;
-
- /* When the task starts is will expect to find the function parameter in
- R15. */
- *pxTopOfStack = ( StackType_t ) pvParameters;
- pxTopOfStack--;
-
- /* The code generated by the mspgcc compiler does not maintain separate
- stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
- use the stack as per other ports. Instead a variable is used to keep
- track of the critical section nesting. This variable has to be stored
- as part of the task context and is initially set to zero. */
- *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
-
- /* Return a pointer to the top of the stack we have generated so this can
- be stored in the task control block for the task. */
- return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
- /* Setup the hardware to generate the tick. Interrupts are disabled when
- this function is called. */
- prvSetupTimerInterrupt();
-
- /* Restore the context of the first task that is going to run. */
- portRESTORE_CONTEXT();
-
- /* Should not get here as the tasks are now running! */
- return pdTRUE;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
- /* It is unlikely that the MSP430 port will get stopped. If required simply
- disable the tick interrupt here. */
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Manual context switch called by portYIELD or taskYIELD.
- *
- * The first thing we do is save the registers so we can use a naked attribute.
- */
-void vPortYield( void ) __attribute__ ( ( naked ) );
-void vPortYield( void )
-{
- /* We want the stack of the task being saved to look exactly as if the task
- was saved during a pre-emptive RTOS tick ISR. Before calling an ISR the
- msp430 places the status register onto the stack. As this is a function
- call and not an ISR we have to do this manually. */
- asm volatile ( "push r2" );
- _DINT();
-
- /* Save the context of the current task. */
- portSAVE_CONTEXT();
-
- /* Switch to the highest priority task that is ready to run. */
- vTaskSwitchContext();
-
- /* Restore the context of the new task. */
- portRESTORE_CONTEXT();
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Hardware initialisation to generate the RTOS tick. This uses timer 0
- * but could alternatively use the watchdog timer or timer 1.
- */
-static void prvSetupTimerInterrupt( void )
-{
- /* Ensure the timer is stopped. */
- TACTL = 0;
-
- /* Run the timer of the ACLK. */
- TACTL = TASSEL_1;
-
- /* Clear everything to start with. */
- TACTL |= TACLR;
-
- /* Set the compare match value according to the tick rate we want. */
- TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ;
-
- /* Enable the interrupts. */
- TACCTL0 = CCIE;
-
- /* Start up clean. */
- TACTL |= TACLR;
-
- /* Up mode. */
- TACTL |= MC_1;
-}
-/*-----------------------------------------------------------*/
-
-/*
- * The interrupt service routine used depends on whether the pre-emptive
- * scheduler is being used or not.
- */
-
-#if configUSE_PREEMPTION == 1
-
- /*
- * Tick ISR for preemptive scheduler. We can use a naked attribute as
- * the context is saved at the start of vPortYieldFromTick(). The tick
- * count is incremented after the context is saved.
- */
- interrupt (TIMERA0_VECTOR) prvTickISR( void ) __attribute__ ( ( naked ) );
- interrupt (TIMERA0_VECTOR) prvTickISR( void )
- {
- /* Save the context of the interrupted task. */
- portSAVE_CONTEXT();
-
- /* Increment the tick count then switch to the highest priority task
- that is ready to run. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- vTaskSwitchContext();
- }
-
- /* Restore the context of the new task. */
- portRESTORE_CONTEXT();
- }
-
-#else
-
- /*
- * Tick ISR for the cooperative scheduler. All this does is increment the
- * tick count. We don't need to switch context, this can only be done by
- * manual calls to taskYIELD();
- */
- interrupt (TIMERA0_VECTOR) prvTickISR( void );
- interrupt (TIMERA0_VECTOR) prvTickISR( void )
- {
- xTaskIncrementTick();
- }
-#endif
-
-
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*
+ Changes from V2.5.2
+
+ + usCriticalNesting now has a volatile qualifier.
+*/
+
+/* Standard includes. */
+#include <stdlib.h>
+#include <signal.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the MSP430 port.
+ *----------------------------------------------------------*/
+
+/* Constants required for hardware setup. The tick ISR runs off the ACLK,
+not the MCLK. */
+#define portACLK_FREQUENCY_HZ ( ( TickType_t ) 32768 )
+#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 )
+#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x08 )
+
+/* We require the address of the pxCurrentTCB variable, but don't want to know
+any details of its type. */
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+
+/* Most ports implement critical sections by placing the interrupt flags on
+the stack before disabling interrupts. Exiting the critical section is then
+simply a case of popping the flags from the stack. As mspgcc does not use
+a frame pointer this cannot be done as modifying the stack will clobber all
+the stack variables. Instead each task maintains a count of the critical
+section nesting depth. Each time a critical section is entered the count is
+incremented. Each time a critical section is left the count is decremented -
+with interrupts only being re-enabled if the count is zero.
+
+usCriticalNesting will get set to zero when the scheduler starts, but must
+not be initialised to zero as this will cause problems during the startup
+sequence. */
+volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
+/*-----------------------------------------------------------*/
+
+/*
+ * Macro to save a task context to the task stack. This simply pushes all the
+ * general purpose msp430 registers onto the stack, followed by the
+ * usCriticalNesting value used by the task. Finally the resultant stack
+ * pointer value is saved into the task control block so it can be retrieved
+ * the next time the task executes.
+ */
+#define portSAVE_CONTEXT() \
+ asm volatile ( "push r4 \n\t" \
+ "push r5 \n\t" \
+ "push r6 \n\t" \
+ "push r7 \n\t" \
+ "push r8 \n\t" \
+ "push r9 \n\t" \
+ "push r10 \n\t" \
+ "push r11 \n\t" \
+ "push r12 \n\t" \
+ "push r13 \n\t" \
+ "push r14 \n\t" \
+ "push r15 \n\t" \
+ "mov.w usCriticalNesting, r14 \n\t" \
+ "push r14 \n\t" \
+ "mov.w pxCurrentTCB, r12 \n\t" \
+ "mov.w r1, @r12 \n\t" \
+ );
+
+/*
+ * Macro to restore a task context from the task stack. This is effectively
+ * the reverse of portSAVE_CONTEXT(). First the stack pointer value is
+ * loaded from the task control block. Next the value for usCriticalNesting
+ * used by the task is retrieved from the stack - followed by the value of all
+ * the general purpose msp430 registers.
+ *
+ * The bic instruction ensures there are no low power bits set in the status
+ * register that is about to be popped from the stack.
+ */
+#define portRESTORE_CONTEXT() \
+ asm volatile ( "mov.w pxCurrentTCB, r12 \n\t" \
+ "mov.w @r12, r1 \n\t" \
+ "pop r15 \n\t" \
+ "mov.w r15, usCriticalNesting \n\t" \
+ "pop r15 \n\t" \
+ "pop r14 \n\t" \
+ "pop r13 \n\t" \
+ "pop r12 \n\t" \
+ "pop r11 \n\t" \
+ "pop r10 \n\t" \
+ "pop r9 \n\t" \
+ "pop r8 \n\t" \
+ "pop r7 \n\t" \
+ "pop r6 \n\t" \
+ "pop r5 \n\t" \
+ "pop r4 \n\t" \
+ "bic #(0xf0),0(r1) \n\t" \
+ "reti \n\t" \
+ );
+/*-----------------------------------------------------------*/
+
+/*
+ * Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but
+ * could have alternatively used the watchdog timer or timer 1.
+ */
+static void prvSetupTimerInterrupt( void );
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been called.
+ *
+ * See the header file portable.h.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+ /*
+ Place a few bytes of known values on the bottom of the stack.
+ This is just useful for debugging and can be included if required.
+
+ *pxTopOfStack = ( StackType_t ) 0x1111;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x2222;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x3333;
+ pxTopOfStack--;
+ */
+
+ /* The msp430 automatically pushes the PC then SR onto the stack before
+ executing an ISR. We want the stack to look just as if this has happened
+ so place a pointer to the start of the task on the stack first - followed
+ by the flags we want the task to use when it starts up. */
+ *pxTopOfStack = ( StackType_t ) pxCode;
+ pxTopOfStack--;
+ *pxTopOfStack = portFLAGS_INT_ENABLED;
+ pxTopOfStack--;
+
+ /* Next the general purpose registers. */
+ *pxTopOfStack = ( StackType_t ) 0x4444;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x5555;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x6666;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x7777;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x8888;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x9999;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xaaaa;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xbbbb;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xcccc;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xdddd;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0xeeee;
+ pxTopOfStack--;
+
+ /* When the task starts is will expect to find the function parameter in
+ R15. */
+ *pxTopOfStack = ( StackType_t ) pvParameters;
+ pxTopOfStack--;
+
+ /* The code generated by the mspgcc compiler does not maintain separate
+ stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
+ use the stack as per other ports. Instead a variable is used to keep
+ track of the critical section nesting. This variable has to be stored
+ as part of the task context and is initially set to zero. */
+ *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
+
+ /* Return a pointer to the top of the stack we have generated so this can
+ be stored in the task control block for the task. */
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+ /* Setup the hardware to generate the tick. Interrupts are disabled when
+ this function is called. */
+ prvSetupTimerInterrupt();
+
+ /* Restore the context of the first task that is going to run. */
+ portRESTORE_CONTEXT();
+
+ /* Should not get here as the tasks are now running! */
+ return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+ /* It is unlikely that the MSP430 port will get stopped. If required simply
+ disable the tick interrupt here. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch called by portYIELD or taskYIELD.
+ *
+ * The first thing we do is save the registers so we can use a naked attribute.
+ */
+void vPortYield( void ) __attribute__ ( ( naked ) );
+void vPortYield( void )
+{
+ /* We want the stack of the task being saved to look exactly as if the task
+ was saved during a pre-emptive RTOS tick ISR. Before calling an ISR the
+ msp430 places the status register onto the stack. As this is a function
+ call and not an ISR we have to do this manually. */
+ asm volatile ( "push r2" );
+ _DINT();
+
+ /* Save the context of the current task. */
+ portSAVE_CONTEXT();
+
+ /* Switch to the highest priority task that is ready to run. */
+ vTaskSwitchContext();
+
+ /* Restore the context of the new task. */
+ portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Hardware initialisation to generate the RTOS tick. This uses timer 0
+ * but could alternatively use the watchdog timer or timer 1.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+ /* Ensure the timer is stopped. */
+ TACTL = 0;
+
+ /* Run the timer of the ACLK. */
+ TACTL = TASSEL_1;
+
+ /* Clear everything to start with. */
+ TACTL |= TACLR;
+
+ /* Set the compare match value according to the tick rate we want. */
+ TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ;
+
+ /* Enable the interrupts. */
+ TACCTL0 = CCIE;
+
+ /* Start up clean. */
+ TACTL |= TACLR;
+
+ /* Up mode. */
+ TACTL |= MC_1;
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * The interrupt service routine used depends on whether the pre-emptive
+ * scheduler is being used or not.
+ */
+
+#if configUSE_PREEMPTION == 1
+
+ /*
+ * Tick ISR for preemptive scheduler. We can use a naked attribute as
+ * the context is saved at the start of vPortYieldFromTick(). The tick
+ * count is incremented after the context is saved.
+ */
+ interrupt (TIMERA0_VECTOR) prvTickISR( void ) __attribute__ ( ( naked ) );
+ interrupt (TIMERA0_VECTOR) prvTickISR( void )
+ {
+ /* Save the context of the interrupted task. */
+ portSAVE_CONTEXT();
+
+ /* Increment the tick count then switch to the highest priority task
+ that is ready to run. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ vTaskSwitchContext();
+ }
+
+ /* Restore the context of the new task. */
+ portRESTORE_CONTEXT();
+ }
+
+#else
+
+ /*
+ * Tick ISR for the cooperative scheduler. All this does is increment the
+ * tick count. We don't need to switch context, this can only be done by
+ * manual calls to taskYIELD();
+ */
+ interrupt (TIMERA0_VECTOR) prvTickISR( void );
+ interrupt (TIMERA0_VECTOR) prvTickISR( void )
+ {
+ xTaskIncrementTick();
+ }
+#endif
+
+
+
diff --git a/portable/GCC/MSP430F449/portmacro.h b/portable/GCC/MSP430F449/portmacro.h
index cc90128..149de12 100644
--- a/portable/GCC/MSP430F449/portmacro.h
+++ b/portable/GCC/MSP430F449/portmacro.h
@@ -1,128 +1,127 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT int
-#define portSTACK_TYPE uint16_t
-#define portBASE_TYPE short
-
-typedef portSTACK_TYPE StackType_t;
-typedef short BaseType_t;
-typedef unsigned short UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
-#else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Interrupt control macros. */
-#define portDISABLE_INTERRUPTS() asm volatile ( "DINT" ); asm volatile ( "NOP" )
-#define portENABLE_INTERRUPTS() asm volatile ( "EINT" ); asm volatile ( "NOP" )
-/*-----------------------------------------------------------*/
-
-/* Critical section control macros. */
-#define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 )
-
-#define portENTER_CRITICAL() \
-{ \
-extern volatile uint16_t usCriticalNesting; \
- \
- portDISABLE_INTERRUPTS(); \
- \
- /* Now interrupts are disabled ulCriticalNesting can be accessed */ \
- /* directly. Increment ulCriticalNesting to keep a count of how many */ \
- /* times portENTER_CRITICAL() has been called. */ \
- usCriticalNesting++; \
-}
-
-#define portEXIT_CRITICAL() \
-{ \
-extern volatile uint16_t usCriticalNesting; \
- \
- if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \
- { \
- /* Decrement the nesting count as we are leaving a critical section. */ \
- usCriticalNesting--; \
- \
- /* If the nesting level has reached zero then interrupts should be */ \
- /* re-enabled. */ \
- if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \
- { \
- portENABLE_INTERRUPTS(); \
- } \
- } \
-}
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-extern void vPortYield( void ) __attribute__ ( ( naked ) );
-#define portYIELD() vPortYield()
-#define portNOP() asm volatile ( "NOP" )
-/*-----------------------------------------------------------*/
-
-/* Hardwware specifics. */
-#define portBYTE_ALIGNMENT 2
-#define portSTACK_GROWTH ( -1 )
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT int
+#define portSTACK_TYPE uint16_t
+#define portBASE_TYPE short
+
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Interrupt control macros. */
+#define portDISABLE_INTERRUPTS() asm volatile ( "DINT" ); asm volatile ( "NOP" )
+#define portENABLE_INTERRUPTS() asm volatile ( "EINT" ); asm volatile ( "NOP" )
+/*-----------------------------------------------------------*/
+
+/* Critical section control macros. */
+#define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 )
+
+#define portENTER_CRITICAL() \
+{ \
+extern volatile uint16_t usCriticalNesting; \
+ \
+ portDISABLE_INTERRUPTS(); \
+ \
+ /* Now interrupts are disabled ulCriticalNesting can be accessed */ \
+ /* directly. Increment ulCriticalNesting to keep a count of how many */ \
+ /* times portENTER_CRITICAL() has been called. */ \
+ usCriticalNesting++; \
+}
+
+#define portEXIT_CRITICAL() \
+{ \
+extern volatile uint16_t usCriticalNesting; \
+ \
+ if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \
+ { \
+ /* Decrement the nesting count as we are leaving a critical section. */ \
+ usCriticalNesting--; \
+ \
+ /* If the nesting level has reached zero then interrupts should be */ \
+ /* re-enabled. */ \
+ if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \
+ { \
+ portENABLE_INTERRUPTS(); \
+ } \
+ } \
+}
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+extern void vPortYield( void ) __attribute__ ( ( naked ) );
+#define portYIELD() vPortYield()
+#define portNOP() asm volatile ( "NOP" )
+/*-----------------------------------------------------------*/
+
+/* Hardwware specifics. */
+#define portBYTE_ALIGNMENT 2
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/portable/GCC/MicroBlaze/port.c b/portable/GCC/MicroBlaze/port.c
index b1df8fb..309b805 100644
--- a/portable/GCC/MicroBlaze/port.c
+++ b/portable/GCC/MicroBlaze/port.c
@@ -1,330 +1,330 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the MicroBlaze port.
- *----------------------------------------------------------*/
-
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Standard includes. */
-#include <string.h>
-
-/* Hardware includes. */
-#include <xintc.h>
-#include <xintc_i.h>
-#include <xtmrctr.h>
-
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
- #error configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 to use this port.
-#endif
-
-/* Tasks are started with interrupts enabled. */
-#define portINITIAL_MSR_STATE ( ( StackType_t ) 0x02 )
-
-/* Tasks are started with a critical section nesting of 0 - however prior
-to the scheduler being commenced we don't want the critical nesting level
-to reach zero, so it is initialised to a high value. */
-#define portINITIAL_NESTING_VALUE ( 0xff )
-
-/* Our hardware setup only uses one counter. */
-#define portCOUNTER_0 0
-
-/* The stack used by the ISR is filled with a known value to assist in
-debugging. */
-#define portISR_STACK_FILL_VALUE 0x55555555
-
-/* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task
-maintains it's own count, so this variable is saved as part of the task
-context. */
-volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE;
-
-/* To limit the amount of stack required by each task, this port uses a
-separate stack for interrupts. */
-uint32_t *pulISRStack;
-
-/*-----------------------------------------------------------*/
-
-/*
- * Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but
- * could have alternatively used the watchdog timer or timer 1.
- */
-static void prvSetupTimerInterrupt( void );
-/*-----------------------------------------------------------*/
-
-/*
- * Initialise the stack of a task to look exactly as if a call to
- * portSAVE_CONTEXT had been made.
- *
- * See the header file portable.h.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-extern void * _SDA2_BASE_;
-extern void * _SDA_BASE_;
-const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
-const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
-
- /* Place a few bytes of known values on the bottom of the stack.
- This is essential for the Microblaze port and these lines must
- not be omitted. The parameter value will overwrite the
- 0x22222222 value during the function prologue. */
- *pxTopOfStack = ( StackType_t ) 0x11111111;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x22222222;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x33333333;
- pxTopOfStack--;
-
- /* First stack an initial value for the critical section nesting. This
- is initialised to zero as tasks are started with interrupts enabled. */
- *pxTopOfStack = ( StackType_t ) 0x00; /* R0. */
-
- /* Place an initial value for all the general purpose registers. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) ulR2; /* R2 - small data area. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03; /* R3. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04; /* R4. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pvParameters;/* R5 contains the function call parameters. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06; /* R6. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07; /* R7. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08; /* R8. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09; /* R9. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x0a; /* R10. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x0b; /* R11. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x0c; /* R12. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) ulR13; /* R13 - small data read write area. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode; /* R14. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x0f; /* R15. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10; /* R16. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11; /* R17. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12; /* R18. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x13; /* R19. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x14; /* R20. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x15; /* R21. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x16; /* R22. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x17; /* R23. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x18; /* R24. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x19; /* R25. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x1a; /* R26. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x1b; /* R27. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x1c; /* R28. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x1d; /* R29. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x1e; /* R30. */
- pxTopOfStack--;
-
- /* The MSR is stacked between R30 and R31. */
- *pxTopOfStack = portINITIAL_MSR_STATE;
- pxTopOfStack--;
-
- *pxTopOfStack = ( StackType_t ) 0x1f; /* R31. */
- pxTopOfStack--;
-
- /* Return a pointer to the top of the stack we have generated so this can
- be stored in the task control block for the task. */
- return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-extern void ( __FreeRTOS_interrupt_Handler )( void );
-extern void ( vStartFirstTask )( void );
-
-
- /* Setup the FreeRTOS interrupt handler. Code copied from crt0.s. */
- asm volatile ( "la r6, r0, __FreeRTOS_interrupt_handler \n\t" \
- "sw r6, r1, r0 \n\t" \
- "lhu r7, r1, r0 \n\t" \
- "shi r7, r0, 0x12 \n\t" \
- "shi r6, r0, 0x16 " );
-
- /* Setup the hardware to generate the tick. Interrupts are disabled when
- this function is called. */
- prvSetupTimerInterrupt();
-
- /* Allocate the stack to be used by the interrupt handler. */
- pulISRStack = ( uint32_t * ) pvPortMalloc( configMINIMAL_STACK_SIZE * sizeof( StackType_t ) );
-
- /* Restore the context of the first task that is going to run. */
- if( pulISRStack != NULL )
- {
- /* Fill the ISR stack with a known value to facilitate debugging. */
- memset( pulISRStack, portISR_STACK_FILL_VALUE, configMINIMAL_STACK_SIZE * sizeof( StackType_t ) );
- pulISRStack += ( configMINIMAL_STACK_SIZE - 1 );
-
- /* Kick off the first task. */
- vStartFirstTask();
- }
-
- /* Should not get here as the tasks are now running! */
- return pdFALSE;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
- /* Not implemented. */
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Manual context switch called by portYIELD or taskYIELD.
- */
-void vPortYield( void )
-{
-extern void VPortYieldASM( void );
-
- /* Perform the context switch in a critical section to assure it is
- not interrupted by the tick ISR. It is not a problem to do this as
- each task maintains it's own interrupt status. */
- portENTER_CRITICAL();
- /* Jump directly to the yield function to ensure there is no
- compiler generated prologue code. */
- asm volatile ( "bralid r14, VPortYieldASM \n\t" \
- "or r0, r0, r0 \n\t" );
- portEXIT_CRITICAL();
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Hardware initialisation to generate the RTOS tick.
- */
-static void prvSetupTimerInterrupt( void )
-{
-XTmrCtr xTimer;
-const uint32_t ulCounterValue = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
-UBaseType_t uxMask;
-
- /* The OPB timer1 is used to generate the tick. Use the provided library
- functions to enable the timer and set the tick frequency. */
- XTmrCtr_mDisable( XPAR_OPB_TIMER_1_BASEADDR, XPAR_OPB_TIMER_1_DEVICE_ID );
- XTmrCtr_Initialize( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID );
- XTmrCtr_mSetLoadReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCounterValue );
- XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_LOAD_MASK | XTC_CSR_INT_OCCURED_MASK );
-
- /* Set the timer interrupt enable bit while maintaining the other bit
- states. */
- uxMask = XIntc_In32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ) );
- uxMask |= XPAR_OPB_TIMER_1_INTERRUPT_MASK;
- XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( uxMask ) );
-
- XTmrCtr_Start( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID );
- XTmrCtr_mSetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK | XTC_CSR_INT_OCCURED_MASK );
- XIntc_mAckIntr( XPAR_INTC_SINGLE_BASEADDR, 1 );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * The interrupt handler placed in the interrupt vector when the scheduler is
- * started. The task context has already been saved when this is called.
- * This handler determines the interrupt source and calls the relevant
- * peripheral handler.
- */
-void vTaskISRHandler( void )
-{
-static uint32_t ulPending;
-
- /* Which interrupts are pending? */
- ulPending = XIntc_In32( ( XPAR_INTC_SINGLE_BASEADDR + XIN_IVR_OFFSET ) );
-
- if( ulPending < XPAR_INTC_MAX_NUM_INTR_INPUTS )
- {
- static XIntc_VectorTableEntry *pxTablePtr;
- static XIntc_Config *pxConfig;
- static uint32_t ulInterruptMask;
-
- ulInterruptMask = ( uint32_t ) 1 << ulPending;
-
- /* Get the configuration data using the device ID */
- pxConfig = &XIntc_ConfigTable[ ( uint32_t ) XPAR_INTC_SINGLE_DEVICE_ID ];
-
- pxTablePtr = &( pxConfig->HandlerTable[ ulPending ] );
- if( pxConfig->AckBeforeService & ( ulInterruptMask ) )
- {
- XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask );
- pxTablePtr->Handler( pxTablePtr->CallBackRef );
- }
- else
- {
- pxTablePtr->Handler( pxTablePtr->CallBackRef );
- XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask );
- }
- }
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Handler for the timer interrupt.
- */
-void vTickISR( void *pvBaseAddress )
-{
-uint32_t ulCSR;
-
- /* Increment the RTOS tick - this might cause a task to unblock. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- vTaskSwitchContext();
- }
-
- /* Clear the timer interrupt */
- ulCSR = XTmrCtr_mGetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, 0);
- XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCSR );
-}
-/*-----------------------------------------------------------*/
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the MicroBlaze port.
+ *----------------------------------------------------------*/
+
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Standard includes. */
+#include <string.h>
+
+/* Hardware includes. */
+#include <xintc.h>
+#include <xintc_i.h>
+#include <xtmrctr.h>
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
+ #error configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 to use this port.
+#endif
+
+/* Tasks are started with interrupts enabled. */
+#define portINITIAL_MSR_STATE ( ( StackType_t ) 0x02 )
+
+/* Tasks are started with a critical section nesting of 0 - however prior
+to the scheduler being commenced we don't want the critical nesting level
+to reach zero, so it is initialised to a high value. */
+#define portINITIAL_NESTING_VALUE ( 0xff )
+
+/* Our hardware setup only uses one counter. */
+#define portCOUNTER_0 0
+
+/* The stack used by the ISR is filled with a known value to assist in
+debugging. */
+#define portISR_STACK_FILL_VALUE 0x55555555
+
+/* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task
+maintains it's own count, so this variable is saved as part of the task
+context. */
+volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE;
+
+/* To limit the amount of stack required by each task, this port uses a
+separate stack for interrupts. */
+uint32_t *pulISRStack;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but
+ * could have alternatively used the watchdog timer or timer 1.
+ */
+static void prvSetupTimerInterrupt( void );
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been made.
+ *
+ * See the header file portable.h.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+extern void * _SDA2_BASE_;
+extern void * _SDA_BASE_;
+const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
+const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
+
+ /* Place a few bytes of known values on the bottom of the stack.
+ This is essential for the Microblaze port and these lines must
+ not be omitted. The parameter value will overwrite the
+ 0x22222222 value during the function prologue. */
+ *pxTopOfStack = ( StackType_t ) 0x11111111;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x22222222;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x33333333;
+ pxTopOfStack--;
+
+ /* First stack an initial value for the critical section nesting. This
+ is initialised to zero as tasks are started with interrupts enabled. */
+ *pxTopOfStack = ( StackType_t ) 0x00; /* R0. */
+
+ /* Place an initial value for all the general purpose registers. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) ulR2; /* R2 - small data area. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03; /* R3. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04; /* R4. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters;/* R5 contains the function call parameters. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06; /* R6. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07; /* R7. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08; /* R8. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09; /* R9. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x0a; /* R10. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x0b; /* R11. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x0c; /* R12. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) ulR13; /* R13 - small data read write area. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* R14. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x0f; /* R15. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10; /* R16. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11; /* R17. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12; /* R18. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x13; /* R19. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x14; /* R20. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x15; /* R21. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x16; /* R22. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x17; /* R23. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x18; /* R24. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x19; /* R25. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x1a; /* R26. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x1b; /* R27. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x1c; /* R28. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x1d; /* R29. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x1e; /* R30. */
+ pxTopOfStack--;
+
+ /* The MSR is stacked between R30 and R31. */
+ *pxTopOfStack = portINITIAL_MSR_STATE;
+ pxTopOfStack--;
+
+ *pxTopOfStack = ( StackType_t ) 0x1f; /* R31. */
+ pxTopOfStack--;
+
+ /* Return a pointer to the top of the stack we have generated so this can
+ be stored in the task control block for the task. */
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void ( __FreeRTOS_interrupt_Handler )( void );
+extern void ( vStartFirstTask )( void );
+
+
+ /* Setup the FreeRTOS interrupt handler. Code copied from crt0.s. */
+ asm volatile ( "la r6, r0, __FreeRTOS_interrupt_handler \n\t" \
+ "sw r6, r1, r0 \n\t" \
+ "lhu r7, r1, r0 \n\t" \
+ "shi r7, r0, 0x12 \n\t" \
+ "shi r6, r0, 0x16 " );
+
+ /* Setup the hardware to generate the tick. Interrupts are disabled when
+ this function is called. */
+ prvSetupTimerInterrupt();
+
+ /* Allocate the stack to be used by the interrupt handler. */
+ pulISRStack = ( uint32_t * ) pvPortMalloc( configMINIMAL_STACK_SIZE * sizeof( StackType_t ) );
+
+ /* Restore the context of the first task that is going to run. */
+ if( pulISRStack != NULL )
+ {
+ /* Fill the ISR stack with a known value to facilitate debugging. */
+ memset( pulISRStack, portISR_STACK_FILL_VALUE, configMINIMAL_STACK_SIZE * sizeof( StackType_t ) );
+ pulISRStack += ( configMINIMAL_STACK_SIZE - 1 );
+
+ /* Kick off the first task. */
+ vStartFirstTask();
+ }
+
+ /* Should not get here as the tasks are now running! */
+ return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+ /* Not implemented. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch called by portYIELD or taskYIELD.
+ */
+void vPortYield( void )
+{
+extern void VPortYieldASM( void );
+
+ /* Perform the context switch in a critical section to assure it is
+ not interrupted by the tick ISR. It is not a problem to do this as
+ each task maintains it's own interrupt status. */
+ portENTER_CRITICAL();
+ /* Jump directly to the yield function to ensure there is no
+ compiler generated prologue code. */
+ asm volatile ( "bralid r14, VPortYieldASM \n\t" \
+ "or r0, r0, r0 \n\t" );
+ portEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Hardware initialisation to generate the RTOS tick.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+XTmrCtr xTimer;
+const uint32_t ulCounterValue = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+UBaseType_t uxMask;
+
+ /* The OPB timer1 is used to generate the tick. Use the provided library
+ functions to enable the timer and set the tick frequency. */
+ XTmrCtr_mDisable( XPAR_OPB_TIMER_1_BASEADDR, XPAR_OPB_TIMER_1_DEVICE_ID );
+ XTmrCtr_Initialize( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID );
+ XTmrCtr_mSetLoadReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCounterValue );
+ XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_LOAD_MASK | XTC_CSR_INT_OCCURED_MASK );
+
+ /* Set the timer interrupt enable bit while maintaining the other bit
+ states. */
+ uxMask = XIntc_In32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ) );
+ uxMask |= XPAR_OPB_TIMER_1_INTERRUPT_MASK;
+ XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( uxMask ) );
+
+ XTmrCtr_Start( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID );
+ XTmrCtr_mSetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK | XTC_CSR_INT_OCCURED_MASK );
+ XIntc_mAckIntr( XPAR_INTC_SINGLE_BASEADDR, 1 );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * The interrupt handler placed in the interrupt vector when the scheduler is
+ * started. The task context has already been saved when this is called.
+ * This handler determines the interrupt source and calls the relevant
+ * peripheral handler.
+ */
+void vTaskISRHandler( void )
+{
+static uint32_t ulPending;
+
+ /* Which interrupts are pending? */
+ ulPending = XIntc_In32( ( XPAR_INTC_SINGLE_BASEADDR + XIN_IVR_OFFSET ) );
+
+ if( ulPending < XPAR_INTC_MAX_NUM_INTR_INPUTS )
+ {
+ static XIntc_VectorTableEntry *pxTablePtr;
+ static XIntc_Config *pxConfig;
+ static uint32_t ulInterruptMask;
+
+ ulInterruptMask = ( uint32_t ) 1 << ulPending;
+
+ /* Get the configuration data using the device ID */
+ pxConfig = &XIntc_ConfigTable[ ( uint32_t ) XPAR_INTC_SINGLE_DEVICE_ID ];
+
+ pxTablePtr = &( pxConfig->HandlerTable[ ulPending ] );
+ if( pxConfig->AckBeforeService & ( ulInterruptMask ) )
+ {
+ XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask );
+ pxTablePtr->Handler( pxTablePtr->CallBackRef );
+ }
+ else
+ {
+ pxTablePtr->Handler( pxTablePtr->CallBackRef );
+ XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask );
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Handler for the timer interrupt.
+ */
+void vTickISR( void *pvBaseAddress )
+{
+uint32_t ulCSR;
+
+ /* Increment the RTOS tick - this might cause a task to unblock. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ vTaskSwitchContext();
+ }
+
+ /* Clear the timer interrupt */
+ ulCSR = XTmrCtr_mGetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, 0);
+ XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCSR );
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/MicroBlaze/portasm.s b/portable/GCC/MicroBlaze/portasm.s
index 6fd995f..3449148 100644
--- a/portable/GCC/MicroBlaze/portasm.s
+++ b/portable/GCC/MicroBlaze/portasm.s
@@ -1,198 +1,194 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
- .extern pxCurrentTCB
- .extern vTaskISRHandler
- .extern vTaskSwitchContext
- .extern uxCriticalNesting
- .extern pulISRStack
-
- .global __FreeRTOS_interrupt_handler
- .global VPortYieldASM
- .global vStartFirstTask
-
-
-.macro portSAVE_CONTEXT
- /* Make room for the context on the stack. */
- addik r1, r1, -132
- /* Save r31 so it can then be used. */
- swi r31, r1, 4
- /* Copy the msr into r31 - this is stacked later. */
- mfs r31, rmsr
- /* Stack general registers. */
- swi r30, r1, 12
- swi r29, r1, 16
- swi r28, r1, 20
- swi r27, r1, 24
- swi r26, r1, 28
- swi r25, r1, 32
- swi r24, r1, 36
- swi r23, r1, 40
- swi r22, r1, 44
- swi r21, r1, 48
- swi r20, r1, 52
- swi r19, r1, 56
- swi r18, r1, 60
- swi r17, r1, 64
- swi r16, r1, 68
- swi r15, r1, 72
- swi r13, r1, 80
- swi r12, r1, 84
- swi r11, r1, 88
- swi r10, r1, 92
- swi r9, r1, 96
- swi r8, r1, 100
- swi r7, r1, 104
- swi r6, r1, 108
- swi r5, r1, 112
- swi r4, r1, 116
- swi r3, r1, 120
- swi r2, r1, 124
- /* Stack the critical section nesting value. */
- lwi r3, r0, uxCriticalNesting
- swi r3, r1, 128
- /* Save the top of stack value to the TCB. */
- lwi r3, r0, pxCurrentTCB
- sw r1, r0, r3
-
- .endm
-
-.macro portRESTORE_CONTEXT
- /* Load the top of stack value from the TCB. */
- lwi r3, r0, pxCurrentTCB
- lw r1, r0, r3
- /* Restore the general registers. */
- lwi r31, r1, 4
- lwi r30, r1, 12
- lwi r29, r1, 16
- lwi r28, r1, 20
- lwi r27, r1, 24
- lwi r26, r1, 28
- lwi r25, r1, 32
- lwi r24, r1, 36
- lwi r23, r1, 40
- lwi r22, r1, 44
- lwi r21, r1, 48
- lwi r20, r1, 52
- lwi r19, r1, 56
- lwi r18, r1, 60
- lwi r17, r1, 64
- lwi r16, r1, 68
- lwi r15, r1, 72
- lwi r14, r1, 76
- lwi r13, r1, 80
- lwi r12, r1, 84
- lwi r11, r1, 88
- lwi r10, r1, 92
- lwi r9, r1, 96
- lwi r8, r1, 100
- lwi r7, r1, 104
- lwi r6, r1, 108
- lwi r5, r1, 112
- lwi r4, r1, 116
- lwi r2, r1, 124
-
- /* Load the critical nesting value. */
- lwi r3, r1, 128
- swi r3, r0, uxCriticalNesting
-
- /* Obtain the MSR value from the stack. */
- lwi r3, r1, 8
-
- /* Are interrupts enabled in the MSR? If so return using an return from
- interrupt instruction to ensure interrupts are enabled only once the task
- is running again. */
- andi r3, r3, 2
- beqid r3, 36
- or r0, r0, r0
-
- /* Reload the rmsr from the stack, clear the enable interrupt bit in the
- value before saving back to rmsr register, then return enabling interrupts
- as we return. */
- lwi r3, r1, 8
- andi r3, r3, ~2
- mts rmsr, r3
- lwi r3, r1, 120
- addik r1, r1, 132
- rtid r14, 0
- or r0, r0, r0
-
- /* Reload the rmsr from the stack, place it in the rmsr register, and
- return without enabling interrupts. */
- lwi r3, r1, 8
- mts rmsr, r3
- lwi r3, r1, 120
- addik r1, r1, 132
- rtsd r14, 0
- or r0, r0, r0
-
- .endm
-
- .text
- .align 2
-
-
-__FreeRTOS_interrupt_handler:
- portSAVE_CONTEXT
- /* Entered via an interrupt so interrupts must be enabled in msr. */
- ori r31, r31, 2
- /* Stack msr. */
- swi r31, r1, 8
- /* Stack the return address. As we entered via an interrupt we do
- not need to modify the return address prior to stacking. */
- swi r14, r1, 76
- /* Now switch to use the ISR stack. */
- lwi r3, r0, pulISRStack
- add r1, r3, r0
- bralid r15, vTaskISRHandler
- or r0, r0, r0
- portRESTORE_CONTEXT
-
-
-VPortYieldASM:
- portSAVE_CONTEXT
- /* Stack msr. */
- swi r31, r1, 8
- /* Modify the return address so we return to the instruction after the
- exception. */
- addi r14, r14, 8
- swi r14, r1, 76
- /* Now switch to use the ISR stack. */
- lwi r3, r0, pulISRStack
- add r1, r3, r0
- bralid r15, vTaskSwitchContext
- or r0, r0, r0
- portRESTORE_CONTEXT
-
-vStartFirstTask:
- portRESTORE_CONTEXT
-
-
-
-
-
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+ .extern pxCurrentTCB
+ .extern vTaskISRHandler
+ .extern vTaskSwitchContext
+ .extern uxCriticalNesting
+ .extern pulISRStack
+
+ .global __FreeRTOS_interrupt_handler
+ .global VPortYieldASM
+ .global vStartFirstTask
+
+
+.macro portSAVE_CONTEXT
+ /* Make room for the context on the stack. */
+ addik r1, r1, -132
+ /* Save r31 so it can then be used. */
+ swi r31, r1, 4
+ /* Copy the msr into r31 - this is stacked later. */
+ mfs r31, rmsr
+ /* Stack general registers. */
+ swi r30, r1, 12
+ swi r29, r1, 16
+ swi r28, r1, 20
+ swi r27, r1, 24
+ swi r26, r1, 28
+ swi r25, r1, 32
+ swi r24, r1, 36
+ swi r23, r1, 40
+ swi r22, r1, 44
+ swi r21, r1, 48
+ swi r20, r1, 52
+ swi r19, r1, 56
+ swi r18, r1, 60
+ swi r17, r1, 64
+ swi r16, r1, 68
+ swi r15, r1, 72
+ swi r13, r1, 80
+ swi r12, r1, 84
+ swi r11, r1, 88
+ swi r10, r1, 92
+ swi r9, r1, 96
+ swi r8, r1, 100
+ swi r7, r1, 104
+ swi r6, r1, 108
+ swi r5, r1, 112
+ swi r4, r1, 116
+ swi r3, r1, 120
+ swi r2, r1, 124
+ /* Stack the critical section nesting value. */
+ lwi r3, r0, uxCriticalNesting
+ swi r3, r1, 128
+ /* Save the top of stack value to the TCB. */
+ lwi r3, r0, pxCurrentTCB
+ sw r1, r0, r3
+
+ .endm
+
+.macro portRESTORE_CONTEXT
+ /* Load the top of stack value from the TCB. */
+ lwi r3, r0, pxCurrentTCB
+ lw r1, r0, r3
+ /* Restore the general registers. */
+ lwi r31, r1, 4
+ lwi r30, r1, 12
+ lwi r29, r1, 16
+ lwi r28, r1, 20
+ lwi r27, r1, 24
+ lwi r26, r1, 28
+ lwi r25, r1, 32
+ lwi r24, r1, 36
+ lwi r23, r1, 40
+ lwi r22, r1, 44
+ lwi r21, r1, 48
+ lwi r20, r1, 52
+ lwi r19, r1, 56
+ lwi r18, r1, 60
+ lwi r17, r1, 64
+ lwi r16, r1, 68
+ lwi r15, r1, 72
+ lwi r14, r1, 76
+ lwi r13, r1, 80
+ lwi r12, r1, 84
+ lwi r11, r1, 88
+ lwi r10, r1, 92
+ lwi r9, r1, 96
+ lwi r8, r1, 100
+ lwi r7, r1, 104
+ lwi r6, r1, 108
+ lwi r5, r1, 112
+ lwi r4, r1, 116
+ lwi r2, r1, 124
+
+ /* Load the critical nesting value. */
+ lwi r3, r1, 128
+ swi r3, r0, uxCriticalNesting
+
+ /* Obtain the MSR value from the stack. */
+ lwi r3, r1, 8
+
+ /* Are interrupts enabled in the MSR? If so return using an return from
+ interrupt instruction to ensure interrupts are enabled only once the task
+ is running again. */
+ andi r3, r3, 2
+ beqid r3, 36
+ or r0, r0, r0
+
+ /* Reload the rmsr from the stack, clear the enable interrupt bit in the
+ value before saving back to rmsr register, then return enabling interrupts
+ as we return. */
+ lwi r3, r1, 8
+ andi r3, r3, ~2
+ mts rmsr, r3
+ lwi r3, r1, 120
+ addik r1, r1, 132
+ rtid r14, 0
+ or r0, r0, r0
+
+ /* Reload the rmsr from the stack, place it in the rmsr register, and
+ return without enabling interrupts. */
+ lwi r3, r1, 8
+ mts rmsr, r3
+ lwi r3, r1, 120
+ addik r1, r1, 132
+ rtsd r14, 0
+ or r0, r0, r0
+
+ .endm
+
+ .text
+ .align 2
+
+
+__FreeRTOS_interrupt_handler:
+ portSAVE_CONTEXT
+ /* Entered via an interrupt so interrupts must be enabled in msr. */
+ ori r31, r31, 2
+ /* Stack msr. */
+ swi r31, r1, 8
+ /* Stack the return address. As we entered via an interrupt we do
+ not need to modify the return address prior to stacking. */
+ swi r14, r1, 76
+ /* Now switch to use the ISR stack. */
+ lwi r3, r0, pulISRStack
+ add r1, r3, r0
+ bralid r15, vTaskISRHandler
+ or r0, r0, r0
+ portRESTORE_CONTEXT
+
+
+VPortYieldASM:
+ portSAVE_CONTEXT
+ /* Stack msr. */
+ swi r31, r1, 8
+ /* Modify the return address so we return to the instruction after the
+ exception. */
+ addi r14, r14, 8
+ swi r14, r1, 76
+ /* Now switch to use the ISR stack. */
+ lwi r3, r0, pulISRStack
+ add r1, r3, r0
+ bralid r15, vTaskSwitchContext
+ or r0, r0, r0
+ portRESTORE_CONTEXT
+
+vStartFirstTask:
+ portRESTORE_CONTEXT
+
+
diff --git a/portable/GCC/MicroBlaze/portmacro.h b/portable/GCC/MicroBlaze/portmacro.h
index 92459cd..5bc52ff 100644
--- a/portable/GCC/MicroBlaze/portmacro.h
+++ b/portable/GCC/MicroBlaze/portmacro.h
@@ -1,127 +1,126 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT short
-#define portSTACK_TYPE uint32_t
-#define portBASE_TYPE long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
-#else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
- /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Interrupt control macros. */
-void microblaze_disable_interrupts( void );
-void microblaze_enable_interrupts( void );
-#define portDISABLE_INTERRUPTS() microblaze_disable_interrupts()
-#define portENABLE_INTERRUPTS() microblaze_enable_interrupts()
-/*-----------------------------------------------------------*/
-
-/* Critical section macros. */
-void vPortEnterCritical( void );
-void vPortExitCritical( void );
-#define portENTER_CRITICAL() { \
- extern UBaseType_t uxCriticalNesting; \
- microblaze_disable_interrupts(); \
- uxCriticalNesting++; \
- }
-
-#define portEXIT_CRITICAL() { \
- extern UBaseType_t uxCriticalNesting; \
- /* Interrupts are disabled, so we can */ \
- /* access the variable directly. */ \
- uxCriticalNesting--; \
- if( uxCriticalNesting == 0 ) \
- { \
- /* The nesting has unwound and we \
- can enable interrupts again. */ \
- portENABLE_INTERRUPTS(); \
- } \
- }
-
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-void vPortYield( void );
-#define portYIELD() vPortYield()
-
-void vTaskSwitchContext();
-#define portYIELD_FROM_ISR() vTaskSwitchContext()
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portBYTE_ALIGNMENT 4
-#define portSTACK_GROWTH ( -1 )
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP() asm volatile ( "NOP" )
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Interrupt control macros. */
+void microblaze_disable_interrupts( void );
+void microblaze_enable_interrupts( void );
+#define portDISABLE_INTERRUPTS() microblaze_disable_interrupts()
+#define portENABLE_INTERRUPTS() microblaze_enable_interrupts()
+/*-----------------------------------------------------------*/
+
+/* Critical section macros. */
+void vPortEnterCritical( void );
+void vPortExitCritical( void );
+#define portENTER_CRITICAL() { \
+ extern UBaseType_t uxCriticalNesting; \
+ microblaze_disable_interrupts(); \
+ uxCriticalNesting++; \
+ }
+
+#define portEXIT_CRITICAL() { \
+ extern UBaseType_t uxCriticalNesting; \
+ /* Interrupts are disabled, so we can */ \
+ /* access the variable directly. */ \
+ uxCriticalNesting--; \
+ if( uxCriticalNesting == 0 ) \
+ { \
+ /* The nesting has unwound and we \
+ can enable interrupts again. */ \
+ portENABLE_INTERRUPTS(); \
+ } \
+ }
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+void vPortYield( void );
+#define portYIELD() vPortYield()
+
+void vTaskSwitchContext();
+#define portYIELD_FROM_ISR() vTaskSwitchContext()
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT 4
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP() asm volatile ( "NOP" )
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/portable/GCC/MicroBlazeV8/port.c b/portable/GCC/MicroBlazeV8/port.c
index 720c144..9285741 100644
--- a/portable/GCC/MicroBlazeV8/port.c
+++ b/portable/GCC/MicroBlazeV8/port.c
@@ -1,452 +1,452 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the MicroBlaze port.
- *----------------------------------------------------------*/
-
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Standard includes. */
-#include <string.h>
-
-/* Hardware includes. */
-#include <xintc_i.h>
-#include <xil_exception.h>
-#include <microblaze_exceptions_g.h>
-
-/* Tasks are started with a critical section nesting of 0 - however, prior to
-the scheduler being commenced interrupts should not be enabled, so the critical
-nesting variable is initialised to a non-zero value. */
-#define portINITIAL_NESTING_VALUE ( 0xff )
-
-/* The bit within the MSR register that enabled/disables interrupts and
-exceptions respectively. */
-#define portMSR_IE ( 0x02U )
-#define portMSR_EE ( 0x100U )
-
-/* If the floating point unit is included in the MicroBlaze build, then the
-FSR register is saved as part of the task context. portINITIAL_FSR is the value
-given to the FSR register when the initial context is set up for a task being
-created. */
-#define portINITIAL_FSR ( 0U )
-/*-----------------------------------------------------------*/
-
-/*
- * Initialise the interrupt controller instance.
- */
-static int32_t prvInitialiseInterruptController( void );
-
-/* Ensure the interrupt controller instance variable is initialised before it is
- * used, and that the initialisation only happens once.
- */
-static int32_t prvEnsureInterruptControllerIsInitialised( void );
-
-/*-----------------------------------------------------------*/
-
-/* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task
-maintains its own count, so this variable is saved as part of the task
-context. */
-volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE;
-
-/* This port uses a separate stack for interrupts. This prevents the stack of
-every task needing to be large enough to hold an entire interrupt stack on top
-of the task stack. */
-uint32_t *pulISRStack;
-
-/* If an interrupt requests a context switch, then ulTaskSwitchRequested will
-get set to 1. ulTaskSwitchRequested is inspected just before the main interrupt
-handler exits. If, at that time, ulTaskSwitchRequested is set to 1, the kernel
-will call vTaskSwitchContext() to ensure the task that runs immediately after
-the interrupt exists is the highest priority task that is able to run. This is
-an unusual mechanism, but is used for this port because a single interrupt can
-cause the servicing of multiple peripherals - and it is inefficient to call
-vTaskSwitchContext() multiple times as each peripheral is serviced. */
-volatile uint32_t ulTaskSwitchRequested = 0UL;
-
-/* The instance of the interrupt controller used by this port. This is required
-by the Xilinx library API functions. */
-static XIntc xInterruptControllerInstance;
-
-/*-----------------------------------------------------------*/
-
-/*
- * Initialise the stack of a task to look exactly as if a call to
- * portSAVE_CONTEXT had been made.
- *
- * See the portable.h header file.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-extern void * _SDA2_BASE_;
-extern void * _SDA_BASE_;
-const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
-const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
-
- /* Place a few bytes of known values on the bottom of the stack.
- This is essential for the Microblaze port and these lines must
- not be omitted. */
- *pxTopOfStack = ( StackType_t ) 0x00000000;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x00000000;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x00000000;
- pxTopOfStack--;
-
- #if( XPAR_MICROBLAZE_USE_FPU != 0 )
- /* The FSR value placed in the initial task context is just 0. */
- *pxTopOfStack = portINITIAL_FSR;
- pxTopOfStack--;
- #endif
-
- /* The MSR value placed in the initial task context should have interrupts
- disabled. Each task will enable interrupts automatically when it enters
- the running state for the first time. */
- *pxTopOfStack = mfmsr() & ~portMSR_IE;
-
- #if( MICROBLAZE_EXCEPTIONS_ENABLED == 1 )
- {
- /* Ensure exceptions are enabled for the task. */
- *pxTopOfStack |= portMSR_EE;
- }
- #endif
-
- pxTopOfStack--;
-
- /* First stack an initial value for the critical section nesting. This
- is initialised to zero. */
- *pxTopOfStack = ( StackType_t ) 0x00;
-
- /* R0 is always zero. */
- /* R1 is the SP. */
-
- /* Place an initial value for all the general purpose registers. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) ulR2; /* R2 - read only small data area. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03; /* R3 - return values and temporaries. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04; /* R4 - return values and temporaries. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pvParameters;/* R5 contains the function call parameters. */
-
- #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06; /* R6 - other parameters and temporaries. Used as the return address from vPortTaskEntryPoint. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07; /* R7 - other parameters and temporaries. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08; /* R8 - other parameters and temporaries. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09; /* R9 - other parameters and temporaries. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x0a; /* R10 - other parameters and temporaries. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x0b; /* R11 - temporaries. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x0c; /* R12 - temporaries. */
- pxTopOfStack--;
- #else
- pxTopOfStack-= 8;
- #endif
-
- *pxTopOfStack = ( StackType_t ) ulR13; /* R13 - read/write small data area. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode; /* R14 - return address for interrupt. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) NULL; /* R15 - return address for subroutine. */
-
- #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10; /* R16 - return address for trap (debugger). */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11; /* R17 - return address for exceptions, if configured. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12; /* R18 - reserved for assembler and compiler temporaries. */
- pxTopOfStack--;
- #else
- pxTopOfStack -= 4;
- #endif
-
- *pxTopOfStack = ( StackType_t ) 0x00; /* R19 - must be saved across function calls. Callee-save. Seems to be interpreted as the frame pointer. */
-
- #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x14; /* R20 - reserved for storing a pointer to the Global Offset Table (GOT) in Position Independent Code (PIC). Non-volatile in non-PIC code. Must be saved across function calls. Callee-save. Not used by FreeRTOS. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x15; /* R21 - must be saved across function calls. Callee-save. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x16; /* R22 - must be saved across function calls. Callee-save. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x17; /* R23 - must be saved across function calls. Callee-save. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x18; /* R24 - must be saved across function calls. Callee-save. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x19; /* R25 - must be saved across function calls. Callee-save. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x1a; /* R26 - must be saved across function calls. Callee-save. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x1b; /* R27 - must be saved across function calls. Callee-save. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x1c; /* R28 - must be saved across function calls. Callee-save. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x1d; /* R29 - must be saved across function calls. Callee-save. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x1e; /* R30 - must be saved across function calls. Callee-save. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x1f; /* R31 - must be saved across function calls. Callee-save. */
- pxTopOfStack--;
- #else
- pxTopOfStack -= 13;
- #endif
-
- /* Return a pointer to the top of the stack that has been generated so this
- can be stored in the task control block for the task. */
- return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-extern void ( vPortStartFirstTask )( void );
-extern uint32_t _stack[];
-
- /* Setup the hardware to generate the tick. Interrupts are disabled when
- this function is called.
-
- This port uses an application defined callback function to install the tick
- interrupt handler because the kernel will run on lots of different
- MicroBlaze and FPGA configurations - not all of which will have the same
- timer peripherals defined or available. An example definition of
- vApplicationSetupTimerInterrupt() is provided in the official demo
- application that accompanies this port. */
- vApplicationSetupTimerInterrupt();
-
- /* Reuse the stack from main() as the stack for the interrupts/exceptions. */
- pulISRStack = ( uint32_t * ) _stack;
-
- /* Ensure there is enough space for the functions called from the interrupt
- service routines to write back into the stack frame of the caller. */
- pulISRStack -= 2;
-
- /* Restore the context of the first task that is going to run. From here
- on, the created tasks will be executing. */
- vPortStartFirstTask();
-
- /* Should not get here as the tasks are now running! */
- return pdFALSE;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
- /* Not implemented in ports where there is nothing to return to.
- Artificially force an assert. */
- configASSERT( uxCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Manual context switch called by portYIELD or taskYIELD.
- */
-void vPortYield( void )
-{
-extern void VPortYieldASM( void );
-
- /* Perform the context switch in a critical section to assure it is
- not interrupted by the tick ISR. It is not a problem to do this as
- each task maintains its own interrupt status. */
- portENTER_CRITICAL();
- {
- /* Jump directly to the yield function to ensure there is no
- compiler generated prologue code. */
- asm volatile ( "bralid r14, VPortYieldASM \n\t" \
- "or r0, r0, r0 \n\t" );
- }
- portEXIT_CRITICAL();
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnableInterrupt( uint8_t ucInterruptID )
-{
-int32_t lReturn;
-
- /* An API function is provided to enable an interrupt in the interrupt
- controller because the interrupt controller instance variable is private
- to this file. */
- lReturn = prvEnsureInterruptControllerIsInitialised();
- if( lReturn == pdPASS )
- {
- XIntc_Enable( &xInterruptControllerInstance, ucInterruptID );
- }
-
- configASSERT( lReturn );
-}
-/*-----------------------------------------------------------*/
-
-void vPortDisableInterrupt( uint8_t ucInterruptID )
-{
-int32_t lReturn;
-
- /* An API function is provided to disable an interrupt in the interrupt
- controller because the interrupt controller instance variable is private
- to this file. */
- lReturn = prvEnsureInterruptControllerIsInitialised();
-
- if( lReturn == pdPASS )
- {
- XIntc_Disable( &xInterruptControllerInstance, ucInterruptID );
- }
-
- configASSERT( lReturn );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )
-{
-int32_t lReturn;
-
- /* An API function is provided to install an interrupt handler because the
- interrupt controller instance variable is private to this file. */
-
- lReturn = prvEnsureInterruptControllerIsInitialised();
-
- if( lReturn == pdPASS )
- {
- lReturn = XIntc_Connect( &xInterruptControllerInstance, ucInterruptID, pxHandler, pvCallBackRef );
- }
-
- if( lReturn == XST_SUCCESS )
- {
- lReturn = pdPASS;
- }
-
- configASSERT( lReturn == pdPASS );
-
- return lReturn;
-}
-/*-----------------------------------------------------------*/
-
-static int32_t prvEnsureInterruptControllerIsInitialised( void )
-{
-static int32_t lInterruptControllerInitialised = pdFALSE;
-int32_t lReturn;
-
- /* Ensure the interrupt controller instance variable is initialised before
- it is used, and that the initialisation only happens once. */
- if( lInterruptControllerInitialised != pdTRUE )
- {
- lReturn = prvInitialiseInterruptController();
-
- if( lReturn == pdPASS )
- {
- lInterruptControllerInitialised = pdTRUE;
- }
- }
- else
- {
- lReturn = pdPASS;
- }
-
- return lReturn;
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Handler for the timer interrupt. This is the handler that the application
- * defined callback function vApplicationSetupTimerInterrupt() should install.
- */
-void vPortTickISR( void *pvUnused )
-{
-extern void vApplicationClearTimerInterrupt( void );
-
- /* Ensure the unused parameter does not generate a compiler warning. */
- ( void ) pvUnused;
-
- /* This port uses an application defined callback function to clear the tick
- interrupt because the kernel will run on lots of different MicroBlaze and
- FPGA configurations - not all of which will have the same timer peripherals
- defined or available. An example definition of
- vApplicationClearTimerInterrupt() is provided in the official demo
- application that accompanies this port. */
- vApplicationClearTimerInterrupt();
-
- /* Increment the RTOS tick - this might cause a task to unblock. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- /* Force vTaskSwitchContext() to be called as the interrupt exits. */
- ulTaskSwitchRequested = 1;
- }
-}
-/*-----------------------------------------------------------*/
-
-static int32_t prvInitialiseInterruptController( void )
-{
-int32_t lStatus;
-
- lStatus = XIntc_Initialize( &xInterruptControllerInstance, configINTERRUPT_CONTROLLER_TO_USE );
-
- if( lStatus == XST_SUCCESS )
- {
- /* Initialise the exception table. */
- Xil_ExceptionInit();
-
- /* Service all pending interrupts each time the handler is entered. */
- XIntc_SetIntrSvcOption( xInterruptControllerInstance.BaseAddress, XIN_SVC_ALL_ISRS_OPTION );
-
- /* Install exception handlers if the MicroBlaze is configured to handle
- exceptions, and the application defined constant
- configINSTALL_EXCEPTION_HANDLERS is set to 1. */
- #if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
- {
- vPortExceptionsInstallHandlers();
- }
- #endif /* MICROBLAZE_EXCEPTIONS_ENABLED */
-
- /* Start the interrupt controller. Interrupts are enabled when the
- scheduler starts. */
- lStatus = XIntc_Start( &xInterruptControllerInstance, XIN_REAL_MODE );
-
- if( lStatus == XST_SUCCESS )
- {
- lStatus = pdPASS;
- }
- else
- {
- lStatus = pdFAIL;
- }
- }
-
- configASSERT( lStatus == pdPASS );
-
- return lStatus;
-}
-/*-----------------------------------------------------------*/
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the MicroBlaze port.
+ *----------------------------------------------------------*/
+
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Standard includes. */
+#include <string.h>
+
+/* Hardware includes. */
+#include <xintc_i.h>
+#include <xil_exception.h>
+#include <microblaze_exceptions_g.h>
+
+/* Tasks are started with a critical section nesting of 0 - however, prior to
+the scheduler being commenced interrupts should not be enabled, so the critical
+nesting variable is initialised to a non-zero value. */
+#define portINITIAL_NESTING_VALUE ( 0xff )
+
+/* The bit within the MSR register that enabled/disables interrupts and
+exceptions respectively. */
+#define portMSR_IE ( 0x02U )
+#define portMSR_EE ( 0x100U )
+
+/* If the floating point unit is included in the MicroBlaze build, then the
+FSR register is saved as part of the task context. portINITIAL_FSR is the value
+given to the FSR register when the initial context is set up for a task being
+created. */
+#define portINITIAL_FSR ( 0U )
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the interrupt controller instance.
+ */
+static int32_t prvInitialiseInterruptController( void );
+
+/* Ensure the interrupt controller instance variable is initialised before it is
+ * used, and that the initialisation only happens once.
+ */
+static int32_t prvEnsureInterruptControllerIsInitialised( void );
+
+/*-----------------------------------------------------------*/
+
+/* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task
+maintains its own count, so this variable is saved as part of the task
+context. */
+volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE;
+
+/* This port uses a separate stack for interrupts. This prevents the stack of
+every task needing to be large enough to hold an entire interrupt stack on top
+of the task stack. */
+uint32_t *pulISRStack;
+
+/* If an interrupt requests a context switch, then ulTaskSwitchRequested will
+get set to 1. ulTaskSwitchRequested is inspected just before the main interrupt
+handler exits. If, at that time, ulTaskSwitchRequested is set to 1, the kernel
+will call vTaskSwitchContext() to ensure the task that runs immediately after
+the interrupt exists is the highest priority task that is able to run. This is
+an unusual mechanism, but is used for this port because a single interrupt can
+cause the servicing of multiple peripherals - and it is inefficient to call
+vTaskSwitchContext() multiple times as each peripheral is serviced. */
+volatile uint32_t ulTaskSwitchRequested = 0UL;
+
+/* The instance of the interrupt controller used by this port. This is required
+by the Xilinx library API functions. */
+static XIntc xInterruptControllerInstance;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been made.
+ *
+ * See the portable.h header file.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+extern void * _SDA2_BASE_;
+extern void * _SDA_BASE_;
+const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
+const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
+
+ /* Place a few bytes of known values on the bottom of the stack.
+ This is essential for the Microblaze port and these lines must
+ not be omitted. */
+ *pxTopOfStack = ( StackType_t ) 0x00000000;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x00000000;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x00000000;
+ pxTopOfStack--;
+
+ #if( XPAR_MICROBLAZE_USE_FPU != 0 )
+ /* The FSR value placed in the initial task context is just 0. */
+ *pxTopOfStack = portINITIAL_FSR;
+ pxTopOfStack--;
+ #endif
+
+ /* The MSR value placed in the initial task context should have interrupts
+ disabled. Each task will enable interrupts automatically when it enters
+ the running state for the first time. */
+ *pxTopOfStack = mfmsr() & ~portMSR_IE;
+
+ #if( MICROBLAZE_EXCEPTIONS_ENABLED == 1 )
+ {
+ /* Ensure exceptions are enabled for the task. */
+ *pxTopOfStack |= portMSR_EE;
+ }
+ #endif
+
+ pxTopOfStack--;
+
+ /* First stack an initial value for the critical section nesting. This
+ is initialised to zero. */
+ *pxTopOfStack = ( StackType_t ) 0x00;
+
+ /* R0 is always zero. */
+ /* R1 is the SP. */
+
+ /* Place an initial value for all the general purpose registers. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) ulR2; /* R2 - read only small data area. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03; /* R3 - return values and temporaries. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04; /* R4 - return values and temporaries. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters;/* R5 contains the function call parameters. */
+
+ #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06; /* R6 - other parameters and temporaries. Used as the return address from vPortTaskEntryPoint. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07; /* R7 - other parameters and temporaries. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08; /* R8 - other parameters and temporaries. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09; /* R9 - other parameters and temporaries. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x0a; /* R10 - other parameters and temporaries. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x0b; /* R11 - temporaries. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x0c; /* R12 - temporaries. */
+ pxTopOfStack--;
+ #else
+ pxTopOfStack-= 8;
+ #endif
+
+ *pxTopOfStack = ( StackType_t ) ulR13; /* R13 - read/write small data area. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* R14 - return address for interrupt. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) NULL; /* R15 - return address for subroutine. */
+
+ #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10; /* R16 - return address for trap (debugger). */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11; /* R17 - return address for exceptions, if configured. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12; /* R18 - reserved for assembler and compiler temporaries. */
+ pxTopOfStack--;
+ #else
+ pxTopOfStack -= 4;
+ #endif
+
+ *pxTopOfStack = ( StackType_t ) 0x00; /* R19 - must be saved across function calls. Callee-save. Seems to be interpreted as the frame pointer. */
+
+ #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x14; /* R20 - reserved for storing a pointer to the Global Offset Table (GOT) in Position Independent Code (PIC). Non-volatile in non-PIC code. Must be saved across function calls. Callee-save. Not used by FreeRTOS. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x15; /* R21 - must be saved across function calls. Callee-save. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x16; /* R22 - must be saved across function calls. Callee-save. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x17; /* R23 - must be saved across function calls. Callee-save. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x18; /* R24 - must be saved across function calls. Callee-save. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x19; /* R25 - must be saved across function calls. Callee-save. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x1a; /* R26 - must be saved across function calls. Callee-save. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x1b; /* R27 - must be saved across function calls. Callee-save. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x1c; /* R28 - must be saved across function calls. Callee-save. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x1d; /* R29 - must be saved across function calls. Callee-save. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x1e; /* R30 - must be saved across function calls. Callee-save. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x1f; /* R31 - must be saved across function calls. Callee-save. */
+ pxTopOfStack--;
+ #else
+ pxTopOfStack -= 13;
+ #endif
+
+ /* Return a pointer to the top of the stack that has been generated so this
+ can be stored in the task control block for the task. */
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void ( vPortStartFirstTask )( void );
+extern uint32_t _stack[];
+
+ /* Setup the hardware to generate the tick. Interrupts are disabled when
+ this function is called.
+
+ This port uses an application defined callback function to install the tick
+ interrupt handler because the kernel will run on lots of different
+ MicroBlaze and FPGA configurations - not all of which will have the same
+ timer peripherals defined or available. An example definition of
+ vApplicationSetupTimerInterrupt() is provided in the official demo
+ application that accompanies this port. */
+ vApplicationSetupTimerInterrupt();
+
+ /* Reuse the stack from main() as the stack for the interrupts/exceptions. */
+ pulISRStack = ( uint32_t * ) _stack;
+
+ /* Ensure there is enough space for the functions called from the interrupt
+ service routines to write back into the stack frame of the caller. */
+ pulISRStack -= 2;
+
+ /* Restore the context of the first task that is going to run. From here
+ on, the created tasks will be executing. */
+ vPortStartFirstTask();
+
+ /* Should not get here as the tasks are now running! */
+ return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+ /* Not implemented in ports where there is nothing to return to.
+ Artificially force an assert. */
+ configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch called by portYIELD or taskYIELD.
+ */
+void vPortYield( void )
+{
+extern void VPortYieldASM( void );
+
+ /* Perform the context switch in a critical section to assure it is
+ not interrupted by the tick ISR. It is not a problem to do this as
+ each task maintains its own interrupt status. */
+ portENTER_CRITICAL();
+ {
+ /* Jump directly to the yield function to ensure there is no
+ compiler generated prologue code. */
+ asm volatile ( "bralid r14, VPortYieldASM \n\t" \
+ "or r0, r0, r0 \n\t" );
+ }
+ portEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnableInterrupt( uint8_t ucInterruptID )
+{
+int32_t lReturn;
+
+ /* An API function is provided to enable an interrupt in the interrupt
+ controller because the interrupt controller instance variable is private
+ to this file. */
+ lReturn = prvEnsureInterruptControllerIsInitialised();
+ if( lReturn == pdPASS )
+ {
+ XIntc_Enable( &xInterruptControllerInstance, ucInterruptID );
+ }
+
+ configASSERT( lReturn );
+}
+/*-----------------------------------------------------------*/
+
+void vPortDisableInterrupt( uint8_t ucInterruptID )
+{
+int32_t lReturn;
+
+ /* An API function is provided to disable an interrupt in the interrupt
+ controller because the interrupt controller instance variable is private
+ to this file. */
+ lReturn = prvEnsureInterruptControllerIsInitialised();
+
+ if( lReturn == pdPASS )
+ {
+ XIntc_Disable( &xInterruptControllerInstance, ucInterruptID );
+ }
+
+ configASSERT( lReturn );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )
+{
+int32_t lReturn;
+
+ /* An API function is provided to install an interrupt handler because the
+ interrupt controller instance variable is private to this file. */
+
+ lReturn = prvEnsureInterruptControllerIsInitialised();
+
+ if( lReturn == pdPASS )
+ {
+ lReturn = XIntc_Connect( &xInterruptControllerInstance, ucInterruptID, pxHandler, pvCallBackRef );
+ }
+
+ if( lReturn == XST_SUCCESS )
+ {
+ lReturn = pdPASS;
+ }
+
+ configASSERT( lReturn == pdPASS );
+
+ return lReturn;
+}
+/*-----------------------------------------------------------*/
+
+static int32_t prvEnsureInterruptControllerIsInitialised( void )
+{
+static int32_t lInterruptControllerInitialised = pdFALSE;
+int32_t lReturn;
+
+ /* Ensure the interrupt controller instance variable is initialised before
+ it is used, and that the initialisation only happens once. */
+ if( lInterruptControllerInitialised != pdTRUE )
+ {
+ lReturn = prvInitialiseInterruptController();
+
+ if( lReturn == pdPASS )
+ {
+ lInterruptControllerInitialised = pdTRUE;
+ }
+ }
+ else
+ {
+ lReturn = pdPASS;
+ }
+
+ return lReturn;
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Handler for the timer interrupt. This is the handler that the application
+ * defined callback function vApplicationSetupTimerInterrupt() should install.
+ */
+void vPortTickISR( void *pvUnused )
+{
+extern void vApplicationClearTimerInterrupt( void );
+
+ /* Ensure the unused parameter does not generate a compiler warning. */
+ ( void ) pvUnused;
+
+ /* This port uses an application defined callback function to clear the tick
+ interrupt because the kernel will run on lots of different MicroBlaze and
+ FPGA configurations - not all of which will have the same timer peripherals
+ defined or available. An example definition of
+ vApplicationClearTimerInterrupt() is provided in the official demo
+ application that accompanies this port. */
+ vApplicationClearTimerInterrupt();
+
+ /* Increment the RTOS tick - this might cause a task to unblock. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ /* Force vTaskSwitchContext() to be called as the interrupt exits. */
+ ulTaskSwitchRequested = 1;
+ }
+}
+/*-----------------------------------------------------------*/
+
+static int32_t prvInitialiseInterruptController( void )
+{
+int32_t lStatus;
+
+ lStatus = XIntc_Initialize( &xInterruptControllerInstance, configINTERRUPT_CONTROLLER_TO_USE );
+
+ if( lStatus == XST_SUCCESS )
+ {
+ /* Initialise the exception table. */
+ Xil_ExceptionInit();
+
+ /* Service all pending interrupts each time the handler is entered. */
+ XIntc_SetIntrSvcOption( xInterruptControllerInstance.BaseAddress, XIN_SVC_ALL_ISRS_OPTION );
+
+ /* Install exception handlers if the MicroBlaze is configured to handle
+ exceptions, and the application defined constant
+ configINSTALL_EXCEPTION_HANDLERS is set to 1. */
+ #if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
+ {
+ vPortExceptionsInstallHandlers();
+ }
+ #endif /* MICROBLAZE_EXCEPTIONS_ENABLED */
+
+ /* Start the interrupt controller. Interrupts are enabled when the
+ scheduler starts. */
+ lStatus = XIntc_Start( &xInterruptControllerInstance, XIN_REAL_MODE );
+
+ if( lStatus == XST_SUCCESS )
+ {
+ lStatus = pdPASS;
+ }
+ else
+ {
+ lStatus = pdFAIL;
+ }
+ }
+
+ configASSERT( lStatus == pdPASS );
+
+ return lStatus;
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/MicroBlazeV8/port_exceptions.c b/portable/GCC/MicroBlazeV8/port_exceptions.c
index fde2f83..52055fc 100644
--- a/portable/GCC/MicroBlazeV8/port_exceptions.c
+++ b/portable/GCC/MicroBlazeV8/port_exceptions.c
@@ -1,283 +1,280 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Hardware includes. */
-#include <microblaze_exceptions_i.h>
-#include <microblaze_exceptions_g.h>
-
-/* The Xilinx library defined exception entry point stacks a number of
-registers. These definitions are offsets from the stack pointer to the various
-stacked register values. */
-#define portexR3_STACK_OFFSET 4
-#define portexR4_STACK_OFFSET 5
-#define portexR5_STACK_OFFSET 6
-#define portexR6_STACK_OFFSET 7
-#define portexR7_STACK_OFFSET 8
-#define portexR8_STACK_OFFSET 9
-#define portexR9_STACK_OFFSET 10
-#define portexR10_STACK_OFFSET 11
-#define portexR11_STACK_OFFSET 12
-#define portexR12_STACK_OFFSET 13
-#define portexR15_STACK_OFFSET 16
-#define portexR18_STACK_OFFSET 19
-#define portexMSR_STACK_OFFSET 20
-#define portexR19_STACK_OFFSET -1
-
-/* This is defined to equal the size, in bytes, of the stack frame generated by
-the Xilinx standard library exception entry point. It is required to determine
-the stack pointer value prior to the exception being entered. */
-#define portexASM_HANDLER_STACK_FRAME_SIZE 84UL
-
-/* The number of bytes a MicroBlaze instruction consumes. */
-#define portexINSTRUCTION_SIZE 4
-
-/* Exclude this entire file if the MicroBlaze is not configured to handle
-exceptions, or the application defined configuration constant
-configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
-#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
-
-/* This variable is set in the exception entry code, before
-vPortExceptionHandler is called. */
-uint32_t *pulStackPointerOnFunctionEntry = NULL;
-
-/* This is the structure that is filled with the MicroBlaze context as it
-existed immediately prior to the exception occurrence. A pointer to this
-structure is passed into the vApplicationExceptionRegisterDump() callback
-function, if one is defined. */
-static xPortRegisterDump xRegisterDump;
-
-/* This is the FreeRTOS exception handler that is installed for all exception
-types. It is called from vPortExceptionHanlderEntry() - which is itself defined
-in portasm.S. */
-void vPortExceptionHandler( void *pvExceptionID );
-extern void vPortExceptionHandlerEntry( void *pvExceptionID );
-
-/*-----------------------------------------------------------*/
-
-/* vApplicationExceptionRegisterDump() is a callback function that the
-application can optionally define to receive a populated xPortRegisterDump
-structure. If the application chooses not to define a version of
-vApplicationExceptionRegisterDump() then this weekly defined default
-implementation will be called instead. */
-extern void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump ) __attribute__((weak));
-void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump )
-{
- ( void ) xRegisterDump;
-
- for( ;; )
- {
- portNOP();
- }
-}
-/*-----------------------------------------------------------*/
-
-void vPortExceptionHandler( void *pvExceptionID )
-{
-extern void *pxCurrentTCB;
-
- /* Fill an xPortRegisterDump structure with the MicroBlaze context as it
- was immediately before the exception occurrence. */
-
- /* First fill in the name and handle of the task that was in the Running
- state when the exception occurred. */
- xRegisterDump.xCurrentTaskHandle = pxCurrentTCB;
- xRegisterDump.pcCurrentTaskName = pcTaskGetName( NULL );
-
- configASSERT( pulStackPointerOnFunctionEntry );
-
- /* Obtain the values of registers that were stacked prior to this function
- being called, and may have changed since they were stacked. */
- xRegisterDump.ulR3 = pulStackPointerOnFunctionEntry[ portexR3_STACK_OFFSET ];
- xRegisterDump.ulR4 = pulStackPointerOnFunctionEntry[ portexR4_STACK_OFFSET ];
- xRegisterDump.ulR5 = pulStackPointerOnFunctionEntry[ portexR5_STACK_OFFSET ];
- xRegisterDump.ulR6 = pulStackPointerOnFunctionEntry[ portexR6_STACK_OFFSET ];
- xRegisterDump.ulR7 = pulStackPointerOnFunctionEntry[ portexR7_STACK_OFFSET ];
- xRegisterDump.ulR8 = pulStackPointerOnFunctionEntry[ portexR8_STACK_OFFSET ];
- xRegisterDump.ulR9 = pulStackPointerOnFunctionEntry[ portexR9_STACK_OFFSET ];
- xRegisterDump.ulR10 = pulStackPointerOnFunctionEntry[ portexR10_STACK_OFFSET ];
- xRegisterDump.ulR11 = pulStackPointerOnFunctionEntry[ portexR11_STACK_OFFSET ];
- xRegisterDump.ulR12 = pulStackPointerOnFunctionEntry[ portexR12_STACK_OFFSET ];
- xRegisterDump.ulR15_return_address_from_subroutine = pulStackPointerOnFunctionEntry[ portexR15_STACK_OFFSET ];
- xRegisterDump.ulR18 = pulStackPointerOnFunctionEntry[ portexR18_STACK_OFFSET ];
- xRegisterDump.ulR19 = pulStackPointerOnFunctionEntry[ portexR19_STACK_OFFSET ];
- xRegisterDump.ulMSR = pulStackPointerOnFunctionEntry[ portexMSR_STACK_OFFSET ];
-
- /* Obtain the value of all other registers. */
- xRegisterDump.ulR2_small_data_area = mfgpr( R2 );
- xRegisterDump.ulR13_read_write_small_data_area = mfgpr( R13 );
- xRegisterDump.ulR14_return_address_from_interrupt = mfgpr( R14 );
- xRegisterDump.ulR16_return_address_from_trap = mfgpr( R16 );
- xRegisterDump.ulR17_return_address_from_exceptions = mfgpr( R17 );
- xRegisterDump.ulR20 = mfgpr( R20 );
- xRegisterDump.ulR21 = mfgpr( R21 );
- xRegisterDump.ulR22 = mfgpr( R22 );
- xRegisterDump.ulR23 = mfgpr( R23 );
- xRegisterDump.ulR24 = mfgpr( R24 );
- xRegisterDump.ulR25 = mfgpr( R25 );
- xRegisterDump.ulR26 = mfgpr( R26 );
- xRegisterDump.ulR27 = mfgpr( R27 );
- xRegisterDump.ulR28 = mfgpr( R28 );
- xRegisterDump.ulR29 = mfgpr( R29 );
- xRegisterDump.ulR30 = mfgpr( R30 );
- xRegisterDump.ulR31 = mfgpr( R31 );
- xRegisterDump.ulR1_SP = ( ( uint32_t ) pulStackPointerOnFunctionEntry ) + portexASM_HANDLER_STACK_FRAME_SIZE;
- xRegisterDump.ulEAR = mfear();
- xRegisterDump.ulESR = mfesr();
- xRegisterDump.ulEDR = mfedr();
-
- /* Move the saved program counter back to the instruction that was executed
- when the exception occurred. This is only valid for certain types of
- exception. */
- xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_exceptions - portexINSTRUCTION_SIZE;
-
- #if( XPAR_MICROBLAZE_USE_FPU != 0 )
- {
- xRegisterDump.ulFSR = mffsr();
- }
- #else
- {
- xRegisterDump.ulFSR = 0UL;
- }
- #endif
-
- /* Also fill in a string that describes what type of exception this is.
- The string uses the same ID names as defined in the MicroBlaze standard
- library exception header files. */
- switch( ( uint32_t ) pvExceptionID )
- {
- case XEXC_ID_FSL :
- xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FSL";
- break;
-
- case XEXC_ID_UNALIGNED_ACCESS :
- xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_UNALIGNED_ACCESS";
- break;
-
- case XEXC_ID_ILLEGAL_OPCODE :
- xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_ILLEGAL_OPCODE";
- break;
-
- case XEXC_ID_M_AXI_I_EXCEPTION :
- xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_I_EXCEPTION or XEXC_ID_IPLB_EXCEPTION";
- break;
-
- case XEXC_ID_M_AXI_D_EXCEPTION :
- xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_D_EXCEPTION or XEXC_ID_DPLB_EXCEPTION";
- break;
-
- case XEXC_ID_DIV_BY_ZERO :
- xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_DIV_BY_ZERO";
- break;
-
- case XEXC_ID_STACK_VIOLATION :
- xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_STACK_VIOLATION or XEXC_ID_MMU";
- break;
-
- #if( XPAR_MICROBLAZE_USE_FPU != 0 )
-
- case XEXC_ID_FPU :
- xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FPU see ulFSR value";
- break;
-
- #endif /* XPAR_MICROBLAZE_USE_FPU */
- }
-
- /* vApplicationExceptionRegisterDump() is a callback function that the
- application can optionally define to receive the populated xPortRegisterDump
- structure. If the application chooses not to define a version of
- vApplicationExceptionRegisterDump() then the weekly defined default
- implementation within this file will be called instead. */
- vApplicationExceptionRegisterDump( &xRegisterDump );
-
- /* Must not attempt to leave this function! */
- for( ;; )
- {
- portNOP();
- }
-}
-/*-----------------------------------------------------------*/
-
-void vPortExceptionsInstallHandlers( void )
-{
-static uint32_t ulHandlersAlreadyInstalled = pdFALSE;
-
- if( ulHandlersAlreadyInstalled == pdFALSE )
- {
- ulHandlersAlreadyInstalled = pdTRUE;
-
- #if XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS == 1
- microblaze_register_exception_handler( XEXC_ID_UNALIGNED_ACCESS, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_UNALIGNED_ACCESS );
- #endif /* XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS*/
-
- #if XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION == 1
- microblaze_register_exception_handler( XEXC_ID_ILLEGAL_OPCODE, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_ILLEGAL_OPCODE );
- #endif /* XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION */
-
- #if XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION == 1
- microblaze_register_exception_handler( XEXC_ID_M_AXI_I_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_I_EXCEPTION );
- #endif /* XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION */
-
- #if XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION == 1
- microblaze_register_exception_handler( XEXC_ID_M_AXI_D_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_D_EXCEPTION );
- #endif /* XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION */
-
- #if XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION == 1
- microblaze_register_exception_handler( XEXC_ID_IPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_IPLB_EXCEPTION );
- #endif /* XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION */
-
- #if XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION == 1
- microblaze_register_exception_handler( XEXC_ID_DPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DPLB_EXCEPTION );
- #endif /* XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION */
-
- #if XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION == 1
- microblaze_register_exception_handler( XEXC_ID_DIV_BY_ZERO, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DIV_BY_ZERO );
- #endif /* XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION */
-
- #if XPAR_MICROBLAZE_FPU_EXCEPTION == 1
- microblaze_register_exception_handler( XEXC_ID_FPU, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FPU );
- #endif /* XPAR_MICROBLAZE_FPU_EXCEPTION */
-
- #if XPAR_MICROBLAZE_FSL_EXCEPTION == 1
- microblaze_register_exception_handler( XEXC_ID_FSL, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FSL );
- #endif /* XPAR_MICROBLAZE_FSL_EXCEPTION */
-
- microblaze_enable_exceptions();
- }
-}
-
-/* Exclude the entire file if the MicroBlaze is not configured to handle
-exceptions, or the application defined configuration item
-configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
-#endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */
-
-
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Hardware includes. */
+#include <microblaze_exceptions_i.h>
+#include <microblaze_exceptions_g.h>
+
+/* The Xilinx library defined exception entry point stacks a number of
+registers. These definitions are offsets from the stack pointer to the various
+stacked register values. */
+#define portexR3_STACK_OFFSET 4
+#define portexR4_STACK_OFFSET 5
+#define portexR5_STACK_OFFSET 6
+#define portexR6_STACK_OFFSET 7
+#define portexR7_STACK_OFFSET 8
+#define portexR8_STACK_OFFSET 9
+#define portexR9_STACK_OFFSET 10
+#define portexR10_STACK_OFFSET 11
+#define portexR11_STACK_OFFSET 12
+#define portexR12_STACK_OFFSET 13
+#define portexR15_STACK_OFFSET 16
+#define portexR18_STACK_OFFSET 19
+#define portexMSR_STACK_OFFSET 20
+#define portexR19_STACK_OFFSET -1
+
+/* This is defined to equal the size, in bytes, of the stack frame generated by
+the Xilinx standard library exception entry point. It is required to determine
+the stack pointer value prior to the exception being entered. */
+#define portexASM_HANDLER_STACK_FRAME_SIZE 84UL
+
+/* The number of bytes a MicroBlaze instruction consumes. */
+#define portexINSTRUCTION_SIZE 4
+
+/* Exclude this entire file if the MicroBlaze is not configured to handle
+exceptions, or the application defined configuration constant
+configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
+#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
+
+/* This variable is set in the exception entry code, before
+vPortExceptionHandler is called. */
+uint32_t *pulStackPointerOnFunctionEntry = NULL;
+
+/* This is the structure that is filled with the MicroBlaze context as it
+existed immediately prior to the exception occurrence. A pointer to this
+structure is passed into the vApplicationExceptionRegisterDump() callback
+function, if one is defined. */
+static xPortRegisterDump xRegisterDump;
+
+/* This is the FreeRTOS exception handler that is installed for all exception
+types. It is called from vPortExceptionHanlderEntry() - which is itself defined
+in portasm.S. */
+void vPortExceptionHandler( void *pvExceptionID );
+extern void vPortExceptionHandlerEntry( void *pvExceptionID );
+
+/*-----------------------------------------------------------*/
+
+/* vApplicationExceptionRegisterDump() is a callback function that the
+application can optionally define to receive a populated xPortRegisterDump
+structure. If the application chooses not to define a version of
+vApplicationExceptionRegisterDump() then this weekly defined default
+implementation will be called instead. */
+extern void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump ) __attribute__((weak));
+void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump )
+{
+ ( void ) xRegisterDump;
+
+ for( ;; )
+ {
+ portNOP();
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vPortExceptionHandler( void *pvExceptionID )
+{
+extern void *pxCurrentTCB;
+
+ /* Fill an xPortRegisterDump structure with the MicroBlaze context as it
+ was immediately before the exception occurrence. */
+
+ /* First fill in the name and handle of the task that was in the Running
+ state when the exception occurred. */
+ xRegisterDump.xCurrentTaskHandle = pxCurrentTCB;
+ xRegisterDump.pcCurrentTaskName = pcTaskGetName( NULL );
+
+ configASSERT( pulStackPointerOnFunctionEntry );
+
+ /* Obtain the values of registers that were stacked prior to this function
+ being called, and may have changed since they were stacked. */
+ xRegisterDump.ulR3 = pulStackPointerOnFunctionEntry[ portexR3_STACK_OFFSET ];
+ xRegisterDump.ulR4 = pulStackPointerOnFunctionEntry[ portexR4_STACK_OFFSET ];
+ xRegisterDump.ulR5 = pulStackPointerOnFunctionEntry[ portexR5_STACK_OFFSET ];
+ xRegisterDump.ulR6 = pulStackPointerOnFunctionEntry[ portexR6_STACK_OFFSET ];
+ xRegisterDump.ulR7 = pulStackPointerOnFunctionEntry[ portexR7_STACK_OFFSET ];
+ xRegisterDump.ulR8 = pulStackPointerOnFunctionEntry[ portexR8_STACK_OFFSET ];
+ xRegisterDump.ulR9 = pulStackPointerOnFunctionEntry[ portexR9_STACK_OFFSET ];
+ xRegisterDump.ulR10 = pulStackPointerOnFunctionEntry[ portexR10_STACK_OFFSET ];
+ xRegisterDump.ulR11 = pulStackPointerOnFunctionEntry[ portexR11_STACK_OFFSET ];
+ xRegisterDump.ulR12 = pulStackPointerOnFunctionEntry[ portexR12_STACK_OFFSET ];
+ xRegisterDump.ulR15_return_address_from_subroutine = pulStackPointerOnFunctionEntry[ portexR15_STACK_OFFSET ];
+ xRegisterDump.ulR18 = pulStackPointerOnFunctionEntry[ portexR18_STACK_OFFSET ];
+ xRegisterDump.ulR19 = pulStackPointerOnFunctionEntry[ portexR19_STACK_OFFSET ];
+ xRegisterDump.ulMSR = pulStackPointerOnFunctionEntry[ portexMSR_STACK_OFFSET ];
+
+ /* Obtain the value of all other registers. */
+ xRegisterDump.ulR2_small_data_area = mfgpr( R2 );
+ xRegisterDump.ulR13_read_write_small_data_area = mfgpr( R13 );
+ xRegisterDump.ulR14_return_address_from_interrupt = mfgpr( R14 );
+ xRegisterDump.ulR16_return_address_from_trap = mfgpr( R16 );
+ xRegisterDump.ulR17_return_address_from_exceptions = mfgpr( R17 );
+ xRegisterDump.ulR20 = mfgpr( R20 );
+ xRegisterDump.ulR21 = mfgpr( R21 );
+ xRegisterDump.ulR22 = mfgpr( R22 );
+ xRegisterDump.ulR23 = mfgpr( R23 );
+ xRegisterDump.ulR24 = mfgpr( R24 );
+ xRegisterDump.ulR25 = mfgpr( R25 );
+ xRegisterDump.ulR26 = mfgpr( R26 );
+ xRegisterDump.ulR27 = mfgpr( R27 );
+ xRegisterDump.ulR28 = mfgpr( R28 );
+ xRegisterDump.ulR29 = mfgpr( R29 );
+ xRegisterDump.ulR30 = mfgpr( R30 );
+ xRegisterDump.ulR31 = mfgpr( R31 );
+ xRegisterDump.ulR1_SP = ( ( uint32_t ) pulStackPointerOnFunctionEntry ) + portexASM_HANDLER_STACK_FRAME_SIZE;
+ xRegisterDump.ulEAR = mfear();
+ xRegisterDump.ulESR = mfesr();
+ xRegisterDump.ulEDR = mfedr();
+
+ /* Move the saved program counter back to the instruction that was executed
+ when the exception occurred. This is only valid for certain types of
+ exception. */
+ xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_exceptions - portexINSTRUCTION_SIZE;
+
+ #if( XPAR_MICROBLAZE_USE_FPU != 0 )
+ {
+ xRegisterDump.ulFSR = mffsr();
+ }
+ #else
+ {
+ xRegisterDump.ulFSR = 0UL;
+ }
+ #endif
+
+ /* Also fill in a string that describes what type of exception this is.
+ The string uses the same ID names as defined in the MicroBlaze standard
+ library exception header files. */
+ switch( ( uint32_t ) pvExceptionID )
+ {
+ case XEXC_ID_FSL :
+ xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FSL";
+ break;
+
+ case XEXC_ID_UNALIGNED_ACCESS :
+ xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_UNALIGNED_ACCESS";
+ break;
+
+ case XEXC_ID_ILLEGAL_OPCODE :
+ xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_ILLEGAL_OPCODE";
+ break;
+
+ case XEXC_ID_M_AXI_I_EXCEPTION :
+ xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_I_EXCEPTION or XEXC_ID_IPLB_EXCEPTION";
+ break;
+
+ case XEXC_ID_M_AXI_D_EXCEPTION :
+ xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_D_EXCEPTION or XEXC_ID_DPLB_EXCEPTION";
+ break;
+
+ case XEXC_ID_DIV_BY_ZERO :
+ xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_DIV_BY_ZERO";
+ break;
+
+ case XEXC_ID_STACK_VIOLATION :
+ xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_STACK_VIOLATION or XEXC_ID_MMU";
+ break;
+
+ #if( XPAR_MICROBLAZE_USE_FPU != 0 )
+
+ case XEXC_ID_FPU :
+ xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FPU see ulFSR value";
+ break;
+
+ #endif /* XPAR_MICROBLAZE_USE_FPU */
+ }
+
+ /* vApplicationExceptionRegisterDump() is a callback function that the
+ application can optionally define to receive the populated xPortRegisterDump
+ structure. If the application chooses not to define a version of
+ vApplicationExceptionRegisterDump() then the weekly defined default
+ implementation within this file will be called instead. */
+ vApplicationExceptionRegisterDump( &xRegisterDump );
+
+ /* Must not attempt to leave this function! */
+ for( ;; )
+ {
+ portNOP();
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vPortExceptionsInstallHandlers( void )
+{
+static uint32_t ulHandlersAlreadyInstalled = pdFALSE;
+
+ if( ulHandlersAlreadyInstalled == pdFALSE )
+ {
+ ulHandlersAlreadyInstalled = pdTRUE;
+
+ #if XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS == 1
+ microblaze_register_exception_handler( XEXC_ID_UNALIGNED_ACCESS, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_UNALIGNED_ACCESS );
+ #endif /* XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS*/
+
+ #if XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION == 1
+ microblaze_register_exception_handler( XEXC_ID_ILLEGAL_OPCODE, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_ILLEGAL_OPCODE );
+ #endif /* XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION */
+
+ #if XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION == 1
+ microblaze_register_exception_handler( XEXC_ID_M_AXI_I_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_I_EXCEPTION );
+ #endif /* XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION */
+
+ #if XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION == 1
+ microblaze_register_exception_handler( XEXC_ID_M_AXI_D_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_D_EXCEPTION );
+ #endif /* XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION */
+
+ #if XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION == 1
+ microblaze_register_exception_handler( XEXC_ID_IPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_IPLB_EXCEPTION );
+ #endif /* XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION */
+
+ #if XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION == 1
+ microblaze_register_exception_handler( XEXC_ID_DPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DPLB_EXCEPTION );
+ #endif /* XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION */
+
+ #if XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION == 1
+ microblaze_register_exception_handler( XEXC_ID_DIV_BY_ZERO, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DIV_BY_ZERO );
+ #endif /* XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION */
+
+ #if XPAR_MICROBLAZE_FPU_EXCEPTION == 1
+ microblaze_register_exception_handler( XEXC_ID_FPU, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FPU );
+ #endif /* XPAR_MICROBLAZE_FPU_EXCEPTION */
+
+ #if XPAR_MICROBLAZE_FSL_EXCEPTION == 1
+ microblaze_register_exception_handler( XEXC_ID_FSL, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FSL );
+ #endif /* XPAR_MICROBLAZE_FSL_EXCEPTION */
+
+ microblaze_enable_exceptions();
+ }
+}
+
+/* Exclude the entire file if the MicroBlaze is not configured to handle
+exceptions, or the application defined configuration item
+configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
+#endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */
diff --git a/portable/GCC/MicroBlazeV8/portasm.S b/portable/GCC/MicroBlazeV8/portasm.S
index 6bea21f..d0e2051 100644
--- a/portable/GCC/MicroBlazeV8/portasm.S
+++ b/portable/GCC/MicroBlazeV8/portasm.S
@@ -1,329 +1,326 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/* FreeRTOS includes. */
-#include "FreeRTOSConfig.h"
-
-/* Xilinx library includes. */
-#include "microblaze_exceptions_g.h"
-#include "xparameters.h"
-
-/* The context is oversized to allow functions called from the ISR to write
-back into the caller stack. */
-#if( XPAR_MICROBLAZE_USE_FPU != 0 )
- #define portCONTEXT_SIZE 136
- #define portMINUS_CONTEXT_SIZE -136
-#else
- #define portCONTEXT_SIZE 132
- #define portMINUS_CONTEXT_SIZE -132
-#endif
-
-/* Offsets from the stack pointer at which saved registers are placed. */
-#define portR31_OFFSET 4
-#define portR30_OFFSET 8
-#define portR29_OFFSET 12
-#define portR28_OFFSET 16
-#define portR27_OFFSET 20
-#define portR26_OFFSET 24
-#define portR25_OFFSET 28
-#define portR24_OFFSET 32
-#define portR23_OFFSET 36
-#define portR22_OFFSET 40
-#define portR21_OFFSET 44
-#define portR20_OFFSET 48
-#define portR19_OFFSET 52
-#define portR18_OFFSET 56
-#define portR17_OFFSET 60
-#define portR16_OFFSET 64
-#define portR15_OFFSET 68
-#define portR14_OFFSET 72
-#define portR13_OFFSET 76
-#define portR12_OFFSET 80
-#define portR11_OFFSET 84
-#define portR10_OFFSET 88
-#define portR9_OFFSET 92
-#define portR8_OFFSET 96
-#define portR7_OFFSET 100
-#define portR6_OFFSET 104
-#define portR5_OFFSET 108
-#define portR4_OFFSET 112
-#define portR3_OFFSET 116
-#define portR2_OFFSET 120
-#define portCRITICAL_NESTING_OFFSET 124
-#define portMSR_OFFSET 128
-#define portFSR_OFFSET 132
-
- .extern pxCurrentTCB
- .extern XIntc_DeviceInterruptHandler
- .extern vTaskSwitchContext
- .extern uxCriticalNesting
- .extern pulISRStack
- .extern ulTaskSwitchRequested
- .extern vPortExceptionHandler
- .extern pulStackPointerOnFunctionEntry
-
- .global _interrupt_handler
- .global VPortYieldASM
- .global vPortStartFirstTask
- .global vPortExceptionHandlerEntry
-
-
-.macro portSAVE_CONTEXT
-
- /* Make room for the context on the stack. */
- addik r1, r1, portMINUS_CONTEXT_SIZE
-
- /* Stack general registers. */
- swi r31, r1, portR31_OFFSET
- swi r30, r1, portR30_OFFSET
- swi r29, r1, portR29_OFFSET
- swi r28, r1, portR28_OFFSET
- swi r27, r1, portR27_OFFSET
- swi r26, r1, portR26_OFFSET
- swi r25, r1, portR25_OFFSET
- swi r24, r1, portR24_OFFSET
- swi r23, r1, portR23_OFFSET
- swi r22, r1, portR22_OFFSET
- swi r21, r1, portR21_OFFSET
- swi r20, r1, portR20_OFFSET
- swi r19, r1, portR19_OFFSET
- swi r18, r1, portR18_OFFSET
- swi r17, r1, portR17_OFFSET
- swi r16, r1, portR16_OFFSET
- swi r15, r1, portR15_OFFSET
- /* R14 is saved later as it needs adjustment if a yield is performed. */
- swi r13, r1, portR13_OFFSET
- swi r12, r1, portR12_OFFSET
- swi r11, r1, portR11_OFFSET
- swi r10, r1, portR10_OFFSET
- swi r9, r1, portR9_OFFSET
- swi r8, r1, portR8_OFFSET
- swi r7, r1, portR7_OFFSET
- swi r6, r1, portR6_OFFSET
- swi r5, r1, portR5_OFFSET
- swi r4, r1, portR4_OFFSET
- swi r3, r1, portR3_OFFSET
- swi r2, r1, portR2_OFFSET
-
- /* Stack the critical section nesting value. */
- lwi r18, r0, uxCriticalNesting
- swi r18, r1, portCRITICAL_NESTING_OFFSET
-
- /* Stack MSR. */
- mfs r18, rmsr
- swi r18, r1, portMSR_OFFSET
-
- #if( XPAR_MICROBLAZE_USE_FPU != 0 )
- /* Stack FSR. */
- mfs r18, rfsr
- swi r18, r1, portFSR_OFFSET
- #endif
-
- /* Save the top of stack value to the TCB. */
- lwi r3, r0, pxCurrentTCB
- sw r1, r0, r3
-
- .endm
-
-.macro portRESTORE_CONTEXT
-
- /* Load the top of stack value from the TCB. */
- lwi r18, r0, pxCurrentTCB
- lw r1, r0, r18
-
- /* Restore the general registers. */
- lwi r31, r1, portR31_OFFSET
- lwi r30, r1, portR30_OFFSET
- lwi r29, r1, portR29_OFFSET
- lwi r28, r1, portR28_OFFSET
- lwi r27, r1, portR27_OFFSET
- lwi r26, r1, portR26_OFFSET
- lwi r25, r1, portR25_OFFSET
- lwi r24, r1, portR24_OFFSET
- lwi r23, r1, portR23_OFFSET
- lwi r22, r1, portR22_OFFSET
- lwi r21, r1, portR21_OFFSET
- lwi r20, r1, portR20_OFFSET
- lwi r19, r1, portR19_OFFSET
- lwi r17, r1, portR17_OFFSET
- lwi r16, r1, portR16_OFFSET
- lwi r15, r1, portR15_OFFSET
- lwi r14, r1, portR14_OFFSET
- lwi r13, r1, portR13_OFFSET
- lwi r12, r1, portR12_OFFSET
- lwi r11, r1, portR11_OFFSET
- lwi r10, r1, portR10_OFFSET
- lwi r9, r1, portR9_OFFSET
- lwi r8, r1, portR8_OFFSET
- lwi r7, r1, portR7_OFFSET
- lwi r6, r1, portR6_OFFSET
- lwi r5, r1, portR5_OFFSET
- lwi r4, r1, portR4_OFFSET
- lwi r3, r1, portR3_OFFSET
- lwi r2, r1, portR2_OFFSET
-
- /* Reload the rmsr from the stack. */
- lwi r18, r1, portMSR_OFFSET
- mts rmsr, r18
-
- #if( XPAR_MICROBLAZE_USE_FPU != 0 )
- /* Reload the FSR from the stack. */
- lwi r18, r1, portFSR_OFFSET
- mts rfsr, r18
- #endif
-
- /* Load the critical nesting value. */
- lwi r18, r1, portCRITICAL_NESTING_OFFSET
- swi r18, r0, uxCriticalNesting
-
- /* Test the critical nesting value. If it is non zero then the task last
- exited the running state using a yield. If it is zero, then the task
- last exited the running state through an interrupt. */
- xori r18, r18, 0
- bnei r18, exit_from_yield
-
- /* r18 was being used as a temporary. Now restore its true value from the
- stack. */
- lwi r18, r1, portR18_OFFSET
-
- /* Remove the stack frame. */
- addik r1, r1, portCONTEXT_SIZE
-
- /* Return using rtid so interrupts are re-enabled as this function is
- exited. */
- rtid r14, 0
- or r0, r0, r0
-
- .endm
-
-/* This function is used to exit portRESTORE_CONTEXT() if the task being
-returned to last left the Running state by calling taskYIELD() (rather than
-being preempted by an interrupt). */
- .text
- .align 4
-exit_from_yield:
-
- /* r18 was being used as a temporary. Now restore its true value from the
- stack. */
- lwi r18, r1, portR18_OFFSET
-
- /* Remove the stack frame. */
- addik r1, r1, portCONTEXT_SIZE
-
- /* Return to the task. */
- rtsd r14, 0
- or r0, r0, r0
-
-
- .text
- .align 4
-_interrupt_handler:
-
- portSAVE_CONTEXT
-
- /* Stack the return address. */
- swi r14, r1, portR14_OFFSET
-
- /* Switch to the ISR stack. */
- lwi r1, r0, pulISRStack
-
- /* The parameter to the interrupt handler. */
- ori r5, r0, configINTERRUPT_CONTROLLER_TO_USE
-
- /* Execute any pending interrupts. */
- bralid r15, XIntc_DeviceInterruptHandler
- or r0, r0, r0
-
- /* See if a new task should be selected to execute. */
- lwi r18, r0, ulTaskSwitchRequested
- or r18, r18, r0
-
- /* If ulTaskSwitchRequested is already zero, then jump straight to
- restoring the task that is already in the Running state. */
- beqi r18, task_switch_not_requested
-
- /* Set ulTaskSwitchRequested back to zero as a task switch is about to be
- performed. */
- swi r0, r0, ulTaskSwitchRequested
-
- /* ulTaskSwitchRequested was not 0 when tested. Select the next task to
- execute. */
- bralid r15, vTaskSwitchContext
- or r0, r0, r0
-
-task_switch_not_requested:
-
- /* Restore the context of the next task scheduled to execute. */
- portRESTORE_CONTEXT
-
-
- .text
- .align 4
-VPortYieldASM:
-
- portSAVE_CONTEXT
-
- /* Modify the return address so a return is done to the instruction after
- the call to VPortYieldASM. */
- addi r14, r14, 8
- swi r14, r1, portR14_OFFSET
-
- /* Switch to use the ISR stack. */
- lwi r1, r0, pulISRStack
-
- /* Select the next task to execute. */
- bralid r15, vTaskSwitchContext
- or r0, r0, r0
-
- /* Restore the context of the next task scheduled to execute. */
- portRESTORE_CONTEXT
-
- .text
- .align 4
-vPortStartFirstTask:
-
- portRESTORE_CONTEXT
-
-
-
-#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
-
- .text
- .align 4
-vPortExceptionHandlerEntry:
-
- /* Take a copy of the stack pointer before vPortExecptionHandler is called,
- storing its value prior to the function stack frame being created. */
- swi r1, r0, pulStackPointerOnFunctionEntry
- bralid r15, vPortExceptionHandler
- or r0, r0, r0
-
-#endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */
-
-
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* FreeRTOS includes. */
+#include "FreeRTOSConfig.h"
+
+/* Xilinx library includes. */
+#include "microblaze_exceptions_g.h"
+#include "xparameters.h"
+
+/* The context is oversized to allow functions called from the ISR to write
+back into the caller stack. */
+#if( XPAR_MICROBLAZE_USE_FPU != 0 )
+ #define portCONTEXT_SIZE 136
+ #define portMINUS_CONTEXT_SIZE -136
+#else
+ #define portCONTEXT_SIZE 132
+ #define portMINUS_CONTEXT_SIZE -132
+#endif
+
+/* Offsets from the stack pointer at which saved registers are placed. */
+#define portR31_OFFSET 4
+#define portR30_OFFSET 8
+#define portR29_OFFSET 12
+#define portR28_OFFSET 16
+#define portR27_OFFSET 20
+#define portR26_OFFSET 24
+#define portR25_OFFSET 28
+#define portR24_OFFSET 32
+#define portR23_OFFSET 36
+#define portR22_OFFSET 40
+#define portR21_OFFSET 44
+#define portR20_OFFSET 48
+#define portR19_OFFSET 52
+#define portR18_OFFSET 56
+#define portR17_OFFSET 60
+#define portR16_OFFSET 64
+#define portR15_OFFSET 68
+#define portR14_OFFSET 72
+#define portR13_OFFSET 76
+#define portR12_OFFSET 80
+#define portR11_OFFSET 84
+#define portR10_OFFSET 88
+#define portR9_OFFSET 92
+#define portR8_OFFSET 96
+#define portR7_OFFSET 100
+#define portR6_OFFSET 104
+#define portR5_OFFSET 108
+#define portR4_OFFSET 112
+#define portR3_OFFSET 116
+#define portR2_OFFSET 120
+#define portCRITICAL_NESTING_OFFSET 124
+#define portMSR_OFFSET 128
+#define portFSR_OFFSET 132
+
+ .extern pxCurrentTCB
+ .extern XIntc_DeviceInterruptHandler
+ .extern vTaskSwitchContext
+ .extern uxCriticalNesting
+ .extern pulISRStack
+ .extern ulTaskSwitchRequested
+ .extern vPortExceptionHandler
+ .extern pulStackPointerOnFunctionEntry
+
+ .global _interrupt_handler
+ .global VPortYieldASM
+ .global vPortStartFirstTask
+ .global vPortExceptionHandlerEntry
+
+
+.macro portSAVE_CONTEXT
+
+ /* Make room for the context on the stack. */
+ addik r1, r1, portMINUS_CONTEXT_SIZE
+
+ /* Stack general registers. */
+ swi r31, r1, portR31_OFFSET
+ swi r30, r1, portR30_OFFSET
+ swi r29, r1, portR29_OFFSET
+ swi r28, r1, portR28_OFFSET
+ swi r27, r1, portR27_OFFSET
+ swi r26, r1, portR26_OFFSET
+ swi r25, r1, portR25_OFFSET
+ swi r24, r1, portR24_OFFSET
+ swi r23, r1, portR23_OFFSET
+ swi r22, r1, portR22_OFFSET
+ swi r21, r1, portR21_OFFSET
+ swi r20, r1, portR20_OFFSET
+ swi r19, r1, portR19_OFFSET
+ swi r18, r1, portR18_OFFSET
+ swi r17, r1, portR17_OFFSET
+ swi r16, r1, portR16_OFFSET
+ swi r15, r1, portR15_OFFSET
+ /* R14 is saved later as it needs adjustment if a yield is performed. */
+ swi r13, r1, portR13_OFFSET
+ swi r12, r1, portR12_OFFSET
+ swi r11, r1, portR11_OFFSET
+ swi r10, r1, portR10_OFFSET
+ swi r9, r1, portR9_OFFSET
+ swi r8, r1, portR8_OFFSET
+ swi r7, r1, portR7_OFFSET
+ swi r6, r1, portR6_OFFSET
+ swi r5, r1, portR5_OFFSET
+ swi r4, r1, portR4_OFFSET
+ swi r3, r1, portR3_OFFSET
+ swi r2, r1, portR2_OFFSET
+
+ /* Stack the critical section nesting value. */
+ lwi r18, r0, uxCriticalNesting
+ swi r18, r1, portCRITICAL_NESTING_OFFSET
+
+ /* Stack MSR. */
+ mfs r18, rmsr
+ swi r18, r1, portMSR_OFFSET
+
+ #if( XPAR_MICROBLAZE_USE_FPU != 0 )
+ /* Stack FSR. */
+ mfs r18, rfsr
+ swi r18, r1, portFSR_OFFSET
+ #endif
+
+ /* Save the top of stack value to the TCB. */
+ lwi r3, r0, pxCurrentTCB
+ sw r1, r0, r3
+
+ .endm
+
+.macro portRESTORE_CONTEXT
+
+ /* Load the top of stack value from the TCB. */
+ lwi r18, r0, pxCurrentTCB
+ lw r1, r0, r18
+
+ /* Restore the general registers. */
+ lwi r31, r1, portR31_OFFSET
+ lwi r30, r1, portR30_OFFSET
+ lwi r29, r1, portR29_OFFSET
+ lwi r28, r1, portR28_OFFSET
+ lwi r27, r1, portR27_OFFSET
+ lwi r26, r1, portR26_OFFSET
+ lwi r25, r1, portR25_OFFSET
+ lwi r24, r1, portR24_OFFSET
+ lwi r23, r1, portR23_OFFSET
+ lwi r22, r1, portR22_OFFSET
+ lwi r21, r1, portR21_OFFSET
+ lwi r20, r1, portR20_OFFSET
+ lwi r19, r1, portR19_OFFSET
+ lwi r17, r1, portR17_OFFSET
+ lwi r16, r1, portR16_OFFSET
+ lwi r15, r1, portR15_OFFSET
+ lwi r14, r1, portR14_OFFSET
+ lwi r13, r1, portR13_OFFSET
+ lwi r12, r1, portR12_OFFSET
+ lwi r11, r1, portR11_OFFSET
+ lwi r10, r1, portR10_OFFSET
+ lwi r9, r1, portR9_OFFSET
+ lwi r8, r1, portR8_OFFSET
+ lwi r7, r1, portR7_OFFSET
+ lwi r6, r1, portR6_OFFSET
+ lwi r5, r1, portR5_OFFSET
+ lwi r4, r1, portR4_OFFSET
+ lwi r3, r1, portR3_OFFSET
+ lwi r2, r1, portR2_OFFSET
+
+ /* Reload the rmsr from the stack. */
+ lwi r18, r1, portMSR_OFFSET
+ mts rmsr, r18
+
+ #if( XPAR_MICROBLAZE_USE_FPU != 0 )
+ /* Reload the FSR from the stack. */
+ lwi r18, r1, portFSR_OFFSET
+ mts rfsr, r18
+ #endif
+
+ /* Load the critical nesting value. */
+ lwi r18, r1, portCRITICAL_NESTING_OFFSET
+ swi r18, r0, uxCriticalNesting
+
+ /* Test the critical nesting value. If it is non zero then the task last
+ exited the running state using a yield. If it is zero, then the task
+ last exited the running state through an interrupt. */
+ xori r18, r18, 0
+ bnei r18, exit_from_yield
+
+ /* r18 was being used as a temporary. Now restore its true value from the
+ stack. */
+ lwi r18, r1, portR18_OFFSET
+
+ /* Remove the stack frame. */
+ addik r1, r1, portCONTEXT_SIZE
+
+ /* Return using rtid so interrupts are re-enabled as this function is
+ exited. */
+ rtid r14, 0
+ or r0, r0, r0
+
+ .endm
+
+/* This function is used to exit portRESTORE_CONTEXT() if the task being
+returned to last left the Running state by calling taskYIELD() (rather than
+being preempted by an interrupt). */
+ .text
+ .align 4
+exit_from_yield:
+
+ /* r18 was being used as a temporary. Now restore its true value from the
+ stack. */
+ lwi r18, r1, portR18_OFFSET
+
+ /* Remove the stack frame. */
+ addik r1, r1, portCONTEXT_SIZE
+
+ /* Return to the task. */
+ rtsd r14, 0
+ or r0, r0, r0
+
+
+ .text
+ .align 4
+_interrupt_handler:
+
+ portSAVE_CONTEXT
+
+ /* Stack the return address. */
+ swi r14, r1, portR14_OFFSET
+
+ /* Switch to the ISR stack. */
+ lwi r1, r0, pulISRStack
+
+ /* The parameter to the interrupt handler. */
+ ori r5, r0, configINTERRUPT_CONTROLLER_TO_USE
+
+ /* Execute any pending interrupts. */
+ bralid r15, XIntc_DeviceInterruptHandler
+ or r0, r0, r0
+
+ /* See if a new task should be selected to execute. */
+ lwi r18, r0, ulTaskSwitchRequested
+ or r18, r18, r0
+
+ /* If ulTaskSwitchRequested is already zero, then jump straight to
+ restoring the task that is already in the Running state. */
+ beqi r18, task_switch_not_requested
+
+ /* Set ulTaskSwitchRequested back to zero as a task switch is about to be
+ performed. */
+ swi r0, r0, ulTaskSwitchRequested
+
+ /* ulTaskSwitchRequested was not 0 when tested. Select the next task to
+ execute. */
+ bralid r15, vTaskSwitchContext
+ or r0, r0, r0
+
+task_switch_not_requested:
+
+ /* Restore the context of the next task scheduled to execute. */
+ portRESTORE_CONTEXT
+
+
+ .text
+ .align 4
+VPortYieldASM:
+
+ portSAVE_CONTEXT
+
+ /* Modify the return address so a return is done to the instruction after
+ the call to VPortYieldASM. */
+ addi r14, r14, 8
+ swi r14, r1, portR14_OFFSET
+
+ /* Switch to use the ISR stack. */
+ lwi r1, r0, pulISRStack
+
+ /* Select the next task to execute. */
+ bralid r15, vTaskSwitchContext
+ or r0, r0, r0
+
+ /* Restore the context of the next task scheduled to execute. */
+ portRESTORE_CONTEXT
+
+ .text
+ .align 4
+vPortStartFirstTask:
+
+ portRESTORE_CONTEXT
+
+
+
+#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
+
+ .text
+ .align 4
+vPortExceptionHandlerEntry:
+
+ /* Take a copy of the stack pointer before vPortExecptionHandler is called,
+ storing its value prior to the function stack frame being created. */
+ swi r1, r0, pulStackPointerOnFunctionEntry
+ bralid r15, vPortExceptionHandler
+ or r0, r0, r0
+
+#endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */
diff --git a/portable/GCC/MicroBlazeV8/portmacro.h b/portable/GCC/MicroBlazeV8/portmacro.h
index 17166b7..28e5401 100644
--- a/portable/GCC/MicroBlazeV8/portmacro.h
+++ b/portable/GCC/MicroBlazeV8/portmacro.h
@@ -1,370 +1,369 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* BSP includes. */
-#include <mb_interface.h>
-#include <xparameters.h>
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT short
-#define portSTACK_TYPE uint32_t
-#define portBASE_TYPE long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
-#else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
- /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Interrupt control macros and functions. */
-void microblaze_disable_interrupts( void );
-void microblaze_enable_interrupts( void );
-#define portDISABLE_INTERRUPTS() microblaze_disable_interrupts()
-#define portENABLE_INTERRUPTS() microblaze_enable_interrupts()
-/*-----------------------------------------------------------*/
-
-/* Critical section macros. */
-void vPortEnterCritical( void );
-void vPortExitCritical( void );
-#define portENTER_CRITICAL() { \
- extern volatile UBaseType_t uxCriticalNesting; \
- microblaze_disable_interrupts(); \
- uxCriticalNesting++; \
- }
-
-#define portEXIT_CRITICAL() { \
- extern volatile UBaseType_t uxCriticalNesting; \
- /* Interrupts are disabled, so we can */ \
- /* access the variable directly. */ \
- uxCriticalNesting--; \
- if( uxCriticalNesting == 0 ) \
- { \
- /* The nesting has unwound and we \
- can enable interrupts again. */ \
- portENABLE_INTERRUPTS(); \
- } \
- }
-
-/*-----------------------------------------------------------*/
-
-/* The yield macro maps directly to the vPortYield() function. */
-void vPortYield( void );
-#define portYIELD() vPortYield()
-
-/* portYIELD_FROM_ISR() does not directly call vTaskSwitchContext(), but instead
-sets a flag to say that a yield has been requested. The interrupt exit code
-then checks this flag, and calls vTaskSwitchContext() before restoring a task
-context, if the flag is not false. This is done to prevent multiple calls to
-vTaskSwitchContext() being made from a single interrupt, as a single interrupt
-can result in multiple peripherals being serviced. */
-extern volatile uint32_t ulTaskSwitchRequested;
-#define portYIELD_FROM_ISR( x ) do { if( ( x ) != pdFALSE ) ulTaskSwitchRequested = 1; } while( 0 )
-
-#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
-
- /* Generic helper function. */
- __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
- {
- uint8_t ucReturn;
-
- __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );
- return ucReturn;
- }
-
- /* Check the configuration. */
- #if( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
-
- /* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
- /*-----------------------------------------------------------*/
-
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
-
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portBYTE_ALIGNMENT 4
-#define portSTACK_GROWTH ( -1 )
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP() asm volatile ( "NOP" )
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-/* The following structure is used by the FreeRTOS exception handler. It is
-filled with the MicroBlaze context as it was at the time the exception occurred.
-This is done as an aid to debugging exception occurrences. */
-typedef struct PORT_REGISTER_DUMP
-{
- /* The following structure members hold the values of the MicroBlaze
- registers at the time the exception was raised. */
- uint32_t ulR1_SP;
- uint32_t ulR2_small_data_area;
- uint32_t ulR3;
- uint32_t ulR4;
- uint32_t ulR5;
- uint32_t ulR6;
- uint32_t ulR7;
- uint32_t ulR8;
- uint32_t ulR9;
- uint32_t ulR10;
- uint32_t ulR11;
- uint32_t ulR12;
- uint32_t ulR13_read_write_small_data_area;
- uint32_t ulR14_return_address_from_interrupt;
- uint32_t ulR15_return_address_from_subroutine;
- uint32_t ulR16_return_address_from_trap;
- uint32_t ulR17_return_address_from_exceptions; /* The exception entry code will copy the BTR into R17 if the exception occurred in the delay slot of a branch instruction. */
- uint32_t ulR18;
- uint32_t ulR19;
- uint32_t ulR20;
- uint32_t ulR21;
- uint32_t ulR22;
- uint32_t ulR23;
- uint32_t ulR24;
- uint32_t ulR25;
- uint32_t ulR26;
- uint32_t ulR27;
- uint32_t ulR28;
- uint32_t ulR29;
- uint32_t ulR30;
- uint32_t ulR31;
- uint32_t ulPC;
- uint32_t ulESR;
- uint32_t ulMSR;
- uint32_t ulEAR;
- uint32_t ulFSR;
- uint32_t ulEDR;
-
- /* A human readable description of the exception cause. The strings used
- are the same as the #define constant names found in the
- microblaze_exceptions_i.h header file */
- int8_t *pcExceptionCause;
-
- /* The human readable name of the task that was running at the time the
- exception occurred. This is the name that was given to the task when the
- task was created using the FreeRTOS xTaskCreate() API function. */
- char *pcCurrentTaskName;
-
- /* The handle of the task that was running a the time the exception
- occurred. */
- void * xCurrentTaskHandle;
-
-} xPortRegisterDump;
-
-
-/*
- * Installs pxHandler as the interrupt handler for the peripheral specified by
- * the ucInterruptID parameter.
- *
- * ucInterruptID:
- *
- * The ID of the peripheral that will have pxHandler assigned as its interrupt
- * handler. Peripheral IDs are defined in the xparameters.h header file, which
- * is itself part of the BSP project. For example, in the official demo
- * application for this port, xparameters.h defines the following IDs for the
- * four possible interrupt sources:
- *
- * XPAR_INTC_0_UARTLITE_1_VEC_ID - for the UARTlite peripheral.
- * XPAR_INTC_0_TMRCTR_0_VEC_ID - for the AXI Timer 0 peripheral.
- * XPAR_INTC_0_EMACLITE_0_VEC_ID - for the Ethernet lite peripheral.
- * XPAR_INTC_0_GPIO_1_VEC_ID - for the button inputs.
- *
- *
- * pxHandler:
- *
- * A pointer to the interrupt handler function itself. This must be a void
- * function that takes a (void *) parameter.
- *
- *
- * pvCallBackRef:
- *
- * The parameter passed into the handler function. In many cases this will not
- * be used and can be NULL. Some times it is used to pass in a reference to
- * the peripheral instance variable, so it can be accessed from inside the
- * handler function.
- *
- *
- * pdPASS is returned if the function executes successfully. Any other value
- * being returned indicates that the function did not execute correctly.
- */
-BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef );
-
-
-/*
- * Enables the interrupt, within the interrupt controller, for the peripheral
- * specified by the ucInterruptID parameter.
- *
- * ucInterruptID:
- *
- * The ID of the peripheral that will have its interrupt enabled in the
- * interrupt controller. Peripheral IDs are defined in the xparameters.h header
- * file, which is itself part of the BSP project. For example, in the official
- * demo application for this port, xparameters.h defines the following IDs for
- * the four possible interrupt sources:
- *
- * XPAR_INTC_0_UARTLITE_1_VEC_ID - for the UARTlite peripheral.
- * XPAR_INTC_0_TMRCTR_0_VEC_ID - for the AXI Timer 0 peripheral.
- * XPAR_INTC_0_EMACLITE_0_VEC_ID - for the Ethernet lite peripheral.
- * XPAR_INTC_0_GPIO_1_VEC_ID - for the button inputs.
- *
- */
-void vPortEnableInterrupt( uint8_t ucInterruptID );
-
-/*
- * Disables the interrupt, within the interrupt controller, for the peripheral
- * specified by the ucInterruptID parameter.
- *
- * ucInterruptID:
- *
- * The ID of the peripheral that will have its interrupt disabled in the
- * interrupt controller. Peripheral IDs are defined in the xparameters.h header
- * file, which is itself part of the BSP project. For example, in the official
- * demo application for this port, xparameters.h defines the following IDs for
- * the four possible interrupt sources:
- *
- * XPAR_INTC_0_UARTLITE_1_VEC_ID - for the UARTlite peripheral.
- * XPAR_INTC_0_TMRCTR_0_VEC_ID - for the AXI Timer 0 peripheral.
- * XPAR_INTC_0_EMACLITE_0_VEC_ID - for the Ethernet lite peripheral.
- * XPAR_INTC_0_GPIO_1_VEC_ID - for the button inputs.
- *
- */
-void vPortDisableInterrupt( uint8_t ucInterruptID );
-
-/*
- * This is an application defined callback function used to install the tick
- * interrupt handler. It is provided as an application callback because the
- * kernel will run on lots of different MicroBlaze and FPGA configurations - not
- * all of which will have the same timer peripherals defined or available. This
- * example uses the AXI Timer 0. If that is available on your hardware platform
- * then this example callback implementation should not require modification.
- * The name of the interrupt handler that should be installed is vPortTickISR(),
- * which the function below declares as an extern.
- */
-void vApplicationSetupTimerInterrupt( void );
-
-/*
- * This is an application defined callback function used to clear whichever
- * interrupt was installed by the the vApplicationSetupTimerInterrupt() callback
- * function - in this case the interrupt generated by the AXI timer. It is
- * provided as an application callback because the kernel will run on lots of
- * different MicroBlaze and FPGA configurations - not all of which will have the
- * same timer peripherals defined or available. This example uses the AXI Timer 0.
- * If that is available on your hardware platform then this example callback
- * implementation should not require modification provided the example definition
- * of vApplicationSetupTimerInterrupt() is also not modified.
- */
-void vApplicationClearTimerInterrupt( void );
-
-/*
- * vPortExceptionsInstallHandlers() is only available when the MicroBlaze
- * is configured to include exception functionality, and
- * configINSTALL_EXCEPTION_HANDLERS is set to 1 in FreeRTOSConfig.h.
- *
- * vPortExceptionsInstallHandlers() installs the FreeRTOS exception handler
- * for every possible exception cause.
- *
- * vPortExceptionsInstallHandlers() can be called explicitly from application
- * code. After that is done, the default FreeRTOS exception handler that will
- * have been installed can be replaced for any specific exception cause by using
- * the standard Xilinx library function microblaze_register_exception_handler().
- *
- * If vPortExceptionsInstallHandlers() is not called explicitly by the
- * application, it will be called automatically by the kernel the first time
- * xPortInstallInterruptHandler() is called. At that time, any exception
- * handlers that may have already been installed will be replaced.
- *
- * See the description of vApplicationExceptionRegisterDump() for information
- * on the processing performed by the FreeRTOS exception handler.
- */
-void vPortExceptionsInstallHandlers( void );
-
-/*
- * The FreeRTOS exception handler fills an xPortRegisterDump structure (defined
- * in portmacro.h) with the MicroBlaze context, as it was at the time the
- * exception occurred. The exception handler then calls
- * vApplicationExceptionRegisterDump(), passing in the completed
- * xPortRegisterDump structure as its parameter.
- *
- * The FreeRTOS kernel provides its own implementation of
- * vApplicationExceptionRegisterDump(), but the kernel provided implementation
- * is declared as being 'weak'. The weak definition allows the application
- * writer to provide their own implementation, should they wish to use the
- * register dump information. For example, an implementation could be provided
- * that wrote the register dump data to a display, or a UART port.
- */
-void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump );
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* BSP includes. */
+#include <mb_interface.h>
+#include <xparameters.h>
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Interrupt control macros and functions. */
+void microblaze_disable_interrupts( void );
+void microblaze_enable_interrupts( void );
+#define portDISABLE_INTERRUPTS() microblaze_disable_interrupts()
+#define portENABLE_INTERRUPTS() microblaze_enable_interrupts()
+/*-----------------------------------------------------------*/
+
+/* Critical section macros. */
+void vPortEnterCritical( void );
+void vPortExitCritical( void );
+#define portENTER_CRITICAL() { \
+ extern volatile UBaseType_t uxCriticalNesting; \
+ microblaze_disable_interrupts(); \
+ uxCriticalNesting++; \
+ }
+
+#define portEXIT_CRITICAL() { \
+ extern volatile UBaseType_t uxCriticalNesting; \
+ /* Interrupts are disabled, so we can */ \
+ /* access the variable directly. */ \
+ uxCriticalNesting--; \
+ if( uxCriticalNesting == 0 ) \
+ { \
+ /* The nesting has unwound and we \
+ can enable interrupts again. */ \
+ portENABLE_INTERRUPTS(); \
+ } \
+ }
+
+/*-----------------------------------------------------------*/
+
+/* The yield macro maps directly to the vPortYield() function. */
+void vPortYield( void );
+#define portYIELD() vPortYield()
+
+/* portYIELD_FROM_ISR() does not directly call vTaskSwitchContext(), but instead
+sets a flag to say that a yield has been requested. The interrupt exit code
+then checks this flag, and calls vTaskSwitchContext() before restoring a task
+context, if the flag is not false. This is done to prevent multiple calls to
+vTaskSwitchContext() being made from a single interrupt, as a single interrupt
+can result in multiple peripherals being serviced. */
+extern volatile uint32_t ulTaskSwitchRequested;
+#define portYIELD_FROM_ISR( x ) do { if( ( x ) != pdFALSE ) ulTaskSwitchRequested = 1; } while( 0 )
+
+#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+ /* Generic helper function. */
+ __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+ {
+ uint8_t ucReturn;
+
+ __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );
+ return ucReturn;
+ }
+
+ /* Check the configuration. */
+ #if( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
+
+ /* Store/clear the ready priorities in a bit map. */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+ /*-----------------------------------------------------------*/
+
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT 4
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP() asm volatile ( "NOP" )
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+/* The following structure is used by the FreeRTOS exception handler. It is
+filled with the MicroBlaze context as it was at the time the exception occurred.
+This is done as an aid to debugging exception occurrences. */
+typedef struct PORT_REGISTER_DUMP
+{
+ /* The following structure members hold the values of the MicroBlaze
+ registers at the time the exception was raised. */
+ uint32_t ulR1_SP;
+ uint32_t ulR2_small_data_area;
+ uint32_t ulR3;
+ uint32_t ulR4;
+ uint32_t ulR5;
+ uint32_t ulR6;
+ uint32_t ulR7;
+ uint32_t ulR8;
+ uint32_t ulR9;
+ uint32_t ulR10;
+ uint32_t ulR11;
+ uint32_t ulR12;
+ uint32_t ulR13_read_write_small_data_area;
+ uint32_t ulR14_return_address_from_interrupt;
+ uint32_t ulR15_return_address_from_subroutine;
+ uint32_t ulR16_return_address_from_trap;
+ uint32_t ulR17_return_address_from_exceptions; /* The exception entry code will copy the BTR into R17 if the exception occurred in the delay slot of a branch instruction. */
+ uint32_t ulR18;
+ uint32_t ulR19;
+ uint32_t ulR20;
+ uint32_t ulR21;
+ uint32_t ulR22;
+ uint32_t ulR23;
+ uint32_t ulR24;
+ uint32_t ulR25;
+ uint32_t ulR26;
+ uint32_t ulR27;
+ uint32_t ulR28;
+ uint32_t ulR29;
+ uint32_t ulR30;
+ uint32_t ulR31;
+ uint32_t ulPC;
+ uint32_t ulESR;
+ uint32_t ulMSR;
+ uint32_t ulEAR;
+ uint32_t ulFSR;
+ uint32_t ulEDR;
+
+ /* A human readable description of the exception cause. The strings used
+ are the same as the #define constant names found in the
+ microblaze_exceptions_i.h header file */
+ int8_t *pcExceptionCause;
+
+ /* The human readable name of the task that was running at the time the
+ exception occurred. This is the name that was given to the task when the
+ task was created using the FreeRTOS xTaskCreate() API function. */
+ char *pcCurrentTaskName;
+
+ /* The handle of the task that was running a the time the exception
+ occurred. */
+ void * xCurrentTaskHandle;
+
+} xPortRegisterDump;
+
+
+/*
+ * Installs pxHandler as the interrupt handler for the peripheral specified by
+ * the ucInterruptID parameter.
+ *
+ * ucInterruptID:
+ *
+ * The ID of the peripheral that will have pxHandler assigned as its interrupt
+ * handler. Peripheral IDs are defined in the xparameters.h header file, which
+ * is itself part of the BSP project. For example, in the official demo
+ * application for this port, xparameters.h defines the following IDs for the
+ * four possible interrupt sources:
+ *
+ * XPAR_INTC_0_UARTLITE_1_VEC_ID - for the UARTlite peripheral.
+ * XPAR_INTC_0_TMRCTR_0_VEC_ID - for the AXI Timer 0 peripheral.
+ * XPAR_INTC_0_EMACLITE_0_VEC_ID - for the Ethernet lite peripheral.
+ * XPAR_INTC_0_GPIO_1_VEC_ID - for the button inputs.
+ *
+ *
+ * pxHandler:
+ *
+ * A pointer to the interrupt handler function itself. This must be a void
+ * function that takes a (void *) parameter.
+ *
+ *
+ * pvCallBackRef:
+ *
+ * The parameter passed into the handler function. In many cases this will not
+ * be used and can be NULL. Some times it is used to pass in a reference to
+ * the peripheral instance variable, so it can be accessed from inside the
+ * handler function.
+ *
+ *
+ * pdPASS is returned if the function executes successfully. Any other value
+ * being returned indicates that the function did not execute correctly.
+ */
+BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef );
+
+
+/*
+ * Enables the interrupt, within the interrupt controller, for the peripheral
+ * specified by the ucInterruptID parameter.
+ *
+ * ucInterruptID:
+ *
+ * The ID of the peripheral that will have its interrupt enabled in the
+ * interrupt controller. Peripheral IDs are defined in the xparameters.h header
+ * file, which is itself part of the BSP project. For example, in the official
+ * demo application for this port, xparameters.h defines the following IDs for
+ * the four possible interrupt sources:
+ *
+ * XPAR_INTC_0_UARTLITE_1_VEC_ID - for the UARTlite peripheral.
+ * XPAR_INTC_0_TMRCTR_0_VEC_ID - for the AXI Timer 0 peripheral.
+ * XPAR_INTC_0_EMACLITE_0_VEC_ID - for the Ethernet lite peripheral.
+ * XPAR_INTC_0_GPIO_1_VEC_ID - for the button inputs.
+ *
+ */
+void vPortEnableInterrupt( uint8_t ucInterruptID );
+
+/*
+ * Disables the interrupt, within the interrupt controller, for the peripheral
+ * specified by the ucInterruptID parameter.
+ *
+ * ucInterruptID:
+ *
+ * The ID of the peripheral that will have its interrupt disabled in the
+ * interrupt controller. Peripheral IDs are defined in the xparameters.h header
+ * file, which is itself part of the BSP project. For example, in the official
+ * demo application for this port, xparameters.h defines the following IDs for
+ * the four possible interrupt sources:
+ *
+ * XPAR_INTC_0_UARTLITE_1_VEC_ID - for the UARTlite peripheral.
+ * XPAR_INTC_0_TMRCTR_0_VEC_ID - for the AXI Timer 0 peripheral.
+ * XPAR_INTC_0_EMACLITE_0_VEC_ID - for the Ethernet lite peripheral.
+ * XPAR_INTC_0_GPIO_1_VEC_ID - for the button inputs.
+ *
+ */
+void vPortDisableInterrupt( uint8_t ucInterruptID );
+
+/*
+ * This is an application defined callback function used to install the tick
+ * interrupt handler. It is provided as an application callback because the
+ * kernel will run on lots of different MicroBlaze and FPGA configurations - not
+ * all of which will have the same timer peripherals defined or available. This
+ * example uses the AXI Timer 0. If that is available on your hardware platform
+ * then this example callback implementation should not require modification.
+ * The name of the interrupt handler that should be installed is vPortTickISR(),
+ * which the function below declares as an extern.
+ */
+void vApplicationSetupTimerInterrupt( void );
+
+/*
+ * This is an application defined callback function used to clear whichever
+ * interrupt was installed by the the vApplicationSetupTimerInterrupt() callback
+ * function - in this case the interrupt generated by the AXI timer. It is
+ * provided as an application callback because the kernel will run on lots of
+ * different MicroBlaze and FPGA configurations - not all of which will have the
+ * same timer peripherals defined or available. This example uses the AXI Timer 0.
+ * If that is available on your hardware platform then this example callback
+ * implementation should not require modification provided the example definition
+ * of vApplicationSetupTimerInterrupt() is also not modified.
+ */
+void vApplicationClearTimerInterrupt( void );
+
+/*
+ * vPortExceptionsInstallHandlers() is only available when the MicroBlaze
+ * is configured to include exception functionality, and
+ * configINSTALL_EXCEPTION_HANDLERS is set to 1 in FreeRTOSConfig.h.
+ *
+ * vPortExceptionsInstallHandlers() installs the FreeRTOS exception handler
+ * for every possible exception cause.
+ *
+ * vPortExceptionsInstallHandlers() can be called explicitly from application
+ * code. After that is done, the default FreeRTOS exception handler that will
+ * have been installed can be replaced for any specific exception cause by using
+ * the standard Xilinx library function microblaze_register_exception_handler().
+ *
+ * If vPortExceptionsInstallHandlers() is not called explicitly by the
+ * application, it will be called automatically by the kernel the first time
+ * xPortInstallInterruptHandler() is called. At that time, any exception
+ * handlers that may have already been installed will be replaced.
+ *
+ * See the description of vApplicationExceptionRegisterDump() for information
+ * on the processing performed by the FreeRTOS exception handler.
+ */
+void vPortExceptionsInstallHandlers( void );
+
+/*
+ * The FreeRTOS exception handler fills an xPortRegisterDump structure (defined
+ * in portmacro.h) with the MicroBlaze context, as it was at the time the
+ * exception occurred. The exception handler then calls
+ * vApplicationExceptionRegisterDump(), passing in the completed
+ * xPortRegisterDump structure as its parameter.
+ *
+ * The FreeRTOS kernel provides its own implementation of
+ * vApplicationExceptionRegisterDump(), but the kernel provided implementation
+ * is declared as being 'weak'. The weak definition allows the application
+ * writer to provide their own implementation, should they wish to use the
+ * register dump information. For example, an implementation could be provided
+ * that wrote the register dump data to a display, or a UART port.
+ */
+void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump );
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/portable/GCC/MicroBlazeV9/port.c b/portable/GCC/MicroBlazeV9/port.c
index 4f54f99..8018da4 100644
--- a/portable/GCC/MicroBlazeV9/port.c
+++ b/portable/GCC/MicroBlazeV9/port.c
@@ -1,490 +1,490 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the MicroBlaze port.
- *----------------------------------------------------------*/
-
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Standard includes. */
-#include <string.h>
-
-/* Hardware includes. */
-#include <xintc_i.h>
-#include <xil_exception.h>
-#include <microblaze_exceptions_g.h>
-
-/* Tasks are started with a critical section nesting of 0 - however, prior to
-the scheduler being commenced interrupts should not be enabled, so the critical
-nesting variable is initialised to a non-zero value. */
-#define portINITIAL_NESTING_VALUE ( 0xff )
-
-/* The bit within the MSR register that enabled/disables interrupts and
-exceptions respectively. */
-#define portMSR_IE ( 0x02U )
-#define portMSR_EE ( 0x100U )
-
-/* If the floating point unit is included in the MicroBlaze build, then the
-FSR register is saved as part of the task context. portINITIAL_FSR is the value
-given to the FSR register when the initial context is set up for a task being
-created. */
-#define portINITIAL_FSR ( 0U )
-
-/*-----------------------------------------------------------*/
-
-/*
- * Initialise the interrupt controller instance.
- */
-static int32_t prvInitialiseInterruptController( void );
-
-/* Ensure the interrupt controller instance variable is initialised before it is
- * used, and that the initialisation only happens once.
- */
-static int32_t prvEnsureInterruptControllerIsInitialised( void );
-
-/*-----------------------------------------------------------*/
-
-/* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task
-maintains its own count, so this variable is saved as part of the task
-context. */
-volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE;
-
-/* This port uses a separate stack for interrupts. This prevents the stack of
-every task needing to be large enough to hold an entire interrupt stack on top
-of the task stack. */
-uint32_t *pulISRStack;
-
-/* If an interrupt requests a context switch, then ulTaskSwitchRequested will
-get set to 1. ulTaskSwitchRequested is inspected just before the main interrupt
-handler exits. If, at that time, ulTaskSwitchRequested is set to 1, the kernel
-will call vTaskSwitchContext() to ensure the task that runs immediately after
-the interrupt exists is the highest priority task that is able to run. This is
-an unusual mechanism, but is used for this port because a single interrupt can
-cause the servicing of multiple peripherals - and it is inefficient to call
-vTaskSwitchContext() multiple times as each peripheral is serviced. */
-volatile uint32_t ulTaskSwitchRequested = 0UL;
-
-/* The instance of the interrupt controller used by this port. This is required
-by the Xilinx library API functions. */
-static XIntc xInterruptControllerInstance;
-
-/*-----------------------------------------------------------*/
-
-/*
- * Initialise the stack of a task to look exactly as if a call to
- * portSAVE_CONTEXT had been made.
- *
- * See the portable.h header file.
- */
-#if ( portHAS_STACK_OVERFLOW_CHECKING == 1 )
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters )
-#else
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-#endif
-{
-extern void * _SDA2_BASE_;
-extern void * _SDA_BASE_;
-const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
-const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
-extern void _start1( void );
-
- /* Place a few bytes of known values on the bottom of the stack.
- This is essential for the Microblaze port and these lines must
- not be omitted. */
- *pxTopOfStack = ( StackType_t ) 0x00000000;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x00000000;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x00000000;
- pxTopOfStack--;
-
- #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 )
- /* Store the stack limits. */
- *pxTopOfStack = (StackType_t) (pxTopOfStack + 3);
- pxTopOfStack--;
- *pxTopOfStack = (StackType_t) pxEndOfStack;
- pxTopOfStack--;
- #endif
-
- #if( XPAR_MICROBLAZE_USE_FPU != 0 )
- /* The FSR value placed in the initial task context is just 0. */
- *pxTopOfStack = portINITIAL_FSR;
- pxTopOfStack--;
- #endif
-
- /* The MSR value placed in the initial task context should have interrupts
- disabled. Each task will enable interrupts automatically when it enters
- the running state for the first time. */
- *pxTopOfStack = mfmsr() & ~portMSR_IE;
-
- #if( MICROBLAZE_EXCEPTIONS_ENABLED == 1 )
- {
- /* Ensure exceptions are enabled for the task. */
- *pxTopOfStack |= portMSR_EE;
- }
- #endif
-
- pxTopOfStack--;
-
- /* First stack an initial value for the critical section nesting. This
- is initialised to zero. */
- *pxTopOfStack = ( StackType_t ) 0x00;
-
- /* R0 is always zero. */
- /* R1 is the SP. */
-
- /* Place an initial value for all the general purpose registers. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) ulR2; /* R2 - read only small data area. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03; /* R3 - return values and temporaries. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04; /* R4 - return values and temporaries. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pvParameters;/* R5 contains the function call parameters. */
-
- #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06; /* R6 - other parameters and temporaries. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07; /* R7 - other parameters and temporaries. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) NULL; /* R8 - other parameters and temporaries. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09; /* R9 - other parameters and temporaries. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x0a; /* R10 - other parameters and temporaries. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x0b; /* R11 - temporaries. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x0c; /* R12 - temporaries. */
- pxTopOfStack--;
- #else
- pxTopOfStack-= 8;
- #endif
-
- *pxTopOfStack = ( StackType_t ) ulR13; /* R13 - read/write small data area. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode; /* R14 - return address for interrupt. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) _start1; /* R15 - return address for subroutine. */
-
- #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10; /* R16 - return address for trap (debugger). */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11; /* R17 - return address for exceptions, if configured. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12; /* R18 - reserved for assembler and compiler temporaries. */
- pxTopOfStack--;
- #else
- pxTopOfStack -= 4;
- #endif
-
- *pxTopOfStack = ( StackType_t ) 0x00; /* R19 - must be saved across function calls. Callee-save. Seems to be interpreted as the frame pointer. */
-
- #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x14; /* R20 - reserved for storing a pointer to the Global Offset Table (GOT) in Position Independent Code (PIC). Non-volatile in non-PIC code. Must be saved across function calls. Callee-save. Not used by FreeRTOS. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x15; /* R21 - must be saved across function calls. Callee-save. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x16; /* R22 - must be saved across function calls. Callee-save. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x17; /* R23 - must be saved across function calls. Callee-save. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x18; /* R24 - must be saved across function calls. Callee-save. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x19; /* R25 - must be saved across function calls. Callee-save. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x1a; /* R26 - must be saved across function calls. Callee-save. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x1b; /* R27 - must be saved across function calls. Callee-save. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x1c; /* R28 - must be saved across function calls. Callee-save. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x1d; /* R29 - must be saved across function calls. Callee-save. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x1e; /* R30 - must be saved across function calls. Callee-save. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x1f; /* R31 - must be saved across function calls. Callee-save. */
- pxTopOfStack--;
- #else
- pxTopOfStack -= 13;
- #endif
-
- /* Return a pointer to the top of the stack that has been generated so this
- can be stored in the task control block for the task. */
- return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-extern void ( vPortStartFirstTask )( void );
-extern uint32_t _stack[];
-
- /* Setup the hardware to generate the tick. Interrupts are disabled when
- this function is called.
-
- This port uses an application defined callback function to install the tick
- interrupt handler because the kernel will run on lots of different
- MicroBlaze and FPGA configurations - not all of which will have the same
- timer peripherals defined or available. An example definition of
- vApplicationSetupTimerInterrupt() is provided in the official demo
- application that accompanies this port. */
- vApplicationSetupTimerInterrupt();
-
- /* Reuse the stack from main() as the stack for the interrupts/exceptions. */
- pulISRStack = ( uint32_t * ) _stack;
-
- /* Ensure there is enough space for the functions called from the interrupt
- service routines to write back into the stack frame of the caller. */
- pulISRStack -= 2;
-
- /* Restore the context of the first task that is going to run. From here
- on, the created tasks will be executing. */
- vPortStartFirstTask();
-
- /* Should not get here as the tasks are now running! */
- return pdFALSE;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
- /* Not implemented in ports where there is nothing to return to.
- Artificially force an assert. */
- configASSERT( uxCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Manual context switch called by portYIELD or taskYIELD.
- */
-void vPortYield( void )
-{
-extern void VPortYieldASM( void );
-
- /* Perform the context switch in a critical section to assure it is
- not interrupted by the tick ISR. It is not a problem to do this as
- each task maintains its own interrupt status. */
- portENTER_CRITICAL();
- {
- /* Jump directly to the yield function to ensure there is no
- compiler generated prologue code. */
- asm volatile ( "bralid r14, VPortYieldASM \n\t" \
- "or r0, r0, r0 \n\t" );
- }
- portEXIT_CRITICAL();
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnableInterrupt( uint8_t ucInterruptID )
-{
-int32_t lReturn;
-
- /* An API function is provided to enable an interrupt in the interrupt
- controller because the interrupt controller instance variable is private
- to this file. */
- lReturn = prvEnsureInterruptControllerIsInitialised();
- if( lReturn == pdPASS )
- {
- /* Critical section protects read/modify/writer operation inside
- XIntc_Enable(). */
- portENTER_CRITICAL();
- {
- XIntc_Enable( &xInterruptControllerInstance, ucInterruptID );
- }
- portEXIT_CRITICAL();
- }
-
- configASSERT( lReturn == pdPASS );
-}
-/*-----------------------------------------------------------*/
-
-void vPortDisableInterrupt( uint8_t ucInterruptID )
-{
-int32_t lReturn;
-
- /* An API function is provided to disable an interrupt in the interrupt
- controller because the interrupt controller instance variable is private
- to this file. */
- lReturn = prvEnsureInterruptControllerIsInitialised();
-
- if( lReturn == pdPASS )
- {
- XIntc_Disable( &xInterruptControllerInstance, ucInterruptID );
- }
-
- configASSERT( lReturn == pdPASS );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )
-{
-int32_t lReturn;
-
- /* An API function is provided to install an interrupt handler because the
- interrupt controller instance variable is private to this file. */
-
- lReturn = prvEnsureInterruptControllerIsInitialised();
-
- if( lReturn == pdPASS )
- {
- lReturn = XIntc_Connect( &xInterruptControllerInstance, ucInterruptID, pxHandler, pvCallBackRef );
- }
-
- if( lReturn == XST_SUCCESS )
- {
- lReturn = pdPASS;
- }
-
- configASSERT( lReturn == pdPASS );
-
- return lReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vPortRemoveInterruptHandler( uint8_t ucInterruptID )
-{
-int32_t lReturn;
-
- /* An API function is provided to remove an interrupt handler because the
- interrupt controller instance variable is private to this file. */
-
- lReturn = prvEnsureInterruptControllerIsInitialised();
-
- if( lReturn == pdPASS )
- {
- XIntc_Disconnect( &xInterruptControllerInstance, ucInterruptID );
- }
-
- configASSERT( lReturn == pdPASS );
-}
-/*-----------------------------------------------------------*/
-
-static int32_t prvEnsureInterruptControllerIsInitialised( void )
-{
-static int32_t lInterruptControllerInitialised = pdFALSE;
-int32_t lReturn;
-
- /* Ensure the interrupt controller instance variable is initialised before
- it is used, and that the initialisation only happens once. */
- if( lInterruptControllerInitialised != pdTRUE )
- {
- lReturn = prvInitialiseInterruptController();
-
- if( lReturn == pdPASS )
- {
- lInterruptControllerInitialised = pdTRUE;
- }
- }
- else
- {
- lReturn = pdPASS;
- }
-
- return lReturn;
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Handler for the timer interrupt. This is the handler that the application
- * defined callback function vApplicationSetupTimerInterrupt() should install.
- */
-void vPortTickISR( void *pvUnused )
-{
-extern void vApplicationClearTimerInterrupt( void );
-
- /* Ensure the unused parameter does not generate a compiler warning. */
- ( void ) pvUnused;
-
- /* This port uses an application defined callback function to clear the tick
- interrupt because the kernel will run on lots of different MicroBlaze and
- FPGA configurations - not all of which will have the same timer peripherals
- defined or available. An example definition of
- vApplicationClearTimerInterrupt() is provided in the official demo
- application that accompanies this port. */
- vApplicationClearTimerInterrupt();
-
- /* Increment the RTOS tick - this might cause a task to unblock. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- /* Force vTaskSwitchContext() to be called as the interrupt exits. */
- ulTaskSwitchRequested = 1;
- }
-}
-/*-----------------------------------------------------------*/
-
-static int32_t prvInitialiseInterruptController( void )
-{
-int32_t lStatus;
-
- lStatus = XIntc_Initialize( &xInterruptControllerInstance, configINTERRUPT_CONTROLLER_TO_USE );
-
- if( lStatus == XST_SUCCESS )
- {
- /* Initialise the exception table. */
- Xil_ExceptionInit();
-
- /* Service all pending interrupts each time the handler is entered. */
- XIntc_SetIntrSvcOption( xInterruptControllerInstance.BaseAddress, XIN_SVC_ALL_ISRS_OPTION );
-
- /* Install exception handlers if the MicroBlaze is configured to handle
- exceptions, and the application defined constant
- configINSTALL_EXCEPTION_HANDLERS is set to 1. */
- #if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
- {
- vPortExceptionsInstallHandlers();
- }
- #endif /* MICROBLAZE_EXCEPTIONS_ENABLED */
-
- /* Start the interrupt controller. Interrupts are enabled when the
- scheduler starts. */
- lStatus = XIntc_Start( &xInterruptControllerInstance, XIN_REAL_MODE );
-
- if( lStatus == XST_SUCCESS )
- {
- lStatus = pdPASS;
- }
- else
- {
- lStatus = pdFAIL;
- }
- }
-
- configASSERT( lStatus == pdPASS );
-
- return lStatus;
-}
-/*-----------------------------------------------------------*/
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the MicroBlaze port.
+ *----------------------------------------------------------*/
+
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Standard includes. */
+#include <string.h>
+
+/* Hardware includes. */
+#include <xintc_i.h>
+#include <xil_exception.h>
+#include <microblaze_exceptions_g.h>
+
+/* Tasks are started with a critical section nesting of 0 - however, prior to
+the scheduler being commenced interrupts should not be enabled, so the critical
+nesting variable is initialised to a non-zero value. */
+#define portINITIAL_NESTING_VALUE ( 0xff )
+
+/* The bit within the MSR register that enabled/disables interrupts and
+exceptions respectively. */
+#define portMSR_IE ( 0x02U )
+#define portMSR_EE ( 0x100U )
+
+/* If the floating point unit is included in the MicroBlaze build, then the
+FSR register is saved as part of the task context. portINITIAL_FSR is the value
+given to the FSR register when the initial context is set up for a task being
+created. */
+#define portINITIAL_FSR ( 0U )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the interrupt controller instance.
+ */
+static int32_t prvInitialiseInterruptController( void );
+
+/* Ensure the interrupt controller instance variable is initialised before it is
+ * used, and that the initialisation only happens once.
+ */
+static int32_t prvEnsureInterruptControllerIsInitialised( void );
+
+/*-----------------------------------------------------------*/
+
+/* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task
+maintains its own count, so this variable is saved as part of the task
+context. */
+volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE;
+
+/* This port uses a separate stack for interrupts. This prevents the stack of
+every task needing to be large enough to hold an entire interrupt stack on top
+of the task stack. */
+uint32_t *pulISRStack;
+
+/* If an interrupt requests a context switch, then ulTaskSwitchRequested will
+get set to 1. ulTaskSwitchRequested is inspected just before the main interrupt
+handler exits. If, at that time, ulTaskSwitchRequested is set to 1, the kernel
+will call vTaskSwitchContext() to ensure the task that runs immediately after
+the interrupt exists is the highest priority task that is able to run. This is
+an unusual mechanism, but is used for this port because a single interrupt can
+cause the servicing of multiple peripherals - and it is inefficient to call
+vTaskSwitchContext() multiple times as each peripheral is serviced. */
+volatile uint32_t ulTaskSwitchRequested = 0UL;
+
+/* The instance of the interrupt controller used by this port. This is required
+by the Xilinx library API functions. */
+static XIntc xInterruptControllerInstance;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been made.
+ *
+ * See the portable.h header file.
+ */
+#if ( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters )
+#else
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+#endif
+{
+extern void * _SDA2_BASE_;
+extern void * _SDA_BASE_;
+const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
+const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
+extern void _start1( void );
+
+ /* Place a few bytes of known values on the bottom of the stack.
+ This is essential for the Microblaze port and these lines must
+ not be omitted. */
+ *pxTopOfStack = ( StackType_t ) 0x00000000;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x00000000;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x00000000;
+ pxTopOfStack--;
+
+ #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+ /* Store the stack limits. */
+ *pxTopOfStack = (StackType_t) (pxTopOfStack + 3);
+ pxTopOfStack--;
+ *pxTopOfStack = (StackType_t) pxEndOfStack;
+ pxTopOfStack--;
+ #endif
+
+ #if( XPAR_MICROBLAZE_USE_FPU != 0 )
+ /* The FSR value placed in the initial task context is just 0. */
+ *pxTopOfStack = portINITIAL_FSR;
+ pxTopOfStack--;
+ #endif
+
+ /* The MSR value placed in the initial task context should have interrupts
+ disabled. Each task will enable interrupts automatically when it enters
+ the running state for the first time. */
+ *pxTopOfStack = mfmsr() & ~portMSR_IE;
+
+ #if( MICROBLAZE_EXCEPTIONS_ENABLED == 1 )
+ {
+ /* Ensure exceptions are enabled for the task. */
+ *pxTopOfStack |= portMSR_EE;
+ }
+ #endif
+
+ pxTopOfStack--;
+
+ /* First stack an initial value for the critical section nesting. This
+ is initialised to zero. */
+ *pxTopOfStack = ( StackType_t ) 0x00;
+
+ /* R0 is always zero. */
+ /* R1 is the SP. */
+
+ /* Place an initial value for all the general purpose registers. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) ulR2; /* R2 - read only small data area. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03; /* R3 - return values and temporaries. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04; /* R4 - return values and temporaries. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters;/* R5 contains the function call parameters. */
+
+ #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06; /* R6 - other parameters and temporaries. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07; /* R7 - other parameters and temporaries. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) NULL; /* R8 - other parameters and temporaries. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09; /* R9 - other parameters and temporaries. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x0a; /* R10 - other parameters and temporaries. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x0b; /* R11 - temporaries. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x0c; /* R12 - temporaries. */
+ pxTopOfStack--;
+ #else
+ pxTopOfStack-= 8;
+ #endif
+
+ *pxTopOfStack = ( StackType_t ) ulR13; /* R13 - read/write small data area. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* R14 - return address for interrupt. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) _start1; /* R15 - return address for subroutine. */
+
+ #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10; /* R16 - return address for trap (debugger). */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11; /* R17 - return address for exceptions, if configured. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12; /* R18 - reserved for assembler and compiler temporaries. */
+ pxTopOfStack--;
+ #else
+ pxTopOfStack -= 4;
+ #endif
+
+ *pxTopOfStack = ( StackType_t ) 0x00; /* R19 - must be saved across function calls. Callee-save. Seems to be interpreted as the frame pointer. */
+
+ #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x14; /* R20 - reserved for storing a pointer to the Global Offset Table (GOT) in Position Independent Code (PIC). Non-volatile in non-PIC code. Must be saved across function calls. Callee-save. Not used by FreeRTOS. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x15; /* R21 - must be saved across function calls. Callee-save. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x16; /* R22 - must be saved across function calls. Callee-save. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x17; /* R23 - must be saved across function calls. Callee-save. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x18; /* R24 - must be saved across function calls. Callee-save. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x19; /* R25 - must be saved across function calls. Callee-save. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x1a; /* R26 - must be saved across function calls. Callee-save. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x1b; /* R27 - must be saved across function calls. Callee-save. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x1c; /* R28 - must be saved across function calls. Callee-save. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x1d; /* R29 - must be saved across function calls. Callee-save. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x1e; /* R30 - must be saved across function calls. Callee-save. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x1f; /* R31 - must be saved across function calls. Callee-save. */
+ pxTopOfStack--;
+ #else
+ pxTopOfStack -= 13;
+ #endif
+
+ /* Return a pointer to the top of the stack that has been generated so this
+ can be stored in the task control block for the task. */
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void ( vPortStartFirstTask )( void );
+extern uint32_t _stack[];
+
+ /* Setup the hardware to generate the tick. Interrupts are disabled when
+ this function is called.
+
+ This port uses an application defined callback function to install the tick
+ interrupt handler because the kernel will run on lots of different
+ MicroBlaze and FPGA configurations - not all of which will have the same
+ timer peripherals defined or available. An example definition of
+ vApplicationSetupTimerInterrupt() is provided in the official demo
+ application that accompanies this port. */
+ vApplicationSetupTimerInterrupt();
+
+ /* Reuse the stack from main() as the stack for the interrupts/exceptions. */
+ pulISRStack = ( uint32_t * ) _stack;
+
+ /* Ensure there is enough space for the functions called from the interrupt
+ service routines to write back into the stack frame of the caller. */
+ pulISRStack -= 2;
+
+ /* Restore the context of the first task that is going to run. From here
+ on, the created tasks will be executing. */
+ vPortStartFirstTask();
+
+ /* Should not get here as the tasks are now running! */
+ return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+ /* Not implemented in ports where there is nothing to return to.
+ Artificially force an assert. */
+ configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch called by portYIELD or taskYIELD.
+ */
+void vPortYield( void )
+{
+extern void VPortYieldASM( void );
+
+ /* Perform the context switch in a critical section to assure it is
+ not interrupted by the tick ISR. It is not a problem to do this as
+ each task maintains its own interrupt status. */
+ portENTER_CRITICAL();
+ {
+ /* Jump directly to the yield function to ensure there is no
+ compiler generated prologue code. */
+ asm volatile ( "bralid r14, VPortYieldASM \n\t" \
+ "or r0, r0, r0 \n\t" );
+ }
+ portEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnableInterrupt( uint8_t ucInterruptID )
+{
+int32_t lReturn;
+
+ /* An API function is provided to enable an interrupt in the interrupt
+ controller because the interrupt controller instance variable is private
+ to this file. */
+ lReturn = prvEnsureInterruptControllerIsInitialised();
+ if( lReturn == pdPASS )
+ {
+ /* Critical section protects read/modify/writer operation inside
+ XIntc_Enable(). */
+ portENTER_CRITICAL();
+ {
+ XIntc_Enable( &xInterruptControllerInstance, ucInterruptID );
+ }
+ portEXIT_CRITICAL();
+ }
+
+ configASSERT( lReturn == pdPASS );
+}
+/*-----------------------------------------------------------*/
+
+void vPortDisableInterrupt( uint8_t ucInterruptID )
+{
+int32_t lReturn;
+
+ /* An API function is provided to disable an interrupt in the interrupt
+ controller because the interrupt controller instance variable is private
+ to this file. */
+ lReturn = prvEnsureInterruptControllerIsInitialised();
+
+ if( lReturn == pdPASS )
+ {
+ XIntc_Disable( &xInterruptControllerInstance, ucInterruptID );
+ }
+
+ configASSERT( lReturn == pdPASS );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )
+{
+int32_t lReturn;
+
+ /* An API function is provided to install an interrupt handler because the
+ interrupt controller instance variable is private to this file. */
+
+ lReturn = prvEnsureInterruptControllerIsInitialised();
+
+ if( lReturn == pdPASS )
+ {
+ lReturn = XIntc_Connect( &xInterruptControllerInstance, ucInterruptID, pxHandler, pvCallBackRef );
+ }
+
+ if( lReturn == XST_SUCCESS )
+ {
+ lReturn = pdPASS;
+ }
+
+ configASSERT( lReturn == pdPASS );
+
+ return lReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortRemoveInterruptHandler( uint8_t ucInterruptID )
+{
+int32_t lReturn;
+
+ /* An API function is provided to remove an interrupt handler because the
+ interrupt controller instance variable is private to this file. */
+
+ lReturn = prvEnsureInterruptControllerIsInitialised();
+
+ if( lReturn == pdPASS )
+ {
+ XIntc_Disconnect( &xInterruptControllerInstance, ucInterruptID );
+ }
+
+ configASSERT( lReturn == pdPASS );
+}
+/*-----------------------------------------------------------*/
+
+static int32_t prvEnsureInterruptControllerIsInitialised( void )
+{
+static int32_t lInterruptControllerInitialised = pdFALSE;
+int32_t lReturn;
+
+ /* Ensure the interrupt controller instance variable is initialised before
+ it is used, and that the initialisation only happens once. */
+ if( lInterruptControllerInitialised != pdTRUE )
+ {
+ lReturn = prvInitialiseInterruptController();
+
+ if( lReturn == pdPASS )
+ {
+ lInterruptControllerInitialised = pdTRUE;
+ }
+ }
+ else
+ {
+ lReturn = pdPASS;
+ }
+
+ return lReturn;
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Handler for the timer interrupt. This is the handler that the application
+ * defined callback function vApplicationSetupTimerInterrupt() should install.
+ */
+void vPortTickISR( void *pvUnused )
+{
+extern void vApplicationClearTimerInterrupt( void );
+
+ /* Ensure the unused parameter does not generate a compiler warning. */
+ ( void ) pvUnused;
+
+ /* This port uses an application defined callback function to clear the tick
+ interrupt because the kernel will run on lots of different MicroBlaze and
+ FPGA configurations - not all of which will have the same timer peripherals
+ defined or available. An example definition of
+ vApplicationClearTimerInterrupt() is provided in the official demo
+ application that accompanies this port. */
+ vApplicationClearTimerInterrupt();
+
+ /* Increment the RTOS tick - this might cause a task to unblock. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ /* Force vTaskSwitchContext() to be called as the interrupt exits. */
+ ulTaskSwitchRequested = 1;
+ }
+}
+/*-----------------------------------------------------------*/
+
+static int32_t prvInitialiseInterruptController( void )
+{
+int32_t lStatus;
+
+ lStatus = XIntc_Initialize( &xInterruptControllerInstance, configINTERRUPT_CONTROLLER_TO_USE );
+
+ if( lStatus == XST_SUCCESS )
+ {
+ /* Initialise the exception table. */
+ Xil_ExceptionInit();
+
+ /* Service all pending interrupts each time the handler is entered. */
+ XIntc_SetIntrSvcOption( xInterruptControllerInstance.BaseAddress, XIN_SVC_ALL_ISRS_OPTION );
+
+ /* Install exception handlers if the MicroBlaze is configured to handle
+ exceptions, and the application defined constant
+ configINSTALL_EXCEPTION_HANDLERS is set to 1. */
+ #if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
+ {
+ vPortExceptionsInstallHandlers();
+ }
+ #endif /* MICROBLAZE_EXCEPTIONS_ENABLED */
+
+ /* Start the interrupt controller. Interrupts are enabled when the
+ scheduler starts. */
+ lStatus = XIntc_Start( &xInterruptControllerInstance, XIN_REAL_MODE );
+
+ if( lStatus == XST_SUCCESS )
+ {
+ lStatus = pdPASS;
+ }
+ else
+ {
+ lStatus = pdFAIL;
+ }
+ }
+
+ configASSERT( lStatus == pdPASS );
+
+ return lStatus;
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/MicroBlazeV9/port_exceptions.c b/portable/GCC/MicroBlazeV9/port_exceptions.c
index fde2f83..52055fc 100644
--- a/portable/GCC/MicroBlazeV9/port_exceptions.c
+++ b/portable/GCC/MicroBlazeV9/port_exceptions.c
@@ -1,283 +1,280 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Hardware includes. */
-#include <microblaze_exceptions_i.h>
-#include <microblaze_exceptions_g.h>
-
-/* The Xilinx library defined exception entry point stacks a number of
-registers. These definitions are offsets from the stack pointer to the various
-stacked register values. */
-#define portexR3_STACK_OFFSET 4
-#define portexR4_STACK_OFFSET 5
-#define portexR5_STACK_OFFSET 6
-#define portexR6_STACK_OFFSET 7
-#define portexR7_STACK_OFFSET 8
-#define portexR8_STACK_OFFSET 9
-#define portexR9_STACK_OFFSET 10
-#define portexR10_STACK_OFFSET 11
-#define portexR11_STACK_OFFSET 12
-#define portexR12_STACK_OFFSET 13
-#define portexR15_STACK_OFFSET 16
-#define portexR18_STACK_OFFSET 19
-#define portexMSR_STACK_OFFSET 20
-#define portexR19_STACK_OFFSET -1
-
-/* This is defined to equal the size, in bytes, of the stack frame generated by
-the Xilinx standard library exception entry point. It is required to determine
-the stack pointer value prior to the exception being entered. */
-#define portexASM_HANDLER_STACK_FRAME_SIZE 84UL
-
-/* The number of bytes a MicroBlaze instruction consumes. */
-#define portexINSTRUCTION_SIZE 4
-
-/* Exclude this entire file if the MicroBlaze is not configured to handle
-exceptions, or the application defined configuration constant
-configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
-#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
-
-/* This variable is set in the exception entry code, before
-vPortExceptionHandler is called. */
-uint32_t *pulStackPointerOnFunctionEntry = NULL;
-
-/* This is the structure that is filled with the MicroBlaze context as it
-existed immediately prior to the exception occurrence. A pointer to this
-structure is passed into the vApplicationExceptionRegisterDump() callback
-function, if one is defined. */
-static xPortRegisterDump xRegisterDump;
-
-/* This is the FreeRTOS exception handler that is installed for all exception
-types. It is called from vPortExceptionHanlderEntry() - which is itself defined
-in portasm.S. */
-void vPortExceptionHandler( void *pvExceptionID );
-extern void vPortExceptionHandlerEntry( void *pvExceptionID );
-
-/*-----------------------------------------------------------*/
-
-/* vApplicationExceptionRegisterDump() is a callback function that the
-application can optionally define to receive a populated xPortRegisterDump
-structure. If the application chooses not to define a version of
-vApplicationExceptionRegisterDump() then this weekly defined default
-implementation will be called instead. */
-extern void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump ) __attribute__((weak));
-void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump )
-{
- ( void ) xRegisterDump;
-
- for( ;; )
- {
- portNOP();
- }
-}
-/*-----------------------------------------------------------*/
-
-void vPortExceptionHandler( void *pvExceptionID )
-{
-extern void *pxCurrentTCB;
-
- /* Fill an xPortRegisterDump structure with the MicroBlaze context as it
- was immediately before the exception occurrence. */
-
- /* First fill in the name and handle of the task that was in the Running
- state when the exception occurred. */
- xRegisterDump.xCurrentTaskHandle = pxCurrentTCB;
- xRegisterDump.pcCurrentTaskName = pcTaskGetName( NULL );
-
- configASSERT( pulStackPointerOnFunctionEntry );
-
- /* Obtain the values of registers that were stacked prior to this function
- being called, and may have changed since they were stacked. */
- xRegisterDump.ulR3 = pulStackPointerOnFunctionEntry[ portexR3_STACK_OFFSET ];
- xRegisterDump.ulR4 = pulStackPointerOnFunctionEntry[ portexR4_STACK_OFFSET ];
- xRegisterDump.ulR5 = pulStackPointerOnFunctionEntry[ portexR5_STACK_OFFSET ];
- xRegisterDump.ulR6 = pulStackPointerOnFunctionEntry[ portexR6_STACK_OFFSET ];
- xRegisterDump.ulR7 = pulStackPointerOnFunctionEntry[ portexR7_STACK_OFFSET ];
- xRegisterDump.ulR8 = pulStackPointerOnFunctionEntry[ portexR8_STACK_OFFSET ];
- xRegisterDump.ulR9 = pulStackPointerOnFunctionEntry[ portexR9_STACK_OFFSET ];
- xRegisterDump.ulR10 = pulStackPointerOnFunctionEntry[ portexR10_STACK_OFFSET ];
- xRegisterDump.ulR11 = pulStackPointerOnFunctionEntry[ portexR11_STACK_OFFSET ];
- xRegisterDump.ulR12 = pulStackPointerOnFunctionEntry[ portexR12_STACK_OFFSET ];
- xRegisterDump.ulR15_return_address_from_subroutine = pulStackPointerOnFunctionEntry[ portexR15_STACK_OFFSET ];
- xRegisterDump.ulR18 = pulStackPointerOnFunctionEntry[ portexR18_STACK_OFFSET ];
- xRegisterDump.ulR19 = pulStackPointerOnFunctionEntry[ portexR19_STACK_OFFSET ];
- xRegisterDump.ulMSR = pulStackPointerOnFunctionEntry[ portexMSR_STACK_OFFSET ];
-
- /* Obtain the value of all other registers. */
- xRegisterDump.ulR2_small_data_area = mfgpr( R2 );
- xRegisterDump.ulR13_read_write_small_data_area = mfgpr( R13 );
- xRegisterDump.ulR14_return_address_from_interrupt = mfgpr( R14 );
- xRegisterDump.ulR16_return_address_from_trap = mfgpr( R16 );
- xRegisterDump.ulR17_return_address_from_exceptions = mfgpr( R17 );
- xRegisterDump.ulR20 = mfgpr( R20 );
- xRegisterDump.ulR21 = mfgpr( R21 );
- xRegisterDump.ulR22 = mfgpr( R22 );
- xRegisterDump.ulR23 = mfgpr( R23 );
- xRegisterDump.ulR24 = mfgpr( R24 );
- xRegisterDump.ulR25 = mfgpr( R25 );
- xRegisterDump.ulR26 = mfgpr( R26 );
- xRegisterDump.ulR27 = mfgpr( R27 );
- xRegisterDump.ulR28 = mfgpr( R28 );
- xRegisterDump.ulR29 = mfgpr( R29 );
- xRegisterDump.ulR30 = mfgpr( R30 );
- xRegisterDump.ulR31 = mfgpr( R31 );
- xRegisterDump.ulR1_SP = ( ( uint32_t ) pulStackPointerOnFunctionEntry ) + portexASM_HANDLER_STACK_FRAME_SIZE;
- xRegisterDump.ulEAR = mfear();
- xRegisterDump.ulESR = mfesr();
- xRegisterDump.ulEDR = mfedr();
-
- /* Move the saved program counter back to the instruction that was executed
- when the exception occurred. This is only valid for certain types of
- exception. */
- xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_exceptions - portexINSTRUCTION_SIZE;
-
- #if( XPAR_MICROBLAZE_USE_FPU != 0 )
- {
- xRegisterDump.ulFSR = mffsr();
- }
- #else
- {
- xRegisterDump.ulFSR = 0UL;
- }
- #endif
-
- /* Also fill in a string that describes what type of exception this is.
- The string uses the same ID names as defined in the MicroBlaze standard
- library exception header files. */
- switch( ( uint32_t ) pvExceptionID )
- {
- case XEXC_ID_FSL :
- xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FSL";
- break;
-
- case XEXC_ID_UNALIGNED_ACCESS :
- xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_UNALIGNED_ACCESS";
- break;
-
- case XEXC_ID_ILLEGAL_OPCODE :
- xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_ILLEGAL_OPCODE";
- break;
-
- case XEXC_ID_M_AXI_I_EXCEPTION :
- xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_I_EXCEPTION or XEXC_ID_IPLB_EXCEPTION";
- break;
-
- case XEXC_ID_M_AXI_D_EXCEPTION :
- xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_D_EXCEPTION or XEXC_ID_DPLB_EXCEPTION";
- break;
-
- case XEXC_ID_DIV_BY_ZERO :
- xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_DIV_BY_ZERO";
- break;
-
- case XEXC_ID_STACK_VIOLATION :
- xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_STACK_VIOLATION or XEXC_ID_MMU";
- break;
-
- #if( XPAR_MICROBLAZE_USE_FPU != 0 )
-
- case XEXC_ID_FPU :
- xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FPU see ulFSR value";
- break;
-
- #endif /* XPAR_MICROBLAZE_USE_FPU */
- }
-
- /* vApplicationExceptionRegisterDump() is a callback function that the
- application can optionally define to receive the populated xPortRegisterDump
- structure. If the application chooses not to define a version of
- vApplicationExceptionRegisterDump() then the weekly defined default
- implementation within this file will be called instead. */
- vApplicationExceptionRegisterDump( &xRegisterDump );
-
- /* Must not attempt to leave this function! */
- for( ;; )
- {
- portNOP();
- }
-}
-/*-----------------------------------------------------------*/
-
-void vPortExceptionsInstallHandlers( void )
-{
-static uint32_t ulHandlersAlreadyInstalled = pdFALSE;
-
- if( ulHandlersAlreadyInstalled == pdFALSE )
- {
- ulHandlersAlreadyInstalled = pdTRUE;
-
- #if XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS == 1
- microblaze_register_exception_handler( XEXC_ID_UNALIGNED_ACCESS, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_UNALIGNED_ACCESS );
- #endif /* XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS*/
-
- #if XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION == 1
- microblaze_register_exception_handler( XEXC_ID_ILLEGAL_OPCODE, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_ILLEGAL_OPCODE );
- #endif /* XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION */
-
- #if XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION == 1
- microblaze_register_exception_handler( XEXC_ID_M_AXI_I_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_I_EXCEPTION );
- #endif /* XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION */
-
- #if XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION == 1
- microblaze_register_exception_handler( XEXC_ID_M_AXI_D_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_D_EXCEPTION );
- #endif /* XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION */
-
- #if XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION == 1
- microblaze_register_exception_handler( XEXC_ID_IPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_IPLB_EXCEPTION );
- #endif /* XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION */
-
- #if XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION == 1
- microblaze_register_exception_handler( XEXC_ID_DPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DPLB_EXCEPTION );
- #endif /* XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION */
-
- #if XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION == 1
- microblaze_register_exception_handler( XEXC_ID_DIV_BY_ZERO, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DIV_BY_ZERO );
- #endif /* XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION */
-
- #if XPAR_MICROBLAZE_FPU_EXCEPTION == 1
- microblaze_register_exception_handler( XEXC_ID_FPU, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FPU );
- #endif /* XPAR_MICROBLAZE_FPU_EXCEPTION */
-
- #if XPAR_MICROBLAZE_FSL_EXCEPTION == 1
- microblaze_register_exception_handler( XEXC_ID_FSL, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FSL );
- #endif /* XPAR_MICROBLAZE_FSL_EXCEPTION */
-
- microblaze_enable_exceptions();
- }
-}
-
-/* Exclude the entire file if the MicroBlaze is not configured to handle
-exceptions, or the application defined configuration item
-configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
-#endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */
-
-
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Hardware includes. */
+#include <microblaze_exceptions_i.h>
+#include <microblaze_exceptions_g.h>
+
+/* The Xilinx library defined exception entry point stacks a number of
+registers. These definitions are offsets from the stack pointer to the various
+stacked register values. */
+#define portexR3_STACK_OFFSET 4
+#define portexR4_STACK_OFFSET 5
+#define portexR5_STACK_OFFSET 6
+#define portexR6_STACK_OFFSET 7
+#define portexR7_STACK_OFFSET 8
+#define portexR8_STACK_OFFSET 9
+#define portexR9_STACK_OFFSET 10
+#define portexR10_STACK_OFFSET 11
+#define portexR11_STACK_OFFSET 12
+#define portexR12_STACK_OFFSET 13
+#define portexR15_STACK_OFFSET 16
+#define portexR18_STACK_OFFSET 19
+#define portexMSR_STACK_OFFSET 20
+#define portexR19_STACK_OFFSET -1
+
+/* This is defined to equal the size, in bytes, of the stack frame generated by
+the Xilinx standard library exception entry point. It is required to determine
+the stack pointer value prior to the exception being entered. */
+#define portexASM_HANDLER_STACK_FRAME_SIZE 84UL
+
+/* The number of bytes a MicroBlaze instruction consumes. */
+#define portexINSTRUCTION_SIZE 4
+
+/* Exclude this entire file if the MicroBlaze is not configured to handle
+exceptions, or the application defined configuration constant
+configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
+#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
+
+/* This variable is set in the exception entry code, before
+vPortExceptionHandler is called. */
+uint32_t *pulStackPointerOnFunctionEntry = NULL;
+
+/* This is the structure that is filled with the MicroBlaze context as it
+existed immediately prior to the exception occurrence. A pointer to this
+structure is passed into the vApplicationExceptionRegisterDump() callback
+function, if one is defined. */
+static xPortRegisterDump xRegisterDump;
+
+/* This is the FreeRTOS exception handler that is installed for all exception
+types. It is called from vPortExceptionHanlderEntry() - which is itself defined
+in portasm.S. */
+void vPortExceptionHandler( void *pvExceptionID );
+extern void vPortExceptionHandlerEntry( void *pvExceptionID );
+
+/*-----------------------------------------------------------*/
+
+/* vApplicationExceptionRegisterDump() is a callback function that the
+application can optionally define to receive a populated xPortRegisterDump
+structure. If the application chooses not to define a version of
+vApplicationExceptionRegisterDump() then this weekly defined default
+implementation will be called instead. */
+extern void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump ) __attribute__((weak));
+void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump )
+{
+ ( void ) xRegisterDump;
+
+ for( ;; )
+ {
+ portNOP();
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vPortExceptionHandler( void *pvExceptionID )
+{
+extern void *pxCurrentTCB;
+
+ /* Fill an xPortRegisterDump structure with the MicroBlaze context as it
+ was immediately before the exception occurrence. */
+
+ /* First fill in the name and handle of the task that was in the Running
+ state when the exception occurred. */
+ xRegisterDump.xCurrentTaskHandle = pxCurrentTCB;
+ xRegisterDump.pcCurrentTaskName = pcTaskGetName( NULL );
+
+ configASSERT( pulStackPointerOnFunctionEntry );
+
+ /* Obtain the values of registers that were stacked prior to this function
+ being called, and may have changed since they were stacked. */
+ xRegisterDump.ulR3 = pulStackPointerOnFunctionEntry[ portexR3_STACK_OFFSET ];
+ xRegisterDump.ulR4 = pulStackPointerOnFunctionEntry[ portexR4_STACK_OFFSET ];
+ xRegisterDump.ulR5 = pulStackPointerOnFunctionEntry[ portexR5_STACK_OFFSET ];
+ xRegisterDump.ulR6 = pulStackPointerOnFunctionEntry[ portexR6_STACK_OFFSET ];
+ xRegisterDump.ulR7 = pulStackPointerOnFunctionEntry[ portexR7_STACK_OFFSET ];
+ xRegisterDump.ulR8 = pulStackPointerOnFunctionEntry[ portexR8_STACK_OFFSET ];
+ xRegisterDump.ulR9 = pulStackPointerOnFunctionEntry[ portexR9_STACK_OFFSET ];
+ xRegisterDump.ulR10 = pulStackPointerOnFunctionEntry[ portexR10_STACK_OFFSET ];
+ xRegisterDump.ulR11 = pulStackPointerOnFunctionEntry[ portexR11_STACK_OFFSET ];
+ xRegisterDump.ulR12 = pulStackPointerOnFunctionEntry[ portexR12_STACK_OFFSET ];
+ xRegisterDump.ulR15_return_address_from_subroutine = pulStackPointerOnFunctionEntry[ portexR15_STACK_OFFSET ];
+ xRegisterDump.ulR18 = pulStackPointerOnFunctionEntry[ portexR18_STACK_OFFSET ];
+ xRegisterDump.ulR19 = pulStackPointerOnFunctionEntry[ portexR19_STACK_OFFSET ];
+ xRegisterDump.ulMSR = pulStackPointerOnFunctionEntry[ portexMSR_STACK_OFFSET ];
+
+ /* Obtain the value of all other registers. */
+ xRegisterDump.ulR2_small_data_area = mfgpr( R2 );
+ xRegisterDump.ulR13_read_write_small_data_area = mfgpr( R13 );
+ xRegisterDump.ulR14_return_address_from_interrupt = mfgpr( R14 );
+ xRegisterDump.ulR16_return_address_from_trap = mfgpr( R16 );
+ xRegisterDump.ulR17_return_address_from_exceptions = mfgpr( R17 );
+ xRegisterDump.ulR20 = mfgpr( R20 );
+ xRegisterDump.ulR21 = mfgpr( R21 );
+ xRegisterDump.ulR22 = mfgpr( R22 );
+ xRegisterDump.ulR23 = mfgpr( R23 );
+ xRegisterDump.ulR24 = mfgpr( R24 );
+ xRegisterDump.ulR25 = mfgpr( R25 );
+ xRegisterDump.ulR26 = mfgpr( R26 );
+ xRegisterDump.ulR27 = mfgpr( R27 );
+ xRegisterDump.ulR28 = mfgpr( R28 );
+ xRegisterDump.ulR29 = mfgpr( R29 );
+ xRegisterDump.ulR30 = mfgpr( R30 );
+ xRegisterDump.ulR31 = mfgpr( R31 );
+ xRegisterDump.ulR1_SP = ( ( uint32_t ) pulStackPointerOnFunctionEntry ) + portexASM_HANDLER_STACK_FRAME_SIZE;
+ xRegisterDump.ulEAR = mfear();
+ xRegisterDump.ulESR = mfesr();
+ xRegisterDump.ulEDR = mfedr();
+
+ /* Move the saved program counter back to the instruction that was executed
+ when the exception occurred. This is only valid for certain types of
+ exception. */
+ xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_exceptions - portexINSTRUCTION_SIZE;
+
+ #if( XPAR_MICROBLAZE_USE_FPU != 0 )
+ {
+ xRegisterDump.ulFSR = mffsr();
+ }
+ #else
+ {
+ xRegisterDump.ulFSR = 0UL;
+ }
+ #endif
+
+ /* Also fill in a string that describes what type of exception this is.
+ The string uses the same ID names as defined in the MicroBlaze standard
+ library exception header files. */
+ switch( ( uint32_t ) pvExceptionID )
+ {
+ case XEXC_ID_FSL :
+ xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FSL";
+ break;
+
+ case XEXC_ID_UNALIGNED_ACCESS :
+ xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_UNALIGNED_ACCESS";
+ break;
+
+ case XEXC_ID_ILLEGAL_OPCODE :
+ xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_ILLEGAL_OPCODE";
+ break;
+
+ case XEXC_ID_M_AXI_I_EXCEPTION :
+ xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_I_EXCEPTION or XEXC_ID_IPLB_EXCEPTION";
+ break;
+
+ case XEXC_ID_M_AXI_D_EXCEPTION :
+ xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_D_EXCEPTION or XEXC_ID_DPLB_EXCEPTION";
+ break;
+
+ case XEXC_ID_DIV_BY_ZERO :
+ xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_DIV_BY_ZERO";
+ break;
+
+ case XEXC_ID_STACK_VIOLATION :
+ xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_STACK_VIOLATION or XEXC_ID_MMU";
+ break;
+
+ #if( XPAR_MICROBLAZE_USE_FPU != 0 )
+
+ case XEXC_ID_FPU :
+ xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FPU see ulFSR value";
+ break;
+
+ #endif /* XPAR_MICROBLAZE_USE_FPU */
+ }
+
+ /* vApplicationExceptionRegisterDump() is a callback function that the
+ application can optionally define to receive the populated xPortRegisterDump
+ structure. If the application chooses not to define a version of
+ vApplicationExceptionRegisterDump() then the weekly defined default
+ implementation within this file will be called instead. */
+ vApplicationExceptionRegisterDump( &xRegisterDump );
+
+ /* Must not attempt to leave this function! */
+ for( ;; )
+ {
+ portNOP();
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vPortExceptionsInstallHandlers( void )
+{
+static uint32_t ulHandlersAlreadyInstalled = pdFALSE;
+
+ if( ulHandlersAlreadyInstalled == pdFALSE )
+ {
+ ulHandlersAlreadyInstalled = pdTRUE;
+
+ #if XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS == 1
+ microblaze_register_exception_handler( XEXC_ID_UNALIGNED_ACCESS, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_UNALIGNED_ACCESS );
+ #endif /* XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS*/
+
+ #if XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION == 1
+ microblaze_register_exception_handler( XEXC_ID_ILLEGAL_OPCODE, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_ILLEGAL_OPCODE );
+ #endif /* XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION */
+
+ #if XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION == 1
+ microblaze_register_exception_handler( XEXC_ID_M_AXI_I_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_I_EXCEPTION );
+ #endif /* XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION */
+
+ #if XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION == 1
+ microblaze_register_exception_handler( XEXC_ID_M_AXI_D_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_D_EXCEPTION );
+ #endif /* XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION */
+
+ #if XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION == 1
+ microblaze_register_exception_handler( XEXC_ID_IPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_IPLB_EXCEPTION );
+ #endif /* XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION */
+
+ #if XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION == 1
+ microblaze_register_exception_handler( XEXC_ID_DPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DPLB_EXCEPTION );
+ #endif /* XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION */
+
+ #if XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION == 1
+ microblaze_register_exception_handler( XEXC_ID_DIV_BY_ZERO, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DIV_BY_ZERO );
+ #endif /* XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION */
+
+ #if XPAR_MICROBLAZE_FPU_EXCEPTION == 1
+ microblaze_register_exception_handler( XEXC_ID_FPU, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FPU );
+ #endif /* XPAR_MICROBLAZE_FPU_EXCEPTION */
+
+ #if XPAR_MICROBLAZE_FSL_EXCEPTION == 1
+ microblaze_register_exception_handler( XEXC_ID_FSL, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FSL );
+ #endif /* XPAR_MICROBLAZE_FSL_EXCEPTION */
+
+ microblaze_enable_exceptions();
+ }
+}
+
+/* Exclude the entire file if the MicroBlaze is not configured to handle
+exceptions, or the application defined configuration item
+configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
+#endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */
diff --git a/portable/GCC/MicroBlazeV9/portasm.S b/portable/GCC/MicroBlazeV9/portasm.S
index 937b680..2114d00 100644
--- a/portable/GCC/MicroBlazeV9/portasm.S
+++ b/portable/GCC/MicroBlazeV9/portasm.S
@@ -1,376 +1,373 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/* FreeRTOS includes. */
-#include "FreeRTOSConfig.h"
-
-/* Xilinx library includes. */
-#include "microblaze_exceptions_g.h"
-#include "xparameters.h"
-
-/* Offsets from the stack pointer at which saved registers are placed. */
-#define portR31_OFFSET 4
-#define portR30_OFFSET 8
-#define portR29_OFFSET 12
-#define portR28_OFFSET 16
-#define portR27_OFFSET 20
-#define portR26_OFFSET 24
-#define portR25_OFFSET 28
-#define portR24_OFFSET 32
-#define portR23_OFFSET 36
-#define portR22_OFFSET 40
-#define portR21_OFFSET 44
-#define portR20_OFFSET 48
-#define portR19_OFFSET 52
-#define portR18_OFFSET 56
-#define portR17_OFFSET 60
-#define portR16_OFFSET 64
-#define portR15_OFFSET 68
-#define portR14_OFFSET 72
-#define portR13_OFFSET 76
-#define portR12_OFFSET 80
-#define portR11_OFFSET 84
-#define portR10_OFFSET 88
-#define portR9_OFFSET 92
-#define portR8_OFFSET 96
-#define portR7_OFFSET 100
-#define portR6_OFFSET 104
-#define portR5_OFFSET 108
-#define portR4_OFFSET 112
-#define portR3_OFFSET 116
-#define portR2_OFFSET 120
-#define portCRITICAL_NESTING_OFFSET 124
-#define portMSR_OFFSET 128
-
-#if( XPAR_MICROBLAZE_USE_FPU != 0 )
- #define portFSR_OFFSET 132
- #if( XPAR_MICROBLAZE_USE_STACK_PROTECTION )
- #define portSLR_OFFSET 136
- #define portSHR_OFFSET 140
-
- #define portCONTEXT_SIZE 144
- #define portMINUS_CONTEXT_SIZE -144
- #else
- #define portCONTEXT_SIZE 136
- #define portMINUS_CONTEXT_SIZE -136
- #endif
-#else
- #if( XPAR_MICROBLAZE_USE_STACK_PROTECTION )
- #define portSLR_OFFSET 132
- #define portSHR_OFFSET 136
-
- #define portCONTEXT_SIZE 140
- #define portMINUS_CONTEXT_SIZE -140
- #else
- #define portCONTEXT_SIZE 132
- #define portMINUS_CONTEXT_SIZE -132
- #endif
-#endif
-
- .extern pxCurrentTCB
- .extern XIntc_DeviceInterruptHandler
- .extern vTaskSwitchContext
- .extern uxCriticalNesting
- .extern pulISRStack
- .extern ulTaskSwitchRequested
- .extern vPortExceptionHandler
- .extern pulStackPointerOnFunctionEntry
-
- .global _interrupt_handler
- .global VPortYieldASM
- .global vPortStartFirstTask
- .global vPortExceptionHandlerEntry
-
-
-.macro portSAVE_CONTEXT
-
- /* Make room for the context on the stack. */
- addik r1, r1, portMINUS_CONTEXT_SIZE
-
- /* Stack general registers. */
- swi r31, r1, portR31_OFFSET
- swi r30, r1, portR30_OFFSET
- swi r29, r1, portR29_OFFSET
- swi r28, r1, portR28_OFFSET
- swi r27, r1, portR27_OFFSET
- swi r26, r1, portR26_OFFSET
- swi r25, r1, portR25_OFFSET
- swi r24, r1, portR24_OFFSET
- swi r23, r1, portR23_OFFSET
- swi r22, r1, portR22_OFFSET
- swi r21, r1, portR21_OFFSET
- swi r20, r1, portR20_OFFSET
- swi r19, r1, portR19_OFFSET
- swi r18, r1, portR18_OFFSET
- swi r17, r1, portR17_OFFSET
- swi r16, r1, portR16_OFFSET
- swi r15, r1, portR15_OFFSET
- /* R14 is saved later as it needs adjustment if a yield is performed. */
- swi r13, r1, portR13_OFFSET
- swi r12, r1, portR12_OFFSET
- swi r11, r1, portR11_OFFSET
- swi r10, r1, portR10_OFFSET
- swi r9, r1, portR9_OFFSET
- swi r8, r1, portR8_OFFSET
- swi r7, r1, portR7_OFFSET
- swi r6, r1, portR6_OFFSET
- swi r5, r1, portR5_OFFSET
- swi r4, r1, portR4_OFFSET
- swi r3, r1, portR3_OFFSET
- swi r2, r1, portR2_OFFSET
-
- /* Stack the critical section nesting value. */
- lwi r18, r0, uxCriticalNesting
- swi r18, r1, portCRITICAL_NESTING_OFFSET
-
- /* Stack MSR. */
- mfs r18, rmsr
- swi r18, r1, portMSR_OFFSET
-
- #if( XPAR_MICROBLAZE_USE_FPU != 0 )
- /* Stack FSR. */
- mfs r18, rfsr
- swi r18, r1, portFSR_OFFSET
- #endif
-
-#if( XPAR_MICROBLAZE_USE_STACK_PROTECTION )
- /* Save the stack limits */
- mfs r18, rslr
- swi r18, r1, portSLR_OFFSET
- mfs r18, rshr
- swi r18, r1, portSHR_OFFSET
-#endif
-
- /* Save the top of stack value to the TCB. */
- lwi r3, r0, pxCurrentTCB
- sw r1, r0, r3
-
- .endm
-
-.macro portRESTORE_CONTEXT
-
- /* Load the top of stack value from the TCB. */
- lwi r18, r0, pxCurrentTCB
- lw r1, r0, r18
-
-#if( XPAR_MICROBLAZE_USE_STACK_PROTECTION )
- /* Restore the stack limits -- must not load from r1 (Stack Pointer)
- because if the address of load or store instruction is out of range,
- it will trigger Stack Protection Violation exception. */
- or r18, r0, r1
- lwi r12, r18, portSLR_OFFSET
- mts rslr, r12
- lwi r12, r18, portSHR_OFFSET
- mts rshr, r12
-#endif
-
- /* Restore the general registers. */
- lwi r31, r1, portR31_OFFSET
- lwi r30, r1, portR30_OFFSET
- lwi r29, r1, portR29_OFFSET
- lwi r28, r1, portR28_OFFSET
- lwi r27, r1, portR27_OFFSET
- lwi r26, r1, portR26_OFFSET
- lwi r25, r1, portR25_OFFSET
- lwi r24, r1, portR24_OFFSET
- lwi r23, r1, portR23_OFFSET
- lwi r22, r1, portR22_OFFSET
- lwi r21, r1, portR21_OFFSET
- lwi r20, r1, portR20_OFFSET
- lwi r19, r1, portR19_OFFSET
- lwi r17, r1, portR17_OFFSET
- lwi r16, r1, portR16_OFFSET
- lwi r15, r1, portR15_OFFSET
- lwi r14, r1, portR14_OFFSET
- lwi r13, r1, portR13_OFFSET
- lwi r12, r1, portR12_OFFSET
- lwi r11, r1, portR11_OFFSET
- lwi r10, r1, portR10_OFFSET
- lwi r9, r1, portR9_OFFSET
- lwi r8, r1, portR8_OFFSET
- lwi r7, r1, portR7_OFFSET
- lwi r6, r1, portR6_OFFSET
- lwi r5, r1, portR5_OFFSET
- lwi r4, r1, portR4_OFFSET
- lwi r3, r1, portR3_OFFSET
- lwi r2, r1, portR2_OFFSET
-
- /* Reload the rmsr from the stack. */
- lwi r18, r1, portMSR_OFFSET
- mts rmsr, r18
-
- #if( XPAR_MICROBLAZE_USE_FPU != 0 )
- /* Reload the FSR from the stack. */
- lwi r18, r1, portFSR_OFFSET
- mts rfsr, r18
- #endif
-
- /* Load the critical nesting value. */
- lwi r18, r1, portCRITICAL_NESTING_OFFSET
- swi r18, r0, uxCriticalNesting
-
- /* Test the critical nesting value. If it is non zero then the task last
- exited the running state using a yield. If it is zero, then the task
- last exited the running state through an interrupt. */
- xori r18, r18, 0
- bnei r18, exit_from_yield
-
- /* r18 was being used as a temporary. Now restore its true value from the
- stack. */
- lwi r18, r1, portR18_OFFSET
-
- /* Remove the stack frame. */
- addik r1, r1, portCONTEXT_SIZE
-
- /* Return using rtid so interrupts are re-enabled as this function is
- exited. */
- rtid r14, 0
- or r0, r0, r0
-
- .endm
-
-/* This function is used to exit portRESTORE_CONTEXT() if the task being
-returned to last left the Running state by calling taskYIELD() (rather than
-being preempted by an interrupt). */
- .text
- .align 4
-exit_from_yield:
-
- /* r18 was being used as a temporary. Now restore its true value from the
- stack. */
- lwi r18, r1, portR18_OFFSET
-
- /* Remove the stack frame. */
- addik r1, r1, portCONTEXT_SIZE
-
- /* Return to the task. */
- rtsd r14, 0
- or r0, r0, r0
-
-
- .text
- .align 4
-_interrupt_handler:
-
- portSAVE_CONTEXT
-
- /* Stack the return address. */
- swi r14, r1, portR14_OFFSET
-
- /* Switch to the ISR stack. */
- lwi r1, r0, pulISRStack
-
-#if( XPAR_MICROBLAZE_USE_STACK_PROTECTION )
- ori r18, r0, _stack_end
- mts rslr, r18
- ori r18, r0, _stack
- mts rshr, r18
-#endif
-
- /* The parameter to the interrupt handler. */
- ori r5, r0, configINTERRUPT_CONTROLLER_TO_USE
-
- /* Execute any pending interrupts. */
- bralid r15, XIntc_DeviceInterruptHandler
- or r0, r0, r0
-
- /* See if a new task should be selected to execute. */
- lwi r18, r0, ulTaskSwitchRequested
- or r18, r18, r0
-
- /* If ulTaskSwitchRequested is already zero, then jump straight to
- restoring the task that is already in the Running state. */
- beqi r18, task_switch_not_requested
-
- /* Set ulTaskSwitchRequested back to zero as a task switch is about to be
- performed. */
- swi r0, r0, ulTaskSwitchRequested
-
- /* ulTaskSwitchRequested was not 0 when tested. Select the next task to
- execute. */
- bralid r15, vTaskSwitchContext
- or r0, r0, r0
-
-task_switch_not_requested:
-
- /* Restore the context of the next task scheduled to execute. */
- portRESTORE_CONTEXT
-
-
- .text
- .align 4
-VPortYieldASM:
-
- portSAVE_CONTEXT
-
- /* Modify the return address so a return is done to the instruction after
- the call to VPortYieldASM. */
- addi r14, r14, 8
- swi r14, r1, portR14_OFFSET
-
- /* Switch to use the ISR stack. */
- lwi r1, r0, pulISRStack
-
-#if( XPAR_MICROBLAZE_USE_STACK_PROTECTION )
- ori r18, r0, _stack_end
- mts rslr, r18
- ori r18, r0, _stack
- mts rshr, r18
-#endif
-
- /* Select the next task to execute. */
- bralid r15, vTaskSwitchContext
- or r0, r0, r0
-
- /* Restore the context of the next task scheduled to execute. */
- portRESTORE_CONTEXT
-
- .text
- .align 4
-vPortStartFirstTask:
-
- portRESTORE_CONTEXT
-
-
-
-#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
-
- .text
- .align 4
-vPortExceptionHandlerEntry:
-
- /* Take a copy of the stack pointer before vPortExecptionHandler is called,
- storing its value prior to the function stack frame being created. */
- swi r1, r0, pulStackPointerOnFunctionEntry
- bralid r15, vPortExceptionHandler
- or r0, r0, r0
-
-#endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */
-
-
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* FreeRTOS includes. */
+#include "FreeRTOSConfig.h"
+
+/* Xilinx library includes. */
+#include "microblaze_exceptions_g.h"
+#include "xparameters.h"
+
+/* Offsets from the stack pointer at which saved registers are placed. */
+#define portR31_OFFSET 4
+#define portR30_OFFSET 8
+#define portR29_OFFSET 12
+#define portR28_OFFSET 16
+#define portR27_OFFSET 20
+#define portR26_OFFSET 24
+#define portR25_OFFSET 28
+#define portR24_OFFSET 32
+#define portR23_OFFSET 36
+#define portR22_OFFSET 40
+#define portR21_OFFSET 44
+#define portR20_OFFSET 48
+#define portR19_OFFSET 52
+#define portR18_OFFSET 56
+#define portR17_OFFSET 60
+#define portR16_OFFSET 64
+#define portR15_OFFSET 68
+#define portR14_OFFSET 72
+#define portR13_OFFSET 76
+#define portR12_OFFSET 80
+#define portR11_OFFSET 84
+#define portR10_OFFSET 88
+#define portR9_OFFSET 92
+#define portR8_OFFSET 96
+#define portR7_OFFSET 100
+#define portR6_OFFSET 104
+#define portR5_OFFSET 108
+#define portR4_OFFSET 112
+#define portR3_OFFSET 116
+#define portR2_OFFSET 120
+#define portCRITICAL_NESTING_OFFSET 124
+#define portMSR_OFFSET 128
+
+#if( XPAR_MICROBLAZE_USE_FPU != 0 )
+ #define portFSR_OFFSET 132
+ #if( XPAR_MICROBLAZE_USE_STACK_PROTECTION )
+ #define portSLR_OFFSET 136
+ #define portSHR_OFFSET 140
+
+ #define portCONTEXT_SIZE 144
+ #define portMINUS_CONTEXT_SIZE -144
+ #else
+ #define portCONTEXT_SIZE 136
+ #define portMINUS_CONTEXT_SIZE -136
+ #endif
+#else
+ #if( XPAR_MICROBLAZE_USE_STACK_PROTECTION )
+ #define portSLR_OFFSET 132
+ #define portSHR_OFFSET 136
+
+ #define portCONTEXT_SIZE 140
+ #define portMINUS_CONTEXT_SIZE -140
+ #else
+ #define portCONTEXT_SIZE 132
+ #define portMINUS_CONTEXT_SIZE -132
+ #endif
+#endif
+
+ .extern pxCurrentTCB
+ .extern XIntc_DeviceInterruptHandler
+ .extern vTaskSwitchContext
+ .extern uxCriticalNesting
+ .extern pulISRStack
+ .extern ulTaskSwitchRequested
+ .extern vPortExceptionHandler
+ .extern pulStackPointerOnFunctionEntry
+
+ .global _interrupt_handler
+ .global VPortYieldASM
+ .global vPortStartFirstTask
+ .global vPortExceptionHandlerEntry
+
+
+.macro portSAVE_CONTEXT
+
+ /* Make room for the context on the stack. */
+ addik r1, r1, portMINUS_CONTEXT_SIZE
+
+ /* Stack general registers. */
+ swi r31, r1, portR31_OFFSET
+ swi r30, r1, portR30_OFFSET
+ swi r29, r1, portR29_OFFSET
+ swi r28, r1, portR28_OFFSET
+ swi r27, r1, portR27_OFFSET
+ swi r26, r1, portR26_OFFSET
+ swi r25, r1, portR25_OFFSET
+ swi r24, r1, portR24_OFFSET
+ swi r23, r1, portR23_OFFSET
+ swi r22, r1, portR22_OFFSET
+ swi r21, r1, portR21_OFFSET
+ swi r20, r1, portR20_OFFSET
+ swi r19, r1, portR19_OFFSET
+ swi r18, r1, portR18_OFFSET
+ swi r17, r1, portR17_OFFSET
+ swi r16, r1, portR16_OFFSET
+ swi r15, r1, portR15_OFFSET
+ /* R14 is saved later as it needs adjustment if a yield is performed. */
+ swi r13, r1, portR13_OFFSET
+ swi r12, r1, portR12_OFFSET
+ swi r11, r1, portR11_OFFSET
+ swi r10, r1, portR10_OFFSET
+ swi r9, r1, portR9_OFFSET
+ swi r8, r1, portR8_OFFSET
+ swi r7, r1, portR7_OFFSET
+ swi r6, r1, portR6_OFFSET
+ swi r5, r1, portR5_OFFSET
+ swi r4, r1, portR4_OFFSET
+ swi r3, r1, portR3_OFFSET
+ swi r2, r1, portR2_OFFSET
+
+ /* Stack the critical section nesting value. */
+ lwi r18, r0, uxCriticalNesting
+ swi r18, r1, portCRITICAL_NESTING_OFFSET
+
+ /* Stack MSR. */
+ mfs r18, rmsr
+ swi r18, r1, portMSR_OFFSET
+
+ #if( XPAR_MICROBLAZE_USE_FPU != 0 )
+ /* Stack FSR. */
+ mfs r18, rfsr
+ swi r18, r1, portFSR_OFFSET
+ #endif
+
+#if( XPAR_MICROBLAZE_USE_STACK_PROTECTION )
+ /* Save the stack limits */
+ mfs r18, rslr
+ swi r18, r1, portSLR_OFFSET
+ mfs r18, rshr
+ swi r18, r1, portSHR_OFFSET
+#endif
+
+ /* Save the top of stack value to the TCB. */
+ lwi r3, r0, pxCurrentTCB
+ sw r1, r0, r3
+
+ .endm
+
+.macro portRESTORE_CONTEXT
+
+ /* Load the top of stack value from the TCB. */
+ lwi r18, r0, pxCurrentTCB
+ lw r1, r0, r18
+
+#if( XPAR_MICROBLAZE_USE_STACK_PROTECTION )
+ /* Restore the stack limits -- must not load from r1 (Stack Pointer)
+ because if the address of load or store instruction is out of range,
+ it will trigger Stack Protection Violation exception. */
+ or r18, r0, r1
+ lwi r12, r18, portSLR_OFFSET
+ mts rslr, r12
+ lwi r12, r18, portSHR_OFFSET
+ mts rshr, r12
+#endif
+
+ /* Restore the general registers. */
+ lwi r31, r1, portR31_OFFSET
+ lwi r30, r1, portR30_OFFSET
+ lwi r29, r1, portR29_OFFSET
+ lwi r28, r1, portR28_OFFSET
+ lwi r27, r1, portR27_OFFSET
+ lwi r26, r1, portR26_OFFSET
+ lwi r25, r1, portR25_OFFSET
+ lwi r24, r1, portR24_OFFSET
+ lwi r23, r1, portR23_OFFSET
+ lwi r22, r1, portR22_OFFSET
+ lwi r21, r1, portR21_OFFSET
+ lwi r20, r1, portR20_OFFSET
+ lwi r19, r1, portR19_OFFSET
+ lwi r17, r1, portR17_OFFSET
+ lwi r16, r1, portR16_OFFSET
+ lwi r15, r1, portR15_OFFSET
+ lwi r14, r1, portR14_OFFSET
+ lwi r13, r1, portR13_OFFSET
+ lwi r12, r1, portR12_OFFSET
+ lwi r11, r1, portR11_OFFSET
+ lwi r10, r1, portR10_OFFSET
+ lwi r9, r1, portR9_OFFSET
+ lwi r8, r1, portR8_OFFSET
+ lwi r7, r1, portR7_OFFSET
+ lwi r6, r1, portR6_OFFSET
+ lwi r5, r1, portR5_OFFSET
+ lwi r4, r1, portR4_OFFSET
+ lwi r3, r1, portR3_OFFSET
+ lwi r2, r1, portR2_OFFSET
+
+ /* Reload the rmsr from the stack. */
+ lwi r18, r1, portMSR_OFFSET
+ mts rmsr, r18
+
+ #if( XPAR_MICROBLAZE_USE_FPU != 0 )
+ /* Reload the FSR from the stack. */
+ lwi r18, r1, portFSR_OFFSET
+ mts rfsr, r18
+ #endif
+
+ /* Load the critical nesting value. */
+ lwi r18, r1, portCRITICAL_NESTING_OFFSET
+ swi r18, r0, uxCriticalNesting
+
+ /* Test the critical nesting value. If it is non zero then the task last
+ exited the running state using a yield. If it is zero, then the task
+ last exited the running state through an interrupt. */
+ xori r18, r18, 0
+ bnei r18, exit_from_yield
+
+ /* r18 was being used as a temporary. Now restore its true value from the
+ stack. */
+ lwi r18, r1, portR18_OFFSET
+
+ /* Remove the stack frame. */
+ addik r1, r1, portCONTEXT_SIZE
+
+ /* Return using rtid so interrupts are re-enabled as this function is
+ exited. */
+ rtid r14, 0
+ or r0, r0, r0
+
+ .endm
+
+/* This function is used to exit portRESTORE_CONTEXT() if the task being
+returned to last left the Running state by calling taskYIELD() (rather than
+being preempted by an interrupt). */
+ .text
+ .align 4
+exit_from_yield:
+
+ /* r18 was being used as a temporary. Now restore its true value from the
+ stack. */
+ lwi r18, r1, portR18_OFFSET
+
+ /* Remove the stack frame. */
+ addik r1, r1, portCONTEXT_SIZE
+
+ /* Return to the task. */
+ rtsd r14, 0
+ or r0, r0, r0
+
+
+ .text
+ .align 4
+_interrupt_handler:
+
+ portSAVE_CONTEXT
+
+ /* Stack the return address. */
+ swi r14, r1, portR14_OFFSET
+
+ /* Switch to the ISR stack. */
+ lwi r1, r0, pulISRStack
+
+#if( XPAR_MICROBLAZE_USE_STACK_PROTECTION )
+ ori r18, r0, _stack_end
+ mts rslr, r18
+ ori r18, r0, _stack
+ mts rshr, r18
+#endif
+
+ /* The parameter to the interrupt handler. */
+ ori r5, r0, configINTERRUPT_CONTROLLER_TO_USE
+
+ /* Execute any pending interrupts. */
+ bralid r15, XIntc_DeviceInterruptHandler
+ or r0, r0, r0
+
+ /* See if a new task should be selected to execute. */
+ lwi r18, r0, ulTaskSwitchRequested
+ or r18, r18, r0
+
+ /* If ulTaskSwitchRequested is already zero, then jump straight to
+ restoring the task that is already in the Running state. */
+ beqi r18, task_switch_not_requested
+
+ /* Set ulTaskSwitchRequested back to zero as a task switch is about to be
+ performed. */
+ swi r0, r0, ulTaskSwitchRequested
+
+ /* ulTaskSwitchRequested was not 0 when tested. Select the next task to
+ execute. */
+ bralid r15, vTaskSwitchContext
+ or r0, r0, r0
+
+task_switch_not_requested:
+
+ /* Restore the context of the next task scheduled to execute. */
+ portRESTORE_CONTEXT
+
+
+ .text
+ .align 4
+VPortYieldASM:
+
+ portSAVE_CONTEXT
+
+ /* Modify the return address so a return is done to the instruction after
+ the call to VPortYieldASM. */
+ addi r14, r14, 8
+ swi r14, r1, portR14_OFFSET
+
+ /* Switch to use the ISR stack. */
+ lwi r1, r0, pulISRStack
+
+#if( XPAR_MICROBLAZE_USE_STACK_PROTECTION )
+ ori r18, r0, _stack_end
+ mts rslr, r18
+ ori r18, r0, _stack
+ mts rshr, r18
+#endif
+
+ /* Select the next task to execute. */
+ bralid r15, vTaskSwitchContext
+ or r0, r0, r0
+
+ /* Restore the context of the next task scheduled to execute. */
+ portRESTORE_CONTEXT
+
+ .text
+ .align 4
+vPortStartFirstTask:
+
+ portRESTORE_CONTEXT
+
+
+
+#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
+
+ .text
+ .align 4
+vPortExceptionHandlerEntry:
+
+ /* Take a copy of the stack pointer before vPortExecptionHandler is called,
+ storing its value prior to the function stack frame being created. */
+ swi r1, r0, pulStackPointerOnFunctionEntry
+ bralid r15, vPortExceptionHandler
+ or r0, r0, r0
+
+#endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */
diff --git a/portable/GCC/MicroBlazeV9/portmacro.h b/portable/GCC/MicroBlazeV9/portmacro.h
index 3df7d5c..f41205e 100644
--- a/portable/GCC/MicroBlazeV9/portmacro.h
+++ b/portable/GCC/MicroBlazeV9/portmacro.h
@@ -1,375 +1,374 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* BSP includes. */
-#include <mb_interface.h>
-#include <xparameters.h>
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT short
-#define portSTACK_TYPE uint32_t
-#define portBASE_TYPE long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
-#else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
- /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Interrupt control macros and functions. */
-void microblaze_disable_interrupts( void );
-void microblaze_enable_interrupts( void );
-#define portDISABLE_INTERRUPTS() microblaze_disable_interrupts()
-#define portENABLE_INTERRUPTS() microblaze_enable_interrupts()
-/*-----------------------------------------------------------*/
-
-/* Critical section macros. */
-void vPortEnterCritical( void );
-void vPortExitCritical( void );
-#define portENTER_CRITICAL() { \
- extern volatile UBaseType_t uxCriticalNesting; \
- microblaze_disable_interrupts(); \
- uxCriticalNesting++; \
- }
-
-#define portEXIT_CRITICAL() { \
- extern volatile UBaseType_t uxCriticalNesting; \
- /* Interrupts are disabled, so we can */ \
- /* access the variable directly. */ \
- uxCriticalNesting--; \
- if( uxCriticalNesting == 0 ) \
- { \
- /* The nesting has unwound and we \
- can enable interrupts again. */ \
- portENABLE_INTERRUPTS(); \
- } \
- }
-
-/*-----------------------------------------------------------*/
-
-/* The yield macro maps directly to the vPortYield() function. */
-void vPortYield( void );
-#define portYIELD() vPortYield()
-
-/* portYIELD_FROM_ISR() does not directly call vTaskSwitchContext(), but instead
-sets a flag to say that a yield has been requested. The interrupt exit code
-then checks this flag, and calls vTaskSwitchContext() before restoring a task
-context, if the flag is not false. This is done to prevent multiple calls to
-vTaskSwitchContext() being made from a single interrupt, as a single interrupt
-can result in multiple peripherals being serviced. */
-extern volatile uint32_t ulTaskSwitchRequested;
-#define portYIELD_FROM_ISR( x ) do { if( ( x ) != pdFALSE ) ulTaskSwitchRequested = 1; } while( 0 )
-
-#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
-
- /* Generic helper function. */
- __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
- {
- uint8_t ucReturn;
-
- __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );
- return ucReturn;
- }
-
- /* Check the configuration. */
- #if( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
-
- /* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
- /*-----------------------------------------------------------*/
-
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
-
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portBYTE_ALIGNMENT 4
-#define portSTACK_GROWTH ( -1 )
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP() asm volatile ( "NOP" )
-/*-----------------------------------------------------------*/
-
-#if( XPAR_MICROBLAZE_USE_STACK_PROTECTION )
-#define portHAS_STACK_OVERFLOW_CHECKING 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-/* The following structure is used by the FreeRTOS exception handler. It is
-filled with the MicroBlaze context as it was at the time the exception occurred.
-This is done as an aid to debugging exception occurrences. */
-typedef struct PORT_REGISTER_DUMP
-{
- /* The following structure members hold the values of the MicroBlaze
- registers at the time the exception was raised. */
- uint32_t ulR1_SP;
- uint32_t ulR2_small_data_area;
- uint32_t ulR3;
- uint32_t ulR4;
- uint32_t ulR5;
- uint32_t ulR6;
- uint32_t ulR7;
- uint32_t ulR8;
- uint32_t ulR9;
- uint32_t ulR10;
- uint32_t ulR11;
- uint32_t ulR12;
- uint32_t ulR13_read_write_small_data_area;
- uint32_t ulR14_return_address_from_interrupt;
- uint32_t ulR15_return_address_from_subroutine;
- uint32_t ulR16_return_address_from_trap;
- uint32_t ulR17_return_address_from_exceptions; /* The exception entry code will copy the BTR into R17 if the exception occurred in the delay slot of a branch instruction. */
- uint32_t ulR18;
- uint32_t ulR19;
- uint32_t ulR20;
- uint32_t ulR21;
- uint32_t ulR22;
- uint32_t ulR23;
- uint32_t ulR24;
- uint32_t ulR25;
- uint32_t ulR26;
- uint32_t ulR27;
- uint32_t ulR28;
- uint32_t ulR29;
- uint32_t ulR30;
- uint32_t ulR31;
- uint32_t ulPC;
- uint32_t ulESR;
- uint32_t ulMSR;
- uint32_t ulEAR;
- uint32_t ulFSR;
- uint32_t ulEDR;
-
- /* A human readable description of the exception cause. The strings used
- are the same as the #define constant names found in the
- microblaze_exceptions_i.h header file */
- int8_t *pcExceptionCause;
-
- /* The human readable name of the task that was running at the time the
- exception occurred. This is the name that was given to the task when the
- task was created using the FreeRTOS xTaskCreate() API function. */
- char *pcCurrentTaskName;
-
- /* The handle of the task that was running a the time the exception
- occurred. */
- void * xCurrentTaskHandle;
-
-} xPortRegisterDump;
-
-
-/*
- * Installs pxHandler as the interrupt handler for the peripheral specified by
- * the ucInterruptID parameter.
- *
- * ucInterruptID:
- *
- * The ID of the peripheral that will have pxHandler assigned as its interrupt
- * handler. Peripheral IDs are defined in the xparameters.h header file, which
- * is itself part of the BSP project. For example, in the official demo
- * application for this port, xparameters.h defines the following IDs for the
- * four possible interrupt sources:
- *
- * XPAR_INTC_0_UARTLITE_1_VEC_ID - for the UARTlite peripheral.
- * XPAR_INTC_0_TMRCTR_0_VEC_ID - for the AXI Timer 0 peripheral.
- * XPAR_INTC_0_EMACLITE_0_VEC_ID - for the Ethernet lite peripheral.
- * XPAR_INTC_0_GPIO_1_VEC_ID - for the button inputs.
- *
- *
- * pxHandler:
- *
- * A pointer to the interrupt handler function itself. This must be a void
- * function that takes a (void *) parameter.
- *
- *
- * pvCallBackRef:
- *
- * The parameter passed into the handler function. In many cases this will not
- * be used and can be NULL. Some times it is used to pass in a reference to
- * the peripheral instance variable, so it can be accessed from inside the
- * handler function.
- *
- *
- * pdPASS is returned if the function executes successfully. Any other value
- * being returned indicates that the function did not execute correctly.
- */
-BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef );
-
-
-/*
- * Enables the interrupt, within the interrupt controller, for the peripheral
- * specified by the ucInterruptID parameter.
- *
- * ucInterruptID:
- *
- * The ID of the peripheral that will have its interrupt enabled in the
- * interrupt controller. Peripheral IDs are defined in the xparameters.h header
- * file, which is itself part of the BSP project. For example, in the official
- * demo application for this port, xparameters.h defines the following IDs for
- * the four possible interrupt sources:
- *
- * XPAR_INTC_0_UARTLITE_1_VEC_ID - for the UARTlite peripheral.
- * XPAR_INTC_0_TMRCTR_0_VEC_ID - for the AXI Timer 0 peripheral.
- * XPAR_INTC_0_EMACLITE_0_VEC_ID - for the Ethernet lite peripheral.
- * XPAR_INTC_0_GPIO_1_VEC_ID - for the button inputs.
- *
- */
-void vPortEnableInterrupt( uint8_t ucInterruptID );
-
-/*
- * Disables the interrupt, within the interrupt controller, for the peripheral
- * specified by the ucInterruptID parameter.
- *
- * ucInterruptID:
- *
- * The ID of the peripheral that will have its interrupt disabled in the
- * interrupt controller. Peripheral IDs are defined in the xparameters.h header
- * file, which is itself part of the BSP project. For example, in the official
- * demo application for this port, xparameters.h defines the following IDs for
- * the four possible interrupt sources:
- *
- * XPAR_INTC_0_UARTLITE_1_VEC_ID - for the UARTlite peripheral.
- * XPAR_INTC_0_TMRCTR_0_VEC_ID - for the AXI Timer 0 peripheral.
- * XPAR_INTC_0_EMACLITE_0_VEC_ID - for the Ethernet lite peripheral.
- * XPAR_INTC_0_GPIO_1_VEC_ID - for the button inputs.
- *
- */
-void vPortDisableInterrupt( uint8_t ucInterruptID );
-
-/*
- * This is an application defined callback function used to install the tick
- * interrupt handler. It is provided as an application callback because the
- * kernel will run on lots of different MicroBlaze and FPGA configurations - not
- * all of which will have the same timer peripherals defined or available. This
- * example uses the AXI Timer 0. If that is available on your hardware platform
- * then this example callback implementation should not require modification.
- * The name of the interrupt handler that should be installed is vPortTickISR(),
- * which the function below declares as an extern.
- */
-void vApplicationSetupTimerInterrupt( void );
-
-/*
- * This is an application defined callback function used to clear whichever
- * interrupt was installed by the the vApplicationSetupTimerInterrupt() callback
- * function - in this case the interrupt generated by the AXI timer. It is
- * provided as an application callback because the kernel will run on lots of
- * different MicroBlaze and FPGA configurations - not all of which will have the
- * same timer peripherals defined or available. This example uses the AXI Timer 0.
- * If that is available on your hardware platform then this example callback
- * implementation should not require modification provided the example definition
- * of vApplicationSetupTimerInterrupt() is also not modified.
- */
-void vApplicationClearTimerInterrupt( void );
-
-/*
- * vPortExceptionsInstallHandlers() is only available when the MicroBlaze
- * is configured to include exception functionality, and
- * configINSTALL_EXCEPTION_HANDLERS is set to 1 in FreeRTOSConfig.h.
- *
- * vPortExceptionsInstallHandlers() installs the FreeRTOS exception handler
- * for every possible exception cause.
- *
- * vPortExceptionsInstallHandlers() can be called explicitly from application
- * code. After that is done, the default FreeRTOS exception handler that will
- * have been installed can be replaced for any specific exception cause by using
- * the standard Xilinx library function microblaze_register_exception_handler().
- *
- * If vPortExceptionsInstallHandlers() is not called explicitly by the
- * application, it will be called automatically by the kernel the first time
- * xPortInstallInterruptHandler() is called. At that time, any exception
- * handlers that may have already been installed will be replaced.
- *
- * See the description of vApplicationExceptionRegisterDump() for information
- * on the processing performed by the FreeRTOS exception handler.
- */
-void vPortExceptionsInstallHandlers( void );
-
-/*
- * The FreeRTOS exception handler fills an xPortRegisterDump structure (defined
- * in portmacro.h) with the MicroBlaze context, as it was at the time the
- * exception occurred. The exception handler then calls
- * vApplicationExceptionRegisterDump(), passing in the completed
- * xPortRegisterDump structure as its parameter.
- *
- * The FreeRTOS kernel provides its own implementation of
- * vApplicationExceptionRegisterDump(), but the kernel provided implementation
- * is declared as being 'weak'. The weak definition allows the application
- * writer to provide their own implementation, should they wish to use the
- * register dump information. For example, an implementation could be provided
- * that wrote the register dump data to a display, or a UART port.
- */
-void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump );
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* BSP includes. */
+#include <mb_interface.h>
+#include <xparameters.h>
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Interrupt control macros and functions. */
+void microblaze_disable_interrupts( void );
+void microblaze_enable_interrupts( void );
+#define portDISABLE_INTERRUPTS() microblaze_disable_interrupts()
+#define portENABLE_INTERRUPTS() microblaze_enable_interrupts()
+/*-----------------------------------------------------------*/
+
+/* Critical section macros. */
+void vPortEnterCritical( void );
+void vPortExitCritical( void );
+#define portENTER_CRITICAL() { \
+ extern volatile UBaseType_t uxCriticalNesting; \
+ microblaze_disable_interrupts(); \
+ uxCriticalNesting++; \
+ }
+
+#define portEXIT_CRITICAL() { \
+ extern volatile UBaseType_t uxCriticalNesting; \
+ /* Interrupts are disabled, so we can */ \
+ /* access the variable directly. */ \
+ uxCriticalNesting--; \
+ if( uxCriticalNesting == 0 ) \
+ { \
+ /* The nesting has unwound and we \
+ can enable interrupts again. */ \
+ portENABLE_INTERRUPTS(); \
+ } \
+ }
+
+/*-----------------------------------------------------------*/
+
+/* The yield macro maps directly to the vPortYield() function. */
+void vPortYield( void );
+#define portYIELD() vPortYield()
+
+/* portYIELD_FROM_ISR() does not directly call vTaskSwitchContext(), but instead
+sets a flag to say that a yield has been requested. The interrupt exit code
+then checks this flag, and calls vTaskSwitchContext() before restoring a task
+context, if the flag is not false. This is done to prevent multiple calls to
+vTaskSwitchContext() being made from a single interrupt, as a single interrupt
+can result in multiple peripherals being serviced. */
+extern volatile uint32_t ulTaskSwitchRequested;
+#define portYIELD_FROM_ISR( x ) do { if( ( x ) != pdFALSE ) ulTaskSwitchRequested = 1; } while( 0 )
+
+#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+ /* Generic helper function. */
+ __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+ {
+ uint8_t ucReturn;
+
+ __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );
+ return ucReturn;
+ }
+
+ /* Check the configuration. */
+ #if( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
+
+ /* Store/clear the ready priorities in a bit map. */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+ /*-----------------------------------------------------------*/
+
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT 4
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP() asm volatile ( "NOP" )
+/*-----------------------------------------------------------*/
+
+#if( XPAR_MICROBLAZE_USE_STACK_PROTECTION )
+#define portHAS_STACK_OVERFLOW_CHECKING 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+/* The following structure is used by the FreeRTOS exception handler. It is
+filled with the MicroBlaze context as it was at the time the exception occurred.
+This is done as an aid to debugging exception occurrences. */
+typedef struct PORT_REGISTER_DUMP
+{
+ /* The following structure members hold the values of the MicroBlaze
+ registers at the time the exception was raised. */
+ uint32_t ulR1_SP;
+ uint32_t ulR2_small_data_area;
+ uint32_t ulR3;
+ uint32_t ulR4;
+ uint32_t ulR5;
+ uint32_t ulR6;
+ uint32_t ulR7;
+ uint32_t ulR8;
+ uint32_t ulR9;
+ uint32_t ulR10;
+ uint32_t ulR11;
+ uint32_t ulR12;
+ uint32_t ulR13_read_write_small_data_area;
+ uint32_t ulR14_return_address_from_interrupt;
+ uint32_t ulR15_return_address_from_subroutine;
+ uint32_t ulR16_return_address_from_trap;
+ uint32_t ulR17_return_address_from_exceptions; /* The exception entry code will copy the BTR into R17 if the exception occurred in the delay slot of a branch instruction. */
+ uint32_t ulR18;
+ uint32_t ulR19;
+ uint32_t ulR20;
+ uint32_t ulR21;
+ uint32_t ulR22;
+ uint32_t ulR23;
+ uint32_t ulR24;
+ uint32_t ulR25;
+ uint32_t ulR26;
+ uint32_t ulR27;
+ uint32_t ulR28;
+ uint32_t ulR29;
+ uint32_t ulR30;
+ uint32_t ulR31;
+ uint32_t ulPC;
+ uint32_t ulESR;
+ uint32_t ulMSR;
+ uint32_t ulEAR;
+ uint32_t ulFSR;
+ uint32_t ulEDR;
+
+ /* A human readable description of the exception cause. The strings used
+ are the same as the #define constant names found in the
+ microblaze_exceptions_i.h header file */
+ int8_t *pcExceptionCause;
+
+ /* The human readable name of the task that was running at the time the
+ exception occurred. This is the name that was given to the task when the
+ task was created using the FreeRTOS xTaskCreate() API function. */
+ char *pcCurrentTaskName;
+
+ /* The handle of the task that was running a the time the exception
+ occurred. */
+ void * xCurrentTaskHandle;
+
+} xPortRegisterDump;
+
+
+/*
+ * Installs pxHandler as the interrupt handler for the peripheral specified by
+ * the ucInterruptID parameter.
+ *
+ * ucInterruptID:
+ *
+ * The ID of the peripheral that will have pxHandler assigned as its interrupt
+ * handler. Peripheral IDs are defined in the xparameters.h header file, which
+ * is itself part of the BSP project. For example, in the official demo
+ * application for this port, xparameters.h defines the following IDs for the
+ * four possible interrupt sources:
+ *
+ * XPAR_INTC_0_UARTLITE_1_VEC_ID - for the UARTlite peripheral.
+ * XPAR_INTC_0_TMRCTR_0_VEC_ID - for the AXI Timer 0 peripheral.
+ * XPAR_INTC_0_EMACLITE_0_VEC_ID - for the Ethernet lite peripheral.
+ * XPAR_INTC_0_GPIO_1_VEC_ID - for the button inputs.
+ *
+ *
+ * pxHandler:
+ *
+ * A pointer to the interrupt handler function itself. This must be a void
+ * function that takes a (void *) parameter.
+ *
+ *
+ * pvCallBackRef:
+ *
+ * The parameter passed into the handler function. In many cases this will not
+ * be used and can be NULL. Some times it is used to pass in a reference to
+ * the peripheral instance variable, so it can be accessed from inside the
+ * handler function.
+ *
+ *
+ * pdPASS is returned if the function executes successfully. Any other value
+ * being returned indicates that the function did not execute correctly.
+ */
+BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef );
+
+
+/*
+ * Enables the interrupt, within the interrupt controller, for the peripheral
+ * specified by the ucInterruptID parameter.
+ *
+ * ucInterruptID:
+ *
+ * The ID of the peripheral that will have its interrupt enabled in the
+ * interrupt controller. Peripheral IDs are defined in the xparameters.h header
+ * file, which is itself part of the BSP project. For example, in the official
+ * demo application for this port, xparameters.h defines the following IDs for
+ * the four possible interrupt sources:
+ *
+ * XPAR_INTC_0_UARTLITE_1_VEC_ID - for the UARTlite peripheral.
+ * XPAR_INTC_0_TMRCTR_0_VEC_ID - for the AXI Timer 0 peripheral.
+ * XPAR_INTC_0_EMACLITE_0_VEC_ID - for the Ethernet lite peripheral.
+ * XPAR_INTC_0_GPIO_1_VEC_ID - for the button inputs.
+ *
+ */
+void vPortEnableInterrupt( uint8_t ucInterruptID );
+
+/*
+ * Disables the interrupt, within the interrupt controller, for the peripheral
+ * specified by the ucInterruptID parameter.
+ *
+ * ucInterruptID:
+ *
+ * The ID of the peripheral that will have its interrupt disabled in the
+ * interrupt controller. Peripheral IDs are defined in the xparameters.h header
+ * file, which is itself part of the BSP project. For example, in the official
+ * demo application for this port, xparameters.h defines the following IDs for
+ * the four possible interrupt sources:
+ *
+ * XPAR_INTC_0_UARTLITE_1_VEC_ID - for the UARTlite peripheral.
+ * XPAR_INTC_0_TMRCTR_0_VEC_ID - for the AXI Timer 0 peripheral.
+ * XPAR_INTC_0_EMACLITE_0_VEC_ID - for the Ethernet lite peripheral.
+ * XPAR_INTC_0_GPIO_1_VEC_ID - for the button inputs.
+ *
+ */
+void vPortDisableInterrupt( uint8_t ucInterruptID );
+
+/*
+ * This is an application defined callback function used to install the tick
+ * interrupt handler. It is provided as an application callback because the
+ * kernel will run on lots of different MicroBlaze and FPGA configurations - not
+ * all of which will have the same timer peripherals defined or available. This
+ * example uses the AXI Timer 0. If that is available on your hardware platform
+ * then this example callback implementation should not require modification.
+ * The name of the interrupt handler that should be installed is vPortTickISR(),
+ * which the function below declares as an extern.
+ */
+void vApplicationSetupTimerInterrupt( void );
+
+/*
+ * This is an application defined callback function used to clear whichever
+ * interrupt was installed by the the vApplicationSetupTimerInterrupt() callback
+ * function - in this case the interrupt generated by the AXI timer. It is
+ * provided as an application callback because the kernel will run on lots of
+ * different MicroBlaze and FPGA configurations - not all of which will have the
+ * same timer peripherals defined or available. This example uses the AXI Timer 0.
+ * If that is available on your hardware platform then this example callback
+ * implementation should not require modification provided the example definition
+ * of vApplicationSetupTimerInterrupt() is also not modified.
+ */
+void vApplicationClearTimerInterrupt( void );
+
+/*
+ * vPortExceptionsInstallHandlers() is only available when the MicroBlaze
+ * is configured to include exception functionality, and
+ * configINSTALL_EXCEPTION_HANDLERS is set to 1 in FreeRTOSConfig.h.
+ *
+ * vPortExceptionsInstallHandlers() installs the FreeRTOS exception handler
+ * for every possible exception cause.
+ *
+ * vPortExceptionsInstallHandlers() can be called explicitly from application
+ * code. After that is done, the default FreeRTOS exception handler that will
+ * have been installed can be replaced for any specific exception cause by using
+ * the standard Xilinx library function microblaze_register_exception_handler().
+ *
+ * If vPortExceptionsInstallHandlers() is not called explicitly by the
+ * application, it will be called automatically by the kernel the first time
+ * xPortInstallInterruptHandler() is called. At that time, any exception
+ * handlers that may have already been installed will be replaced.
+ *
+ * See the description of vApplicationExceptionRegisterDump() for information
+ * on the processing performed by the FreeRTOS exception handler.
+ */
+void vPortExceptionsInstallHandlers( void );
+
+/*
+ * The FreeRTOS exception handler fills an xPortRegisterDump structure (defined
+ * in portmacro.h) with the MicroBlaze context, as it was at the time the
+ * exception occurred. The exception handler then calls
+ * vApplicationExceptionRegisterDump(), passing in the completed
+ * xPortRegisterDump structure as its parameter.
+ *
+ * The FreeRTOS kernel provides its own implementation of
+ * vApplicationExceptionRegisterDump(), but the kernel provided implementation
+ * is declared as being 'weak'. The weak definition allows the application
+ * writer to provide their own implementation, should they wish to use the
+ * register dump information. For example, an implementation could be provided
+ * that wrote the register dump data to a display, or a UART port.
+ */
+void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump );
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/portable/GCC/NiosII/port.c b/portable/GCC/NiosII/port.c
index cc68ed0..f26e295 100644
--- a/portable/GCC/NiosII/port.c
+++ b/portable/GCC/NiosII/port.c
@@ -1,209 +1,208 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the NIOS2 port.
- *----------------------------------------------------------*/
-
-/* Standard Includes. */
-#include <string.h>
-#include <errno.h>
-
-/* Altera includes. */
-#include "sys/alt_irq.h"
-#include "sys/alt_exceptions.h"
-#include "altera_avalon_timer_regs.h"
-#include "priv/alt_irq_table.h"
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Interrupts are enabled. */
-#define portINITIAL_ESTATUS ( StackType_t ) 0x01
-
-int _alt_ic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr,
- void *isr_context, void *flags);
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the timer to generate the tick interrupts.
- */
-static void prvSetupTimerInterrupt( void );
-
-/*
- * Call back for the alarm function.
- */
-void vPortSysTickHandler( void * context);
-
-/*-----------------------------------------------------------*/
-
-static void prvReadGp( uint32_t *ulValue )
-{
- asm( "stw gp, (%0)" :: "r"(ulValue) );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-StackType_t *pxFramePointer = pxTopOfStack - 1;
-StackType_t xGlobalPointer;
-
- prvReadGp( &xGlobalPointer );
-
- /* End of stack marker. */
- *pxTopOfStack = 0xdeadbeef;
- pxTopOfStack--;
-
- *pxTopOfStack = ( StackType_t ) pxFramePointer;
- pxTopOfStack--;
-
- *pxTopOfStack = xGlobalPointer;
-
- /* Space for R23 to R16. */
- pxTopOfStack -= 9;
-
- *pxTopOfStack = ( StackType_t ) pxCode;
- pxTopOfStack--;
-
- *pxTopOfStack = portINITIAL_ESTATUS;
-
- /* Space for R15 to R5. */
- pxTopOfStack -= 12;
-
- *pxTopOfStack = ( StackType_t ) pvParameters;
-
- /* Space for R3 to R1, muldiv and RA. */
- pxTopOfStack -= 5;
-
- return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-BaseType_t xPortStartScheduler( void )
-{
- /* Start the timer that generates the tick ISR. Interrupts are disabled
- here already. */
- prvSetupTimerInterrupt();
-
- /* Start the first task. */
- asm volatile ( " movia r2, restore_sp_from_pxCurrentTCB \n"
- " jmp r2 " );
-
- /* Should not get here! */
- return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
- /* It is unlikely that the NIOS2 port will require this function as there
- is nothing to return to. */
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the systick timer to generate the tick interrupts at the required
- * frequency.
- */
-void prvSetupTimerInterrupt( void )
-{
- /* Try to register the interrupt handler. */
- if ( -EINVAL == _alt_ic_isr_register( SYS_CLK_IRQ_INTERRUPT_CONTROLLER_ID, SYS_CLK_IRQ, vPortSysTickHandler, 0x0, 0x0 ) )
- {
- /* Failed to install the Interrupt Handler. */
- asm( "break" );
- }
- else
- {
- /* Configure SysTick to interrupt at the requested rate. */
- IOWR_ALTERA_AVALON_TIMER_CONTROL( SYS_CLK_BASE, ALTERA_AVALON_TIMER_CONTROL_STOP_MSK );
- IOWR_ALTERA_AVALON_TIMER_PERIODL( SYS_CLK_BASE, ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) & 0xFFFF );
- IOWR_ALTERA_AVALON_TIMER_PERIODH( SYS_CLK_BASE, ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) >> 16 );
- IOWR_ALTERA_AVALON_TIMER_CONTROL( SYS_CLK_BASE, ALTERA_AVALON_TIMER_CONTROL_CONT_MSK | ALTERA_AVALON_TIMER_CONTROL_START_MSK | ALTERA_AVALON_TIMER_CONTROL_ITO_MSK );
- }
-
- /* Clear any already pending interrupts generated by the Timer. */
- IOWR_ALTERA_AVALON_TIMER_STATUS( SYS_CLK_BASE, ~ALTERA_AVALON_TIMER_STATUS_TO_MSK );
-}
-/*-----------------------------------------------------------*/
-
-void vPortSysTickHandler( void * context)
-{
- /* Increment the kernel tick. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- vTaskSwitchContext();
- }
-
- /* Clear the interrupt. */
- IOWR_ALTERA_AVALON_TIMER_STATUS( SYS_CLK_BASE, ~ALTERA_AVALON_TIMER_STATUS_TO_MSK );
-}
-/*-----------------------------------------------------------*/
-
-/** This function is a re-implementation of the Altera provided function.
- * The function is re-implemented to prevent it from enabling an interrupt
- * when it is registered. Interrupts should only be enabled after the FreeRTOS.org
- * kernel has its scheduler started so that contexts are saved and switched
- * correctly.
- */
-int _alt_ic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr,
- void *isr_context, void *flags)
-{
- int rc = -EINVAL;
- alt_irq_context status;
- int id = irq; /* IRQ interpreted as the interrupt ID. */
-
- if (id < ALT_NIRQ)
- {
- /*
- * interrupts are disabled while the handler tables are updated to ensure
- * that an interrupt doesn't occur while the tables are in an inconsistant
- * state.
- */
-
- status = alt_irq_disable_all ();
-
- alt_irq[id].handler = isr;
- alt_irq[id].context = isr_context;
-
- rc = (isr) ? alt_ic_irq_enable(ic_id, id) : alt_ic_irq_disable(ic_id, id);
-
- /* alt_irq_enable_all(status); This line is removed to prevent the interrupt from being immediately enabled. */
- }
-
- return rc;
-}
-/*-----------------------------------------------------------*/
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the NIOS2 port.
+ *----------------------------------------------------------*/
+
+/* Standard Includes. */
+#include <string.h>
+#include <errno.h>
+
+/* Altera includes. */
+#include "sys/alt_irq.h"
+#include "sys/alt_exceptions.h"
+#include "altera_avalon_timer_regs.h"
+#include "priv/alt_irq_table.h"
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Interrupts are enabled. */
+#define portINITIAL_ESTATUS ( StackType_t ) 0x01
+
+int _alt_ic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr,
+ void *isr_context, void *flags);
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the timer to generate the tick interrupts.
+ */
+static void prvSetupTimerInterrupt( void );
+
+/*
+ * Call back for the alarm function.
+ */
+void vPortSysTickHandler( void * context);
+
+/*-----------------------------------------------------------*/
+
+static void prvReadGp( uint32_t *ulValue )
+{
+ asm( "stw gp, (%0)" :: "r"(ulValue) );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+StackType_t *pxFramePointer = pxTopOfStack - 1;
+StackType_t xGlobalPointer;
+
+ prvReadGp( &xGlobalPointer );
+
+ /* End of stack marker. */
+ *pxTopOfStack = 0xdeadbeef;
+ pxTopOfStack--;
+
+ *pxTopOfStack = ( StackType_t ) pxFramePointer;
+ pxTopOfStack--;
+
+ *pxTopOfStack = xGlobalPointer;
+
+ /* Space for R23 to R16. */
+ pxTopOfStack -= 9;
+
+ *pxTopOfStack = ( StackType_t ) pxCode;
+ pxTopOfStack--;
+
+ *pxTopOfStack = portINITIAL_ESTATUS;
+
+ /* Space for R15 to R5. */
+ pxTopOfStack -= 12;
+
+ *pxTopOfStack = ( StackType_t ) pvParameters;
+
+ /* Space for R3 to R1, muldiv and RA. */
+ pxTopOfStack -= 5;
+
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ here already. */
+ prvSetupTimerInterrupt();
+
+ /* Start the first task. */
+ asm volatile ( " movia r2, restore_sp_from_pxCurrentTCB \n"
+ " jmp r2 " );
+
+ /* Should not get here! */
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+ /* It is unlikely that the NIOS2 port will require this function as there
+ is nothing to return to. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+void prvSetupTimerInterrupt( void )
+{
+ /* Try to register the interrupt handler. */
+ if ( -EINVAL == _alt_ic_isr_register( SYS_CLK_IRQ_INTERRUPT_CONTROLLER_ID, SYS_CLK_IRQ, vPortSysTickHandler, 0x0, 0x0 ) )
+ {
+ /* Failed to install the Interrupt Handler. */
+ asm( "break" );
+ }
+ else
+ {
+ /* Configure SysTick to interrupt at the requested rate. */
+ IOWR_ALTERA_AVALON_TIMER_CONTROL( SYS_CLK_BASE, ALTERA_AVALON_TIMER_CONTROL_STOP_MSK );
+ IOWR_ALTERA_AVALON_TIMER_PERIODL( SYS_CLK_BASE, ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) & 0xFFFF );
+ IOWR_ALTERA_AVALON_TIMER_PERIODH( SYS_CLK_BASE, ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) >> 16 );
+ IOWR_ALTERA_AVALON_TIMER_CONTROL( SYS_CLK_BASE, ALTERA_AVALON_TIMER_CONTROL_CONT_MSK | ALTERA_AVALON_TIMER_CONTROL_START_MSK | ALTERA_AVALON_TIMER_CONTROL_ITO_MSK );
+ }
+
+ /* Clear any already pending interrupts generated by the Timer. */
+ IOWR_ALTERA_AVALON_TIMER_STATUS( SYS_CLK_BASE, ~ALTERA_AVALON_TIMER_STATUS_TO_MSK );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSysTickHandler( void * context)
+{
+ /* Increment the kernel tick. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ vTaskSwitchContext();
+ }
+
+ /* Clear the interrupt. */
+ IOWR_ALTERA_AVALON_TIMER_STATUS( SYS_CLK_BASE, ~ALTERA_AVALON_TIMER_STATUS_TO_MSK );
+}
+/*-----------------------------------------------------------*/
+
+/** This function is a re-implementation of the Altera provided function.
+ * The function is re-implemented to prevent it from enabling an interrupt
+ * when it is registered. Interrupts should only be enabled after the FreeRTOS.org
+ * kernel has its scheduler started so that contexts are saved and switched
+ * correctly.
+ */
+int _alt_ic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr,
+ void *isr_context, void *flags)
+{
+ int rc = -EINVAL;
+ alt_irq_context status;
+ int id = irq; /* IRQ interpreted as the interrupt ID. */
+
+ if (id < ALT_NIRQ)
+ {
+ /*
+ * interrupts are disabled while the handler tables are updated to ensure
+ * that an interrupt doesn't occur while the tables are in an inconsistant
+ * state.
+ */
+
+ status = alt_irq_disable_all ();
+
+ alt_irq[id].handler = isr;
+ alt_irq[id].context = isr_context;
+
+ rc = (isr) ? alt_ic_irq_enable(ic_id, id) : alt_ic_irq_disable(ic_id, id);
+
+ /* alt_irq_enable_all(status); This line is removed to prevent the interrupt from being immediately enabled. */
+ }
+
+ return rc;
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/NiosII/port_asm.S b/portable/GCC/NiosII/port_asm.S
index a28677e..80117e5 100644
--- a/portable/GCC/NiosII/port_asm.S
+++ b/portable/GCC/NiosII/port_asm.S
@@ -1,140 +1,139 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-.extern vTaskSwitchContext
-
-.set noat
-
-# Exported to start the first task.
-.globl restore_sp_from_pxCurrentTCB
-
-# Entry point for exceptions.
-.section .exceptions.entry.user, "xa"
-
-# Save the entire context of a task.
-save_context:
- addi sp, sp, -116 # Create space on the stack.
- stw ra, 0(sp)
- # Leave a gap for muldiv 0
- stw at, 8(sp)
- stw r2, 12(sp)
- stw r3, 16(sp)
- stw r4, 20(sp)
- stw r5, 24(sp)
- stw r6, 28(sp)
- stw r7, 32(sp)
- stw r8, 36(sp)
- stw r9, 40(sp)
- stw r10, 44(sp)
- stw r11, 48(sp)
- stw r12, 52(sp)
- stw r13, 56(sp)
- stw r14, 60(sp)
- stw r15, 64(sp)
- rdctl r5, estatus # Save the eStatus
- stw r5, 68(sp)
- addi r15, ea, -4 # Instruction that caused exception
- stw r15, 72(sp) # Save as EA
- stw r16, 76(sp) # Save the remaining registers
- stw r17, 80(sp)
- stw r18, 84(sp)
- stw r19, 88(sp)
- stw r20, 92(sp)
- stw r21, 96(sp)
- stw r22, 100(sp)
- stw r23, 104(sp)
- stw gp, 108(sp)
- stw fp, 112(sp)
-
-save_sp_to_pxCurrentTCB:
- movia et, pxCurrentTCB # Load the address of the pxCurrentTCB pointer
- ldw et, (et) # Load the value of the pxCurrentTCB pointer
- stw sp, (et) # Store the stack pointer into the top of the TCB
-
- br irq_test_user # skip the section .exceptions.entry
-
- .section .exceptions.irqtest, "xa"
-irq_test_user:
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
- .section .exceptions.exit.user, "xa"
-restore_sp_from_pxCurrentTCB:
- movia et, pxCurrentTCB # Load the address of the pxCurrentTCB pointer
- ldw et, (et) # Load the value of the pxCurrentTCB pointer
- ldw sp, (et) # Load the stack pointer with the top value of the TCB
-
-restore_context:
- ldw ra, 0(sp) # Restore the registers.
- # Leave a gap for muldiv 0.
- ldw at, 8(sp)
- ldw r2, 12(sp)
- ldw r3, 16(sp)
- ldw r4, 20(sp)
- ldw r5, 24(sp)
- ldw r6, 28(sp)
- ldw r7, 32(sp)
- ldw r8, 36(sp)
- ldw r9, 40(sp)
- ldw r10, 44(sp)
- ldw r11, 48(sp)
- ldw r12, 52(sp)
- ldw r13, 56(sp)
- ldw r14, 60(sp)
- ldw r15, 64(sp)
- ldw et, 68(sp) # Load the eStatus
- wrctl estatus, et # Write the eStatus
- ldw ea, 72(sp) # Load the Program Counter
- ldw r16, 76(sp)
- ldw r17, 80(sp)
- ldw r18, 84(sp)
- ldw r19, 88(sp)
- ldw r20, 92(sp)
- ldw r21, 96(sp)
- ldw r22, 100(sp)
- ldw r23, 104(sp)
- ldw gp, 108(sp)
- ldw fp, 112(sp)
- addi sp, sp, 116 # Release stack space
-
- eret # Return to address ea, loading eStatus into Status.
-
- .section .exceptions.soft, "xa"
-soft_exceptions:
- movhi r3, 0x003b /* upper half of trap opcode */
- ori r3, r3, 0x683a /* lower half of trap opcode */
- beq r2, r3, call_scheduler
- br exceptions_unknown_user # its something else
-
-call_scheduler:
- stw ea, 72(sp) # EA is PC+4 so will skip over instruction causing exception
- movia r15, vTaskSwitchContext # Pick the next context - use long call version in place of "call"
- callr r15
- br restore_sp_from_pxCurrentTCB # Switch in the task context and restore.
-
- .section .exceptions.unknown.user
-exceptions_unknown_user:
-
+.extern vTaskSwitchContext
+
+.set noat
+
+# Exported to start the first task.
+.globl restore_sp_from_pxCurrentTCB
+
+# Entry point for exceptions.
+.section .exceptions.entry.user, "xa"
+
+# Save the entire context of a task.
+save_context:
+ addi sp, sp, -116 # Create space on the stack.
+ stw ra, 0(sp)
+ # Leave a gap for muldiv 0
+ stw at, 8(sp)
+ stw r2, 12(sp)
+ stw r3, 16(sp)
+ stw r4, 20(sp)
+ stw r5, 24(sp)
+ stw r6, 28(sp)
+ stw r7, 32(sp)
+ stw r8, 36(sp)
+ stw r9, 40(sp)
+ stw r10, 44(sp)
+ stw r11, 48(sp)
+ stw r12, 52(sp)
+ stw r13, 56(sp)
+ stw r14, 60(sp)
+ stw r15, 64(sp)
+ rdctl r5, estatus # Save the eStatus
+ stw r5, 68(sp)
+ addi r15, ea, -4 # Instruction that caused exception
+ stw r15, 72(sp) # Save as EA
+ stw r16, 76(sp) # Save the remaining registers
+ stw r17, 80(sp)
+ stw r18, 84(sp)
+ stw r19, 88(sp)
+ stw r20, 92(sp)
+ stw r21, 96(sp)
+ stw r22, 100(sp)
+ stw r23, 104(sp)
+ stw gp, 108(sp)
+ stw fp, 112(sp)
+
+save_sp_to_pxCurrentTCB:
+ movia et, pxCurrentTCB # Load the address of the pxCurrentTCB pointer
+ ldw et, (et) # Load the value of the pxCurrentTCB pointer
+ stw sp, (et) # Store the stack pointer into the top of the TCB
+
+ br irq_test_user # skip the section .exceptions.entry
+
+ .section .exceptions.irqtest, "xa"
+irq_test_user:
+
+ .section .exceptions.exit.user, "xa"
+restore_sp_from_pxCurrentTCB:
+ movia et, pxCurrentTCB # Load the address of the pxCurrentTCB pointer
+ ldw et, (et) # Load the value of the pxCurrentTCB pointer
+ ldw sp, (et) # Load the stack pointer with the top value of the TCB
+
+restore_context:
+ ldw ra, 0(sp) # Restore the registers.
+ # Leave a gap for muldiv 0.
+ ldw at, 8(sp)
+ ldw r2, 12(sp)
+ ldw r3, 16(sp)
+ ldw r4, 20(sp)
+ ldw r5, 24(sp)
+ ldw r6, 28(sp)
+ ldw r7, 32(sp)
+ ldw r8, 36(sp)
+ ldw r9, 40(sp)
+ ldw r10, 44(sp)
+ ldw r11, 48(sp)
+ ldw r12, 52(sp)
+ ldw r13, 56(sp)
+ ldw r14, 60(sp)
+ ldw r15, 64(sp)
+ ldw et, 68(sp) # Load the eStatus
+ wrctl estatus, et # Write the eStatus
+ ldw ea, 72(sp) # Load the Program Counter
+ ldw r16, 76(sp)
+ ldw r17, 80(sp)
+ ldw r18, 84(sp)
+ ldw r19, 88(sp)
+ ldw r20, 92(sp)
+ ldw r21, 96(sp)
+ ldw r22, 100(sp)
+ ldw r23, 104(sp)
+ ldw gp, 108(sp)
+ ldw fp, 112(sp)
+ addi sp, sp, 116 # Release stack space
+
+ eret # Return to address ea, loading eStatus into Status.
+
+ .section .exceptions.soft, "xa"
+soft_exceptions:
+ movhi r3, 0x003b /* upper half of trap opcode */
+ ori r3, r3, 0x683a /* lower half of trap opcode */
+ beq r2, r3, call_scheduler
+ br exceptions_unknown_user # its something else
+
+call_scheduler:
+ stw ea, 72(sp) # EA is PC+4 so will skip over instruction causing exception
+ movia r15, vTaskSwitchContext # Pick the next context - use long call version in place of "call"
+ callr r15
+ br restore_sp_from_pxCurrentTCB # Switch in the task context and restore.
+
+ .section .exceptions.unknown.user
+exceptions_unknown_user:
diff --git a/portable/GCC/NiosII/portmacro.h b/portable/GCC/NiosII/portmacro.h
index 60c1178..fb482ff 100644
--- a/portable/GCC/NiosII/portmacro.h
+++ b/portable/GCC/NiosII/portmacro.h
@@ -1,110 +1,109 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "sys/alt_irq.h"
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT short
-#define portSTACK_TYPE uint32_t
-#define portBASE_TYPE long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
-#else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
- /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH ( -1 )
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT 4
-#define portNOP() asm volatile ( "NOP" )
-#define portCRITICAL_NESTING_IN_TCB 1
-/*-----------------------------------------------------------*/
-
-extern void vTaskSwitchContext( void );
-#define portYIELD() asm volatile ( "trap" );
-#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) vTaskSwitchContext(); } while( 0 )
-
-
-/* Include the port_asm.S file where the Context saving/restoring is defined. */
-__asm__( "\n\t.globl save_context" );
-
-/*-----------------------------------------------------------*/
-
-extern void vTaskEnterCritical( void );
-extern void vTaskExitCritical( void );
-
-#define portDISABLE_INTERRUPTS() alt_irq_disable_all()
-#define portENABLE_INTERRUPTS() alt_irq_enable_all( 0x01 );
-#define portENTER_CRITICAL() vTaskEnterCritical()
-#define portEXIT_CRITICAL() vTaskExitCritical()
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "sys/alt_irq.h"
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 4
+#define portNOP() asm volatile ( "NOP" )
+#define portCRITICAL_NESTING_IN_TCB 1
+/*-----------------------------------------------------------*/
+
+extern void vTaskSwitchContext( void );
+#define portYIELD() asm volatile ( "trap" );
+#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) vTaskSwitchContext(); } while( 0 )
+
+
+/* Include the port_asm.S file where the Context saving/restoring is defined. */
+__asm__( "\n\t.globl save_context" );
+
+/*-----------------------------------------------------------*/
+
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+
+#define portDISABLE_INTERRUPTS() alt_irq_disable_all()
+#define portENABLE_INTERRUPTS() alt_irq_enable_all( 0x01 );
+#define portENTER_CRITICAL() vTaskEnterCritical()
+#define portEXIT_CRITICAL() vTaskExitCritical()
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/portable/GCC/PPC405_Xilinx/FPU_Macros.h b/portable/GCC/PPC405_Xilinx/FPU_Macros.h
index 2132499..9c56658 100644
--- a/portable/GCC/PPC405_Xilinx/FPU_Macros.h
+++ b/portable/GCC/PPC405_Xilinx/FPU_Macros.h
@@ -1,46 +1,45 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/* When switching out a task, if the task tag contains a buffer address then
-save the flop context into the buffer. */
-#define traceTASK_SWITCHED_OUT() \
- if( pxCurrentTCB->pxTaskTag != NULL ) \
- { \
- extern void vPortSaveFPURegisters( void * ); \
- vPortSaveFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) ); \
- }
-
-/* When switching in a task, if the task tag contains a buffer address then
-load the flop context from the buffer. */
-#define traceTASK_SWITCHED_IN() \
- if( pxCurrentTCB->pxTaskTag != NULL ) \
- { \
- extern void vPortRestoreFPURegisters( void * ); \
- vPortRestoreFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) ); \
- }
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* When switching out a task, if the task tag contains a buffer address then
+save the flop context into the buffer. */
+#define traceTASK_SWITCHED_OUT() \
+ if( pxCurrentTCB->pxTaskTag != NULL ) \
+ { \
+ extern void vPortSaveFPURegisters( void * ); \
+ vPortSaveFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) ); \
+ }
+
+/* When switching in a task, if the task tag contains a buffer address then
+load the flop context from the buffer. */
+#define traceTASK_SWITCHED_IN() \
+ if( pxCurrentTCB->pxTaskTag != NULL ) \
+ { \
+ extern void vPortRestoreFPURegisters( void * ); \
+ vPortRestoreFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) ); \
+ }
diff --git a/portable/GCC/PPC405_Xilinx/port.c b/portable/GCC/PPC405_Xilinx/port.c
index 2759e0a..c7ecac0 100644
--- a/portable/GCC/PPC405_Xilinx/port.c
+++ b/portable/GCC/PPC405_Xilinx/port.c
@@ -1,261 +1,261 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the PPC405 port.
- *----------------------------------------------------------*/
-
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Library includes. */
-#include "xtime_l.h"
-#include "xintc.h"
-#include "xintc_i.h"
-
-/*-----------------------------------------------------------*/
-
-/* Definitions to set the initial MSR of each task. */
-#define portCRITICAL_INTERRUPT_ENABLE ( 1UL << 17UL )
-#define portEXTERNAL_INTERRUPT_ENABLE ( 1UL << 15UL )
-#define portMACHINE_CHECK_ENABLE ( 1UL << 12UL )
-
-#if configUSE_FPU == 1
- #define portAPU_PRESENT ( 1UL << 25UL )
- #define portFCM_FPU_PRESENT ( 1UL << 13UL )
-#else
- #define portAPU_PRESENT ( 0UL )
- #define portFCM_FPU_PRESENT ( 0UL )
-#endif
-
-#define portINITIAL_MSR ( portCRITICAL_INTERRUPT_ENABLE | portEXTERNAL_INTERRUPT_ENABLE | portMACHINE_CHECK_ENABLE | portAPU_PRESENT | portFCM_FPU_PRESENT )
-
-
-extern const unsigned _SDA_BASE_;
-extern const unsigned _SDA2_BASE_;
-
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the system timer to generate the tick interrupt.
- */
-static void prvSetupTimerInterrupt( void );
-
-/*
- * The handler for the tick interrupt - defined in portasm.s.
- */
-extern void vPortTickISR( void );
-
-/*
- * The handler for the yield function - defined in portasm.s.
- */
-extern void vPortYield( void );
-
-/*
- * Function to start the scheduler running by starting the highest
- * priority task that has thus far been created.
- */
-extern void vPortStartFirstTask( void );
-
-/*-----------------------------------------------------------*/
-
-/* Structure used to hold the state of the interrupt controller. */
-static XIntc xInterruptController;
-
-/*-----------------------------------------------------------*/
-
-/*
- * Initialise the stack of a task to look exactly as if the task had been
- * interrupted.
- *
- * See the header file portable.h.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
- /* Place a known value at the bottom of the stack for debugging. */
- *pxTopOfStack = 0xDEADBEEF;
- pxTopOfStack--;
-
- /* EABI stack frame. */
- pxTopOfStack -= 20; /* Previous backchain and LR, R31 to R4 inclusive. */
-
- /* Parameters in R13. */
- *pxTopOfStack = ( StackType_t ) &_SDA_BASE_; /* address of the first small data area */
- pxTopOfStack -= 10;
-
- /* Parameters in R3. */
- *pxTopOfStack = ( StackType_t ) pvParameters;
- pxTopOfStack--;
-
- /* Parameters in R2. */
- *pxTopOfStack = ( StackType_t ) &_SDA2_BASE_; /* address of the second small data area */
- pxTopOfStack--;
-
- /* R1 is the stack pointer so is omitted. */
-
- *pxTopOfStack = 0x10000001UL;; /* R0. */
- pxTopOfStack--;
- *pxTopOfStack = 0x00000000UL; /* USPRG0. */
- pxTopOfStack--;
- *pxTopOfStack = 0x00000000UL; /* CR. */
- pxTopOfStack--;
- *pxTopOfStack = 0x00000000UL; /* XER. */
- pxTopOfStack--;
- *pxTopOfStack = 0x00000000UL; /* CTR. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) vPortEndScheduler; /* LR. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode; /* SRR0. */
- pxTopOfStack--;
- *pxTopOfStack = portINITIAL_MSR;/* SRR1. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) vPortEndScheduler;/* Next LR. */
- pxTopOfStack--;
- *pxTopOfStack = 0x00000000UL;/* Backchain. */
-
- return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
- prvSetupTimerInterrupt();
- XExc_RegisterHandler( XEXC_ID_SYSTEM_CALL, ( XExceptionHandler ) vPortYield, ( void * ) 0 );
- vPortStartFirstTask();
-
- /* Should not get here as the tasks are now running! */
- return pdFALSE;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
- /* Not implemented. */
- for( ;; );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Hardware initialisation to generate the RTOS tick.
- */
-static void prvSetupTimerInterrupt( void )
-{
-const uint32_t ulInterval = ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL );
-
- XTime_PITClearInterrupt();
- XTime_FITClearInterrupt();
- XTime_WDTClearInterrupt();
- XTime_WDTDisableInterrupt();
- XTime_FITDisableInterrupt();
-
- XExc_RegisterHandler( XEXC_ID_PIT_INT, ( XExceptionHandler ) vPortTickISR, ( void * ) 0 );
-
- XTime_PITEnableAutoReload();
- XTime_PITSetInterval( ulInterval );
- XTime_PITEnableInterrupt();
-}
-/*-----------------------------------------------------------*/
-
-void vPortISRHandler( void *pvNullDoNotUse )
-{
-uint32_t ulInterruptStatus, ulInterruptMask = 1UL;
-BaseType_t xInterruptNumber;
-XIntc_Config *pxInterruptController;
-XIntc_VectorTableEntry *pxTable;
-
- /* Just to remove compiler warning. */
- ( void ) pvNullDoNotUse;
-
- /* Get the configuration by using the device ID - in this case it is
- assumed that only one interrupt controller is being used. */
- pxInterruptController = &XIntc_ConfigTable[ XPAR_XPS_INTC_0_DEVICE_ID ];
-
- /* Which interrupts are pending? */
- ulInterruptStatus = XIntc_mGetIntrStatus( pxInterruptController->BaseAddress );
-
- for( xInterruptNumber = 0; xInterruptNumber < XPAR_INTC_MAX_NUM_INTR_INPUTS; xInterruptNumber++ )
- {
- if( ulInterruptStatus & 0x01UL )
- {
- /* Clear the pending interrupt. */
- XIntc_mAckIntr( pxInterruptController->BaseAddress, ulInterruptMask );
-
- /* Call the registered handler. */
- pxTable = &( pxInterruptController->HandlerTable[ xInterruptNumber ] );
- pxTable->Handler( pxTable->CallBackRef );
- }
-
- /* Check the next interrupt. */
- ulInterruptMask <<= 0x01UL;
- ulInterruptStatus >>= 0x01UL;
-
- /* Have we serviced all interrupts? */
- if( ulInterruptStatus == 0UL )
- {
- break;
- }
- }
-}
-/*-----------------------------------------------------------*/
-
-void vPortSetupInterruptController( void )
-{
-extern void vPortISRWrapper( void );
-
- /* Perform all library calls necessary to initialise the exception table
- and interrupt controller. This assumes only one interrupt controller is in
- use. */
- XExc_mDisableExceptions( XEXC_NON_CRITICAL );
- XExc_Init();
-
- /* The library functions save the context - we then jump to a wrapper to
- save the stack into the TCB. The wrapper then calls the handler defined
- above. */
- XExc_RegisterHandler( XEXC_ID_NON_CRITICAL_INT, ( XExceptionHandler ) vPortISRWrapper, NULL );
- XIntc_Initialize( &xInterruptController, XPAR_XPS_INTC_0_DEVICE_ID );
- XIntc_Start( &xInterruptController, XIN_REAL_MODE );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )
-{
-BaseType_t xReturn = pdFAIL;
-
- /* This function is defined here so the scope of xInterruptController can
- remain within this file. */
-
- if( XST_SUCCESS == XIntc_Connect( &xInterruptController, ucInterruptID, pxHandler, pvCallBackRef ) )
- {
- XIntc_Enable( &xInterruptController, ucInterruptID );
- xReturn = pdPASS;
- }
-
- return xReturn;
-}
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the PPC405 port.
+ *----------------------------------------------------------*/
+
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Library includes. */
+#include "xtime_l.h"
+#include "xintc.h"
+#include "xintc_i.h"
+
+/*-----------------------------------------------------------*/
+
+/* Definitions to set the initial MSR of each task. */
+#define portCRITICAL_INTERRUPT_ENABLE ( 1UL << 17UL )
+#define portEXTERNAL_INTERRUPT_ENABLE ( 1UL << 15UL )
+#define portMACHINE_CHECK_ENABLE ( 1UL << 12UL )
+
+#if configUSE_FPU == 1
+ #define portAPU_PRESENT ( 1UL << 25UL )
+ #define portFCM_FPU_PRESENT ( 1UL << 13UL )
+#else
+ #define portAPU_PRESENT ( 0UL )
+ #define portFCM_FPU_PRESENT ( 0UL )
+#endif
+
+#define portINITIAL_MSR ( portCRITICAL_INTERRUPT_ENABLE | portEXTERNAL_INTERRUPT_ENABLE | portMACHINE_CHECK_ENABLE | portAPU_PRESENT | portFCM_FPU_PRESENT )
+
+
+extern const unsigned _SDA_BASE_;
+extern const unsigned _SDA2_BASE_;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the system timer to generate the tick interrupt.
+ */
+static void prvSetupTimerInterrupt( void );
+
+/*
+ * The handler for the tick interrupt - defined in portasm.s.
+ */
+extern void vPortTickISR( void );
+
+/*
+ * The handler for the yield function - defined in portasm.s.
+ */
+extern void vPortYield( void );
+
+/*
+ * Function to start the scheduler running by starting the highest
+ * priority task that has thus far been created.
+ */
+extern void vPortStartFirstTask( void );
+
+/*-----------------------------------------------------------*/
+
+/* Structure used to hold the state of the interrupt controller. */
+static XIntc xInterruptController;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if the task had been
+ * interrupted.
+ *
+ * See the header file portable.h.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+ /* Place a known value at the bottom of the stack for debugging. */
+ *pxTopOfStack = 0xDEADBEEF;
+ pxTopOfStack--;
+
+ /* EABI stack frame. */
+ pxTopOfStack -= 20; /* Previous backchain and LR, R31 to R4 inclusive. */
+
+ /* Parameters in R13. */
+ *pxTopOfStack = ( StackType_t ) &_SDA_BASE_; /* address of the first small data area */
+ pxTopOfStack -= 10;
+
+ /* Parameters in R3. */
+ *pxTopOfStack = ( StackType_t ) pvParameters;
+ pxTopOfStack--;
+
+ /* Parameters in R2. */
+ *pxTopOfStack = ( StackType_t ) &_SDA2_BASE_; /* address of the second small data area */
+ pxTopOfStack--;
+
+ /* R1 is the stack pointer so is omitted. */
+
+ *pxTopOfStack = 0x10000001UL;; /* R0. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x00000000UL; /* USPRG0. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x00000000UL; /* CR. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x00000000UL; /* XER. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x00000000UL; /* CTR. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) vPortEndScheduler; /* LR. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* SRR0. */
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_MSR;/* SRR1. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) vPortEndScheduler;/* Next LR. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x00000000UL;/* Backchain. */
+
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+ prvSetupTimerInterrupt();
+ XExc_RegisterHandler( XEXC_ID_SYSTEM_CALL, ( XExceptionHandler ) vPortYield, ( void * ) 0 );
+ vPortStartFirstTask();
+
+ /* Should not get here as the tasks are now running! */
+ return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+ /* Not implemented. */
+ for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Hardware initialisation to generate the RTOS tick.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+const uint32_t ulInterval = ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL );
+
+ XTime_PITClearInterrupt();
+ XTime_FITClearInterrupt();
+ XTime_WDTClearInterrupt();
+ XTime_WDTDisableInterrupt();
+ XTime_FITDisableInterrupt();
+
+ XExc_RegisterHandler( XEXC_ID_PIT_INT, ( XExceptionHandler ) vPortTickISR, ( void * ) 0 );
+
+ XTime_PITEnableAutoReload();
+ XTime_PITSetInterval( ulInterval );
+ XTime_PITEnableInterrupt();
+}
+/*-----------------------------------------------------------*/
+
+void vPortISRHandler( void *pvNullDoNotUse )
+{
+uint32_t ulInterruptStatus, ulInterruptMask = 1UL;
+BaseType_t xInterruptNumber;
+XIntc_Config *pxInterruptController;
+XIntc_VectorTableEntry *pxTable;
+
+ /* Just to remove compiler warning. */
+ ( void ) pvNullDoNotUse;
+
+ /* Get the configuration by using the device ID - in this case it is
+ assumed that only one interrupt controller is being used. */
+ pxInterruptController = &XIntc_ConfigTable[ XPAR_XPS_INTC_0_DEVICE_ID ];
+
+ /* Which interrupts are pending? */
+ ulInterruptStatus = XIntc_mGetIntrStatus( pxInterruptController->BaseAddress );
+
+ for( xInterruptNumber = 0; xInterruptNumber < XPAR_INTC_MAX_NUM_INTR_INPUTS; xInterruptNumber++ )
+ {
+ if( ulInterruptStatus & 0x01UL )
+ {
+ /* Clear the pending interrupt. */
+ XIntc_mAckIntr( pxInterruptController->BaseAddress, ulInterruptMask );
+
+ /* Call the registered handler. */
+ pxTable = &( pxInterruptController->HandlerTable[ xInterruptNumber ] );
+ pxTable->Handler( pxTable->CallBackRef );
+ }
+
+ /* Check the next interrupt. */
+ ulInterruptMask <<= 0x01UL;
+ ulInterruptStatus >>= 0x01UL;
+
+ /* Have we serviced all interrupts? */
+ if( ulInterruptStatus == 0UL )
+ {
+ break;
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vPortSetupInterruptController( void )
+{
+extern void vPortISRWrapper( void );
+
+ /* Perform all library calls necessary to initialise the exception table
+ and interrupt controller. This assumes only one interrupt controller is in
+ use. */
+ XExc_mDisableExceptions( XEXC_NON_CRITICAL );
+ XExc_Init();
+
+ /* The library functions save the context - we then jump to a wrapper to
+ save the stack into the TCB. The wrapper then calls the handler defined
+ above. */
+ XExc_RegisterHandler( XEXC_ID_NON_CRITICAL_INT, ( XExceptionHandler ) vPortISRWrapper, NULL );
+ XIntc_Initialize( &xInterruptController, XPAR_XPS_INTC_0_DEVICE_ID );
+ XIntc_Start( &xInterruptController, XIN_REAL_MODE );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )
+{
+BaseType_t xReturn = pdFAIL;
+
+ /* This function is defined here so the scope of xInterruptController can
+ remain within this file. */
+
+ if( XST_SUCCESS == XIntc_Connect( &xInterruptController, ucInterruptID, pxHandler, pvCallBackRef ) )
+ {
+ XIntc_Enable( &xInterruptController, ucInterruptID );
+ xReturn = pdPASS;
+ }
+
+ return xReturn;
+}
diff --git a/portable/GCC/PPC405_Xilinx/portasm.S b/portable/GCC/PPC405_Xilinx/portasm.S
index f443e8d..49866e8 100644
--- a/portable/GCC/PPC405_Xilinx/portasm.S
+++ b/portable/GCC/PPC405_Xilinx/portasm.S
@@ -1,383 +1,381 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#include "FreeRTOSConfig.h"
-
- .extern pxCurrentTCB
- .extern vTaskSwitchContext
- .extern xTaskIncrementTick
- .extern vPortISRHandler
-
- .global vPortStartFirstTask
- .global vPortYield
- .global vPortTickISR
- .global vPortISRWrapper
- .global vPortSaveFPURegisters
- .global vPortRestoreFPURegisters
-
-.set BChainField, 0
-.set NextLRField, BChainField + 4
-.set MSRField, NextLRField + 4
-.set PCField, MSRField + 4
-.set LRField, PCField + 4
-.set CTRField, LRField + 4
-.set XERField, CTRField + 4
-.set CRField, XERField + 4
-.set USPRG0Field, CRField + 4
-.set r0Field, USPRG0Field + 4
-.set r2Field, r0Field + 4
-.set r3r31Field, r2Field + 4
-.set IFrameSize, r3r31Field + ( ( 31 - 3 ) + 1 ) * 4
-
-
-.macro portSAVE_STACK_POINTER_AND_LR
-
- /* Get the address of the TCB. */
- xor R0, R0, R0
- addis R2, R0, pxCurrentTCB@ha
- lwz R2, pxCurrentTCB@l( R2 )
-
- /* Store the stack pointer into the TCB */
- stw SP, 0( R2 )
-
- /* Save the link register */
- stwu R1, -24( R1 )
- mflr R0
- stw R31, 20( R1 )
- stw R0, 28( R1 )
- mr R31, r1
-
-.endm
-
-.macro portRESTORE_STACK_POINTER_AND_LR
-
- /* Restore the link register */
- lwz R11, 0( R1 )
- lwz R0, 4( R11 )
- mtlr R0
- lwz R31, -4( R11 )
- mr R1, R11
-
- /* Get the address of the TCB. */
- xor R0, R0, R0
- addis SP, R0, pxCurrentTCB@ha
- lwz SP, pxCurrentTCB@l( R1 )
-
- /* Get the task stack pointer from the TCB. */
- lwz SP, 0( SP )
-
-.endm
-
-
-vPortStartFirstTask:
-
- /* Get the address of the TCB. */
- xor R0, R0, R0
- addis SP, R0, pxCurrentTCB@ha
- lwz SP, pxCurrentTCB@l( SP )
-
- /* Get the task stack pointer from the TCB. */
- lwz SP, 0( SP )
-
- /* Restore MSR register to SRR1. */
- lwz R0, MSRField(R1)
- mtsrr1 R0
-
- /* Restore current PC location to SRR0. */
- lwz R0, PCField(R1)
- mtsrr0 R0
-
- /* Save USPRG0 register */
- lwz R0, USPRG0Field(R1)
- mtspr 0x100,R0
-
- /* Restore Condition register */
- lwz R0, CRField(R1)
- mtcr R0
-
- /* Restore Fixed Point Exception register */
- lwz R0, XERField(R1)
- mtxer R0
-
- /* Restore Counter register */
- lwz R0, CTRField(R1)
- mtctr R0
-
- /* Restore Link register */
- lwz R0, LRField(R1)
- mtlr R0
-
- /* Restore remaining GPR registers. */
- lmw R3,r3r31Field(R1)
-
- /* Restore r0 and r2. */
- lwz R0, r0Field(R1)
- lwz R2, r2Field(R1)
-
- /* Remove frame from stack */
- addi R1,R1,IFrameSize
-
- /* Return into the first task */
- rfi
-
-
-
-vPortYield:
-
- portSAVE_STACK_POINTER_AND_LR
- bl vTaskSwitchContext
- portRESTORE_STACK_POINTER_AND_LR
- blr
-
-vPortTickISR:
-
- portSAVE_STACK_POINTER_AND_LR
- bl xTaskIncrementTick
-
- #if configUSE_PREEMPTION == 1
- bl vTaskSwitchContext
- #endif
-
- /* Clear the interrupt */
- lis R0, 2048
- mttsr R0
-
- portRESTORE_STACK_POINTER_AND_LR
- blr
-
-vPortISRWrapper:
-
- portSAVE_STACK_POINTER_AND_LR
- bl vPortISRHandler
- portRESTORE_STACK_POINTER_AND_LR
- blr
-
-#if configUSE_FPU == 1
-
-vPortSaveFPURegisters:
-
- /* Enable APU and mark FPU as present. */
- mfmsr r0
- xor r30, r30, r30
- oris r30, r30, 512
- ori r30, r30, 8192
- or r0, r0, r30
- mtmsr r0
-
-#ifdef USE_DP_FPU
-
- /* Buffer address is in r3. Save each flop register into an offset from
- this buffer address. */
- stfd f0, 0(r3)
- stfd f1, 8(r3)
- stfd f2, 16(r3)
- stfd f3, 24(r3)
- stfd f4, 32(r3)
- stfd f5, 40(r3)
- stfd f6, 48(r3)
- stfd f7, 56(r3)
- stfd f8, 64(r3)
- stfd f9, 72(r3)
- stfd f10, 80(r3)
- stfd f11, 88(r3)
- stfd f12, 96(r3)
- stfd f13, 104(r3)
- stfd f14, 112(r3)
- stfd f15, 120(r3)
- stfd f16, 128(r3)
- stfd f17, 136(r3)
- stfd f18, 144(r3)
- stfd f19, 152(r3)
- stfd f20, 160(r3)
- stfd f21, 168(r3)
- stfd f22, 176(r3)
- stfd f23, 184(r3)
- stfd f24, 192(r3)
- stfd f25, 200(r3)
- stfd f26, 208(r3)
- stfd f27, 216(r3)
- stfd f28, 224(r3)
- stfd f29, 232(r3)
- stfd f30, 240(r3)
- stfd f31, 248(r3)
-
- /* Also save the FPSCR. */
- mffs f31
- stfs f31, 256(r3)
-
-#else
-
- /* Buffer address is in r3. Save each flop register into an offset from
- this buffer address. */
- stfs f0, 0(r3)
- stfs f1, 4(r3)
- stfs f2, 8(r3)
- stfs f3, 12(r3)
- stfs f4, 16(r3)
- stfs f5, 20(r3)
- stfs f6, 24(r3)
- stfs f7, 28(r3)
- stfs f8, 32(r3)
- stfs f9, 36(r3)
- stfs f10, 40(r3)
- stfs f11, 44(r3)
- stfs f12, 48(r3)
- stfs f13, 52(r3)
- stfs f14, 56(r3)
- stfs f15, 60(r3)
- stfs f16, 64(r3)
- stfs f17, 68(r3)
- stfs f18, 72(r3)
- stfs f19, 76(r3)
- stfs f20, 80(r3)
- stfs f21, 84(r3)
- stfs f22, 88(r3)
- stfs f23, 92(r3)
- stfs f24, 96(r3)
- stfs f25, 100(r3)
- stfs f26, 104(r3)
- stfs f27, 108(r3)
- stfs f28, 112(r3)
- stfs f29, 116(r3)
- stfs f30, 120(r3)
- stfs f31, 124(r3)
-
- /* Also save the FPSCR. */
- mffs f31
- stfs f31, 128(r3)
-
-#endif
-
- blr
-
-#endif /* configUSE_FPU. */
-
-
-#if configUSE_FPU == 1
-
-vPortRestoreFPURegisters:
-
- /* Enable APU and mark FPU as present. */
- mfmsr r0
- xor r30, r30, r30
- oris r30, r30, 512
- ori r30, r30, 8192
- or r0, r0, r30
- mtmsr r0
-
-#ifdef USE_DP_FPU
-
- /* Buffer address is in r3. Restore each flop register from an offset
- into this buffer.
-
- First the FPSCR. */
- lfs f31, 256(r3)
- mtfsf f31, 7
-
- lfd f0, 0(r3)
- lfd f1, 8(r3)
- lfd f2, 16(r3)
- lfd f3, 24(r3)
- lfd f4, 32(r3)
- lfd f5, 40(r3)
- lfd f6, 48(r3)
- lfd f7, 56(r3)
- lfd f8, 64(r3)
- lfd f9, 72(r3)
- lfd f10, 80(r3)
- lfd f11, 88(r3)
- lfd f12, 96(r3)
- lfd f13, 104(r3)
- lfd f14, 112(r3)
- lfd f15, 120(r3)
- lfd f16, 128(r3)
- lfd f17, 136(r3)
- lfd f18, 144(r3)
- lfd f19, 152(r3)
- lfd f20, 160(r3)
- lfd f21, 168(r3)
- lfd f22, 176(r3)
- lfd f23, 184(r3)
- lfd f24, 192(r3)
- lfd f25, 200(r3)
- lfd f26, 208(r3)
- lfd f27, 216(r3)
- lfd f28, 224(r3)
- lfd f29, 232(r3)
- lfd f30, 240(r3)
- lfd f31, 248(r3)
-
-#else
-
- /* Buffer address is in r3. Restore each flop register from an offset
- into this buffer.
-
- First the FPSCR. */
- lfs f31, 128(r3)
- mtfsf f31, 7
-
- lfs f0, 0(r3)
- lfs f1, 4(r3)
- lfs f2, 8(r3)
- lfs f3, 12(r3)
- lfs f4, 16(r3)
- lfs f5, 20(r3)
- lfs f6, 24(r3)
- lfs f7, 28(r3)
- lfs f8, 32(r3)
- lfs f9, 36(r3)
- lfs f10, 40(r3)
- lfs f11, 44(r3)
- lfs f12, 48(r3)
- lfs f13, 52(r3)
- lfs f14, 56(r3)
- lfs f15, 60(r3)
- lfs f16, 64(r3)
- lfs f17, 68(r3)
- lfs f18, 72(r3)
- lfs f19, 76(r3)
- lfs f20, 80(r3)
- lfs f21, 84(r3)
- lfs f22, 88(r3)
- lfs f23, 92(r3)
- lfs f24, 96(r3)
- lfs f25, 100(r3)
- lfs f26, 104(r3)
- lfs f27, 108(r3)
- lfs f28, 112(r3)
- lfs f29, 116(r3)
- lfs f30, 120(r3)
- lfs f31, 124(r3)
-
-#endif
-
- blr
-
-#endif /* configUSE_FPU. */
-
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#include "FreeRTOSConfig.h"
+
+ .extern pxCurrentTCB
+ .extern vTaskSwitchContext
+ .extern xTaskIncrementTick
+ .extern vPortISRHandler
+
+ .global vPortStartFirstTask
+ .global vPortYield
+ .global vPortTickISR
+ .global vPortISRWrapper
+ .global vPortSaveFPURegisters
+ .global vPortRestoreFPURegisters
+
+.set BChainField, 0
+.set NextLRField, BChainField + 4
+.set MSRField, NextLRField + 4
+.set PCField, MSRField + 4
+.set LRField, PCField + 4
+.set CTRField, LRField + 4
+.set XERField, CTRField + 4
+.set CRField, XERField + 4
+.set USPRG0Field, CRField + 4
+.set r0Field, USPRG0Field + 4
+.set r2Field, r0Field + 4
+.set r3r31Field, r2Field + 4
+.set IFrameSize, r3r31Field + ( ( 31 - 3 ) + 1 ) * 4
+
+
+.macro portSAVE_STACK_POINTER_AND_LR
+
+ /* Get the address of the TCB. */
+ xor R0, R0, R0
+ addis R2, R0, pxCurrentTCB@ha
+ lwz R2, pxCurrentTCB@l( R2 )
+
+ /* Store the stack pointer into the TCB */
+ stw SP, 0( R2 )
+
+ /* Save the link register */
+ stwu R1, -24( R1 )
+ mflr R0
+ stw R31, 20( R1 )
+ stw R0, 28( R1 )
+ mr R31, r1
+
+.endm
+
+.macro portRESTORE_STACK_POINTER_AND_LR
+
+ /* Restore the link register */
+ lwz R11, 0( R1 )
+ lwz R0, 4( R11 )
+ mtlr R0
+ lwz R31, -4( R11 )
+ mr R1, R11
+
+ /* Get the address of the TCB. */
+ xor R0, R0, R0
+ addis SP, R0, pxCurrentTCB@ha
+ lwz SP, pxCurrentTCB@l( R1 )
+
+ /* Get the task stack pointer from the TCB. */
+ lwz SP, 0( SP )
+
+.endm
+
+
+vPortStartFirstTask:
+
+ /* Get the address of the TCB. */
+ xor R0, R0, R0
+ addis SP, R0, pxCurrentTCB@ha
+ lwz SP, pxCurrentTCB@l( SP )
+
+ /* Get the task stack pointer from the TCB. */
+ lwz SP, 0( SP )
+
+ /* Restore MSR register to SRR1. */
+ lwz R0, MSRField(R1)
+ mtsrr1 R0
+
+ /* Restore current PC location to SRR0. */
+ lwz R0, PCField(R1)
+ mtsrr0 R0
+
+ /* Save USPRG0 register */
+ lwz R0, USPRG0Field(R1)
+ mtspr 0x100,R0
+
+ /* Restore Condition register */
+ lwz R0, CRField(R1)
+ mtcr R0
+
+ /* Restore Fixed Point Exception register */
+ lwz R0, XERField(R1)
+ mtxer R0
+
+ /* Restore Counter register */
+ lwz R0, CTRField(R1)
+ mtctr R0
+
+ /* Restore Link register */
+ lwz R0, LRField(R1)
+ mtlr R0
+
+ /* Restore remaining GPR registers. */
+ lmw R3,r3r31Field(R1)
+
+ /* Restore r0 and r2. */
+ lwz R0, r0Field(R1)
+ lwz R2, r2Field(R1)
+
+ /* Remove frame from stack */
+ addi R1,R1,IFrameSize
+
+ /* Return into the first task */
+ rfi
+
+
+
+vPortYield:
+
+ portSAVE_STACK_POINTER_AND_LR
+ bl vTaskSwitchContext
+ portRESTORE_STACK_POINTER_AND_LR
+ blr
+
+vPortTickISR:
+
+ portSAVE_STACK_POINTER_AND_LR
+ bl xTaskIncrementTick
+
+ #if configUSE_PREEMPTION == 1
+ bl vTaskSwitchContext
+ #endif
+
+ /* Clear the interrupt */
+ lis R0, 2048
+ mttsr R0
+
+ portRESTORE_STACK_POINTER_AND_LR
+ blr
+
+vPortISRWrapper:
+
+ portSAVE_STACK_POINTER_AND_LR
+ bl vPortISRHandler
+ portRESTORE_STACK_POINTER_AND_LR
+ blr
+
+#if configUSE_FPU == 1
+
+vPortSaveFPURegisters:
+
+ /* Enable APU and mark FPU as present. */
+ mfmsr r0
+ xor r30, r30, r30
+ oris r30, r30, 512
+ ori r30, r30, 8192
+ or r0, r0, r30
+ mtmsr r0
+
+#ifdef USE_DP_FPU
+
+ /* Buffer address is in r3. Save each flop register into an offset from
+ this buffer address. */
+ stfd f0, 0(r3)
+ stfd f1, 8(r3)
+ stfd f2, 16(r3)
+ stfd f3, 24(r3)
+ stfd f4, 32(r3)
+ stfd f5, 40(r3)
+ stfd f6, 48(r3)
+ stfd f7, 56(r3)
+ stfd f8, 64(r3)
+ stfd f9, 72(r3)
+ stfd f10, 80(r3)
+ stfd f11, 88(r3)
+ stfd f12, 96(r3)
+ stfd f13, 104(r3)
+ stfd f14, 112(r3)
+ stfd f15, 120(r3)
+ stfd f16, 128(r3)
+ stfd f17, 136(r3)
+ stfd f18, 144(r3)
+ stfd f19, 152(r3)
+ stfd f20, 160(r3)
+ stfd f21, 168(r3)
+ stfd f22, 176(r3)
+ stfd f23, 184(r3)
+ stfd f24, 192(r3)
+ stfd f25, 200(r3)
+ stfd f26, 208(r3)
+ stfd f27, 216(r3)
+ stfd f28, 224(r3)
+ stfd f29, 232(r3)
+ stfd f30, 240(r3)
+ stfd f31, 248(r3)
+
+ /* Also save the FPSCR. */
+ mffs f31
+ stfs f31, 256(r3)
+
+#else
+
+ /* Buffer address is in r3. Save each flop register into an offset from
+ this buffer address. */
+ stfs f0, 0(r3)
+ stfs f1, 4(r3)
+ stfs f2, 8(r3)
+ stfs f3, 12(r3)
+ stfs f4, 16(r3)
+ stfs f5, 20(r3)
+ stfs f6, 24(r3)
+ stfs f7, 28(r3)
+ stfs f8, 32(r3)
+ stfs f9, 36(r3)
+ stfs f10, 40(r3)
+ stfs f11, 44(r3)
+ stfs f12, 48(r3)
+ stfs f13, 52(r3)
+ stfs f14, 56(r3)
+ stfs f15, 60(r3)
+ stfs f16, 64(r3)
+ stfs f17, 68(r3)
+ stfs f18, 72(r3)
+ stfs f19, 76(r3)
+ stfs f20, 80(r3)
+ stfs f21, 84(r3)
+ stfs f22, 88(r3)
+ stfs f23, 92(r3)
+ stfs f24, 96(r3)
+ stfs f25, 100(r3)
+ stfs f26, 104(r3)
+ stfs f27, 108(r3)
+ stfs f28, 112(r3)
+ stfs f29, 116(r3)
+ stfs f30, 120(r3)
+ stfs f31, 124(r3)
+
+ /* Also save the FPSCR. */
+ mffs f31
+ stfs f31, 128(r3)
+
+#endif
+
+ blr
+
+#endif /* configUSE_FPU. */
+
+
+#if configUSE_FPU == 1
+
+vPortRestoreFPURegisters:
+
+ /* Enable APU and mark FPU as present. */
+ mfmsr r0
+ xor r30, r30, r30
+ oris r30, r30, 512
+ ori r30, r30, 8192
+ or r0, r0, r30
+ mtmsr r0
+
+#ifdef USE_DP_FPU
+
+ /* Buffer address is in r3. Restore each flop register from an offset
+ into this buffer.
+
+ First the FPSCR. */
+ lfs f31, 256(r3)
+ mtfsf f31, 7
+
+ lfd f0, 0(r3)
+ lfd f1, 8(r3)
+ lfd f2, 16(r3)
+ lfd f3, 24(r3)
+ lfd f4, 32(r3)
+ lfd f5, 40(r3)
+ lfd f6, 48(r3)
+ lfd f7, 56(r3)
+ lfd f8, 64(r3)
+ lfd f9, 72(r3)
+ lfd f10, 80(r3)
+ lfd f11, 88(r3)
+ lfd f12, 96(r3)
+ lfd f13, 104(r3)
+ lfd f14, 112(r3)
+ lfd f15, 120(r3)
+ lfd f16, 128(r3)
+ lfd f17, 136(r3)
+ lfd f18, 144(r3)
+ lfd f19, 152(r3)
+ lfd f20, 160(r3)
+ lfd f21, 168(r3)
+ lfd f22, 176(r3)
+ lfd f23, 184(r3)
+ lfd f24, 192(r3)
+ lfd f25, 200(r3)
+ lfd f26, 208(r3)
+ lfd f27, 216(r3)
+ lfd f28, 224(r3)
+ lfd f29, 232(r3)
+ lfd f30, 240(r3)
+ lfd f31, 248(r3)
+
+#else
+
+ /* Buffer address is in r3. Restore each flop register from an offset
+ into this buffer.
+
+ First the FPSCR. */
+ lfs f31, 128(r3)
+ mtfsf f31, 7
+
+ lfs f0, 0(r3)
+ lfs f1, 4(r3)
+ lfs f2, 8(r3)
+ lfs f3, 12(r3)
+ lfs f4, 16(r3)
+ lfs f5, 20(r3)
+ lfs f6, 24(r3)
+ lfs f7, 28(r3)
+ lfs f8, 32(r3)
+ lfs f9, 36(r3)
+ lfs f10, 40(r3)
+ lfs f11, 44(r3)
+ lfs f12, 48(r3)
+ lfs f13, 52(r3)
+ lfs f14, 56(r3)
+ lfs f15, 60(r3)
+ lfs f16, 64(r3)
+ lfs f17, 68(r3)
+ lfs f18, 72(r3)
+ lfs f19, 76(r3)
+ lfs f20, 80(r3)
+ lfs f21, 84(r3)
+ lfs f22, 88(r3)
+ lfs f23, 92(r3)
+ lfs f24, 96(r3)
+ lfs f25, 100(r3)
+ lfs f26, 104(r3)
+ lfs f27, 108(r3)
+ lfs f28, 112(r3)
+ lfs f29, 116(r3)
+ lfs f30, 120(r3)
+ lfs f31, 124(r3)
+
+#endif
+
+ blr
+
+#endif /* configUSE_FPU. */
diff --git a/portable/GCC/PPC405_Xilinx/portmacro.h b/portable/GCC/PPC405_Xilinx/portmacro.h
index cfbc15a..eaad8fe 100644
--- a/portable/GCC/PPC405_Xilinx/portmacro.h
+++ b/portable/GCC/PPC405_Xilinx/portmacro.h
@@ -1,119 +1,118 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#include "xexception_l.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT short
-#define portSTACK_TYPE uint32_t
-#define portBASE_TYPE long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
-#else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* This port uses the critical nesting count from the TCB rather than
-maintaining a separate value and then saving this value in the task stack. */
-#define portCRITICAL_NESTING_IN_TCB 1
-
-/* Interrupt control macros. */
-#define portDISABLE_INTERRUPTS() XExc_mDisableExceptions( XEXC_NON_CRITICAL );
-#define portENABLE_INTERRUPTS() XExc_mEnableExceptions( XEXC_NON_CRITICAL );
-
-/*-----------------------------------------------------------*/
-
-/* Critical section macros. */
-void vTaskEnterCritical( void );
-void vTaskExitCritical( void );
-#define portENTER_CRITICAL() vTaskEnterCritical()
-#define portEXIT_CRITICAL() vTaskExitCritical()
-
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-void vPortYield( void );
-#define portYIELD() asm volatile ( "SC \n\t NOP" )
-#define portYIELD_FROM_ISR() vTaskSwitchContext()
-
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portBYTE_ALIGNMENT 8
-#define portSTACK_GROWTH ( -1 )
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP() asm volatile ( "NOP" )
-
-/* There are 32 * 32bit floating point regieters, plus the FPSCR to save. */
-#define portNO_FLOP_REGISTERS_TO_SAVE ( 32 + 1 )
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-/* Port specific interrupt handling functions. */
-void vPortSetupInterruptController( void );
-BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#include "xexception_l.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* This port uses the critical nesting count from the TCB rather than
+maintaining a separate value and then saving this value in the task stack. */
+#define portCRITICAL_NESTING_IN_TCB 1
+
+/* Interrupt control macros. */
+#define portDISABLE_INTERRUPTS() XExc_mDisableExceptions( XEXC_NON_CRITICAL );
+#define portENABLE_INTERRUPTS() XExc_mEnableExceptions( XEXC_NON_CRITICAL );
+
+/*-----------------------------------------------------------*/
+
+/* Critical section macros. */
+void vTaskEnterCritical( void );
+void vTaskExitCritical( void );
+#define portENTER_CRITICAL() vTaskEnterCritical()
+#define portEXIT_CRITICAL() vTaskExitCritical()
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+void vPortYield( void );
+#define portYIELD() asm volatile ( "SC \n\t NOP" )
+#define portYIELD_FROM_ISR() vTaskSwitchContext()
+
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT 8
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP() asm volatile ( "NOP" )
+
+/* There are 32 * 32bit floating point regieters, plus the FPSCR to save. */
+#define portNO_FLOP_REGISTERS_TO_SAVE ( 32 + 1 )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+/* Port specific interrupt handling functions. */
+void vPortSetupInterruptController( void );
+BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/portable/GCC/PPC440_Xilinx/FPU_Macros.h b/portable/GCC/PPC440_Xilinx/FPU_Macros.h
index 2132499..9c56658 100644
--- a/portable/GCC/PPC440_Xilinx/FPU_Macros.h
+++ b/portable/GCC/PPC440_Xilinx/FPU_Macros.h
@@ -1,46 +1,45 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/* When switching out a task, if the task tag contains a buffer address then
-save the flop context into the buffer. */
-#define traceTASK_SWITCHED_OUT() \
- if( pxCurrentTCB->pxTaskTag != NULL ) \
- { \
- extern void vPortSaveFPURegisters( void * ); \
- vPortSaveFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) ); \
- }
-
-/* When switching in a task, if the task tag contains a buffer address then
-load the flop context from the buffer. */
-#define traceTASK_SWITCHED_IN() \
- if( pxCurrentTCB->pxTaskTag != NULL ) \
- { \
- extern void vPortRestoreFPURegisters( void * ); \
- vPortRestoreFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) ); \
- }
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* When switching out a task, if the task tag contains a buffer address then
+save the flop context into the buffer. */
+#define traceTASK_SWITCHED_OUT() \
+ if( pxCurrentTCB->pxTaskTag != NULL ) \
+ { \
+ extern void vPortSaveFPURegisters( void * ); \
+ vPortSaveFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) ); \
+ }
+
+/* When switching in a task, if the task tag contains a buffer address then
+load the flop context from the buffer. */
+#define traceTASK_SWITCHED_IN() \
+ if( pxCurrentTCB->pxTaskTag != NULL ) \
+ { \
+ extern void vPortRestoreFPURegisters( void * ); \
+ vPortRestoreFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) ); \
+ }
diff --git a/portable/GCC/PPC440_Xilinx/port.c b/portable/GCC/PPC440_Xilinx/port.c
index 883b22d..89caeac 100644
--- a/portable/GCC/PPC440_Xilinx/port.c
+++ b/portable/GCC/PPC440_Xilinx/port.c
@@ -1,261 +1,261 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the PPC440 port.
- *----------------------------------------------------------*/
-
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Library includes. */
-#include "xtime_l.h"
-#include "xintc.h"
-#include "xintc_i.h"
-
-/*-----------------------------------------------------------*/
-
-/* Definitions to set the initial MSR of each task. */
-#define portCRITICAL_INTERRUPT_ENABLE ( 1UL << 17UL )
-#define portEXTERNAL_INTERRUPT_ENABLE ( 1UL << 15UL )
-#define portMACHINE_CHECK_ENABLE ( 1UL << 12UL )
-
-#if configUSE_FPU == 1
- #define portAPU_PRESENT ( 1UL << 25UL )
- #define portFCM_FPU_PRESENT ( 1UL << 13UL )
-#else
- #define portAPU_PRESENT ( 0UL )
- #define portFCM_FPU_PRESENT ( 0UL )
-#endif
-
-#define portINITIAL_MSR ( portCRITICAL_INTERRUPT_ENABLE | portEXTERNAL_INTERRUPT_ENABLE | portMACHINE_CHECK_ENABLE | portAPU_PRESENT | portFCM_FPU_PRESENT )
-
-
-extern const unsigned _SDA_BASE_;
-extern const unsigned _SDA2_BASE_;
-
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the system timer to generate the tick interrupt.
- */
-static void prvSetupTimerInterrupt( void );
-
-/*
- * The handler for the tick interrupt - defined in portasm.s.
- */
-extern void vPortTickISR( void );
-
-/*
- * The handler for the yield function - defined in portasm.s.
- */
-extern void vPortYield( void );
-
-/*
- * Function to start the scheduler running by starting the highest
- * priority task that has thus far been created.
- */
-extern void vPortStartFirstTask( void );
-
-/*-----------------------------------------------------------*/
-
-/* Structure used to hold the state of the interrupt controller. */
-static XIntc xInterruptController;
-
-/*-----------------------------------------------------------*/
-
-/*
- * Initialise the stack of a task to look exactly as if the task had been
- * interrupted.
- *
- * See the header file portable.h.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
- /* Place a known value at the bottom of the stack for debugging. */
- *pxTopOfStack = 0xDEADBEEF;
- pxTopOfStack--;
-
- /* EABI stack frame. */
- pxTopOfStack -= 20; /* Previous backchain and LR, R31 to R4 inclusive. */
-
- /* Parameters in R13. */
- *pxTopOfStack = ( StackType_t ) &_SDA_BASE_; /* address of the first small data area */
- pxTopOfStack -= 10;
-
- /* Parameters in R3. */
- *pxTopOfStack = ( StackType_t ) pvParameters;
- pxTopOfStack--;
-
- /* Parameters in R2. */
- *pxTopOfStack = ( StackType_t ) &_SDA2_BASE_; /* address of the second small data area */
- pxTopOfStack--;
-
- /* R1 is the stack pointer so is omitted. */
-
- *pxTopOfStack = 0x10000001UL;; /* R0. */
- pxTopOfStack--;
- *pxTopOfStack = 0x00000000UL; /* USPRG0. */
- pxTopOfStack--;
- *pxTopOfStack = 0x00000000UL; /* CR. */
- pxTopOfStack--;
- *pxTopOfStack = 0x00000000UL; /* XER. */
- pxTopOfStack--;
- *pxTopOfStack = 0x00000000UL; /* CTR. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) vPortEndScheduler; /* LR. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode; /* SRR0. */
- pxTopOfStack--;
- *pxTopOfStack = portINITIAL_MSR;/* SRR1. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) vPortEndScheduler;/* Next LR. */
- pxTopOfStack--;
- *pxTopOfStack = 0x00000000UL;/* Backchain. */
-
- return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
- prvSetupTimerInterrupt();
- XExc_RegisterHandler( XEXC_ID_SYSTEM_CALL, ( XExceptionHandler ) vPortYield, ( void * ) 0 );
- vPortStartFirstTask();
-
- /* Should not get here as the tasks are now running! */
- return pdFALSE;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
- /* Not implemented. */
- for( ;; );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Hardware initialisation to generate the RTOS tick.
- */
-static void prvSetupTimerInterrupt( void )
-{
-const uint32_t ulInterval = ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL );
-
- XTime_DECClearInterrupt();
- XTime_FITClearInterrupt();
- XTime_WDTClearInterrupt();
- XTime_WDTDisableInterrupt();
- XTime_FITDisableInterrupt();
-
- XExc_RegisterHandler( XEXC_ID_DEC_INT, ( XExceptionHandler ) vPortTickISR, ( void * ) 0 );
-
- XTime_DECEnableAutoReload();
- XTime_DECSetInterval( ulInterval );
- XTime_DECEnableInterrupt();
-}
-/*-----------------------------------------------------------*/
-
-void vPortISRHandler( void *pvNullDoNotUse )
-{
-uint32_t ulInterruptStatus, ulInterruptMask = 1UL;
-BaseType_t xInterruptNumber;
-XIntc_Config *pxInterruptController;
-XIntc_VectorTableEntry *pxTable;
-
- /* Just to remove compiler warning. */
- ( void ) pvNullDoNotUse;
-
- /* Get the configuration by using the device ID - in this case it is
- assumed that only one interrupt controller is being used. */
- pxInterruptController = &XIntc_ConfigTable[ XPAR_XPS_INTC_0_DEVICE_ID ];
-
- /* Which interrupts are pending? */
- ulInterruptStatus = XIntc_mGetIntrStatus( pxInterruptController->BaseAddress );
-
- for( xInterruptNumber = 0; xInterruptNumber < XPAR_INTC_MAX_NUM_INTR_INPUTS; xInterruptNumber++ )
- {
- if( ulInterruptStatus & 0x01UL )
- {
- /* Clear the pending interrupt. */
- XIntc_mAckIntr( pxInterruptController->BaseAddress, ulInterruptMask );
-
- /* Call the registered handler. */
- pxTable = &( pxInterruptController->HandlerTable[ xInterruptNumber ] );
- pxTable->Handler( pxTable->CallBackRef );
- }
-
- /* Check the next interrupt. */
- ulInterruptMask <<= 0x01UL;
- ulInterruptStatus >>= 0x01UL;
-
- /* Have we serviced all interrupts? */
- if( ulInterruptStatus == 0UL )
- {
- break;
- }
- }
-}
-/*-----------------------------------------------------------*/
-
-void vPortSetupInterruptController( void )
-{
-extern void vPortISRWrapper( void );
-
- /* Perform all library calls necessary to initialise the exception table
- and interrupt controller. This assumes only one interrupt controller is in
- use. */
- XExc_mDisableExceptions( XEXC_NON_CRITICAL );
- XExc_Init();
-
- /* The library functions save the context - we then jump to a wrapper to
- save the stack into the TCB. The wrapper then calls the handler defined
- above. */
- XExc_RegisterHandler( XEXC_ID_NON_CRITICAL_INT, ( XExceptionHandler ) vPortISRWrapper, NULL );
- XIntc_Initialize( &xInterruptController, XPAR_XPS_INTC_0_DEVICE_ID );
- XIntc_Start( &xInterruptController, XIN_REAL_MODE );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )
-{
-BaseType_t xReturn = pdFAIL;
-
- /* This function is defined here so the scope of xInterruptController can
- remain within this file. */
-
- if( XST_SUCCESS == XIntc_Connect( &xInterruptController, ucInterruptID, pxHandler, pvCallBackRef ) )
- {
- XIntc_Enable( &xInterruptController, ucInterruptID );
- xReturn = pdPASS;
- }
-
- return xReturn;
-}
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the PPC440 port.
+ *----------------------------------------------------------*/
+
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Library includes. */
+#include "xtime_l.h"
+#include "xintc.h"
+#include "xintc_i.h"
+
+/*-----------------------------------------------------------*/
+
+/* Definitions to set the initial MSR of each task. */
+#define portCRITICAL_INTERRUPT_ENABLE ( 1UL << 17UL )
+#define portEXTERNAL_INTERRUPT_ENABLE ( 1UL << 15UL )
+#define portMACHINE_CHECK_ENABLE ( 1UL << 12UL )
+
+#if configUSE_FPU == 1
+ #define portAPU_PRESENT ( 1UL << 25UL )
+ #define portFCM_FPU_PRESENT ( 1UL << 13UL )
+#else
+ #define portAPU_PRESENT ( 0UL )
+ #define portFCM_FPU_PRESENT ( 0UL )
+#endif
+
+#define portINITIAL_MSR ( portCRITICAL_INTERRUPT_ENABLE | portEXTERNAL_INTERRUPT_ENABLE | portMACHINE_CHECK_ENABLE | portAPU_PRESENT | portFCM_FPU_PRESENT )
+
+
+extern const unsigned _SDA_BASE_;
+extern const unsigned _SDA2_BASE_;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the system timer to generate the tick interrupt.
+ */
+static void prvSetupTimerInterrupt( void );
+
+/*
+ * The handler for the tick interrupt - defined in portasm.s.
+ */
+extern void vPortTickISR( void );
+
+/*
+ * The handler for the yield function - defined in portasm.s.
+ */
+extern void vPortYield( void );
+
+/*
+ * Function to start the scheduler running by starting the highest
+ * priority task that has thus far been created.
+ */
+extern void vPortStartFirstTask( void );
+
+/*-----------------------------------------------------------*/
+
+/* Structure used to hold the state of the interrupt controller. */
+static XIntc xInterruptController;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if the task had been
+ * interrupted.
+ *
+ * See the header file portable.h.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+ /* Place a known value at the bottom of the stack for debugging. */
+ *pxTopOfStack = 0xDEADBEEF;
+ pxTopOfStack--;
+
+ /* EABI stack frame. */
+ pxTopOfStack -= 20; /* Previous backchain and LR, R31 to R4 inclusive. */
+
+ /* Parameters in R13. */
+ *pxTopOfStack = ( StackType_t ) &_SDA_BASE_; /* address of the first small data area */
+ pxTopOfStack -= 10;
+
+ /* Parameters in R3. */
+ *pxTopOfStack = ( StackType_t ) pvParameters;
+ pxTopOfStack--;
+
+ /* Parameters in R2. */
+ *pxTopOfStack = ( StackType_t ) &_SDA2_BASE_; /* address of the second small data area */
+ pxTopOfStack--;
+
+ /* R1 is the stack pointer so is omitted. */
+
+ *pxTopOfStack = 0x10000001UL;; /* R0. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x00000000UL; /* USPRG0. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x00000000UL; /* CR. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x00000000UL; /* XER. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x00000000UL; /* CTR. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) vPortEndScheduler; /* LR. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* SRR0. */
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_MSR;/* SRR1. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) vPortEndScheduler;/* Next LR. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x00000000UL;/* Backchain. */
+
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+ prvSetupTimerInterrupt();
+ XExc_RegisterHandler( XEXC_ID_SYSTEM_CALL, ( XExceptionHandler ) vPortYield, ( void * ) 0 );
+ vPortStartFirstTask();
+
+ /* Should not get here as the tasks are now running! */
+ return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+ /* Not implemented. */
+ for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Hardware initialisation to generate the RTOS tick.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+const uint32_t ulInterval = ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL );
+
+ XTime_DECClearInterrupt();
+ XTime_FITClearInterrupt();
+ XTime_WDTClearInterrupt();
+ XTime_WDTDisableInterrupt();
+ XTime_FITDisableInterrupt();
+
+ XExc_RegisterHandler( XEXC_ID_DEC_INT, ( XExceptionHandler ) vPortTickISR, ( void * ) 0 );
+
+ XTime_DECEnableAutoReload();
+ XTime_DECSetInterval( ulInterval );
+ XTime_DECEnableInterrupt();
+}
+/*-----------------------------------------------------------*/
+
+void vPortISRHandler( void *pvNullDoNotUse )
+{
+uint32_t ulInterruptStatus, ulInterruptMask = 1UL;
+BaseType_t xInterruptNumber;
+XIntc_Config *pxInterruptController;
+XIntc_VectorTableEntry *pxTable;
+
+ /* Just to remove compiler warning. */
+ ( void ) pvNullDoNotUse;
+
+ /* Get the configuration by using the device ID - in this case it is
+ assumed that only one interrupt controller is being used. */
+ pxInterruptController = &XIntc_ConfigTable[ XPAR_XPS_INTC_0_DEVICE_ID ];
+
+ /* Which interrupts are pending? */
+ ulInterruptStatus = XIntc_mGetIntrStatus( pxInterruptController->BaseAddress );
+
+ for( xInterruptNumber = 0; xInterruptNumber < XPAR_INTC_MAX_NUM_INTR_INPUTS; xInterruptNumber++ )
+ {
+ if( ulInterruptStatus & 0x01UL )
+ {
+ /* Clear the pending interrupt. */
+ XIntc_mAckIntr( pxInterruptController->BaseAddress, ulInterruptMask );
+
+ /* Call the registered handler. */
+ pxTable = &( pxInterruptController->HandlerTable[ xInterruptNumber ] );
+ pxTable->Handler( pxTable->CallBackRef );
+ }
+
+ /* Check the next interrupt. */
+ ulInterruptMask <<= 0x01UL;
+ ulInterruptStatus >>= 0x01UL;
+
+ /* Have we serviced all interrupts? */
+ if( ulInterruptStatus == 0UL )
+ {
+ break;
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vPortSetupInterruptController( void )
+{
+extern void vPortISRWrapper( void );
+
+ /* Perform all library calls necessary to initialise the exception table
+ and interrupt controller. This assumes only one interrupt controller is in
+ use. */
+ XExc_mDisableExceptions( XEXC_NON_CRITICAL );
+ XExc_Init();
+
+ /* The library functions save the context - we then jump to a wrapper to
+ save the stack into the TCB. The wrapper then calls the handler defined
+ above. */
+ XExc_RegisterHandler( XEXC_ID_NON_CRITICAL_INT, ( XExceptionHandler ) vPortISRWrapper, NULL );
+ XIntc_Initialize( &xInterruptController, XPAR_XPS_INTC_0_DEVICE_ID );
+ XIntc_Start( &xInterruptController, XIN_REAL_MODE );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )
+{
+BaseType_t xReturn = pdFAIL;
+
+ /* This function is defined here so the scope of xInterruptController can
+ remain within this file. */
+
+ if( XST_SUCCESS == XIntc_Connect( &xInterruptController, ucInterruptID, pxHandler, pvCallBackRef ) )
+ {
+ XIntc_Enable( &xInterruptController, ucInterruptID );
+ xReturn = pdPASS;
+ }
+
+ return xReturn;
+}
diff --git a/portable/GCC/PPC440_Xilinx/portasm.S b/portable/GCC/PPC440_Xilinx/portasm.S
index f443e8d..49866e8 100644
--- a/portable/GCC/PPC440_Xilinx/portasm.S
+++ b/portable/GCC/PPC440_Xilinx/portasm.S
@@ -1,383 +1,381 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#include "FreeRTOSConfig.h"
-
- .extern pxCurrentTCB
- .extern vTaskSwitchContext
- .extern xTaskIncrementTick
- .extern vPortISRHandler
-
- .global vPortStartFirstTask
- .global vPortYield
- .global vPortTickISR
- .global vPortISRWrapper
- .global vPortSaveFPURegisters
- .global vPortRestoreFPURegisters
-
-.set BChainField, 0
-.set NextLRField, BChainField + 4
-.set MSRField, NextLRField + 4
-.set PCField, MSRField + 4
-.set LRField, PCField + 4
-.set CTRField, LRField + 4
-.set XERField, CTRField + 4
-.set CRField, XERField + 4
-.set USPRG0Field, CRField + 4
-.set r0Field, USPRG0Field + 4
-.set r2Field, r0Field + 4
-.set r3r31Field, r2Field + 4
-.set IFrameSize, r3r31Field + ( ( 31 - 3 ) + 1 ) * 4
-
-
-.macro portSAVE_STACK_POINTER_AND_LR
-
- /* Get the address of the TCB. */
- xor R0, R0, R0
- addis R2, R0, pxCurrentTCB@ha
- lwz R2, pxCurrentTCB@l( R2 )
-
- /* Store the stack pointer into the TCB */
- stw SP, 0( R2 )
-
- /* Save the link register */
- stwu R1, -24( R1 )
- mflr R0
- stw R31, 20( R1 )
- stw R0, 28( R1 )
- mr R31, r1
-
-.endm
-
-.macro portRESTORE_STACK_POINTER_AND_LR
-
- /* Restore the link register */
- lwz R11, 0( R1 )
- lwz R0, 4( R11 )
- mtlr R0
- lwz R31, -4( R11 )
- mr R1, R11
-
- /* Get the address of the TCB. */
- xor R0, R0, R0
- addis SP, R0, pxCurrentTCB@ha
- lwz SP, pxCurrentTCB@l( R1 )
-
- /* Get the task stack pointer from the TCB. */
- lwz SP, 0( SP )
-
-.endm
-
-
-vPortStartFirstTask:
-
- /* Get the address of the TCB. */
- xor R0, R0, R0
- addis SP, R0, pxCurrentTCB@ha
- lwz SP, pxCurrentTCB@l( SP )
-
- /* Get the task stack pointer from the TCB. */
- lwz SP, 0( SP )
-
- /* Restore MSR register to SRR1. */
- lwz R0, MSRField(R1)
- mtsrr1 R0
-
- /* Restore current PC location to SRR0. */
- lwz R0, PCField(R1)
- mtsrr0 R0
-
- /* Save USPRG0 register */
- lwz R0, USPRG0Field(R1)
- mtspr 0x100,R0
-
- /* Restore Condition register */
- lwz R0, CRField(R1)
- mtcr R0
-
- /* Restore Fixed Point Exception register */
- lwz R0, XERField(R1)
- mtxer R0
-
- /* Restore Counter register */
- lwz R0, CTRField(R1)
- mtctr R0
-
- /* Restore Link register */
- lwz R0, LRField(R1)
- mtlr R0
-
- /* Restore remaining GPR registers. */
- lmw R3,r3r31Field(R1)
-
- /* Restore r0 and r2. */
- lwz R0, r0Field(R1)
- lwz R2, r2Field(R1)
-
- /* Remove frame from stack */
- addi R1,R1,IFrameSize
-
- /* Return into the first task */
- rfi
-
-
-
-vPortYield:
-
- portSAVE_STACK_POINTER_AND_LR
- bl vTaskSwitchContext
- portRESTORE_STACK_POINTER_AND_LR
- blr
-
-vPortTickISR:
-
- portSAVE_STACK_POINTER_AND_LR
- bl xTaskIncrementTick
-
- #if configUSE_PREEMPTION == 1
- bl vTaskSwitchContext
- #endif
-
- /* Clear the interrupt */
- lis R0, 2048
- mttsr R0
-
- portRESTORE_STACK_POINTER_AND_LR
- blr
-
-vPortISRWrapper:
-
- portSAVE_STACK_POINTER_AND_LR
- bl vPortISRHandler
- portRESTORE_STACK_POINTER_AND_LR
- blr
-
-#if configUSE_FPU == 1
-
-vPortSaveFPURegisters:
-
- /* Enable APU and mark FPU as present. */
- mfmsr r0
- xor r30, r30, r30
- oris r30, r30, 512
- ori r30, r30, 8192
- or r0, r0, r30
- mtmsr r0
-
-#ifdef USE_DP_FPU
-
- /* Buffer address is in r3. Save each flop register into an offset from
- this buffer address. */
- stfd f0, 0(r3)
- stfd f1, 8(r3)
- stfd f2, 16(r3)
- stfd f3, 24(r3)
- stfd f4, 32(r3)
- stfd f5, 40(r3)
- stfd f6, 48(r3)
- stfd f7, 56(r3)
- stfd f8, 64(r3)
- stfd f9, 72(r3)
- stfd f10, 80(r3)
- stfd f11, 88(r3)
- stfd f12, 96(r3)
- stfd f13, 104(r3)
- stfd f14, 112(r3)
- stfd f15, 120(r3)
- stfd f16, 128(r3)
- stfd f17, 136(r3)
- stfd f18, 144(r3)
- stfd f19, 152(r3)
- stfd f20, 160(r3)
- stfd f21, 168(r3)
- stfd f22, 176(r3)
- stfd f23, 184(r3)
- stfd f24, 192(r3)
- stfd f25, 200(r3)
- stfd f26, 208(r3)
- stfd f27, 216(r3)
- stfd f28, 224(r3)
- stfd f29, 232(r3)
- stfd f30, 240(r3)
- stfd f31, 248(r3)
-
- /* Also save the FPSCR. */
- mffs f31
- stfs f31, 256(r3)
-
-#else
-
- /* Buffer address is in r3. Save each flop register into an offset from
- this buffer address. */
- stfs f0, 0(r3)
- stfs f1, 4(r3)
- stfs f2, 8(r3)
- stfs f3, 12(r3)
- stfs f4, 16(r3)
- stfs f5, 20(r3)
- stfs f6, 24(r3)
- stfs f7, 28(r3)
- stfs f8, 32(r3)
- stfs f9, 36(r3)
- stfs f10, 40(r3)
- stfs f11, 44(r3)
- stfs f12, 48(r3)
- stfs f13, 52(r3)
- stfs f14, 56(r3)
- stfs f15, 60(r3)
- stfs f16, 64(r3)
- stfs f17, 68(r3)
- stfs f18, 72(r3)
- stfs f19, 76(r3)
- stfs f20, 80(r3)
- stfs f21, 84(r3)
- stfs f22, 88(r3)
- stfs f23, 92(r3)
- stfs f24, 96(r3)
- stfs f25, 100(r3)
- stfs f26, 104(r3)
- stfs f27, 108(r3)
- stfs f28, 112(r3)
- stfs f29, 116(r3)
- stfs f30, 120(r3)
- stfs f31, 124(r3)
-
- /* Also save the FPSCR. */
- mffs f31
- stfs f31, 128(r3)
-
-#endif
-
- blr
-
-#endif /* configUSE_FPU. */
-
-
-#if configUSE_FPU == 1
-
-vPortRestoreFPURegisters:
-
- /* Enable APU and mark FPU as present. */
- mfmsr r0
- xor r30, r30, r30
- oris r30, r30, 512
- ori r30, r30, 8192
- or r0, r0, r30
- mtmsr r0
-
-#ifdef USE_DP_FPU
-
- /* Buffer address is in r3. Restore each flop register from an offset
- into this buffer.
-
- First the FPSCR. */
- lfs f31, 256(r3)
- mtfsf f31, 7
-
- lfd f0, 0(r3)
- lfd f1, 8(r3)
- lfd f2, 16(r3)
- lfd f3, 24(r3)
- lfd f4, 32(r3)
- lfd f5, 40(r3)
- lfd f6, 48(r3)
- lfd f7, 56(r3)
- lfd f8, 64(r3)
- lfd f9, 72(r3)
- lfd f10, 80(r3)
- lfd f11, 88(r3)
- lfd f12, 96(r3)
- lfd f13, 104(r3)
- lfd f14, 112(r3)
- lfd f15, 120(r3)
- lfd f16, 128(r3)
- lfd f17, 136(r3)
- lfd f18, 144(r3)
- lfd f19, 152(r3)
- lfd f20, 160(r3)
- lfd f21, 168(r3)
- lfd f22, 176(r3)
- lfd f23, 184(r3)
- lfd f24, 192(r3)
- lfd f25, 200(r3)
- lfd f26, 208(r3)
- lfd f27, 216(r3)
- lfd f28, 224(r3)
- lfd f29, 232(r3)
- lfd f30, 240(r3)
- lfd f31, 248(r3)
-
-#else
-
- /* Buffer address is in r3. Restore each flop register from an offset
- into this buffer.
-
- First the FPSCR. */
- lfs f31, 128(r3)
- mtfsf f31, 7
-
- lfs f0, 0(r3)
- lfs f1, 4(r3)
- lfs f2, 8(r3)
- lfs f3, 12(r3)
- lfs f4, 16(r3)
- lfs f5, 20(r3)
- lfs f6, 24(r3)
- lfs f7, 28(r3)
- lfs f8, 32(r3)
- lfs f9, 36(r3)
- lfs f10, 40(r3)
- lfs f11, 44(r3)
- lfs f12, 48(r3)
- lfs f13, 52(r3)
- lfs f14, 56(r3)
- lfs f15, 60(r3)
- lfs f16, 64(r3)
- lfs f17, 68(r3)
- lfs f18, 72(r3)
- lfs f19, 76(r3)
- lfs f20, 80(r3)
- lfs f21, 84(r3)
- lfs f22, 88(r3)
- lfs f23, 92(r3)
- lfs f24, 96(r3)
- lfs f25, 100(r3)
- lfs f26, 104(r3)
- lfs f27, 108(r3)
- lfs f28, 112(r3)
- lfs f29, 116(r3)
- lfs f30, 120(r3)
- lfs f31, 124(r3)
-
-#endif
-
- blr
-
-#endif /* configUSE_FPU. */
-
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#include "FreeRTOSConfig.h"
+
+ .extern pxCurrentTCB
+ .extern vTaskSwitchContext
+ .extern xTaskIncrementTick
+ .extern vPortISRHandler
+
+ .global vPortStartFirstTask
+ .global vPortYield
+ .global vPortTickISR
+ .global vPortISRWrapper
+ .global vPortSaveFPURegisters
+ .global vPortRestoreFPURegisters
+
+.set BChainField, 0
+.set NextLRField, BChainField + 4
+.set MSRField, NextLRField + 4
+.set PCField, MSRField + 4
+.set LRField, PCField + 4
+.set CTRField, LRField + 4
+.set XERField, CTRField + 4
+.set CRField, XERField + 4
+.set USPRG0Field, CRField + 4
+.set r0Field, USPRG0Field + 4
+.set r2Field, r0Field + 4
+.set r3r31Field, r2Field + 4
+.set IFrameSize, r3r31Field + ( ( 31 - 3 ) + 1 ) * 4
+
+
+.macro portSAVE_STACK_POINTER_AND_LR
+
+ /* Get the address of the TCB. */
+ xor R0, R0, R0
+ addis R2, R0, pxCurrentTCB@ha
+ lwz R2, pxCurrentTCB@l( R2 )
+
+ /* Store the stack pointer into the TCB */
+ stw SP, 0( R2 )
+
+ /* Save the link register */
+ stwu R1, -24( R1 )
+ mflr R0
+ stw R31, 20( R1 )
+ stw R0, 28( R1 )
+ mr R31, r1
+
+.endm
+
+.macro portRESTORE_STACK_POINTER_AND_LR
+
+ /* Restore the link register */
+ lwz R11, 0( R1 )
+ lwz R0, 4( R11 )
+ mtlr R0
+ lwz R31, -4( R11 )
+ mr R1, R11
+
+ /* Get the address of the TCB. */
+ xor R0, R0, R0
+ addis SP, R0, pxCurrentTCB@ha
+ lwz SP, pxCurrentTCB@l( R1 )
+
+ /* Get the task stack pointer from the TCB. */
+ lwz SP, 0( SP )
+
+.endm
+
+
+vPortStartFirstTask:
+
+ /* Get the address of the TCB. */
+ xor R0, R0, R0
+ addis SP, R0, pxCurrentTCB@ha
+ lwz SP, pxCurrentTCB@l( SP )
+
+ /* Get the task stack pointer from the TCB. */
+ lwz SP, 0( SP )
+
+ /* Restore MSR register to SRR1. */
+ lwz R0, MSRField(R1)
+ mtsrr1 R0
+
+ /* Restore current PC location to SRR0. */
+ lwz R0, PCField(R1)
+ mtsrr0 R0
+
+ /* Save USPRG0 register */
+ lwz R0, USPRG0Field(R1)
+ mtspr 0x100,R0
+
+ /* Restore Condition register */
+ lwz R0, CRField(R1)
+ mtcr R0
+
+ /* Restore Fixed Point Exception register */
+ lwz R0, XERField(R1)
+ mtxer R0
+
+ /* Restore Counter register */
+ lwz R0, CTRField(R1)
+ mtctr R0
+
+ /* Restore Link register */
+ lwz R0, LRField(R1)
+ mtlr R0
+
+ /* Restore remaining GPR registers. */
+ lmw R3,r3r31Field(R1)
+
+ /* Restore r0 and r2. */
+ lwz R0, r0Field(R1)
+ lwz R2, r2Field(R1)
+
+ /* Remove frame from stack */
+ addi R1,R1,IFrameSize
+
+ /* Return into the first task */
+ rfi
+
+
+
+vPortYield:
+
+ portSAVE_STACK_POINTER_AND_LR
+ bl vTaskSwitchContext
+ portRESTORE_STACK_POINTER_AND_LR
+ blr
+
+vPortTickISR:
+
+ portSAVE_STACK_POINTER_AND_LR
+ bl xTaskIncrementTick
+
+ #if configUSE_PREEMPTION == 1
+ bl vTaskSwitchContext
+ #endif
+
+ /* Clear the interrupt */
+ lis R0, 2048
+ mttsr R0
+
+ portRESTORE_STACK_POINTER_AND_LR
+ blr
+
+vPortISRWrapper:
+
+ portSAVE_STACK_POINTER_AND_LR
+ bl vPortISRHandler
+ portRESTORE_STACK_POINTER_AND_LR
+ blr
+
+#if configUSE_FPU == 1
+
+vPortSaveFPURegisters:
+
+ /* Enable APU and mark FPU as present. */
+ mfmsr r0
+ xor r30, r30, r30
+ oris r30, r30, 512
+ ori r30, r30, 8192
+ or r0, r0, r30
+ mtmsr r0
+
+#ifdef USE_DP_FPU
+
+ /* Buffer address is in r3. Save each flop register into an offset from
+ this buffer address. */
+ stfd f0, 0(r3)
+ stfd f1, 8(r3)
+ stfd f2, 16(r3)
+ stfd f3, 24(r3)
+ stfd f4, 32(r3)
+ stfd f5, 40(r3)
+ stfd f6, 48(r3)
+ stfd f7, 56(r3)
+ stfd f8, 64(r3)
+ stfd f9, 72(r3)
+ stfd f10, 80(r3)
+ stfd f11, 88(r3)
+ stfd f12, 96(r3)
+ stfd f13, 104(r3)
+ stfd f14, 112(r3)
+ stfd f15, 120(r3)
+ stfd f16, 128(r3)
+ stfd f17, 136(r3)
+ stfd f18, 144(r3)
+ stfd f19, 152(r3)
+ stfd f20, 160(r3)
+ stfd f21, 168(r3)
+ stfd f22, 176(r3)
+ stfd f23, 184(r3)
+ stfd f24, 192(r3)
+ stfd f25, 200(r3)
+ stfd f26, 208(r3)
+ stfd f27, 216(r3)
+ stfd f28, 224(r3)
+ stfd f29, 232(r3)
+ stfd f30, 240(r3)
+ stfd f31, 248(r3)
+
+ /* Also save the FPSCR. */
+ mffs f31
+ stfs f31, 256(r3)
+
+#else
+
+ /* Buffer address is in r3. Save each flop register into an offset from
+ this buffer address. */
+ stfs f0, 0(r3)
+ stfs f1, 4(r3)
+ stfs f2, 8(r3)
+ stfs f3, 12(r3)
+ stfs f4, 16(r3)
+ stfs f5, 20(r3)
+ stfs f6, 24(r3)
+ stfs f7, 28(r3)
+ stfs f8, 32(r3)
+ stfs f9, 36(r3)
+ stfs f10, 40(r3)
+ stfs f11, 44(r3)
+ stfs f12, 48(r3)
+ stfs f13, 52(r3)
+ stfs f14, 56(r3)
+ stfs f15, 60(r3)
+ stfs f16, 64(r3)
+ stfs f17, 68(r3)
+ stfs f18, 72(r3)
+ stfs f19, 76(r3)
+ stfs f20, 80(r3)
+ stfs f21, 84(r3)
+ stfs f22, 88(r3)
+ stfs f23, 92(r3)
+ stfs f24, 96(r3)
+ stfs f25, 100(r3)
+ stfs f26, 104(r3)
+ stfs f27, 108(r3)
+ stfs f28, 112(r3)
+ stfs f29, 116(r3)
+ stfs f30, 120(r3)
+ stfs f31, 124(r3)
+
+ /* Also save the FPSCR. */
+ mffs f31
+ stfs f31, 128(r3)
+
+#endif
+
+ blr
+
+#endif /* configUSE_FPU. */
+
+
+#if configUSE_FPU == 1
+
+vPortRestoreFPURegisters:
+
+ /* Enable APU and mark FPU as present. */
+ mfmsr r0
+ xor r30, r30, r30
+ oris r30, r30, 512
+ ori r30, r30, 8192
+ or r0, r0, r30
+ mtmsr r0
+
+#ifdef USE_DP_FPU
+
+ /* Buffer address is in r3. Restore each flop register from an offset
+ into this buffer.
+
+ First the FPSCR. */
+ lfs f31, 256(r3)
+ mtfsf f31, 7
+
+ lfd f0, 0(r3)
+ lfd f1, 8(r3)
+ lfd f2, 16(r3)
+ lfd f3, 24(r3)
+ lfd f4, 32(r3)
+ lfd f5, 40(r3)
+ lfd f6, 48(r3)
+ lfd f7, 56(r3)
+ lfd f8, 64(r3)
+ lfd f9, 72(r3)
+ lfd f10, 80(r3)
+ lfd f11, 88(r3)
+ lfd f12, 96(r3)
+ lfd f13, 104(r3)
+ lfd f14, 112(r3)
+ lfd f15, 120(r3)
+ lfd f16, 128(r3)
+ lfd f17, 136(r3)
+ lfd f18, 144(r3)
+ lfd f19, 152(r3)
+ lfd f20, 160(r3)
+ lfd f21, 168(r3)
+ lfd f22, 176(r3)
+ lfd f23, 184(r3)
+ lfd f24, 192(r3)
+ lfd f25, 200(r3)
+ lfd f26, 208(r3)
+ lfd f27, 216(r3)
+ lfd f28, 224(r3)
+ lfd f29, 232(r3)
+ lfd f30, 240(r3)
+ lfd f31, 248(r3)
+
+#else
+
+ /* Buffer address is in r3. Restore each flop register from an offset
+ into this buffer.
+
+ First the FPSCR. */
+ lfs f31, 128(r3)
+ mtfsf f31, 7
+
+ lfs f0, 0(r3)
+ lfs f1, 4(r3)
+ lfs f2, 8(r3)
+ lfs f3, 12(r3)
+ lfs f4, 16(r3)
+ lfs f5, 20(r3)
+ lfs f6, 24(r3)
+ lfs f7, 28(r3)
+ lfs f8, 32(r3)
+ lfs f9, 36(r3)
+ lfs f10, 40(r3)
+ lfs f11, 44(r3)
+ lfs f12, 48(r3)
+ lfs f13, 52(r3)
+ lfs f14, 56(r3)
+ lfs f15, 60(r3)
+ lfs f16, 64(r3)
+ lfs f17, 68(r3)
+ lfs f18, 72(r3)
+ lfs f19, 76(r3)
+ lfs f20, 80(r3)
+ lfs f21, 84(r3)
+ lfs f22, 88(r3)
+ lfs f23, 92(r3)
+ lfs f24, 96(r3)
+ lfs f25, 100(r3)
+ lfs f26, 104(r3)
+ lfs f27, 108(r3)
+ lfs f28, 112(r3)
+ lfs f29, 116(r3)
+ lfs f30, 120(r3)
+ lfs f31, 124(r3)
+
+#endif
+
+ blr
+
+#endif /* configUSE_FPU. */
diff --git a/portable/GCC/PPC440_Xilinx/portmacro.h b/portable/GCC/PPC440_Xilinx/portmacro.h
index cfbc15a..eaad8fe 100644
--- a/portable/GCC/PPC440_Xilinx/portmacro.h
+++ b/portable/GCC/PPC440_Xilinx/portmacro.h
@@ -1,119 +1,118 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#include "xexception_l.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT short
-#define portSTACK_TYPE uint32_t
-#define portBASE_TYPE long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
-#else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* This port uses the critical nesting count from the TCB rather than
-maintaining a separate value and then saving this value in the task stack. */
-#define portCRITICAL_NESTING_IN_TCB 1
-
-/* Interrupt control macros. */
-#define portDISABLE_INTERRUPTS() XExc_mDisableExceptions( XEXC_NON_CRITICAL );
-#define portENABLE_INTERRUPTS() XExc_mEnableExceptions( XEXC_NON_CRITICAL );
-
-/*-----------------------------------------------------------*/
-
-/* Critical section macros. */
-void vTaskEnterCritical( void );
-void vTaskExitCritical( void );
-#define portENTER_CRITICAL() vTaskEnterCritical()
-#define portEXIT_CRITICAL() vTaskExitCritical()
-
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-void vPortYield( void );
-#define portYIELD() asm volatile ( "SC \n\t NOP" )
-#define portYIELD_FROM_ISR() vTaskSwitchContext()
-
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portBYTE_ALIGNMENT 8
-#define portSTACK_GROWTH ( -1 )
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP() asm volatile ( "NOP" )
-
-/* There are 32 * 32bit floating point regieters, plus the FPSCR to save. */
-#define portNO_FLOP_REGISTERS_TO_SAVE ( 32 + 1 )
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-/* Port specific interrupt handling functions. */
-void vPortSetupInterruptController( void );
-BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#include "xexception_l.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* This port uses the critical nesting count from the TCB rather than
+maintaining a separate value and then saving this value in the task stack. */
+#define portCRITICAL_NESTING_IN_TCB 1
+
+/* Interrupt control macros. */
+#define portDISABLE_INTERRUPTS() XExc_mDisableExceptions( XEXC_NON_CRITICAL );
+#define portENABLE_INTERRUPTS() XExc_mEnableExceptions( XEXC_NON_CRITICAL );
+
+/*-----------------------------------------------------------*/
+
+/* Critical section macros. */
+void vTaskEnterCritical( void );
+void vTaskExitCritical( void );
+#define portENTER_CRITICAL() vTaskEnterCritical()
+#define portEXIT_CRITICAL() vTaskExitCritical()
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+void vPortYield( void );
+#define portYIELD() asm volatile ( "SC \n\t NOP" )
+#define portYIELD_FROM_ISR() vTaskSwitchContext()
+
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT 8
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP() asm volatile ( "NOP" )
+
+/* There are 32 * 32bit floating point regieters, plus the FPSCR to save. */
+#define portNO_FLOP_REGISTERS_TO_SAVE ( 32 + 1 )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+/* Port specific interrupt handling functions. */
+void vPortSetupInterruptController( void );
+BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/portable/GCC/RISC-V/Documentation.url b/portable/GCC/RISC-V/Documentation.url
index c7819d5..5546f87 100644
--- a/portable/GCC/RISC-V/Documentation.url
+++ b/portable/GCC/RISC-V/Documentation.url
@@ -1,5 +1,5 @@
-[{000214A0-0000-0000-C000-000000000046}]
-Prop3=19,11
-[InternetShortcut]
-IDList=
-URL=https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
+[{000214A0-0000-0000-C000-000000000046}]
+Prop3=19,11
+[InternetShortcut]
+IDList=
+URL=https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
diff --git a/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h b/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h
index 67a537a..262c337 100644
--- a/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h
+++ b/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h
@@ -1,108 +1,108 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*
- * The FreeRTOS kernel's RISC-V port is split between the the code that is
- * common across all currently supported RISC-V chips (implementations of the
- * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
- *
- * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
- * is common to all currently supported RISC-V chips. There is only one
- * portASM.S file because the same file is built for all RISC-V target chips.
- *
- * + Header files called freertos_risc_v_chip_specific_extensions.h contain the
- * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
- * chip. There are multiple freertos_risc_v_chip_specific_extensions.h files
- * as there are multiple RISC-V chip implementations.
- *
- * !!!NOTE!!!
- * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h
- * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the
- * compiler's!) include path. For example, if the chip in use includes a core
- * local interrupter (CLINT) and does not include any chip specific register
- * extensions then add the path below to the assembler's include path:
- * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
- *
- */
-
-/*
- * This freertos_risc_v_chip_specific_extensions.h is for use with Pulpino Ri5cy
- * devices, developed and tested using the Vega board RV32M1RM.
- */
-
-#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
-#define __FREERTOS_RISC_V_EXTENSIONS_H__
-
-#define portasmHAS_MTIME 0
-
-/* Constants to define the additional registers found on the Pulpino RI5KY. */
-#define lpstart0 0x7b0
-#define lpend0 0x7b1
-#define lpcount0 0x7b2
-#define lpstart1 0x7b4
-#define lpend1 0x7b5
-#define lpcount1 0x7b6
-
-/* Six additional registers to save and restore, as per the #defines above. */
-#define portasmADDITIONAL_CONTEXT_SIZE 6 /* Must be even number on 32-bit cores. */
-
-/* Save additional registers found on the Pulpino. */
-.macro portasmSAVE_ADDITIONAL_REGISTERS
- addi sp, sp, -(portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE) /* Make room for the additional registers. */
- csrr t0, lpstart0 /* Load additional registers into accessible temporary registers. */
- csrr t1, lpend0
- csrr t2, lpcount0
- csrr t3, lpstart1
- csrr t4, lpend1
- csrr t5, lpcount1
- sw t0, 1 * portWORD_SIZE( sp )
- sw t1, 2 * portWORD_SIZE( sp )
- sw t2, 3 * portWORD_SIZE( sp )
- sw t3, 4 * portWORD_SIZE( sp )
- sw t4, 5 * portWORD_SIZE( sp )
- sw t5, 6 * portWORD_SIZE( sp )
- .endm
-
-/* Restore the additional registers found on the Pulpino. */
-.macro portasmRESTORE_ADDITIONAL_REGISTERS
- lw t0, 1 * portWORD_SIZE( sp ) /* Load additional registers into accessible temporary registers. */
- lw t1, 2 * portWORD_SIZE( sp )
- lw t2, 3 * portWORD_SIZE( sp )
- lw t3, 4 * portWORD_SIZE( sp )
- lw t4, 5 * portWORD_SIZE( sp )
- lw t5, 6 * portWORD_SIZE( sp )
- csrw lpstart0, t0
- csrw lpend0, t1
- csrw lpcount0, t2
- csrw lpstart1, t3
- csrw lpend1, t4
- csrw lpcount1, t5
- addi sp, sp, (portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE )/* Remove space added for additional registers. */
- .endm
-
-#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*
+ * The FreeRTOS kernel's RISC-V port is split between the the code that is
+ * common across all currently supported RISC-V chips (implementations of the
+ * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
+ *
+ * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
+ * is common to all currently supported RISC-V chips. There is only one
+ * portASM.S file because the same file is built for all RISC-V target chips.
+ *
+ * + Header files called freertos_risc_v_chip_specific_extensions.h contain the
+ * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
+ * chip. There are multiple freertos_risc_v_chip_specific_extensions.h files
+ * as there are multiple RISC-V chip implementations.
+ *
+ * !!!NOTE!!!
+ * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h
+ * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the
+ * compiler's!) include path. For example, if the chip in use includes a core
+ * local interrupter (CLINT) and does not include any chip specific register
+ * extensions then add the path below to the assembler's include path:
+ * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
+ *
+ */
+
+/*
+ * This freertos_risc_v_chip_specific_extensions.h is for use with Pulpino Ri5cy
+ * devices, developed and tested using the Vega board RV32M1RM.
+ */
+
+#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
+#define __FREERTOS_RISC_V_EXTENSIONS_H__
+
+#define portasmHAS_MTIME 0
+
+/* Constants to define the additional registers found on the Pulpino RI5KY. */
+#define lpstart0 0x7b0
+#define lpend0 0x7b1
+#define lpcount0 0x7b2
+#define lpstart1 0x7b4
+#define lpend1 0x7b5
+#define lpcount1 0x7b6
+
+/* Six additional registers to save and restore, as per the #defines above. */
+#define portasmADDITIONAL_CONTEXT_SIZE 6 /* Must be even number on 32-bit cores. */
+
+/* Save additional registers found on the Pulpino. */
+.macro portasmSAVE_ADDITIONAL_REGISTERS
+ addi sp, sp, -(portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE) /* Make room for the additional registers. */
+ csrr t0, lpstart0 /* Load additional registers into accessible temporary registers. */
+ csrr t1, lpend0
+ csrr t2, lpcount0
+ csrr t3, lpstart1
+ csrr t4, lpend1
+ csrr t5, lpcount1
+ sw t0, 1 * portWORD_SIZE( sp )
+ sw t1, 2 * portWORD_SIZE( sp )
+ sw t2, 3 * portWORD_SIZE( sp )
+ sw t3, 4 * portWORD_SIZE( sp )
+ sw t4, 5 * portWORD_SIZE( sp )
+ sw t5, 6 * portWORD_SIZE( sp )
+ .endm
+
+/* Restore the additional registers found on the Pulpino. */
+.macro portasmRESTORE_ADDITIONAL_REGISTERS
+ lw t0, 1 * portWORD_SIZE( sp ) /* Load additional registers into accessible temporary registers. */
+ lw t1, 2 * portWORD_SIZE( sp )
+ lw t2, 3 * portWORD_SIZE( sp )
+ lw t3, 4 * portWORD_SIZE( sp )
+ lw t4, 5 * portWORD_SIZE( sp )
+ lw t5, 6 * portWORD_SIZE( sp )
+ csrw lpstart0, t0
+ csrw lpend0, t1
+ csrw lpcount0, t2
+ csrw lpstart1, t3
+ csrw lpend1, t4
+ csrw lpcount1, t5
+ addi sp, sp, (portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE )/* Remove space added for additional registers. */
+ .endm
+
+#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
diff --git a/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h b/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
index 0e4deee..65204a2 100644
--- a/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
+++ b/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
@@ -1,69 +1,69 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*
- * The FreeRTOS kernel's RISC-V port is split between the the code that is
- * common across all currently supported RISC-V chips (implementations of the
- * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
- *
- * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
- * is common to all currently supported RISC-V chips. There is only one
- * portASM.S file because the same file is built for all RISC-V target chips.
- *
- * + Header files called freertos_risc_v_chip_specific_extensions.h contain the
- * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
- * chip. There are multiple freertos_risc_v_chip_specific_extensions.h files
- * as there are multiple RISC-V chip implementations.
- *
- * !!!NOTE!!!
- * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h
- * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the
- * compiler's!) include path. For example, if the chip in use includes a core
- * local interrupter (CLINT) and does not include any chip specific register
- * extensions then add the path below to the assembler's include path:
- * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
- *
- */
-
-
-#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
-#define __FREERTOS_RISC_V_EXTENSIONS_H__
-
-#define portasmHAS_SIFIVE_CLINT 1
-#define portasmHAS_MTIME 1
-#define portasmADDITIONAL_CONTEXT_SIZE 0 /* Must be even number on 32-bit cores. */
-
-.macro portasmSAVE_ADDITIONAL_REGISTERS
- /* No additional registers to save, so this macro does nothing. */
- .endm
-
-.macro portasmRESTORE_ADDITIONAL_REGISTERS
- /* No additional registers to restore, so this macro does nothing. */
- .endm
-
-#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*
+ * The FreeRTOS kernel's RISC-V port is split between the the code that is
+ * common across all currently supported RISC-V chips (implementations of the
+ * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
+ *
+ * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
+ * is common to all currently supported RISC-V chips. There is only one
+ * portASM.S file because the same file is built for all RISC-V target chips.
+ *
+ * + Header files called freertos_risc_v_chip_specific_extensions.h contain the
+ * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
+ * chip. There are multiple freertos_risc_v_chip_specific_extensions.h files
+ * as there are multiple RISC-V chip implementations.
+ *
+ * !!!NOTE!!!
+ * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h
+ * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the
+ * compiler's!) include path. For example, if the chip in use includes a core
+ * local interrupter (CLINT) and does not include any chip specific register
+ * extensions then add the path below to the assembler's include path:
+ * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
+ *
+ */
+
+
+#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
+#define __FREERTOS_RISC_V_EXTENSIONS_H__
+
+#define portasmHAS_SIFIVE_CLINT 1
+#define portasmHAS_MTIME 1
+#define portasmADDITIONAL_CONTEXT_SIZE 0 /* Must be even number on 32-bit cores. */
+
+.macro portasmSAVE_ADDITIONAL_REGISTERS
+ /* No additional registers to save, so this macro does nothing. */
+ .endm
+
+.macro portasmRESTORE_ADDITIONAL_REGISTERS
+ /* No additional registers to restore, so this macro does nothing. */
+ .endm
+
+#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
diff --git a/portable/GCC/RISC-V/chip_specific_extensions/readme.txt b/portable/GCC/RISC-V/chip_specific_extensions/readme.txt
index 69d98d9..b24c0b9 100644
--- a/portable/GCC/RISC-V/chip_specific_extensions/readme.txt
+++ b/portable/GCC/RISC-V/chip_specific_extensions/readme.txt
@@ -1,23 +1,23 @@
-/*
- * The FreeRTOS kernel's RISC-V port is split between the the code that is
- * common across all currently supported RISC-V chips (implementations of the
- * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
- *
- * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
- * is common to all currently supported RISC-V chips. There is only one
- * portASM.S file because the same file is built for all RISC-V target chips.
- *
- * + Header files called freertos_risc_v_chip_specific_extensions.h contain the
- * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
- * chip. There are multiple freertos_risc_v_chip_specific_extensions.h files
- * as there are multiple RISC-V chip implementations.
- *
- * !!!NOTE!!!
- * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h
- * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the
- * compiler's!) include path. For example, if the chip in use includes a core
- * local interrupter (CLINT) and does not include any chip specific register
- * extensions then add the path below to the assembler's include path:
- * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
- *
- */
+/*
+ * The FreeRTOS kernel's RISC-V port is split between the the code that is
+ * common across all currently supported RISC-V chips (implementations of the
+ * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
+ *
+ * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
+ * is common to all currently supported RISC-V chips. There is only one
+ * portASM.S file because the same file is built for all RISC-V target chips.
+ *
+ * + Header files called freertos_risc_v_chip_specific_extensions.h contain the
+ * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
+ * chip. There are multiple freertos_risc_v_chip_specific_extensions.h files
+ * as there are multiple RISC-V chip implementations.
+ *
+ * !!!NOTE!!!
+ * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h
+ * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the
+ * compiler's!) include path. For example, if the chip in use includes a core
+ * local interrupter (CLINT) and does not include any chip specific register
+ * extensions then add the path below to the assembler's include path:
+ * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
+ *
+ */
diff --git a/portable/GCC/RISC-V/port.c b/portable/GCC/RISC-V/port.c
index 275b3d3..628df83 100644
--- a/portable/GCC/RISC-V/port.c
+++ b/portable/GCC/RISC-V/port.c
@@ -1,203 +1,203 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the RISC-V port.
- *----------------------------------------------------------*/
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-#include "portmacro.h"
-
-/* Standard includes. */
-#include "string.h"
-
-#ifdef configCLINT_BASE_ADDRESS
- #warning The configCLINT_BASE_ADDRESS constant has been deprecated. configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS are currently being derived from the (possibly 0) configCLINT_BASE_ADDRESS setting. Please update to define configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS dirctly in place of configCLINT_BASE_ADDRESS. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
-#endif
-
-#ifndef configMTIME_BASE_ADDRESS
- #warning configMTIME_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtime register then set configMTIME_BASE_ADDRESS to the mapped address. Otherwise set configMTIME_BASE_ADDRESS to 0. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
-#endif
-
-#ifndef configMTIMECMP_BASE_ADDRESS
- #warning configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtimecmp register then set configMTIMECMP_BASE_ADDRESS to the mapped address. Otherwise set configMTIMECMP_BASE_ADDRESS to 0. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
-#endif
-
-/* Let the user override the pre-loading of the initial RA. */
-#ifdef configTASK_RETURN_ADDRESS
- #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
-#else
- #define portTASK_RETURN_ADDRESS 0
-#endif
-
-/* The stack used by interrupt service routines. Set configISR_STACK_SIZE_WORDS
- * to use a statically allocated array as the interrupt stack. Alternative leave
- * configISR_STACK_SIZE_WORDS undefined and update the linker script so that a
- * linker variable names __freertos_irq_stack_top has the same value as the top
- * of the stack used by main. Using the linker script method will repurpose the
- * stack that was used by main before the scheduler was started for use as the
- * interrupt stack after the scheduler has started. */
-#ifdef configISR_STACK_SIZE_WORDS
- static __attribute__ ((aligned(16))) StackType_t xISRStack[ configISR_STACK_SIZE_WORDS ] = { 0 };
- const StackType_t xISRStackTop = ( StackType_t ) &( xISRStack[ configISR_STACK_SIZE_WORDS & ~portBYTE_ALIGNMENT_MASK ] );
-
- /* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for
- the task stacks, and so will legitimately appear in many positions within
- the ISR stack. */
- #define portISR_STACK_FILL_BYTE 0xee
-#else
- extern const uint32_t __freertos_irq_stack_top[];
- const StackType_t xISRStackTop = ( StackType_t ) __freertos_irq_stack_top;
-#endif
-
-/*
- * Setup the timer to generate the tick interrupts. The implementation in this
- * file is weak to allow application writers to change the timer used to
- * generate the tick interrupt.
- */
-void vPortSetupTimerInterrupt( void ) __attribute__(( weak ));
-
-/*-----------------------------------------------------------*/
-
-/* Used to program the machine timer compare register. */
-uint64_t ullNextTime = 0ULL;
-const uint64_t *pullNextTime = &ullNextTime;
-const size_t uxTimerIncrementsForOneTick = ( size_t ) ( ( configCPU_CLOCK_HZ ) / ( configTICK_RATE_HZ ) ); /* Assumes increment won't go over 32-bits. */
-uint32_t const ullMachineTimerCompareRegisterBase = configMTIMECMP_BASE_ADDRESS;
-volatile uint64_t * pullMachineTimerCompareRegister = NULL;
-
-/* Holds the critical nesting value - deliberately non-zero at start up to
- * ensure interrupts are not accidentally enabled before the scheduler starts. */
-size_t xCriticalNesting = ( size_t ) 0xaaaaaaaa;
-size_t *pxCriticalNesting = &xCriticalNesting;
-
-/* Used to catch tasks that attempt to return from their implementing function. */
-size_t xTaskReturnAddress = ( size_t ) portTASK_RETURN_ADDRESS;
-
-/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
- * stack checking. A problem in the ISR stack will trigger an assert, not call
- * the stack overflow hook function (because the stack overflow hook is specific
- * to a task stack, not the ISR stack). */
-#if defined( configISR_STACK_SIZE_WORDS ) && ( configCHECK_FOR_STACK_OVERFLOW > 2 )
- #warning This path not tested, or even compiled yet.
-
- static const uint8_t ucExpectedStackBytes[] = {
- portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
- portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
- portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
- portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
- portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE }; \
-
- #define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
-#else
- /* Define the function away. */
- #define portCHECK_ISR_STACK()
-#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
-
-/*-----------------------------------------------------------*/
-
-#if( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 )
-
- void vPortSetupTimerInterrupt( void )
- {
- uint32_t ulCurrentTimeHigh, ulCurrentTimeLow;
- volatile uint32_t * const pulTimeHigh = ( volatile uint32_t * const ) ( ( configMTIME_BASE_ADDRESS ) + 4UL ); /* 8-byte type so high 32-bit word is 4 bytes up. */
- volatile uint32_t * const pulTimeLow = ( volatile uint32_t * const ) ( configMTIME_BASE_ADDRESS );
- volatile uint32_t ulHartId;
-
- __asm volatile( "csrr %0, mhartid" : "=r"( ulHartId ) );
- pullMachineTimerCompareRegister = ( volatile uint64_t * ) ( ullMachineTimerCompareRegisterBase + ( ulHartId * sizeof( uint64_t ) ) );
-
- do
- {
- ulCurrentTimeHigh = *pulTimeHigh;
- ulCurrentTimeLow = *pulTimeLow;
- } while( ulCurrentTimeHigh != *pulTimeHigh );
-
- ullNextTime = ( uint64_t ) ulCurrentTimeHigh;
- ullNextTime <<= 32ULL; /* High 4-byte word is 32-bits up. */
- ullNextTime |= ( uint64_t ) ulCurrentTimeLow;
- ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick;
- *pullMachineTimerCompareRegister = ullNextTime;
-
- /* Prepare the time to use after the next tick interrupt. */
- ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick;
- }
-
-#endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIME_BASE_ADDRESS != 0 ) */
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-extern void xPortStartFirstTask( void );
-
- #if( configASSERT_DEFINED == 1 )
- {
- /* Check alignment of the interrupt stack - which is the same as the
- * stack that was being used by main() prior to the scheduler being
- * started. */
- configASSERT( ( xISRStackTop & portBYTE_ALIGNMENT_MASK ) == 0 );
-
- #ifdef configISR_STACK_SIZE_WORDS
- {
- memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) );
- }
- #endif /* configISR_STACK_SIZE_WORDS */
- }
- #endif /* configASSERT_DEFINED */
-
- /* If there is a CLINT then it is ok to use the default implementation
- * in this file, otherwise vPortSetupTimerInterrupt() must be implemented to
- * configure whichever clock is to be used to generate the tick interrupt. */
- vPortSetupTimerInterrupt();
-
- #if( ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) )
- {
- /* Enable mtime and external interrupts. 1<<7 for timer interrupt,
- * 1<<11 for external interrupt. _RB_ What happens here when mtime is
- * not present as with pulpino? */
- __asm volatile( "csrs mie, %0" :: "r"(0x880) );
- }
- #endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) */
-
- xPortStartFirstTask();
-
- /* Should not get here as after calling xPortStartFirstTask() only tasks
- * should be executing. */
- return pdFAIL;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
- /* Not implemented. */
- for( ;; );
-}
-/*-----------------------------------------------------------*/
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the RISC-V port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "portmacro.h"
+
+/* Standard includes. */
+#include "string.h"
+
+#ifdef configCLINT_BASE_ADDRESS
+ #warning The configCLINT_BASE_ADDRESS constant has been deprecated. configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS are currently being derived from the (possibly 0) configCLINT_BASE_ADDRESS setting. Please update to define configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS dirctly in place of configCLINT_BASE_ADDRESS. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
+#endif
+
+#ifndef configMTIME_BASE_ADDRESS
+ #warning configMTIME_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtime register then set configMTIME_BASE_ADDRESS to the mapped address. Otherwise set configMTIME_BASE_ADDRESS to 0. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
+#endif
+
+#ifndef configMTIMECMP_BASE_ADDRESS
+ #warning configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtimecmp register then set configMTIMECMP_BASE_ADDRESS to the mapped address. Otherwise set configMTIMECMP_BASE_ADDRESS to 0. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
+#endif
+
+/* Let the user override the pre-loading of the initial RA. */
+#ifdef configTASK_RETURN_ADDRESS
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
+#else
+ #define portTASK_RETURN_ADDRESS 0
+#endif
+
+/* The stack used by interrupt service routines. Set configISR_STACK_SIZE_WORDS
+ * to use a statically allocated array as the interrupt stack. Alternative leave
+ * configISR_STACK_SIZE_WORDS undefined and update the linker script so that a
+ * linker variable names __freertos_irq_stack_top has the same value as the top
+ * of the stack used by main. Using the linker script method will repurpose the
+ * stack that was used by main before the scheduler was started for use as the
+ * interrupt stack after the scheduler has started. */
+#ifdef configISR_STACK_SIZE_WORDS
+ static __attribute__ ((aligned(16))) StackType_t xISRStack[ configISR_STACK_SIZE_WORDS ] = { 0 };
+ const StackType_t xISRStackTop = ( StackType_t ) &( xISRStack[ configISR_STACK_SIZE_WORDS & ~portBYTE_ALIGNMENT_MASK ] );
+
+ /* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for
+ the task stacks, and so will legitimately appear in many positions within
+ the ISR stack. */
+ #define portISR_STACK_FILL_BYTE 0xee
+#else
+ extern const uint32_t __freertos_irq_stack_top[];
+ const StackType_t xISRStackTop = ( StackType_t ) __freertos_irq_stack_top;
+#endif
+
+/*
+ * Setup the timer to generate the tick interrupts. The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void ) __attribute__(( weak ));
+
+/*-----------------------------------------------------------*/
+
+/* Used to program the machine timer compare register. */
+uint64_t ullNextTime = 0ULL;
+const uint64_t *pullNextTime = &ullNextTime;
+const size_t uxTimerIncrementsForOneTick = ( size_t ) ( ( configCPU_CLOCK_HZ ) / ( configTICK_RATE_HZ ) ); /* Assumes increment won't go over 32-bits. */
+uint32_t const ullMachineTimerCompareRegisterBase = configMTIMECMP_BASE_ADDRESS;
+volatile uint64_t * pullMachineTimerCompareRegister = NULL;
+
+/* Holds the critical nesting value - deliberately non-zero at start up to
+ * ensure interrupts are not accidentally enabled before the scheduler starts. */
+size_t xCriticalNesting = ( size_t ) 0xaaaaaaaa;
+size_t *pxCriticalNesting = &xCriticalNesting;
+
+/* Used to catch tasks that attempt to return from their implementing function. */
+size_t xTaskReturnAddress = ( size_t ) portTASK_RETURN_ADDRESS;
+
+/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
+ * stack checking. A problem in the ISR stack will trigger an assert, not call
+ * the stack overflow hook function (because the stack overflow hook is specific
+ * to a task stack, not the ISR stack). */
+#if defined( configISR_STACK_SIZE_WORDS ) && ( configCHECK_FOR_STACK_OVERFLOW > 2 )
+ #warning This path not tested, or even compiled yet.
+
+ static const uint8_t ucExpectedStackBytes[] = {
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE }; \
+
+ #define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
+#else
+ /* Define the function away. */
+ #define portCHECK_ISR_STACK()
+#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
+
+/*-----------------------------------------------------------*/
+
+#if( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 )
+
+ void vPortSetupTimerInterrupt( void )
+ {
+ uint32_t ulCurrentTimeHigh, ulCurrentTimeLow;
+ volatile uint32_t * const pulTimeHigh = ( volatile uint32_t * const ) ( ( configMTIME_BASE_ADDRESS ) + 4UL ); /* 8-byte type so high 32-bit word is 4 bytes up. */
+ volatile uint32_t * const pulTimeLow = ( volatile uint32_t * const ) ( configMTIME_BASE_ADDRESS );
+ volatile uint32_t ulHartId;
+
+ __asm volatile( "csrr %0, mhartid" : "=r"( ulHartId ) );
+ pullMachineTimerCompareRegister = ( volatile uint64_t * ) ( ullMachineTimerCompareRegisterBase + ( ulHartId * sizeof( uint64_t ) ) );
+
+ do
+ {
+ ulCurrentTimeHigh = *pulTimeHigh;
+ ulCurrentTimeLow = *pulTimeLow;
+ } while( ulCurrentTimeHigh != *pulTimeHigh );
+
+ ullNextTime = ( uint64_t ) ulCurrentTimeHigh;
+ ullNextTime <<= 32ULL; /* High 4-byte word is 32-bits up. */
+ ullNextTime |= ( uint64_t ) ulCurrentTimeLow;
+ ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick;
+ *pullMachineTimerCompareRegister = ullNextTime;
+
+ /* Prepare the time to use after the next tick interrupt. */
+ ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick;
+ }
+
+#endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIME_BASE_ADDRESS != 0 ) */
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void xPortStartFirstTask( void );
+
+ #if( configASSERT_DEFINED == 1 )
+ {
+ /* Check alignment of the interrupt stack - which is the same as the
+ * stack that was being used by main() prior to the scheduler being
+ * started. */
+ configASSERT( ( xISRStackTop & portBYTE_ALIGNMENT_MASK ) == 0 );
+
+ #ifdef configISR_STACK_SIZE_WORDS
+ {
+ memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) );
+ }
+ #endif /* configISR_STACK_SIZE_WORDS */
+ }
+ #endif /* configASSERT_DEFINED */
+
+ /* If there is a CLINT then it is ok to use the default implementation
+ * in this file, otherwise vPortSetupTimerInterrupt() must be implemented to
+ * configure whichever clock is to be used to generate the tick interrupt. */
+ vPortSetupTimerInterrupt();
+
+ #if( ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) )
+ {
+ /* Enable mtime and external interrupts. 1<<7 for timer interrupt,
+ * 1<<11 for external interrupt. _RB_ What happens here when mtime is
+ * not present as with pulpino? */
+ __asm volatile( "csrs mie, %0" :: "r"(0x880) );
+ }
+ #endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) */
+
+ xPortStartFirstTask();
+
+ /* Should not get here as after calling xPortStartFirstTask() only tasks
+ * should be executing. */
+ return pdFAIL;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+ /* Not implemented. */
+ for( ;; );
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/RISC-V/portmacro.h b/portable/GCC/RISC-V/portmacro.h
index 76b7c92..1e72b1a 100644
--- a/portable/GCC/RISC-V/portmacro.h
+++ b/portable/GCC/RISC-V/portmacro.h
@@ -1,191 +1,191 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#if __riscv_xlen == 64
- #define portSTACK_TYPE uint64_t
- #define portBASE_TYPE int64_t
- #define portUBASE_TYPE uint64_t
- #define portMAX_DELAY ( TickType_t ) 0xffffffffffffffffUL
- #define portPOINTER_SIZE_TYPE uint64_t
-#elif __riscv_xlen == 32
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE int32_t
- #define portUBASE_TYPE uint32_t
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#else
- #error Assembler did not define __riscv_xlen
-#endif
-
-typedef portSTACK_TYPE StackType_t;
-typedef portBASE_TYPE BaseType_t;
-typedef portUBASE_TYPE UBaseType_t;
-typedef portUBASE_TYPE TickType_t;
-
-/* Legacy type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT short
-
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
-#define portTICK_TYPE_IS_ATOMIC 1
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH ( -1 )
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#ifdef __riscv_32e
- #define portBYTE_ALIGNMENT 8 /* RV32E uses RISC-V EABI with reduced stack alignment requirements */
-#else
- #define portBYTE_ALIGNMENT 16
-#endif
-/*-----------------------------------------------------------*/
-
-/* Scheduler utilities. */
-extern void vTaskSwitchContext( void );
-#define portYIELD() __asm volatile( "ecall" );
-#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) vTaskSwitchContext(); } while( 0 )
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/* Critical section management. */
-#define portCRITICAL_NESTING_IN_TCB 0
-
-#define portSET_INTERRUPT_MASK_FROM_ISR() 0
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue
-
-#define portDISABLE_INTERRUPTS() __asm volatile( "csrc mstatus, 8" )
-#define portENABLE_INTERRUPTS() __asm volatile( "csrs mstatus, 8" )
-
-extern size_t xCriticalNesting;
-#define portENTER_CRITICAL() \
-{ \
- portDISABLE_INTERRUPTS(); \
- xCriticalNesting++; \
-}
-
-#define portEXIT_CRITICAL() \
-{ \
- xCriticalNesting--; \
- if( xCriticalNesting == 0 ) \
- { \
- portENABLE_INTERRUPTS(); \
- } \
-}
-
-/*-----------------------------------------------------------*/
-
-/* Architecture specific optimisations. */
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-#endif
-
-#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
-
- /* Check the configuration. */
- #if( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
-
- /* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
- /*-----------------------------------------------------------*/
-
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - __builtin_clz( uxReadyPriorities ) )
-
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. These are
- * not necessary for to use this port. They are defined so the common demo
- * files (which build with all the ports) will build. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-/*-----------------------------------------------------------*/
-
-#define portNOP() __asm volatile( " nop " )
-#define portINLINE __inline
-
-#ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__(( always_inline))
-#endif
-
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
-/*-----------------------------------------------------------*/
-
-/* configCLINT_BASE_ADDRESS is a legacy definition that was replaced by the
- * configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS definitions. For
- * backward compatibility derive the newer definitions from the old if the old
- * definition is found. */
-#if defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS ) && ( configCLINT_BASE_ADDRESS == 0 )
- /* Legacy case where configCLINT_BASE_ADDRESS was defined as 0 to indicate
- * there was no CLINT. Equivalent now is to set the MTIME and MTIMECMP
- * addresses to 0. */
- #define configMTIME_BASE_ADDRESS ( 0 )
- #define configMTIMECMP_BASE_ADDRESS ( 0 )
-#elif defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS )
- /* Legacy case where configCLINT_BASE_ADDRESS was set to the base address of
- * the CLINT. Equivalent now is to derive the MTIME and MTIMECMP addresses
- * from the CLINT address. */
- #define configMTIME_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0xBFF8UL )
- #define configMTIMECMP_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0x4000UL )
-#elif !defined( configMTIME_BASE_ADDRESS ) || !defined( configMTIMECMP_BASE_ADDRESS )
- #error configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. Set them to zero if there is no MTIME (machine time) clock. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#if __riscv_xlen == 64
+ #define portSTACK_TYPE uint64_t
+ #define portBASE_TYPE int64_t
+ #define portUBASE_TYPE uint64_t
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffffffffffUL
+ #define portPOINTER_SIZE_TYPE uint64_t
+#elif __riscv_xlen == 32
+ #define portSTACK_TYPE uint32_t
+ #define portBASE_TYPE int32_t
+ #define portUBASE_TYPE uint32_t
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#else
+ #error Assembler did not define __riscv_xlen
+#endif
+
+typedef portSTACK_TYPE StackType_t;
+typedef portBASE_TYPE BaseType_t;
+typedef portUBASE_TYPE UBaseType_t;
+typedef portUBASE_TYPE TickType_t;
+
+/* Legacy type definitions. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+#define portTICK_TYPE_IS_ATOMIC 1
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#ifdef __riscv_32e
+ #define portBYTE_ALIGNMENT 8 /* RV32E uses RISC-V EABI with reduced stack alignment requirements */
+#else
+ #define portBYTE_ALIGNMENT 16
+#endif
+/*-----------------------------------------------------------*/
+
+/* Scheduler utilities. */
+extern void vTaskSwitchContext( void );
+#define portYIELD() __asm volatile( "ecall" );
+#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) vTaskSwitchContext(); } while( 0 )
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+#define portCRITICAL_NESTING_IN_TCB 0
+
+#define portSET_INTERRUPT_MASK_FROM_ISR() 0
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue
+
+#define portDISABLE_INTERRUPTS() __asm volatile( "csrc mstatus, 8" )
+#define portENABLE_INTERRUPTS() __asm volatile( "csrs mstatus, 8" )
+
+extern size_t xCriticalNesting;
+#define portENTER_CRITICAL() \
+{ \
+ portDISABLE_INTERRUPTS(); \
+ xCriticalNesting++; \
+}
+
+#define portEXIT_CRITICAL() \
+{ \
+ xCriticalNesting--; \
+ if( xCriticalNesting == 0 ) \
+ { \
+ portENABLE_INTERRUPTS(); \
+ } \
+}
+
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+ /* Check the configuration. */
+ #if( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
+
+ /* Store/clear the ready priorities in a bit map. */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+ /*-----------------------------------------------------------*/
+
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - __builtin_clz( uxReadyPriorities ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. These are
+ * not necessary for to use this port. They are defined so the common demo
+ * files (which build with all the ports) will build. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+/*-----------------------------------------------------------*/
+
+#define portNOP() __asm volatile( " nop " )
+#define portINLINE __inline
+
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__(( always_inline))
+#endif
+
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+/* configCLINT_BASE_ADDRESS is a legacy definition that was replaced by the
+ * configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS definitions. For
+ * backward compatibility derive the newer definitions from the old if the old
+ * definition is found. */
+#if defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS ) && ( configCLINT_BASE_ADDRESS == 0 )
+ /* Legacy case where configCLINT_BASE_ADDRESS was defined as 0 to indicate
+ * there was no CLINT. Equivalent now is to set the MTIME and MTIMECMP
+ * addresses to 0. */
+ #define configMTIME_BASE_ADDRESS ( 0 )
+ #define configMTIMECMP_BASE_ADDRESS ( 0 )
+#elif defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS )
+ /* Legacy case where configCLINT_BASE_ADDRESS was set to the base address of
+ * the CLINT. Equivalent now is to derive the MTIME and MTIMECMP addresses
+ * from the CLINT address. */
+ #define configMTIME_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0xBFF8UL )
+ #define configMTIMECMP_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0x4000UL )
+#elif !defined( configMTIME_BASE_ADDRESS ) || !defined( configMTIMECMP_BASE_ADDRESS )
+ #error configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. Set them to zero if there is no MTIME (machine time) clock. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/portable/GCC/RISC-V/readme.txt b/portable/GCC/RISC-V/readme.txt
index 69d98d9..b24c0b9 100644
--- a/portable/GCC/RISC-V/readme.txt
+++ b/portable/GCC/RISC-V/readme.txt
@@ -1,23 +1,23 @@
-/*
- * The FreeRTOS kernel's RISC-V port is split between the the code that is
- * common across all currently supported RISC-V chips (implementations of the
- * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
- *
- * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
- * is common to all currently supported RISC-V chips. There is only one
- * portASM.S file because the same file is built for all RISC-V target chips.
- *
- * + Header files called freertos_risc_v_chip_specific_extensions.h contain the
- * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
- * chip. There are multiple freertos_risc_v_chip_specific_extensions.h files
- * as there are multiple RISC-V chip implementations.
- *
- * !!!NOTE!!!
- * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h
- * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the
- * compiler's!) include path. For example, if the chip in use includes a core
- * local interrupter (CLINT) and does not include any chip specific register
- * extensions then add the path below to the assembler's include path:
- * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
- *
- */
+/*
+ * The FreeRTOS kernel's RISC-V port is split between the the code that is
+ * common across all currently supported RISC-V chips (implementations of the
+ * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
+ *
+ * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
+ * is common to all currently supported RISC-V chips. There is only one
+ * portASM.S file because the same file is built for all RISC-V target chips.
+ *
+ * + Header files called freertos_risc_v_chip_specific_extensions.h contain the
+ * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
+ * chip. There are multiple freertos_risc_v_chip_specific_extensions.h files
+ * as there are multiple RISC-V chip implementations.
+ *
+ * !!!NOTE!!!
+ * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h
+ * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the
+ * compiler's!) include path. For example, if the chip in use includes a core
+ * local interrupter (CLINT) and does not include any chip specific register
+ * extensions then add the path below to the assembler's include path:
+ * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
+ *
+ */
diff --git a/portable/GCC/RL78/isr_support.h b/portable/GCC/RL78/isr_support.h
index e02ca27..348af1d 100644
--- a/portable/GCC/RL78/isr_support.h
+++ b/portable/GCC/RL78/isr_support.h
@@ -1,127 +1,126 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/* Variables used by scheduler */
- .extern _pxCurrentTCB
- .extern _usCriticalNesting
-
-/*
- * portSAVE_CONTEXT MACRO
- * Saves the context of the general purpose registers, CS and ES (only in far
- * memory mode) registers the usCriticalNesting Value and the Stack Pointer
- * of the active Task onto the task stack
- */
- .macro portSAVE_CONTEXT
-
- SEL RB0
-
- /* Save AX Register to stack. */
- PUSH AX
- PUSH HL
- /* Save CS register. */
- MOV A, CS
- XCH A, X
- /* Save ES register. */
- MOV A, ES
- PUSH AX
- /* Save the remaining general purpose registers from bank 0. */
- PUSH DE
- PUSH BC
- /* Save the other register banks - only necessary in the GCC port. */
- SEL RB1
- PUSH AX
- PUSH BC
- PUSH DE
- PUSH HL
- SEL RB2
- PUSH AX
- PUSH BC
- PUSH DE
- PUSH HL
- /* Registers in bank 3 are for ISR use only so don't need saving. */
- SEL RB0
- /* Save the usCriticalNesting value. */
- MOVW AX, !_usCriticalNesting
- PUSH AX
- /* Save the Stack pointer. */
- MOVW AX, !_pxCurrentTCB
- MOVW HL, AX
- MOVW AX, SP
- MOVW [HL], AX
- /* Switch stack pointers. */
- movw sp,#_stack /* Set stack pointer */
-
- .endm
-
-
-/*
- * portRESTORE_CONTEXT MACRO
- * Restores the task Stack Pointer then use this to restore usCriticalNesting,
- * general purpose registers and the CS and ES (only in far memory mode)
- * of the selected task from the task stack
- */
-.macro portRESTORE_CONTEXT MACRO
- SEL RB0
- /* Restore the Stack pointer. */
- MOVW AX, !_pxCurrentTCB
- MOVW HL, AX
- MOVW AX, [HL]
- MOVW SP, AX
- /* Restore usCriticalNesting value. */
- POP AX
- MOVW !_usCriticalNesting, AX
- /* Restore the alternative register banks - only necessary in the GCC
- port. Register bank 3 is dedicated for interrupts use so is not saved or
- restored. */
- SEL RB2
- POP HL
- POP DE
- POP BC
- POP AX
- SEL RB1
- POP HL
- POP DE
- POP BC
- POP AX
- SEL RB0
- /* Restore the necessary general purpose registers. */
- POP BC
- POP DE
- /* Restore the ES register. */
- POP AX
- MOV ES, A
- /* Restore the CS register. */
- XCH A, X
- MOV CS, A
- /* Restore general purpose register HL. */
- POP HL
- /* Restore AX. */
- POP AX
-
- .endm
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Variables used by scheduler */
+ .extern _pxCurrentTCB
+ .extern _usCriticalNesting
+
+/*
+ * portSAVE_CONTEXT MACRO
+ * Saves the context of the general purpose registers, CS and ES (only in far
+ * memory mode) registers the usCriticalNesting Value and the Stack Pointer
+ * of the active Task onto the task stack
+ */
+ .macro portSAVE_CONTEXT
+
+ SEL RB0
+
+ /* Save AX Register to stack. */
+ PUSH AX
+ PUSH HL
+ /* Save CS register. */
+ MOV A, CS
+ XCH A, X
+ /* Save ES register. */
+ MOV A, ES
+ PUSH AX
+ /* Save the remaining general purpose registers from bank 0. */
+ PUSH DE
+ PUSH BC
+ /* Save the other register banks - only necessary in the GCC port. */
+ SEL RB1
+ PUSH AX
+ PUSH BC
+ PUSH DE
+ PUSH HL
+ SEL RB2
+ PUSH AX
+ PUSH BC
+ PUSH DE
+ PUSH HL
+ /* Registers in bank 3 are for ISR use only so don't need saving. */
+ SEL RB0
+ /* Save the usCriticalNesting value. */
+ MOVW AX, !_usCriticalNesting
+ PUSH AX
+ /* Save the Stack pointer. */
+ MOVW AX, !_pxCurrentTCB
+ MOVW HL, AX
+ MOVW AX, SP
+ MOVW [HL], AX
+ /* Switch stack pointers. */
+ movw sp,#_stack /* Set stack pointer */
+
+ .endm
+
+
+/*
+ * portRESTORE_CONTEXT MACRO
+ * Restores the task Stack Pointer then use this to restore usCriticalNesting,
+ * general purpose registers and the CS and ES (only in far memory mode)
+ * of the selected task from the task stack
+ */
+.macro portRESTORE_CONTEXT MACRO
+ SEL RB0
+ /* Restore the Stack pointer. */
+ MOVW AX, !_pxCurrentTCB
+ MOVW HL, AX
+ MOVW AX, [HL]
+ MOVW SP, AX
+ /* Restore usCriticalNesting value. */
+ POP AX
+ MOVW !_usCriticalNesting, AX
+ /* Restore the alternative register banks - only necessary in the GCC
+ port. Register bank 3 is dedicated for interrupts use so is not saved or
+ restored. */
+ SEL RB2
+ POP HL
+ POP DE
+ POP BC
+ POP AX
+ SEL RB1
+ POP HL
+ POP DE
+ POP BC
+ POP AX
+ SEL RB0
+ /* Restore the necessary general purpose registers. */
+ POP BC
+ POP DE
+ /* Restore the ES register. */
+ POP AX
+ MOV ES, A
+ /* Restore the CS register. */
+ XCH A, X
+ MOV CS, A
+ /* Restore general purpose register HL. */
+ POP HL
+ /* Restore AX. */
+ POP AX
+
+ .endm
diff --git a/portable/GCC/RL78/port.c b/portable/GCC/RL78/port.c
index 1007525..35ff7df 100644
--- a/portable/GCC/RL78/port.c
+++ b/portable/GCC/RL78/port.c
@@ -1,212 +1,211 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* The critical nesting value is initialised to a non zero value to ensure
-interrupts don't accidentally become enabled before the scheduler is started. */
-#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 )
-
-/* Initial PSW value allocated to a newly created task.
- * 11000110
- * ||||||||-------------- Fill byte
- * |||||||--------------- Carry Flag cleared
- * |||||----------------- In-service priority Flags set to low level
- * ||||------------------ Register bank Select 0 Flag cleared
- * |||------------------- Auxiliary Carry Flag cleared
- * ||-------------------- Register bank Select 1 Flag cleared
- * |--------------------- Zero Flag set
- * ---------------------- Global Interrupt Flag set (enabled)
- */
-#define portPSW ( 0xc6UL )
-
-/* Each task maintains a count of the critical section nesting depth. Each time
-a critical section is entered the count is incremented. Each time a critical
-section is exited the count is decremented - with interrupts only being
-re-enabled if the count is zero.
-
-usCriticalNesting will get set to zero when the scheduler starts, but must
-not be initialised to zero as that could cause problems during the startup
-sequence. */
-volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
-
-/*-----------------------------------------------------------*/
-
-/*
- * Sets up the periodic ISR used for the RTOS tick.
- */
-__attribute__((weak)) void vApplicationSetupTimerInterrupt( void );
-
-/*
- * Starts the scheduler by loading the context of the first task to run.
- * (defined in portasm.S).
- */
-extern void vPortStartFirstTask( void );
-
-/*-----------------------------------------------------------*/
-
-/*
- * Initialise the stack of a task to look exactly as if a call to
- * portSAVE_CONTEXT had been called.
- *
- * See the header file portable.h.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-uint32_t *pulLocal;
-
- /* Stack type and pointers to the stack type are both 2 bytes. */
-
- /* Parameters are passed in on the stack, and written using a 32bit value
- hence a space is left for the second two bytes. */
- pxTopOfStack--;
-
- /* Write in the parameter value. */
- pulLocal = ( uint32_t * ) pxTopOfStack;
- *pulLocal = ( StackType_t ) pvParameters;
- pxTopOfStack--;
-
- /* The return address, leaving space for the first two bytes of the
- 32-bit value. */
- pxTopOfStack--;
- pulLocal = ( uint32_t * ) pxTopOfStack;
- *pulLocal = ( uint32_t ) 0;
- pxTopOfStack--;
-
- /* The start address / PSW value is also written in as a 32bit value,
- so leave a space for the second two bytes. */
- pxTopOfStack--;
-
- /* Task function start address combined with the PSW. */
- pulLocal = ( uint32_t * ) pxTopOfStack;
- *pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) );
- pxTopOfStack--;
-
- /* An initial value for the AX register. */
- *pxTopOfStack = ( StackType_t ) 0x1111;
- pxTopOfStack--;
-
- /* An initial value for the HL register. */
- *pxTopOfStack = ( StackType_t ) 0x2222;
- pxTopOfStack--;
-
- /* CS and ES registers. */
- *pxTopOfStack = ( StackType_t ) 0x0F00;
- pxTopOfStack--;
-
- /* The remaining general purpose registers bank 0 (DE and BC) and the other
- two register banks...register bank 3 is dedicated for use by interrupts so
- is not saved as part of the task context. */
- pxTopOfStack -= 10;
-
- /* Finally the critical section nesting count is set to zero when the task
- first starts. */
- *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
-
- /* Return a pointer to the top of the stack that has beene generated so it
- can be stored in the task control block for the task. */
- return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-portBASE_TYPE xPortStartScheduler( void )
-{
- /* Setup the hardware to generate the tick. Interrupts are disabled when
- this function is called. */
- vApplicationSetupTimerInterrupt();
-
- /* Restore the context of the first task that is going to run. */
- vPortStartFirstTask();
-
- /* Execution should not reach here as the tasks are now running! */
- return pdTRUE;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
- /* It is unlikely that the RL78 port will get stopped. */
-}
-/*-----------------------------------------------------------*/
-
-__attribute__((weak)) void vApplicationSetupTimerInterrupt( void )
-{
-const uint16_t usClockHz = 15000UL; /* Internal clock. */
-const uint16_t usCompareMatch = ( usClockHz / configTICK_RATE_HZ ) + 1UL;
-
- /* Use the internal 15K clock. */
- OSMC = ( unsigned char ) 0x16;
-
- #ifdef RTCEN
- {
- /* Supply the interval timer clock. */
- RTCEN = ( unsigned char ) 1U;
-
- /* Disable INTIT interrupt. */
- ITMK = ( unsigned char ) 1;
-
- /* Disable ITMC operation. */
- ITMC = ( unsigned char ) 0x0000;
-
- /* Clear INIT interrupt. */
- ITIF = ( unsigned char ) 0;
-
- /* Set interval and enable interrupt operation. */
- ITMC = usCompareMatch | 0x8000U;
-
- /* Enable INTIT interrupt. */
- ITMK = ( unsigned char ) 0;
- }
- #endif
-
- #ifdef TMKAEN
- {
- /* Supply the interval timer clock. */
- TMKAEN = ( unsigned char ) 1U;
-
- /* Disable INTIT interrupt. */
- TMKAMK = ( unsigned char ) 1;
-
- /* Disable ITMC operation. */
- ITMC = ( unsigned char ) 0x0000;
-
- /* Clear INIT interrupt. */
- TMKAIF = ( unsigned char ) 0;
-
- /* Set interval and enable interrupt operation. */
- ITMC = usCompareMatch | 0x8000U;
-
- /* Enable INTIT interrupt. */
- TMKAMK = ( unsigned char ) 0;
- }
- #endif
-}
-/*-----------------------------------------------------------*/
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* The critical nesting value is initialised to a non zero value to ensure
+interrupts don't accidentally become enabled before the scheduler is started. */
+#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 )
+
+/* Initial PSW value allocated to a newly created task.
+ * 11000110
+ * ||||||||-------------- Fill byte
+ * |||||||--------------- Carry Flag cleared
+ * |||||----------------- In-service priority Flags set to low level
+ * ||||------------------ Register bank Select 0 Flag cleared
+ * |||------------------- Auxiliary Carry Flag cleared
+ * ||-------------------- Register bank Select 1 Flag cleared
+ * |--------------------- Zero Flag set
+ * ---------------------- Global Interrupt Flag set (enabled)
+ */
+#define portPSW ( 0xc6UL )
+
+/* Each task maintains a count of the critical section nesting depth. Each time
+a critical section is entered the count is incremented. Each time a critical
+section is exited the count is decremented - with interrupts only being
+re-enabled if the count is zero.
+
+usCriticalNesting will get set to zero when the scheduler starts, but must
+not be initialised to zero as that could cause problems during the startup
+sequence. */
+volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Sets up the periodic ISR used for the RTOS tick.
+ */
+__attribute__((weak)) void vApplicationSetupTimerInterrupt( void );
+
+/*
+ * Starts the scheduler by loading the context of the first task to run.
+ * (defined in portasm.S).
+ */
+extern void vPortStartFirstTask( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been called.
+ *
+ * See the header file portable.h.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+uint32_t *pulLocal;
+
+ /* Stack type and pointers to the stack type are both 2 bytes. */
+
+ /* Parameters are passed in on the stack, and written using a 32bit value
+ hence a space is left for the second two bytes. */
+ pxTopOfStack--;
+
+ /* Write in the parameter value. */
+ pulLocal = ( uint32_t * ) pxTopOfStack;
+ *pulLocal = ( StackType_t ) pvParameters;
+ pxTopOfStack--;
+
+ /* The return address, leaving space for the first two bytes of the
+ 32-bit value. */
+ pxTopOfStack--;
+ pulLocal = ( uint32_t * ) pxTopOfStack;
+ *pulLocal = ( uint32_t ) 0;
+ pxTopOfStack--;
+
+ /* The start address / PSW value is also written in as a 32bit value,
+ so leave a space for the second two bytes. */
+ pxTopOfStack--;
+
+ /* Task function start address combined with the PSW. */
+ pulLocal = ( uint32_t * ) pxTopOfStack;
+ *pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) );
+ pxTopOfStack--;
+
+ /* An initial value for the AX register. */
+ *pxTopOfStack = ( StackType_t ) 0x1111;
+ pxTopOfStack--;
+
+ /* An initial value for the HL register. */
+ *pxTopOfStack = ( StackType_t ) 0x2222;
+ pxTopOfStack--;
+
+ /* CS and ES registers. */
+ *pxTopOfStack = ( StackType_t ) 0x0F00;
+ pxTopOfStack--;
+
+ /* The remaining general purpose registers bank 0 (DE and BC) and the other
+ two register banks...register bank 3 is dedicated for use by interrupts so
+ is not saved as part of the task context. */
+ pxTopOfStack -= 10;
+
+ /* Finally the critical section nesting count is set to zero when the task
+ first starts. */
+ *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
+
+ /* Return a pointer to the top of the stack that has beene generated so it
+ can be stored in the task control block for the task. */
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+portBASE_TYPE xPortStartScheduler( void )
+{
+ /* Setup the hardware to generate the tick. Interrupts are disabled when
+ this function is called. */
+ vApplicationSetupTimerInterrupt();
+
+ /* Restore the context of the first task that is going to run. */
+ vPortStartFirstTask();
+
+ /* Execution should not reach here as the tasks are now running! */
+ return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+ /* It is unlikely that the RL78 port will get stopped. */
+}
+/*-----------------------------------------------------------*/
+
+__attribute__((weak)) void vApplicationSetupTimerInterrupt( void )
+{
+const uint16_t usClockHz = 15000UL; /* Internal clock. */
+const uint16_t usCompareMatch = ( usClockHz / configTICK_RATE_HZ ) + 1UL;
+
+ /* Use the internal 15K clock. */
+ OSMC = ( unsigned char ) 0x16;
+
+ #ifdef RTCEN
+ {
+ /* Supply the interval timer clock. */
+ RTCEN = ( unsigned char ) 1U;
+
+ /* Disable INTIT interrupt. */
+ ITMK = ( unsigned char ) 1;
+
+ /* Disable ITMC operation. */
+ ITMC = ( unsigned char ) 0x0000;
+
+ /* Clear INIT interrupt. */
+ ITIF = ( unsigned char ) 0;
+
+ /* Set interval and enable interrupt operation. */
+ ITMC = usCompareMatch | 0x8000U;
+
+ /* Enable INTIT interrupt. */
+ ITMK = ( unsigned char ) 0;
+ }
+ #endif
+
+ #ifdef TMKAEN
+ {
+ /* Supply the interval timer clock. */
+ TMKAEN = ( unsigned char ) 1U;
+
+ /* Disable INTIT interrupt. */
+ TMKAMK = ( unsigned char ) 1;
+
+ /* Disable ITMC operation. */
+ ITMC = ( unsigned char ) 0x0000;
+
+ /* Clear INIT interrupt. */
+ TMKAIF = ( unsigned char ) 0;
+
+ /* Set interval and enable interrupt operation. */
+ ITMC = usCompareMatch | 0x8000U;
+
+ /* Enable INTIT interrupt. */
+ TMKAMK = ( unsigned char ) 0;
+ }
+ #endif
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/RL78/portasm.S b/portable/GCC/RL78/portasm.S
index a2bc960..18ac665 100644
--- a/portable/GCC/RL78/portasm.S
+++ b/portable/GCC/RL78/portasm.S
@@ -1,81 +1,80 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#include "FreeRTOSConfig.h"
-#include "ISR_Support.h"
-
- .global _vPortYield
- .global _vPortStartFirstTask
- .global _vPortTickISR
-
- .extern _vTaskSwitchContext
- .extern _xTaskIncrementTick
-
- .text
- .align 2
-
-/* FreeRTOS yield handler. This is installed as the BRK software interrupt
-handler. */
-_vPortYield:
- /* Save the context of the current task. */
- portSAVE_CONTEXT
- /* Call the scheduler to select the next task. */
- call !!_vTaskSwitchContext
- /* Restore the context of the next task to run. */
- portRESTORE_CONTEXT
- retb
-
-
-/* Starts the scheduler by restoring the context of the task that will execute
-first. */
- .align 2
-_vPortStartFirstTask:
- /* Restore the context of whichever task will execute first. */
- portRESTORE_CONTEXT
- /* An interrupt stack frame is used so the task is started using RETI. */
- reti
-
-/* FreeRTOS tick handler. This is installed as the interval timer interrupt
-handler. */
- .align 2
-_vPortTickISR:
-
- /* Save the context of the currently executing task. */
- portSAVE_CONTEXT
- /* Call the RTOS tick function. */
- call !!_xTaskIncrementTick
-#if configUSE_PREEMPTION == 1
- /* Select the next task to run. */
- call !!_vTaskSwitchContext
-#endif
- /* Retore the context of whichever task will run next. */
- portRESTORE_CONTEXT
- reti
-
- .end
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#include "FreeRTOSConfig.h"
+#include "ISR_Support.h"
+
+ .global _vPortYield
+ .global _vPortStartFirstTask
+ .global _vPortTickISR
+
+ .extern _vTaskSwitchContext
+ .extern _xTaskIncrementTick
+
+ .text
+ .align 2
+
+/* FreeRTOS yield handler. This is installed as the BRK software interrupt
+handler. */
+_vPortYield:
+ /* Save the context of the current task. */
+ portSAVE_CONTEXT
+ /* Call the scheduler to select the next task. */
+ call !!_vTaskSwitchContext
+ /* Restore the context of the next task to run. */
+ portRESTORE_CONTEXT
+ retb
+
+
+/* Starts the scheduler by restoring the context of the task that will execute
+first. */
+ .align 2
+_vPortStartFirstTask:
+ /* Restore the context of whichever task will execute first. */
+ portRESTORE_CONTEXT
+ /* An interrupt stack frame is used so the task is started using RETI. */
+ reti
+
+/* FreeRTOS tick handler. This is installed as the interval timer interrupt
+handler. */
+ .align 2
+_vPortTickISR:
+
+ /* Save the context of the currently executing task. */
+ portSAVE_CONTEXT
+ /* Call the RTOS tick function. */
+ call !!_xTaskIncrementTick
+#if configUSE_PREEMPTION == 1
+ /* Select the next task to run. */
+ call !!_vTaskSwitchContext
+#endif
+ /* Retore the context of whichever task will run next. */
+ portRESTORE_CONTEXT
+ reti
+
+ .end
diff --git a/portable/GCC/RL78/portmacro.h b/portable/GCC/RL78/portmacro.h
index d7d9dec..4b3cc49 100644
--- a/portable/GCC/RL78/portmacro.h
+++ b/portable/GCC/RL78/portmacro.h
@@ -1,122 +1,121 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT short
-#define portSTACK_TYPE uint16_t
-#define portBASE_TYPE short
-#define portPOINTER_SIZE_TYPE uint16_t
-
-typedef portSTACK_TYPE StackType_t;
-typedef short BaseType_t;
-typedef unsigned short UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
-#else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Interrupt control macros. */
-#define portDISABLE_INTERRUPTS() __asm volatile ( "DI" )
-#define portENABLE_INTERRUPTS() __asm volatile ( "EI" )
-/*-----------------------------------------------------------*/
-
-/* Critical section control macros. */
-#define portNO_CRITICAL_SECTION_NESTING ( ( unsigned short ) 0 )
-
-#define portENTER_CRITICAL() \
-{ \
-extern volatile uint16_t usCriticalNesting; \
- \
- portDISABLE_INTERRUPTS(); \
- \
- /* Now interrupts are disabled ulCriticalNesting can be accessed */ \
- /* directly. Increment ulCriticalNesting to keep a count of how many */ \
- /* times portENTER_CRITICAL() has been called. */ \
- usCriticalNesting++; \
-}
-
-#define portEXIT_CRITICAL() \
-{ \
-extern volatile uint16_t usCriticalNesting; \
- \
- if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \
- { \
- /* Decrement the nesting count as we are leaving a critical section. */ \
- usCriticalNesting--; \
- \
- /* If the nesting level has reached zero then interrupts should be */ \
- /* re-enabled. */ \
- if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \
- { \
- portENABLE_INTERRUPTS(); \
- } \
- } \
-}
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-#define portYIELD() __asm volatile ( "BRK" )
-#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) do { if( xHigherPriorityTaskWoken ) vTaskSwitchContext(); } while( 0 )
-#define portNOP() __asm volatile ( "NOP" )
-/*-----------------------------------------------------------*/
-
-/* Hardwware specifics. */
-#define portBYTE_ALIGNMENT 2
-#define portSTACK_GROWTH ( -1 )
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#endif /* PORTMACRO_H */
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint16_t
+#define portBASE_TYPE short
+#define portPOINTER_SIZE_TYPE uint16_t
+
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Interrupt control macros. */
+#define portDISABLE_INTERRUPTS() __asm volatile ( "DI" )
+#define portENABLE_INTERRUPTS() __asm volatile ( "EI" )
+/*-----------------------------------------------------------*/
+
+/* Critical section control macros. */
+#define portNO_CRITICAL_SECTION_NESTING ( ( unsigned short ) 0 )
+
+#define portENTER_CRITICAL() \
+{ \
+extern volatile uint16_t usCriticalNesting; \
+ \
+ portDISABLE_INTERRUPTS(); \
+ \
+ /* Now interrupts are disabled ulCriticalNesting can be accessed */ \
+ /* directly. Increment ulCriticalNesting to keep a count of how many */ \
+ /* times portENTER_CRITICAL() has been called. */ \
+ usCriticalNesting++; \
+}
+
+#define portEXIT_CRITICAL() \
+{ \
+extern volatile uint16_t usCriticalNesting; \
+ \
+ if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \
+ { \
+ /* Decrement the nesting count as we are leaving a critical section. */ \
+ usCriticalNesting--; \
+ \
+ /* If the nesting level has reached zero then interrupts should be */ \
+ /* re-enabled. */ \
+ if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \
+ { \
+ portENABLE_INTERRUPTS(); \
+ } \
+ } \
+}
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+#define portYIELD() __asm volatile ( "BRK" )
+#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) do { if( xHigherPriorityTaskWoken ) vTaskSwitchContext(); } while( 0 )
+#define portNOP() __asm volatile ( "NOP" )
+/*-----------------------------------------------------------*/
+
+/* Hardwware specifics. */
+#define portBYTE_ALIGNMENT 2
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#endif /* PORTMACRO_H */
diff --git a/portable/GCC/RX100/port.c b/portable/GCC/RX100/port.c
index e4cdbd7..fc19586 100644
--- a/portable/GCC/RX100/port.c
+++ b/portable/GCC/RX100/port.c
@@ -1,701 +1,700 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the SH2A port.
- *----------------------------------------------------------*/
-
-/* Standard C includes. */
-#include "limits.h"
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Library includes. */
-#include "string.h"
-
-/* Hardware specifics. */
-#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
-
- #include "platform.h"
-
-#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
-
- #include "iodefine.h"
-
-#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
-/*-----------------------------------------------------------*/
-
-/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
-PSW is set with U and I set, and PM and IPL clear. */
-#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
-
-/* The peripheral clock is divided by this value before being supplying the
-CMT. */
-#if ( configUSE_TICKLESS_IDLE == 0 )
- /* If tickless idle is not used then the divisor can be fixed. */
- #define portCLOCK_DIVISOR 8UL
-#elif ( configPERIPHERAL_CLOCK_HZ >= 12000000 )
- #define portCLOCK_DIVISOR 512UL
-#elif ( configPERIPHERAL_CLOCK_HZ >= 6000000 )
- #define portCLOCK_DIVISOR 128UL
-#elif ( configPERIPHERAL_CLOCK_HZ >= 1000000 )
- #define portCLOCK_DIVISOR 32UL
-#else
- #define portCLOCK_DIVISOR 8UL
-#endif
-
-/* These macros allow a critical section to be added around the call to
-xTaskIncrementTick(), which is only ever called from interrupts at the kernel
-priority - ie a known priority. Therefore these local macros are a slight
-optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
-which would require the old IPL to be read first and stored in a local variable. */
-#define portDISABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
-#define portENABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )
-
-/* Keys required to lock and unlock access to certain system registers
-respectively. */
-#define portUNLOCK_KEY 0xA50B
-#define portLOCK_KEY 0xA500
-
-/*-----------------------------------------------------------*/
-
-/*
- * Function to start the first task executing - written in asm code as direct
- * access to registers is required.
- */
-static void prvStartFirstTask( void ) __attribute__((naked));
-
-/*
- * Software interrupt handler. Performs the actual context switch (saving and
- * restoring of registers). Written in asm code as direct register access is
- * required.
- */
-#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
-
- R_BSP_PRAGMA_INTERRUPT( vPortSoftwareInterruptISR, VECT( ICU, SWINT ) )
- R_BSP_ATTRIB_INTERRUPT void vPortSoftwareInterruptISR( void ) __attribute__( ( naked ) );
-
-#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
-
- void vPortSoftwareInterruptISR( void ) __attribute__( ( naked ) );
-
-#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
-
-/*
- * The tick ISR handler. The peripheral used is configured by the application
- * via a hook/callback function.
- */
-#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
-
- R_BSP_PRAGMA_INTERRUPT( vPortTickISR, _VECT( configTICK_VECTOR ) )
- R_BSP_ATTRIB_INTERRUPT void vPortTickISR( void ); /* Do not add __attribute__( ( interrupt ) ). */
-
-#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
-
- void vPortTickISR( void ) __attribute__( ( interrupt ) );
-
-#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
-
-/*
- * Sets up the periodic ISR used for the RTOS tick using the CMT.
- * The application writer can define configSETUP_TICK_INTERRUPT() (in
- * FreeRTOSConfig.h) such that their own tick interrupt configuration is used
- * in place of prvSetupTimerInterrupt().
- */
-static void prvSetupTimerInterrupt( void );
-#ifndef configSETUP_TICK_INTERRUPT
- /* The user has not provided their own tick interrupt configuration so use
- the definition in this file (which uses the interval timer). */
- #define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt()
-#endif /* configSETUP_TICK_INTERRUPT */
-
-/*
- * Called after the sleep mode registers have been configured, prvSleep()
- * executes the pre and post sleep macros, and actually calls the wait
- * instruction.
- */
-#if configUSE_TICKLESS_IDLE == 1
- static void prvSleep( TickType_t xExpectedIdleTime );
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*-----------------------------------------------------------*/
-
-/* Used in the context save and restore code. */
-extern void *pxCurrentTCB;
-
-/* Calculate how many clock increments make up a single tick period. */
-static const uint32_t ulMatchValueForOneTick = ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
-
-#if configUSE_TICKLESS_IDLE == 1
-
- /* Holds the maximum number of ticks that can be suppressed - which is
- basically how far into the future an interrupt can be generated. Set
- during initialisation. This is the maximum possible value that the
- compare match register can hold divided by ulMatchValueForOneTick. */
- static const TickType_t xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
-
- /* Flag set from the tick interrupt to allow the sleep processing to know if
- sleep mode was exited because of a tick interrupt, or an interrupt
- generated by something else. */
- static volatile uint32_t ulTickFlag = pdFALSE;
-
- /* The CMT counter is stopped temporarily each time it is re-programmed.
- The following constant offsets the CMT counter match value by the number of
- CMT counts that would typically be missed while the counter was stopped to
- compensate for the lost time. The large difference between the divided CMT
- clock and the CPU clock means it is likely ulStoppedTimerCompensation will
- equal zero - and be optimised away. */
- static const uint32_t ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) );
-
-#endif
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
- /* Offset to end up on 8 byte boundary. */
- pxTopOfStack--;
-
- /* R0 is not included as it is the stack pointer. */
- *pxTopOfStack = 0x00;
- pxTopOfStack--;
- *pxTopOfStack = 0x00;
- pxTopOfStack--;
- *pxTopOfStack = portINITIAL_PSW;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode;
-
- /* When debugging it can be useful if every register is set to a known
- value. Otherwise code space can be saved by just setting the registers
- that need to be set. */
- #ifdef USE_FULL_REGISTER_INITIALISATION
- {
- pxTopOfStack--;
- *pxTopOfStack = 0x12345678; /* r15. */
- pxTopOfStack--;
- *pxTopOfStack = 0xaaaabbbb;
- pxTopOfStack--;
- *pxTopOfStack = 0xdddddddd;
- pxTopOfStack--;
- *pxTopOfStack = 0xcccccccc;
- pxTopOfStack--;
- *pxTopOfStack = 0xbbbbbbbb;
- pxTopOfStack--;
- *pxTopOfStack = 0xaaaaaaaa;
- pxTopOfStack--;
- *pxTopOfStack = 0x99999999;
- pxTopOfStack--;
- *pxTopOfStack = 0x88888888;
- pxTopOfStack--;
- *pxTopOfStack = 0x77777777;
- pxTopOfStack--;
- *pxTopOfStack = 0x66666666;
- pxTopOfStack--;
- *pxTopOfStack = 0x55555555;
- pxTopOfStack--;
- *pxTopOfStack = 0x44444444;
- pxTopOfStack--;
- *pxTopOfStack = 0x33333333;
- pxTopOfStack--;
- *pxTopOfStack = 0x22222222;
- pxTopOfStack--;
- }
- #else
- {
- /* Leave space for the registers that will get popped from the stack
- when the task first starts executing. */
- pxTopOfStack -= 15;
- }
- #endif
-
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
- pxTopOfStack--;
- *pxTopOfStack = 0x12345678; /* Accumulator. */
- pxTopOfStack--;
- *pxTopOfStack = 0x87654321; /* Accumulator. */
-
- return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
- /* Use pxCurrentTCB just so it does not get optimised away. */
- if( pxCurrentTCB != NULL )
- {
- /* Call an application function to set up the timer that will generate
- the tick interrupt. This way the application can decide which
- peripheral to use. If tickless mode is used then the default
- implementation defined in this file (which uses CMT0) should not be
- overridden. */
- configSETUP_TICK_INTERRUPT();
-
- /* Enable the software interrupt. */
- _IEN( _ICU_SWINT ) = 1;
-
- /* Ensure the software interrupt is clear. */
- _IR( _ICU_SWINT ) = 0;
-
- /* Ensure the software interrupt is set to the kernel priority. */
- _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
-
- /* Start the first task. */
- prvStartFirstTask();
- }
-
- /* Execution should not reach here as the tasks are now running!
- prvSetupTimerInterrupt() is called here to prevent the compiler outputting
- a warning about a statically declared function not being referenced in the
- case that the application writer has provided their own tick interrupt
- configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
- their own routine will be called in place of prvSetupTimerInterrupt()). */
- prvSetupTimerInterrupt();
-
- /* Should not get here. */
- return pdFAIL;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
- /* Not implemented in ports where there is nothing to return to.
- Artificially force an assert. */
- configASSERT( pxCurrentTCB == NULL );
-}
-/*-----------------------------------------------------------*/
-
-static void prvStartFirstTask( void )
-{
- __asm volatile
- (
- /* When starting the scheduler there is nothing that needs moving to the
- interrupt stack because the function is not called from an interrupt.
- Just ensure the current stack is the user stack. */
- "SETPSW U \n" \
-
- /* Obtain the location of the stack associated with which ever task
- pxCurrentTCB is currently pointing to. */
- "MOV.L #_pxCurrentTCB, R15 \n" \
- "MOV.L [R15], R15 \n" \
- "MOV.L [R15], R0 \n" \
-
- /* Restore the registers from the stack of the task pointed to by
- pxCurrentTCB. */
- "POP R15 \n" \
-
- /* Accumulator low 32 bits. */
- "MVTACLO R15 \n" \
- "POP R15 \n" \
-
- /* Accumulator high 32 bits. */
- "MVTACHI R15 \n" \
-
- /* R1 to R15 - R0 is not included as it is the SP. */
- "POPM R1-R15 \n" \
-
- /* This pops the remaining registers. */
- "RTE \n" \
- "NOP \n" \
- "NOP \n"
- );
-}
-/*-----------------------------------------------------------*/
-
-void vPortSoftwareInterruptISR( void )
-{
- __asm volatile
- (
- /* Re-enable interrupts. */
- "SETPSW I \n" \
-
- /* Move the data that was automatically pushed onto the interrupt stack when
- the interrupt occurred from the interrupt stack to the user stack.
-
- R15 is saved before it is clobbered. */
- "PUSH.L R15 \n" \
-
- /* Read the user stack pointer. */
- "MVFC USP, R15 \n" \
-
- /* Move the address down to the data being moved. */
- "SUB #12, R15 \n" \
- "MVTC R15, USP \n" \
-
- /* Copy the data across, R15, then PC, then PSW. */
- "MOV.L [ R0 ], [ R15 ] \n" \
- "MOV.L 4[ R0 ], 4[ R15 ] \n" \
- "MOV.L 8[ R0 ], 8[ R15 ] \n" \
-
- /* Move the interrupt stack pointer to its new correct position. */
- "ADD #12, R0 \n" \
-
- /* All the rest of the registers are saved directly to the user stack. */
- "SETPSW U \n" \
-
- /* Save the rest of the general registers (R15 has been saved already). */
- "PUSHM R1-R14 \n" \
-
- /* Save the accumulator. */
- "MVFACHI R15 \n" \
- "PUSH.L R15 \n" \
-
- /* Middle word. */
- "MVFACMI R15 \n" \
-
- /* Shifted left as it is restored to the low order word. */
- "SHLL #16, R15 \n" \
- "PUSH.L R15 \n" \
-
- /* Save the stack pointer to the TCB. */
- "MOV.L #_pxCurrentTCB, R15 \n" \
- "MOV.L [ R15 ], R15 \n" \
- "MOV.L R0, [ R15 ] \n" \
-
- /* Ensure the interrupt mask is set to the syscall priority while the kernel
- structures are being accessed. */
- "MVTIPL %0 \n" \
-
- /* Select the next task to run. */
- "BSR.A _vTaskSwitchContext \n" \
-
- /* Reset the interrupt mask as no more data structure access is required. */
- "MVTIPL %1 \n" \
-
- /* Load the stack pointer of the task that is now selected as the Running
- state task from its TCB. */
- "MOV.L #_pxCurrentTCB,R15 \n" \
- "MOV.L [ R15 ], R15 \n" \
- "MOV.L [ R15 ], R0 \n" \
-
- /* Restore the context of the new task. The PSW (Program Status Word) and
- PC will be popped by the RTE instruction. */
- "POP R15 \n" \
- "MVTACLO R15 \n" \
- "POP R15 \n" \
- "MVTACHI R15 \n" \
- "POPM R1-R15 \n" \
- "RTE \n" \
- "NOP \n" \
- "NOP "
- :: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY)
- );
-}
-/*-----------------------------------------------------------*/
-
-void vPortTickISR( void )
-{
- /* Re-enabled interrupts. */
- __asm volatile( "SETPSW I" );
-
- /* Increment the tick, and perform any processing the new tick value
- necessitates. Ensure IPL is at the max syscall value first. */
- portDISABLE_INTERRUPTS_FROM_KERNEL_ISR();
- {
- if( xTaskIncrementTick() != pdFALSE )
- {
- taskYIELD();
- }
- }
- portENABLE_INTERRUPTS_FROM_KERNEL_ISR();
-
- #if configUSE_TICKLESS_IDLE == 1
- {
- /* The CPU woke because of a tick. */
- ulTickFlag = pdTRUE;
-
- /* If this is the first tick since exiting tickless mode then the CMT
- compare match value needs resetting. */
- CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
- }
- #endif
-}
-/*-----------------------------------------------------------*/
-
-uint32_t ulPortGetIPL( void )
-{
- __asm volatile
- (
- "MVFC PSW, R1 \n" \
- "SHLR #24, R1 \n" \
- "RTS "
- );
-
- /* This will never get executed, but keeps the compiler from complaining. */
- return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortSetIPL( uint32_t ulNewIPL )
-{
- __asm volatile
- (
- "PUSH R5 \n" \
- "MVFC PSW, R5 \n" \
- "SHLL #24, R1 \n" \
- "AND #-0F000001H, R5 \n" \
- "OR R1, R5 \n" \
- "MVTC R5, PSW \n" \
- "POP R5 \n" \
- "RTS "
- );
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupTimerInterrupt( void )
-{
- /* Unlock. */
- SYSTEM.PRCR.WORD = portUNLOCK_KEY;
-
- /* Enable CMT0. */
- MSTP( CMT0 ) = 0;
-
- /* Lock again. */
- SYSTEM.PRCR.WORD = portLOCK_KEY;
-
- /* Interrupt on compare match. */
- CMT0.CMCR.BIT.CMIE = 1;
-
- /* Set the compare match value. */
- CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
-
- /* Divide the PCLK. */
- #if portCLOCK_DIVISOR == 512
- {
- CMT0.CMCR.BIT.CKS = 3;
- }
- #elif portCLOCK_DIVISOR == 128
- {
- CMT0.CMCR.BIT.CKS = 2;
- }
- #elif portCLOCK_DIVISOR == 32
- {
- CMT0.CMCR.BIT.CKS = 1;
- }
- #elif portCLOCK_DIVISOR == 8
- {
- CMT0.CMCR.BIT.CKS = 0;
- }
- #else
- {
- #error Invalid portCLOCK_DIVISOR setting
- }
- #endif
-
- /* Enable the interrupt... */
- _IEN( _CMT0_CMI0 ) = 1;
-
- /* ...and set its priority to the application defined kernel priority. */
- _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;
-
- /* Start the timer. */
- CMT.CMSTR0.BIT.STR0 = 1;
-}
-/*-----------------------------------------------------------*/
-
-#if configUSE_TICKLESS_IDLE == 1
-
- static void prvSleep( TickType_t xExpectedIdleTime )
- {
- /* Allow the application to define some pre-sleep processing. */
- configPRE_SLEEP_PROCESSING( xExpectedIdleTime );
-
- /* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING()
- means the application defined code has already executed the WAIT
- instruction. */
- if( xExpectedIdleTime > 0 )
- {
- __asm volatile( "WAIT" );
- }
-
- /* Allow the application to define some post sleep processing. */
- configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
- }
-
-#endif /* configUSE_TICKLESS_IDLE */
-/*-----------------------------------------------------------*/
-
-#if configUSE_TICKLESS_IDLE == 1
-
- void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
- {
- uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount;
- eSleepModeStatus eSleepAction;
-
- /* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */
-
- /* Make sure the CMT reload value does not overflow the counter. */
- if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
- {
- xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
- }
-
- /* Calculate the reload value required to wait xExpectedIdleTime tick
- periods. */
- ulMatchValue = ulMatchValueForOneTick * xExpectedIdleTime;
- if( ulMatchValue > ulStoppedTimerCompensation )
- {
- /* Compensate for the fact that the CMT is going to be stopped
- momentarily. */
- ulMatchValue -= ulStoppedTimerCompensation;
- }
-
- /* Stop the CMT momentarily. The time the CMT is stopped for is
- accounted for as best it can be, but using the tickless mode will
- inevitably result in some tiny drift of the time maintained by the
- kernel with respect to calendar time. */
- CMT.CMSTR0.BIT.STR0 = 0;
- while( CMT.CMSTR0.BIT.STR0 == 1 )
- {
- /* Nothing to do here. */
- }
-
- /* Critical section using the global interrupt bit as the i bit is
- automatically reset by the WAIT instruction. */
- __asm volatile( "CLRPSW i" );
-
- /* The tick flag is set to false before sleeping. If it is true when
- sleep mode is exited then sleep mode was probably exited because the
- tick was suppressed for the entire xExpectedIdleTime period. */
- ulTickFlag = pdFALSE;
-
- /* If a context switch is pending then abandon the low power entry as
- the context switch might have been pended by an external interrupt that
- requires processing. */
- eSleepAction = eTaskConfirmSleepModeStatus();
- if( eSleepAction == eAbortSleep )
- {
- /* Restart tick. */
- CMT.CMSTR0.BIT.STR0 = 1;
- __asm volatile( "SETPSW i" );
- }
- else if( eSleepAction == eNoTasksWaitingTimeout )
- {
- /* Protection off. */
- SYSTEM.PRCR.WORD = portUNLOCK_KEY;
-
- /* Ready for software standby with all clocks stopped. */
- SYSTEM.SBYCR.BIT.SSBY = 1;
-
- /* Protection on. */
- SYSTEM.PRCR.WORD = portLOCK_KEY;
-
- /* Sleep until something happens. Calling prvSleep() will
- automatically reset the i bit in the PSW. */
- prvSleep( xExpectedIdleTime );
-
- /* Restart the CMT. */
- CMT.CMSTR0.BIT.STR0 = 1;
- }
- else
- {
- /* Protection off. */
- SYSTEM.PRCR.WORD = portUNLOCK_KEY;
-
- /* Ready for deep sleep mode. */
- SYSTEM.MSTPCRC.BIT.DSLPE = 1;
- SYSTEM.MSTPCRA.BIT.MSTPA28 = 1;
- SYSTEM.SBYCR.BIT.SSBY = 0;
-
- /* Protection on. */
- SYSTEM.PRCR.WORD = portLOCK_KEY;
-
- /* Adjust the match value to take into account that the current
- time slice is already partially complete. */
- ulMatchValue -= ( uint32_t ) CMT0.CMCNT;
- CMT0.CMCOR = ( uint16_t ) ulMatchValue;
-
- /* Restart the CMT to count up to the new match value. */
- CMT0.CMCNT = 0;
- CMT.CMSTR0.BIT.STR0 = 1;
-
- /* Sleep until something happens. Calling prvSleep() will
- automatically reset the i bit in the PSW. */
- prvSleep( xExpectedIdleTime );
-
- /* Stop CMT. Again, the time the SysTick is stopped for is
- accounted for as best it can be, but using the tickless mode will
- inevitably result in some tiny drift of the time maintained by the
- kernel with respect to calendar time. */
- CMT.CMSTR0.BIT.STR0 = 0;
- while( CMT.CMSTR0.BIT.STR0 == 1 )
- {
- /* Nothing to do here. */
- }
-
- ulCurrentCount = ( uint32_t ) CMT0.CMCNT;
-
- if( ulTickFlag != pdFALSE )
- {
- /* The tick interrupt has already executed, although because
- this function is called with the scheduler suspended the actual
- tick processing will not occur until after this function has
- exited. Reset the match value with whatever remains of this
- tick period. */
- ulMatchValue = ulMatchValueForOneTick - ulCurrentCount;
- CMT0.CMCOR = ( uint16_t ) ulMatchValue;
-
- /* The tick interrupt handler will already have pended the tick
- processing in the kernel. As the pending tick will be
- processed as soon as this function exits, the tick value
- maintained by the tick is stepped forward by one less than the
- time spent sleeping. The actual stepping of the tick appears
- later in this function. */
- ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
- }
- else
- {
- /* Something other than the tick interrupt ended the sleep.
- How many complete tick periods passed while the processor was
- sleeping? */
- ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick;
-
- /* The match value is set to whatever fraction of a single tick
- period remains. */
- ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick );
- CMT0.CMCOR = ( uint16_t ) ulMatchValue;
- }
-
- /* Restart the CMT so it runs up to the match value. The match value
- will get set to the value required to generate exactly one tick period
- the next time the CMT interrupt executes. */
- CMT0.CMCNT = 0;
- CMT.CMSTR0.BIT.STR0 = 1;
-
- /* Wind the tick forward by the number of tick periods that the CPU
- remained in a low power state. */
- vTaskStepTick( ulCompleteTickPeriods );
- }
- }
-
-#endif /* configUSE_TICKLESS_IDLE */
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the SH2A port.
+ *----------------------------------------------------------*/
+
+/* Standard C includes. */
+#include "limits.h"
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Library includes. */
+#include "string.h"
+
+/* Hardware specifics. */
+#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
+
+ #include "platform.h"
+
+#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+ #include "iodefine.h"
+
+#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+/*-----------------------------------------------------------*/
+
+/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
+PSW is set with U and I set, and PM and IPL clear. */
+#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
+
+/* The peripheral clock is divided by this value before being supplying the
+CMT. */
+#if ( configUSE_TICKLESS_IDLE == 0 )
+ /* If tickless idle is not used then the divisor can be fixed. */
+ #define portCLOCK_DIVISOR 8UL
+#elif ( configPERIPHERAL_CLOCK_HZ >= 12000000 )
+ #define portCLOCK_DIVISOR 512UL
+#elif ( configPERIPHERAL_CLOCK_HZ >= 6000000 )
+ #define portCLOCK_DIVISOR 128UL
+#elif ( configPERIPHERAL_CLOCK_HZ >= 1000000 )
+ #define portCLOCK_DIVISOR 32UL
+#else
+ #define portCLOCK_DIVISOR 8UL
+#endif
+
+/* These macros allow a critical section to be added around the call to
+xTaskIncrementTick(), which is only ever called from interrupts at the kernel
+priority - ie a known priority. Therefore these local macros are a slight
+optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
+which would require the old IPL to be read first and stored in a local variable. */
+#define portDISABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+#define portENABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )
+
+/* Keys required to lock and unlock access to certain system registers
+respectively. */
+#define portUNLOCK_KEY 0xA50B
+#define portLOCK_KEY 0xA500
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Function to start the first task executing - written in asm code as direct
+ * access to registers is required.
+ */
+static void prvStartFirstTask( void ) __attribute__((naked));
+
+/*
+ * Software interrupt handler. Performs the actual context switch (saving and
+ * restoring of registers). Written in asm code as direct register access is
+ * required.
+ */
+#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
+
+ R_BSP_PRAGMA_INTERRUPT( vPortSoftwareInterruptISR, VECT( ICU, SWINT ) )
+ R_BSP_ATTRIB_INTERRUPT void vPortSoftwareInterruptISR( void ) __attribute__( ( naked ) );
+
+#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+ void vPortSoftwareInterruptISR( void ) __attribute__( ( naked ) );
+
+#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+/*
+ * The tick ISR handler. The peripheral used is configured by the application
+ * via a hook/callback function.
+ */
+#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
+
+ R_BSP_PRAGMA_INTERRUPT( vPortTickISR, _VECT( configTICK_VECTOR ) )
+ R_BSP_ATTRIB_INTERRUPT void vPortTickISR( void ); /* Do not add __attribute__( ( interrupt ) ). */
+
+#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+ void vPortTickISR( void ) __attribute__( ( interrupt ) );
+
+#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+/*
+ * Sets up the periodic ISR used for the RTOS tick using the CMT.
+ * The application writer can define configSETUP_TICK_INTERRUPT() (in
+ * FreeRTOSConfig.h) such that their own tick interrupt configuration is used
+ * in place of prvSetupTimerInterrupt().
+ */
+static void prvSetupTimerInterrupt( void );
+#ifndef configSETUP_TICK_INTERRUPT
+ /* The user has not provided their own tick interrupt configuration so use
+ the definition in this file (which uses the interval timer). */
+ #define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt()
+#endif /* configSETUP_TICK_INTERRUPT */
+
+/*
+ * Called after the sleep mode registers have been configured, prvSleep()
+ * executes the pre and post sleep macros, and actually calls the wait
+ * instruction.
+ */
+#if configUSE_TICKLESS_IDLE == 1
+ static void prvSleep( TickType_t xExpectedIdleTime );
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*-----------------------------------------------------------*/
+
+/* Used in the context save and restore code. */
+extern void *pxCurrentTCB;
+
+/* Calculate how many clock increments make up a single tick period. */
+static const uint32_t ulMatchValueForOneTick = ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
+
+#if configUSE_TICKLESS_IDLE == 1
+
+ /* Holds the maximum number of ticks that can be suppressed - which is
+ basically how far into the future an interrupt can be generated. Set
+ during initialisation. This is the maximum possible value that the
+ compare match register can hold divided by ulMatchValueForOneTick. */
+ static const TickType_t xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
+
+ /* Flag set from the tick interrupt to allow the sleep processing to know if
+ sleep mode was exited because of a tick interrupt, or an interrupt
+ generated by something else. */
+ static volatile uint32_t ulTickFlag = pdFALSE;
+
+ /* The CMT counter is stopped temporarily each time it is re-programmed.
+ The following constant offsets the CMT counter match value by the number of
+ CMT counts that would typically be missed while the counter was stopped to
+ compensate for the lost time. The large difference between the divided CMT
+ clock and the CPU clock means it is likely ulStoppedTimerCompensation will
+ equal zero - and be optimised away. */
+ static const uint32_t ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) );
+
+#endif
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+ /* Offset to end up on 8 byte boundary. */
+ pxTopOfStack--;
+
+ /* R0 is not included as it is the stack pointer. */
+ *pxTopOfStack = 0x00;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x00;
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_PSW;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode;
+
+ /* When debugging it can be useful if every register is set to a known
+ value. Otherwise code space can be saved by just setting the registers
+ that need to be set. */
+ #ifdef USE_FULL_REGISTER_INITIALISATION
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = 0x12345678; /* r15. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0xaaaabbbb;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xdddddddd;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xcccccccc;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xbbbbbbbb;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xaaaaaaaa;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x99999999;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x88888888;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x77777777;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x66666666;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x55555555;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x44444444;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x33333333;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x22222222;
+ pxTopOfStack--;
+ }
+ #else
+ {
+ /* Leave space for the registers that will get popped from the stack
+ when the task first starts executing. */
+ pxTopOfStack -= 15;
+ }
+ #endif
+
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x12345678; /* Accumulator. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x87654321; /* Accumulator. */
+
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+ /* Use pxCurrentTCB just so it does not get optimised away. */
+ if( pxCurrentTCB != NULL )
+ {
+ /* Call an application function to set up the timer that will generate
+ the tick interrupt. This way the application can decide which
+ peripheral to use. If tickless mode is used then the default
+ implementation defined in this file (which uses CMT0) should not be
+ overridden. */
+ configSETUP_TICK_INTERRUPT();
+
+ /* Enable the software interrupt. */
+ _IEN( _ICU_SWINT ) = 1;
+
+ /* Ensure the software interrupt is clear. */
+ _IR( _ICU_SWINT ) = 0;
+
+ /* Ensure the software interrupt is set to the kernel priority. */
+ _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
+
+ /* Start the first task. */
+ prvStartFirstTask();
+ }
+
+ /* Execution should not reach here as the tasks are now running!
+ prvSetupTimerInterrupt() is called here to prevent the compiler outputting
+ a warning about a statically declared function not being referenced in the
+ case that the application writer has provided their own tick interrupt
+ configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
+ their own routine will be called in place of prvSetupTimerInterrupt()). */
+ prvSetupTimerInterrupt();
+
+ /* Should not get here. */
+ return pdFAIL;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+ /* Not implemented in ports where there is nothing to return to.
+ Artificially force an assert. */
+ configASSERT( pxCurrentTCB == NULL );
+}
+/*-----------------------------------------------------------*/
+
+static void prvStartFirstTask( void )
+{
+ __asm volatile
+ (
+ /* When starting the scheduler there is nothing that needs moving to the
+ interrupt stack because the function is not called from an interrupt.
+ Just ensure the current stack is the user stack. */
+ "SETPSW U \n" \
+
+ /* Obtain the location of the stack associated with which ever task
+ pxCurrentTCB is currently pointing to. */
+ "MOV.L #_pxCurrentTCB, R15 \n" \
+ "MOV.L [R15], R15 \n" \
+ "MOV.L [R15], R0 \n" \
+
+ /* Restore the registers from the stack of the task pointed to by
+ pxCurrentTCB. */
+ "POP R15 \n" \
+
+ /* Accumulator low 32 bits. */
+ "MVTACLO R15 \n" \
+ "POP R15 \n" \
+
+ /* Accumulator high 32 bits. */
+ "MVTACHI R15 \n" \
+
+ /* R1 to R15 - R0 is not included as it is the SP. */
+ "POPM R1-R15 \n" \
+
+ /* This pops the remaining registers. */
+ "RTE \n" \
+ "NOP \n" \
+ "NOP \n"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSoftwareInterruptISR( void )
+{
+ __asm volatile
+ (
+ /* Re-enable interrupts. */
+ "SETPSW I \n" \
+
+ /* Move the data that was automatically pushed onto the interrupt stack when
+ the interrupt occurred from the interrupt stack to the user stack.
+
+ R15 is saved before it is clobbered. */
+ "PUSH.L R15 \n" \
+
+ /* Read the user stack pointer. */
+ "MVFC USP, R15 \n" \
+
+ /* Move the address down to the data being moved. */
+ "SUB #12, R15 \n" \
+ "MVTC R15, USP \n" \
+
+ /* Copy the data across, R15, then PC, then PSW. */
+ "MOV.L [ R0 ], [ R15 ] \n" \
+ "MOV.L 4[ R0 ], 4[ R15 ] \n" \
+ "MOV.L 8[ R0 ], 8[ R15 ] \n" \
+
+ /* Move the interrupt stack pointer to its new correct position. */
+ "ADD #12, R0 \n" \
+
+ /* All the rest of the registers are saved directly to the user stack. */
+ "SETPSW U \n" \
+
+ /* Save the rest of the general registers (R15 has been saved already). */
+ "PUSHM R1-R14 \n" \
+
+ /* Save the accumulator. */
+ "MVFACHI R15 \n" \
+ "PUSH.L R15 \n" \
+
+ /* Middle word. */
+ "MVFACMI R15 \n" \
+
+ /* Shifted left as it is restored to the low order word. */
+ "SHLL #16, R15 \n" \
+ "PUSH.L R15 \n" \
+
+ /* Save the stack pointer to the TCB. */
+ "MOV.L #_pxCurrentTCB, R15 \n" \
+ "MOV.L [ R15 ], R15 \n" \
+ "MOV.L R0, [ R15 ] \n" \
+
+ /* Ensure the interrupt mask is set to the syscall priority while the kernel
+ structures are being accessed. */
+ "MVTIPL %0 \n" \
+
+ /* Select the next task to run. */
+ "BSR.A _vTaskSwitchContext \n" \
+
+ /* Reset the interrupt mask as no more data structure access is required. */
+ "MVTIPL %1 \n" \
+
+ /* Load the stack pointer of the task that is now selected as the Running
+ state task from its TCB. */
+ "MOV.L #_pxCurrentTCB,R15 \n" \
+ "MOV.L [ R15 ], R15 \n" \
+ "MOV.L [ R15 ], R0 \n" \
+
+ /* Restore the context of the new task. The PSW (Program Status Word) and
+ PC will be popped by the RTE instruction. */
+ "POP R15 \n" \
+ "MVTACLO R15 \n" \
+ "POP R15 \n" \
+ "MVTACHI R15 \n" \
+ "POPM R1-R15 \n" \
+ "RTE \n" \
+ "NOP \n" \
+ "NOP "
+ :: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY)
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vPortTickISR( void )
+{
+ /* Re-enabled interrupts. */
+ __asm volatile( "SETPSW I" );
+
+ /* Increment the tick, and perform any processing the new tick value
+ necessitates. Ensure IPL is at the max syscall value first. */
+ portDISABLE_INTERRUPTS_FROM_KERNEL_ISR();
+ {
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ taskYIELD();
+ }
+ }
+ portENABLE_INTERRUPTS_FROM_KERNEL_ISR();
+
+ #if configUSE_TICKLESS_IDLE == 1
+ {
+ /* The CPU woke because of a tick. */
+ ulTickFlag = pdTRUE;
+
+ /* If this is the first tick since exiting tickless mode then the CMT
+ compare match value needs resetting. */
+ CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
+ }
+ #endif
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulPortGetIPL( void )
+{
+ __asm volatile
+ (
+ "MVFC PSW, R1 \n" \
+ "SHLR #24, R1 \n" \
+ "RTS "
+ );
+
+ /* This will never get executed, but keeps the compiler from complaining. */
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortSetIPL( uint32_t ulNewIPL )
+{
+ __asm volatile
+ (
+ "PUSH R5 \n" \
+ "MVFC PSW, R5 \n" \
+ "SHLL #24, R1 \n" \
+ "AND #-0F000001H, R5 \n" \
+ "OR R1, R5 \n" \
+ "MVTC R5, PSW \n" \
+ "POP R5 \n" \
+ "RTS "
+ );
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+ /* Unlock. */
+ SYSTEM.PRCR.WORD = portUNLOCK_KEY;
+
+ /* Enable CMT0. */
+ MSTP( CMT0 ) = 0;
+
+ /* Lock again. */
+ SYSTEM.PRCR.WORD = portLOCK_KEY;
+
+ /* Interrupt on compare match. */
+ CMT0.CMCR.BIT.CMIE = 1;
+
+ /* Set the compare match value. */
+ CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
+
+ /* Divide the PCLK. */
+ #if portCLOCK_DIVISOR == 512
+ {
+ CMT0.CMCR.BIT.CKS = 3;
+ }
+ #elif portCLOCK_DIVISOR == 128
+ {
+ CMT0.CMCR.BIT.CKS = 2;
+ }
+ #elif portCLOCK_DIVISOR == 32
+ {
+ CMT0.CMCR.BIT.CKS = 1;
+ }
+ #elif portCLOCK_DIVISOR == 8
+ {
+ CMT0.CMCR.BIT.CKS = 0;
+ }
+ #else
+ {
+ #error Invalid portCLOCK_DIVISOR setting
+ }
+ #endif
+
+ /* Enable the interrupt... */
+ _IEN( _CMT0_CMI0 ) = 1;
+
+ /* ...and set its priority to the application defined kernel priority. */
+ _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;
+
+ /* Start the timer. */
+ CMT.CMSTR0.BIT.STR0 = 1;
+}
+/*-----------------------------------------------------------*/
+
+#if configUSE_TICKLESS_IDLE == 1
+
+ static void prvSleep( TickType_t xExpectedIdleTime )
+ {
+ /* Allow the application to define some pre-sleep processing. */
+ configPRE_SLEEP_PROCESSING( xExpectedIdleTime );
+
+ /* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING()
+ means the application defined code has already executed the WAIT
+ instruction. */
+ if( xExpectedIdleTime > 0 )
+ {
+ __asm volatile( "WAIT" );
+ }
+
+ /* Allow the application to define some post sleep processing. */
+ configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+ }
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+#if configUSE_TICKLESS_IDLE == 1
+
+ void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+ {
+ uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount;
+ eSleepModeStatus eSleepAction;
+
+ /* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */
+
+ /* Make sure the CMT reload value does not overflow the counter. */
+ if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+ {
+ xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+ }
+
+ /* Calculate the reload value required to wait xExpectedIdleTime tick
+ periods. */
+ ulMatchValue = ulMatchValueForOneTick * xExpectedIdleTime;
+ if( ulMatchValue > ulStoppedTimerCompensation )
+ {
+ /* Compensate for the fact that the CMT is going to be stopped
+ momentarily. */
+ ulMatchValue -= ulStoppedTimerCompensation;
+ }
+
+ /* Stop the CMT momentarily. The time the CMT is stopped for is
+ accounted for as best it can be, but using the tickless mode will
+ inevitably result in some tiny drift of the time maintained by the
+ kernel with respect to calendar time. */
+ CMT.CMSTR0.BIT.STR0 = 0;
+ while( CMT.CMSTR0.BIT.STR0 == 1 )
+ {
+ /* Nothing to do here. */
+ }
+
+ /* Critical section using the global interrupt bit as the i bit is
+ automatically reset by the WAIT instruction. */
+ __asm volatile( "CLRPSW i" );
+
+ /* The tick flag is set to false before sleeping. If it is true when
+ sleep mode is exited then sleep mode was probably exited because the
+ tick was suppressed for the entire xExpectedIdleTime period. */
+ ulTickFlag = pdFALSE;
+
+ /* If a context switch is pending then abandon the low power entry as
+ the context switch might have been pended by an external interrupt that
+ requires processing. */
+ eSleepAction = eTaskConfirmSleepModeStatus();
+ if( eSleepAction == eAbortSleep )
+ {
+ /* Restart tick. */
+ CMT.CMSTR0.BIT.STR0 = 1;
+ __asm volatile( "SETPSW i" );
+ }
+ else if( eSleepAction == eNoTasksWaitingTimeout )
+ {
+ /* Protection off. */
+ SYSTEM.PRCR.WORD = portUNLOCK_KEY;
+
+ /* Ready for software standby with all clocks stopped. */
+ SYSTEM.SBYCR.BIT.SSBY = 1;
+
+ /* Protection on. */
+ SYSTEM.PRCR.WORD = portLOCK_KEY;
+
+ /* Sleep until something happens. Calling prvSleep() will
+ automatically reset the i bit in the PSW. */
+ prvSleep( xExpectedIdleTime );
+
+ /* Restart the CMT. */
+ CMT.CMSTR0.BIT.STR0 = 1;
+ }
+ else
+ {
+ /* Protection off. */
+ SYSTEM.PRCR.WORD = portUNLOCK_KEY;
+
+ /* Ready for deep sleep mode. */
+ SYSTEM.MSTPCRC.BIT.DSLPE = 1;
+ SYSTEM.MSTPCRA.BIT.MSTPA28 = 1;
+ SYSTEM.SBYCR.BIT.SSBY = 0;
+
+ /* Protection on. */
+ SYSTEM.PRCR.WORD = portLOCK_KEY;
+
+ /* Adjust the match value to take into account that the current
+ time slice is already partially complete. */
+ ulMatchValue -= ( uint32_t ) CMT0.CMCNT;
+ CMT0.CMCOR = ( uint16_t ) ulMatchValue;
+
+ /* Restart the CMT to count up to the new match value. */
+ CMT0.CMCNT = 0;
+ CMT.CMSTR0.BIT.STR0 = 1;
+
+ /* Sleep until something happens. Calling prvSleep() will
+ automatically reset the i bit in the PSW. */
+ prvSleep( xExpectedIdleTime );
+
+ /* Stop CMT. Again, the time the SysTick is stopped for is
+ accounted for as best it can be, but using the tickless mode will
+ inevitably result in some tiny drift of the time maintained by the
+ kernel with respect to calendar time. */
+ CMT.CMSTR0.BIT.STR0 = 0;
+ while( CMT.CMSTR0.BIT.STR0 == 1 )
+ {
+ /* Nothing to do here. */
+ }
+
+ ulCurrentCount = ( uint32_t ) CMT0.CMCNT;
+
+ if( ulTickFlag != pdFALSE )
+ {
+ /* The tick interrupt has already executed, although because
+ this function is called with the scheduler suspended the actual
+ tick processing will not occur until after this function has
+ exited. Reset the match value with whatever remains of this
+ tick period. */
+ ulMatchValue = ulMatchValueForOneTick - ulCurrentCount;
+ CMT0.CMCOR = ( uint16_t ) ulMatchValue;
+
+ /* The tick interrupt handler will already have pended the tick
+ processing in the kernel. As the pending tick will be
+ processed as soon as this function exits, the tick value
+ maintained by the tick is stepped forward by one less than the
+ time spent sleeping. The actual stepping of the tick appears
+ later in this function. */
+ ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+ }
+ else
+ {
+ /* Something other than the tick interrupt ended the sleep.
+ How many complete tick periods passed while the processor was
+ sleeping? */
+ ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick;
+
+ /* The match value is set to whatever fraction of a single tick
+ period remains. */
+ ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick );
+ CMT0.CMCOR = ( uint16_t ) ulMatchValue;
+ }
+
+ /* Restart the CMT so it runs up to the match value. The match value
+ will get set to the value required to generate exactly one tick period
+ the next time the CMT interrupt executes. */
+ CMT0.CMCNT = 0;
+ CMT.CMSTR0.BIT.STR0 = 1;
+
+ /* Wind the tick forward by the number of tick periods that the CPU
+ remained in a low power state. */
+ vTaskStepTick( ulCompleteTickPeriods );
+ }
+ }
+
+#endif /* configUSE_TICKLESS_IDLE */
diff --git a/portable/GCC/RX100/portmacro.h b/portable/GCC/RX100/portmacro.h
index 1246f94..842754f 100644
--- a/portable/GCC/RX100/portmacro.h
+++ b/portable/GCC/RX100/portmacro.h
@@ -1,150 +1,149 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-/* When the FIT configurator or the Smart Configurator is used, platform.h has to be
- * used. */
-#ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H
- #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0
-#endif
-
-/* Type definitions - these are a bit legacy and not really used now, other than
-portSTACK_TYPE and portBASE_TYPE. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT short
-#define portSTACK_TYPE uint32_t
-#define portBASE_TYPE long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
-#else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
- /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */
-#define portSTACK_GROWTH -1
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP() __asm volatile( "NOP" )
-
-/* Save clobbered register, set ITU SWINR (at address 0x872E0), read the value
-back to ensure it is set before continuing, then restore the clobbered
-register. */
-#define portYIELD() \
- __asm volatile \
- ( \
- "MOV.L #0x872E0, r5 \n\t" \
- "MOV.B #1, [r5] \n\t" \
- "MOV.L [r5], r5 \n\t" \
- ::: "r5" \
- )
-
-#define portYIELD_FROM_ISR( x ) do { if( x != pdFALSE ) { portYIELD(); } } while( 0 )
-
-/* These macros should not be called directly, but through the
-taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is
-performed if configASSERT() is defined to ensure an assertion handler does not
-inadvertently attempt to lower the IPL when the call to assert was triggered
-because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
-when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API
-functions are those that end in FromISR. FreeRTOS maintains a separate
-interrupt API to ensure API function and interrupt entry is as fast and as
-simple as possible. */
-#define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0" )
-#ifdef configASSERT
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
- #define portDISABLE_INTERRUPTS() if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
-#else
- #define portDISABLE_INTERRUPTS() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
-#endif
-
-/* Critical nesting counts are stored in the TCB. */
-#define portCRITICAL_NESTING_IN_TCB ( 1 )
-
-/* The critical nesting functions defined within tasks.c. */
-extern void vTaskEnterCritical( void );
-extern void vTaskExitCritical( void );
-#define portENTER_CRITICAL() vTaskEnterCritical()
-#define portEXIT_CRITICAL() vTaskExitCritical()
-
-/* As this port allows interrupt nesting... */
-uint32_t ulPortGetIPL( void ) __attribute__((naked));
-void vPortSetIPL( uint32_t ulNewIPL ) __attribute__((naked));
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus )
-
-/* Tickless idle/low power functionality. */
-#if configUSE_TICKLESS_IDLE == 1
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
-#endif
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+/* When the FIT configurator or the Smart Configurator is used, platform.h has to be
+ * used. */
+#ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H
+ #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0
+#endif
+
+/* Type definitions - these are a bit legacy and not really used now, other than
+portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */
+#define portSTACK_GROWTH -1
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP() __asm volatile( "NOP" )
+
+/* Save clobbered register, set ITU SWINR (at address 0x872E0), read the value
+back to ensure it is set before continuing, then restore the clobbered
+register. */
+#define portYIELD() \
+ __asm volatile \
+ ( \
+ "MOV.L #0x872E0, r5 \n\t" \
+ "MOV.B #1, [r5] \n\t" \
+ "MOV.L [r5], r5 \n\t" \
+ ::: "r5" \
+ )
+
+#define portYIELD_FROM_ISR( x ) do { if( x != pdFALSE ) { portYIELD(); } } while( 0 )
+
+/* These macros should not be called directly, but through the
+taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is
+performed if configASSERT() is defined to ensure an assertion handler does not
+inadvertently attempt to lower the IPL when the call to assert was triggered
+because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
+when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API
+functions are those that end in FromISR. FreeRTOS maintains a separate
+interrupt API to ensure API function and interrupt entry is as fast and as
+simple as possible. */
+#define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0" )
+#ifdef configASSERT
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+ #define portDISABLE_INTERRUPTS() if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+#else
+ #define portDISABLE_INTERRUPTS() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+#endif
+
+/* Critical nesting counts are stored in the TCB. */
+#define portCRITICAL_NESTING_IN_TCB ( 1 )
+
+/* The critical nesting functions defined within tasks.c. */
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL() vTaskEnterCritical()
+#define portEXIT_CRITICAL() vTaskExitCritical()
+
+/* As this port allows interrupt nesting... */
+uint32_t ulPortGetIPL( void ) __attribute__((naked));
+void vPortSetIPL( uint32_t ulNewIPL ) __attribute__((naked));
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus )
+
+/* Tickless idle/low power functionality. */
+#if configUSE_TICKLESS_IDLE == 1
+ #ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+ #endif
+#endif
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/portable/GCC/RX100/readme.txt b/portable/GCC/RX100/readme.txt
index 9e89a09..8dbc983 100644
--- a/portable/GCC/RX100/readme.txt
+++ b/portable/GCC/RX100/readme.txt
@@ -69,4 +69,3 @@
For more information about Renesas RX MCUs, please visit the following URL:
https://www.renesas.com/products/microcontrollers-microprocessors/rx.html
-
diff --git a/portable/GCC/RX200/port.c b/portable/GCC/RX200/port.c
index 9707774..0f3770a 100644
--- a/portable/GCC/RX200/port.c
+++ b/portable/GCC/RX200/port.c
@@ -1,436 +1,436 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the SH2A port.
- *----------------------------------------------------------*/
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Library includes. */
-#include "string.h"
-
-/* Hardware specifics. */
-#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
-
- #include "platform.h"
-
-#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
-
- #include "iodefine.h"
-
-#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
-
-/*-----------------------------------------------------------*/
-
-/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
-PSW is set with U and I set, and PM and IPL clear. */
-#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
-#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 )
-
-/* These macros allow a critical section to be added around the call to
-xTaskIncrementTick(), which is only ever called from interrupts at the kernel
-priority - ie a known priority. Therefore these local macros are a slight
-optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
-which would require the old IPL to be read first and stored in a local variable. */
-#define portMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
-#define portUNMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )
-
-/*-----------------------------------------------------------*/
-
-/*
- * Function to start the first task executing - written in asm code as direct
- * access to registers is required.
- */
-static void prvStartFirstTask( void ) __attribute__((naked));
-
-
-/*
- * Software interrupt handler. Performs the actual context switch (saving and
- * restoring of registers). Written in asm code as direct register access is
- * required.
- */
-#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
-
- R_BSP_PRAGMA_INTERRUPT( vSoftwareInterruptISR, VECT( ICU, SWINT ) )
- R_BSP_ATTRIB_INTERRUPT void vSoftwareInterruptISR( void ) __attribute__( ( naked ) );
-
-#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
-
- void vSoftwareInterruptISR( void ) __attribute__( ( naked ) );
-
-#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
-
-/*
- * The tick ISR handler. The peripheral used is configured by the application
- * via a hook/callback function.
- */
-#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
-
- R_BSP_PRAGMA_INTERRUPT( vTickISR, _VECT( configTICK_VECTOR ) )
- R_BSP_ATTRIB_INTERRUPT void vTickISR( void ); /* Do not add __attribute__( ( interrupt ) ). */
-
-#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
-
- void vTickISR( void ) __attribute__( ( interrupt ) );
-
-#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
-
-/*-----------------------------------------------------------*/
-
-extern void *pxCurrentTCB;
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
- /* R0 is not included as it is the stack pointer. */
-
- *pxTopOfStack = 0x00;
- pxTopOfStack--;
- *pxTopOfStack = portINITIAL_PSW;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode;
-
- /* When debugging it can be useful if every register is set to a known
- value. Otherwise code space can be saved by just setting the registers
- that need to be set. */
- #ifdef USE_FULL_REGISTER_INITIALISATION
- {
- pxTopOfStack--;
- *pxTopOfStack = 0xffffffff; /* r15. */
- pxTopOfStack--;
- *pxTopOfStack = 0xeeeeeeee;
- pxTopOfStack--;
- *pxTopOfStack = 0xdddddddd;
- pxTopOfStack--;
- *pxTopOfStack = 0xcccccccc;
- pxTopOfStack--;
- *pxTopOfStack = 0xbbbbbbbb;
- pxTopOfStack--;
- *pxTopOfStack = 0xaaaaaaaa;
- pxTopOfStack--;
- *pxTopOfStack = 0x99999999;
- pxTopOfStack--;
- *pxTopOfStack = 0x88888888;
- pxTopOfStack--;
- *pxTopOfStack = 0x77777777;
- pxTopOfStack--;
- *pxTopOfStack = 0x66666666;
- pxTopOfStack--;
- *pxTopOfStack = 0x55555555;
- pxTopOfStack--;
- *pxTopOfStack = 0x44444444;
- pxTopOfStack--;
- *pxTopOfStack = 0x33333333;
- pxTopOfStack--;
- *pxTopOfStack = 0x22222222;
- pxTopOfStack--;
- }
- #else
- {
- pxTopOfStack -= 15;
- }
- #endif
-
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
- pxTopOfStack--;
- *pxTopOfStack = portINITIAL_FPSW;
- pxTopOfStack--;
- *pxTopOfStack = 0x11111111; /* Accumulator 0. */
- pxTopOfStack--;
- *pxTopOfStack = 0x22222222; /* Accumulator 0. */
- pxTopOfStack--;
- *pxTopOfStack = 0x33333333; /* Accumulator 0. */
- pxTopOfStack--;
- *pxTopOfStack = 0x44444444; /* Accumulator 1. */
- pxTopOfStack--;
- *pxTopOfStack = 0x55555555; /* Accumulator 1. */
- pxTopOfStack--;
- *pxTopOfStack = 0x66666666; /* Accumulator 1. */
-
- return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-extern void vApplicationSetupTimerInterrupt( void );
-
- /* Use pxCurrentTCB just so it does not get optimised away. */
- if( pxCurrentTCB != NULL )
- {
- /* Call an application function to set up the timer that will generate the
- tick interrupt. This way the application can decide which peripheral to
- use. A demo application is provided to show a suitable example. */
- vApplicationSetupTimerInterrupt();
-
- /* Enable the software interrupt. */
- _IEN( _ICU_SWINT ) = 1;
-
- /* Ensure the software interrupt is clear. */
- _IR( _ICU_SWINT ) = 0;
-
- /* Ensure the software interrupt is set to the kernel priority. */
- _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
-
- /* Start the first task. */
- prvStartFirstTask();
- }
-
- /* Should not get here. */
- return pdFAIL;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
- /* Not implemented in ports where there is nothing to return to.
- Artificially force an assert. */
- configASSERT( pxCurrentTCB == NULL );
-}
-/*-----------------------------------------------------------*/
-
-static void prvStartFirstTask( void )
-{
- __asm volatile
- (
- /* When starting the scheduler there is nothing that needs moving to the
- interrupt stack because the function is not called from an interrupt.
- Just ensure the current stack is the user stack. */
- "SETPSW U \n" \
-
- /* Obtain the location of the stack associated with which ever task
- pxCurrentTCB is currently pointing to. */
- "MOV.L #_pxCurrentTCB, R15 \n" \
- "MOV.L [R15], R15 \n" \
- "MOV.L [R15], R0 \n" \
-
- /* Restore the registers from the stack of the task pointed to by
- pxCurrentTCB. */
- "POP R15 \n" \
-
- /* Accumulator low 32 bits. */
- "MVTACLO R15, A0 \n" \
- "POP R15 \n" \
-
- /* Accumulator high 32 bits. */
- "MVTACHI R15, A0 \n" \
- "POP R15 \n" \
-
- /* Accumulator guard. */
- "MVTACGU R15, A0 \n" \
- "POP R15 \n" \
-
- /* Accumulator low 32 bits. */
- "MVTACLO R15, A1 \n" \
- "POP R15 \n" \
-
- /* Accumulator high 32 bits. */
- "MVTACHI R15, A1 \n" \
- "POP R15 \n" \
-
- /* Accumulator guard. */
- "MVTACGU R15, A1 \n" \
- "POP R15 \n" \
-
- /* Floating point status word. */
- "MVTC R15, FPSW \n" \
-
- /* R1 to R15 - R0 is not included as it is the SP. */
- "POPM R1-R15 \n" \
-
- /* This pops the remaining registers. */
- "RTE \n" \
- "NOP \n" \
- "NOP \n"
- );
-}
-/*-----------------------------------------------------------*/
-
-void vSoftwareInterruptISR( void )
-{
- __asm volatile
- (
- /* Re-enable interrupts. */
- "SETPSW I \n" \
-
- /* Move the data that was automatically pushed onto the interrupt stack when
- the interrupt occurred from the interrupt stack to the user stack.
-
- R15 is saved before it is clobbered. */
- "PUSH.L R15 \n" \
-
- /* Read the user stack pointer. */
- "MVFC USP, R15 \n" \
-
- /* Move the address down to the data being moved. */
- "SUB #12, R15 \n" \
- "MVTC R15, USP \n" \
-
- /* Copy the data across, R15, then PC, then PSW. */
- "MOV.L [ R0 ], [ R15 ] \n" \
- "MOV.L 4[ R0 ], 4[ R15 ] \n" \
- "MOV.L 8[ R0 ], 8[ R15 ] \n" \
-
- /* Move the interrupt stack pointer to its new correct position. */
- "ADD #12, R0 \n" \
-
- /* All the rest of the registers are saved directly to the user stack. */
- "SETPSW U \n" \
-
- /* Save the rest of the general registers (R15 has been saved already). */
- "PUSHM R1-R14 \n" \
-
- /* Save the FPSW and accumulator. */
- "MVFC FPSW, R15 \n" \
- "PUSH.L R15 \n" \
- "MVFACGU #0, A1, R15 \n" \
- "PUSH.L R15 \n" \
- "MVFACHI #0, A1, R15 \n" \
- "PUSH.L R15 \n" \
- /* Low order word. */
- "MVFACLO #0, A1, R15 \n" \
- "PUSH.L R15 \n" \
- "MVFACGU #0, A0, R15 \n" \
- "PUSH.L R15 \n" \
- "MVFACHI #0, A0, R15 \n" \
- "PUSH.L R15 \n" \
- /* Low order word. */
- "MVFACLO #0, A0, R15 \n" \
- "PUSH.L R15 \n" \
-
- /* Save the stack pointer to the TCB. */
- "MOV.L #_pxCurrentTCB, R15 \n" \
- "MOV.L [ R15 ], R15 \n" \
- "MOV.L R0, [ R15 ] \n" \
-
- /* Ensure the interrupt mask is set to the syscall priority while the kernel
- structures are being accessed. */
- "MVTIPL %0 \n" \
-
- /* Select the next task to run. */
- "BSR.A _vTaskSwitchContext \n" \
-
- /* Reset the interrupt mask as no more data structure access is required. */
- "MVTIPL %1 \n" \
-
- /* Load the stack pointer of the task that is now selected as the Running
- state task from its TCB. */
- "MOV.L #_pxCurrentTCB,R15 \n" \
- "MOV.L [ R15 ], R15 \n" \
- "MOV.L [ R15 ], R0 \n" \
-
- /* Restore the context of the new task. The PSW (Program Status Word) and
- PC will be popped by the RTE instruction. */
- "POP R15 \n" \
-
- /* Accumulator low 32 bits. */
- "MVTACLO R15, A0 \n" \
- "POP R15 \n" \
-
- /* Accumulator high 32 bits. */
- "MVTACHI R15, A0 \n" \
- "POP R15 \n" \
-
- /* Accumulator guard. */
- "MVTACGU R15, A0 \n" \
- "POP R15 \n" \
-
- /* Accumulator low 32 bits. */
- "MVTACLO R15, A1 \n" \
- "POP R15 \n" \
-
- /* Accumulator high 32 bits. */
- "MVTACHI R15, A1 \n" \
- "POP R15 \n" \
-
- /* Accumulator guard. */
- "MVTACGU R15, A1 \n" \
- "POP R15 \n" \
- "MVTC R15, FPSW \n" \
- "POPM R1-R15 \n" \
- "RTE \n" \
- "NOP \n" \
- "NOP "
- :: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY)
- );
-}
-/*-----------------------------------------------------------*/
-
-void vTickISR( void )
-{
- /* Re-enabled interrupts. */
- __asm volatile( "SETPSW I" );
-
- /* Increment the tick, and perform any processing the new tick value
- necessitates. Ensure IPL is at the max syscall value first. */
- portMASK_INTERRUPTS_FROM_KERNEL_ISR();
- {
- if( xTaskIncrementTick() != pdFALSE )
- {
- taskYIELD();
- }
- }
- portUNMASK_INTERRUPTS_FROM_KERNEL_ISR();
-}
-/*-----------------------------------------------------------*/
-
-uint32_t ulPortGetIPL( void )
-{
- __asm volatile
- (
- "MVFC PSW, R1 \n" \
- "SHLR #24, R1 \n" \
- "RTS "
- );
-
- /* This will never get executed, but keeps the compiler from complaining. */
- return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortSetIPL( uint32_t ulNewIPL )
-{
- __asm volatile
- (
- "PUSH R5 \n" \
- "MVFC PSW, R5 \n" \
- "SHLL #24, R1 \n" \
- "AND #-0F000001H, R5 \n" \
- "OR R1, R5 \n" \
- "MVTC R5, PSW \n" \
- "POP R5 \n" \
- "RTS "
- );
-}
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the SH2A port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Library includes. */
+#include "string.h"
+
+/* Hardware specifics. */
+#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
+
+ #include "platform.h"
+
+#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+ #include "iodefine.h"
+
+#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+/*-----------------------------------------------------------*/
+
+/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
+PSW is set with U and I set, and PM and IPL clear. */
+#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
+#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 )
+
+/* These macros allow a critical section to be added around the call to
+xTaskIncrementTick(), which is only ever called from interrupts at the kernel
+priority - ie a known priority. Therefore these local macros are a slight
+optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
+which would require the old IPL to be read first and stored in a local variable. */
+#define portMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+#define portUNMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Function to start the first task executing - written in asm code as direct
+ * access to registers is required.
+ */
+static void prvStartFirstTask( void ) __attribute__((naked));
+
+
+/*
+ * Software interrupt handler. Performs the actual context switch (saving and
+ * restoring of registers). Written in asm code as direct register access is
+ * required.
+ */
+#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
+
+ R_BSP_PRAGMA_INTERRUPT( vSoftwareInterruptISR, VECT( ICU, SWINT ) )
+ R_BSP_ATTRIB_INTERRUPT void vSoftwareInterruptISR( void ) __attribute__( ( naked ) );
+
+#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+ void vSoftwareInterruptISR( void ) __attribute__( ( naked ) );
+
+#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+/*
+ * The tick ISR handler. The peripheral used is configured by the application
+ * via a hook/callback function.
+ */
+#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
+
+ R_BSP_PRAGMA_INTERRUPT( vTickISR, _VECT( configTICK_VECTOR ) )
+ R_BSP_ATTRIB_INTERRUPT void vTickISR( void ); /* Do not add __attribute__( ( interrupt ) ). */
+
+#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+ void vTickISR( void ) __attribute__( ( interrupt ) );
+
+#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+/*-----------------------------------------------------------*/
+
+extern void *pxCurrentTCB;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+ /* R0 is not included as it is the stack pointer. */
+
+ *pxTopOfStack = 0x00;
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_PSW;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode;
+
+ /* When debugging it can be useful if every register is set to a known
+ value. Otherwise code space can be saved by just setting the registers
+ that need to be set. */
+ #ifdef USE_FULL_REGISTER_INITIALISATION
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = 0xffffffff; /* r15. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0xeeeeeeee;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xdddddddd;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xcccccccc;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xbbbbbbbb;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xaaaaaaaa;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x99999999;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x88888888;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x77777777;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x66666666;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x55555555;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x44444444;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x33333333;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x22222222;
+ pxTopOfStack--;
+ }
+ #else
+ {
+ pxTopOfStack -= 15;
+ }
+ #endif
+
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_FPSW;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x11111111; /* Accumulator 0. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x22222222; /* Accumulator 0. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x33333333; /* Accumulator 0. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x44444444; /* Accumulator 1. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x55555555; /* Accumulator 1. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x66666666; /* Accumulator 1. */
+
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vApplicationSetupTimerInterrupt( void );
+
+ /* Use pxCurrentTCB just so it does not get optimised away. */
+ if( pxCurrentTCB != NULL )
+ {
+ /* Call an application function to set up the timer that will generate the
+ tick interrupt. This way the application can decide which peripheral to
+ use. A demo application is provided to show a suitable example. */
+ vApplicationSetupTimerInterrupt();
+
+ /* Enable the software interrupt. */
+ _IEN( _ICU_SWINT ) = 1;
+
+ /* Ensure the software interrupt is clear. */
+ _IR( _ICU_SWINT ) = 0;
+
+ /* Ensure the software interrupt is set to the kernel priority. */
+ _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
+
+ /* Start the first task. */
+ prvStartFirstTask();
+ }
+
+ /* Should not get here. */
+ return pdFAIL;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+ /* Not implemented in ports where there is nothing to return to.
+ Artificially force an assert. */
+ configASSERT( pxCurrentTCB == NULL );
+}
+/*-----------------------------------------------------------*/
+
+static void prvStartFirstTask( void )
+{
+ __asm volatile
+ (
+ /* When starting the scheduler there is nothing that needs moving to the
+ interrupt stack because the function is not called from an interrupt.
+ Just ensure the current stack is the user stack. */
+ "SETPSW U \n" \
+
+ /* Obtain the location of the stack associated with which ever task
+ pxCurrentTCB is currently pointing to. */
+ "MOV.L #_pxCurrentTCB, R15 \n" \
+ "MOV.L [R15], R15 \n" \
+ "MOV.L [R15], R0 \n" \
+
+ /* Restore the registers from the stack of the task pointed to by
+ pxCurrentTCB. */
+ "POP R15 \n" \
+
+ /* Accumulator low 32 bits. */
+ "MVTACLO R15, A0 \n" \
+ "POP R15 \n" \
+
+ /* Accumulator high 32 bits. */
+ "MVTACHI R15, A0 \n" \
+ "POP R15 \n" \
+
+ /* Accumulator guard. */
+ "MVTACGU R15, A0 \n" \
+ "POP R15 \n" \
+
+ /* Accumulator low 32 bits. */
+ "MVTACLO R15, A1 \n" \
+ "POP R15 \n" \
+
+ /* Accumulator high 32 bits. */
+ "MVTACHI R15, A1 \n" \
+ "POP R15 \n" \
+
+ /* Accumulator guard. */
+ "MVTACGU R15, A1 \n" \
+ "POP R15 \n" \
+
+ /* Floating point status word. */
+ "MVTC R15, FPSW \n" \
+
+ /* R1 to R15 - R0 is not included as it is the SP. */
+ "POPM R1-R15 \n" \
+
+ /* This pops the remaining registers. */
+ "RTE \n" \
+ "NOP \n" \
+ "NOP \n"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vSoftwareInterruptISR( void )
+{
+ __asm volatile
+ (
+ /* Re-enable interrupts. */
+ "SETPSW I \n" \
+
+ /* Move the data that was automatically pushed onto the interrupt stack when
+ the interrupt occurred from the interrupt stack to the user stack.
+
+ R15 is saved before it is clobbered. */
+ "PUSH.L R15 \n" \
+
+ /* Read the user stack pointer. */
+ "MVFC USP, R15 \n" \
+
+ /* Move the address down to the data being moved. */
+ "SUB #12, R15 \n" \
+ "MVTC R15, USP \n" \
+
+ /* Copy the data across, R15, then PC, then PSW. */
+ "MOV.L [ R0 ], [ R15 ] \n" \
+ "MOV.L 4[ R0 ], 4[ R15 ] \n" \
+ "MOV.L 8[ R0 ], 8[ R15 ] \n" \
+
+ /* Move the interrupt stack pointer to its new correct position. */
+ "ADD #12, R0 \n" \
+
+ /* All the rest of the registers are saved directly to the user stack. */
+ "SETPSW U \n" \
+
+ /* Save the rest of the general registers (R15 has been saved already). */
+ "PUSHM R1-R14 \n" \
+
+ /* Save the FPSW and accumulator. */
+ "MVFC FPSW, R15 \n" \
+ "PUSH.L R15 \n" \
+ "MVFACGU #0, A1, R15 \n" \
+ "PUSH.L R15 \n" \
+ "MVFACHI #0, A1, R15 \n" \
+ "PUSH.L R15 \n" \
+ /* Low order word. */
+ "MVFACLO #0, A1, R15 \n" \
+ "PUSH.L R15 \n" \
+ "MVFACGU #0, A0, R15 \n" \
+ "PUSH.L R15 \n" \
+ "MVFACHI #0, A0, R15 \n" \
+ "PUSH.L R15 \n" \
+ /* Low order word. */
+ "MVFACLO #0, A0, R15 \n" \
+ "PUSH.L R15 \n" \
+
+ /* Save the stack pointer to the TCB. */
+ "MOV.L #_pxCurrentTCB, R15 \n" \
+ "MOV.L [ R15 ], R15 \n" \
+ "MOV.L R0, [ R15 ] \n" \
+
+ /* Ensure the interrupt mask is set to the syscall priority while the kernel
+ structures are being accessed. */
+ "MVTIPL %0 \n" \
+
+ /* Select the next task to run. */
+ "BSR.A _vTaskSwitchContext \n" \
+
+ /* Reset the interrupt mask as no more data structure access is required. */
+ "MVTIPL %1 \n" \
+
+ /* Load the stack pointer of the task that is now selected as the Running
+ state task from its TCB. */
+ "MOV.L #_pxCurrentTCB,R15 \n" \
+ "MOV.L [ R15 ], R15 \n" \
+ "MOV.L [ R15 ], R0 \n" \
+
+ /* Restore the context of the new task. The PSW (Program Status Word) and
+ PC will be popped by the RTE instruction. */
+ "POP R15 \n" \
+
+ /* Accumulator low 32 bits. */
+ "MVTACLO R15, A0 \n" \
+ "POP R15 \n" \
+
+ /* Accumulator high 32 bits. */
+ "MVTACHI R15, A0 \n" \
+ "POP R15 \n" \
+
+ /* Accumulator guard. */
+ "MVTACGU R15, A0 \n" \
+ "POP R15 \n" \
+
+ /* Accumulator low 32 bits. */
+ "MVTACLO R15, A1 \n" \
+ "POP R15 \n" \
+
+ /* Accumulator high 32 bits. */
+ "MVTACHI R15, A1 \n" \
+ "POP R15 \n" \
+
+ /* Accumulator guard. */
+ "MVTACGU R15, A1 \n" \
+ "POP R15 \n" \
+ "MVTC R15, FPSW \n" \
+ "POPM R1-R15 \n" \
+ "RTE \n" \
+ "NOP \n" \
+ "NOP "
+ :: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY)
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vTickISR( void )
+{
+ /* Re-enabled interrupts. */
+ __asm volatile( "SETPSW I" );
+
+ /* Increment the tick, and perform any processing the new tick value
+ necessitates. Ensure IPL is at the max syscall value first. */
+ portMASK_INTERRUPTS_FROM_KERNEL_ISR();
+ {
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ taskYIELD();
+ }
+ }
+ portUNMASK_INTERRUPTS_FROM_KERNEL_ISR();
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulPortGetIPL( void )
+{
+ __asm volatile
+ (
+ "MVFC PSW, R1 \n" \
+ "SHLR #24, R1 \n" \
+ "RTS "
+ );
+
+ /* This will never get executed, but keeps the compiler from complaining. */
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortSetIPL( uint32_t ulNewIPL )
+{
+ __asm volatile
+ (
+ "PUSH R5 \n" \
+ "MVFC PSW, R5 \n" \
+ "SHLL #24, R1 \n" \
+ "AND #-0F000001H, R5 \n" \
+ "OR R1, R5 \n" \
+ "MVTC R5, PSW \n" \
+ "POP R5 \n" \
+ "RTS "
+ );
+}
diff --git a/portable/GCC/RX200/portmacro.h b/portable/GCC/RX200/portmacro.h
index cb697a7..7c3fefc 100644
--- a/portable/GCC/RX200/portmacro.h
+++ b/portable/GCC/RX200/portmacro.h
@@ -1,145 +1,144 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* When the FIT configurator or the Smart Configurator is used, platform.h has to be
- * used. */
-#ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H
- #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0
-#endif
-
-/* Type definitions - these are a bit legacy and not really used now, other than
-portSTACK_TYPE and portBASE_TYPE. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT short
-#define portSTACK_TYPE uint32_t
-#define portBASE_TYPE long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
-#else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
- /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */
-#define portSTACK_GROWTH -1
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP() __asm volatile( "NOP" )
-
-/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;"
-where portITU_SWINTR is the location of the software interrupt register
-(0x000872E0). Don't rely on the assembler to select a register, so instead
-save and restore clobbered registers manually. */
-#define portYIELD() \
- __asm volatile \
- ( \
- "PUSH.L R10 \n" \
- "MOV.L #0x872E0, R10 \n" \
- "MOV.B #0x1, [R10] \n" \
- "MOV.L [R10], R10 \n" \
- "POP R10 \n" \
- )
-
-#define portYIELD_FROM_ISR( x ) if( x != pdFALSE ) portYIELD()
-
-/* These macros should not be called directly, but through the
-taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is
-performed if configASSERT() is defined to ensure an assertion handler does not
-inadvertently attempt to lower the IPL when the call to assert was triggered
-because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
-when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API
-functions are those that end in FromISR. FreeRTOS maintains a separate
-interrupt API to ensure API function and interrupt entry is as fast and as
-simple as possible. */
-#define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0" )
-#ifdef configASSERT
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
- #define portDISABLE_INTERRUPTS() if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
-#else
- #define portDISABLE_INTERRUPTS() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
-#endif
-
-/* Critical nesting counts are stored in the TCB. */
-#define portCRITICAL_NESTING_IN_TCB ( 1 )
-
-/* The critical nesting functions defined within tasks.c. */
-extern void vTaskEnterCritical( void );
-extern void vTaskExitCritical( void );
-#define portENTER_CRITICAL() vTaskEnterCritical()
-#define portEXIT_CRITICAL() vTaskExitCritical()
-
-/* As this port allows interrupt nesting... */
-uint32_t ulPortGetIPL( void ) __attribute__((naked));
-void vPortSetIPL( uint32_t ulNewIPL ) __attribute__((naked));
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus )
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* When the FIT configurator or the Smart Configurator is used, platform.h has to be
+ * used. */
+#ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H
+ #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0
+#endif
+
+/* Type definitions - these are a bit legacy and not really used now, other than
+portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */
+#define portSTACK_GROWTH -1
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP() __asm volatile( "NOP" )
+
+/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;"
+where portITU_SWINTR is the location of the software interrupt register
+(0x000872E0). Don't rely on the assembler to select a register, so instead
+save and restore clobbered registers manually. */
+#define portYIELD() \
+ __asm volatile \
+ ( \
+ "PUSH.L R10 \n" \
+ "MOV.L #0x872E0, R10 \n" \
+ "MOV.B #0x1, [R10] \n" \
+ "MOV.L [R10], R10 \n" \
+ "POP R10 \n" \
+ )
+
+#define portYIELD_FROM_ISR( x ) if( x != pdFALSE ) portYIELD()
+
+/* These macros should not be called directly, but through the
+taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is
+performed if configASSERT() is defined to ensure an assertion handler does not
+inadvertently attempt to lower the IPL when the call to assert was triggered
+because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
+when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API
+functions are those that end in FromISR. FreeRTOS maintains a separate
+interrupt API to ensure API function and interrupt entry is as fast and as
+simple as possible. */
+#define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0" )
+#ifdef configASSERT
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+ #define portDISABLE_INTERRUPTS() if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+#else
+ #define portDISABLE_INTERRUPTS() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+#endif
+
+/* Critical nesting counts are stored in the TCB. */
+#define portCRITICAL_NESTING_IN_TCB ( 1 )
+
+/* The critical nesting functions defined within tasks.c. */
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL() vTaskEnterCritical()
+#define portEXIT_CRITICAL() vTaskExitCritical()
+
+/* As this port allows interrupt nesting... */
+uint32_t ulPortGetIPL( void ) __attribute__((naked));
+void vPortSetIPL( uint32_t ulNewIPL ) __attribute__((naked));
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/portable/GCC/RX600/port.c b/portable/GCC/RX600/port.c
index afe1a71..0bc9968 100644
--- a/portable/GCC/RX600/port.c
+++ b/portable/GCC/RX600/port.c
@@ -1,389 +1,389 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the SH2A port.
- *----------------------------------------------------------*/
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Library includes. */
-#include "string.h"
-
-/* Hardware specifics. */
-#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
-
- #include "platform.h"
-
-#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
-
- #include "iodefine.h"
-
-#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
-
-
-/*-----------------------------------------------------------*/
-
-/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
-PSW is set with U and I set, and PM and IPL clear. */
-#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
-#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 )
-
-/* These macros allow a critical section to be added around the call to
-xTaskIncrementTick(), which is only ever called from interrupts at the kernel
-priority - ie a known priority. Therefore these local macros are a slight
-optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
-which would require the old IPL to be read first and stored in a local variable. */
-#define portDISABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
-#define portENABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )
-
-/*-----------------------------------------------------------*/
-
-/*
- * Function to start the first task executing - written in asm code as direct
- * access to registers is required.
- */
-static void prvStartFirstTask( void ) __attribute__((naked));
-/*
- * Software interrupt handler. Performs the actual context switch (saving and
- * restoring of registers). Written in asm code as direct register access is
- * required.
- */
-#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
-
- R_BSP_PRAGMA_INTERRUPT( vSoftwareInterruptISR, VECT( ICU, SWINT ) )
- R_BSP_ATTRIB_INTERRUPT void vSoftwareInterruptISR( void ) __attribute__( ( naked ) );
-
-#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
-
- void vSoftwareInterruptISR( void ) __attribute__( ( naked ) );
-
-#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
-
-/*
- * The tick ISR handler. The peripheral used is configured by the application
- * via a hook/callback function.
- */
-#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
-
- R_BSP_PRAGMA_INTERRUPT( vTickISR, _VECT( configTICK_VECTOR ) )
- R_BSP_ATTRIB_INTERRUPT void vTickISR( void ); /* Do not add __attribute__( ( interrupt ) ). */
-
-#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
-
- void vTickISR( void ) __attribute__( ( interrupt ) );
-
-#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
-
-/*-----------------------------------------------------------*/
-
-extern void *pxCurrentTCB;
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
- /* R0 is not included as it is the stack pointer. */
-
- *pxTopOfStack = 0x00;
- pxTopOfStack--;
- *pxTopOfStack = portINITIAL_PSW;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode;
-
- /* When debugging it can be useful if every register is set to a known
- value. Otherwise code space can be saved by just setting the registers
- that need to be set. */
- #ifdef USE_FULL_REGISTER_INITIALISATION
- {
- pxTopOfStack--;
- *pxTopOfStack = 0xffffffff; /* r15. */
- pxTopOfStack--;
- *pxTopOfStack = 0xeeeeeeee;
- pxTopOfStack--;
- *pxTopOfStack = 0xdddddddd;
- pxTopOfStack--;
- *pxTopOfStack = 0xcccccccc;
- pxTopOfStack--;
- *pxTopOfStack = 0xbbbbbbbb;
- pxTopOfStack--;
- *pxTopOfStack = 0xaaaaaaaa;
- pxTopOfStack--;
- *pxTopOfStack = 0x99999999;
- pxTopOfStack--;
- *pxTopOfStack = 0x88888888;
- pxTopOfStack--;
- *pxTopOfStack = 0x77777777;
- pxTopOfStack--;
- *pxTopOfStack = 0x66666666;
- pxTopOfStack--;
- *pxTopOfStack = 0x55555555;
- pxTopOfStack--;
- *pxTopOfStack = 0x44444444;
- pxTopOfStack--;
- *pxTopOfStack = 0x33333333;
- pxTopOfStack--;
- *pxTopOfStack = 0x22222222;
- pxTopOfStack--;
- }
- #else
- {
- pxTopOfStack -= 15;
- }
- #endif
-
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
- pxTopOfStack--;
- *pxTopOfStack = portINITIAL_FPSW;
- pxTopOfStack--;
- *pxTopOfStack = 0x12345678; /* Accumulator. */
- pxTopOfStack--;
- *pxTopOfStack = 0x87654321; /* Accumulator. */
-
- return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-extern void vApplicationSetupTimerInterrupt( void );
-
- /* Use pxCurrentTCB just so it does not get optimised away. */
- if( pxCurrentTCB != NULL )
- {
- /* Call an application function to set up the timer that will generate the
- tick interrupt. This way the application can decide which peripheral to
- use. A demo application is provided to show a suitable example. */
- vApplicationSetupTimerInterrupt();
-
- /* Enable the software interrupt. */
- _IEN( _ICU_SWINT ) = 1;
-
- /* Ensure the software interrupt is clear. */
- _IR( _ICU_SWINT ) = 0;
-
- /* Ensure the software interrupt is set to the kernel priority. */
- _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
-
- /* Start the first task. */
- prvStartFirstTask();
- }
-
- /* Should not get here. */
- return pdFAIL;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
- /* Not implemented in ports where there is nothing to return to.
- Artificially force an assert. */
- configASSERT( pxCurrentTCB == NULL );
-}
-/*-----------------------------------------------------------*/
-
-static void prvStartFirstTask( void )
-{
- __asm volatile
- (
- /* When starting the scheduler there is nothing that needs moving to the
- interrupt stack because the function is not called from an interrupt.
- Just ensure the current stack is the user stack. */
- "SETPSW U \n" \
-
- /* Obtain the location of the stack associated with which ever task
- pxCurrentTCB is currently pointing to. */
- "MOV.L #_pxCurrentTCB, R15 \n" \
- "MOV.L [R15], R15 \n" \
- "MOV.L [R15], R0 \n" \
-
- /* Restore the registers from the stack of the task pointed to by
- pxCurrentTCB. */
- "POP R15 \n" \
-
- /* Accumulator low 32 bits. */
- "MVTACLO R15 \n" \
- "POP R15 \n" \
-
- /* Accumulator high 32 bits. */
- "MVTACHI R15 \n" \
- "POP R15 \n" \
-
- /* Floating point status word. */
- "MVTC R15, FPSW \n" \
-
- /* R1 to R15 - R0 is not included as it is the SP. */
- "POPM R1-R15 \n" \
-
- /* This pops the remaining registers. */
- "RTE \n" \
- "NOP \n" \
- "NOP \n"
- );
-}
-/*-----------------------------------------------------------*/
-
-void vSoftwareInterruptISR( void )
-{
- __asm volatile
- (
- /* Re-enable interrupts. */
- "SETPSW I \n" \
-
- /* Move the data that was automatically pushed onto the interrupt stack when
- the interrupt occurred from the interrupt stack to the user stack.
-
- R15 is saved before it is clobbered. */
- "PUSH.L R15 \n" \
-
- /* Read the user stack pointer. */
- "MVFC USP, R15 \n" \
-
- /* Move the address down to the data being moved. */
- "SUB #12, R15 \n" \
- "MVTC R15, USP \n" \
-
- /* Copy the data across, R15, then PC, then PSW. */
- "MOV.L [ R0 ], [ R15 ] \n" \
- "MOV.L 4[ R0 ], 4[ R15 ] \n" \
- "MOV.L 8[ R0 ], 8[ R15 ] \n" \
-
- /* Move the interrupt stack pointer to its new correct position. */
- "ADD #12, R0 \n" \
-
- /* All the rest of the registers are saved directly to the user stack. */
- "SETPSW U \n" \
-
- /* Save the rest of the general registers (R15 has been saved already). */
- "PUSHM R1-R14 \n" \
-
- /* Save the FPSW and accumulator. */
- "MVFC FPSW, R15 \n" \
- "PUSH.L R15 \n" \
- "MVFACHI R15 \n" \
- "PUSH.L R15 \n" \
-
- /* Middle word. */
- "MVFACMI R15 \n" \
-
- /* Shifted left as it is restored to the low order word. */
- "SHLL #16, R15 \n" \
- "PUSH.L R15 \n" \
-
- /* Save the stack pointer to the TCB. */
- "MOV.L #_pxCurrentTCB, R15 \n" \
- "MOV.L [ R15 ], R15 \n" \
- "MOV.L R0, [ R15 ] \n" \
-
- /* Ensure the interrupt mask is set to the syscall priority while the kernel
- structures are being accessed. */
- "MVTIPL %0 \n" \
-
- /* Select the next task to run. */
- "BSR.A _vTaskSwitchContext \n" \
-
- /* Reset the interrupt mask as no more data structure access is required. */
- "MVTIPL %1 \n" \
-
- /* Load the stack pointer of the task that is now selected as the Running
- state task from its TCB. */
- "MOV.L #_pxCurrentTCB,R15 \n" \
- "MOV.L [ R15 ], R15 \n" \
- "MOV.L [ R15 ], R0 \n" \
-
- /* Restore the context of the new task. The PSW (Program Status Word) and
- PC will be popped by the RTE instruction. */
- "POP R15 \n" \
- "MVTACLO R15 \n" \
- "POP R15 \n" \
- "MVTACHI R15 \n" \
- "POP R15 \n" \
- "MVTC R15, FPSW \n" \
- "POPM R1-R15 \n" \
- "RTE \n" \
- "NOP \n" \
- "NOP "
- :: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY)
- );
-}
-/*-----------------------------------------------------------*/
-
-void vTickISR( void )
-{
- /* Re-enabled interrupts. */
- __asm volatile( "SETPSW I" );
-
- /* Increment the tick, and perform any processing the new tick value
- necessitates. Ensure IPL is at the max syscall value first. */
- portDISABLE_INTERRUPTS_FROM_KERNEL_ISR();
- {
- if( xTaskIncrementTick() != pdFALSE )
- {
- taskYIELD();
- }
- }
- portENABLE_INTERRUPTS_FROM_KERNEL_ISR();
-}
-/*-----------------------------------------------------------*/
-
-uint32_t ulPortGetIPL( void )
-{
- __asm volatile
- (
- "MVFC PSW, R1 \n" \
- "SHLR #24, R1 \n" \
- "RTS "
- );
-
- /* This will never get executed, but keeps the compiler from complaining. */
- return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortSetIPL( uint32_t ulNewIPL )
-{
- /* Avoid compiler warning about unreferenced parameter. */
- ( void ) ulNewIPL;
-
- __asm volatile
- (
- "PUSH R5 \n" \
- "MVFC PSW, R5 \n" \
- "SHLL #24, R1 \n" \
- "AND #-0F000001H, R5 \n" \
- "OR R1, R5 \n" \
- "MVTC R5, PSW \n" \
- "POP R5 \n" \
- "RTS "
- );
-}
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the SH2A port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Library includes. */
+#include "string.h"
+
+/* Hardware specifics. */
+#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
+
+ #include "platform.h"
+
+#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+ #include "iodefine.h"
+
+#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+
+/*-----------------------------------------------------------*/
+
+/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
+PSW is set with U and I set, and PM and IPL clear. */
+#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
+#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 )
+
+/* These macros allow a critical section to be added around the call to
+xTaskIncrementTick(), which is only ever called from interrupts at the kernel
+priority - ie a known priority. Therefore these local macros are a slight
+optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
+which would require the old IPL to be read first and stored in a local variable. */
+#define portDISABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+#define portENABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Function to start the first task executing - written in asm code as direct
+ * access to registers is required.
+ */
+static void prvStartFirstTask( void ) __attribute__((naked));
+/*
+ * Software interrupt handler. Performs the actual context switch (saving and
+ * restoring of registers). Written in asm code as direct register access is
+ * required.
+ */
+#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
+
+ R_BSP_PRAGMA_INTERRUPT( vSoftwareInterruptISR, VECT( ICU, SWINT ) )
+ R_BSP_ATTRIB_INTERRUPT void vSoftwareInterruptISR( void ) __attribute__( ( naked ) );
+
+#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+ void vSoftwareInterruptISR( void ) __attribute__( ( naked ) );
+
+#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+/*
+ * The tick ISR handler. The peripheral used is configured by the application
+ * via a hook/callback function.
+ */
+#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
+
+ R_BSP_PRAGMA_INTERRUPT( vTickISR, _VECT( configTICK_VECTOR ) )
+ R_BSP_ATTRIB_INTERRUPT void vTickISR( void ); /* Do not add __attribute__( ( interrupt ) ). */
+
+#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+ void vTickISR( void ) __attribute__( ( interrupt ) );
+
+#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+/*-----------------------------------------------------------*/
+
+extern void *pxCurrentTCB;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+ /* R0 is not included as it is the stack pointer. */
+
+ *pxTopOfStack = 0x00;
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_PSW;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode;
+
+ /* When debugging it can be useful if every register is set to a known
+ value. Otherwise code space can be saved by just setting the registers
+ that need to be set. */
+ #ifdef USE_FULL_REGISTER_INITIALISATION
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = 0xffffffff; /* r15. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0xeeeeeeee;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xdddddddd;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xcccccccc;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xbbbbbbbb;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xaaaaaaaa;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x99999999;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x88888888;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x77777777;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x66666666;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x55555555;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x44444444;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x33333333;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x22222222;
+ pxTopOfStack--;
+ }
+ #else
+ {
+ pxTopOfStack -= 15;
+ }
+ #endif
+
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_FPSW;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x12345678; /* Accumulator. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x87654321; /* Accumulator. */
+
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vApplicationSetupTimerInterrupt( void );
+
+ /* Use pxCurrentTCB just so it does not get optimised away. */
+ if( pxCurrentTCB != NULL )
+ {
+ /* Call an application function to set up the timer that will generate the
+ tick interrupt. This way the application can decide which peripheral to
+ use. A demo application is provided to show a suitable example. */
+ vApplicationSetupTimerInterrupt();
+
+ /* Enable the software interrupt. */
+ _IEN( _ICU_SWINT ) = 1;
+
+ /* Ensure the software interrupt is clear. */
+ _IR( _ICU_SWINT ) = 0;
+
+ /* Ensure the software interrupt is set to the kernel priority. */
+ _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
+
+ /* Start the first task. */
+ prvStartFirstTask();
+ }
+
+ /* Should not get here. */
+ return pdFAIL;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+ /* Not implemented in ports where there is nothing to return to.
+ Artificially force an assert. */
+ configASSERT( pxCurrentTCB == NULL );
+}
+/*-----------------------------------------------------------*/
+
+static void prvStartFirstTask( void )
+{
+ __asm volatile
+ (
+ /* When starting the scheduler there is nothing that needs moving to the
+ interrupt stack because the function is not called from an interrupt.
+ Just ensure the current stack is the user stack. */
+ "SETPSW U \n" \
+
+ /* Obtain the location of the stack associated with which ever task
+ pxCurrentTCB is currently pointing to. */
+ "MOV.L #_pxCurrentTCB, R15 \n" \
+ "MOV.L [R15], R15 \n" \
+ "MOV.L [R15], R0 \n" \
+
+ /* Restore the registers from the stack of the task pointed to by
+ pxCurrentTCB. */
+ "POP R15 \n" \
+
+ /* Accumulator low 32 bits. */
+ "MVTACLO R15 \n" \
+ "POP R15 \n" \
+
+ /* Accumulator high 32 bits. */
+ "MVTACHI R15 \n" \
+ "POP R15 \n" \
+
+ /* Floating point status word. */
+ "MVTC R15, FPSW \n" \
+
+ /* R1 to R15 - R0 is not included as it is the SP. */
+ "POPM R1-R15 \n" \
+
+ /* This pops the remaining registers. */
+ "RTE \n" \
+ "NOP \n" \
+ "NOP \n"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vSoftwareInterruptISR( void )
+{
+ __asm volatile
+ (
+ /* Re-enable interrupts. */
+ "SETPSW I \n" \
+
+ /* Move the data that was automatically pushed onto the interrupt stack when
+ the interrupt occurred from the interrupt stack to the user stack.
+
+ R15 is saved before it is clobbered. */
+ "PUSH.L R15 \n" \
+
+ /* Read the user stack pointer. */
+ "MVFC USP, R15 \n" \
+
+ /* Move the address down to the data being moved. */
+ "SUB #12, R15 \n" \
+ "MVTC R15, USP \n" \
+
+ /* Copy the data across, R15, then PC, then PSW. */
+ "MOV.L [ R0 ], [ R15 ] \n" \
+ "MOV.L 4[ R0 ], 4[ R15 ] \n" \
+ "MOV.L 8[ R0 ], 8[ R15 ] \n" \
+
+ /* Move the interrupt stack pointer to its new correct position. */
+ "ADD #12, R0 \n" \
+
+ /* All the rest of the registers are saved directly to the user stack. */
+ "SETPSW U \n" \
+
+ /* Save the rest of the general registers (R15 has been saved already). */
+ "PUSHM R1-R14 \n" \
+
+ /* Save the FPSW and accumulator. */
+ "MVFC FPSW, R15 \n" \
+ "PUSH.L R15 \n" \
+ "MVFACHI R15 \n" \
+ "PUSH.L R15 \n" \
+
+ /* Middle word. */
+ "MVFACMI R15 \n" \
+
+ /* Shifted left as it is restored to the low order word. */
+ "SHLL #16, R15 \n" \
+ "PUSH.L R15 \n" \
+
+ /* Save the stack pointer to the TCB. */
+ "MOV.L #_pxCurrentTCB, R15 \n" \
+ "MOV.L [ R15 ], R15 \n" \
+ "MOV.L R0, [ R15 ] \n" \
+
+ /* Ensure the interrupt mask is set to the syscall priority while the kernel
+ structures are being accessed. */
+ "MVTIPL %0 \n" \
+
+ /* Select the next task to run. */
+ "BSR.A _vTaskSwitchContext \n" \
+
+ /* Reset the interrupt mask as no more data structure access is required. */
+ "MVTIPL %1 \n" \
+
+ /* Load the stack pointer of the task that is now selected as the Running
+ state task from its TCB. */
+ "MOV.L #_pxCurrentTCB,R15 \n" \
+ "MOV.L [ R15 ], R15 \n" \
+ "MOV.L [ R15 ], R0 \n" \
+
+ /* Restore the context of the new task. The PSW (Program Status Word) and
+ PC will be popped by the RTE instruction. */
+ "POP R15 \n" \
+ "MVTACLO R15 \n" \
+ "POP R15 \n" \
+ "MVTACHI R15 \n" \
+ "POP R15 \n" \
+ "MVTC R15, FPSW \n" \
+ "POPM R1-R15 \n" \
+ "RTE \n" \
+ "NOP \n" \
+ "NOP "
+ :: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY)
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vTickISR( void )
+{
+ /* Re-enabled interrupts. */
+ __asm volatile( "SETPSW I" );
+
+ /* Increment the tick, and perform any processing the new tick value
+ necessitates. Ensure IPL is at the max syscall value first. */
+ portDISABLE_INTERRUPTS_FROM_KERNEL_ISR();
+ {
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ taskYIELD();
+ }
+ }
+ portENABLE_INTERRUPTS_FROM_KERNEL_ISR();
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulPortGetIPL( void )
+{
+ __asm volatile
+ (
+ "MVFC PSW, R1 \n" \
+ "SHLR #24, R1 \n" \
+ "RTS "
+ );
+
+ /* This will never get executed, but keeps the compiler from complaining. */
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortSetIPL( uint32_t ulNewIPL )
+{
+ /* Avoid compiler warning about unreferenced parameter. */
+ ( void ) ulNewIPL;
+
+ __asm volatile
+ (
+ "PUSH R5 \n" \
+ "MVFC PSW, R5 \n" \
+ "SHLL #24, R1 \n" \
+ "AND #-0F000001H, R5 \n" \
+ "OR R1, R5 \n" \
+ "MVTC R5, PSW \n" \
+ "POP R5 \n" \
+ "RTS "
+ );
+}
diff --git a/portable/GCC/RX600/portmacro.h b/portable/GCC/RX600/portmacro.h
index 3a63cc3..5919edf 100644
--- a/portable/GCC/RX600/portmacro.h
+++ b/portable/GCC/RX600/portmacro.h
@@ -1,145 +1,144 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* When the FIT configurator or the Smart Configurator is used, platform.h has to be
- * used. */
-#ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H
- #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0
-#endif
-
-/* Type definitions - these are a bit legacy and not really used now, other than
-portSTACK_TYPE and portBASE_TYPE. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT short
-#define portSTACK_TYPE uint32_t
-#define portBASE_TYPE long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
-#else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
- /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */
-#define portSTACK_GROWTH -1
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP() __asm volatile( "NOP" )
-
-/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;"
-where portITU_SWINTR is the location of the software interrupt register
-(0x000872E0). Don't rely on the assembler to select a register, so instead
-save and restore clobbered registers manually. */
-#define portYIELD() \
- __asm volatile \
- ( \
- "PUSH.L R10 \n" \
- "MOV.L #0x872E0, R10 \n" \
- "MOV.B #0x1, [R10] \n" \
- "MOV.L [R10], R10 \n" \
- "POP R10 \n" \
- )
-
-#define portYIELD_FROM_ISR( x ) do { if( x != pdFALSE ) portYIELD(); } while( 0 )
-
-/* These macros should not be called directly, but through the
-taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is
-performed if configASSERT() is defined to ensure an assertion handler does not
-inadvertently attempt to lower the IPL when the call to assert was triggered
-because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
-when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API
-functions are those that end in FromISR. FreeRTOS maintains a separate
-interrupt API to ensure API function and interrupt entry is as fast and as
-simple as possible. */
-#define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0" )
-#ifdef configASSERT
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
- #define portDISABLE_INTERRUPTS() if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
-#else
- #define portDISABLE_INTERRUPTS() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
-#endif
-
-/* Critical nesting counts are stored in the TCB. */
-#define portCRITICAL_NESTING_IN_TCB ( 1 )
-
-/* The critical nesting functions defined within tasks.c. */
-extern void vTaskEnterCritical( void );
-extern void vTaskExitCritical( void );
-#define portENTER_CRITICAL() vTaskEnterCritical()
-#define portEXIT_CRITICAL() vTaskExitCritical()
-
-/* As this port allows interrupt nesting... */
-uint32_t ulPortGetIPL( void ) __attribute__((naked));
-void vPortSetIPL( uint32_t ulNewIPL ) __attribute__((naked));
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus )
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* When the FIT configurator or the Smart Configurator is used, platform.h has to be
+ * used. */
+#ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H
+ #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0
+#endif
+
+/* Type definitions - these are a bit legacy and not really used now, other than
+portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */
+#define portSTACK_GROWTH -1
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP() __asm volatile( "NOP" )
+
+/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;"
+where portITU_SWINTR is the location of the software interrupt register
+(0x000872E0). Don't rely on the assembler to select a register, so instead
+save and restore clobbered registers manually. */
+#define portYIELD() \
+ __asm volatile \
+ ( \
+ "PUSH.L R10 \n" \
+ "MOV.L #0x872E0, R10 \n" \
+ "MOV.B #0x1, [R10] \n" \
+ "MOV.L [R10], R10 \n" \
+ "POP R10 \n" \
+ )
+
+#define portYIELD_FROM_ISR( x ) do { if( x != pdFALSE ) portYIELD(); } while( 0 )
+
+/* These macros should not be called directly, but through the
+taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is
+performed if configASSERT() is defined to ensure an assertion handler does not
+inadvertently attempt to lower the IPL when the call to assert was triggered
+because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
+when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API
+functions are those that end in FromISR. FreeRTOS maintains a separate
+interrupt API to ensure API function and interrupt entry is as fast and as
+simple as possible. */
+#define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0" )
+#ifdef configASSERT
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+ #define portDISABLE_INTERRUPTS() if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+#else
+ #define portDISABLE_INTERRUPTS() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+#endif
+
+/* Critical nesting counts are stored in the TCB. */
+#define portCRITICAL_NESTING_IN_TCB ( 1 )
+
+/* The critical nesting functions defined within tasks.c. */
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL() vTaskEnterCritical()
+#define portEXIT_CRITICAL() vTaskExitCritical()
+
+/* As this port allows interrupt nesting... */
+uint32_t ulPortGetIPL( void ) __attribute__((naked));
+void vPortSetIPL( uint32_t ulNewIPL ) __attribute__((naked));
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/portable/GCC/RX600/readme.txt b/portable/GCC/RX600/readme.txt
index 9e89a09..8dbc983 100644
--- a/portable/GCC/RX600/readme.txt
+++ b/portable/GCC/RX600/readme.txt
@@ -69,4 +69,3 @@
For more information about Renesas RX MCUs, please visit the following URL:
https://www.renesas.com/products/microcontrollers-microprocessors/rx.html
-
diff --git a/portable/GCC/RX600v2/port.c b/portable/GCC/RX600v2/port.c
index 5527cf9..ca96d81 100644
--- a/portable/GCC/RX600v2/port.c
+++ b/portable/GCC/RX600v2/port.c
@@ -1,433 +1,433 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the SH2A port.
- *----------------------------------------------------------*/
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Library includes. */
-#include "string.h"
-
-/* Hardware specifics. */
-#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
-
- #include "platform.h"
-
-#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
-
- #include "iodefine.h"
-
-#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
-
-/*-----------------------------------------------------------*/
-
-/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
-PSW is set with U and I set, and PM and IPL clear. */
-#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
-#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 )
-
-/* These macros allow a critical section to be added around the call to
-xTaskIncrementTick(), which is only ever called from interrupts at the kernel
-priority - ie a known priority. Therefore these local macros are a slight
-optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
-which would require the old IPL to be read first and stored in a local variable. */
-#define portMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
-#define portUNMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )
-
-/*-----------------------------------------------------------*/
-
-/*
- * Function to start the first task executing - written in asm code as direct
- * access to registers is required.
- */
-static void prvStartFirstTask( void ) __attribute__((naked));
-
-/*
- * Software interrupt handler. Performs the actual context switch (saving and
- * restoring of registers). Written in asm code as direct register access is
- * required.
- */
-#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
-R_BSP_PRAGMA_INTERRUPT( vSoftwareInterruptISR, VECT( ICU, SWINT ) )
-R_BSP_ATTRIB_INTERRUPT void vSoftwareInterruptISR( void ) __attribute__( ( naked ) );
-#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
-void vSoftwareInterruptISR( void ) __attribute__((naked));
-#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
-
-/*
- * The tick ISR handler. The peripheral used is configured by the application
- * via a hook/callback function.
- */
-#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
-
- R_BSP_PRAGMA_INTERRUPT( vTickISR, _VECT( configTICK_VECTOR ) )
- R_BSP_ATTRIB_INTERRUPT void vTickISR( void ); /* Do not add __attribute__( ( interrupt ) ). */
-
-#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
-
- void vTickISR( void ) __attribute__( ( interrupt ) );
-
-#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
-/*-----------------------------------------------------------*/
-
-extern void *pxCurrentTCB;
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
- /* R0 is not included as it is the stack pointer. */
-
- *pxTopOfStack = 0x00;
- pxTopOfStack--;
- *pxTopOfStack = portINITIAL_PSW;
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode;
-
- /* When debugging it can be useful if every register is set to a known
- value. Otherwise code space can be saved by just setting the registers
- that need to be set. */
- #ifdef USE_FULL_REGISTER_INITIALISATION
- {
- pxTopOfStack--;
- *pxTopOfStack = 0xffffffff; /* r15. */
- pxTopOfStack--;
- *pxTopOfStack = 0xeeeeeeee;
- pxTopOfStack--;
- *pxTopOfStack = 0xdddddddd;
- pxTopOfStack--;
- *pxTopOfStack = 0xcccccccc;
- pxTopOfStack--;
- *pxTopOfStack = 0xbbbbbbbb;
- pxTopOfStack--;
- *pxTopOfStack = 0xaaaaaaaa;
- pxTopOfStack--;
- *pxTopOfStack = 0x99999999;
- pxTopOfStack--;
- *pxTopOfStack = 0x88888888;
- pxTopOfStack--;
- *pxTopOfStack = 0x77777777;
- pxTopOfStack--;
- *pxTopOfStack = 0x66666666;
- pxTopOfStack--;
- *pxTopOfStack = 0x55555555;
- pxTopOfStack--;
- *pxTopOfStack = 0x44444444;
- pxTopOfStack--;
- *pxTopOfStack = 0x33333333;
- pxTopOfStack--;
- *pxTopOfStack = 0x22222222;
- pxTopOfStack--;
- }
- #else
- {
- pxTopOfStack -= 15;
- }
- #endif
-
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
- pxTopOfStack--;
- *pxTopOfStack = portINITIAL_FPSW;
- pxTopOfStack--;
- *pxTopOfStack = 0x11111111; /* Accumulator 0. */
- pxTopOfStack--;
- *pxTopOfStack = 0x22222222; /* Accumulator 0. */
- pxTopOfStack--;
- *pxTopOfStack = 0x33333333; /* Accumulator 0. */
- pxTopOfStack--;
- *pxTopOfStack = 0x44444444; /* Accumulator 1. */
- pxTopOfStack--;
- *pxTopOfStack = 0x55555555; /* Accumulator 1. */
- pxTopOfStack--;
- *pxTopOfStack = 0x66666666; /* Accumulator 1. */
-
- return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-extern void vApplicationSetupTimerInterrupt( void );
-
- /* Use pxCurrentTCB just so it does not get optimised away. */
- if( pxCurrentTCB != NULL )
- {
- /* Call an application function to set up the timer that will generate the
- tick interrupt. This way the application can decide which peripheral to
- use. A demo application is provided to show a suitable example. */
- vApplicationSetupTimerInterrupt();
-
- /* Enable the software interrupt. */
- _IEN( _ICU_SWINT ) = 1;
-
- /* Ensure the software interrupt is clear. */
- _IR( _ICU_SWINT ) = 0;
-
- /* Ensure the software interrupt is set to the kernel priority. */
- _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
-
- /* Start the first task. */
- prvStartFirstTask();
- }
-
- /* Should not get here. */
- return pdFAIL;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
- /* Not implemented in ports where there is nothing to return to.
- Artificially force an assert. */
- configASSERT( pxCurrentTCB == NULL );
-}
-/*-----------------------------------------------------------*/
-
-static void prvStartFirstTask( void )
-{
- __asm volatile
- (
- /* When starting the scheduler there is nothing that needs moving to the
- interrupt stack because the function is not called from an interrupt.
- Just ensure the current stack is the user stack. */
- "SETPSW U \n" \
-
- /* Obtain the location of the stack associated with which ever task
- pxCurrentTCB is currently pointing to. */
- "MOV.L #_pxCurrentTCB, R15 \n" \
- "MOV.L [R15], R15 \n" \
- "MOV.L [R15], R0 \n" \
-
- /* Restore the registers from the stack of the task pointed to by
- pxCurrentTCB. */
- "POP R15 \n" \
-
- /* Accumulator low 32 bits. */
- "MVTACLO R15, A0 \n" \
- "POP R15 \n" \
-
- /* Accumulator high 32 bits. */
- "MVTACHI R15, A0 \n" \
- "POP R15 \n" \
-
- /* Accumulator guard. */
- "MVTACGU R15, A0 \n" \
- "POP R15 \n" \
-
- /* Accumulator low 32 bits. */
- "MVTACLO R15, A1 \n" \
- "POP R15 \n" \
-
- /* Accumulator high 32 bits. */
- "MVTACHI R15, A1 \n" \
- "POP R15 \n" \
-
- /* Accumulator guard. */
- "MVTACGU R15, A1 \n" \
- "POP R15 \n" \
-
- /* Floating point status word. */
- "MVTC R15, FPSW \n" \
-
- /* R1 to R15 - R0 is not included as it is the SP. */
- "POPM R1-R15 \n" \
-
- /* This pops the remaining registers. */
- "RTE \n" \
- "NOP \n" \
- "NOP \n"
- );
-}
-/*-----------------------------------------------------------*/
-
-void vSoftwareInterruptISR( void )
-{
- __asm volatile
- (
- /* Re-enable interrupts. */
- "SETPSW I \n" \
-
- /* Move the data that was automatically pushed onto the interrupt stack when
- the interrupt occurred from the interrupt stack to the user stack.
-
- R15 is saved before it is clobbered. */
- "PUSH.L R15 \n" \
-
- /* Read the user stack pointer. */
- "MVFC USP, R15 \n" \
-
- /* Move the address down to the data being moved. */
- "SUB #12, R15 \n" \
- "MVTC R15, USP \n" \
-
- /* Copy the data across, R15, then PC, then PSW. */
- "MOV.L [ R0 ], [ R15 ] \n" \
- "MOV.L 4[ R0 ], 4[ R15 ] \n" \
- "MOV.L 8[ R0 ], 8[ R15 ] \n" \
-
- /* Move the interrupt stack pointer to its new correct position. */
- "ADD #12, R0 \n" \
-
- /* All the rest of the registers are saved directly to the user stack. */
- "SETPSW U \n" \
-
- /* Save the rest of the general registers (R15 has been saved already). */
- "PUSHM R1-R14 \n" \
-
- /* Save the FPSW and accumulator. */
- "MVFC FPSW, R15 \n" \
- "PUSH.L R15 \n" \
- "MVFACGU #0, A1, R15 \n" \
- "PUSH.L R15 \n" \
- "MVFACHI #0, A1, R15 \n" \
- "PUSH.L R15 \n" \
- /* Low order word. */
- "MVFACLO #0, A1, R15 \n" \
- "PUSH.L R15 \n" \
- "MVFACGU #0, A0, R15 \n" \
- "PUSH.L R15 \n" \
- "MVFACHI #0, A0, R15 \n" \
- "PUSH.L R15 \n" \
- /* Low order word. */
- "MVFACLO #0, A0, R15 \n" \
- "PUSH.L R15 \n" \
-
- /* Save the stack pointer to the TCB. */
- "MOV.L #_pxCurrentTCB, R15 \n" \
- "MOV.L [ R15 ], R15 \n" \
- "MOV.L R0, [ R15 ] \n" \
-
- /* Ensure the interrupt mask is set to the syscall priority while the kernel
- structures are being accessed. */
- "MVTIPL %0 \n" \
-
- /* Select the next task to run. */
- "BSR.A _vTaskSwitchContext \n" \
-
- /* Reset the interrupt mask as no more data structure access is required. */
- "MVTIPL %1 \n" \
-
- /* Load the stack pointer of the task that is now selected as the Running
- state task from its TCB. */
- "MOV.L #_pxCurrentTCB,R15 \n" \
- "MOV.L [ R15 ], R15 \n" \
- "MOV.L [ R15 ], R0 \n" \
-
- /* Restore the context of the new task. The PSW (Program Status Word) and
- PC will be popped by the RTE instruction. */
- "POP R15 \n" \
-
- /* Accumulator low 32 bits. */
- "MVTACLO R15, A0 \n" \
- "POP R15 \n" \
-
- /* Accumulator high 32 bits. */
- "MVTACHI R15, A0 \n" \
- "POP R15 \n" \
-
- /* Accumulator guard. */
- "MVTACGU R15, A0 \n" \
- "POP R15 \n" \
-
- /* Accumulator low 32 bits. */
- "MVTACLO R15, A1 \n" \
- "POP R15 \n" \
-
- /* Accumulator high 32 bits. */
- "MVTACHI R15, A1 \n" \
- "POP R15 \n" \
-
- /* Accumulator guard. */
- "MVTACGU R15, A1 \n" \
- "POP R15 \n" \
- "MVTC R15, FPSW \n" \
- "POPM R1-R15 \n" \
- "RTE \n" \
- "NOP \n" \
- "NOP "
- :: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY)
- );
-}
-/*-----------------------------------------------------------*/
-
-void vTickISR( void )
-{
- /* Re-enabled interrupts. */
- __asm volatile( "SETPSW I" );
-
- /* Increment the tick, and perform any processing the new tick value
- necessitates. Ensure IPL is at the max syscall value first. */
- portMASK_INTERRUPTS_FROM_KERNEL_ISR();
- {
- if( xTaskIncrementTick() != pdFALSE )
- {
- taskYIELD();
- }
- }
- portUNMASK_INTERRUPTS_FROM_KERNEL_ISR();
-}
-/*-----------------------------------------------------------*/
-
-uint32_t ulPortGetIPL( void )
-{
- __asm volatile
- (
- "MVFC PSW, R1 \n" \
- "SHLR #24, R1 \n" \
- "RTS "
- );
-
- /* This will never get executed, but keeps the compiler from complaining. */
- return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortSetIPL( uint32_t ulNewIPL )
-{
- /* Avoid compiler warning about unreferenced parameter. */
- ( void ) ulNewIPL;
-
- __asm volatile
- (
- "PUSH R5 \n" \
- "MVFC PSW, R5 \n" \
- "SHLL #24, R1 \n" \
- "AND #-0F000001H, R5 \n" \
- "OR R1, R5 \n" \
- "MVTC R5, PSW \n" \
- "POP R5 \n" \
- "RTS "
- );
-}
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the SH2A port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Library includes. */
+#include "string.h"
+
+/* Hardware specifics. */
+#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
+
+ #include "platform.h"
+
+#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+ #include "iodefine.h"
+
+#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+/*-----------------------------------------------------------*/
+
+/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
+PSW is set with U and I set, and PM and IPL clear. */
+#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
+#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 )
+
+/* These macros allow a critical section to be added around the call to
+xTaskIncrementTick(), which is only ever called from interrupts at the kernel
+priority - ie a known priority. Therefore these local macros are a slight
+optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
+which would require the old IPL to be read first and stored in a local variable. */
+#define portMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+#define portUNMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Function to start the first task executing - written in asm code as direct
+ * access to registers is required.
+ */
+static void prvStartFirstTask( void ) __attribute__((naked));
+
+/*
+ * Software interrupt handler. Performs the actual context switch (saving and
+ * restoring of registers). Written in asm code as direct register access is
+ * required.
+ */
+#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
+R_BSP_PRAGMA_INTERRUPT( vSoftwareInterruptISR, VECT( ICU, SWINT ) )
+R_BSP_ATTRIB_INTERRUPT void vSoftwareInterruptISR( void ) __attribute__( ( naked ) );
+#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+void vSoftwareInterruptISR( void ) __attribute__((naked));
+#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+/*
+ * The tick ISR handler. The peripheral used is configured by the application
+ * via a hook/callback function.
+ */
+#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
+
+ R_BSP_PRAGMA_INTERRUPT( vTickISR, _VECT( configTICK_VECTOR ) )
+ R_BSP_ATTRIB_INTERRUPT void vTickISR( void ); /* Do not add __attribute__( ( interrupt ) ). */
+
+#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+ void vTickISR( void ) __attribute__( ( interrupt ) );
+
+#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+/*-----------------------------------------------------------*/
+
+extern void *pxCurrentTCB;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+ /* R0 is not included as it is the stack pointer. */
+
+ *pxTopOfStack = 0x00;
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_PSW;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode;
+
+ /* When debugging it can be useful if every register is set to a known
+ value. Otherwise code space can be saved by just setting the registers
+ that need to be set. */
+ #ifdef USE_FULL_REGISTER_INITIALISATION
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = 0xffffffff; /* r15. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0xeeeeeeee;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xdddddddd;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xcccccccc;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xbbbbbbbb;
+ pxTopOfStack--;
+ *pxTopOfStack = 0xaaaaaaaa;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x99999999;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x88888888;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x77777777;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x66666666;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x55555555;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x44444444;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x33333333;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x22222222;
+ pxTopOfStack--;
+ }
+ #else
+ {
+ pxTopOfStack -= 15;
+ }
+ #endif
+
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_FPSW;
+ pxTopOfStack--;
+ *pxTopOfStack = 0x11111111; /* Accumulator 0. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x22222222; /* Accumulator 0. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x33333333; /* Accumulator 0. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x44444444; /* Accumulator 1. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x55555555; /* Accumulator 1. */
+ pxTopOfStack--;
+ *pxTopOfStack = 0x66666666; /* Accumulator 1. */
+
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vApplicationSetupTimerInterrupt( void );
+
+ /* Use pxCurrentTCB just so it does not get optimised away. */
+ if( pxCurrentTCB != NULL )
+ {
+ /* Call an application function to set up the timer that will generate the
+ tick interrupt. This way the application can decide which peripheral to
+ use. A demo application is provided to show a suitable example. */
+ vApplicationSetupTimerInterrupt();
+
+ /* Enable the software interrupt. */
+ _IEN( _ICU_SWINT ) = 1;
+
+ /* Ensure the software interrupt is clear. */
+ _IR( _ICU_SWINT ) = 0;
+
+ /* Ensure the software interrupt is set to the kernel priority. */
+ _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
+
+ /* Start the first task. */
+ prvStartFirstTask();
+ }
+
+ /* Should not get here. */
+ return pdFAIL;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+ /* Not implemented in ports where there is nothing to return to.
+ Artificially force an assert. */
+ configASSERT( pxCurrentTCB == NULL );
+}
+/*-----------------------------------------------------------*/
+
+static void prvStartFirstTask( void )
+{
+ __asm volatile
+ (
+ /* When starting the scheduler there is nothing that needs moving to the
+ interrupt stack because the function is not called from an interrupt.
+ Just ensure the current stack is the user stack. */
+ "SETPSW U \n" \
+
+ /* Obtain the location of the stack associated with which ever task
+ pxCurrentTCB is currently pointing to. */
+ "MOV.L #_pxCurrentTCB, R15 \n" \
+ "MOV.L [R15], R15 \n" \
+ "MOV.L [R15], R0 \n" \
+
+ /* Restore the registers from the stack of the task pointed to by
+ pxCurrentTCB. */
+ "POP R15 \n" \
+
+ /* Accumulator low 32 bits. */
+ "MVTACLO R15, A0 \n" \
+ "POP R15 \n" \
+
+ /* Accumulator high 32 bits. */
+ "MVTACHI R15, A0 \n" \
+ "POP R15 \n" \
+
+ /* Accumulator guard. */
+ "MVTACGU R15, A0 \n" \
+ "POP R15 \n" \
+
+ /* Accumulator low 32 bits. */
+ "MVTACLO R15, A1 \n" \
+ "POP R15 \n" \
+
+ /* Accumulator high 32 bits. */
+ "MVTACHI R15, A1 \n" \
+ "POP R15 \n" \
+
+ /* Accumulator guard. */
+ "MVTACGU R15, A1 \n" \
+ "POP R15 \n" \
+
+ /* Floating point status word. */
+ "MVTC R15, FPSW \n" \
+
+ /* R1 to R15 - R0 is not included as it is the SP. */
+ "POPM R1-R15 \n" \
+
+ /* This pops the remaining registers. */
+ "RTE \n" \
+ "NOP \n" \
+ "NOP \n"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vSoftwareInterruptISR( void )
+{
+ __asm volatile
+ (
+ /* Re-enable interrupts. */
+ "SETPSW I \n" \
+
+ /* Move the data that was automatically pushed onto the interrupt stack when
+ the interrupt occurred from the interrupt stack to the user stack.
+
+ R15 is saved before it is clobbered. */
+ "PUSH.L R15 \n" \
+
+ /* Read the user stack pointer. */
+ "MVFC USP, R15 \n" \
+
+ /* Move the address down to the data being moved. */
+ "SUB #12, R15 \n" \
+ "MVTC R15, USP \n" \
+
+ /* Copy the data across, R15, then PC, then PSW. */
+ "MOV.L [ R0 ], [ R15 ] \n" \
+ "MOV.L 4[ R0 ], 4[ R15 ] \n" \
+ "MOV.L 8[ R0 ], 8[ R15 ] \n" \
+
+ /* Move the interrupt stack pointer to its new correct position. */
+ "ADD #12, R0 \n" \
+
+ /* All the rest of the registers are saved directly to the user stack. */
+ "SETPSW U \n" \
+
+ /* Save the rest of the general registers (R15 has been saved already). */
+ "PUSHM R1-R14 \n" \
+
+ /* Save the FPSW and accumulator. */
+ "MVFC FPSW, R15 \n" \
+ "PUSH.L R15 \n" \
+ "MVFACGU #0, A1, R15 \n" \
+ "PUSH.L R15 \n" \
+ "MVFACHI #0, A1, R15 \n" \
+ "PUSH.L R15 \n" \
+ /* Low order word. */
+ "MVFACLO #0, A1, R15 \n" \
+ "PUSH.L R15 \n" \
+ "MVFACGU #0, A0, R15 \n" \
+ "PUSH.L R15 \n" \
+ "MVFACHI #0, A0, R15 \n" \
+ "PUSH.L R15 \n" \
+ /* Low order word. */
+ "MVFACLO #0, A0, R15 \n" \
+ "PUSH.L R15 \n" \
+
+ /* Save the stack pointer to the TCB. */
+ "MOV.L #_pxCurrentTCB, R15 \n" \
+ "MOV.L [ R15 ], R15 \n" \
+ "MOV.L R0, [ R15 ] \n" \
+
+ /* Ensure the interrupt mask is set to the syscall priority while the kernel
+ structures are being accessed. */
+ "MVTIPL %0 \n" \
+
+ /* Select the next task to run. */
+ "BSR.A _vTaskSwitchContext \n" \
+
+ /* Reset the interrupt mask as no more data structure access is required. */
+ "MVTIPL %1 \n" \
+
+ /* Load the stack pointer of the task that is now selected as the Running
+ state task from its TCB. */
+ "MOV.L #_pxCurrentTCB,R15 \n" \
+ "MOV.L [ R15 ], R15 \n" \
+ "MOV.L [ R15 ], R0 \n" \
+
+ /* Restore the context of the new task. The PSW (Program Status Word) and
+ PC will be popped by the RTE instruction. */
+ "POP R15 \n" \
+
+ /* Accumulator low 32 bits. */
+ "MVTACLO R15, A0 \n" \
+ "POP R15 \n" \
+
+ /* Accumulator high 32 bits. */
+ "MVTACHI R15, A0 \n" \
+ "POP R15 \n" \
+
+ /* Accumulator guard. */
+ "MVTACGU R15, A0 \n" \
+ "POP R15 \n" \
+
+ /* Accumulator low 32 bits. */
+ "MVTACLO R15, A1 \n" \
+ "POP R15 \n" \
+
+ /* Accumulator high 32 bits. */
+ "MVTACHI R15, A1 \n" \
+ "POP R15 \n" \
+
+ /* Accumulator guard. */
+ "MVTACGU R15, A1 \n" \
+ "POP R15 \n" \
+ "MVTC R15, FPSW \n" \
+ "POPM R1-R15 \n" \
+ "RTE \n" \
+ "NOP \n" \
+ "NOP "
+ :: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY)
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vTickISR( void )
+{
+ /* Re-enabled interrupts. */
+ __asm volatile( "SETPSW I" );
+
+ /* Increment the tick, and perform any processing the new tick value
+ necessitates. Ensure IPL is at the max syscall value first. */
+ portMASK_INTERRUPTS_FROM_KERNEL_ISR();
+ {
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ taskYIELD();
+ }
+ }
+ portUNMASK_INTERRUPTS_FROM_KERNEL_ISR();
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulPortGetIPL( void )
+{
+ __asm volatile
+ (
+ "MVFC PSW, R1 \n" \
+ "SHLR #24, R1 \n" \
+ "RTS "
+ );
+
+ /* This will never get executed, but keeps the compiler from complaining. */
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortSetIPL( uint32_t ulNewIPL )
+{
+ /* Avoid compiler warning about unreferenced parameter. */
+ ( void ) ulNewIPL;
+
+ __asm volatile
+ (
+ "PUSH R5 \n" \
+ "MVFC PSW, R5 \n" \
+ "SHLL #24, R1 \n" \
+ "AND #-0F000001H, R5 \n" \
+ "OR R1, R5 \n" \
+ "MVTC R5, PSW \n" \
+ "POP R5 \n" \
+ "RTS "
+ );
+}
diff --git a/portable/GCC/RX600v2/portmacro.h b/portable/GCC/RX600v2/portmacro.h
index 3a63cc3..5919edf 100644
--- a/portable/GCC/RX600v2/portmacro.h
+++ b/portable/GCC/RX600v2/portmacro.h
@@ -1,145 +1,144 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* When the FIT configurator or the Smart Configurator is used, platform.h has to be
- * used. */
-#ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H
- #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0
-#endif
-
-/* Type definitions - these are a bit legacy and not really used now, other than
-portSTACK_TYPE and portBASE_TYPE. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT short
-#define portSTACK_TYPE uint32_t
-#define portBASE_TYPE long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
-#else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
- /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */
-#define portSTACK_GROWTH -1
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP() __asm volatile( "NOP" )
-
-/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;"
-where portITU_SWINTR is the location of the software interrupt register
-(0x000872E0). Don't rely on the assembler to select a register, so instead
-save and restore clobbered registers manually. */
-#define portYIELD() \
- __asm volatile \
- ( \
- "PUSH.L R10 \n" \
- "MOV.L #0x872E0, R10 \n" \
- "MOV.B #0x1, [R10] \n" \
- "MOV.L [R10], R10 \n" \
- "POP R10 \n" \
- )
-
-#define portYIELD_FROM_ISR( x ) do { if( x != pdFALSE ) portYIELD(); } while( 0 )
-
-/* These macros should not be called directly, but through the
-taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is
-performed if configASSERT() is defined to ensure an assertion handler does not
-inadvertently attempt to lower the IPL when the call to assert was triggered
-because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
-when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API
-functions are those that end in FromISR. FreeRTOS maintains a separate
-interrupt API to ensure API function and interrupt entry is as fast and as
-simple as possible. */
-#define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0" )
-#ifdef configASSERT
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
- #define portDISABLE_INTERRUPTS() if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
-#else
- #define portDISABLE_INTERRUPTS() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
-#endif
-
-/* Critical nesting counts are stored in the TCB. */
-#define portCRITICAL_NESTING_IN_TCB ( 1 )
-
-/* The critical nesting functions defined within tasks.c. */
-extern void vTaskEnterCritical( void );
-extern void vTaskExitCritical( void );
-#define portENTER_CRITICAL() vTaskEnterCritical()
-#define portEXIT_CRITICAL() vTaskExitCritical()
-
-/* As this port allows interrupt nesting... */
-uint32_t ulPortGetIPL( void ) __attribute__((naked));
-void vPortSetIPL( uint32_t ulNewIPL ) __attribute__((naked));
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus )
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* When the FIT configurator or the Smart Configurator is used, platform.h has to be
+ * used. */
+#ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H
+ #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0
+#endif
+
+/* Type definitions - these are a bit legacy and not really used now, other than
+portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */
+#define portSTACK_GROWTH -1
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP() __asm volatile( "NOP" )
+
+/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;"
+where portITU_SWINTR is the location of the software interrupt register
+(0x000872E0). Don't rely on the assembler to select a register, so instead
+save and restore clobbered registers manually. */
+#define portYIELD() \
+ __asm volatile \
+ ( \
+ "PUSH.L R10 \n" \
+ "MOV.L #0x872E0, R10 \n" \
+ "MOV.B #0x1, [R10] \n" \
+ "MOV.L [R10], R10 \n" \
+ "POP R10 \n" \
+ )
+
+#define portYIELD_FROM_ISR( x ) do { if( x != pdFALSE ) portYIELD(); } while( 0 )
+
+/* These macros should not be called directly, but through the
+taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is
+performed if configASSERT() is defined to ensure an assertion handler does not
+inadvertently attempt to lower the IPL when the call to assert was triggered
+because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
+when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API
+functions are those that end in FromISR. FreeRTOS maintains a separate
+interrupt API to ensure API function and interrupt entry is as fast and as
+simple as possible. */
+#define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0" )
+#ifdef configASSERT
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+ #define portDISABLE_INTERRUPTS() if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+#else
+ #define portDISABLE_INTERRUPTS() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+#endif
+
+/* Critical nesting counts are stored in the TCB. */
+#define portCRITICAL_NESTING_IN_TCB ( 1 )
+
+/* The critical nesting functions defined within tasks.c. */
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL() vTaskEnterCritical()
+#define portEXIT_CRITICAL() vTaskExitCritical()
+
+/* As this port allows interrupt nesting... */
+uint32_t ulPortGetIPL( void ) __attribute__((naked));
+void vPortSetIPL( uint32_t ulNewIPL ) __attribute__((naked));
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/portable/GCC/RX600v2/readme.txt b/portable/GCC/RX600v2/readme.txt
index 9e89a09..8dbc983 100644
--- a/portable/GCC/RX600v2/readme.txt
+++ b/portable/GCC/RX600v2/readme.txt
@@ -69,4 +69,3 @@
For more information about Renesas RX MCUs, please visit the following URL:
https://www.renesas.com/products/microcontrollers-microprocessors/rx.html
-
diff --git a/portable/GCC/RX700v3_DPFPU/port.c b/portable/GCC/RX700v3_DPFPU/port.c
index 4575c45..c89e7ee 100644
--- a/portable/GCC/RX700v3_DPFPU/port.c
+++ b/portable/GCC/RX700v3_DPFPU/port.c
@@ -76,8 +76,8 @@
* priority - ie a known priority. Therefore these local macros are a slight
* optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
* which would require the old IPL to be read first and stored in a local variable. */
-#define portMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
-#define portUNMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i" ( configKERNEL_INTERRUPT_PRIORITY ) )
+#define portMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+#define portUNMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i" ( configKERNEL_INTERRUPT_PRIORITY ) )
/*-----------------------------------------------------------*/
@@ -339,14 +339,14 @@
/* When starting the scheduler there is nothing that needs moving to the
* interrupt stack because the function is not called from an interrupt.
* Just ensure the current stack is the user stack. */
- "SETPSW U \n"\
+ "SETPSW U \n"\
/* Obtain the location of the stack associated with which ever task
* pxCurrentTCB is currently pointing to. */
- "MOV.L #_pxCurrentTCB, R15 \n"\
- "MOV.L [R15], R15 \n"\
- "MOV.L [R15], R0 \n"\
+ "MOV.L #_pxCurrentTCB, R15 \n"\
+ "MOV.L [R15], R15 \n"\
+ "MOV.L [R15], R0 \n"\
/* Restore the registers from the stack of the task pointed to by
@@ -356,54 +356,54 @@
/* The restored ulPortTaskHasDPFPUContext is to be zero here.
* So, it is never necessary to restore the DPFPU context here. */
- "POP R15 \n"\
- "MOV.L #_ulPortTaskHasDPFPUContext, R14 \n"\
- "MOV.L R15, [R14] \n"\
+ "POP R15 \n"\
+ "MOV.L #_ulPortTaskHasDPFPUContext, R14 \n"\
+ "MOV.L R15, [R14] \n"\
#elif ( configUSE_TASK_DPFPU_SUPPORT == 2 )
/* Restore the DPFPU context. */
- "DPOPM.L DPSW-DECNT \n"\
- "DPOPM.D DR0-DR15 \n"\
+ "DPOPM.L DPSW-DECNT \n"\
+ "DPOPM.D DR0-DR15 \n"\
#endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
- "POP R15 \n"\
+ "POP R15 \n"\
/* Accumulator low 32 bits. */
- "MVTACLO R15, A0 \n"\
- "POP R15 \n"\
+ "MVTACLO R15, A0 \n"\
+ "POP R15 \n"\
/* Accumulator high 32 bits. */
- "MVTACHI R15, A0 \n"\
- "POP R15 \n"\
+ "MVTACHI R15, A0 \n"\
+ "POP R15 \n"\
/* Accumulator guard. */
- "MVTACGU R15, A0 \n"\
- "POP R15 \n"\
+ "MVTACGU R15, A0 \n"\
+ "POP R15 \n"\
/* Accumulator low 32 bits. */
- "MVTACLO R15, A1 \n"\
- "POP R15 \n"\
+ "MVTACLO R15, A1 \n"\
+ "POP R15 \n"\
/* Accumulator high 32 bits. */
- "MVTACHI R15, A1 \n"\
- "POP R15 \n"\
+ "MVTACHI R15, A1 \n"\
+ "POP R15 \n"\
/* Accumulator guard. */
- "MVTACGU R15, A1 \n"\
- "POP R15 \n"\
+ "MVTACGU R15, A1 \n"\
+ "POP R15 \n"\
/* Floating point status word. */
- "MVTC R15, FPSW \n"\
+ "MVTC R15, FPSW \n"\
/* R1 to R15 - R0 is not included as it is the SP. */
- "POPM R1-R15 \n"\
+ "POPM R1-R15 \n"\
/* This pops the remaining registers. */
- "RTE \n"\
- "NOP \n"\
- "NOP \n"
+ "RTE \n"\
+ "NOP \n"\
+ "NOP \n"
);
}
/*-----------------------------------------------------------*/
@@ -413,100 +413,100 @@
__asm volatile
(
/* Re-enable interrupts. */
- "SETPSW I \n"\
+ "SETPSW I \n"\
/* Move the data that was automatically pushed onto the interrupt stack when
* the interrupt occurred from the interrupt stack to the user stack.
*
* R15 is saved before it is clobbered. */
- "PUSH.L R15 \n"\
+ "PUSH.L R15 \n"\
/* Read the user stack pointer. */
- "MVFC USP, R15 \n"\
+ "MVFC USP, R15 \n"\
/* Move the address down to the data being moved. */
- "SUB #12, R15 \n"\
- "MVTC R15, USP \n"\
+ "SUB #12, R15 \n"\
+ "MVTC R15, USP \n"\
/* Copy the data across, R15, then PC, then PSW. */
- "MOV.L [ R0 ], [ R15 ] \n"\
- "MOV.L 4[ R0 ], 4[ R15 ] \n"\
- "MOV.L 8[ R0 ], 8[ R15 ] \n"\
+ "MOV.L [ R0 ], [ R15 ] \n"\
+ "MOV.L 4[ R0 ], 4[ R15 ] \n"\
+ "MOV.L 8[ R0 ], 8[ R15 ] \n"\
/* Move the interrupt stack pointer to its new correct position. */
- "ADD #12, R0 \n"\
+ "ADD #12, R0 \n"\
/* All the rest of the registers are saved directly to the user stack. */
- "SETPSW U \n"\
+ "SETPSW U \n"\
/* Save the rest of the general registers (R15 has been saved already). */
- "PUSHM R1-R14 \n"\
+ "PUSHM R1-R14 \n"\
/* Save the FPSW and accumulators. */
- "MVFC FPSW, R15 \n"\
- "PUSH.L R15 \n"\
- "MVFACGU #0, A1, R15 \n"\
- "PUSH.L R15 \n"\
- "MVFACHI #0, A1, R15 \n"\
- "PUSH.L R15 \n"\
- "MVFACLO #0, A1, R15 \n" /* Low order word. */ \
- "PUSH.L R15 \n"\
- "MVFACGU #0, A0, R15 \n"\
- "PUSH.L R15 \n"\
- "MVFACHI #0, A0, R15 \n"\
- "PUSH.L R15 \n"\
- "MVFACLO #0, A0, R15 \n" /* Low order word. */ \
- "PUSH.L R15 \n"\
+ "MVFC FPSW, R15 \n"\
+ "PUSH.L R15 \n"\
+ "MVFACGU #0, A1, R15 \n"\
+ "PUSH.L R15 \n"\
+ "MVFACHI #0, A1, R15 \n"\
+ "PUSH.L R15 \n"\
+ "MVFACLO #0, A1, R15 \n" /* Low order word. */ \
+ "PUSH.L R15 \n"\
+ "MVFACGU #0, A0, R15 \n"\
+ "PUSH.L R15 \n"\
+ "MVFACHI #0, A0, R15 \n"\
+ "PUSH.L R15 \n"\
+ "MVFACLO #0, A0, R15 \n" /* Low order word. */ \
+ "PUSH.L R15 \n"\
#if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
/* Does the task have a DPFPU context that needs saving? If
* ulPortTaskHasDPFPUContext is 0 then no. */
- "MOV.L #_ulPortTaskHasDPFPUContext, R15 \n"\
- "MOV.L [R15], R15 \n"\
- "CMP #0, R15 \n"\
+ "MOV.L #_ulPortTaskHasDPFPUContext, R15 \n"\
+ "MOV.L [R15], R15 \n"\
+ "CMP #0, R15 \n"\
/* Save the DPFPU context, if any. */
- "BEQ.B ?+ \n"\
- "DPUSHM.D DR0-DR15 \n"\
- "DPUSHM.L DPSW-DECNT \n"\
- "?: \n"\
+ "BEQ.B ?+ \n"\
+ "DPUSHM.D DR0-DR15 \n"\
+ "DPUSHM.L DPSW-DECNT \n"\
+ "?: \n"\
/* Save ulPortTaskHasDPFPUContext itself. */
- "PUSH.L R15 \n"\
+ "PUSH.L R15 \n"\
#elif ( configUSE_TASK_DPFPU_SUPPORT == 2 )
/* Save the DPFPU context, always. */
- "DPUSHM.D DR0-DR15 \n"\
- "DPUSHM.L DPSW-DECNT \n"\
+ "DPUSHM.D DR0-DR15 \n"\
+ "DPUSHM.L DPSW-DECNT \n"\
#endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
/* Save the stack pointer to the TCB. */
- "MOV.L #_pxCurrentTCB, R15 \n"\
- "MOV.L [ R15 ], R15 \n"\
- "MOV.L R0, [ R15 ] \n"\
+ "MOV.L #_pxCurrentTCB, R15 \n"\
+ "MOV.L [ R15 ], R15 \n"\
+ "MOV.L R0, [ R15 ] \n"\
/* Ensure the interrupt mask is set to the syscall priority while the kernel
* structures are being accessed. */
- "MVTIPL %0 \n"\
+ "MVTIPL %0 \n"\
/* Select the next task to run. */
- "BSR.A _vTaskSwitchContext \n"\
+ "BSR.A _vTaskSwitchContext \n"\
/* Reset the interrupt mask as no more data structure access is required. */
- "MVTIPL %1 \n"\
+ "MVTIPL %1 \n"\
/* Load the stack pointer of the task that is now selected as the Running
* state task from its TCB. */
- "MOV.L #_pxCurrentTCB,R15 \n"\
- "MOV.L [ R15 ], R15 \n"\
- "MOV.L [ R15 ], R0 \n"\
+ "MOV.L #_pxCurrentTCB,R15 \n"\
+ "MOV.L [ R15 ], R15 \n"\
+ "MOV.L [ R15 ], R0 \n"\
/* Restore the context of the new task. The PSW (Program Status Word) and
@@ -516,55 +516,55 @@
/* Is there a DPFPU context to restore? If the restored
* ulPortTaskHasDPFPUContext is zero then no. */
- "POP R15 \n"\
- "MOV.L #_ulPortTaskHasDPFPUContext, R14 \n"\
- "MOV.L R15, [R14] \n"\
- "CMP #0, R15 \n"\
+ "POP R15 \n"\
+ "MOV.L #_ulPortTaskHasDPFPUContext, R14 \n"\
+ "MOV.L R15, [R14] \n"\
+ "CMP #0, R15 \n"\
/* Restore the DPFPU context, if any. */
- "BEQ.B ?+ \n"\
- "DPOPM.L DPSW-DECNT \n"\
- "DPOPM.D DR0-DR15 \n"\
- "?: \n"\
+ "BEQ.B ?+ \n"\
+ "DPOPM.L DPSW-DECNT \n"\
+ "DPOPM.D DR0-DR15 \n"\
+ "?: \n"\
#elif ( configUSE_TASK_DPFPU_SUPPORT == 2 )
/* Restore the DPFPU context, always. */
- "DPOPM.L DPSW-DECNT \n"\
- "DPOPM.D DR0-DR15 \n"\
+ "DPOPM.L DPSW-DECNT \n"\
+ "DPOPM.D DR0-DR15 \n"\
#endif /* if( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
- "POP R15 \n"\
+ "POP R15 \n"\
/* Accumulator low 32 bits. */
- "MVTACLO R15, A0 \n"\
- "POP R15 \n"\
+ "MVTACLO R15, A0 \n"\
+ "POP R15 \n"\
/* Accumulator high 32 bits. */
- "MVTACHI R15, A0 \n"\
- "POP R15 \n"\
+ "MVTACHI R15, A0 \n"\
+ "POP R15 \n"\
/* Accumulator guard. */
- "MVTACGU R15, A0 \n"\
- "POP R15 \n"\
+ "MVTACGU R15, A0 \n"\
+ "POP R15 \n"\
/* Accumulator low 32 bits. */
- "MVTACLO R15, A1 \n"\
- "POP R15 \n"\
+ "MVTACLO R15, A1 \n"\
+ "POP R15 \n"\
/* Accumulator high 32 bits. */
- "MVTACHI R15, A1 \n"\
- "POP R15 \n"\
+ "MVTACHI R15, A1 \n"\
+ "POP R15 \n"\
/* Accumulator guard. */
- "MVTACGU R15, A1 \n"\
- "POP R15 \n"\
- "MVTC R15, FPSW \n"\
- "POPM R1-R15 \n"\
- "RTE \n"\
- "NOP \n"\
- "NOP "
+ "MVTACGU R15, A1 \n"\
+ "POP R15 \n"\
+ "MVTC R15, FPSW \n"\
+ "POPM R1-R15 \n"\
+ "RTE \n"\
+ "NOP \n"\
+ "NOP "
::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ), "i" ( configKERNEL_INTERRUPT_PRIORITY )
);
}
@@ -573,7 +573,7 @@
void vTickISR( void )
{
/* Re-enabled interrupts. */
- __asm volatile ( "SETPSW I");
+ __asm volatile ( "SETPSW I");
/* Increment the tick, and perform any processing the new tick value
* necessitates. Ensure IPL is at the max syscall value first. */
@@ -592,9 +592,9 @@
{
__asm volatile
(
- "MVFC PSW, R1 \n"\
- "SHLR #24, R1 \n"\
- "RTS "
+ "MVFC PSW, R1 \n"\
+ "SHLR #24, R1 \n"\
+ "RTS "
);
/* This will never get executed, but keeps the compiler from complaining. */
@@ -609,14 +609,14 @@
__asm volatile
(
- "PUSH R5 \n"\
- "MVFC PSW, R5 \n"\
- "SHLL #24, R1 \n"\
- "AND #-0F000001H, R5 \n"\
- "OR R1, R5 \n"\
- "MVTC R5, PSW \n"\
- "POP R5 \n"\
- "RTS "
+ "PUSH R5 \n"\
+ "MVFC PSW, R5 \n"\
+ "SHLL #24, R1 \n"\
+ "AND #-0F000001H, R5 \n"\
+ "OR R1, R5 \n"\
+ "MVTC R5, PSW \n"\
+ "POP R5 \n"\
+ "RTS "
);
}
/*-----------------------------------------------------------*/
diff --git a/portable/GCC/RX700v3_DPFPU/portmacro.h b/portable/GCC/RX700v3_DPFPU/portmacro.h
index 8e5c458..75d405f 100644
--- a/portable/GCC/RX700v3_DPFPU/portmacro.h
+++ b/portable/GCC/RX700v3_DPFPU/portmacro.h
@@ -44,7 +44,7 @@
*-----------------------------------------------------------
*/
-/* When the FIT configurator or the Smart Configurator is used, platform.h has to be
+/* When the FIT configurator or the Smart Configurator is used, platform.h has to be
* used. */
#ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H
#define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0
@@ -103,12 +103,12 @@
#define portYIELD() \
__asm volatile \
( \
- "PUSH.L R10 \n"\
- "MOV.L #0x872E0, R10 \n"\
- "MOV.B #0x1, [R10] \n"\
- "CMP [R10].UB, R10 \n"\
- "POP R10 \n"\
- :::"cc" \
+ "PUSH.L R10 \n"\
+ "MOV.L #0x872E0, R10 \n"\
+ "MOV.B #0x1, [R10] \n"\
+ "CMP [R10].UB, R10 \n"\
+ "POP R10 \n"\
+ :::"cc" \
)
#define portYIELD_FROM_ISR( x ) do { if( ( x ) != pdFALSE ) portYIELD(); } while( 0 )
@@ -127,17 +127,17 @@
* taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is
* performed if configASSERT() is defined to ensure an assertion handler does not
* inadvertently attempt to lower the IPL when the call to assert was triggered
- * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
* when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API
* functions are those that end in FromISR. FreeRTOS maintains a separate
* interrupt API to ensure API function and interrupt entry is as fast and as
* simple as possible. */
- #define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0")
+ #define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0")
#ifdef configASSERT
#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
- #define portDISABLE_INTERRUPTS() if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL %0"::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+ #define portDISABLE_INTERRUPTS() if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL %0"::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
#else
- #define portDISABLE_INTERRUPTS() __asm volatile ( "MVTIPL %0"::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+ #define portDISABLE_INTERRUPTS() __asm volatile ( "MVTIPL %0"::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
#endif
/* Critical nesting counts are stored in the TCB. */
diff --git a/portable/GCC/RX700v3_DPFPU/readme.txt b/portable/GCC/RX700v3_DPFPU/readme.txt
index 9e89a09..8dbc983 100644
--- a/portable/GCC/RX700v3_DPFPU/readme.txt
+++ b/portable/GCC/RX700v3_DPFPU/readme.txt
@@ -69,4 +69,3 @@
For more information about Renesas RX MCUs, please visit the following URL:
https://www.renesas.com/products/microcontrollers-microprocessors/rx.html
-
diff --git a/portable/GCC/STR75x/port.c b/portable/GCC/STR75x/port.c
index 651e1be..bd3b3ef 100644
--- a/portable/GCC/STR75x/port.c
+++ b/portable/GCC/STR75x/port.c
@@ -1,198 +1,191 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the ST STR75x ARM7
- * port.
- *----------------------------------------------------------*/
-
-/* Library includes. */
-#include "75x_tb.h"
-#include "75x_eic.h"
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Constants required to setup the initial stack. */
-#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
-#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
-
-/* Constants required to handle critical sections. */
-#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
-
-/* Prescale used on the timer clock when calculating the tick period. */
-#define portPRESCALE 20
-
-
-/*-----------------------------------------------------------*/
-
-/* Setup the TB to generate the tick interrupts. */
-static void prvSetupTimerInterrupt( void );
-
-/*-----------------------------------------------------------*/
-
-/*
- * Initialise the stack of a task to look exactly as if a call to
- * portSAVE_CONTEXT had been called.
- *
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-StackType_t *pxOriginalTOS;
-
- pxOriginalTOS = pxTopOfStack;
-
- /* To ensure asserts in tasks.c don't fail, although in this case the assert
- is not really required. */
- pxTopOfStack--;
-
- /* Setup the initial stack of the task. The stack is set exactly as
- expected by the portRESTORE_CONTEXT() macro. */
-
- /* First on the stack is the return address - which in this case is the
- start of the task. The offset is added to make the return address appear
- as it would within an IRQ ISR. */
- *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
- pxTopOfStack--;
-
- *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
- pxTopOfStack--;
-
- /* When the task starts is will expect to find the function parameter in
- R0. */
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack--;
-
- /* The status register is set for system mode, with interrupts enabled. */
- *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
-
- #ifdef THUMB_INTERWORK
- {
- /* We want the task to start in thumb mode. */
- *pxTopOfStack |= portTHUMB_MODE_BIT;
- }
- #endif
-
- pxTopOfStack--;
-
- /* Interrupt flags cannot always be stored on the stack and will
- instead be stored in a variable, which is then saved as part of the
- tasks context. */
- *pxTopOfStack = portNO_CRITICAL_NESTING;
-
- return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-extern void vPortISRStartFirstTask( void );
-
- /* Start the timer that generates the tick ISR. Interrupts are disabled
- here already. */
- prvSetupTimerInterrupt();
-
- /* Start the first task. */
- vPortISRStartFirstTask();
-
- /* Should not get here! */
- return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
- /* It is unlikely that the ARM port will require this function as there
- is nothing to return to. */
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupTimerInterrupt( void )
-{
-EIC_IRQInitTypeDef EIC_IRQInitStructure;
-TB_InitTypeDef TB_InitStructure;
-
- /* Setup the EIC for the TB. */
- EIC_IRQInitStructure.EIC_IRQChannelCmd = ENABLE;
- EIC_IRQInitStructure.EIC_IRQChannel = TB_IRQChannel;
- EIC_IRQInitStructure.EIC_IRQChannelPriority = 1;
- EIC_IRQInit(&EIC_IRQInitStructure);
-
- /* Setup the TB for the generation of the tick interrupt. */
- TB_InitStructure.TB_Mode = TB_Mode_Timing;
- TB_InitStructure.TB_CounterMode = TB_CounterMode_Down;
- TB_InitStructure.TB_Prescaler = portPRESCALE - 1;
- TB_InitStructure.TB_AutoReload = ( ( configCPU_CLOCK_HZ / portPRESCALE ) / configTICK_RATE_HZ );
- TB_Init(&TB_InitStructure);
-
- /* Enable TB Update interrupt */
- TB_ITConfig(TB_IT_Update, ENABLE);
-
- /* Clear TB Update interrupt pending bit */
- TB_ClearITPendingBit(TB_IT_Update);
-
- /* Enable TB */
- TB_Cmd(ENABLE);
-}
-/*-----------------------------------------------------------*/
-
-
-
-
-
-
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ST STR75x ARM7
+ * port.
+ *----------------------------------------------------------*/
+
+/* Library includes. */
+#include "75x_tb.h"
+#include "75x_eic.h"
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to setup the initial stack. */
+#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
+
+/* Constants required to handle critical sections. */
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
+
+/* Prescale used on the timer clock when calculating the tick period. */
+#define portPRESCALE 20
+
+
+/*-----------------------------------------------------------*/
+
+/* Setup the TB to generate the tick interrupts. */
+static void prvSetupTimerInterrupt( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been called.
+ *
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+StackType_t *pxOriginalTOS;
+
+ pxOriginalTOS = pxTopOfStack;
+
+ /* To ensure asserts in tasks.c don't fail, although in this case the assert
+ is not really required. */
+ pxTopOfStack--;
+
+ /* Setup the initial stack of the task. The stack is set exactly as
+ expected by the portRESTORE_CONTEXT() macro. */
+
+ /* First on the stack is the return address - which in this case is the
+ start of the task. The offset is added to make the return address appear
+ as it would within an IRQ ISR. */
+ *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
+ pxTopOfStack--;
+
+ *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+ pxTopOfStack--;
+
+ /* When the task starts is will expect to find the function parameter in
+ R0. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
+
+ /* The status register is set for system mode, with interrupts enabled. */
+ *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+
+ #ifdef THUMB_INTERWORK
+ {
+ /* We want the task to start in thumb mode. */
+ *pxTopOfStack |= portTHUMB_MODE_BIT;
+ }
+ #endif
+
+ pxTopOfStack--;
+
+ /* Interrupt flags cannot always be stored on the stack and will
+ instead be stored in a variable, which is then saved as part of the
+ tasks context. */
+ *pxTopOfStack = portNO_CRITICAL_NESTING;
+
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vPortISRStartFirstTask( void );
+
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ here already. */
+ prvSetupTimerInterrupt();
+
+ /* Start the first task. */
+ vPortISRStartFirstTask();
+
+ /* Should not get here! */
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+ /* It is unlikely that the ARM port will require this function as there
+ is nothing to return to. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+EIC_IRQInitTypeDef EIC_IRQInitStructure;
+TB_InitTypeDef TB_InitStructure;
+
+ /* Setup the EIC for the TB. */
+ EIC_IRQInitStructure.EIC_IRQChannelCmd = ENABLE;
+ EIC_IRQInitStructure.EIC_IRQChannel = TB_IRQChannel;
+ EIC_IRQInitStructure.EIC_IRQChannelPriority = 1;
+ EIC_IRQInit(&EIC_IRQInitStructure);
+
+ /* Setup the TB for the generation of the tick interrupt. */
+ TB_InitStructure.TB_Mode = TB_Mode_Timing;
+ TB_InitStructure.TB_CounterMode = TB_CounterMode_Down;
+ TB_InitStructure.TB_Prescaler = portPRESCALE - 1;
+ TB_InitStructure.TB_AutoReload = ( ( configCPU_CLOCK_HZ / portPRESCALE ) / configTICK_RATE_HZ );
+ TB_Init(&TB_InitStructure);
+
+ /* Enable TB Update interrupt */
+ TB_ITConfig(TB_IT_Update, ENABLE);
+
+ /* Clear TB Update interrupt pending bit */
+ TB_ClearITPendingBit(TB_IT_Update);
+
+ /* Enable TB */
+ TB_Cmd(ENABLE);
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/STR75x/portISR.c b/portable/GCC/STR75x/portISR.c
index a431a15..fd66e4c 100644
--- a/portable/GCC/STR75x/portISR.c
+++ b/portable/GCC/STR75x/portISR.c
@@ -1,183 +1,178 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-
-/*-----------------------------------------------------------
- * Components that can be compiled to either ARM or THUMB mode are
- * contained in port.c The ISR routines, which can only be compiled
- * to ARM mode, are contained in this file.
- *----------------------------------------------------------*/
-
-/*
-*/
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Constants required to handle critical sections. */
-#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
-
-volatile uint32_t ulCriticalNesting = 9999UL;
-
-/*-----------------------------------------------------------*/
-
-/*
- * The scheduler can only be started from ARM mode, hence the inclusion of this
- * function here.
- */
-void vPortISRStartFirstTask( void );
-/*-----------------------------------------------------------*/
-
-void vPortISRStartFirstTask( void )
-{
- /* Simply start the scheduler. This is included here as it can only be
- called from ARM mode. */
- asm volatile ( \
- "LDR R0, =pxCurrentTCB \n\t" \
- "LDR R0, [R0] \n\t" \
- "LDR LR, [R0] \n\t" \
- \
- /* The critical nesting depth is the first item on the stack. */ \
- /* Load it into the ulCriticalNesting variable. */ \
- "LDR R0, =ulCriticalNesting \n\t" \
- "LDMFD LR!, {R1} \n\t" \
- "STR R1, [R0] \n\t" \
- \
- /* Get the SPSR from the stack. */ \
- "LDMFD LR!, {R0} \n\t" \
- "MSR SPSR, R0 \n\t" \
- \
- /* Restore all system mode registers for the task. */ \
- "LDMFD LR, {R0-R14}^ \n\t" \
- "NOP \n\t" \
- \
- /* Restore the return address. */ \
- "LDR LR, [LR, #+60] \n\t" \
- \
- /* And return - correcting the offset in the LR to obtain the */ \
- /* correct address. */ \
- "SUBS PC, LR, #4 \n\t" \
- );
-}
-/*-----------------------------------------------------------*/
-
-void vPortTickISR( void )
-{
- /* Increment the RTOS tick count, then look for the highest priority
- task that is ready to run. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- vTaskSwitchContext();
- }
-
- /* Ready for the next interrupt. */
- TB_ClearITPendingBit( TB_IT_Update );
-}
-
-/*-----------------------------------------------------------*/
-
-/*
- * The interrupt management utilities can only be called from ARM mode. When
- * THUMB_INTERWORK is defined the utilities are defined as functions here to
- * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then
- * the utilities are defined as macros in portmacro.h - as per other ports.
- */
-#ifdef THUMB_INTERWORK
-
- void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
- void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
-
- void vPortDisableInterruptsFromThumb( void )
- {
- asm volatile (
- "STMDB SP!, {R0} \n\t" /* Push R0. */
- "MRS R0, CPSR \n\t" /* Get CPSR. */
- "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
- "MSR CPSR, R0 \n\t" /* Write back modified value. */
- "LDMIA SP!, {R0} \n\t" /* Pop R0. */
- "BX R14" ); /* Return back to thumb. */
- }
-
- void vPortEnableInterruptsFromThumb( void )
- {
- asm volatile (
- "STMDB SP!, {R0} \n\t" /* Push R0. */
- "MRS R0, CPSR \n\t" /* Get CPSR. */
- "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
- "MSR CPSR, R0 \n\t" /* Write back modified value. */
- "LDMIA SP!, {R0} \n\t" /* Pop R0. */
- "BX R14" ); /* Return back to thumb. */
- }
-
-#endif /* THUMB_INTERWORK */
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
- /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
- asm volatile (
- "STMDB SP!, {R0} \n\t" /* Push R0. */
- "MRS R0, CPSR \n\t" /* Get CPSR. */
- "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
- "MSR CPSR, R0 \n\t" /* Write back modified value. */
- "LDMIA SP!, {R0}" ); /* Pop R0. */
-
- /* Now interrupts are disabled ulCriticalNesting can be accessed
- directly. Increment ulCriticalNesting to keep a count of how many times
- portENTER_CRITICAL() has been called. */
- ulCriticalNesting++;
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
- if( ulCriticalNesting > portNO_CRITICAL_NESTING )
- {
- /* Decrement the nesting count as we are leaving a critical section. */
- ulCriticalNesting--;
-
- /* If the nesting level has reached zero then interrupts should be
- re-enabled. */
- if( ulCriticalNesting == portNO_CRITICAL_NESTING )
- {
- /* Enable interrupts as per portEXIT_CRITICAL(). */
- asm volatile (
- "STMDB SP!, {R0} \n\t" /* Push R0. */
- "MRS R0, CPSR \n\t" /* Get CPSR. */
- "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
- "MSR CPSR, R0 \n\t" /* Write back modified value. */
- "LDMIA SP!, {R0}" ); /* Pop R0. */
- }
- }
-}
-
-
-
-
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+/*-----------------------------------------------------------
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in port.c The ISR routines, which can only be compiled
+ * to ARM mode, are contained in this file.
+ *----------------------------------------------------------*/
+
+/*
+*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to handle critical sections. */
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
+
+volatile uint32_t ulCriticalNesting = 9999UL;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The scheduler can only be started from ARM mode, hence the inclusion of this
+ * function here.
+ */
+void vPortISRStartFirstTask( void );
+/*-----------------------------------------------------------*/
+
+void vPortISRStartFirstTask( void )
+{
+ /* Simply start the scheduler. This is included here as it can only be
+ called from ARM mode. */
+ asm volatile ( \
+ "LDR R0, =pxCurrentTCB \n\t" \
+ "LDR R0, [R0] \n\t" \
+ "LDR LR, [R0] \n\t" \
+ \
+ /* The critical nesting depth is the first item on the stack. */ \
+ /* Load it into the ulCriticalNesting variable. */ \
+ "LDR R0, =ulCriticalNesting \n\t" \
+ "LDMFD LR!, {R1} \n\t" \
+ "STR R1, [R0] \n\t" \
+ \
+ /* Get the SPSR from the stack. */ \
+ "LDMFD LR!, {R0} \n\t" \
+ "MSR SPSR, R0 \n\t" \
+ \
+ /* Restore all system mode registers for the task. */ \
+ "LDMFD LR, {R0-R14}^ \n\t" \
+ "NOP \n\t" \
+ \
+ /* Restore the return address. */ \
+ "LDR LR, [LR, #+60] \n\t" \
+ \
+ /* And return - correcting the offset in the LR to obtain the */ \
+ /* correct address. */ \
+ "SUBS PC, LR, #4 \n\t" \
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vPortTickISR( void )
+{
+ /* Increment the RTOS tick count, then look for the highest priority
+ task that is ready to run. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ vTaskSwitchContext();
+ }
+
+ /* Ready for the next interrupt. */
+ TB_ClearITPendingBit( TB_IT_Update );
+}
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The interrupt management utilities can only be called from ARM mode. When
+ * THUMB_INTERWORK is defined the utilities are defined as functions here to
+ * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then
+ * the utilities are defined as macros in portmacro.h - as per other ports.
+ */
+#ifdef THUMB_INTERWORK
+
+ void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+ void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+
+ void vPortDisableInterruptsFromThumb( void )
+ {
+ asm volatile (
+ "STMDB SP!, {R0} \n\t" /* Push R0. */
+ "MRS R0, CPSR \n\t" /* Get CPSR. */
+ "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */
+ "LDMIA SP!, {R0} \n\t" /* Pop R0. */
+ "BX R14" ); /* Return back to thumb. */
+ }
+
+ void vPortEnableInterruptsFromThumb( void )
+ {
+ asm volatile (
+ "STMDB SP!, {R0} \n\t" /* Push R0. */
+ "MRS R0, CPSR \n\t" /* Get CPSR. */
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */
+ "LDMIA SP!, {R0} \n\t" /* Pop R0. */
+ "BX R14" ); /* Return back to thumb. */
+ }
+
+#endif /* THUMB_INTERWORK */
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+ /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
+ asm volatile (
+ "STMDB SP!, {R0} \n\t" /* Push R0. */
+ "MRS R0, CPSR \n\t" /* Get CPSR. */
+ "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */
+ "LDMIA SP!, {R0}" ); /* Pop R0. */
+
+ /* Now interrupts are disabled ulCriticalNesting can be accessed
+ directly. Increment ulCriticalNesting to keep a count of how many times
+ portENTER_CRITICAL() has been called. */
+ ulCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+ if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+ {
+ /* Decrement the nesting count as we are leaving a critical section. */
+ ulCriticalNesting--;
+
+ /* If the nesting level has reached zero then interrupts should be
+ re-enabled. */
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+ {
+ /* Enable interrupts as per portEXIT_CRITICAL(). */
+ asm volatile (
+ "STMDB SP!, {R0} \n\t" /* Push R0. */
+ "MRS R0, CPSR \n\t" /* Get CPSR. */
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */
+ "LDMIA SP!, {R0}" ); /* Pop R0. */
+ }
+ }
+}
diff --git a/portable/GCC/STR75x/portmacro.h b/portable/GCC/STR75x/portmacro.h
index 4bcd9c7..b7fbe66 100644
--- a/portable/GCC/STR75x/portmacro.h
+++ b/portable/GCC/STR75x/portmacro.h
@@ -1,142 +1,140 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT short
-#define portSTACK_TYPE uint32_t
-#define portBASE_TYPE long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
-#else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portSTACK_GROWTH ( -1 )
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT 8
-#define portYIELD() asm volatile ( "SWI 0" )
-#define portNOP() asm volatile ( "NOP" )
-/*-----------------------------------------------------------*/
-
-/* Critical section handling. */
-/*
- * The interrupt management utilities can only be called from ARM mode. When
- * THUMB_INTERWORK is defined the utilities are defined as functions in
- * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not
- * defined then the utilities are defined as macros here - as per other ports.
- */
-
-#ifdef THUMB_INTERWORK
-
- extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
- extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
-
- #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb()
- #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb()
-
-#else
-
- #define portDISABLE_INTERRUPTS() \
- asm volatile ( \
- "STMDB SP!, {R0} \n\t" /* Push R0. */ \
- "MRS R0, CPSR \n\t" /* Get CPSR. */ \
- "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \
- "MSR CPSR, R0 \n\t" /* Write back modified value. */ \
- "LDMIA SP!, {R0} " ) /* Pop R0. */
-
- #define portENABLE_INTERRUPTS() \
- asm volatile ( \
- "STMDB SP!, {R0} \n\t" /* Push R0. */ \
- "MRS R0, CPSR \n\t" /* Get CPSR. */ \
- "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \
- "MSR CPSR, R0 \n\t" /* Write back modified value. */ \
- "LDMIA SP!, {R0} " ) /* Pop R0. */
-
-#endif /* THUMB_INTERWORK */
-
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-
-#define portENTER_CRITICAL() vPortEnterCritical();
-#define portEXIT_CRITICAL() vPortExitCritical();
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-#define portEND_SWITCHING_ISR( xSwitchRequired ) \
-{ \
-extern void vTaskSwitchContext( void ); \
- \
- if( xSwitchRequired ) \
- { \
- vTaskSwitchContext(); \
- } \
-}
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portYIELD() asm volatile ( "SWI 0" )
+#define portNOP() asm volatile ( "NOP" )
+/*-----------------------------------------------------------*/
+
+/* Critical section handling. */
+/*
+ * The interrupt management utilities can only be called from ARM mode. When
+ * THUMB_INTERWORK is defined the utilities are defined as functions in
+ * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not
+ * defined then the utilities are defined as macros here - as per other ports.
+ */
+
+#ifdef THUMB_INTERWORK
+
+ extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+ extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+
+ #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb()
+ #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb()
+
+#else
+
+ #define portDISABLE_INTERRUPTS() \
+ asm volatile ( \
+ "STMDB SP!, {R0} \n\t" /* Push R0. */ \
+ "MRS R0, CPSR \n\t" /* Get CPSR. */ \
+ "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */ \
+ "LDMIA SP!, {R0} " ) /* Pop R0. */
+
+ #define portENABLE_INTERRUPTS() \
+ asm volatile ( \
+ "STMDB SP!, {R0} \n\t" /* Push R0. */ \
+ "MRS R0, CPSR \n\t" /* Get CPSR. */ \
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */ \
+ "LDMIA SP!, {R0} " ) /* Pop R0. */
+
+#endif /* THUMB_INTERWORK */
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portENTER_CRITICAL() vPortEnterCritical();
+#define portEXIT_CRITICAL() vPortExitCritical();
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+{ \
+extern void vTaskSwitchContext( void ); \
+ \
+ if( xSwitchRequired ) \
+ { \
+ vTaskSwitchContext(); \
+ } \
+}
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/portable/GCC/TriCore_1782/port.c b/portable/GCC/TriCore_1782/port.c
index 0dedda2..173fed0 100644
--- a/portable/GCC/TriCore_1782/port.c
+++ b/portable/GCC/TriCore_1782/port.c
@@ -1,542 +1,540 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/* Standard includes. */
-#include <stdlib.h>
-#include <string.h>
-
-/* TriCore specific includes. */
-#include <tc1782.h>
-#include <machine/intrinsics.h>
-#include <machine/cint.h>
-#include <machine/wdtcon.h>
-
-/* Kernel includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-#include "list.h"
-
-#if configCHECK_FOR_STACK_OVERFLOW > 0
- #error "Stack checking cannot be used with this port, as, unlike most ports, the pxTopOfStack member of the TCB is consumed CSA. CSA starvation, loosely equivalent to stack overflow, will result in a trap exception."
- /* The stack pointer is accessible using portCSA_TO_ADDRESS( portCSA_TO_ADDRESS( pxCurrentTCB->pxTopOfStack )[ 0 ] )[ 2 ]; */
-#endif /* configCHECK_FOR_STACK_OVERFLOW */
-
-
-/*-----------------------------------------------------------*/
-
-/* System register Definitions. */
-#define portSYSTEM_PROGRAM_STATUS_WORD ( 0x000008FFUL ) /* Supervisor Mode, MPU Register Set 0 and Call Depth Counting disabled. */
-#define portINITIAL_PRIVILEGED_PROGRAM_STATUS_WORD ( 0x000014FFUL ) /* IO Level 1, MPU Register Set 1 and Call Depth Counting disabled. */
-#define portINITIAL_UNPRIVILEGED_PROGRAM_STATUS_WORD ( 0x000010FFUL ) /* IO Level 0, MPU Register Set 1 and Call Depth Counting disabled. */
-#define portINITIAL_PCXI_UPPER_CONTEXT_WORD ( 0x00C00000UL ) /* The lower 20 bits identify the CSA address. */
-#define portINITIAL_SYSCON ( 0x00000000UL ) /* MPU Disable. */
-
-/* CSA manipulation macros. */
-#define portCSA_FCX_MASK ( 0x000FFFFFUL )
-
-/* OS Interrupt and Trap mechanisms. */
-#define portRESTORE_PSW_MASK ( ~( 0x000000FFUL ) )
-#define portSYSCALL_TRAP ( 6 )
-
-/* Each CSA contains 16 words of data. */
-#define portNUM_WORDS_IN_CSA ( 16 )
-
-/* The interrupt enable bit in the PCP_SRC register. */
-#define portENABLE_CPU_INTERRUPT ( 1U << 12U )
-/*-----------------------------------------------------------*/
-
-/*
- * Perform any hardware configuration necessary to generate the tick interrupt.
- */
-static void prvSystemTickHandler( int ) __attribute__((longcall));
-static void prvSetupTimerInterrupt( void );
-
-/*
- * Trap handler for yields.
- */
-static void prvTrapYield( int iTrapIdentification );
-
-/*
- * Priority 1 interrupt handler for yields pended from an interrupt.
- */
-static void prvInterruptYield( int iTrapIdentification );
-
-/*-----------------------------------------------------------*/
-
-/* This reference is required by the save/restore context macros. */
-extern volatile uint32_t *pxCurrentTCB;
-
-/* Precalculate the compare match value at compile time. */
-static const uint32_t ulCompareMatchValue = ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ );
-
-/*-----------------------------------------------------------*/
-
-StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-uint32_t *pulUpperCSA = NULL;
-uint32_t *pulLowerCSA = NULL;
-
- /* 16 Address Registers (4 Address registers are global), 16 Data
- Registers, and 3 System Registers.
-
- There are 3 registers that track the CSAs.
- FCX points to the head of globally free set of CSAs.
- PCX for the task needs to point to Lower->Upper->NULL arrangement.
- LCX points to the last free CSA so that corrective action can be taken.
-
- Need two CSAs to store the context of a task.
- The upper context contains D8-D15, A10-A15, PSW and PCXI->NULL.
- The lower context contains D0-D7, A2-A7, A11 and PCXI->UpperContext.
- The pxCurrentTCB->pxTopOfStack points to the Lower Context RSLCX matching the initial BISR.
- The Lower Context points to the Upper Context ready for the return from the interrupt handler.
-
- The Real stack pointer for the task is stored in the A10 which is restored
- with the upper context. */
-
- /* Have to disable interrupts here because the CSAs are going to be
- manipulated. */
- portENTER_CRITICAL();
- {
- /* DSync to ensure that buffering is not a problem. */
- _dsync();
-
- /* Consume two free CSAs. */
- pulLowerCSA = portCSA_TO_ADDRESS( __MFCR( $FCX ) );
- if( NULL != pulLowerCSA )
- {
- /* The Lower Links to the Upper. */
- pulUpperCSA = portCSA_TO_ADDRESS( pulLowerCSA[ 0 ] );
- }
-
- /* Check that we have successfully reserved two CSAs. */
- if( ( NULL != pulLowerCSA ) && ( NULL != pulUpperCSA ) )
- {
- /* Remove the two consumed CSAs from the free CSA list. */
- _disable();
- _dsync();
- _mtcr( $FCX, pulUpperCSA[ 0 ] );
- _isync();
- _enable();
- }
- else
- {
- /* Simply trigger a context list depletion trap. */
- _svlcx();
- }
- }
- portEXIT_CRITICAL();
-
- /* Clear the upper CSA. */
- memset( pulUpperCSA, 0, portNUM_WORDS_IN_CSA * sizeof( uint32_t ) );
-
- /* Upper Context. */
- pulUpperCSA[ 2 ] = ( uint32_t )pxTopOfStack; /* A10; Stack Return aka Stack Pointer */
- pulUpperCSA[ 1 ] = portSYSTEM_PROGRAM_STATUS_WORD; /* PSW */
-
- /* Clear the lower CSA. */
- memset( pulLowerCSA, 0, portNUM_WORDS_IN_CSA * sizeof( uint32_t ) );
-
- /* Lower Context. */
- pulLowerCSA[ 8 ] = ( uint32_t ) pvParameters; /* A4; Address Type Parameter Register */
- pulLowerCSA[ 1 ] = ( uint32_t ) pxCode; /* A11; Return Address aka RA */
-
- /* PCXI pointing to the Upper context. */
- pulLowerCSA[ 0 ] = ( portINITIAL_PCXI_UPPER_CONTEXT_WORD | ( uint32_t ) portADDRESS_TO_CSA( pulUpperCSA ) );
-
- /* Save the link to the CSA in the top of stack. */
- pxTopOfStack = (uint32_t * ) portADDRESS_TO_CSA( pulLowerCSA );
-
- /* DSync to ensure that buffering is not a problem. */
- _dsync();
-
- return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-int32_t xPortStartScheduler( void )
-{
-extern void vTrapInstallHandlers( void );
-uint32_t ulMFCR = 0UL;
-uint32_t *pulUpperCSA = NULL;
-uint32_t *pulLowerCSA = NULL;
-
- /* Interrupts at or below configMAX_SYSCALL_INTERRUPT_PRIORITY are disable
- when this function is called. */
-
- /* Set-up the timer interrupt. */
- prvSetupTimerInterrupt();
-
- /* Install the Trap Handlers. */
- vTrapInstallHandlers();
-
- /* Install the Syscall Handler for yield calls. */
- if( 0 == _install_trap_handler( portSYSCALL_TRAP, prvTrapYield ) )
- {
- /* Failed to install the yield handler, force an assert. */
- configASSERT( ( ( volatile void * ) NULL ) );
- }
-
- /* Enable then install the priority 1 interrupt for pending context
- switches from an ISR. See mod_SRC in the TriCore manual. */
- CPU_SRC0.reg = ( portENABLE_CPU_INTERRUPT ) | ( configKERNEL_YIELD_PRIORITY );
- if( 0 == _install_int_handler( configKERNEL_YIELD_PRIORITY, prvInterruptYield, 0 ) )
- {
- /* Failed to install the yield handler, force an assert. */
- configASSERT( ( ( volatile void * ) NULL ) );
- }
-
- _disable();
-
- /* Load the initial SYSCON. */
- _mtcr( $SYSCON, portINITIAL_SYSCON );
- _isync();
-
- /* ENDINIT has already been applied in the 'cstart.c' code. */
-
- /* Clear the PSW.CDC to enable the use of an RFE without it generating an
- exception because this code is not genuinely in an exception. */
- ulMFCR = __MFCR( $PSW );
- ulMFCR &= portRESTORE_PSW_MASK;
- _dsync();
- _mtcr( $PSW, ulMFCR );
- _isync();
-
- /* Finally, perform the equivalent of a portRESTORE_CONTEXT() */
- pulLowerCSA = portCSA_TO_ADDRESS( ( *pxCurrentTCB ) );
- pulUpperCSA = portCSA_TO_ADDRESS( pulLowerCSA[0] );
- _dsync();
- _mtcr( $PCXI, *pxCurrentTCB );
- _isync();
- _nop();
- _rslcx();
- _nop();
-
- /* Return to the first task selected to execute. */
- __asm volatile( "rfe" );
-
- /* Will not get here. */
- return 0;
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupTimerInterrupt( void )
-{
- /* Set-up the clock divider. */
- unlock_wdtcon();
- {
- /* Wait until access to Endint protected register is enabled. */
- while( 0 != ( WDT_CON0.reg & 0x1UL ) );
-
- /* RMC == 1 so STM Clock == FPI */
- STM_CLC.reg = ( 1UL << 8 );
- }
- lock_wdtcon();
-
- /* Determine how many bits are used without changing other bits in the CMCON register. */
- STM_CMCON.reg &= ~( 0x1fUL );
- STM_CMCON.reg |= ( 0x1fUL - __CLZ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ ) );
-
- /* Take into account the current time so a tick doesn't happen immediately. */
- STM_CMP0.reg = ulCompareMatchValue + STM_TIM0.reg;
-
- if( 0 != _install_int_handler( configKERNEL_INTERRUPT_PRIORITY, prvSystemTickHandler, 0 ) )
- {
- /* Set-up the interrupt. */
- STM_SRC0.reg = ( configKERNEL_INTERRUPT_PRIORITY | 0x00005000UL );
-
- /* Enable the Interrupt. */
- STM_ISRR.reg &= ~( 0x03UL );
- STM_ISRR.reg |= 0x1UL;
- STM_ISRR.reg &= ~( 0x07UL );
- STM_ICR.reg |= 0x1UL;
- }
- else
- {
- /* Failed to install the Tick Interrupt. */
- configASSERT( ( ( volatile void * ) NULL ) );
- }
-}
-/*-----------------------------------------------------------*/
-
-static void prvSystemTickHandler( int iArg )
-{
-uint32_t ulSavedInterruptMask;
-uint32_t *pxUpperCSA = NULL;
-uint32_t xUpperCSA = 0UL;
-extern volatile uint32_t *pxCurrentTCB;
-int32_t lYieldRequired;
-
- /* Just to avoid compiler warnings about unused parameters. */
- ( void ) iArg;
-
- /* Clear the interrupt source. */
- STM_ISRR.reg = 1UL;
-
- /* Reload the Compare Match register for X ticks into the future.
-
- If critical section or interrupt nesting budgets are exceeded, then
- it is possible that the calculated next compare match value is in the
- past. If this occurs (unlikely), it is possible that the resulting
- time slippage will exceed a single tick period. Any adverse effect of
- this is time bounded by the fact that only the first n bits of the 56 bit
- STM timer are being used for a compare match, so another compare match
- will occur after an overflow in just those n bits (not the entire 56 bits).
- As an example, if the peripheral clock is 75MHz, and the tick rate is 1KHz,
- a missed tick could result in the next tick interrupt occurring within a
- time that is 1.7 times the desired period. The fact that this is greater
- than a single tick period is an effect of using a timer that cannot be
- automatically reset, in hardware, by the occurrence of a tick interrupt.
- Changing the tick source to a timer that has an automatic reset on compare
- match (such as a GPTA timer) will reduce the maximum possible additional
- period to exactly 1 times the desired period. */
- STM_CMP0.reg += ulCompareMatchValue;
-
- /* Kernel API calls require Critical Sections. */
- ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
- {
- /* Increment the Tick. */
- lYieldRequired = xTaskIncrementTick();
- }
- portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
-
- if( lYieldRequired != pdFALSE )
- {
- /* Save the context of a task.
- The upper context is automatically saved when entering a trap or interrupt.
- Need to save the lower context as well and copy the PCXI CSA ID into
- pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
- TCB of a task.
-
- Call vTaskSwitchContext to select the next task, note that this changes the
- value of pxCurrentTCB so that it needs to be reloaded.
-
- Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
- that has just been switched in.
-
- Load the context of the task.
- Need to restore the lower context by loading the CSA from
- pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
- In the Interrupt handler post-amble, RSLCX will restore the lower context
- of the task. RFE will restore the upper context of the task, jump to the
- return address and restore the previous state of interrupts being
- enabled/disabled. */
- _disable();
- _dsync();
- xUpperCSA = __MFCR( $PCXI );
- pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA );
- *pxCurrentTCB = pxUpperCSA[ 0 ];
- vTaskSwitchContext();
- pxUpperCSA[ 0 ] = *pxCurrentTCB;
- CPU_SRC0.bits.SETR = 0;
- _isync();
- }
-}
-/*-----------------------------------------------------------*/
-
-/*
- * When a task is deleted, it is yielded permanently until the IDLE task
- * has an opportunity to reclaim the memory that that task was using.
- * Typically, the memory used by a task is the TCB and Stack but in the
- * TriCore this includes the CSAs that were consumed as part of the Call
- * Stack. These CSAs can only be returned to the Globally Free Pool when
- * they are not part of the current Call Stack, hence, delaying the
- * reclamation until the IDLE task is freeing the task's other resources.
- * This function uses the head of the linked list of CSAs (from when the
- * task yielded for the last time) and finds the tail (the very bottom of
- * the call stack) and inserts this list at the head of the Free list,
- * attaching the existing Free List to the tail of the reclaimed call stack.
- *
- * NOTE: the IDLE task needs processing time to complete this function
- * and in heavily loaded systems, the Free CSAs may be consumed faster
- * than they can be freed assuming that tasks are being spawned and
- * deleted frequently.
- */
-void vPortReclaimCSA( uint32_t *pxTCB )
-{
-uint32_t pxHeadCSA, pxTailCSA, pxFreeCSA;
-uint32_t *pulNextCSA;
-
- /* A pointer to the first CSA in the list of CSAs consumed by the task is
- stored in the first element of the tasks TCB structure (where the stack
- pointer would be on a traditional stack based architecture). */
- pxHeadCSA = ( *pxTCB ) & portCSA_FCX_MASK;
-
- /* Mask off everything in the CSA link field other than the address. If
- the address is NULL, then the CSA is not linking anywhere and there is
- nothing to do. */
- pxTailCSA = pxHeadCSA;
-
- /* Convert the link value to contain just a raw address and store this
- in a local variable. */
- pulNextCSA = portCSA_TO_ADDRESS( pxTailCSA );
-
- /* Iterate over the CSAs that were consumed as part of the task. The
- first field in the CSA is the pointer to then next CSA. Mask off
- everything in the pointer to the next CSA, other than the link address.
- If this is NULL, then the CSA currently being pointed to is the last in
- the chain. */
- while( 0UL != ( pulNextCSA[ 0 ] & portCSA_FCX_MASK ) )
- {
- /* Clear all bits of the pointer to the next in the chain, other
- than the address bits themselves. */
- pulNextCSA[ 0 ] = pulNextCSA[ 0 ] & portCSA_FCX_MASK;
-
- /* Move the pointer to point to the next CSA in the list. */
- pxTailCSA = pulNextCSA[ 0 ];
-
- /* Update the local pointer to the CSA. */
- pulNextCSA = portCSA_TO_ADDRESS( pxTailCSA );
- }
-
- _disable();
- {
- /* Look up the current free CSA head. */
- _dsync();
- pxFreeCSA = __MFCR( $FCX );
-
- /* Join the current Free onto the Tail of what is being reclaimed. */
- portCSA_TO_ADDRESS( pxTailCSA )[ 0 ] = pxFreeCSA;
-
- /* Move the head of the reclaimed into the Free. */
- _dsync();
- _mtcr( $FCX, pxHeadCSA );
- _isync();
- }
- _enable();
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
- /* Nothing to do. Unlikely to want to end. */
-}
-/*-----------------------------------------------------------*/
-
-static void prvTrapYield( int iTrapIdentification )
-{
-uint32_t *pxUpperCSA = NULL;
-uint32_t xUpperCSA = 0UL;
-extern volatile uint32_t *pxCurrentTCB;
-
- switch( iTrapIdentification )
- {
- case portSYSCALL_TASK_YIELD:
- /* Save the context of a task.
- The upper context is automatically saved when entering a trap or interrupt.
- Need to save the lower context as well and copy the PCXI CSA ID into
- pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
- TCB of a task.
-
- Call vTaskSwitchContext to select the next task, note that this changes the
- value of pxCurrentTCB so that it needs to be reloaded.
-
- Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
- that has just been switched in.
-
- Load the context of the task.
- Need to restore the lower context by loading the CSA from
- pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
- In the Interrupt handler post-amble, RSLCX will restore the lower context
- of the task. RFE will restore the upper context of the task, jump to the
- return address and restore the previous state of interrupts being
- enabled/disabled. */
- _disable();
- _dsync();
- xUpperCSA = __MFCR( $PCXI );
- pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA );
- *pxCurrentTCB = pxUpperCSA[ 0 ];
- vTaskSwitchContext();
- pxUpperCSA[ 0 ] = *pxCurrentTCB;
- CPU_SRC0.bits.SETR = 0;
- _isync();
- break;
-
- default:
- /* Unimplemented trap called. */
- configASSERT( ( ( volatile void * ) NULL ) );
- break;
- }
-}
-/*-----------------------------------------------------------*/
-
-static void prvInterruptYield( int iId )
-{
-uint32_t *pxUpperCSA = NULL;
-uint32_t xUpperCSA = 0UL;
-extern volatile uint32_t *pxCurrentTCB;
-
- /* Just to remove compiler warnings. */
- ( void ) iId;
-
- /* Save the context of a task.
- The upper context is automatically saved when entering a trap or interrupt.
- Need to save the lower context as well and copy the PCXI CSA ID into
- pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
- TCB of a task.
-
- Call vTaskSwitchContext to select the next task, note that this changes the
- value of pxCurrentTCB so that it needs to be reloaded.
-
- Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
- that has just been switched in.
-
- Load the context of the task.
- Need to restore the lower context by loading the CSA from
- pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
- In the Interrupt handler post-amble, RSLCX will restore the lower context
- of the task. RFE will restore the upper context of the task, jump to the
- return address and restore the previous state of interrupts being
- enabled/disabled. */
- _disable();
- _dsync();
- xUpperCSA = __MFCR( $PCXI );
- pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA );
- *pxCurrentTCB = pxUpperCSA[ 0 ];
- vTaskSwitchContext();
- pxUpperCSA[ 0 ] = *pxCurrentTCB;
- CPU_SRC0.bits.SETR = 0;
- _isync();
-}
-/*-----------------------------------------------------------*/
-
-uint32_t uxPortSetInterruptMaskFromISR( void )
-{
-uint32_t uxReturn = 0UL;
-
- _disable();
- uxReturn = __MFCR( $ICR );
- _mtcr( $ICR, ( ( uxReturn & ~portCCPN_MASK ) | configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
- _isync();
- _enable();
-
- /* Return just the interrupt mask bits. */
- return ( uxReturn & portCCPN_MASK );
-}
-/*-----------------------------------------------------------*/
-
-
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Standard includes. */
+#include <stdlib.h>
+#include <string.h>
+
+/* TriCore specific includes. */
+#include <tc1782.h>
+#include <machine/intrinsics.h>
+#include <machine/cint.h>
+#include <machine/wdtcon.h>
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "list.h"
+
+#if configCHECK_FOR_STACK_OVERFLOW > 0
+ #error "Stack checking cannot be used with this port, as, unlike most ports, the pxTopOfStack member of the TCB is consumed CSA. CSA starvation, loosely equivalent to stack overflow, will result in a trap exception."
+ /* The stack pointer is accessible using portCSA_TO_ADDRESS( portCSA_TO_ADDRESS( pxCurrentTCB->pxTopOfStack )[ 0 ] )[ 2 ]; */
+#endif /* configCHECK_FOR_STACK_OVERFLOW */
+
+
+/*-----------------------------------------------------------*/
+
+/* System register Definitions. */
+#define portSYSTEM_PROGRAM_STATUS_WORD ( 0x000008FFUL ) /* Supervisor Mode, MPU Register Set 0 and Call Depth Counting disabled. */
+#define portINITIAL_PRIVILEGED_PROGRAM_STATUS_WORD ( 0x000014FFUL ) /* IO Level 1, MPU Register Set 1 and Call Depth Counting disabled. */
+#define portINITIAL_UNPRIVILEGED_PROGRAM_STATUS_WORD ( 0x000010FFUL ) /* IO Level 0, MPU Register Set 1 and Call Depth Counting disabled. */
+#define portINITIAL_PCXI_UPPER_CONTEXT_WORD ( 0x00C00000UL ) /* The lower 20 bits identify the CSA address. */
+#define portINITIAL_SYSCON ( 0x00000000UL ) /* MPU Disable. */
+
+/* CSA manipulation macros. */
+#define portCSA_FCX_MASK ( 0x000FFFFFUL )
+
+/* OS Interrupt and Trap mechanisms. */
+#define portRESTORE_PSW_MASK ( ~( 0x000000FFUL ) )
+#define portSYSCALL_TRAP ( 6 )
+
+/* Each CSA contains 16 words of data. */
+#define portNUM_WORDS_IN_CSA ( 16 )
+
+/* The interrupt enable bit in the PCP_SRC register. */
+#define portENABLE_CPU_INTERRUPT ( 1U << 12U )
+/*-----------------------------------------------------------*/
+
+/*
+ * Perform any hardware configuration necessary to generate the tick interrupt.
+ */
+static void prvSystemTickHandler( int ) __attribute__((longcall));
+static void prvSetupTimerInterrupt( void );
+
+/*
+ * Trap handler for yields.
+ */
+static void prvTrapYield( int iTrapIdentification );
+
+/*
+ * Priority 1 interrupt handler for yields pended from an interrupt.
+ */
+static void prvInterruptYield( int iTrapIdentification );
+
+/*-----------------------------------------------------------*/
+
+/* This reference is required by the save/restore context macros. */
+extern volatile uint32_t *pxCurrentTCB;
+
+/* Precalculate the compare match value at compile time. */
+static const uint32_t ulCompareMatchValue = ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ );
+
+/*-----------------------------------------------------------*/
+
+StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+uint32_t *pulUpperCSA = NULL;
+uint32_t *pulLowerCSA = NULL;
+
+ /* 16 Address Registers (4 Address registers are global), 16 Data
+ Registers, and 3 System Registers.
+
+ There are 3 registers that track the CSAs.
+ FCX points to the head of globally free set of CSAs.
+ PCX for the task needs to point to Lower->Upper->NULL arrangement.
+ LCX points to the last free CSA so that corrective action can be taken.
+
+ Need two CSAs to store the context of a task.
+ The upper context contains D8-D15, A10-A15, PSW and PCXI->NULL.
+ The lower context contains D0-D7, A2-A7, A11 and PCXI->UpperContext.
+ The pxCurrentTCB->pxTopOfStack points to the Lower Context RSLCX matching the initial BISR.
+ The Lower Context points to the Upper Context ready for the return from the interrupt handler.
+
+ The Real stack pointer for the task is stored in the A10 which is restored
+ with the upper context. */
+
+ /* Have to disable interrupts here because the CSAs are going to be
+ manipulated. */
+ portENTER_CRITICAL();
+ {
+ /* DSync to ensure that buffering is not a problem. */
+ _dsync();
+
+ /* Consume two free CSAs. */
+ pulLowerCSA = portCSA_TO_ADDRESS( __MFCR( $FCX ) );
+ if( NULL != pulLowerCSA )
+ {
+ /* The Lower Links to the Upper. */
+ pulUpperCSA = portCSA_TO_ADDRESS( pulLowerCSA[ 0 ] );
+ }
+
+ /* Check that we have successfully reserved two CSAs. */
+ if( ( NULL != pulLowerCSA ) && ( NULL != pulUpperCSA ) )
+ {
+ /* Remove the two consumed CSAs from the free CSA list. */
+ _disable();
+ _dsync();
+ _mtcr( $FCX, pulUpperCSA[ 0 ] );
+ _isync();
+ _enable();
+ }
+ else
+ {
+ /* Simply trigger a context list depletion trap. */
+ _svlcx();
+ }
+ }
+ portEXIT_CRITICAL();
+
+ /* Clear the upper CSA. */
+ memset( pulUpperCSA, 0, portNUM_WORDS_IN_CSA * sizeof( uint32_t ) );
+
+ /* Upper Context. */
+ pulUpperCSA[ 2 ] = ( uint32_t )pxTopOfStack; /* A10; Stack Return aka Stack Pointer */
+ pulUpperCSA[ 1 ] = portSYSTEM_PROGRAM_STATUS_WORD; /* PSW */
+
+ /* Clear the lower CSA. */
+ memset( pulLowerCSA, 0, portNUM_WORDS_IN_CSA * sizeof( uint32_t ) );
+
+ /* Lower Context. */
+ pulLowerCSA[ 8 ] = ( uint32_t ) pvParameters; /* A4; Address Type Parameter Register */
+ pulLowerCSA[ 1 ] = ( uint32_t ) pxCode; /* A11; Return Address aka RA */
+
+ /* PCXI pointing to the Upper context. */
+ pulLowerCSA[ 0 ] = ( portINITIAL_PCXI_UPPER_CONTEXT_WORD | ( uint32_t ) portADDRESS_TO_CSA( pulUpperCSA ) );
+
+ /* Save the link to the CSA in the top of stack. */
+ pxTopOfStack = (uint32_t * ) portADDRESS_TO_CSA( pulLowerCSA );
+
+ /* DSync to ensure that buffering is not a problem. */
+ _dsync();
+
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+int32_t xPortStartScheduler( void )
+{
+extern void vTrapInstallHandlers( void );
+uint32_t ulMFCR = 0UL;
+uint32_t *pulUpperCSA = NULL;
+uint32_t *pulLowerCSA = NULL;
+
+ /* Interrupts at or below configMAX_SYSCALL_INTERRUPT_PRIORITY are disable
+ when this function is called. */
+
+ /* Set-up the timer interrupt. */
+ prvSetupTimerInterrupt();
+
+ /* Install the Trap Handlers. */
+ vTrapInstallHandlers();
+
+ /* Install the Syscall Handler for yield calls. */
+ if( 0 == _install_trap_handler( portSYSCALL_TRAP, prvTrapYield ) )
+ {
+ /* Failed to install the yield handler, force an assert. */
+ configASSERT( ( ( volatile void * ) NULL ) );
+ }
+
+ /* Enable then install the priority 1 interrupt for pending context
+ switches from an ISR. See mod_SRC in the TriCore manual. */
+ CPU_SRC0.reg = ( portENABLE_CPU_INTERRUPT ) | ( configKERNEL_YIELD_PRIORITY );
+ if( 0 == _install_int_handler( configKERNEL_YIELD_PRIORITY, prvInterruptYield, 0 ) )
+ {
+ /* Failed to install the yield handler, force an assert. */
+ configASSERT( ( ( volatile void * ) NULL ) );
+ }
+
+ _disable();
+
+ /* Load the initial SYSCON. */
+ _mtcr( $SYSCON, portINITIAL_SYSCON );
+ _isync();
+
+ /* ENDINIT has already been applied in the 'cstart.c' code. */
+
+ /* Clear the PSW.CDC to enable the use of an RFE without it generating an
+ exception because this code is not genuinely in an exception. */
+ ulMFCR = __MFCR( $PSW );
+ ulMFCR &= portRESTORE_PSW_MASK;
+ _dsync();
+ _mtcr( $PSW, ulMFCR );
+ _isync();
+
+ /* Finally, perform the equivalent of a portRESTORE_CONTEXT() */
+ pulLowerCSA = portCSA_TO_ADDRESS( ( *pxCurrentTCB ) );
+ pulUpperCSA = portCSA_TO_ADDRESS( pulLowerCSA[0] );
+ _dsync();
+ _mtcr( $PCXI, *pxCurrentTCB );
+ _isync();
+ _nop();
+ _rslcx();
+ _nop();
+
+ /* Return to the first task selected to execute. */
+ __asm volatile( "rfe" );
+
+ /* Will not get here. */
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+ /* Set-up the clock divider. */
+ unlock_wdtcon();
+ {
+ /* Wait until access to Endint protected register is enabled. */
+ while( 0 != ( WDT_CON0.reg & 0x1UL ) );
+
+ /* RMC == 1 so STM Clock == FPI */
+ STM_CLC.reg = ( 1UL << 8 );
+ }
+ lock_wdtcon();
+
+ /* Determine how many bits are used without changing other bits in the CMCON register. */
+ STM_CMCON.reg &= ~( 0x1fUL );
+ STM_CMCON.reg |= ( 0x1fUL - __CLZ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ ) );
+
+ /* Take into account the current time so a tick doesn't happen immediately. */
+ STM_CMP0.reg = ulCompareMatchValue + STM_TIM0.reg;
+
+ if( 0 != _install_int_handler( configKERNEL_INTERRUPT_PRIORITY, prvSystemTickHandler, 0 ) )
+ {
+ /* Set-up the interrupt. */
+ STM_SRC0.reg = ( configKERNEL_INTERRUPT_PRIORITY | 0x00005000UL );
+
+ /* Enable the Interrupt. */
+ STM_ISRR.reg &= ~( 0x03UL );
+ STM_ISRR.reg |= 0x1UL;
+ STM_ISRR.reg &= ~( 0x07UL );
+ STM_ICR.reg |= 0x1UL;
+ }
+ else
+ {
+ /* Failed to install the Tick Interrupt. */
+ configASSERT( ( ( volatile void * ) NULL ) );
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void prvSystemTickHandler( int iArg )
+{
+uint32_t ulSavedInterruptMask;
+uint32_t *pxUpperCSA = NULL;
+uint32_t xUpperCSA = 0UL;
+extern volatile uint32_t *pxCurrentTCB;
+int32_t lYieldRequired;
+
+ /* Just to avoid compiler warnings about unused parameters. */
+ ( void ) iArg;
+
+ /* Clear the interrupt source. */
+ STM_ISRR.reg = 1UL;
+
+ /* Reload the Compare Match register for X ticks into the future.
+
+ If critical section or interrupt nesting budgets are exceeded, then
+ it is possible that the calculated next compare match value is in the
+ past. If this occurs (unlikely), it is possible that the resulting
+ time slippage will exceed a single tick period. Any adverse effect of
+ this is time bounded by the fact that only the first n bits of the 56 bit
+ STM timer are being used for a compare match, so another compare match
+ will occur after an overflow in just those n bits (not the entire 56 bits).
+ As an example, if the peripheral clock is 75MHz, and the tick rate is 1KHz,
+ a missed tick could result in the next tick interrupt occurring within a
+ time that is 1.7 times the desired period. The fact that this is greater
+ than a single tick period is an effect of using a timer that cannot be
+ automatically reset, in hardware, by the occurrence of a tick interrupt.
+ Changing the tick source to a timer that has an automatic reset on compare
+ match (such as a GPTA timer) will reduce the maximum possible additional
+ period to exactly 1 times the desired period. */
+ STM_CMP0.reg += ulCompareMatchValue;
+
+ /* Kernel API calls require Critical Sections. */
+ ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
+ {
+ /* Increment the Tick. */
+ lYieldRequired = xTaskIncrementTick();
+ }
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
+
+ if( lYieldRequired != pdFALSE )
+ {
+ /* Save the context of a task.
+ The upper context is automatically saved when entering a trap or interrupt.
+ Need to save the lower context as well and copy the PCXI CSA ID into
+ pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
+ TCB of a task.
+
+ Call vTaskSwitchContext to select the next task, note that this changes the
+ value of pxCurrentTCB so that it needs to be reloaded.
+
+ Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
+ that has just been switched in.
+
+ Load the context of the task.
+ Need to restore the lower context by loading the CSA from
+ pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
+ In the Interrupt handler post-amble, RSLCX will restore the lower context
+ of the task. RFE will restore the upper context of the task, jump to the
+ return address and restore the previous state of interrupts being
+ enabled/disabled. */
+ _disable();
+ _dsync();
+ xUpperCSA = __MFCR( $PCXI );
+ pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA );
+ *pxCurrentTCB = pxUpperCSA[ 0 ];
+ vTaskSwitchContext();
+ pxUpperCSA[ 0 ] = *pxCurrentTCB;
+ CPU_SRC0.bits.SETR = 0;
+ _isync();
+ }
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * When a task is deleted, it is yielded permanently until the IDLE task
+ * has an opportunity to reclaim the memory that that task was using.
+ * Typically, the memory used by a task is the TCB and Stack but in the
+ * TriCore this includes the CSAs that were consumed as part of the Call
+ * Stack. These CSAs can only be returned to the Globally Free Pool when
+ * they are not part of the current Call Stack, hence, delaying the
+ * reclamation until the IDLE task is freeing the task's other resources.
+ * This function uses the head of the linked list of CSAs (from when the
+ * task yielded for the last time) and finds the tail (the very bottom of
+ * the call stack) and inserts this list at the head of the Free list,
+ * attaching the existing Free List to the tail of the reclaimed call stack.
+ *
+ * NOTE: the IDLE task needs processing time to complete this function
+ * and in heavily loaded systems, the Free CSAs may be consumed faster
+ * than they can be freed assuming that tasks are being spawned and
+ * deleted frequently.
+ */
+void vPortReclaimCSA( uint32_t *pxTCB )
+{
+uint32_t pxHeadCSA, pxTailCSA, pxFreeCSA;
+uint32_t *pulNextCSA;
+
+ /* A pointer to the first CSA in the list of CSAs consumed by the task is
+ stored in the first element of the tasks TCB structure (where the stack
+ pointer would be on a traditional stack based architecture). */
+ pxHeadCSA = ( *pxTCB ) & portCSA_FCX_MASK;
+
+ /* Mask off everything in the CSA link field other than the address. If
+ the address is NULL, then the CSA is not linking anywhere and there is
+ nothing to do. */
+ pxTailCSA = pxHeadCSA;
+
+ /* Convert the link value to contain just a raw address and store this
+ in a local variable. */
+ pulNextCSA = portCSA_TO_ADDRESS( pxTailCSA );
+
+ /* Iterate over the CSAs that were consumed as part of the task. The
+ first field in the CSA is the pointer to then next CSA. Mask off
+ everything in the pointer to the next CSA, other than the link address.
+ If this is NULL, then the CSA currently being pointed to is the last in
+ the chain. */
+ while( 0UL != ( pulNextCSA[ 0 ] & portCSA_FCX_MASK ) )
+ {
+ /* Clear all bits of the pointer to the next in the chain, other
+ than the address bits themselves. */
+ pulNextCSA[ 0 ] = pulNextCSA[ 0 ] & portCSA_FCX_MASK;
+
+ /* Move the pointer to point to the next CSA in the list. */
+ pxTailCSA = pulNextCSA[ 0 ];
+
+ /* Update the local pointer to the CSA. */
+ pulNextCSA = portCSA_TO_ADDRESS( pxTailCSA );
+ }
+
+ _disable();
+ {
+ /* Look up the current free CSA head. */
+ _dsync();
+ pxFreeCSA = __MFCR( $FCX );
+
+ /* Join the current Free onto the Tail of what is being reclaimed. */
+ portCSA_TO_ADDRESS( pxTailCSA )[ 0 ] = pxFreeCSA;
+
+ /* Move the head of the reclaimed into the Free. */
+ _dsync();
+ _mtcr( $FCX, pxHeadCSA );
+ _isync();
+ }
+ _enable();
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+ /* Nothing to do. Unlikely to want to end. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvTrapYield( int iTrapIdentification )
+{
+uint32_t *pxUpperCSA = NULL;
+uint32_t xUpperCSA = 0UL;
+extern volatile uint32_t *pxCurrentTCB;
+
+ switch( iTrapIdentification )
+ {
+ case portSYSCALL_TASK_YIELD:
+ /* Save the context of a task.
+ The upper context is automatically saved when entering a trap or interrupt.
+ Need to save the lower context as well and copy the PCXI CSA ID into
+ pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
+ TCB of a task.
+
+ Call vTaskSwitchContext to select the next task, note that this changes the
+ value of pxCurrentTCB so that it needs to be reloaded.
+
+ Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
+ that has just been switched in.
+
+ Load the context of the task.
+ Need to restore the lower context by loading the CSA from
+ pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
+ In the Interrupt handler post-amble, RSLCX will restore the lower context
+ of the task. RFE will restore the upper context of the task, jump to the
+ return address and restore the previous state of interrupts being
+ enabled/disabled. */
+ _disable();
+ _dsync();
+ xUpperCSA = __MFCR( $PCXI );
+ pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA );
+ *pxCurrentTCB = pxUpperCSA[ 0 ];
+ vTaskSwitchContext();
+ pxUpperCSA[ 0 ] = *pxCurrentTCB;
+ CPU_SRC0.bits.SETR = 0;
+ _isync();
+ break;
+
+ default:
+ /* Unimplemented trap called. */
+ configASSERT( ( ( volatile void * ) NULL ) );
+ break;
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void prvInterruptYield( int iId )
+{
+uint32_t *pxUpperCSA = NULL;
+uint32_t xUpperCSA = 0UL;
+extern volatile uint32_t *pxCurrentTCB;
+
+ /* Just to remove compiler warnings. */
+ ( void ) iId;
+
+ /* Save the context of a task.
+ The upper context is automatically saved when entering a trap or interrupt.
+ Need to save the lower context as well and copy the PCXI CSA ID into
+ pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
+ TCB of a task.
+
+ Call vTaskSwitchContext to select the next task, note that this changes the
+ value of pxCurrentTCB so that it needs to be reloaded.
+
+ Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
+ that has just been switched in.
+
+ Load the context of the task.
+ Need to restore the lower context by loading the CSA from
+ pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
+ In the Interrupt handler post-amble, RSLCX will restore the lower context
+ of the task. RFE will restore the upper context of the task, jump to the
+ return address and restore the previous state of interrupts being
+ enabled/disabled. */
+ _disable();
+ _dsync();
+ xUpperCSA = __MFCR( $PCXI );
+ pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA );
+ *pxCurrentTCB = pxUpperCSA[ 0 ];
+ vTaskSwitchContext();
+ pxUpperCSA[ 0 ] = *pxCurrentTCB;
+ CPU_SRC0.bits.SETR = 0;
+ _isync();
+}
+/*-----------------------------------------------------------*/
+
+uint32_t uxPortSetInterruptMaskFromISR( void )
+{
+uint32_t uxReturn = 0UL;
+
+ _disable();
+ uxReturn = __MFCR( $ICR );
+ _mtcr( $ICR, ( ( uxReturn & ~portCCPN_MASK ) | configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
+ _isync();
+ _enable();
+
+ /* Return just the interrupt mask bits. */
+ return ( uxReturn & portCCPN_MASK );
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/TriCore_1782/portmacro.h b/portable/GCC/TriCore_1782/portmacro.h
index 5224594..4e51954 100644
--- a/portable/GCC/TriCore_1782/portmacro.h
+++ b/portable/GCC/TriCore_1782/portmacro.h
@@ -1,174 +1,174 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* System Includes. */
-#include <tc1782.h>
-#include <machine/intrinsics.h>
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT short
-#define portSTACK_TYPE uint32_t
-#define portBASE_TYPE long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
-#else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
- /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*---------------------------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH ( -1 )
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT 4
-#define portNOP() __asm volatile( " nop " )
-#define portCRITICAL_NESTING_IN_TCB 1
-#define portRESTORE_FIRST_TASK_PRIORITY_LEVEL 1
-
-
-/*---------------------------------------------------------------------------*/
-
-typedef struct MPU_SETTINGS { uint32_t ulNotUsed; } xMPU_SETTINGS;
-
-/* Define away the instruction from the Restore Context Macro. */
-#define portPRIVILEGE_BIT 0x0UL
-
-#define portCCPN_MASK ( 0x000000FFUL )
-
-extern void vTaskEnterCritical( void );
-extern void vTaskExitCritical( void );
-#define portENTER_CRITICAL() vTaskEnterCritical()
-#define portEXIT_CRITICAL() vTaskExitCritical()
-/*---------------------------------------------------------------------------*/
-
-/* CSA Manipulation. */
-#define portCSA_TO_ADDRESS( pCSA ) ( ( uint32_t * )( ( ( ( pCSA ) & 0x000F0000 ) << 12 ) | ( ( ( pCSA ) & 0x0000FFFF ) << 6 ) ) )
-#define portADDRESS_TO_CSA( pAddress ) ( ( uint32_t )( ( ( ( (uint32_t)( pAddress ) ) & 0xF0000000 ) >> 12 ) | ( ( ( uint32_t )( pAddress ) & 0x003FFFC0 ) >> 6 ) ) )
-/*---------------------------------------------------------------------------*/
-
-#define portYIELD() _syscall( 0 )
-/* Port Restore is implicit in the platform when the function is returned from the original PSW is automatically replaced. */
-#define portSYSCALL_TASK_YIELD 0
-#define portSYSCALL_RAISE_PRIORITY 1
-/*---------------------------------------------------------------------------*/
-
-/* Critical section management. */
-
-/* Set ICR.CCPN to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-#define portDISABLE_INTERRUPTS() { \
- uint32_t ulICR; \
- _disable(); \
- ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \
- ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \
- ulICR |= configMAX_SYSCALL_INTERRUPT_PRIORITY; /* Set mask bits to required priority mask. */ \
- _mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \
- _isync(); \
- _enable(); \
- }
-
-/* Clear ICR.CCPN to allow all interrupt priorities. */
-#define portENABLE_INTERRUPTS() { \
- uint32_t ulICR; \
- _disable(); \
- ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \
- ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \
- _mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \
- _isync(); \
- _enable(); \
- }
-
-/* Set ICR.CCPN to uxSavedMaskValue. */
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedMaskValue ) { \
- uint32_t ulICR; \
- _disable(); \
- ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \
- ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \
- ulICR |= uxSavedMaskValue; /* Set mask bits to previously saved mask value. */ \
- _mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \
- _isync(); \
- _enable(); \
- }
-
-
-/* Set ICR.CCPN to configMAX_SYSCALL_INTERRUPT_PRIORITY */
-extern uint32_t uxPortSetInterruptMaskFromISR( void );
-#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
-
-/* Pend a priority 1 interrupt, which will take care of the context switch. */
-#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) do { if( xHigherPriorityTaskWoken != pdFALSE ) { CPU_SRC0.bits.SETR = 1; _isync(); } } while( 0 )
-
-/*---------------------------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-/*---------------------------------------------------------------------------*/
-
-/*
- * Port specific clean up macro required to free the CSAs that were consumed by
- * a task that has since been deleted.
- */
-void vPortReclaimCSA( uint32_t *pxTCB );
-#define portCLEAN_UP_TCB( pxTCB ) vPortReclaimCSA( ( uint32_t * ) ( pxTCB ) )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* System Includes. */
+#include <tc1782.h>
+#include <machine/intrinsics.h>
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*---------------------------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 4
+#define portNOP() __asm volatile( " nop " )
+#define portCRITICAL_NESTING_IN_TCB 1
+#define portRESTORE_FIRST_TASK_PRIORITY_LEVEL 1
+
+
+/*---------------------------------------------------------------------------*/
+
+typedef struct MPU_SETTINGS { uint32_t ulNotUsed; } xMPU_SETTINGS;
+
+/* Define away the instruction from the Restore Context Macro. */
+#define portPRIVILEGE_BIT 0x0UL
+
+#define portCCPN_MASK ( 0x000000FFUL )
+
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL() vTaskEnterCritical()
+#define portEXIT_CRITICAL() vTaskExitCritical()
+/*---------------------------------------------------------------------------*/
+
+/* CSA Manipulation. */
+#define portCSA_TO_ADDRESS( pCSA ) ( ( uint32_t * )( ( ( ( pCSA ) & 0x000F0000 ) << 12 ) | ( ( ( pCSA ) & 0x0000FFFF ) << 6 ) ) )
+#define portADDRESS_TO_CSA( pAddress ) ( ( uint32_t )( ( ( ( (uint32_t)( pAddress ) ) & 0xF0000000 ) >> 12 ) | ( ( ( uint32_t )( pAddress ) & 0x003FFFC0 ) >> 6 ) ) )
+/*---------------------------------------------------------------------------*/
+
+#define portYIELD() _syscall( 0 )
+/* Port Restore is implicit in the platform when the function is returned from the original PSW is automatically replaced. */
+#define portSYSCALL_TASK_YIELD 0
+#define portSYSCALL_RAISE_PRIORITY 1
+/*---------------------------------------------------------------------------*/
+
+/* Critical section management. */
+
+/* Set ICR.CCPN to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+#define portDISABLE_INTERRUPTS() { \
+ uint32_t ulICR; \
+ _disable(); \
+ ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \
+ ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \
+ ulICR |= configMAX_SYSCALL_INTERRUPT_PRIORITY; /* Set mask bits to required priority mask. */ \
+ _mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \
+ _isync(); \
+ _enable(); \
+ }
+
+/* Clear ICR.CCPN to allow all interrupt priorities. */
+#define portENABLE_INTERRUPTS() { \
+ uint32_t ulICR; \
+ _disable(); \
+ ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \
+ ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \
+ _mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \
+ _isync(); \
+ _enable(); \
+ }
+
+/* Set ICR.CCPN to uxSavedMaskValue. */
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedMaskValue ) { \
+ uint32_t ulICR; \
+ _disable(); \
+ ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \
+ ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \
+ ulICR |= uxSavedMaskValue; /* Set mask bits to previously saved mask value. */ \
+ _mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \
+ _isync(); \
+ _enable(); \
+ }
+
+
+/* Set ICR.CCPN to configMAX_SYSCALL_INTERRUPT_PRIORITY */
+extern uint32_t uxPortSetInterruptMaskFromISR( void );
+#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
+
+/* Pend a priority 1 interrupt, which will take care of the context switch. */
+#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) do { if( xHigherPriorityTaskWoken != pdFALSE ) { CPU_SRC0.bits.SETR = 1; _isync(); } } while( 0 )
+
+/*---------------------------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*---------------------------------------------------------------------------*/
+
+/*
+ * Port specific clean up macro required to free the CSAs that were consumed by
+ * a task that has since been deleted.
+ */
+void vPortReclaimCSA( uint32_t *pxTCB );
+#define portCLEAN_UP_TCB( pxTCB ) vPortReclaimCSA( ( uint32_t * ) ( pxTCB ) )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/portable/GCC/TriCore_1782/porttrap.c b/portable/GCC/TriCore_1782/porttrap.c
index c34a3de..79d6ea0 100644
--- a/portable/GCC/TriCore_1782/porttrap.c
+++ b/portable/GCC/TriCore_1782/porttrap.c
@@ -1,282 +1,282 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/* Kernel includes. */
-#include "FreeRTOS.h"
-
-/* Machine includes */
-#include <tc1782.h>
-#include <machine/intrinsics.h>
-#include <machine/cint.h>
-/*---------------------------------------------------------------------------*/
-
-/*
- * This reference is required by the Save/Restore Context Macros.
- */
-extern volatile uint32_t *pxCurrentTCB;
-/*-----------------------------------------------------------*/
-
-/*
- * This file contains base definitions for all of the possible traps in the system.
- * It is suggested to provide implementations for all of the traps but for
- * the time being they simply trigger a DEBUG instruction so that it is easy
- * to see what caused a particular trap.
- *
- * Trap Class 6, the SYSCALL, is used exclusively by the operating system.
- */
-
-/* The Trap Classes. */
-#define portMMU_TRAP 0
-#define portIPT_TRAP 1
-#define portIE_TRAP 2
-#define portCM_TRAP 3
-#define portSBP_TRAP 4
-#define portASSERT_TRAP 5
-#define portNMI_TRAP 7
-
-/* MMU Trap Identifications. */
-#define portTIN_MMU_VIRTUAL_ADDRESS_FILL 0
-#define portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION 1
-
-/* Internal Protection Trap Identifications. */
-#define portTIN_IPT_PRIVILIGED_INSTRUCTION 1
-#define portTIN_IPT_MEMORY_PROTECTION_READ 2
-#define portTIN_IPT_MEMORY_PROTECTION_WRITE 3
-#define portTIN_IPT_MEMORY_PROTECTION_EXECUTION 4
-#define portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS 5
-#define portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS 6
-#define portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION 7
-
-/* Instruction Error Trap Identifications. */
-#define portTIN_IE_ILLEGAL_OPCODE 1
-#define portTIN_IE_UNIMPLEMENTED_OPCODE 2
-#define portTIN_IE_INVALID_OPERAND 3
-#define portTIN_IE_DATA_ADDRESS_ALIGNMENT 4
-#define portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS 5
-
-/* Context Management Trap Identifications. */
-#define portTIN_CM_FREE_CONTEXT_LIST_DEPLETION 1
-#define portTIN_CM_CALL_DEPTH_OVERFLOW 2
-#define portTIN_CM_CALL_DEPTH_UNDEFLOW 3
-#define portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW 4
-#define portTIN_CM_CALL_STACK_UNDERFLOW 5
-#define portTIN_CM_CONTEXT_TYPE 6
-#define portTIN_CM_NESTING_ERROR 7
-
-/* System Bus and Peripherals Trap Identifications. */
-#define portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR 1
-#define portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR 2
-#define portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR 3
-#define portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR 4
-#define portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR 5
-#define portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR 6
-
-/* Assertion Trap Identifications. */
-#define portTIN_ASSERT_ARITHMETIC_OVERFLOW 1
-#define portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW 2
-
-/* Non-maskable Interrupt Trap Identifications. */
-#define portTIN_NMI_NON_MASKABLE_INTERRUPT 0
-/*---------------------------------------------------------------------------*/
-
-void vMMUTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
-void vInternalProtectionTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
-void vInstructionErrorTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
-void vContextManagementTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
-void vSystemBusAndPeripheralsTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
-void vAssertionTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
-void vNonMaskableInterruptTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
-/*---------------------------------------------------------------------------*/
-
-void vTrapInstallHandlers( void )
-{
- if( 0 == _install_trap_handler ( portMMU_TRAP, vMMUTrap ) )
- {
- _debug();
- }
-
- if( 0 == _install_trap_handler ( portIPT_TRAP, vInternalProtectionTrap ) )
- {
- _debug();
- }
-
- if( 0 == _install_trap_handler ( portIE_TRAP, vInstructionErrorTrap ) )
- {
- _debug();
- }
-
- if( 0 == _install_trap_handler ( portCM_TRAP, vContextManagementTrap ) )
- {
- _debug();
- }
-
- if( 0 == _install_trap_handler ( portSBP_TRAP, vSystemBusAndPeripheralsTrap ) )
- {
- _debug();
- }
-
- if( 0 == _install_trap_handler ( portASSERT_TRAP, vAssertionTrap ) )
- {
- _debug();
- }
-
- if( 0 == _install_trap_handler ( portNMI_TRAP, vNonMaskableInterruptTrap ) )
- {
- _debug();
- }
-}
-/*-----------------------------------------------------------*/
-
-void vMMUTrap( int iTrapIdentification )
-{
- switch( iTrapIdentification )
- {
- case portTIN_MMU_VIRTUAL_ADDRESS_FILL:
- case portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION:
- default:
- _debug();
- break;
- }
-}
-/*---------------------------------------------------------------------------*/
-
-void vInternalProtectionTrap( int iTrapIdentification )
-{
- /* Deliberate fall through to default. */
- switch( iTrapIdentification )
- {
- case portTIN_IPT_PRIVILIGED_INSTRUCTION:
- /* Instruction is not allowed at current execution level, eg DISABLE at User-0. */
-
- case portTIN_IPT_MEMORY_PROTECTION_READ:
- /* Load word using invalid address. */
-
- case portTIN_IPT_MEMORY_PROTECTION_WRITE:
- /* Store Word using invalid address. */
-
- case portTIN_IPT_MEMORY_PROTECTION_EXECUTION:
- /* PC jumped to an address outside of the valid range. */
-
- case portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS:
- /* Access to a peripheral denied at current execution level. */
-
- case portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS:
- /* NULL Pointer. */
-
- case portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION:
- /* Tried to modify a global address pointer register. */
-
- default:
-
- pxCurrentTCB[ 0 ] = __MFCR( $PCXI );
- _debug();
- break;
- }
-}
-/*---------------------------------------------------------------------------*/
-
-void vInstructionErrorTrap( int iTrapIdentification )
-{
- /* Deliberate fall through to default. */
- switch( iTrapIdentification )
- {
- case portTIN_IE_ILLEGAL_OPCODE:
- case portTIN_IE_UNIMPLEMENTED_OPCODE:
- case portTIN_IE_INVALID_OPERAND:
- case portTIN_IE_DATA_ADDRESS_ALIGNMENT:
- case portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS:
- default:
- _debug();
- break;
- }
-}
-/*---------------------------------------------------------------------------*/
-
-void vContextManagementTrap( int iTrapIdentification )
-{
- /* Deliberate fall through to default. */
- switch( iTrapIdentification )
- {
- case portTIN_CM_FREE_CONTEXT_LIST_DEPLETION:
- case portTIN_CM_CALL_DEPTH_OVERFLOW:
- case portTIN_CM_CALL_DEPTH_UNDEFLOW:
- case portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW:
- case portTIN_CM_CALL_STACK_UNDERFLOW:
- case portTIN_CM_CONTEXT_TYPE:
- case portTIN_CM_NESTING_ERROR:
- default:
- _debug();
- break;
- }
-}
-/*---------------------------------------------------------------------------*/
-
-void vSystemBusAndPeripheralsTrap( int iTrapIdentification )
-{
- /* Deliberate fall through to default. */
- switch( iTrapIdentification )
- {
- case portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR:
- case portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR:
- case portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR:
- case portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR:
- case portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR:
- case portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR:
- default:
- _debug();
- break;
- }
-}
-/*---------------------------------------------------------------------------*/
-
-void vAssertionTrap( int iTrapIdentification )
-{
- /* Deliberate fall through to default. */
- switch( iTrapIdentification )
- {
- case portTIN_ASSERT_ARITHMETIC_OVERFLOW:
- case portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW:
- default:
- _debug();
- break;
- }
-}
-/*---------------------------------------------------------------------------*/
-
-void vNonMaskableInterruptTrap( int iTrapIdentification )
-{
- /* Deliberate fall through to default. */
- switch( iTrapIdentification )
- {
- case portTIN_NMI_NON_MASKABLE_INTERRUPT:
- default:
- _debug();
- break;
- }
-}
-/*---------------------------------------------------------------------------*/
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+
+/* Machine includes */
+#include <tc1782.h>
+#include <machine/intrinsics.h>
+#include <machine/cint.h>
+/*---------------------------------------------------------------------------*/
+
+/*
+ * This reference is required by the Save/Restore Context Macros.
+ */
+extern volatile uint32_t *pxCurrentTCB;
+/*-----------------------------------------------------------*/
+
+/*
+ * This file contains base definitions for all of the possible traps in the system.
+ * It is suggested to provide implementations for all of the traps but for
+ * the time being they simply trigger a DEBUG instruction so that it is easy
+ * to see what caused a particular trap.
+ *
+ * Trap Class 6, the SYSCALL, is used exclusively by the operating system.
+ */
+
+/* The Trap Classes. */
+#define portMMU_TRAP 0
+#define portIPT_TRAP 1
+#define portIE_TRAP 2
+#define portCM_TRAP 3
+#define portSBP_TRAP 4
+#define portASSERT_TRAP 5
+#define portNMI_TRAP 7
+
+/* MMU Trap Identifications. */
+#define portTIN_MMU_VIRTUAL_ADDRESS_FILL 0
+#define portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION 1
+
+/* Internal Protection Trap Identifications. */
+#define portTIN_IPT_PRIVILIGED_INSTRUCTION 1
+#define portTIN_IPT_MEMORY_PROTECTION_READ 2
+#define portTIN_IPT_MEMORY_PROTECTION_WRITE 3
+#define portTIN_IPT_MEMORY_PROTECTION_EXECUTION 4
+#define portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS 5
+#define portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS 6
+#define portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION 7
+
+/* Instruction Error Trap Identifications. */
+#define portTIN_IE_ILLEGAL_OPCODE 1
+#define portTIN_IE_UNIMPLEMENTED_OPCODE 2
+#define portTIN_IE_INVALID_OPERAND 3
+#define portTIN_IE_DATA_ADDRESS_ALIGNMENT 4
+#define portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS 5
+
+/* Context Management Trap Identifications. */
+#define portTIN_CM_FREE_CONTEXT_LIST_DEPLETION 1
+#define portTIN_CM_CALL_DEPTH_OVERFLOW 2
+#define portTIN_CM_CALL_DEPTH_UNDEFLOW 3
+#define portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW 4
+#define portTIN_CM_CALL_STACK_UNDERFLOW 5
+#define portTIN_CM_CONTEXT_TYPE 6
+#define portTIN_CM_NESTING_ERROR 7
+
+/* System Bus and Peripherals Trap Identifications. */
+#define portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR 1
+#define portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR 2
+#define portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR 3
+#define portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR 4
+#define portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR 5
+#define portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR 6
+
+/* Assertion Trap Identifications. */
+#define portTIN_ASSERT_ARITHMETIC_OVERFLOW 1
+#define portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW 2
+
+/* Non-maskable Interrupt Trap Identifications. */
+#define portTIN_NMI_NON_MASKABLE_INTERRUPT 0
+/*---------------------------------------------------------------------------*/
+
+void vMMUTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
+void vInternalProtectionTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
+void vInstructionErrorTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
+void vContextManagementTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
+void vSystemBusAndPeripheralsTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
+void vAssertionTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
+void vNonMaskableInterruptTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
+/*---------------------------------------------------------------------------*/
+
+void vTrapInstallHandlers( void )
+{
+ if( 0 == _install_trap_handler ( portMMU_TRAP, vMMUTrap ) )
+ {
+ _debug();
+ }
+
+ if( 0 == _install_trap_handler ( portIPT_TRAP, vInternalProtectionTrap ) )
+ {
+ _debug();
+ }
+
+ if( 0 == _install_trap_handler ( portIE_TRAP, vInstructionErrorTrap ) )
+ {
+ _debug();
+ }
+
+ if( 0 == _install_trap_handler ( portCM_TRAP, vContextManagementTrap ) )
+ {
+ _debug();
+ }
+
+ if( 0 == _install_trap_handler ( portSBP_TRAP, vSystemBusAndPeripheralsTrap ) )
+ {
+ _debug();
+ }
+
+ if( 0 == _install_trap_handler ( portASSERT_TRAP, vAssertionTrap ) )
+ {
+ _debug();
+ }
+
+ if( 0 == _install_trap_handler ( portNMI_TRAP, vNonMaskableInterruptTrap ) )
+ {
+ _debug();
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vMMUTrap( int iTrapIdentification )
+{
+ switch( iTrapIdentification )
+ {
+ case portTIN_MMU_VIRTUAL_ADDRESS_FILL:
+ case portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION:
+ default:
+ _debug();
+ break;
+ }
+}
+/*---------------------------------------------------------------------------*/
+
+void vInternalProtectionTrap( int iTrapIdentification )
+{
+ /* Deliberate fall through to default. */
+ switch( iTrapIdentification )
+ {
+ case portTIN_IPT_PRIVILIGED_INSTRUCTION:
+ /* Instruction is not allowed at current execution level, eg DISABLE at User-0. */
+
+ case portTIN_IPT_MEMORY_PROTECTION_READ:
+ /* Load word using invalid address. */
+
+ case portTIN_IPT_MEMORY_PROTECTION_WRITE:
+ /* Store Word using invalid address. */
+
+ case portTIN_IPT_MEMORY_PROTECTION_EXECUTION:
+ /* PC jumped to an address outside of the valid range. */
+
+ case portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS:
+ /* Access to a peripheral denied at current execution level. */
+
+ case portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS:
+ /* NULL Pointer. */
+
+ case portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION:
+ /* Tried to modify a global address pointer register. */
+
+ default:
+
+ pxCurrentTCB[ 0 ] = __MFCR( $PCXI );
+ _debug();
+ break;
+ }
+}
+/*---------------------------------------------------------------------------*/
+
+void vInstructionErrorTrap( int iTrapIdentification )
+{
+ /* Deliberate fall through to default. */
+ switch( iTrapIdentification )
+ {
+ case portTIN_IE_ILLEGAL_OPCODE:
+ case portTIN_IE_UNIMPLEMENTED_OPCODE:
+ case portTIN_IE_INVALID_OPERAND:
+ case portTIN_IE_DATA_ADDRESS_ALIGNMENT:
+ case portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS:
+ default:
+ _debug();
+ break;
+ }
+}
+/*---------------------------------------------------------------------------*/
+
+void vContextManagementTrap( int iTrapIdentification )
+{
+ /* Deliberate fall through to default. */
+ switch( iTrapIdentification )
+ {
+ case portTIN_CM_FREE_CONTEXT_LIST_DEPLETION:
+ case portTIN_CM_CALL_DEPTH_OVERFLOW:
+ case portTIN_CM_CALL_DEPTH_UNDEFLOW:
+ case portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW:
+ case portTIN_CM_CALL_STACK_UNDERFLOW:
+ case portTIN_CM_CONTEXT_TYPE:
+ case portTIN_CM_NESTING_ERROR:
+ default:
+ _debug();
+ break;
+ }
+}
+/*---------------------------------------------------------------------------*/
+
+void vSystemBusAndPeripheralsTrap( int iTrapIdentification )
+{
+ /* Deliberate fall through to default. */
+ switch( iTrapIdentification )
+ {
+ case portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR:
+ case portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR:
+ case portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR:
+ case portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR:
+ case portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR:
+ case portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR:
+ default:
+ _debug();
+ break;
+ }
+}
+/*---------------------------------------------------------------------------*/
+
+void vAssertionTrap( int iTrapIdentification )
+{
+ /* Deliberate fall through to default. */
+ switch( iTrapIdentification )
+ {
+ case portTIN_ASSERT_ARITHMETIC_OVERFLOW:
+ case portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW:
+ default:
+ _debug();
+ break;
+ }
+}
+/*---------------------------------------------------------------------------*/
+
+void vNonMaskableInterruptTrap( int iTrapIdentification )
+{
+ /* Deliberate fall through to default. */
+ switch( iTrapIdentification )
+ {
+ case portTIN_NMI_NON_MASKABLE_INTERRUPT:
+ default:
+ _debug();
+ break;
+ }
+}
+/*---------------------------------------------------------------------------*/
