blob: 8806a3936608571c7688bd7a83f176f73cec1522 [file] [log] [blame]
/*
* Copyright 2016-2018 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stdint.h>
#include "fsl_common.h"
#include "clock_config.h"
#include "board.h"
#include "fsl_debug_console.h"
/*******************************************************************************
* Variables
******************************************************************************/
/* Clock rate on the CLKIN pin */
const uint32_t ExtClockIn = BOARD_EXTCLKINRATE;
/*******************************************************************************
* Code
******************************************************************************/
/* Initialize debug console. */
status_t BOARD_InitDebugConsole(void)
{
status_t result;
/* attach 12 MHz clock to FLEXCOMM0 (debug console) */
CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
RESET_PeripheralReset(BOARD_DEBUG_UART_RST);
result = DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE,
BOARD_DEBUG_UART_CLK_FREQ);
assert(kStatus_Success == result);
return result;
}