blob: 14222fb204ab4ec77ceb7a93c205239e5aa66b04 [file] [log] [blame]
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/**
* @file asm_vectors.s
*
* This file contains the initial vector table for the Cortex R5 processor
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------- -------- ---------------------------------------------------
* 5.00 pkp 02/10/14 Initial version
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
.org 0
.text
.globl _boot
.globl _freertos_vector_table
.globl FreeRTOS_FIQInterrupt
.globl FreeRTOS_DataAbortHandler
.globl FreeRTOS_PrefetchAbortHandler
.globl vPortInstallFreeRTOSVectorTable
.globl IRQHandler
.globl prof_pc
.extern FreeRTOS_IRQ_Handler
.extern FreeRTOS_SWI_Handler
.section .freertos_vectors
_freertos_vector_table:
ldr pc,=_boot
ldr pc,=FreeRTOS_Undefined
LDR pc, _swi
ldr pc,=FreeRTOS_PrefetchAbortHandler
ldr pc,=FreeRTOS_DataAbortHandler
NOP /* Placeholder for address exception vector*/
LDR pc, _irq
ldr pc,=FreeRTOS_FIQHandler
_irq: .word FreeRTOS_IRQ_Handler
_swi: .word FreeRTOS_SWI_Handler
.text
FreeRTOS_FIQHandler: /* FIQ vector handler */
stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
FreeRTOS_FIQLoop:
bl FIQInterrupt /* FIQ vector */
ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
subs pc, lr, #4 /* adjust return */
FreeRTOS_Undefined: /* Undefined handler */
b FreeRTOS_Undefined
FreeRTOS_DataAbortHandler: /* Data Abort handler */
b FreeRTOS_DataAbortHandler
FreeRTOS_PrefetchAbortHandler: /* Prefetch Abort handler */
b FreeRTOS_PrefetchAbortHandler
.end