Update Zynq, MPSoc Cortex-A53 and MPSoc Cortex-R5 demo projects to build with the 18.1 version of the Xilinx SDK - building BUT NOT YET TESTED.
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/Makefile new file mode 100644 index 0000000..a97e121 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/Makefile
@@ -0,0 +1,74 @@ +############################################################################### +# +# Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# Use of the Software is limited solely to applications: +# (a) running on a Xilinx device, or +# (b) that interact with a Xilinx device through a bus or interconnect. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. +# +# Except as contained in this notice, the name of the Xilinx shall not be used +# in advertising or otherwise to promote the sale, use or other dealings in +# this Software without prior written authorization from Xilinx. +# +############################################################################### +include config.make + +CC=$(COMPILER) +AR=$(ARCHIVER) +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a +CC_FLAGS = $(subst -pg, -DPROFILING, $(COMPILER_FLAGS)) +ECC_FLAGS = $(subst -pg, -DPROFILING, $(EXTRA_COMPILER_FLAGS)) + +ECC_FLAGS += -nostartfiles\ + -march=armv8-a +ECC_FLAGS_NO_FLTO1 = $(subst -flto,,$(ECC_FLAGS)) +ECC_FLAGS_NO_FLTO = $(subst -ffat-lto-objects,,$(ECC_FLAGS_NO_FLTO1)) + + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +OUTS = *.o +OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) +ASSEMBLY_OBJECTS = $(addsuffix .o, $(basename $(wildcard *.S))) +INCLUDEFILES=*.h +INCLUDEFILES+=includes_ps/*.h +libs: $(LIBS) + +standalone_libs: $(LIBSOURCES) + echo "Compiling standalone A53" + $(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(filter-out _exit.c, $^) + $(CC) $(CC_FLAGS) $(ECC_FLAGS_NO_FLTO) $(INCLUDES) _exit.c + $(AR) -r ${RELEASEDIR}/${LIB} ${OUTS} + +.PHONY: include +include: standalone_includes + +standalone_includes: + ${CP} ${INCLUDEFILES} ${INCLUDEDIR} + +clean: + rm -rf ${OBJECTS} + rm -rf ${ASSEMBLY_OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/_exit.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/_exit.c new file mode 100644 index 0000000..cf59888 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/_exit.c
@@ -0,0 +1,44 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include <unistd.h> +#include "xil_types.h" + +/* _exit - Simple implementation. Does not return. +*/ +__attribute__((weak)) void _exit (sint32 status) +{ + (void)status; + while (1) { + ; + } +}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/_open.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/_open.c new file mode 100644 index 0000000..a108b77 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/_open.c
@@ -0,0 +1,54 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +#ifndef UNDEFINE_FILE_OPS +#include <errno.h> +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode); +} +#endif + +/* + * _open -- open a file descriptor. We don't have a filesystem, so + * we return an error. + */ +__attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode) +{ + (void)buf; + (void)flags; + (void)mode; + errno = EIO; + return (-1); +} +#endif
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/_sbrk.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/_sbrk.c new file mode 100644 index 0000000..967bdfc --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/_sbrk.c
@@ -0,0 +1,65 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include <sys/types.h> +#include "xil_types.h" + +extern u8 _heap_start[]; +extern u8 _heap_end[]; + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) caddr_t _sbrk ( s32 incr ); +} +#endif + +__attribute__((weak)) caddr_t _sbrk ( s32 incr ) +{ + static u8 *heap = NULL; + u8 *prev_heap; + static u8 *HeapEndPtr = (u8 *)&_heap_end; + caddr_t Status; + + if (heap == NULL) { + heap = (u8 *)&_heap_start; + } + prev_heap = heap; + + if (((heap + incr) <= HeapEndPtr) && (prev_heap != NULL)) { + heap += incr; + Status = (caddr_t) ((void *)prev_heap); + } else { + Status = (caddr_t) -1; + } + + return Status; +}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/abort.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/abort.c new file mode 100644 index 0000000..e8988c0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/abort.c
@@ -0,0 +1,42 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include <stdlib.h> +#include <unistd.h> + +/* + * abort -- go out via exit... + */ +__attribute__((weak)) void abort(void) +{ + _exit(1); +}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/asm_vectors.S b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/asm_vectors.S new file mode 100644 index 0000000..56bb9ae --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/asm_vectors.S
@@ -0,0 +1,374 @@ +/****************************************************************************** +* +* Copyright (C) 2014 - 2018 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file asm_vectors.s +* +* This file contains the initial vector table for the Cortex A53 processor +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ------- -------- --------------------------------------------------- +* 5.00 pkp 05/21/14 Initial version +* 6.02 pkp 12/21/16 Added support for floating point access +* 6.02 pkp 01/22/17 Added support for EL1 non-secure and hypervisor +* baremetal guest +* 6.4 mus 06/14/17 Fixed bug in IRQInterruptHandler code snippet, +* which checks for the FPEN bit of CPACR_EL1 +* 6.6 mus 01/19/18 Added isb after writing to the cpacr_el1/cptr_el3, +* to ensure enabling/disabling of floating-point unit +* is completed, before any subsequent instruction. +* +* </pre> +* +* @note +* +* None. +* +******************************************************************************/ + +#include "bspconfig.h" + +.org 0 +.text + +.globl _boot +.globl _vector_table + +.globl FIQInterrupt +.globl IRQInterrupt +.globl SErrorInterrupt +.globl SynchronousInterrupt +.globl FPUStatus + +/* + * FPUContextSize is the size of the array where floating point registers are + * stored when required. The default size corresponds to the case when there is no + * nested interrupt. If there are nested interrupts in application which are using + * floating point operation, the size of FPUContextSize need to be increased as per + * requirement + */ + +.set FPUContextSize, 528 + +.macro saveregister + stp X0,X1, [sp,#-0x10]! + stp X2,X3, [sp,#-0x10]! + stp X4,X5, [sp,#-0x10]! + stp X6,X7, [sp,#-0x10]! + stp X8,X9, [sp,#-0x10]! + stp X10,X11, [sp,#-0x10]! + stp X12,X13, [sp,#-0x10]! + stp X14,X15, [sp,#-0x10]! + stp X16,X17, [sp,#-0x10]! + stp X18,X19, [sp,#-0x10]! + stp X29,X30, [sp,#-0x10]! +.endm + +.macro restoreregister + ldp X29,X30, [sp], #0x10 + ldp X18,X19, [sp], #0x10 + ldp X16,X17, [sp], #0x10 + ldp X14,X15, [sp], #0x10 + ldp X12,X13, [sp], #0x10 + ldp X10,X11, [sp], #0x10 + ldp X8,X9, [sp], #0x10 + ldp X6,X7, [sp], #0x10 + ldp X4,X5, [sp], #0x10 + ldp X2,X3, [sp], #0x10 + ldp X0,X1, [sp], #0x10 +.endm + +.macro savefloatregister + +/* Load the floating point context array address from FPUContextBase */ + ldr x1,=FPUContextBase + ldr x0, [x1] + +/* Save all the floating point register to the array */ + stp q0,q1, [x0], #0x20 + stp q2,q3, [x0], #0x20 + stp q4,q5, [x0], #0x20 + stp q6,q7, [x0], #0x20 + stp q8,q9, [x0], #0x20 + stp q10,q11, [x0], #0x20 + stp q12,q13, [x0], #0x20 + stp q14,q15, [x0], #0x20 + stp q16,q17, [x0], #0x20 + stp q18,q19, [x0], #0x20 + stp q20,q21, [x0], #0x20 + stp q22,q23, [x0], #0x20 + stp q24,q25, [x0], #0x20 + stp q26,q27, [x0], #0x20 + stp q28,q29, [x0], #0x20 + stp q30,q31, [x0], #0x20 + mrs x2, FPCR + mrs x3, FPSR + stp x2, x3, [x0], #0x10 + +/* Save current address of floating point context array to FPUContextBase */ + str x0, [x1] +.endm + +.macro restorefloatregister + +/* Restore the address of floating point context array from FPUContextBase */ + ldr x1,=FPUContextBase + ldr x0, [x1] + +/* Restore all the floating point register from the array */ + ldp x2, x3, [x0,#-0x10]! + msr FPCR, x2 + msr FPSR, x3 + ldp q30,q31, [x0,#-0x20]! + ldp q28,q29, [x0,#-0x20]! + ldp q26,q27, [x0,#-0x20]! + ldp q24,q25, [x0,#-0x20]! + ldp q22,q23, [x0,#-0x20]! + ldp q20,q21, [x0,#-0x20]! + ldp q18,q19, [x0,#-0x20]! + ldp q16,q17, [x0,#-0x20]! + ldp q14,q15, [x0,#-0x20]! + ldp q12,q13, [x0,#-0x20]! + ldp q10,q11, [x0,#-0x20]! + ldp q8,q9, [x0,#-0x20]! + ldp q6,q7, [x0,#-0x20]! + ldp q4,q5, [x0,#-0x20]! + ldp q2,q3, [x0,#-0x20]! + ldp q0,q1, [x0,#-0x20]! + +/* Save current address of floating point context array to FPUContextBase */ + str x0, [x1] +.endm + + +.org 0 + +.section .vectors, "a" + +_vector_table: +.set VBAR, _vector_table +.org VBAR +/* + * if application is built for XEN GUEST as EL1 Non-secure following image + * header is required by XEN. + */ +.if (HYP_GUEST == 1) + + /* Valid Image header. */ + /* HW reset vector. */ + ldr x16, =_boot + br x16 + + /* text offset. */ + .dword 0 + /* image size. */ + .dword 0 + /* flags. */ + .dword 8 + /* RES0 */ + .dword 0 + .dword 0 + .dword 0 + + /* magic */ + .dword 0x644d5241 + /* RES0 */ + .dword 0 + /* End of Image header. */ +.endif + + b _boot +.org (VBAR + 0x200) + b SynchronousInterruptHandler + +.org (VBAR + 0x280) + b IRQInterruptHandler + +.org (VBAR + 0x300) + b FIQInterruptHandler + +.org (VBAR + 0x380) + b SErrorInterruptHandler + + +SynchronousInterruptHandler: + saveregister + +/* Check if the Synchronous abort is occured due to floating point access. */ +.if (EL3 == 1) + mrs x0, ESR_EL3 +.else + mrs x0, ESR_EL1 +.endif + and x0, x0, #(0x3F << 26) + mov x1, #(0x7 << 26) + cmp x0, x1 +/* If exception is not due to floating point access go to synchronous handler */ + bne synchronoushandler + +/* + * If excpetion occured due to floating point access, Enable the floating point + * access i.e. do not trap floating point instruction + */ + .if (EL3 == 1) + mrs x1,CPTR_EL3 + bic x1, x1, #(0x1<<10) + msr CPTR_EL3, x1 +.else + mrs x1,CPACR_EL1 + orr x1, x1, #(0x1<<20) + msr CPACR_EL1, x1 +.endif + isb + +/* If the floating point access was previously enabled, store FPU context + * registers(storefloat). + */ + ldr x0, =FPUStatus + ldrb w1,[x0] + cbnz w1, storefloat +/* + * If the floating point access was not enabled previously, save the status of + * floating point accessibility i.e. enabled and store floating point context + * array address(FPUContext) to FPUContextBase. + */ + mov w1, #0x1 + strb w1, [x0] + ldr x0, =FPUContext + ldr x1, =FPUContextBase + str x0,[x1] + b restorecontext +storefloat: + savefloatregister + b restorecontext +synchronoushandler: + bl SynchronousInterrupt +restorecontext: + restoreregister + eret + +IRQInterruptHandler: + + saveregister +/* Save the status of SPSR, ELR and CPTR to stack */ + .if (EL3 == 1) + mrs x0, CPTR_EL3 + mrs x1, ELR_EL3 + mrs x2, SPSR_EL3 +.else + mrs x0, CPACR_EL1 + mrs x1, ELR_EL1 + mrs x2, SPSR_EL1 +.endif + stp x0, x1, [sp,#-0x10]! + str x2, [sp,#-0x10]! + +/* Trap floating point access */ + .if (EL3 == 1) + mrs x1,CPTR_EL3 + orr x1, x1, #(0x1<<10) + msr CPTR_EL3, x1 +.else + mrs x1,CPACR_EL1 + bic x1, x1, #(0x1<<20) + msr CPACR_EL1, x1 +.endif + isb + + bl IRQInterrupt +/* + * If floating point access is enabled during interrupt handling, + * restore floating point registers. + */ + + .if (EL3 == 1) + mrs x0, CPTR_EL3 + ands x0, x0, #(0x1<<10) + bne RestorePrevState +.else + mrs x0,CPACR_EL1 + ands x0, x0, #(0x1<<20) + beq RestorePrevState +.endif + + restorefloatregister + +/* Restore the status of SPSR, ELR and CPTR from stack */ +RestorePrevState: + ldr x2,[sp],0x10 + ldp x0, x1, [sp],0x10 + .if (EL3 == 1) + msr CPTR_EL3, x0 + msr ELR_EL3, x1 + msr SPSR_EL3, x2 +.else + msr CPACR_EL1, x0 + msr ELR_EL1, x1 + msr SPSR_EL1, x2 +.endif + restoreregister + eret + +FIQInterruptHandler: + + saveregister + + bl FIQInterrupt + + restoreregister + + eret + +SErrorInterruptHandler: + + saveregister + + bl SErrorInterrupt + + restoreregister + + eret + + +.align 8 +/* Array to store floating point registers */ +FPUContext: .skip FPUContextSize + +/* Stores address for floating point context array */ +FPUContextBase: .skip 8 + +FPUStatus: .skip 1 + +.end
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/boot.S b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/boot.S new file mode 100644 index 0000000..7609949 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/boot.S
@@ -0,0 +1,446 @@ +/****************************************************************************** +* +* Copyright (C) 2014 - 2018 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file boot.S +* +* @addtogroup a53_64_boot_code Cortex A53 64bit Processor Boot Code +* @{ +* <h2> boot.S </h2> +* +* The boot code performs minimum configuration which is required for an +* application. Cortex-A53 starts by checking current exception level. If the +* current exception level is EL3 and BSP is built for EL3, it will do +* initialization required for application execution at EL3. Below is a +* sequence illustrating what all configuration is performed before control +* reaches to main function for EL3 execution. +* +* 1. Program vector table base for exception handling +* 2. Set reset vector table base address +* 3. Program stack pointer for EL3 +* 4. Routing of interrupts to EL3 +* 5. Enable ECC protection +* 6. Program generic counter frequency +* 7. Invalidate instruction cache, data cache and TLBs +* 8. Configure MMU registers and program base address of translation table +* 9. Transfer control to _start which clears BSS sections and runs global +* constructor before jumping to main application +* +* If the current exception level is EL1 and BSP is also built for EL1_NONSECURE +* it will perform initialization required for application execution at EL1 +* non-secure. For all other combination, the execution will go into infinite +* loop. Below is a sequence illustrating what all configuration is performed +* before control reaches to main function for EL1 execution. +* +* 1. Program vector table base for exception handling +* 2. Program stack pointer for EL1 +* 3. Invalidate instruction cache, data cache and TLBs +* 4. Configure MMU registers and program base address of translation table +* 5. Transfer control to _start which clears BSS sections and runs global +* constructor before jumping to main application +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ------- -------- --------------------------------------------------- +* 5.00 pkp 05/21/14 Initial version +* 6.00 pkp 07/25/16 Program the counter frequency +* 6.02 pkp 01/22/17 Added support for EL1 non-secure +* 6.02 pkp 01/24/17 Clearing status of FPUStatus variable to ensure it +* holds correct value. +* 6.3 mus 04/20/17 CPU Cache protection bit in the L2CTLR_EL1 will be in +* set state on reset. So, setting that bit through boot +* code is redundant, hence removed the code which sets +* CPU cache protection bit. +* 6.4 mus 08/11/17 Implemented ARM erratum 855873.It fixes +* CR#982209. +* 6.6 mus 01/19/18 Added isb after writing to the cpacr_el1/cptr_el3, +* to ensure floating-point unit is disabled, before +* any subsequent instruction. +* +* +******************************************************************************/ + +#include "xparameters.h" +#include "bspconfig.h" +#include "xil_errata.h" + +.globl MMUTableL0 +.globl MMUTableL1 +.globl MMUTableL2 +.global _prestart +.global _boot + +.global __el3_stack +.global __el2_stack +.global __el1_stack +.global __el0_stack +.global _vector_table + +.set EL3_stack, __el3_stack +.set EL2_stack, __el2_stack +.set EL1_stack, __el1_stack +.set EL0_stack, __el0_stack + +.set TT_S1_FAULT, 0x0 +.set TT_S1_TABLE, 0x3 + +.set L0Table, MMUTableL0 +.set L1Table, MMUTableL1 +.set L2Table, MMUTableL2 +.set vector_base, _vector_table +.set rvbar_base, 0xFD5C0040 + +.set counterfreq, XPAR_CPU_CORTEXA53_0_TIMESTAMP_CLK_FREQ +.set MODE_EL1, 0x5 +.set DAIF_BIT, 0x1C0 + +.section .boot,"ax" + + +/* this initializes the various processor modes */ + +_prestart: +_boot: + mov x0, #0 + mov x1, #0 + mov x2, #0 + mov x3, #0 + mov x4, #0 + mov x5, #0 + mov x6, #0 + mov x7, #0 + mov x8, #0 + mov x9, #0 + mov x10, #0 + mov x11, #0 + mov x12, #0 + mov x13, #0 + mov x14, #0 + mov x15, #0 + mov x16, #0 + mov x17, #0 + mov x18, #0 + mov x19, #0 + mov x20, #0 + mov x21, #0 + mov x22, #0 + mov x23, #0 + mov x24, #0 + mov x25, #0 + mov x26, #0 + mov x27, #0 + mov x28, #0 + mov x29, #0 + mov x30, #0 +#if 0 //dont put other a53 cpus in wfi + //Which core am I + // ---------------- + mrs x0, MPIDR_EL1 + and x0, x0, #0xFF //Mask off to leave Aff0 + cbz x0, OKToRun //If core 0, run the primary init code +EndlessLoop0: + wfi + b EndlessLoop0 +#endif +OKToRun: + + mrs x0, currentEL + cmp x0, #0xC + beq InitEL3 + + cmp x0, #0x4 + beq InitEL1 + + b error // go to error if current exception level is neither EL3 nor EL1 +InitEL3: +.if (EL3 == 1) + /*Set vector table base address*/ + ldr x1, =vector_base + msr VBAR_EL3,x1 + + /* Set reset vector address */ + /* Get the cpu ID */ + mrs x0, MPIDR_EL1 + and x0, x0, #0xFF + mov w0, w0 + ldr w2, =rvbar_base + /* calculate the rvbar base address for particular CPU core */ + mov w3, #0x8 + mul w0, w0, w3 + add w2, w2, w0 + /* store vector base address to RVBAR */ + str x1, [x2] + + /*Define stack pointer for current exception level*/ + ldr x2,=EL3_stack + mov sp,x2 + + /* Enable Trapping of SIMD/FPU register for standalone BSP */ + mov x0, #0 +#ifndef FREERTOS_BSP + orr x0, x0, #(0x1 << 10) +#endif + msr CPTR_EL3, x0 + isb + + /* + * Clear FPUStatus variable to make sure that it contains current + * status of FPU i.e. disabled. In case of a warm restart execution + * when bss sections are not cleared, it may contain previously updated + * value which does not hold true now. + */ +#ifndef FREERTOS_BSP + ldr x0,=FPUStatus + str xzr, [x0] +#endif + /* Configure SCR_EL3 */ + mov w1, #0 //; Initial value of register is unknown + orr w1, w1, #(1 << 11) //; Set ST bit (Secure EL1 can access CNTPS_TVAL_EL1, CNTPS_CTL_EL1 & CNTPS_CVAL_EL1) + orr w1, w1, #(1 << 10) //; Set RW bit (EL1 is AArch64, as this is the Secure world) + orr w1, w1, #(1 << 3) //; Set EA bit (SError routed to EL3) + orr w1, w1, #(1 << 2) //; Set FIQ bit (FIQs routed to EL3) + orr w1, w1, #(1 << 1) //; Set IRQ bit (IRQs routed to EL3) + msr SCR_EL3, x1 + + /*configure cpu auxiliary control register EL1 */ + ldr x0,=0x80CA000 // L1 Data prefetch control - 5, Enable device split throttle, 2 independent data prefetch streams +#if CONFIG_ARM_ERRATA_855873 + /* + * Set ENDCCASCI bit in CPUACTLR_EL1 register, to execute data + * cache clean operations as data cache clean and invalidate + * + */ + orr x0, x0, #(1 << 44) //; Set ENDCCASCI bit +#endif + msr S3_1_C15_C2_0, x0 //CPUACTLR_EL1 + + /* program the counter frequency */ + ldr x0,=counterfreq + msr CNTFRQ_EL0, x0 + + /*Enable hardware coherency between cores*/ + mrs x0, S3_1_c15_c2_1 //Read EL1 CPU Extended Control Register + orr x0, x0, #(1 << 6) //Set the SMPEN bit + msr S3_1_c15_c2_1, x0 //Write EL1 CPU Extended Control Register + isb + + tlbi ALLE3 + ic IALLU //; Invalidate I cache to PoU + bl invalidate_dcaches + dsb sy + isb + + ldr x1, =L0Table //; Get address of level 0 for TTBR0_EL3 + msr TTBR0_EL3, x1 //; Set TTBR0_EL3 + + /********************************************** + * Set up memory attributes + * This equates to: + * 0 = b01000100 = Normal, Inner/Outer Non-Cacheable + * 1 = b11111111 = Normal, Inner/Outer WB/WA/RA + * 2 = b00000000 = Device-nGnRnE + * 3 = b00000100 = Device-nGnRE + * 4 = b10111011 = Normal, Inner/Outer WT/WA/RA + **********************************************/ + ldr x1, =0x000000BB0400FF44 + msr MAIR_EL3, x1 + + /********************************************** + * Set up TCR_EL3 + * Physical Address Size PS = 010 -> 40bits 1TB + * Granual Size TG0 = 00 -> 4KB + * size offset of the memory region T0SZ = 24 -> (region size 2^(64-24) = 2^40) + ***************************************************/ + ldr x1,=0x80823518 + msr TCR_EL3, x1 + isb + + /* Enable SError Exception for asynchronous abort */ + mrs x1,DAIF + bic x1,x1,#(0x1<<8) + msr DAIF,x1 + + /* Configure SCTLR_EL3 */ + mov x1, #0 //Most of the SCTLR_EL3 bits are unknown at reset + orr x1, x1, #(1 << 12) //Enable I cache + orr x1, x1, #(1 << 3) //Enable SP alignment check + orr x1, x1, #(1 << 2) //Enable caches + orr x1, x1, #(1 << 0) //Enable MMU + msr SCTLR_EL3, x1 + dsb sy + isb + + b _startup //jump to start +.else + b error // present exception level and selected exception level mismatch +.endif + +InitEL1: +.if (EL1_NONSECURE == 1) + /*Set vector table base address*/ + ldr x1, =vector_base + msr VBAR_EL1,x1 + + mrs x0, CPACR_EL1 + bic x0, x0, #(0x3 << 0x20) + msr CPACR_EL1, x0 + isb + + /* + * Clear FPUStatus variable to make sure that it contains current + * status of FPU i.e. disabled. In case of a warm restart execution + * when bss sections are not cleared, it may contain previously updated + * value which does not hold true now. + */ +#ifndef FREERTOS_BSP + ldr x0,=FPUStatus + str xzr, [x0] +#endif + /*Define stack pointer for current exception level*/ + ldr x2,=EL1_stack + mov sp,x2 + + /* Disable MMU first */ + mov x1,#0x0 + msr SCTLR_EL1, x1 + isb + + TLBI VMALLE1 + + ic IALLU //; Invalidate I cache to PoU + bl invalidate_dcaches + dsb sy + isb + + ldr x1, =L0Table //; Get address of level 0 for TTBR0_EL1 + msr TTBR0_EL1, x1 //; Set TTBR0_EL1 + + /********************************************** + * Set up memory attributes + * This equates to: + * 0 = b01000100 = Normal, Inner/Outer Non-Cacheable + * 1 = b11111111 = Normal, Inner/Outer WB/WA/RA + * 2 = b00000000 = Device-nGnRnE + * 3 = b00000100 = Device-nGnRE + * 4 = b10111011 = Normal, Inner/Outer WT/WA/RA + **********************************************/ + ldr x1, =0x000000BB0400FF44 + msr MAIR_EL1, x1 + + /********************************************** + * Set up TCR_EL1 + * Physical Address Size PS = 010 -> 40bits 1TB + * Granual Size TG0 = 00 -> 4KB + * size offset of the memory region T0SZ = 24 -> (region size 2^(64-24) = 2^40) + ***************************************************/ + ldr x1,=0x285800518 + msr TCR_EL1, x1 + isb + /* Enable SError Exception for asynchronous abort */ + mrs x1,DAIF + bic x1,x1,#(0x1<<8) + msr DAIF,x1 + + //; Enable MMU + mov x1,#0x0 + orr x1, x1, #(1 << 18) // ; Set WFE non trapping + orr x1, x1, #(1 << 17) // ; Set WFI non trapping + orr x1, x1, #(1 << 5) // ; Set CP15 barrier enabled + orr x1, x1, #(1 << 12) // ; Set I bit + orr x1, x1, #(1 << 2) // ; Set C bit + orr x1, x1, #(1 << 0) // ; Set M bit + msr SCTLR_EL1, x1 + isb + + bl _startup //jump to start +.else + b error // present exception level and selected exception level mismatch +.endif + +error: b error + + +invalidate_dcaches: + + dmb ISH + mrs x0, CLIDR_EL1 //; x0 = CLIDR + ubfx w2, w0, #24, #3 //; w2 = CLIDR.LoC + cmp w2, #0 //; LoC is 0? + b.eq invalidateCaches_end //; No cleaning required and enable MMU + mov w1, #0 //; w1 = level iterator + +invalidateCaches_flush_level: + add w3, w1, w1, lsl #1 //; w3 = w1 * 3 (right-shift for cache type) + lsr w3, w0, w3 //; w3 = w0 >> w3 + ubfx w3, w3, #0, #3 //; w3 = cache type of this level + cmp w3, #2 //; No cache at this level? + b.lt invalidateCaches_next_level + + lsl w4, w1, #1 + msr CSSELR_EL1, x4 //; Select current cache level in CSSELR + isb //; ISB required to reflect new CSIDR + mrs x4, CCSIDR_EL1 //; w4 = CSIDR + + ubfx w3, w4, #0, #3 + add w3, w3, #2 //; w3 = log2(line size) + ubfx w5, w4, #13, #15 + ubfx w4, w4, #3, #10 //; w4 = Way number + clz w6, w4 //; w6 = 32 - log2(number of ways) + +invalidateCaches_flush_set: + mov w8, w4 //; w8 = Way number +invalidateCaches_flush_way: + lsl w7, w1, #1 //; Fill level field + lsl w9, w5, w3 + orr w7, w7, w9 //; Fill index field + lsl w9, w8, w6 + orr w7, w7, w9 //; Fill way field + dc CISW, x7 //; Invalidate by set/way to point of coherency + subs w8, w8, #1 //; Decrement way + b.ge invalidateCaches_flush_way + subs w5, w5, #1 //; Descrement set + b.ge invalidateCaches_flush_set + +invalidateCaches_next_level: + add w1, w1, #1 //; Next level + cmp w2, w1 + b.gt invalidateCaches_flush_level + +invalidateCaches_end: + ret + +.end +/** +* @} End of "addtogroup a53_64_boot_code". +*/
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/bspconfig.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/bspconfig.h new file mode 100644 index 0000000..aaf4af1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/bspconfig.h
@@ -0,0 +1,48 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: +* DO NOT EDIT. +* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* +*Permission is hereby granted, free of charge, to any person obtaining a copy +*of this software and associated documentation files (the Software), to deal +*in the Software without restriction, including without limitation the rights +*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +*copies of the Software, and to permit persons to whom the Software is +*furnished to do so, subject to the following conditions: +* +*The above copyright notice and this permission notice shall be included in +*all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +*(a) running on a Xilinx device, or +*(b) that interact with a Xilinx device through a bus or interconnect. +* +*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +*Except as contained in this notice, the name of the Xilinx shall not be used +*in advertising or otherwise to promote the sale, use or other dealings in +*this Software without prior written authorization from Xilinx. +* + +* +* Description: Configurations for Standalone BSP +* +*******************************************************************/ + +#ifndef BSPCONFIG_H /* prevent circular inclusions */ +#define BSPCONFIG_H /* by using protection macros */ + +#define MICROBLAZE_PVR_NONE +#define EL3 1 +#define EL1_NONSECURE 0 +#define HYP_GUEST 0 + +#endif /*end of __BSPCONFIG_H_*/
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/changelog.txt b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/changelog.txt new file mode 100644 index 0000000..6414440 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/changelog.txt
@@ -0,0 +1,539 @@ +/***************************************************************************** + * MODIFICATION HISTORY: + * + * Ver Who Date Changes + * ----- ---- -------- --------------------------------------------------- + * 3.02a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros + * 3.02a sdm 06/27/11 Added INST_SYNC and DATA_SYNC macros for all the CPUs + * 3.02a sdm 07/07/11 Updated ppc440 boot.S to set guarded bit for all but + * cacheable regions + * Update ppc440/xil_cache.c to use CACHEABLE_REGION_MASK + * generated by the cpu driver, for enabling caches + * 3.02a sdm 07/08/11 Updated microblaze cache flush APIs based on write-back/ + * write-thru caches + * 3.03a sdm 08/20/11 Updated the tag/data RAM latency values for L2CC + * Updated the MMU table to mark OCM in high address space + * as inner cacheable and reserved space as Invalid + * 3.03a sdm 08/20/11 Changes to support FreeRTOS + * Updated the MMU table to mark upper half of the DDR as + * non-cacheable + * Setup supervisor and abort mode stacks + * Do not initialize/enable L2CC in case of AMP + * Initialize UART1 for 9600bps in case of AMP + * 3.03a sdm 08/27/11 Setup abort and supervisor mode stacks and don't init SMC + * in case of AMP + * 3.03a sdm 09/14/11 Added code for performance monitor and L2CC event + * counters + * 3.03a sdm 11/08/11 Updated microblaze xil_cache.h file to include + * xparameters.h file for CR630532 - Xil_DCacheFlush()/ + * Xil_DCacheFlushRange() functions in standalone BSP v3_02a + * for MicroBlaze will invalidate data in the cache instead + * of flushing it for writeback caches + * 3.04a sdm 11/21/11 Updated to initialize stdio device for 115200bps, for PS7 + * 3.04a sdm 01/02/12 Updated to clear cp15 regs with unknown reset values + * Remove redundant dsb/dmb instructions in cache maintenance + * APIs + * Remove redundant dsb in mcr instruction + * 3.04a sdm 01/13/12 Updated MMU table to mark DDR memory as Shareable + * 3.05a sdm 02/02/12 Removed some of the defines as they are being generated through + * driver tcl in xparameters.h. Update the gcc/translationtable.s + * for the QSPI complete address range - DT644567 + * Removed profile directory for armcc compiler and changed + * profiling setting to false in standalone_v2_1_0.tcl file + * Deleting boot.S file after preprocessing for armcc compiler + * 3.05a asa 03/11/12 Updated the function Xil_EnableMMU in file xil_mmu.c to + * invalidate the caches before enabling back the MMU and + * D cache. + * 3.05a asa 04/15/12 Updated the function Xil_SetTlbAttributes in file + * xil_mmu.c. Now we invalidate UTLB, Branch predictor + * array, flush the D-cache before changing the attributes + * in translation table. The user need not call Xil_DisableMMU + * before calling Xil_SetTlbAttributes. + * 3.06a asa/ 06/17/12 Removed the UART initialization for Zynq. For PEEP, the UART + * sgd initialization is present. Changes for this were done in + * uart.c and xil-crt0.s. + * Made changes in xil_io.c to use volatile pointers. + * Made changes in xil_mmu.c to correct the function + * Xil_SetTlbAttributes. + * Changes are made xil-crt0.s to initialize the static + * C++ constructors. + * Changes are made in boot.s, to fix the TTBR settings, + * correct the L2 Cache Auxiliary register settings, L2 cache + * latency settings. + * 3.07a asa/ 07/16/12 Made changes in cortexa9/xtime_l.c, xtime_l.h, sleep.c + * sgd usleep.c to use global timer intstead of CP15. + * Made changes in cortexa9/gcc/translation_table.s to map + * the peripheral devices as shareable device memory. + * Made changes in cortexa9/gcc/xil-crt0.s to initialize + * the global timer. + * Made changes in cortexa9/armcc/boot.S to initialize + * the global timer. + * Made changes in cortexa9/armcc/translation_table.s to + * map the peripheral devices as shareable device memory. + * Made changes in cortexa9/gcc/boot.S to optimize the + * L2 cache settings. Changes the section properties for + * ".mmu_tbl" and ".boot" sections in cortexa9/gcc/boot.S + * and cortexa9/gcc/translation_table.S. + * Made changes in cortexa9/xil_cache.c to change the + * cache invalidation order. + * 3.07a asa 08/17/12 Made changes across files for Cortexa9 to remove + * compilation/linking issues for C++ compiler. + * Made changes in mb_interface.h to remove compilation/ + * linking issues for C++ compiler. + * Added macros for swapb and swaph microblaze instructions + * mb_interface.h + * Remove barrier usage (SYNCHRONIZE_IO) from xil_io.c + * for CortexA9. + * 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address + * 3.07a asa 08/31/12 Added xil_printf.h include + * 3.07a sgd 09/18/12 Corrected the L2 cache enable settings + * Corrected L2 cache sequence disable sequence + * 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with compiler option + * 3.09a asa 01/25/13 Updated to push and pop neon registers into stack for + * irq/fiq handling. + * Relocated COUNTS_PER_SECOND from sleep.c to xtime_l.h. This + * fixes the CR #692094. + * 3.09a sgd 02/14/13 Fix for CRs 697094 (SI#687034) and 675552. + * 3.10a srt 04/18/13 Implemented ARM Erratas. + * Cortex A9 Errata - 742230, 743622, 775420, 794073 + * L2Cache PL310 Errata - 588369, 727915, 759370 + * Please refer to file 'xil_errata.h' for errata + * description. + * 3.10a asa 05/04/13 Added support for L2 cache in MicroBlaze BSP. The older + * cache APIs were corresponding to only Layer 1 cache + * memories. New APIs were now added and the existing cache + * related APIs were changed to provide a uniform interface + * to flush/invalidate/enable/disable the complete cache + * system which includes both L1 and L2 caches. The changes + * for these were done in: + * src/microblaze/xil_cache.c and src/microblaze/xil_cache.h + * files. + * Four new files were added for supporting L2 cache. They are: + * microblaze_flush_cache_ext.S-> Flushes L2 cache + * microblaze_flush_cache_ext_range.S -> Flushes a range of + * memory in L2 cache. + * microblaze_invalidate_cache_ext.S-> Invalidates L2 cache + * microblaze_invalidate_cache_ext_range -> Invalidates a + * range of memory in L2 cache. + * These changes are done to implement PR #697214. + * 3.10a asa 05/13/13 Modified cache disable APIs at src/cortexa9/xil_cache.c to + * fix the CR #706464. L2 cache disabling happens independent + * of L1 data cache disable operation. Changes are done in the + * same file in cache handling APIs to do a L2 cache sync + * (poll reg7_?cache_?sync). This fixes CR #700542. + * 3.10a asa 05/20/13 Added API/Macros for enabling and disabling nested + * interrupts for ARM. These are done to fix the CR#699680. + * 3.10a srt 05/20/13 Made changes in cache maintenance APIs to do a proper cach + * sync operation. This fixes the CR# 716781. + * 3.11a asa 09/07/13 Updated armcc specific BSP files to have proper support + * for armcc toolchain. + * Modified asm_vectors.S (gcc) and asm_vectors.s (armcc) to + * fix issues related to NEON context saving. The assembly + * routines for IRQ and FIQ handling are modified. + * Deprecated the older BSP (3.10a). + * 3.11a asa 09/22/13 Fix for CR#732704. Cache APIs are modified to avoid + * various potential issues. Made changes in the function + * Xil_SetAttributes in file xil_mmu.c. + * 3.11a asa 09/23/13 Added files xil_misc_psreset_api.c and xil_misc_psreset_api.h + * in src\cortexa9 and src\microblaze folders. + * 3.11a asa 09/28/13 Modified the cache APIs (src\cortexa9) to fix handling of + * L2 cache sync operation and to fix issues around complete + * L2 cache flush/invalidation by ways. + * 3.12a asa 10/22/13 Modified the files xpseudo_asm_rvct.c and xpseudo_asm_rvct.h + * to fix linking issues with armcc/DS-5. Modified the armcc + * makefile to fix issues. + * 3.12a asa 11/15/13 Fix for CR#754800. It fixes issues around profiling for MB. + * 4.0 hk 12/13/13 Added check for STDOUT_BASEADDRESS where outbyte is used. + * 4.0 pkp 22/01/14 Modified return addresses for interrupt handlers (DataAbortHandler + * and SWIHandler) in asm_vector.S (src\cortexa9\gcc\ and + * src\cortexa9\armcc\) to fix CR#767251 + * 4.0 pkp 24/01/14 Modified cache APIs (Xil_DCacheInvalidateRange and + * Xil_L1DCacheInvalidate) in xil_cache.c (src\cortexa9) to fix the bugs. + * Few cache lines were missed to invalidate when unaligned address + * invalidation was accommodated in Xil_DCacheInvalidateRange. + * In Xil_L1DCacheInvalidate, while invalidating all L1D cache + * stack memory (which contains return address) was invalidated. So + * stack memory is flushed first and then L1D cache is invalidated. + * This is done to fix CR #763829 + * 4.0 adk 22/02/2014 Fixed the CR:775379 removed unnecessay _t(unit32_t etc) from + * mblaze_nt_types.h file and replace uint32_t with u32 in the + * profile_hist.c to fix the above CR. + * 4.1 bss 04/14/14 Updated driver tcl to remove _interrupt_handler.o from libgloss.a + * instead of libxil.a and added prototypes for + * microblaze_invalidate_cache_ext and microblaze_flush_cache_ext in + * mb_interface.h + * 4.1 hk 04/18/14 Add sleep function. + * 4.1 asa 04/21/14 Fix for CR#764881. Added support for msrset and msrclr. Renamed + * some of the *.s files inMB BSP source to *.S. + * 4.1 asa 04/28/14 Fix for CR#772280. Made changes in file cortexa9/gcc/read.c. + * 4.1 bss 04/29/14 Modified driver tcl to use libxil.a if libgloss.a does not exist + * CR#794205 + * 4.1 asa 05/09/14 Fix for CR#798230. Made changes in cortexa9/xil_cache.c and + * common/xil_testcache.c + * Fix for CR#764881. + * 4.1 srt 06/27/14 Remove '#undef DEBUG' from src/common/xdebug.h, which allows to + * output the DEBUG logs when -DDEBUG flag is enabled in BSP. + * 4.2 pkp 06/27/14 Added support for IAR compiler in src/cortexa9/iccarm. + * Also added explanatory notes in cortexa9/xil_cache.c for CR#785243. + * 4.2 pkp 06/19/14 Asynchronous abort has been enabled into cortexa9/gcc/boot.s and + * cortexa9/armcc/boot.s. Added default exception handlers for data + * abort and prefetch abort using handlers called + * DataAbortHandler and PrefetchAbortHandler respectively in + * cortexa9/xil_exception.c to fix CR#802862. + * 4.2 pkp 06/30/14 MakeFile for cortexa9/armcc has been changed to fixes the + * issue of improper linking of translation_table.s + * 4.2 pkp 07/04/14 added weak attribute for the function in BSP which are also present + * in tool chain to avoid conflicts into some special cases + * 4.2 pkp 07/21/14 Corrected reset value of event counter in function + * Xpm_ResetEventCounters in src/cortexa9/xpm_counter.c to fix CR#796275 + * 4.2 pkp 07/21/14 Included xil_types.h file in xil_mmu.h which had contained a function + * containing type def u32 defined in xil_types.g to resolve issue of + * CR#805869 + * 4.2 pkp 08/04/14 Removed unimplemented nanosleep routine from cortexa9/usleep.c as + * it is not possible to generate timer in nanosecond due to limited + * cpu frequency + * 4.2 pkp 08/04/14 Removed PEEP board related code which contained initialization of + * uart, smc nor and sram from cortexa9/gcc/xil-crt0.s and armcc/boot.s + * and iccarm/boot.s. Also uart.c and smc.c have been removed. Also + * removed function definition of XSmc_NorInit and XSmc_NorInit from + * cortexa9/smc.h + * 4.2 bss 08/11/14 Added microblaze_flush_cache_ext_range and microblaze_invalidate_ + * cache_ext_range declarations in mb_interface.h CR#783821. + * Modified profile_mcount_mb.S to fix CR#808412. + * 4.2 pkp 08/21/14 modified makefile of iccarm for proper linking of objectfiles in + * cortexa9/iccarm to fix CR#816701 + * 4.2 pkp 09/02/14 modified translation table entries in cortexa9/gcc/translation_table.s, + * armcc/translation_table.s and iccarm/translation_table.s + * to properly defined reserved entries according to address map for + * fixing CR#820146 + * 4.2 pkp 09/11/14 modified translation table entries in cortexa9/iccarm/translation_table.s + * and cortexa9/armcc/translation_table.s to resolve compilation + * error for solving CR#822897 + * 5.0 kvn 12/9/14 Support for Zync Ultrascale Mp.Also modified code for + * MISRA-C:2012 compliance. + * 5.0 pkp 12/15/14 Added APIs to get information about the platforms running the code by + * adding src/common/xplatform_info.*s + * 5.0 pkp 16/12/14 Modified boot code to enable scu after MMU is enabled and + * removed incorrect initialization of TLB lockdown register to fix + * CR#830580 in cortexa9/gcc/boot.S & cpu_init.S, armcc/boot.S + * and iccarm/boot.s + * 5.0 pkp 25/02/15 Modified floating point flag to vfpv3 from vfpv3_d16 in BSP MakeFile + * for iccarm and armcc compiler of cortexA9 + * 5.1 pkp 05/13/15 Changed the initialization order in cortexa9/gcc/boot.S, iccarm/boot.s + * and armcc/boot.s so to first invalidate caches and TLB, enable MMU and + * caches, then enable SMP bit in ACTLR. L2Cache invalidation and enabling + * of L2Cache is done later. + * 5.1 pkp 12/05/15 Modified cortexa9/xil_cache.c to modify Xil_DCacheInvalidateRange and + * Xil_DCacheFlushRange to remove unnecessary dsb which is unnecessarily + * taking long time to fix CR#853097. L2CacheSync is added into + * Xil_L2CacheInvalidateRange API. Xil_L1DCacheInvalidate and + * Xil_L2CacheInvalidate APIs are modified to flush the complete stack + * instead of just System Stack + * 5.1 pkp 14/05/15 Modified cortexa9/gcc/Makefile to keep a correct check of a compiler + * to update ECC_FLAGS and also take the compiler and archiver as specified + * in settings instead of hardcoding it. + * 5.2 pkp 06/08/15 Modified cortexa9/gcc/translation_table.S to put a check for + * XPAR_PS7_DDR_0_S_AXI_BASEADDR to confirm if DDR is present or not and + * accordingly generate the translation table + * 5.2 pkp 23/07/15 Modified cortexa9/gcc/Makefile to keep a correct check of a compiler + * to update ECC_FLAGS to fix a bug introduced during new version creation + * of BSP. + * 5.3 pkp 10/07/15 Modified cortexa9/xil_cache.c file to change cache API so that L2 Cache + * functionalities are avoided for the OpenAMP slave application(when + * USE_AMP flag is defined for BSP) as master CPU would be utilizing L2 + * cache for its operation. Also file operations such as read, write, + * close, open are also avoided for OpenAMP support(when USE_AMP flag is + * defined for BSP) because XilOpenAMP library contains own file operation. + * The xil-crt0.S file is modified for not initializing global timer for + * OpenAMP application as it might be already in use by master CPU + * 5.3 pkp 10/09/15 Modified cortexa9/iccarm/xpseudo_asm_iccarm.h file to change function + * definition for dsb, isb and dmb to fix the compilation error when used + * kvn 16/10/15 Encapsulated assembly code into macros for R5 xil_cache file. + * 5.4 pkp 09/11/15 Modified cortexr5/gcc/boot.S to disable ACTLR.DBWR bit to avoid potential + * R5 deadlock for errata 780125 + * 5.4 pkp 09/11/15 Modified cortexa53/32bit/gcc/boot.S to enable I-Cache and D-Cache for a53 + * 32 bit BSP in the initialization + * 5.4 pkp 09/11/15 Modified cortexa9/xil_misc_psreset_api.c file to change the description + * for XOcm_Remap function + * 5.4 pkp 16/11/15 Modified microblaze/xil_misc_psreset_api.c file to change the description + * for XOcm_Remap function + * kvn 21/11/15 Added volatile keyword for ADDR varibles in Xil_Out API + * kvn 21/11/15 Changed ADDR variable type from u32 to UINTPTR. This is + * required for MISRA-C:2012 Compliance. + * 5.4 pkp 23/11/15 Added attribute definitions for Xil_SetTlbAttributes API of Cortex-A9 + * in cortexa9/xil_mmu.h + * 5.4 pkp 23/11/15 Added default undefined exception handler for Cortex-A9 + * 5.4 pkp 11/12/15 Modified common/xplatform_info.h to add #defines for silicon for + * checking the current executing platform + * 5.4 pkp 18/12/15 Modified cortexa53/32bit/gcc/xil-crt0.S and 64bit/gcc/xil-crt0.S + * to initialize global constructor for C++ applications + * 5.4 pkp 18/12/15 Modified cortexr5/gcc/xil-crt0.S to initialize global constructor for + * C++ applications + * 5.4 pkp 18/12/15 Modified cortexa53/32bit/gcc/translation_table.S and 64bit/gcc/ + * translation_table.S to update the translation table according to proper + * address map + * 5.4 pkp 18/12/15 Modified cortexar5/mpu.c to initialize the MPU according to proper + * address map + * 5.4 pkp 05/01/16 Modified cortexa53/64bit/boot.S to set the reset vector register RVBAR + * equivalent to vector table base address + * 5.4 pkp 08/01/16 Modified cortexa9/gcc/Makefile to update the extra compiler flag + * as per the toolchain update + * 5.4 pkp 12/01/16 Changed common/xplatform_info.* to add platform information support + * for Cortex-A53 32bit mode + * 5.4 pkp 28/01/16 Modified cortexa53/32bit/sleep.c and usleep.c & cortexa53/64bit/sleep.c + * and usleep.c to correct routines to avoid hardcoding the timer frequency, + * instead take it from xparameters.h to properly configure the timestamp + * clock frequency + * 5.4 asa 29/01/16 Modified microblaze/mb_interface.h to add macros that support the + * new instructions for MB address extension feature + * 5.4 kvn 30/01/16 Modified xparameters_ps.h file to add interrupt ID number for + * system monitor. + * 5.4 pkp 04/02/16 Modified cortexr5/gcc/boot.S to enable fault log for lock-step mode + * 5.4 pkp 19/02/16 Modified cortexr5/xtime_l.c to add an API XTime_StartTimer and updated + * cortexr5/xil-crt0.S to configure the TTC3 timer when present. Modified + * cortexr5/sleep.c, cortexr5/usleep.c to use TTC3 when present otherwise + * use set of assembly instructions to provide required delay to fix + * CR#913249. + * 5.4 asa 25/02/16 Made changes in xil-crt0.S for R5, A53 64 and 32 bit BSPs, to replace + * _exit with exit. We should not be directly calling _exit and should + * always use the library exit. This fixes the CR#937036. + * 5.4 pkp 25/02/16 Made change to cortexr5/gcc/boot.S to initialize the floating point + * registers, banked registers for various modes and enabled + * the cache ECC check before enabling the fault log for lock step mode + * Also modified the cortexr5/gcc/Makefile to support floating point + * registers initialization in boot code. + * 5.4 pkp 03/01/16 Updated the exit function in cortexr5/gcc/_exit.c to enable the debug + * logic in case of lock-step mode when fault log is enabled to fix + * CR#938281 + * 5.4 pkp 03/02/16 Modified cortexa9/iccarm/xpseudo_asm_iccarm.h file to include + * header file instrinsics.h which contains assembly instructions + * definitions which can be used by C + * 5.4 asa 03/02/16 Added print.c in MB BSP. Made other cosmetic changes to have uniform + * proto for all print.c across the BSPs. This patch fixes CR#938738. + * 5.4 pkp 03/09/16 Modified cortexr5/sleep.c and usleep.c to avoid disabling the + * interrupts when sleep/usleep is being executed using assembly + * instructions to fix CR#913249. + * 5.4 pkp 03/11/16 Modified cortexr5/xtime_l.c to avoid enabling overflow interrupt, + * instead modified cortexr5/sleep.c and usleep.c to poll the counter + * value and compare it with previous value to detect the overflow + * to fix CR#940209. + * 5.4 pkp 03/24/16 Modified cortexr5/boot.S to reset the dbg_lpd_reset before enabling + * the fault log to avoid intervention for lock-step mode and cortexr5/ + * _exit.c to enable the dbg_lpd_reset once the fault log is disabled + * to fix CR#947335 + * 5.5 pkp 04/11/16 Modified cortexr5/boot.S to enable comparators for non-JTAG bootmode + * in lock-step to avoid resetting the debug logic which restricts the + * access for debugger and removed enabling back of debug modules in + * cortexr5/_exit.c + * 5.5 pkp 04/13/16 Modified cortexa9/gcc/read.c to return correct number of bytes when + * read buffer is filled and removed the redundant NULL checking for + * buffer to simplify the code + * 5.5 pkp 04/13/16 Modified cortexa53/64bit/gcc/read.c and cortexa53/32bit/gcc/read.c + * to return correct number of bytes when read buffer is filled and + * removed the redundant NULL checking for buffer to simplify the code + * 5.5 pkp 04/13/16 Modified cortexr5/gcc/read.c to return correct number of bytes when + * read buffer is filled and removed the redundant NULL checking for + * buffer to simplify the code + * 5.5 pkp 04/13/16 Modified cortexa53/64bit/xpseudo_asm_gcc.h to add volatile to asm + * instruction macros to disable certain optimizations which may move + * code out of loops if optimizers believe that the code will always + * return the same result or discard asm statements if optimizers + * determine there is no need for the output variables + * 5.5 pkp 04/13/16 Modified cortexa53/64bit/xtime_l.c to add XTime_StartTimer which + * starts the timer if it is disabled and modified XTime_GetTime to + * enable the timer if it is not enabled. Also modified cortexa53/64bit/ + * sleep.c and cortexa53/64bit/usleep.c to enable the timer if it is + * disabled and read the counter value directly from register instead + * of using XTime_GetTime for optimization + * 5.5 pkp 04/13/16 Modified cortexa53/32bit/xtime_l.c to add XTime_StartTimer which + * starts the timer if it is disabled and modified XTime_GetTime to + * enable the timer if it is not enabled. Also modified cortexa53/32bit/ + * sleep.c and cortexa53/32bit/usleep.c to enable the timer if it is + * disabled and read the counter value directly from register instead + * of using XTime_GetTime for optimization + * 5.5 pkp 04/13/16 Modified cortexa53/32bit/xil_cache.c and cortexa53/64bit/xil_cache.c + * to update the Xil_DCacheInvalidate, Xil_DCacheInvalidateLine and + * Xil_DCacheInvalidateRange functions description for proper + * explaination to fix CR#949801 + * 5.5 asa 04/20/16 Added missing macros for hibernate and suspend in Microblaze BSP + * file mb_interface.h. This fixes the CR#949503. + * 5.5 asa 04/29/16 Fix for CR#951080. Updated cache APIs for HW designs where cache + * memory is not included for MicroBlaze. + * 5.5 pkp 05/06/16 Modified the cortexa9/xil_exception.h to update the macros + * Xil_EnableNestedInterrupts and Xil_DisableNestedInterrupts for fixing + * the issue of lr being corrupted to resolve CR#950468 + * 5.5 pkp 05/06/16 Modified the cortexr5/xil_exception.h to update the macros + * Xil_EnableNestedInterrupts and Xil_DisableNestedInterrupts for fixing + * the issue of lr being corrupted to resolve CR#950468 + * 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable + * 6.0 pkp 06/27/16 Updated cortexr5/mpu.c to move the code related to Init_MPU to .boot + * section since it is part of boot process to fix CR#949555 + * hk 07/12/16 Correct masks for IOU SLCR GEM registers + * 6.0 pkp 07/25/16 Program the counter frequency in boot code for CortexA53 + * 6.0 asa 08/03/16 Updated sleep_common function in microblaze_sleep.c to improve the + * the accuracy of MB sleep functionality. This fixes the CR#954191. + * 6.0 mus 08/03/16 Restructured the BSP to avoid code duplication across all BSPs. + * Source code directories specific to ARM processor's are moved to src/arm + * directory(i.e. src/cortexa53,src/cortexa9 and src/cortexr5 moved to src/arm/cortexa53, + * src/arm/cortexa9 and src/arm/cortexr5 respectively).Files xil_printf.c,xil_printf.h, + * print.c,xil_io.c and xil_io.h are consolidated across all BSPs into common file each and + * consolidated files are kept at src/common directory.Files putnum.c,vectors.c,vectors.h, + * xil_exception.c and xil_exception.h are consolidated across all ARM BSPs + * into common file each and consolidated files are kept at src/arm/common directory. + * GCC source files related to file operations are consolidated and kept + * at src/arm/common/gcc directory. + * All io interfacing functions (i.e. All variants of xil_out, xil_in ) + * are made as static inline and implementation is kept in consolidated common/xil_io.h, + * xil_io.h must be included as a header file to access io interfacing functions. + * Added undefined exception handler for A53 32 bit and R5 processor + * 6.0 mus 08/11/16 Updated xtime_l.c in R5 BSP to remove implementation of XTime_SetTime API, since + * TTC counter value register is read only. + * 6.0 asa 08/15/16 Modified the signatures for functions sleep and usleep. This fixes + * the CR#956899. + * 6.0 mus 08/18/16 Defined ARMA53_32 flag in cortexa53/32bit/xparameters_ps.h and ARMR5 flag + * in cortexr5/xparameters_ps.h + * 6.0 mus 08/18/16 Added support for the the Zynq 7000s devices + * 6.0 mus 08/18/16 Removed unused variables from xil_printf.c and xplatform_info.c + * 6.0 mus 08/19/16 Modified xil_io.h to remove __LITTLE_ENDIAN__ flag check for all ARM processors + * 6.1 mus 11/03/16 Added APIs handle_stdin_parameter and handle_stdout_parameter in standalone tcl. + * ::hsi::utils::handle_stdin and ::hsi::utils::handle_stdout are taken as a base for + * these APIs and modifications are done on top of it to handle stdout/stdin + * parameters for design which doesnt have UART.It fixes CR#953681 + * 6.1 nsk 11/07/16 Added two new files xil_mem.c and xil_mem.h for xil_memcpy + * 6.2 pkp 12/14/16 Updated cortexa53/64bit/translation_table.S for upper ps DDR. The 0x800000000 - + * 0xFFFFFFFFF range is marked normal memory for the DDR size defined in hdf + * and rest of the memory in that 32GB region is marked as reserved to avoid + * any speculative access + * 6.2 pkp 12/23/16 Added support for floating point operation to Cortex-A53 64bit mode. It modified + * asm_vectors.S to implement lazy floating point context saving i.e. floating point + * access is enabled if there is any floating point operation, it is disabled by + * default. Also FPU is initally disabled for IRQ and none of the floating point + * registers are saved during normal context saving. If IRQ handler does not require + * floating point operation, the floating point registers are untouched and no need + * for saving/restoring. If IRQ handler uses any floating point operation, then floating + * point registers are saved and FPU is enabled for IRQ handler. Then floating point + * registers are restored back after servicing IRQ during normal context restoring. + * 6.2 mus 01/01/17 Updated makefiles of R5 and a53 64 bit/32 bit processors to fix error in clean + * target.It fixes the CR#966900 + * 6.2 pkp 01/22/17 Added support for EL1 non-secure execution and Hypervisor Baremetal for Cortex-A53 + * 64bit Mode. If Hypervisor_guest is selected as true in BSP settings, BSP will be built + * for EL1 Non-secure, else BSP will be built for EL3. By default hypervisor_guest is + * as false i.e. default bsp is EL3. + * 6.2 pkp 01/24/17 Updated cortexa53/64bit/boot.S to clear FPUStatus variable to make sure that it + * contains initial status of FPU i.e. disabled. In case of a warm restart execution + * when bss sections are not cleared, it may contain previously updated value which + * does not hold true once processor resumes. This fixes CR#966826. + * 6.2 asa 01/31/17 The existing Xil_DCacheDisable API first flushes the + * D caches and then disables it. The problem with that is, + * potentially there will be a small window after the cache + * flush operation and before the we disable D caches where + * we might have valid data in cache lines. In such a + * scenario disabling the D cache can lead to unknown behavior. + * The ideal solution to this is to use assembly code for + * the complete API and avoid any memory accesses. But with + * that we will end up having a huge amount on assembly code + * which is not maintainable. Changes are done to use a mix + * of assembly and C code. All local variables are put in + * registers. Also function calls are avoided in the API to + * avoid using stack memory. + * 6.2 mus 02/13/17 A53 CPU cache system can pre-fetch catch lines.So there are + * scenarios when an invalidated cache line can get pre fetched to cache. + * If that happens, the coherency between cache and memory is lost + * resulting in lost data. To avoid this kind of issue either + * user has to use dsb() or disable pre-fetching for L1 cache + * or else reduce maximum number of outstanding data prefetches allowed. + * Using dsb() while comparing data costing more performance compared to + * disabling pre-fetching/reducing maximum number of outstanding data + * prefetches for L1 Cache.The new api Xil_ConfigureL1Prefetch is added + * to disable pre-fetching/configure maximum number of outstanding data + * prefetches allowed in L1 cache system.This fixes CR#967864. + * 6.2 pkp 02/16/17 Added xil_smc.c file to provide a C wrapper for smc calling which can be + * used by cortex-A53 64bit EL1 Non-secure application. + * 6.2 kvn 03/03/17 Added support thumb mode + * 6.2 mus 03/13/17 Fixed MISRA C mandatory standard violations in ARM cortexr5 and cortexa53 BSP. + * It fixes CR#970543 + * 6.2 asa 03/16/17 Fix for CR#970859. For Mcroblaze BSP, when we enable intrusive + * profiling we see a crash. That is because the the tcl uses invalid + * HSI command. This change fixes it. + * 6.2 mus 03/22/17 Updated standalone tcl to generate xparameter XPAR_FPD_IS_CACHE_COHERENT, if + * any FPD peripheral is configured to use CCI.It fixes CR#972638 + * 6.3 mus 03/20/17 Updated cortex-r5 BSP, to add hard floating point support. + * 6.3 mus 04/17/17 Updated Cortex-a53 32 bit BSP boot code to fix bug in + * the HW coherency enablement. It fixes the CR#973287 + * 6.3 mus 04/20/17 Updated Cortex-A53 64 bit BSP boot code, to remove redundant write to the + * L2CTLR_EL1 register. It fixes the CR#974698 + * 6.4 mus 06/08/17 Updated arm/common/xil_exception.c to fix warnings in C level exception handlers + * of ARM 32 bit processor's. + * 6.4 mus 06/14/17 Updated cortexa53/64bit/gcc/asm_vectors.S to fix bug in IRQInterruptHandler code + * snippet, which checks for the FPEN bit of CPACR_EL1 register. + * 6.4 ms 05/23/17 Added PSU_PMU macro in xplatform_info.c, xparameters.h to support + * XGetPSVersion_Info function for PMUFW. + * ms 06/13/17 Added PSU_PMU macro in xplatform_info.c to support XGetPlatform_Info + * function for PMUFW. + * 6.4 mus 07/05/17 Updated Xil_In32BE function in xil_io.h to fix bug.It fixes CR#979740. + * 6.4 mus 07/25/17 Updated a53 32 bit boot code and vectors to support hard floating point + * operations.Now,VFP is being enabled in FPEXC register, through boot code + * and FPU registers are being saved/restored when irq/fiq vector is invoked. + * 6.4 adk 08/01/17 Updated standalone tcl to generate xparameter XPAR_PL_IS_CACHE_COHERENT, + * if h/w design configured with HPC port. + * 6.4 mus 08/10/17 Updated a53 64 bit translation table to mark memory as a outer shareable for + * EL1 NS execution. This change has been done to support CCI enabled IP's. + * 6.4 mus 08/11/17 Updated a53 64 bit boot code to implement ARM erratum 855873.This fixes + * CR#982209. + * 6.4 asa 08/16/17 Made several changes in the R5 MPU handling logic. Added new APIs to + * make RPU MPU handling user-friendly. This also fixes the CR-981028. + * 6.4 mus 08/17/17 Updated XGet_Zynq_UltraMp_Platform_info and XGetPSVersion_Info APIs to read + * version register through SMC call, over EL1 NS mode. This change has been done to + * support these APIs over EL1 NS mode. + * 6.5 mus 10/20/17 Updated standalone.tcl to fix bug in mb_can_handle_exceptions_in_delay_slots proc, + * it fixes CR#987464. + * 6.6 mus 12/07/17 Updated cortexa9/xil_errata.h and cortexa9/xil_cache.c to remove Errata 753970. + * It fixes CR#989132. + * srm 10/18/17 Updated all the sleep routines in a9,a53,R5,microblaze. Now the sleep routines + * will use the timer specified by the user to provide delay. A9 and A53 can use + * Global timer or TTC. R5 can use TTC or the machine cycles. Microblaze can use + * machine cycles or Axi timer. Updated standalone.tcl and standalone.mld files + * to support the sleep configuration Added new API's for the Axi timer in + * microblaze and TTC in ARM. Added two new files, xil_sleeptimer.c and + * xil_sleeptimer.h in ARM for the common sleep routines and 1 new file, + * xil_sleepcommon.c in Standalone-common for sleep/usleep API's. + * 6.6 hk 12/15/17 Export platform macros to bspconfig.h based on the processor. + * 6.6 asa 1/16/18 Ensure C stack information for A9 are flushed out from L1 D cache + * or L2 cache only when the respective caches are enabled. This fixes CR-922023. + * 6.6 mus 01/19/18 Updated asm_vectors.S and boot.S in Cortexa53 64 bit BSP, to add isb + * after writing to cpacr_el1/cptr_el3 registers. It would ensure + * disabling/enabling of floating-point unit, before any subsequent + * instruction. + * 6.6 mus 01/30/18 Updated hypervisor enabled Cortexa53 64 bit BSP, to add xen PV console + * support. Now, xil_printf would use PV console instead of UART in case of + * hypervisor enabled BSP. + * 6.6 mus 02/02/18 Updated get_connected_if proc in standalone tcl to detect the HPC port + * configured with smart interconnect.It fixes CR#990318. + * 6.6 srm 02/10/18 Updated csu_wdt interrupt to the correct value. Fixes CR#992229 + * 6.6 asa 02/12/18 Fix for heap handling for ARM platforms. CR#993932. + * 6.6 mus 02/19/18 Updated standalone.tcl to fix bug in handle_profile_opbtimer proc, + * CR#995014. + * 6.6 mus 02/23/18 Presently Cortex R5 BSP boot code is disabling the debug logic in +* non-JTAG boot mode, when processor is in lockstep configuration. +* This behavior is restricting application debugging in non-JTAG boot +* mode. To get rid of this restriction, added new mld parameter +* "lockstep_mode_debug", to enable/disable debug logic from BSP +* settings. Now, debug logic can be enabled through BSP settings, +* by modifying value of parameter "lockstep_mode_debug" as "true". +* It fixes CR#993896. + * 6.6.mus 02/27/18 Updated Xil_DCacheInvalidateRange and +* Xil_ICacheInvalidateRange APIs in Cortexa53 64 bit BSP, to fix bug +* in handling upper DDR addresses.It fixes CR#995581. +* 6.6 mus 03/12/18 Updated makefile of Cortexa53 32bit BSP to add includes_ps directory +* in the list of include paths. This change allows applications/BSP +* files to include .h files in include_ps directory. +* 6.6 mus 03/16/18 By default CPUACTLR_EL1 is accessible only from EL3, it +* results into abort if accessed from EL1 non secure privilege +* level. Updated Xil_ConfigureL1Prefetch function in Cortexa53 64 bit BSP +* to avoid CPUACTLR_EL1 access from privile levels other than EL3. +* 6.6 mus 03/16/18 Updated hypervisor enabled BSP to use PV console, based on the +* XEN_USE_PV_CONSOLE flag. By deafault hypervisor enabled BSP would +* use UART console, PV console can be enabled by appending + "-DXEN_USE_PV_CONSOLE" to the BSP extra compiler flags. + * + *****************************************************************************************/
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/close.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/close.c new file mode 100644 index 0000000..dbbe0d4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/close.c
@@ -0,0 +1,49 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +#ifndef UNDEFINE_FILE_OPS +#include "xil_types.h" +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) s32 _close(s32 fd); +} +#endif + +/* + * close -- We don't need to do anything, but pretend we did. + */ + +__attribute__((weak)) s32 _close(s32 fd) +{ + (void)fd; + return (0); +} +#endif
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/config.make b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/config.make new file mode 100644 index 0000000..2b7dbb6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/config.make
@@ -0,0 +1,2 @@ +LIBSOURCES = *.c *.S +LIBS = standalone_libs
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/errno.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/errno.c new file mode 100644 index 0000000..df0218e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/errno.c
@@ -0,0 +1,51 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/* The errno variable is stored in the reentrancy structure. This + function returns its address for use by the macro errno defined in + errno.h. */ + +#include <errno.h> +#include <reent.h> +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) sint32 * __errno (void); +} +#endif + +__attribute__((weak)) sint32 * +__errno (void) +{ + return &_REENT->_errno; +}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/fcntl.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/fcntl.c new file mode 100644 index 0000000..e58221a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/fcntl.c
@@ -0,0 +1,46 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include <stdio.h> +#include "xil_types.h" + +/* + * fcntl -- Manipulate a file descriptor. + * We don't have a filesystem, so we do nothing. + */ +__attribute__((weak)) sint32 fcntl (sint32 fd, sint32 cmd, long arg) +{ + (void)fd; + (void)cmd; + (void)arg; + return 0; +}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/fstat.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/fstat.c new file mode 100644 index 0000000..c5a31f3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/fstat.c
@@ -0,0 +1,50 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include <sys/stat.h> +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf); +} +#endif +/* + * fstat -- Since we have no file system, we just return an error. + */ +__attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf) +{ + (void)fd; + buf->st_mode = S_IFCHR; /* Always pretend to be a tty */ + + return (0); +}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/getpid.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/getpid.c new file mode 100644 index 0000000..d02df5c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/getpid.c
@@ -0,0 +1,51 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include "xil_types.h" +/* + * getpid -- only one process, so just return 1. + */ +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) s32 _getpid(void); +} +#endif + +__attribute__((weak)) s32 getpid(void) +{ + return 1; +} + +__attribute__((weak)) s32 _getpid(void) +{ + return 1; +}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/inbyte.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/inbyte.c new file mode 100644 index 0000000..a5a6448 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/inbyte.c
@@ -0,0 +1,14 @@ +#include "xparameters.h" +#include "xuartps_hw.h" + +#ifdef __cplusplus +extern "C" { +#endif +char inbyte(void); +#ifdef __cplusplus +} +#endif + +char inbyte(void) { + return XUartPs_RecvByte(STDIN_BASEADDRESS); +}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu0_cfg.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu0_cfg.h new file mode 100644 index 0000000..9029bea --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu0_cfg.h
@@ -0,0 +1,1304 @@ +/* ### HEADER ### */ + +#ifndef __XDDR_XMPU0_CFG_H__ +#define __XDDR_XMPU0_CFG_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XddrXmpu0Cfg Base Address + */ +#define XDDR_XMPU0_CFG_BASEADDR 0xFD000000UL + +/** + * Register: XddrXmpu0CfgCtrl + */ +#define XDDR_XMPU0_CFG_CTRL ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000000UL ) +#define XDDR_XMPU0_CFG_CTRL_RSTVAL 0x00000003UL + +#define XDDR_XMPU0_CFG_CTRL_ALIGNCFG_SHIFT 3UL +#define XDDR_XMPU0_CFG_CTRL_ALIGNCFG_WIDTH 1UL +#define XDDR_XMPU0_CFG_CTRL_ALIGNCFG_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_CTRL_ALIGNCFG_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_CTRL_POISONCFG_SHIFT 2UL +#define XDDR_XMPU0_CFG_CTRL_POISONCFG_WIDTH 1UL +#define XDDR_XMPU0_CFG_CTRL_POISONCFG_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_CTRL_POISONCFG_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_CTRL_DEFWRALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_CTRL_DEFWRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_CTRL_DEFWRALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_CTRL_DEFWRALWD_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_CTRL_DEFRDALWD_SHIFT 0UL +#define XDDR_XMPU0_CFG_CTRL_DEFRDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_CTRL_DEFRDALWD_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_CTRL_DEFRDALWD_DEFVAL 0x1UL + +/** + * Register: XddrXmpu0CfgErrSts1 + */ +#define XDDR_XMPU0_CFG_ERR_STS1 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000004UL ) +#define XDDR_XMPU0_CFG_ERR_STS1_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_ERR_STS1_AXI_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_ERR_STS1_AXI_ADDR_WIDTH 32UL +#define XDDR_XMPU0_CFG_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL +#define XDDR_XMPU0_CFG_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgErrSts2 + */ +#define XDDR_XMPU0_CFG_ERR_STS2 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000008UL ) +#define XDDR_XMPU0_CFG_ERR_STS2_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_ERR_STS2_AXI_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_ERR_STS2_AXI_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_ERR_STS2_AXI_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_ERR_STS2_AXI_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgPoison + */ +#define XDDR_XMPU0_CFG_POISON ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000000CUL ) +#define XDDR_XMPU0_CFG_POISON_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_POISON_ATTRIB_SHIFT 20UL +#define XDDR_XMPU0_CFG_POISON_ATTRIB_WIDTH 12UL +#define XDDR_XMPU0_CFG_POISON_ATTRIB_MASK 0xfff00000UL +#define XDDR_XMPU0_CFG_POISON_ATTRIB_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_POISON_BASE_SHIFT 0UL +#define XDDR_XMPU0_CFG_POISON_BASE_WIDTH 20UL +#define XDDR_XMPU0_CFG_POISON_BASE_MASK 0x000fffffUL +#define XDDR_XMPU0_CFG_POISON_BASE_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgIsr + */ +#define XDDR_XMPU0_CFG_ISR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000010UL ) +#define XDDR_XMPU0_CFG_ISR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_ISR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU0_CFG_ISR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_ISR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_ISR_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_ISR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU0_CFG_ISR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_ISR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_ISR_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_ISR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU0_CFG_ISR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_ISR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_ISR_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_ISR_INV_APB_SHIFT 0UL +#define XDDR_XMPU0_CFG_ISR_INV_APB_WIDTH 1UL +#define XDDR_XMPU0_CFG_ISR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_ISR_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgImr + */ +#define XDDR_XMPU0_CFG_IMR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000014UL ) +#define XDDR_XMPU0_CFG_IMR_RSTVAL 0x0000000fUL + +#define XDDR_XMPU0_CFG_IMR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU0_CFG_IMR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_IMR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_IMR_SECURTYVIO_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_IMR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU0_CFG_IMR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_IMR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_IMR_WRPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_IMR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU0_CFG_IMR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_IMR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_IMR_RDPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_IMR_INV_APB_SHIFT 0UL +#define XDDR_XMPU0_CFG_IMR_INV_APB_WIDTH 1UL +#define XDDR_XMPU0_CFG_IMR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_IMR_INV_APB_DEFVAL 0x1UL + +/** + * Register: XddrXmpu0CfgIen + */ +#define XDDR_XMPU0_CFG_IEN ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000018UL ) +#define XDDR_XMPU0_CFG_IEN_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_IEN_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU0_CFG_IEN_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_IEN_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_IEN_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_IEN_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU0_CFG_IEN_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_IEN_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_IEN_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_IEN_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU0_CFG_IEN_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_IEN_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_IEN_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_IEN_INV_APB_SHIFT 0UL +#define XDDR_XMPU0_CFG_IEN_INV_APB_WIDTH 1UL +#define XDDR_XMPU0_CFG_IEN_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_IEN_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgIds + */ +#define XDDR_XMPU0_CFG_IDS ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000001CUL ) +#define XDDR_XMPU0_CFG_IDS_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_IDS_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU0_CFG_IDS_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_IDS_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_IDS_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_IDS_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU0_CFG_IDS_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_IDS_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_IDS_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_IDS_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU0_CFG_IDS_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_IDS_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_IDS_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_IDS_INV_APB_SHIFT 0UL +#define XDDR_XMPU0_CFG_IDS_INV_APB_WIDTH 1UL +#define XDDR_XMPU0_CFG_IDS_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_IDS_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgLock + */ +#define XDDR_XMPU0_CFG_LOCK ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000020UL ) +#define XDDR_XMPU0_CFG_LOCK_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_LOCK_REGWRDIS_SHIFT 0UL +#define XDDR_XMPU0_CFG_LOCK_REGWRDIS_WIDTH 1UL +#define XDDR_XMPU0_CFG_LOCK_REGWRDIS_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_LOCK_REGWRDIS_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR00Strt + */ +#define XDDR_XMPU0_CFG_R00_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000100UL ) +#define XDDR_XMPU0_CFG_R00_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R00_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R00_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R00_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R00_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR00End + */ +#define XDDR_XMPU0_CFG_R00_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000104UL ) +#define XDDR_XMPU0_CFG_R00_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R00_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R00_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R00_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R00_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR00Mstr + */ +#define XDDR_XMPU0_CFG_R00_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000108UL ) +#define XDDR_XMPU0_CFG_R00_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R00_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R00_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R00_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R00_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R00_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R00_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R00_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R00_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR00 + */ +#define XDDR_XMPU0_CFG_R00 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000010CUL ) +#define XDDR_XMPU0_CFG_R00_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R00_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R00_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R00_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R00_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R00_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R00_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R00_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R00_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R00_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R00_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R00_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R00_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R00_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R00_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R00_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R00_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R00_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R00_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R00_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R00_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR01Strt + */ +#define XDDR_XMPU0_CFG_R01_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000110UL ) +#define XDDR_XMPU0_CFG_R01_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R01_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R01_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R01_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R01_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR01End + */ +#define XDDR_XMPU0_CFG_R01_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000114UL ) +#define XDDR_XMPU0_CFG_R01_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R01_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R01_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R01_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R01_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR01Mstr + */ +#define XDDR_XMPU0_CFG_R01_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000118UL ) +#define XDDR_XMPU0_CFG_R01_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R01_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R01_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R01_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R01_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R01_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R01_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R01_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R01_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR01 + */ +#define XDDR_XMPU0_CFG_R01 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000011CUL ) +#define XDDR_XMPU0_CFG_R01_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R01_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R01_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R01_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R01_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R01_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R01_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R01_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R01_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R01_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R01_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R01_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R01_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R01_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R01_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R01_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R01_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R01_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R01_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R01_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R01_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR02Strt + */ +#define XDDR_XMPU0_CFG_R02_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000120UL ) +#define XDDR_XMPU0_CFG_R02_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R02_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R02_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R02_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R02_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR02End + */ +#define XDDR_XMPU0_CFG_R02_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000124UL ) +#define XDDR_XMPU0_CFG_R02_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R02_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R02_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R02_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R02_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR02Mstr + */ +#define XDDR_XMPU0_CFG_R02_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000128UL ) +#define XDDR_XMPU0_CFG_R02_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R02_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R02_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R02_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R02_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R02_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R02_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R02_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R02_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR02 + */ +#define XDDR_XMPU0_CFG_R02 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000012CUL ) +#define XDDR_XMPU0_CFG_R02_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R02_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R02_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R02_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R02_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R02_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R02_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R02_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R02_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R02_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R02_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R02_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R02_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R02_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R02_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R02_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R02_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R02_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R02_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R02_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R02_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR03Strt + */ +#define XDDR_XMPU0_CFG_R03_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000130UL ) +#define XDDR_XMPU0_CFG_R03_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R03_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R03_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R03_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R03_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR03End + */ +#define XDDR_XMPU0_CFG_R03_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000134UL ) +#define XDDR_XMPU0_CFG_R03_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R03_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R03_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R03_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R03_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR03Mstr + */ +#define XDDR_XMPU0_CFG_R03_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000138UL ) +#define XDDR_XMPU0_CFG_R03_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R03_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R03_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R03_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R03_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R03_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R03_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R03_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R03_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR03 + */ +#define XDDR_XMPU0_CFG_R03 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000013CUL ) +#define XDDR_XMPU0_CFG_R03_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R03_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R03_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R03_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R03_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R03_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R03_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R03_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R03_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R03_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R03_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R03_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R03_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R03_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R03_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R03_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R03_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R03_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R03_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R03_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R03_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR04Strt + */ +#define XDDR_XMPU0_CFG_R04_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000140UL ) +#define XDDR_XMPU0_CFG_R04_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R04_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R04_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R04_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R04_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR04End + */ +#define XDDR_XMPU0_CFG_R04_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000144UL ) +#define XDDR_XMPU0_CFG_R04_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R04_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R04_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R04_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R04_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR04Mstr + */ +#define XDDR_XMPU0_CFG_R04_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000148UL ) +#define XDDR_XMPU0_CFG_R04_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R04_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R04_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R04_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R04_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R04_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R04_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R04_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R04_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR04 + */ +#define XDDR_XMPU0_CFG_R04 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000014CUL ) +#define XDDR_XMPU0_CFG_R04_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R04_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R04_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R04_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R04_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R04_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R04_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R04_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R04_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R04_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R04_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R04_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R04_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R04_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R04_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R04_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R04_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R04_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R04_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R04_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R04_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR05Strt + */ +#define XDDR_XMPU0_CFG_R05_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000150UL ) +#define XDDR_XMPU0_CFG_R05_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R05_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R05_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R05_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R05_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR05End + */ +#define XDDR_XMPU0_CFG_R05_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000154UL ) +#define XDDR_XMPU0_CFG_R05_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R05_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R05_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R05_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R05_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR05Mstr + */ +#define XDDR_XMPU0_CFG_R05_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000158UL ) +#define XDDR_XMPU0_CFG_R05_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R05_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R05_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R05_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R05_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R05_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R05_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R05_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R05_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR05 + */ +#define XDDR_XMPU0_CFG_R05 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000015CUL ) +#define XDDR_XMPU0_CFG_R05_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R05_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R05_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R05_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R05_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R05_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R05_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R05_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R05_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R05_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R05_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R05_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R05_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R05_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R05_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R05_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R05_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R05_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R05_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R05_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R05_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR06Strt + */ +#define XDDR_XMPU0_CFG_R06_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000160UL ) +#define XDDR_XMPU0_CFG_R06_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R06_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R06_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R06_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R06_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR06End + */ +#define XDDR_XMPU0_CFG_R06_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000164UL ) +#define XDDR_XMPU0_CFG_R06_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R06_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R06_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R06_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R06_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR06Mstr + */ +#define XDDR_XMPU0_CFG_R06_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000168UL ) +#define XDDR_XMPU0_CFG_R06_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R06_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R06_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R06_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R06_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R06_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R06_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R06_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R06_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR06 + */ +#define XDDR_XMPU0_CFG_R06 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000016CUL ) +#define XDDR_XMPU0_CFG_R06_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R06_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R06_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R06_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R06_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R06_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R06_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R06_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R06_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R06_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R06_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R06_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R06_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R06_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R06_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R06_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R06_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R06_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R06_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R06_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R06_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR07Strt + */ +#define XDDR_XMPU0_CFG_R07_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000170UL ) +#define XDDR_XMPU0_CFG_R07_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R07_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R07_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R07_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R07_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR07End + */ +#define XDDR_XMPU0_CFG_R07_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000174UL ) +#define XDDR_XMPU0_CFG_R07_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R07_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R07_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R07_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R07_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR07Mstr + */ +#define XDDR_XMPU0_CFG_R07_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000178UL ) +#define XDDR_XMPU0_CFG_R07_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R07_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R07_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R07_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R07_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R07_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R07_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R07_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R07_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR07 + */ +#define XDDR_XMPU0_CFG_R07 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000017CUL ) +#define XDDR_XMPU0_CFG_R07_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R07_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R07_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R07_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R07_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R07_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R07_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R07_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R07_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R07_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R07_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R07_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R07_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R07_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R07_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R07_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R07_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R07_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R07_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R07_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R07_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR08Strt + */ +#define XDDR_XMPU0_CFG_R08_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000180UL ) +#define XDDR_XMPU0_CFG_R08_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R08_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R08_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R08_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R08_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR08End + */ +#define XDDR_XMPU0_CFG_R08_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000184UL ) +#define XDDR_XMPU0_CFG_R08_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R08_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R08_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R08_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R08_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR08Mstr + */ +#define XDDR_XMPU0_CFG_R08_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000188UL ) +#define XDDR_XMPU0_CFG_R08_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R08_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R08_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R08_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R08_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R08_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R08_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R08_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R08_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR08 + */ +#define XDDR_XMPU0_CFG_R08 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000018CUL ) +#define XDDR_XMPU0_CFG_R08_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R08_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R08_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R08_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R08_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R08_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R08_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R08_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R08_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R08_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R08_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R08_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R08_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R08_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R08_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R08_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R08_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R08_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R08_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R08_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R08_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR09Strt + */ +#define XDDR_XMPU0_CFG_R09_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000190UL ) +#define XDDR_XMPU0_CFG_R09_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R09_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R09_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R09_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R09_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR09End + */ +#define XDDR_XMPU0_CFG_R09_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000194UL ) +#define XDDR_XMPU0_CFG_R09_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R09_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R09_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R09_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R09_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR09Mstr + */ +#define XDDR_XMPU0_CFG_R09_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000198UL ) +#define XDDR_XMPU0_CFG_R09_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R09_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R09_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R09_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R09_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R09_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R09_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R09_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R09_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR09 + */ +#define XDDR_XMPU0_CFG_R09 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000019CUL ) +#define XDDR_XMPU0_CFG_R09_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R09_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R09_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R09_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R09_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R09_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R09_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R09_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R09_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R09_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R09_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R09_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R09_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R09_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R09_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R09_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R09_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R09_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R09_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R09_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R09_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR10Strt + */ +#define XDDR_XMPU0_CFG_R10_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001A0UL ) +#define XDDR_XMPU0_CFG_R10_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R10_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R10_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R10_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R10_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR10End + */ +#define XDDR_XMPU0_CFG_R10_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001A4UL ) +#define XDDR_XMPU0_CFG_R10_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R10_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R10_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R10_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R10_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR10Mstr + */ +#define XDDR_XMPU0_CFG_R10_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001A8UL ) +#define XDDR_XMPU0_CFG_R10_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R10_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R10_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R10_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R10_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R10_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R10_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R10_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R10_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR10 + */ +#define XDDR_XMPU0_CFG_R10 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001ACUL ) +#define XDDR_XMPU0_CFG_R10_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R10_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R10_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R10_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R10_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R10_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R10_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R10_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R10_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R10_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R10_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R10_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R10_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R10_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R10_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R10_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R10_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R10_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R10_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R10_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R10_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR11Strt + */ +#define XDDR_XMPU0_CFG_R11_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001B0UL ) +#define XDDR_XMPU0_CFG_R11_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R11_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R11_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R11_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R11_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR11End + */ +#define XDDR_XMPU0_CFG_R11_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001B4UL ) +#define XDDR_XMPU0_CFG_R11_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R11_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R11_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R11_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R11_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR11Mstr + */ +#define XDDR_XMPU0_CFG_R11_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001B8UL ) +#define XDDR_XMPU0_CFG_R11_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R11_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R11_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R11_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R11_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R11_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R11_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R11_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R11_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR11 + */ +#define XDDR_XMPU0_CFG_R11 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001BCUL ) +#define XDDR_XMPU0_CFG_R11_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R11_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R11_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R11_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R11_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R11_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R11_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R11_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R11_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R11_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R11_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R11_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R11_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R11_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R11_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R11_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R11_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R11_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R11_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R11_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R11_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR12Strt + */ +#define XDDR_XMPU0_CFG_R12_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001C0UL ) +#define XDDR_XMPU0_CFG_R12_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R12_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R12_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R12_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R12_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR12End + */ +#define XDDR_XMPU0_CFG_R12_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001C4UL ) +#define XDDR_XMPU0_CFG_R12_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R12_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R12_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R12_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R12_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR12Mstr + */ +#define XDDR_XMPU0_CFG_R12_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001C8UL ) +#define XDDR_XMPU0_CFG_R12_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R12_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R12_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R12_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R12_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R12_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R12_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R12_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R12_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR12 + */ +#define XDDR_XMPU0_CFG_R12 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001CCUL ) +#define XDDR_XMPU0_CFG_R12_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R12_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R12_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R12_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R12_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R12_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R12_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R12_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R12_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R12_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R12_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R12_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R12_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R12_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R12_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R12_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R12_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R12_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R12_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R12_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R12_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR13Strt + */ +#define XDDR_XMPU0_CFG_R13_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001D0UL ) +#define XDDR_XMPU0_CFG_R13_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R13_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R13_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R13_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R13_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR13End + */ +#define XDDR_XMPU0_CFG_R13_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001D4UL ) +#define XDDR_XMPU0_CFG_R13_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R13_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R13_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R13_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R13_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR13Mstr + */ +#define XDDR_XMPU0_CFG_R13_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001D8UL ) +#define XDDR_XMPU0_CFG_R13_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R13_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R13_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R13_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R13_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R13_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R13_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R13_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R13_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR13 + */ +#define XDDR_XMPU0_CFG_R13 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001DCUL ) +#define XDDR_XMPU0_CFG_R13_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R13_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R13_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R13_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R13_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R13_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R13_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R13_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R13_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R13_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R13_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R13_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R13_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R13_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R13_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R13_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R13_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R13_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R13_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R13_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R13_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR14Strt + */ +#define XDDR_XMPU0_CFG_R14_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001E0UL ) +#define XDDR_XMPU0_CFG_R14_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R14_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R14_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R14_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R14_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR14End + */ +#define XDDR_XMPU0_CFG_R14_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001E4UL ) +#define XDDR_XMPU0_CFG_R14_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R14_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R14_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R14_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R14_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR14Mstr + */ +#define XDDR_XMPU0_CFG_R14_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001E8UL ) +#define XDDR_XMPU0_CFG_R14_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R14_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R14_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R14_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R14_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R14_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R14_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R14_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R14_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR14 + */ +#define XDDR_XMPU0_CFG_R14 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001ECUL ) +#define XDDR_XMPU0_CFG_R14_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R14_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R14_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R14_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R14_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R14_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R14_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R14_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R14_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R14_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R14_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R14_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R14_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R14_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R14_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R14_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R14_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R14_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R14_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R14_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R14_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR15Strt + */ +#define XDDR_XMPU0_CFG_R15_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001F0UL ) +#define XDDR_XMPU0_CFG_R15_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R15_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R15_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R15_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R15_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR15End + */ +#define XDDR_XMPU0_CFG_R15_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001F4UL ) +#define XDDR_XMPU0_CFG_R15_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R15_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R15_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R15_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R15_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR15Mstr + */ +#define XDDR_XMPU0_CFG_R15_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001F8UL ) +#define XDDR_XMPU0_CFG_R15_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R15_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R15_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R15_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R15_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R15_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R15_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R15_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R15_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR15 + */ +#define XDDR_XMPU0_CFG_R15 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001FCUL ) +#define XDDR_XMPU0_CFG_R15_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R15_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R15_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R15_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R15_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R15_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R15_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R15_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R15_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R15_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R15_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R15_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R15_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R15_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R15_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R15_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R15_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R15_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R15_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R15_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R15_EN_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XDDR_XMPU0_CFG_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu1_cfg.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu1_cfg.h new file mode 100644 index 0000000..e2fa6d4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu1_cfg.h
@@ -0,0 +1,1304 @@ +/* ### HEADER ### */ + +#ifndef __XDDR_XMPU1_CFG_H__ +#define __XDDR_XMPU1_CFG_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XddrXmpu1Cfg Base Address + */ +#define XDDR_XMPU1_CFG_BASEADDR 0xFD010000UL + +/** + * Register: XddrXmpu1CfgCtrl + */ +#define XDDR_XMPU1_CFG_CTRL ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000000UL ) +#define XDDR_XMPU1_CFG_CTRL_RSTVAL 0x00000003UL + +#define XDDR_XMPU1_CFG_CTRL_ALIGNCFG_SHIFT 3UL +#define XDDR_XMPU1_CFG_CTRL_ALIGNCFG_WIDTH 1UL +#define XDDR_XMPU1_CFG_CTRL_ALIGNCFG_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_CTRL_ALIGNCFG_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_CTRL_POISONCFG_SHIFT 2UL +#define XDDR_XMPU1_CFG_CTRL_POISONCFG_WIDTH 1UL +#define XDDR_XMPU1_CFG_CTRL_POISONCFG_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_CTRL_POISONCFG_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_CTRL_DEFWRALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_CTRL_DEFWRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_CTRL_DEFWRALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_CTRL_DEFWRALWD_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_CTRL_DEFRDALWD_SHIFT 0UL +#define XDDR_XMPU1_CFG_CTRL_DEFRDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_CTRL_DEFRDALWD_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_CTRL_DEFRDALWD_DEFVAL 0x1UL + +/** + * Register: XddrXmpu1CfgErrSts1 + */ +#define XDDR_XMPU1_CFG_ERR_STS1 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000004UL ) +#define XDDR_XMPU1_CFG_ERR_STS1_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_ERR_STS1_AXI_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_ERR_STS1_AXI_ADDR_WIDTH 32UL +#define XDDR_XMPU1_CFG_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL +#define XDDR_XMPU1_CFG_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgErrSts2 + */ +#define XDDR_XMPU1_CFG_ERR_STS2 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000008UL ) +#define XDDR_XMPU1_CFG_ERR_STS2_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_ERR_STS2_AXI_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_ERR_STS2_AXI_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_ERR_STS2_AXI_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_ERR_STS2_AXI_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgPoison + */ +#define XDDR_XMPU1_CFG_POISON ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000000CUL ) +#define XDDR_XMPU1_CFG_POISON_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_POISON_ATTRIB_SHIFT 20UL +#define XDDR_XMPU1_CFG_POISON_ATTRIB_WIDTH 12UL +#define XDDR_XMPU1_CFG_POISON_ATTRIB_MASK 0xfff00000UL +#define XDDR_XMPU1_CFG_POISON_ATTRIB_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_POISON_BASE_SHIFT 0UL +#define XDDR_XMPU1_CFG_POISON_BASE_WIDTH 20UL +#define XDDR_XMPU1_CFG_POISON_BASE_MASK 0x000fffffUL +#define XDDR_XMPU1_CFG_POISON_BASE_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgIsr + */ +#define XDDR_XMPU1_CFG_ISR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000010UL ) +#define XDDR_XMPU1_CFG_ISR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_ISR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU1_CFG_ISR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_ISR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_ISR_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_ISR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU1_CFG_ISR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_ISR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_ISR_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_ISR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU1_CFG_ISR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_ISR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_ISR_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_ISR_INV_APB_SHIFT 0UL +#define XDDR_XMPU1_CFG_ISR_INV_APB_WIDTH 1UL +#define XDDR_XMPU1_CFG_ISR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_ISR_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgImr + */ +#define XDDR_XMPU1_CFG_IMR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000014UL ) +#define XDDR_XMPU1_CFG_IMR_RSTVAL 0x0000000fUL + +#define XDDR_XMPU1_CFG_IMR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU1_CFG_IMR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_IMR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_IMR_SECURTYVIO_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_IMR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU1_CFG_IMR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_IMR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_IMR_WRPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_IMR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU1_CFG_IMR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_IMR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_IMR_RDPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_IMR_INV_APB_SHIFT 0UL +#define XDDR_XMPU1_CFG_IMR_INV_APB_WIDTH 1UL +#define XDDR_XMPU1_CFG_IMR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_IMR_INV_APB_DEFVAL 0x1UL + +/** + * Register: XddrXmpu1CfgIen + */ +#define XDDR_XMPU1_CFG_IEN ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000018UL ) +#define XDDR_XMPU1_CFG_IEN_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_IEN_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU1_CFG_IEN_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_IEN_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_IEN_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_IEN_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU1_CFG_IEN_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_IEN_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_IEN_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_IEN_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU1_CFG_IEN_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_IEN_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_IEN_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_IEN_INV_APB_SHIFT 0UL +#define XDDR_XMPU1_CFG_IEN_INV_APB_WIDTH 1UL +#define XDDR_XMPU1_CFG_IEN_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_IEN_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgIds + */ +#define XDDR_XMPU1_CFG_IDS ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000001CUL ) +#define XDDR_XMPU1_CFG_IDS_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_IDS_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU1_CFG_IDS_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_IDS_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_IDS_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_IDS_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU1_CFG_IDS_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_IDS_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_IDS_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_IDS_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU1_CFG_IDS_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_IDS_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_IDS_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_IDS_INV_APB_SHIFT 0UL +#define XDDR_XMPU1_CFG_IDS_INV_APB_WIDTH 1UL +#define XDDR_XMPU1_CFG_IDS_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_IDS_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgLock + */ +#define XDDR_XMPU1_CFG_LOCK ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000020UL ) +#define XDDR_XMPU1_CFG_LOCK_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_LOCK_REGWRDIS_SHIFT 0UL +#define XDDR_XMPU1_CFG_LOCK_REGWRDIS_WIDTH 1UL +#define XDDR_XMPU1_CFG_LOCK_REGWRDIS_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_LOCK_REGWRDIS_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR00Strt + */ +#define XDDR_XMPU1_CFG_R00_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000100UL ) +#define XDDR_XMPU1_CFG_R00_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R00_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R00_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R00_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R00_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR00End + */ +#define XDDR_XMPU1_CFG_R00_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000104UL ) +#define XDDR_XMPU1_CFG_R00_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R00_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R00_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R00_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R00_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR00Mstr + */ +#define XDDR_XMPU1_CFG_R00_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000108UL ) +#define XDDR_XMPU1_CFG_R00_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R00_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R00_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R00_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R00_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R00_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R00_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R00_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R00_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR00 + */ +#define XDDR_XMPU1_CFG_R00 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000010CUL ) +#define XDDR_XMPU1_CFG_R00_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R00_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R00_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R00_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R00_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R00_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R00_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R00_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R00_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R00_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R00_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R00_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R00_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R00_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R00_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R00_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R00_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R00_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R00_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R00_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R00_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR01Strt + */ +#define XDDR_XMPU1_CFG_R01_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000110UL ) +#define XDDR_XMPU1_CFG_R01_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R01_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R01_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R01_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R01_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR01End + */ +#define XDDR_XMPU1_CFG_R01_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000114UL ) +#define XDDR_XMPU1_CFG_R01_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R01_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R01_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R01_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R01_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR01Mstr + */ +#define XDDR_XMPU1_CFG_R01_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000118UL ) +#define XDDR_XMPU1_CFG_R01_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R01_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R01_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R01_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R01_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R01_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R01_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R01_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R01_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR01 + */ +#define XDDR_XMPU1_CFG_R01 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000011CUL ) +#define XDDR_XMPU1_CFG_R01_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R01_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R01_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R01_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R01_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R01_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R01_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R01_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R01_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R01_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R01_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R01_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R01_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R01_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R01_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R01_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R01_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R01_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R01_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R01_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R01_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR02Strt + */ +#define XDDR_XMPU1_CFG_R02_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000120UL ) +#define XDDR_XMPU1_CFG_R02_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R02_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R02_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R02_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R02_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR02End + */ +#define XDDR_XMPU1_CFG_R02_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000124UL ) +#define XDDR_XMPU1_CFG_R02_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R02_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R02_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R02_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R02_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR02Mstr + */ +#define XDDR_XMPU1_CFG_R02_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000128UL ) +#define XDDR_XMPU1_CFG_R02_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R02_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R02_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R02_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R02_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R02_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R02_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R02_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R02_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR02 + */ +#define XDDR_XMPU1_CFG_R02 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000012CUL ) +#define XDDR_XMPU1_CFG_R02_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R02_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R02_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R02_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R02_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R02_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R02_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R02_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R02_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R02_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R02_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R02_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R02_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R02_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R02_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R02_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R02_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R02_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R02_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R02_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R02_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR03Strt + */ +#define XDDR_XMPU1_CFG_R03_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000130UL ) +#define XDDR_XMPU1_CFG_R03_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R03_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R03_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R03_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R03_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR03End + */ +#define XDDR_XMPU1_CFG_R03_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000134UL ) +#define XDDR_XMPU1_CFG_R03_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R03_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R03_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R03_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R03_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR03Mstr + */ +#define XDDR_XMPU1_CFG_R03_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000138UL ) +#define XDDR_XMPU1_CFG_R03_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R03_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R03_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R03_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R03_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R03_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R03_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R03_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R03_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR03 + */ +#define XDDR_XMPU1_CFG_R03 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000013CUL ) +#define XDDR_XMPU1_CFG_R03_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R03_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R03_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R03_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R03_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R03_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R03_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R03_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R03_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R03_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R03_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R03_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R03_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R03_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R03_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R03_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R03_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R03_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R03_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R03_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R03_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR04Strt + */ +#define XDDR_XMPU1_CFG_R04_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000140UL ) +#define XDDR_XMPU1_CFG_R04_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R04_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R04_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R04_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R04_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR04End + */ +#define XDDR_XMPU1_CFG_R04_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000144UL ) +#define XDDR_XMPU1_CFG_R04_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R04_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R04_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R04_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R04_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR04Mstr + */ +#define XDDR_XMPU1_CFG_R04_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000148UL ) +#define XDDR_XMPU1_CFG_R04_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R04_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R04_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R04_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R04_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R04_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R04_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R04_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R04_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR04 + */ +#define XDDR_XMPU1_CFG_R04 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000014CUL ) +#define XDDR_XMPU1_CFG_R04_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R04_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R04_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R04_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R04_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R04_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R04_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R04_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R04_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R04_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R04_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R04_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R04_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R04_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R04_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R04_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R04_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R04_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R04_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R04_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R04_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR05Strt + */ +#define XDDR_XMPU1_CFG_R05_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000150UL ) +#define XDDR_XMPU1_CFG_R05_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R05_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R05_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R05_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R05_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR05End + */ +#define XDDR_XMPU1_CFG_R05_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000154UL ) +#define XDDR_XMPU1_CFG_R05_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R05_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R05_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R05_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R05_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR05Mstr + */ +#define XDDR_XMPU1_CFG_R05_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000158UL ) +#define XDDR_XMPU1_CFG_R05_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R05_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R05_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R05_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R05_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R05_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R05_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R05_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R05_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR05 + */ +#define XDDR_XMPU1_CFG_R05 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000015CUL ) +#define XDDR_XMPU1_CFG_R05_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R05_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R05_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R05_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R05_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R05_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R05_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R05_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R05_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R05_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R05_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R05_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R05_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R05_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R05_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R05_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R05_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R05_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R05_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R05_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R05_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR06Strt + */ +#define XDDR_XMPU1_CFG_R06_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000160UL ) +#define XDDR_XMPU1_CFG_R06_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R06_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R06_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R06_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R06_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR06End + */ +#define XDDR_XMPU1_CFG_R06_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000164UL ) +#define XDDR_XMPU1_CFG_R06_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R06_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R06_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R06_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R06_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR06Mstr + */ +#define XDDR_XMPU1_CFG_R06_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000168UL ) +#define XDDR_XMPU1_CFG_R06_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R06_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R06_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R06_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R06_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R06_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R06_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R06_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R06_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR06 + */ +#define XDDR_XMPU1_CFG_R06 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000016CUL ) +#define XDDR_XMPU1_CFG_R06_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R06_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R06_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R06_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R06_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R06_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R06_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R06_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R06_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R06_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R06_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R06_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R06_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R06_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R06_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R06_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R06_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R06_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R06_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R06_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R06_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR07Strt + */ +#define XDDR_XMPU1_CFG_R07_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000170UL ) +#define XDDR_XMPU1_CFG_R07_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R07_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R07_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R07_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R07_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR07End + */ +#define XDDR_XMPU1_CFG_R07_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000174UL ) +#define XDDR_XMPU1_CFG_R07_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R07_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R07_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R07_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R07_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR07Mstr + */ +#define XDDR_XMPU1_CFG_R07_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000178UL ) +#define XDDR_XMPU1_CFG_R07_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R07_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R07_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R07_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R07_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R07_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R07_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R07_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R07_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR07 + */ +#define XDDR_XMPU1_CFG_R07 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000017CUL ) +#define XDDR_XMPU1_CFG_R07_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R07_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R07_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R07_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R07_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R07_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R07_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R07_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R07_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R07_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R07_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R07_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R07_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R07_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R07_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R07_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R07_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R07_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R07_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R07_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R07_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR08Strt + */ +#define XDDR_XMPU1_CFG_R08_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000180UL ) +#define XDDR_XMPU1_CFG_R08_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R08_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R08_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R08_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R08_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR08End + */ +#define XDDR_XMPU1_CFG_R08_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000184UL ) +#define XDDR_XMPU1_CFG_R08_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R08_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R08_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R08_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R08_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR08Mstr + */ +#define XDDR_XMPU1_CFG_R08_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000188UL ) +#define XDDR_XMPU1_CFG_R08_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R08_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R08_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R08_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R08_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R08_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R08_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R08_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R08_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR08 + */ +#define XDDR_XMPU1_CFG_R08 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000018CUL ) +#define XDDR_XMPU1_CFG_R08_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R08_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R08_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R08_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R08_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R08_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R08_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R08_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R08_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R08_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R08_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R08_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R08_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R08_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R08_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R08_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R08_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R08_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R08_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R08_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R08_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR09Strt + */ +#define XDDR_XMPU1_CFG_R09_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000190UL ) +#define XDDR_XMPU1_CFG_R09_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R09_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R09_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R09_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R09_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR09End + */ +#define XDDR_XMPU1_CFG_R09_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000194UL ) +#define XDDR_XMPU1_CFG_R09_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R09_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R09_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R09_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R09_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR09Mstr + */ +#define XDDR_XMPU1_CFG_R09_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000198UL ) +#define XDDR_XMPU1_CFG_R09_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R09_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R09_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R09_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R09_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R09_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R09_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R09_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R09_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR09 + */ +#define XDDR_XMPU1_CFG_R09 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000019CUL ) +#define XDDR_XMPU1_CFG_R09_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R09_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R09_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R09_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R09_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R09_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R09_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R09_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R09_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R09_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R09_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R09_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R09_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R09_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R09_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R09_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R09_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R09_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R09_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R09_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R09_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR10Strt + */ +#define XDDR_XMPU1_CFG_R10_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001A0UL ) +#define XDDR_XMPU1_CFG_R10_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R10_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R10_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R10_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R10_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR10End + */ +#define XDDR_XMPU1_CFG_R10_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001A4UL ) +#define XDDR_XMPU1_CFG_R10_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R10_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R10_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R10_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R10_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR10Mstr + */ +#define XDDR_XMPU1_CFG_R10_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001A8UL ) +#define XDDR_XMPU1_CFG_R10_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R10_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R10_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R10_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R10_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R10_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R10_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R10_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R10_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR10 + */ +#define XDDR_XMPU1_CFG_R10 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001ACUL ) +#define XDDR_XMPU1_CFG_R10_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R10_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R10_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R10_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R10_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R10_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R10_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R10_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R10_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R10_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R10_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R10_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R10_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R10_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R10_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R10_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R10_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R10_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R10_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R10_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R10_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR11Strt + */ +#define XDDR_XMPU1_CFG_R11_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001B0UL ) +#define XDDR_XMPU1_CFG_R11_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R11_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R11_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R11_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R11_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR11End + */ +#define XDDR_XMPU1_CFG_R11_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001B4UL ) +#define XDDR_XMPU1_CFG_R11_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R11_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R11_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R11_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R11_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR11Mstr + */ +#define XDDR_XMPU1_CFG_R11_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001B8UL ) +#define XDDR_XMPU1_CFG_R11_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R11_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R11_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R11_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R11_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R11_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R11_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R11_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R11_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR11 + */ +#define XDDR_XMPU1_CFG_R11 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001BCUL ) +#define XDDR_XMPU1_CFG_R11_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R11_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R11_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R11_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R11_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R11_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R11_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R11_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R11_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R11_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R11_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R11_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R11_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R11_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R11_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R11_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R11_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R11_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R11_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R11_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R11_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR12Strt + */ +#define XDDR_XMPU1_CFG_R12_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001C0UL ) +#define XDDR_XMPU1_CFG_R12_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R12_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R12_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R12_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R12_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR12End + */ +#define XDDR_XMPU1_CFG_R12_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001C4UL ) +#define XDDR_XMPU1_CFG_R12_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R12_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R12_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R12_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R12_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR12Mstr + */ +#define XDDR_XMPU1_CFG_R12_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001C8UL ) +#define XDDR_XMPU1_CFG_R12_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R12_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R12_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R12_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R12_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R12_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R12_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R12_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R12_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR12 + */ +#define XDDR_XMPU1_CFG_R12 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001CCUL ) +#define XDDR_XMPU1_CFG_R12_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R12_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R12_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R12_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R12_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R12_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R12_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R12_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R12_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R12_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R12_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R12_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R12_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R12_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R12_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R12_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R12_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R12_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R12_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R12_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R12_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR13Strt + */ +#define XDDR_XMPU1_CFG_R13_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001D0UL ) +#define XDDR_XMPU1_CFG_R13_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R13_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R13_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R13_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R13_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR13End + */ +#define XDDR_XMPU1_CFG_R13_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001D4UL ) +#define XDDR_XMPU1_CFG_R13_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R13_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R13_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R13_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R13_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR13Mstr + */ +#define XDDR_XMPU1_CFG_R13_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001D8UL ) +#define XDDR_XMPU1_CFG_R13_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R13_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R13_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R13_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R13_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R13_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R13_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R13_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R13_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR13 + */ +#define XDDR_XMPU1_CFG_R13 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001DCUL ) +#define XDDR_XMPU1_CFG_R13_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R13_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R13_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R13_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R13_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R13_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R13_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R13_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R13_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R13_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R13_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R13_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R13_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R13_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R13_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R13_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R13_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R13_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R13_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R13_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R13_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR14Strt + */ +#define XDDR_XMPU1_CFG_R14_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001E0UL ) +#define XDDR_XMPU1_CFG_R14_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R14_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R14_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R14_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R14_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR14End + */ +#define XDDR_XMPU1_CFG_R14_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001E4UL ) +#define XDDR_XMPU1_CFG_R14_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R14_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R14_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R14_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R14_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR14Mstr + */ +#define XDDR_XMPU1_CFG_R14_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001E8UL ) +#define XDDR_XMPU1_CFG_R14_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R14_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R14_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R14_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R14_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R14_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R14_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R14_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R14_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR14 + */ +#define XDDR_XMPU1_CFG_R14 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001ECUL ) +#define XDDR_XMPU1_CFG_R14_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R14_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R14_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R14_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R14_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R14_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R14_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R14_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R14_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R14_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R14_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R14_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R14_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R14_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R14_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R14_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R14_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R14_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R14_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R14_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R14_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR15Strt + */ +#define XDDR_XMPU1_CFG_R15_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001F0UL ) +#define XDDR_XMPU1_CFG_R15_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R15_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R15_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R15_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R15_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR15End + */ +#define XDDR_XMPU1_CFG_R15_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001F4UL ) +#define XDDR_XMPU1_CFG_R15_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R15_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R15_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R15_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R15_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR15Mstr + */ +#define XDDR_XMPU1_CFG_R15_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001F8UL ) +#define XDDR_XMPU1_CFG_R15_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R15_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R15_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R15_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R15_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R15_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R15_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R15_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R15_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR15 + */ +#define XDDR_XMPU1_CFG_R15 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001FCUL ) +#define XDDR_XMPU1_CFG_R15_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R15_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R15_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R15_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R15_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R15_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R15_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R15_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R15_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R15_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R15_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R15_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R15_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R15_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R15_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R15_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R15_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R15_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R15_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R15_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R15_EN_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XDDR_XMPU1_CFG_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu2_cfg.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu2_cfg.h new file mode 100644 index 0000000..55ea2a7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu2_cfg.h
@@ -0,0 +1,1304 @@ +/* ### HEADER ### */ + +#ifndef __XDDR_XMPU2_CFG_H__ +#define __XDDR_XMPU2_CFG_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XddrXmpu2Cfg Base Address + */ +#define XDDR_XMPU2_CFG_BASEADDR 0xFD020000UL + +/** + * Register: XddrXmpu2CfgCtrl + */ +#define XDDR_XMPU2_CFG_CTRL ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000000UL ) +#define XDDR_XMPU2_CFG_CTRL_RSTVAL 0x00000003UL + +#define XDDR_XMPU2_CFG_CTRL_ALIGNCFG_SHIFT 3UL +#define XDDR_XMPU2_CFG_CTRL_ALIGNCFG_WIDTH 1UL +#define XDDR_XMPU2_CFG_CTRL_ALIGNCFG_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_CTRL_ALIGNCFG_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_CTRL_POISONCFG_SHIFT 2UL +#define XDDR_XMPU2_CFG_CTRL_POISONCFG_WIDTH 1UL +#define XDDR_XMPU2_CFG_CTRL_POISONCFG_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_CTRL_POISONCFG_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_CTRL_DEFWRALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_CTRL_DEFWRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_CTRL_DEFWRALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_CTRL_DEFWRALWD_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_CTRL_DEFRDALWD_SHIFT 0UL +#define XDDR_XMPU2_CFG_CTRL_DEFRDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_CTRL_DEFRDALWD_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_CTRL_DEFRDALWD_DEFVAL 0x1UL + +/** + * Register: XddrXmpu2CfgErrSts1 + */ +#define XDDR_XMPU2_CFG_ERR_STS1 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000004UL ) +#define XDDR_XMPU2_CFG_ERR_STS1_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_ERR_STS1_AXI_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_ERR_STS1_AXI_ADDR_WIDTH 32UL +#define XDDR_XMPU2_CFG_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL +#define XDDR_XMPU2_CFG_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgErrSts2 + */ +#define XDDR_XMPU2_CFG_ERR_STS2 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000008UL ) +#define XDDR_XMPU2_CFG_ERR_STS2_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_ERR_STS2_AXI_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_ERR_STS2_AXI_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_ERR_STS2_AXI_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_ERR_STS2_AXI_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgPoison + */ +#define XDDR_XMPU2_CFG_POISON ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000000CUL ) +#define XDDR_XMPU2_CFG_POISON_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_POISON_ATTRIB_SHIFT 20UL +#define XDDR_XMPU2_CFG_POISON_ATTRIB_WIDTH 12UL +#define XDDR_XMPU2_CFG_POISON_ATTRIB_MASK 0xfff00000UL +#define XDDR_XMPU2_CFG_POISON_ATTRIB_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_POISON_BASE_SHIFT 0UL +#define XDDR_XMPU2_CFG_POISON_BASE_WIDTH 20UL +#define XDDR_XMPU2_CFG_POISON_BASE_MASK 0x000fffffUL +#define XDDR_XMPU2_CFG_POISON_BASE_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgIsr + */ +#define XDDR_XMPU2_CFG_ISR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000010UL ) +#define XDDR_XMPU2_CFG_ISR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_ISR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU2_CFG_ISR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_ISR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_ISR_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_ISR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU2_CFG_ISR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_ISR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_ISR_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_ISR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU2_CFG_ISR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_ISR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_ISR_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_ISR_INV_APB_SHIFT 0UL +#define XDDR_XMPU2_CFG_ISR_INV_APB_WIDTH 1UL +#define XDDR_XMPU2_CFG_ISR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_ISR_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgImr + */ +#define XDDR_XMPU2_CFG_IMR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000014UL ) +#define XDDR_XMPU2_CFG_IMR_RSTVAL 0x0000000fUL + +#define XDDR_XMPU2_CFG_IMR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU2_CFG_IMR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_IMR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_IMR_SECURTYVIO_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_IMR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU2_CFG_IMR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_IMR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_IMR_WRPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_IMR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU2_CFG_IMR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_IMR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_IMR_RDPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_IMR_INV_APB_SHIFT 0UL +#define XDDR_XMPU2_CFG_IMR_INV_APB_WIDTH 1UL +#define XDDR_XMPU2_CFG_IMR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_IMR_INV_APB_DEFVAL 0x1UL + +/** + * Register: XddrXmpu2CfgIen + */ +#define XDDR_XMPU2_CFG_IEN ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000018UL ) +#define XDDR_XMPU2_CFG_IEN_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_IEN_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU2_CFG_IEN_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_IEN_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_IEN_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_IEN_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU2_CFG_IEN_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_IEN_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_IEN_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_IEN_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU2_CFG_IEN_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_IEN_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_IEN_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_IEN_INV_APB_SHIFT 0UL +#define XDDR_XMPU2_CFG_IEN_INV_APB_WIDTH 1UL +#define XDDR_XMPU2_CFG_IEN_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_IEN_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgIds + */ +#define XDDR_XMPU2_CFG_IDS ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000001CUL ) +#define XDDR_XMPU2_CFG_IDS_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_IDS_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU2_CFG_IDS_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_IDS_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_IDS_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_IDS_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU2_CFG_IDS_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_IDS_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_IDS_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_IDS_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU2_CFG_IDS_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_IDS_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_IDS_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_IDS_INV_APB_SHIFT 0UL +#define XDDR_XMPU2_CFG_IDS_INV_APB_WIDTH 1UL +#define XDDR_XMPU2_CFG_IDS_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_IDS_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgLock + */ +#define XDDR_XMPU2_CFG_LOCK ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000020UL ) +#define XDDR_XMPU2_CFG_LOCK_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_LOCK_REGWRDIS_SHIFT 0UL +#define XDDR_XMPU2_CFG_LOCK_REGWRDIS_WIDTH 1UL +#define XDDR_XMPU2_CFG_LOCK_REGWRDIS_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_LOCK_REGWRDIS_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR00Strt + */ +#define XDDR_XMPU2_CFG_R00_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000100UL ) +#define XDDR_XMPU2_CFG_R00_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R00_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R00_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R00_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R00_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR00End + */ +#define XDDR_XMPU2_CFG_R00_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000104UL ) +#define XDDR_XMPU2_CFG_R00_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R00_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R00_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R00_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R00_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR00Mstr + */ +#define XDDR_XMPU2_CFG_R00_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000108UL ) +#define XDDR_XMPU2_CFG_R00_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R00_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R00_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R00_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R00_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R00_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R00_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R00_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R00_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR00 + */ +#define XDDR_XMPU2_CFG_R00 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000010CUL ) +#define XDDR_XMPU2_CFG_R00_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R00_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R00_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R00_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R00_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R00_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R00_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R00_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R00_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R00_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R00_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R00_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R00_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R00_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R00_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R00_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R00_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R00_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R00_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R00_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R00_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR01Strt + */ +#define XDDR_XMPU2_CFG_R01_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000110UL ) +#define XDDR_XMPU2_CFG_R01_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R01_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R01_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R01_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R01_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR01End + */ +#define XDDR_XMPU2_CFG_R01_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000114UL ) +#define XDDR_XMPU2_CFG_R01_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R01_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R01_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R01_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R01_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR01Mstr + */ +#define XDDR_XMPU2_CFG_R01_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000118UL ) +#define XDDR_XMPU2_CFG_R01_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R01_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R01_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R01_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R01_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R01_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R01_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R01_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R01_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR01 + */ +#define XDDR_XMPU2_CFG_R01 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000011CUL ) +#define XDDR_XMPU2_CFG_R01_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R01_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R01_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R01_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R01_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R01_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R01_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R01_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R01_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R01_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R01_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R01_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R01_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R01_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R01_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R01_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R01_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R01_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R01_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R01_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R01_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR02Strt + */ +#define XDDR_XMPU2_CFG_R02_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000120UL ) +#define XDDR_XMPU2_CFG_R02_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R02_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R02_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R02_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R02_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR02End + */ +#define XDDR_XMPU2_CFG_R02_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000124UL ) +#define XDDR_XMPU2_CFG_R02_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R02_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R02_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R02_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R02_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR02Mstr + */ +#define XDDR_XMPU2_CFG_R02_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000128UL ) +#define XDDR_XMPU2_CFG_R02_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R02_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R02_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R02_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R02_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R02_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R02_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R02_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R02_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR02 + */ +#define XDDR_XMPU2_CFG_R02 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000012CUL ) +#define XDDR_XMPU2_CFG_R02_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R02_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R02_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R02_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R02_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R02_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R02_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R02_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R02_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R02_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R02_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R02_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R02_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R02_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R02_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R02_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R02_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R02_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R02_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R02_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R02_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR03Strt + */ +#define XDDR_XMPU2_CFG_R03_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000130UL ) +#define XDDR_XMPU2_CFG_R03_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R03_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R03_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R03_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R03_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR03End + */ +#define XDDR_XMPU2_CFG_R03_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000134UL ) +#define XDDR_XMPU2_CFG_R03_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R03_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R03_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R03_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R03_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR03Mstr + */ +#define XDDR_XMPU2_CFG_R03_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000138UL ) +#define XDDR_XMPU2_CFG_R03_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R03_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R03_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R03_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R03_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R03_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R03_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R03_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R03_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR03 + */ +#define XDDR_XMPU2_CFG_R03 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000013CUL ) +#define XDDR_XMPU2_CFG_R03_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R03_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R03_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R03_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R03_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R03_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R03_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R03_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R03_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R03_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R03_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R03_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R03_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R03_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R03_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R03_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R03_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R03_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R03_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R03_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R03_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR04Strt + */ +#define XDDR_XMPU2_CFG_R04_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000140UL ) +#define XDDR_XMPU2_CFG_R04_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R04_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R04_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R04_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R04_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR04End + */ +#define XDDR_XMPU2_CFG_R04_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000144UL ) +#define XDDR_XMPU2_CFG_R04_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R04_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R04_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R04_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R04_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR04Mstr + */ +#define XDDR_XMPU2_CFG_R04_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000148UL ) +#define XDDR_XMPU2_CFG_R04_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R04_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R04_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R04_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R04_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R04_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R04_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R04_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R04_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR04 + */ +#define XDDR_XMPU2_CFG_R04 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000014CUL ) +#define XDDR_XMPU2_CFG_R04_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R04_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R04_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R04_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R04_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R04_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R04_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R04_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R04_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R04_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R04_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R04_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R04_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R04_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R04_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R04_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R04_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R04_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R04_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R04_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R04_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR05Strt + */ +#define XDDR_XMPU2_CFG_R05_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000150UL ) +#define XDDR_XMPU2_CFG_R05_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R05_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R05_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R05_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R05_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR05End + */ +#define XDDR_XMPU2_CFG_R05_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000154UL ) +#define XDDR_XMPU2_CFG_R05_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R05_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R05_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R05_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R05_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR05Mstr + */ +#define XDDR_XMPU2_CFG_R05_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000158UL ) +#define XDDR_XMPU2_CFG_R05_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R05_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R05_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R05_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R05_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R05_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R05_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R05_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R05_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR05 + */ +#define XDDR_XMPU2_CFG_R05 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000015CUL ) +#define XDDR_XMPU2_CFG_R05_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R05_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R05_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R05_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R05_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R05_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R05_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R05_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R05_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R05_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R05_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R05_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R05_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R05_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R05_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R05_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R05_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R05_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R05_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R05_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R05_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR06Strt + */ +#define XDDR_XMPU2_CFG_R06_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000160UL ) +#define XDDR_XMPU2_CFG_R06_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R06_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R06_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R06_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R06_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR06End + */ +#define XDDR_XMPU2_CFG_R06_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000164UL ) +#define XDDR_XMPU2_CFG_R06_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R06_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R06_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R06_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R06_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR06Mstr + */ +#define XDDR_XMPU2_CFG_R06_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000168UL ) +#define XDDR_XMPU2_CFG_R06_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R06_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R06_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R06_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R06_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R06_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R06_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R06_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R06_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR06 + */ +#define XDDR_XMPU2_CFG_R06 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000016CUL ) +#define XDDR_XMPU2_CFG_R06_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R06_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R06_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R06_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R06_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R06_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R06_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R06_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R06_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R06_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R06_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R06_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R06_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R06_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R06_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R06_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R06_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R06_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R06_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R06_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R06_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR07Strt + */ +#define XDDR_XMPU2_CFG_R07_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000170UL ) +#define XDDR_XMPU2_CFG_R07_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R07_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R07_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R07_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R07_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR07End + */ +#define XDDR_XMPU2_CFG_R07_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000174UL ) +#define XDDR_XMPU2_CFG_R07_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R07_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R07_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R07_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R07_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR07Mstr + */ +#define XDDR_XMPU2_CFG_R07_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000178UL ) +#define XDDR_XMPU2_CFG_R07_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R07_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R07_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R07_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R07_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R07_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R07_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R07_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R07_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR07 + */ +#define XDDR_XMPU2_CFG_R07 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000017CUL ) +#define XDDR_XMPU2_CFG_R07_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R07_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R07_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R07_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R07_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R07_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R07_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R07_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R07_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R07_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R07_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R07_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R07_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R07_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R07_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R07_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R07_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R07_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R07_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R07_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R07_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR08Strt + */ +#define XDDR_XMPU2_CFG_R08_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000180UL ) +#define XDDR_XMPU2_CFG_R08_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R08_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R08_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R08_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R08_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR08End + */ +#define XDDR_XMPU2_CFG_R08_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000184UL ) +#define XDDR_XMPU2_CFG_R08_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R08_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R08_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R08_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R08_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR08Mstr + */ +#define XDDR_XMPU2_CFG_R08_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000188UL ) +#define XDDR_XMPU2_CFG_R08_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R08_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R08_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R08_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R08_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R08_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R08_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R08_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R08_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR08 + */ +#define XDDR_XMPU2_CFG_R08 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000018CUL ) +#define XDDR_XMPU2_CFG_R08_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R08_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R08_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R08_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R08_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R08_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R08_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R08_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R08_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R08_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R08_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R08_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R08_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R08_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R08_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R08_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R08_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R08_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R08_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R08_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R08_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR09Strt + */ +#define XDDR_XMPU2_CFG_R09_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000190UL ) +#define XDDR_XMPU2_CFG_R09_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R09_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R09_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R09_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R09_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR09End + */ +#define XDDR_XMPU2_CFG_R09_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000194UL ) +#define XDDR_XMPU2_CFG_R09_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R09_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R09_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R09_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R09_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR09Mstr + */ +#define XDDR_XMPU2_CFG_R09_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000198UL ) +#define XDDR_XMPU2_CFG_R09_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R09_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R09_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R09_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R09_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R09_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R09_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R09_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R09_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR09 + */ +#define XDDR_XMPU2_CFG_R09 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000019CUL ) +#define XDDR_XMPU2_CFG_R09_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R09_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R09_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R09_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R09_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R09_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R09_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R09_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R09_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R09_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R09_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R09_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R09_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R09_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R09_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R09_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R09_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R09_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R09_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R09_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R09_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR10Strt + */ +#define XDDR_XMPU2_CFG_R10_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001A0UL ) +#define XDDR_XMPU2_CFG_R10_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R10_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R10_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R10_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R10_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR10End + */ +#define XDDR_XMPU2_CFG_R10_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001A4UL ) +#define XDDR_XMPU2_CFG_R10_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R10_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R10_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R10_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R10_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR10Mstr + */ +#define XDDR_XMPU2_CFG_R10_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001A8UL ) +#define XDDR_XMPU2_CFG_R10_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R10_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R10_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R10_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R10_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R10_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R10_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R10_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R10_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR10 + */ +#define XDDR_XMPU2_CFG_R10 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001ACUL ) +#define XDDR_XMPU2_CFG_R10_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R10_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R10_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R10_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R10_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R10_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R10_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R10_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R10_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R10_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R10_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R10_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R10_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R10_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R10_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R10_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R10_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R10_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R10_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R10_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R10_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR11Strt + */ +#define XDDR_XMPU2_CFG_R11_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001B0UL ) +#define XDDR_XMPU2_CFG_R11_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R11_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R11_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R11_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R11_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR11End + */ +#define XDDR_XMPU2_CFG_R11_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001B4UL ) +#define XDDR_XMPU2_CFG_R11_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R11_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R11_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R11_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R11_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR11Mstr + */ +#define XDDR_XMPU2_CFG_R11_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001B8UL ) +#define XDDR_XMPU2_CFG_R11_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R11_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R11_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R11_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R11_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R11_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R11_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R11_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R11_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR11 + */ +#define XDDR_XMPU2_CFG_R11 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001BCUL ) +#define XDDR_XMPU2_CFG_R11_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R11_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R11_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R11_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R11_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R11_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R11_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R11_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R11_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R11_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R11_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R11_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R11_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R11_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R11_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R11_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R11_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R11_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R11_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R11_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R11_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR12Strt + */ +#define XDDR_XMPU2_CFG_R12_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001C0UL ) +#define XDDR_XMPU2_CFG_R12_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R12_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R12_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R12_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R12_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR12End + */ +#define XDDR_XMPU2_CFG_R12_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001C4UL ) +#define XDDR_XMPU2_CFG_R12_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R12_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R12_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R12_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R12_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR12Mstr + */ +#define XDDR_XMPU2_CFG_R12_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001C8UL ) +#define XDDR_XMPU2_CFG_R12_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R12_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R12_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R12_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R12_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R12_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R12_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R12_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R12_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR12 + */ +#define XDDR_XMPU2_CFG_R12 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001CCUL ) +#define XDDR_XMPU2_CFG_R12_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R12_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R12_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R12_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R12_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R12_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R12_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R12_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R12_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R12_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R12_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R12_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R12_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R12_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R12_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R12_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R12_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R12_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R12_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R12_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R12_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR13Strt + */ +#define XDDR_XMPU2_CFG_R13_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001D0UL ) +#define XDDR_XMPU2_CFG_R13_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R13_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R13_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R13_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R13_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR13End + */ +#define XDDR_XMPU2_CFG_R13_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001D4UL ) +#define XDDR_XMPU2_CFG_R13_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R13_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R13_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R13_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R13_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR13Mstr + */ +#define XDDR_XMPU2_CFG_R13_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001D8UL ) +#define XDDR_XMPU2_CFG_R13_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R13_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R13_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R13_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R13_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R13_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R13_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R13_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R13_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR13 + */ +#define XDDR_XMPU2_CFG_R13 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001DCUL ) +#define XDDR_XMPU2_CFG_R13_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R13_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R13_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R13_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R13_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R13_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R13_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R13_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R13_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R13_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R13_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R13_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R13_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R13_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R13_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R13_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R13_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R13_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R13_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R13_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R13_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR14Strt + */ +#define XDDR_XMPU2_CFG_R14_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001E0UL ) +#define XDDR_XMPU2_CFG_R14_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R14_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R14_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R14_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R14_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR14End + */ +#define XDDR_XMPU2_CFG_R14_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001E4UL ) +#define XDDR_XMPU2_CFG_R14_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R14_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R14_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R14_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R14_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR14Mstr + */ +#define XDDR_XMPU2_CFG_R14_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001E8UL ) +#define XDDR_XMPU2_CFG_R14_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R14_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R14_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R14_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R14_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R14_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R14_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R14_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R14_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR14 + */ +#define XDDR_XMPU2_CFG_R14 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001ECUL ) +#define XDDR_XMPU2_CFG_R14_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R14_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R14_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R14_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R14_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R14_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R14_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R14_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R14_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R14_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R14_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R14_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R14_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R14_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R14_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R14_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R14_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R14_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R14_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R14_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R14_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR15Strt + */ +#define XDDR_XMPU2_CFG_R15_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001F0UL ) +#define XDDR_XMPU2_CFG_R15_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R15_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R15_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R15_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R15_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR15End + */ +#define XDDR_XMPU2_CFG_R15_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001F4UL ) +#define XDDR_XMPU2_CFG_R15_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R15_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R15_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R15_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R15_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR15Mstr + */ +#define XDDR_XMPU2_CFG_R15_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001F8UL ) +#define XDDR_XMPU2_CFG_R15_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R15_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R15_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R15_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R15_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R15_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R15_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R15_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R15_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR15 + */ +#define XDDR_XMPU2_CFG_R15 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001FCUL ) +#define XDDR_XMPU2_CFG_R15_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R15_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R15_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R15_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R15_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R15_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R15_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R15_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R15_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R15_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R15_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R15_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R15_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R15_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R15_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R15_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R15_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R15_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R15_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R15_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R15_EN_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XDDR_XMPU2_CFG_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu3_cfg.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu3_cfg.h new file mode 100644 index 0000000..4163149 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu3_cfg.h
@@ -0,0 +1,1304 @@ +/* ### HEADER ### */ + +#ifndef __XDDR_XMPU3_CFG_H__ +#define __XDDR_XMPU3_CFG_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XddrXmpu3Cfg Base Address + */ +#define XDDR_XMPU3_CFG_BASEADDR 0xFD030000UL + +/** + * Register: XddrXmpu3CfgCtrl + */ +#define XDDR_XMPU3_CFG_CTRL ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000000UL ) +#define XDDR_XMPU3_CFG_CTRL_RSTVAL 0x00000003UL + +#define XDDR_XMPU3_CFG_CTRL_ALIGNCFG_SHIFT 3UL +#define XDDR_XMPU3_CFG_CTRL_ALIGNCFG_WIDTH 1UL +#define XDDR_XMPU3_CFG_CTRL_ALIGNCFG_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_CTRL_ALIGNCFG_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_CTRL_POISONCFG_SHIFT 2UL +#define XDDR_XMPU3_CFG_CTRL_POISONCFG_WIDTH 1UL +#define XDDR_XMPU3_CFG_CTRL_POISONCFG_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_CTRL_POISONCFG_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_CTRL_DEFWRALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_CTRL_DEFWRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_CTRL_DEFWRALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_CTRL_DEFWRALWD_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_CTRL_DEFRDALWD_SHIFT 0UL +#define XDDR_XMPU3_CFG_CTRL_DEFRDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_CTRL_DEFRDALWD_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_CTRL_DEFRDALWD_DEFVAL 0x1UL + +/** + * Register: XddrXmpu3CfgErrSts1 + */ +#define XDDR_XMPU3_CFG_ERR_STS1 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000004UL ) +#define XDDR_XMPU3_CFG_ERR_STS1_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_ERR_STS1_AXI_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_ERR_STS1_AXI_ADDR_WIDTH 32UL +#define XDDR_XMPU3_CFG_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL +#define XDDR_XMPU3_CFG_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgErrSts2 + */ +#define XDDR_XMPU3_CFG_ERR_STS2 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000008UL ) +#define XDDR_XMPU3_CFG_ERR_STS2_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_ERR_STS2_AXI_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_ERR_STS2_AXI_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_ERR_STS2_AXI_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_ERR_STS2_AXI_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgPoison + */ +#define XDDR_XMPU3_CFG_POISON ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000000CUL ) +#define XDDR_XMPU3_CFG_POISON_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_POISON_ATTRIB_SHIFT 20UL +#define XDDR_XMPU3_CFG_POISON_ATTRIB_WIDTH 12UL +#define XDDR_XMPU3_CFG_POISON_ATTRIB_MASK 0xfff00000UL +#define XDDR_XMPU3_CFG_POISON_ATTRIB_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_POISON_BASE_SHIFT 0UL +#define XDDR_XMPU3_CFG_POISON_BASE_WIDTH 20UL +#define XDDR_XMPU3_CFG_POISON_BASE_MASK 0x000fffffUL +#define XDDR_XMPU3_CFG_POISON_BASE_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgIsr + */ +#define XDDR_XMPU3_CFG_ISR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000010UL ) +#define XDDR_XMPU3_CFG_ISR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_ISR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU3_CFG_ISR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_ISR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_ISR_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_ISR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU3_CFG_ISR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_ISR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_ISR_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_ISR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU3_CFG_ISR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_ISR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_ISR_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_ISR_INV_APB_SHIFT 0UL +#define XDDR_XMPU3_CFG_ISR_INV_APB_WIDTH 1UL +#define XDDR_XMPU3_CFG_ISR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_ISR_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgImr + */ +#define XDDR_XMPU3_CFG_IMR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000014UL ) +#define XDDR_XMPU3_CFG_IMR_RSTVAL 0x0000000fUL + +#define XDDR_XMPU3_CFG_IMR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU3_CFG_IMR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_IMR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_IMR_SECURTYVIO_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_IMR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU3_CFG_IMR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_IMR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_IMR_WRPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_IMR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU3_CFG_IMR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_IMR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_IMR_RDPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_IMR_INV_APB_SHIFT 0UL +#define XDDR_XMPU3_CFG_IMR_INV_APB_WIDTH 1UL +#define XDDR_XMPU3_CFG_IMR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_IMR_INV_APB_DEFVAL 0x1UL + +/** + * Register: XddrXmpu3CfgIen + */ +#define XDDR_XMPU3_CFG_IEN ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000018UL ) +#define XDDR_XMPU3_CFG_IEN_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_IEN_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU3_CFG_IEN_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_IEN_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_IEN_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_IEN_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU3_CFG_IEN_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_IEN_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_IEN_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_IEN_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU3_CFG_IEN_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_IEN_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_IEN_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_IEN_INV_APB_SHIFT 0UL +#define XDDR_XMPU3_CFG_IEN_INV_APB_WIDTH 1UL +#define XDDR_XMPU3_CFG_IEN_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_IEN_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgIds + */ +#define XDDR_XMPU3_CFG_IDS ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000001CUL ) +#define XDDR_XMPU3_CFG_IDS_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_IDS_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU3_CFG_IDS_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_IDS_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_IDS_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_IDS_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU3_CFG_IDS_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_IDS_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_IDS_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_IDS_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU3_CFG_IDS_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_IDS_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_IDS_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_IDS_INV_APB_SHIFT 0UL +#define XDDR_XMPU3_CFG_IDS_INV_APB_WIDTH 1UL +#define XDDR_XMPU3_CFG_IDS_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_IDS_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgLock + */ +#define XDDR_XMPU3_CFG_LOCK ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000020UL ) +#define XDDR_XMPU3_CFG_LOCK_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_LOCK_REGWRDIS_SHIFT 0UL +#define XDDR_XMPU3_CFG_LOCK_REGWRDIS_WIDTH 1UL +#define XDDR_XMPU3_CFG_LOCK_REGWRDIS_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_LOCK_REGWRDIS_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR00Strt + */ +#define XDDR_XMPU3_CFG_R00_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000100UL ) +#define XDDR_XMPU3_CFG_R00_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R00_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R00_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R00_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R00_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR00End + */ +#define XDDR_XMPU3_CFG_R00_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000104UL ) +#define XDDR_XMPU3_CFG_R00_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R00_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R00_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R00_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R00_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR00Mstr + */ +#define XDDR_XMPU3_CFG_R00_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000108UL ) +#define XDDR_XMPU3_CFG_R00_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R00_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R00_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R00_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R00_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R00_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R00_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R00_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R00_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR00 + */ +#define XDDR_XMPU3_CFG_R00 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000010CUL ) +#define XDDR_XMPU3_CFG_R00_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R00_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R00_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R00_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R00_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R00_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R00_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R00_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R00_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R00_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R00_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R00_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R00_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R00_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R00_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R00_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R00_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R00_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R00_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R00_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R00_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR01Strt + */ +#define XDDR_XMPU3_CFG_R01_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000110UL ) +#define XDDR_XMPU3_CFG_R01_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R01_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R01_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R01_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R01_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR01End + */ +#define XDDR_XMPU3_CFG_R01_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000114UL ) +#define XDDR_XMPU3_CFG_R01_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R01_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R01_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R01_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R01_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR01Mstr + */ +#define XDDR_XMPU3_CFG_R01_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000118UL ) +#define XDDR_XMPU3_CFG_R01_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R01_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R01_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R01_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R01_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R01_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R01_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R01_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R01_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR01 + */ +#define XDDR_XMPU3_CFG_R01 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000011CUL ) +#define XDDR_XMPU3_CFG_R01_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R01_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R01_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R01_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R01_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R01_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R01_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R01_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R01_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R01_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R01_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R01_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R01_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R01_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R01_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R01_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R01_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R01_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R01_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R01_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R01_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR02Strt + */ +#define XDDR_XMPU3_CFG_R02_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000120UL ) +#define XDDR_XMPU3_CFG_R02_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R02_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R02_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R02_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R02_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR02End + */ +#define XDDR_XMPU3_CFG_R02_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000124UL ) +#define XDDR_XMPU3_CFG_R02_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R02_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R02_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R02_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R02_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR02Mstr + */ +#define XDDR_XMPU3_CFG_R02_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000128UL ) +#define XDDR_XMPU3_CFG_R02_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R02_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R02_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R02_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R02_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R02_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R02_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R02_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R02_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR02 + */ +#define XDDR_XMPU3_CFG_R02 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000012CUL ) +#define XDDR_XMPU3_CFG_R02_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R02_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R02_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R02_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R02_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R02_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R02_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R02_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R02_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R02_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R02_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R02_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R02_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R02_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R02_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R02_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R02_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R02_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R02_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R02_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R02_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR03Strt + */ +#define XDDR_XMPU3_CFG_R03_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000130UL ) +#define XDDR_XMPU3_CFG_R03_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R03_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R03_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R03_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R03_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR03End + */ +#define XDDR_XMPU3_CFG_R03_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000134UL ) +#define XDDR_XMPU3_CFG_R03_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R03_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R03_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R03_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R03_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR03Mstr + */ +#define XDDR_XMPU3_CFG_R03_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000138UL ) +#define XDDR_XMPU3_CFG_R03_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R03_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R03_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R03_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R03_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R03_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R03_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R03_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R03_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR03 + */ +#define XDDR_XMPU3_CFG_R03 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000013CUL ) +#define XDDR_XMPU3_CFG_R03_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R03_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R03_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R03_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R03_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R03_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R03_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R03_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R03_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R03_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R03_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R03_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R03_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R03_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R03_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R03_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R03_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R03_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R03_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R03_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R03_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR04Strt + */ +#define XDDR_XMPU3_CFG_R04_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000140UL ) +#define XDDR_XMPU3_CFG_R04_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R04_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R04_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R04_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R04_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR04End + */ +#define XDDR_XMPU3_CFG_R04_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000144UL ) +#define XDDR_XMPU3_CFG_R04_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R04_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R04_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R04_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R04_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR04Mstr + */ +#define XDDR_XMPU3_CFG_R04_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000148UL ) +#define XDDR_XMPU3_CFG_R04_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R04_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R04_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R04_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R04_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R04_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R04_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R04_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R04_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR04 + */ +#define XDDR_XMPU3_CFG_R04 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000014CUL ) +#define XDDR_XMPU3_CFG_R04_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R04_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R04_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R04_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R04_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R04_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R04_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R04_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R04_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R04_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R04_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R04_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R04_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R04_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R04_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R04_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R04_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R04_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R04_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R04_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R04_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR05Strt + */ +#define XDDR_XMPU3_CFG_R05_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000150UL ) +#define XDDR_XMPU3_CFG_R05_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R05_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R05_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R05_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R05_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR05End + */ +#define XDDR_XMPU3_CFG_R05_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000154UL ) +#define XDDR_XMPU3_CFG_R05_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R05_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R05_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R05_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R05_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR05Mstr + */ +#define XDDR_XMPU3_CFG_R05_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000158UL ) +#define XDDR_XMPU3_CFG_R05_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R05_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R05_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R05_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R05_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R05_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R05_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R05_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R05_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR05 + */ +#define XDDR_XMPU3_CFG_R05 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000015CUL ) +#define XDDR_XMPU3_CFG_R05_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R05_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R05_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R05_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R05_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R05_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R05_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R05_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R05_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R05_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R05_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R05_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R05_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R05_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R05_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R05_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R05_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R05_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R05_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R05_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R05_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR06Strt + */ +#define XDDR_XMPU3_CFG_R06_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000160UL ) +#define XDDR_XMPU3_CFG_R06_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R06_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R06_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R06_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R06_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR06End + */ +#define XDDR_XMPU3_CFG_R06_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000164UL ) +#define XDDR_XMPU3_CFG_R06_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R06_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R06_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R06_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R06_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR06Mstr + */ +#define XDDR_XMPU3_CFG_R06_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000168UL ) +#define XDDR_XMPU3_CFG_R06_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R06_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R06_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R06_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R06_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R06_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R06_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R06_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R06_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR06 + */ +#define XDDR_XMPU3_CFG_R06 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000016CUL ) +#define XDDR_XMPU3_CFG_R06_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R06_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R06_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R06_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R06_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R06_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R06_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R06_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R06_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R06_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R06_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R06_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R06_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R06_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R06_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R06_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R06_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R06_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R06_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R06_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R06_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR07Strt + */ +#define XDDR_XMPU3_CFG_R07_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000170UL ) +#define XDDR_XMPU3_CFG_R07_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R07_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R07_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R07_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R07_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR07End + */ +#define XDDR_XMPU3_CFG_R07_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000174UL ) +#define XDDR_XMPU3_CFG_R07_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R07_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R07_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R07_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R07_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR07Mstr + */ +#define XDDR_XMPU3_CFG_R07_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000178UL ) +#define XDDR_XMPU3_CFG_R07_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R07_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R07_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R07_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R07_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R07_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R07_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R07_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R07_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR07 + */ +#define XDDR_XMPU3_CFG_R07 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000017CUL ) +#define XDDR_XMPU3_CFG_R07_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R07_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R07_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R07_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R07_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R07_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R07_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R07_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R07_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R07_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R07_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R07_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R07_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R07_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R07_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R07_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R07_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R07_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R07_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R07_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R07_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR08Strt + */ +#define XDDR_XMPU3_CFG_R08_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000180UL ) +#define XDDR_XMPU3_CFG_R08_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R08_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R08_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R08_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R08_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR08End + */ +#define XDDR_XMPU3_CFG_R08_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000184UL ) +#define XDDR_XMPU3_CFG_R08_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R08_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R08_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R08_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R08_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR08Mstr + */ +#define XDDR_XMPU3_CFG_R08_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000188UL ) +#define XDDR_XMPU3_CFG_R08_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R08_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R08_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R08_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R08_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R08_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R08_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R08_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R08_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR08 + */ +#define XDDR_XMPU3_CFG_R08 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000018CUL ) +#define XDDR_XMPU3_CFG_R08_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R08_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R08_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R08_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R08_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R08_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R08_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R08_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R08_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R08_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R08_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R08_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R08_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R08_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R08_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R08_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R08_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R08_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R08_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R08_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R08_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR09Strt + */ +#define XDDR_XMPU3_CFG_R09_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000190UL ) +#define XDDR_XMPU3_CFG_R09_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R09_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R09_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R09_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R09_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR09End + */ +#define XDDR_XMPU3_CFG_R09_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000194UL ) +#define XDDR_XMPU3_CFG_R09_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R09_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R09_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R09_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R09_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR09Mstr + */ +#define XDDR_XMPU3_CFG_R09_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000198UL ) +#define XDDR_XMPU3_CFG_R09_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R09_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R09_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R09_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R09_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R09_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R09_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R09_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R09_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR09 + */ +#define XDDR_XMPU3_CFG_R09 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000019CUL ) +#define XDDR_XMPU3_CFG_R09_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R09_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R09_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R09_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R09_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R09_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R09_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R09_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R09_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R09_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R09_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R09_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R09_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R09_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R09_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R09_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R09_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R09_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R09_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R09_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R09_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR10Strt + */ +#define XDDR_XMPU3_CFG_R10_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001A0UL ) +#define XDDR_XMPU3_CFG_R10_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R10_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R10_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R10_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R10_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR10End + */ +#define XDDR_XMPU3_CFG_R10_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001A4UL ) +#define XDDR_XMPU3_CFG_R10_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R10_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R10_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R10_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R10_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR10Mstr + */ +#define XDDR_XMPU3_CFG_R10_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001A8UL ) +#define XDDR_XMPU3_CFG_R10_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R10_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R10_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R10_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R10_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R10_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R10_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R10_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R10_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR10 + */ +#define XDDR_XMPU3_CFG_R10 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001ACUL ) +#define XDDR_XMPU3_CFG_R10_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R10_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R10_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R10_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R10_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R10_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R10_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R10_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R10_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R10_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R10_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R10_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R10_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R10_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R10_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R10_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R10_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R10_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R10_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R10_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R10_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR11Strt + */ +#define XDDR_XMPU3_CFG_R11_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001B0UL ) +#define XDDR_XMPU3_CFG_R11_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R11_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R11_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R11_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R11_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR11End + */ +#define XDDR_XMPU3_CFG_R11_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001B4UL ) +#define XDDR_XMPU3_CFG_R11_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R11_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R11_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R11_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R11_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR11Mstr + */ +#define XDDR_XMPU3_CFG_R11_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001B8UL ) +#define XDDR_XMPU3_CFG_R11_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R11_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R11_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R11_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R11_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R11_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R11_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R11_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R11_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR11 + */ +#define XDDR_XMPU3_CFG_R11 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001BCUL ) +#define XDDR_XMPU3_CFG_R11_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R11_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R11_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R11_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R11_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R11_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R11_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R11_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R11_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R11_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R11_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R11_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R11_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R11_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R11_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R11_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R11_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R11_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R11_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R11_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R11_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR12Strt + */ +#define XDDR_XMPU3_CFG_R12_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001C0UL ) +#define XDDR_XMPU3_CFG_R12_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R12_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R12_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R12_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R12_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR12End + */ +#define XDDR_XMPU3_CFG_R12_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001C4UL ) +#define XDDR_XMPU3_CFG_R12_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R12_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R12_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R12_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R12_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR12Mstr + */ +#define XDDR_XMPU3_CFG_R12_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001C8UL ) +#define XDDR_XMPU3_CFG_R12_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R12_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R12_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R12_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R12_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R12_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R12_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R12_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R12_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR12 + */ +#define XDDR_XMPU3_CFG_R12 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001CCUL ) +#define XDDR_XMPU3_CFG_R12_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R12_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R12_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R12_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R12_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R12_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R12_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R12_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R12_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R12_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R12_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R12_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R12_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R12_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R12_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R12_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R12_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R12_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R12_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R12_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R12_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR13Strt + */ +#define XDDR_XMPU3_CFG_R13_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001D0UL ) +#define XDDR_XMPU3_CFG_R13_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R13_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R13_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R13_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R13_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR13End + */ +#define XDDR_XMPU3_CFG_R13_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001D4UL ) +#define XDDR_XMPU3_CFG_R13_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R13_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R13_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R13_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R13_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR13Mstr + */ +#define XDDR_XMPU3_CFG_R13_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001D8UL ) +#define XDDR_XMPU3_CFG_R13_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R13_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R13_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R13_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R13_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R13_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R13_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R13_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R13_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR13 + */ +#define XDDR_XMPU3_CFG_R13 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001DCUL ) +#define XDDR_XMPU3_CFG_R13_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R13_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R13_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R13_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R13_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R13_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R13_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R13_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R13_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R13_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R13_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R13_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R13_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R13_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R13_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R13_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R13_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R13_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R13_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R13_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R13_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR14Strt + */ +#define XDDR_XMPU3_CFG_R14_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001E0UL ) +#define XDDR_XMPU3_CFG_R14_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R14_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R14_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R14_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R14_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR14End + */ +#define XDDR_XMPU3_CFG_R14_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001E4UL ) +#define XDDR_XMPU3_CFG_R14_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R14_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R14_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R14_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R14_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR14Mstr + */ +#define XDDR_XMPU3_CFG_R14_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001E8UL ) +#define XDDR_XMPU3_CFG_R14_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R14_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R14_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R14_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R14_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R14_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R14_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R14_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R14_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR14 + */ +#define XDDR_XMPU3_CFG_R14 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001ECUL ) +#define XDDR_XMPU3_CFG_R14_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R14_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R14_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R14_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R14_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R14_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R14_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R14_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R14_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R14_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R14_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R14_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R14_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R14_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R14_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R14_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R14_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R14_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R14_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R14_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R14_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR15Strt + */ +#define XDDR_XMPU3_CFG_R15_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001F0UL ) +#define XDDR_XMPU3_CFG_R15_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R15_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R15_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R15_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R15_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR15End + */ +#define XDDR_XMPU3_CFG_R15_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001F4UL ) +#define XDDR_XMPU3_CFG_R15_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R15_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R15_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R15_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R15_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR15Mstr + */ +#define XDDR_XMPU3_CFG_R15_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001F8UL ) +#define XDDR_XMPU3_CFG_R15_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R15_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R15_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R15_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R15_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R15_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R15_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R15_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R15_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR15 + */ +#define XDDR_XMPU3_CFG_R15 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001FCUL ) +#define XDDR_XMPU3_CFG_R15_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R15_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R15_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R15_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R15_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R15_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R15_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R15_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R15_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R15_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R15_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R15_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R15_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R15_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R15_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R15_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R15_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R15_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R15_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R15_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R15_EN_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XDDR_XMPU3_CFG_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu4_cfg.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu4_cfg.h new file mode 100644 index 0000000..2df8144 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu4_cfg.h
@@ -0,0 +1,1304 @@ +/* ### HEADER ### */ + +#ifndef __XDDR_XMPU4_CFG_H__ +#define __XDDR_XMPU4_CFG_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XddrXmpu4Cfg Base Address + */ +#define XDDR_XMPU4_CFG_BASEADDR 0xFD040000UL + +/** + * Register: XddrXmpu4CfgCtrl + */ +#define XDDR_XMPU4_CFG_CTRL ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000000UL ) +#define XDDR_XMPU4_CFG_CTRL_RSTVAL 0x00000003UL + +#define XDDR_XMPU4_CFG_CTRL_ALIGNCFG_SHIFT 3UL +#define XDDR_XMPU4_CFG_CTRL_ALIGNCFG_WIDTH 1UL +#define XDDR_XMPU4_CFG_CTRL_ALIGNCFG_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_CTRL_ALIGNCFG_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_CTRL_POISONCFG_SHIFT 2UL +#define XDDR_XMPU4_CFG_CTRL_POISONCFG_WIDTH 1UL +#define XDDR_XMPU4_CFG_CTRL_POISONCFG_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_CTRL_POISONCFG_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_CTRL_DEFWRALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_CTRL_DEFWRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_CTRL_DEFWRALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_CTRL_DEFWRALWD_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_CTRL_DEFRDALWD_SHIFT 0UL +#define XDDR_XMPU4_CFG_CTRL_DEFRDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_CTRL_DEFRDALWD_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_CTRL_DEFRDALWD_DEFVAL 0x1UL + +/** + * Register: XddrXmpu4CfgErrSts1 + */ +#define XDDR_XMPU4_CFG_ERR_STS1 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000004UL ) +#define XDDR_XMPU4_CFG_ERR_STS1_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_ERR_STS1_AXI_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_ERR_STS1_AXI_ADDR_WIDTH 32UL +#define XDDR_XMPU4_CFG_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL +#define XDDR_XMPU4_CFG_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgErrSts2 + */ +#define XDDR_XMPU4_CFG_ERR_STS2 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000008UL ) +#define XDDR_XMPU4_CFG_ERR_STS2_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_ERR_STS2_AXI_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_ERR_STS2_AXI_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_ERR_STS2_AXI_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_ERR_STS2_AXI_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgPoison + */ +#define XDDR_XMPU4_CFG_POISON ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000000CUL ) +#define XDDR_XMPU4_CFG_POISON_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_POISON_ATTRIB_SHIFT 20UL +#define XDDR_XMPU4_CFG_POISON_ATTRIB_WIDTH 12UL +#define XDDR_XMPU4_CFG_POISON_ATTRIB_MASK 0xfff00000UL +#define XDDR_XMPU4_CFG_POISON_ATTRIB_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_POISON_BASE_SHIFT 0UL +#define XDDR_XMPU4_CFG_POISON_BASE_WIDTH 20UL +#define XDDR_XMPU4_CFG_POISON_BASE_MASK 0x000fffffUL +#define XDDR_XMPU4_CFG_POISON_BASE_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgIsr + */ +#define XDDR_XMPU4_CFG_ISR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000010UL ) +#define XDDR_XMPU4_CFG_ISR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_ISR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU4_CFG_ISR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_ISR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_ISR_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_ISR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU4_CFG_ISR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_ISR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_ISR_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_ISR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU4_CFG_ISR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_ISR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_ISR_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_ISR_INV_APB_SHIFT 0UL +#define XDDR_XMPU4_CFG_ISR_INV_APB_WIDTH 1UL +#define XDDR_XMPU4_CFG_ISR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_ISR_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgImr + */ +#define XDDR_XMPU4_CFG_IMR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000014UL ) +#define XDDR_XMPU4_CFG_IMR_RSTVAL 0x0000000fUL + +#define XDDR_XMPU4_CFG_IMR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU4_CFG_IMR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_IMR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_IMR_SECURTYVIO_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_IMR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU4_CFG_IMR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_IMR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_IMR_WRPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_IMR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU4_CFG_IMR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_IMR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_IMR_RDPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_IMR_INV_APB_SHIFT 0UL +#define XDDR_XMPU4_CFG_IMR_INV_APB_WIDTH 1UL +#define XDDR_XMPU4_CFG_IMR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_IMR_INV_APB_DEFVAL 0x1UL + +/** + * Register: XddrXmpu4CfgIen + */ +#define XDDR_XMPU4_CFG_IEN ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000018UL ) +#define XDDR_XMPU4_CFG_IEN_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_IEN_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU4_CFG_IEN_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_IEN_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_IEN_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_IEN_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU4_CFG_IEN_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_IEN_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_IEN_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_IEN_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU4_CFG_IEN_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_IEN_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_IEN_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_IEN_INV_APB_SHIFT 0UL +#define XDDR_XMPU4_CFG_IEN_INV_APB_WIDTH 1UL +#define XDDR_XMPU4_CFG_IEN_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_IEN_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgIds + */ +#define XDDR_XMPU4_CFG_IDS ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000001CUL ) +#define XDDR_XMPU4_CFG_IDS_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_IDS_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU4_CFG_IDS_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_IDS_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_IDS_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_IDS_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU4_CFG_IDS_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_IDS_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_IDS_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_IDS_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU4_CFG_IDS_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_IDS_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_IDS_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_IDS_INV_APB_SHIFT 0UL +#define XDDR_XMPU4_CFG_IDS_INV_APB_WIDTH 1UL +#define XDDR_XMPU4_CFG_IDS_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_IDS_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgLock + */ +#define XDDR_XMPU4_CFG_LOCK ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000020UL ) +#define XDDR_XMPU4_CFG_LOCK_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_LOCK_REGWRDIS_SHIFT 0UL +#define XDDR_XMPU4_CFG_LOCK_REGWRDIS_WIDTH 1UL +#define XDDR_XMPU4_CFG_LOCK_REGWRDIS_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_LOCK_REGWRDIS_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR00Strt + */ +#define XDDR_XMPU4_CFG_R00_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000100UL ) +#define XDDR_XMPU4_CFG_R00_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R00_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R00_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R00_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R00_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR00End + */ +#define XDDR_XMPU4_CFG_R00_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000104UL ) +#define XDDR_XMPU4_CFG_R00_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R00_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R00_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R00_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R00_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR00Mstr + */ +#define XDDR_XMPU4_CFG_R00_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000108UL ) +#define XDDR_XMPU4_CFG_R00_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R00_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R00_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R00_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R00_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R00_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R00_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R00_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R00_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR00 + */ +#define XDDR_XMPU4_CFG_R00 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000010CUL ) +#define XDDR_XMPU4_CFG_R00_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R00_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R00_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R00_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R00_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R00_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R00_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R00_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R00_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R00_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R00_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R00_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R00_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R00_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R00_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R00_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R00_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R00_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R00_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R00_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R00_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR01Strt + */ +#define XDDR_XMPU4_CFG_R01_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000110UL ) +#define XDDR_XMPU4_CFG_R01_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R01_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R01_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R01_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R01_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR01End + */ +#define XDDR_XMPU4_CFG_R01_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000114UL ) +#define XDDR_XMPU4_CFG_R01_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R01_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R01_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R01_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R01_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR01Mstr + */ +#define XDDR_XMPU4_CFG_R01_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000118UL ) +#define XDDR_XMPU4_CFG_R01_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R01_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R01_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R01_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R01_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R01_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R01_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R01_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R01_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR01 + */ +#define XDDR_XMPU4_CFG_R01 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000011CUL ) +#define XDDR_XMPU4_CFG_R01_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R01_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R01_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R01_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R01_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R01_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R01_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R01_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R01_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R01_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R01_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R01_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R01_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R01_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R01_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R01_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R01_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R01_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R01_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R01_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R01_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR02Strt + */ +#define XDDR_XMPU4_CFG_R02_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000120UL ) +#define XDDR_XMPU4_CFG_R02_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R02_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R02_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R02_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R02_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR02End + */ +#define XDDR_XMPU4_CFG_R02_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000124UL ) +#define XDDR_XMPU4_CFG_R02_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R02_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R02_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R02_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R02_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR02Mstr + */ +#define XDDR_XMPU4_CFG_R02_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000128UL ) +#define XDDR_XMPU4_CFG_R02_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R02_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R02_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R02_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R02_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R02_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R02_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R02_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R02_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR02 + */ +#define XDDR_XMPU4_CFG_R02 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000012CUL ) +#define XDDR_XMPU4_CFG_R02_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R02_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R02_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R02_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R02_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R02_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R02_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R02_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R02_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R02_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R02_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R02_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R02_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R02_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R02_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R02_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R02_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R02_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R02_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R02_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R02_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR03Strt + */ +#define XDDR_XMPU4_CFG_R03_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000130UL ) +#define XDDR_XMPU4_CFG_R03_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R03_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R03_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R03_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R03_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR03End + */ +#define XDDR_XMPU4_CFG_R03_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000134UL ) +#define XDDR_XMPU4_CFG_R03_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R03_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R03_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R03_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R03_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR03Mstr + */ +#define XDDR_XMPU4_CFG_R03_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000138UL ) +#define XDDR_XMPU4_CFG_R03_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R03_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R03_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R03_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R03_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R03_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R03_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R03_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R03_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR03 + */ +#define XDDR_XMPU4_CFG_R03 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000013CUL ) +#define XDDR_XMPU4_CFG_R03_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R03_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R03_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R03_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R03_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R03_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R03_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R03_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R03_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R03_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R03_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R03_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R03_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R03_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R03_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R03_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R03_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R03_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R03_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R03_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R03_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR04Strt + */ +#define XDDR_XMPU4_CFG_R04_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000140UL ) +#define XDDR_XMPU4_CFG_R04_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R04_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R04_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R04_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R04_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR04End + */ +#define XDDR_XMPU4_CFG_R04_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000144UL ) +#define XDDR_XMPU4_CFG_R04_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R04_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R04_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R04_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R04_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR04Mstr + */ +#define XDDR_XMPU4_CFG_R04_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000148UL ) +#define XDDR_XMPU4_CFG_R04_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R04_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R04_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R04_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R04_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R04_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R04_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R04_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R04_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR04 + */ +#define XDDR_XMPU4_CFG_R04 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000014CUL ) +#define XDDR_XMPU4_CFG_R04_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R04_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R04_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R04_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R04_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R04_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R04_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R04_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R04_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R04_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R04_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R04_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R04_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R04_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R04_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R04_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R04_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R04_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R04_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R04_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R04_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR05Strt + */ +#define XDDR_XMPU4_CFG_R05_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000150UL ) +#define XDDR_XMPU4_CFG_R05_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R05_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R05_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R05_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R05_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR05End + */ +#define XDDR_XMPU4_CFG_R05_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000154UL ) +#define XDDR_XMPU4_CFG_R05_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R05_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R05_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R05_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R05_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR05Mstr + */ +#define XDDR_XMPU4_CFG_R05_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000158UL ) +#define XDDR_XMPU4_CFG_R05_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R05_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R05_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R05_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R05_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R05_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R05_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R05_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R05_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR05 + */ +#define XDDR_XMPU4_CFG_R05 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000015CUL ) +#define XDDR_XMPU4_CFG_R05_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R05_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R05_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R05_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R05_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R05_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R05_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R05_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R05_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R05_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R05_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R05_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R05_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R05_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R05_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R05_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R05_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R05_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R05_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R05_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R05_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR06Strt + */ +#define XDDR_XMPU4_CFG_R06_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000160UL ) +#define XDDR_XMPU4_CFG_R06_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R06_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R06_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R06_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R06_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR06End + */ +#define XDDR_XMPU4_CFG_R06_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000164UL ) +#define XDDR_XMPU4_CFG_R06_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R06_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R06_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R06_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R06_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR06Mstr + */ +#define XDDR_XMPU4_CFG_R06_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000168UL ) +#define XDDR_XMPU4_CFG_R06_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R06_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R06_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R06_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R06_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R06_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R06_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R06_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R06_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR06 + */ +#define XDDR_XMPU4_CFG_R06 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000016CUL ) +#define XDDR_XMPU4_CFG_R06_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R06_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R06_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R06_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R06_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R06_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R06_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R06_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R06_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R06_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R06_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R06_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R06_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R06_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R06_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R06_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R06_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R06_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R06_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R06_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R06_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR07Strt + */ +#define XDDR_XMPU4_CFG_R07_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000170UL ) +#define XDDR_XMPU4_CFG_R07_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R07_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R07_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R07_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R07_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR07End + */ +#define XDDR_XMPU4_CFG_R07_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000174UL ) +#define XDDR_XMPU4_CFG_R07_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R07_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R07_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R07_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R07_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR07Mstr + */ +#define XDDR_XMPU4_CFG_R07_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000178UL ) +#define XDDR_XMPU4_CFG_R07_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R07_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R07_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R07_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R07_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R07_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R07_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R07_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R07_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR07 + */ +#define XDDR_XMPU4_CFG_R07 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000017CUL ) +#define XDDR_XMPU4_CFG_R07_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R07_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R07_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R07_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R07_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R07_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R07_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R07_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R07_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R07_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R07_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R07_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R07_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R07_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R07_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R07_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R07_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R07_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R07_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R07_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R07_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR08Strt + */ +#define XDDR_XMPU4_CFG_R08_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000180UL ) +#define XDDR_XMPU4_CFG_R08_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R08_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R08_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R08_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R08_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR08End + */ +#define XDDR_XMPU4_CFG_R08_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000184UL ) +#define XDDR_XMPU4_CFG_R08_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R08_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R08_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R08_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R08_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR08Mstr + */ +#define XDDR_XMPU4_CFG_R08_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000188UL ) +#define XDDR_XMPU4_CFG_R08_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R08_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R08_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R08_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R08_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R08_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R08_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R08_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R08_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR08 + */ +#define XDDR_XMPU4_CFG_R08 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000018CUL ) +#define XDDR_XMPU4_CFG_R08_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R08_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R08_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R08_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R08_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R08_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R08_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R08_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R08_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R08_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R08_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R08_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R08_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R08_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R08_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R08_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R08_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R08_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R08_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R08_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R08_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR09Strt + */ +#define XDDR_XMPU4_CFG_R09_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000190UL ) +#define XDDR_XMPU4_CFG_R09_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R09_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R09_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R09_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R09_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR09End + */ +#define XDDR_XMPU4_CFG_R09_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000194UL ) +#define XDDR_XMPU4_CFG_R09_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R09_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R09_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R09_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R09_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR09Mstr + */ +#define XDDR_XMPU4_CFG_R09_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000198UL ) +#define XDDR_XMPU4_CFG_R09_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R09_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R09_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R09_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R09_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R09_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R09_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R09_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R09_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR09 + */ +#define XDDR_XMPU4_CFG_R09 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000019CUL ) +#define XDDR_XMPU4_CFG_R09_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R09_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R09_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R09_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R09_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R09_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R09_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R09_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R09_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R09_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R09_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R09_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R09_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R09_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R09_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R09_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R09_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R09_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R09_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R09_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R09_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR10Strt + */ +#define XDDR_XMPU4_CFG_R10_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001A0UL ) +#define XDDR_XMPU4_CFG_R10_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R10_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R10_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R10_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R10_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR10End + */ +#define XDDR_XMPU4_CFG_R10_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001A4UL ) +#define XDDR_XMPU4_CFG_R10_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R10_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R10_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R10_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R10_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR10Mstr + */ +#define XDDR_XMPU4_CFG_R10_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001A8UL ) +#define XDDR_XMPU4_CFG_R10_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R10_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R10_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R10_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R10_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R10_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R10_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R10_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R10_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR10 + */ +#define XDDR_XMPU4_CFG_R10 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001ACUL ) +#define XDDR_XMPU4_CFG_R10_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R10_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R10_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R10_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R10_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R10_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R10_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R10_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R10_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R10_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R10_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R10_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R10_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R10_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R10_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R10_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R10_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R10_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R10_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R10_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R10_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR11Strt + */ +#define XDDR_XMPU4_CFG_R11_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001B0UL ) +#define XDDR_XMPU4_CFG_R11_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R11_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R11_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R11_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R11_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR11End + */ +#define XDDR_XMPU4_CFG_R11_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001B4UL ) +#define XDDR_XMPU4_CFG_R11_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R11_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R11_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R11_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R11_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR11Mstr + */ +#define XDDR_XMPU4_CFG_R11_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001B8UL ) +#define XDDR_XMPU4_CFG_R11_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R11_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R11_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R11_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R11_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R11_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R11_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R11_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R11_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR11 + */ +#define XDDR_XMPU4_CFG_R11 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001BCUL ) +#define XDDR_XMPU4_CFG_R11_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R11_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R11_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R11_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R11_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R11_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R11_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R11_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R11_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R11_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R11_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R11_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R11_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R11_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R11_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R11_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R11_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R11_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R11_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R11_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R11_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR12Strt + */ +#define XDDR_XMPU4_CFG_R12_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001C0UL ) +#define XDDR_XMPU4_CFG_R12_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R12_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R12_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R12_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R12_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR12End + */ +#define XDDR_XMPU4_CFG_R12_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001C4UL ) +#define XDDR_XMPU4_CFG_R12_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R12_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R12_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R12_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R12_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR12Mstr + */ +#define XDDR_XMPU4_CFG_R12_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001C8UL ) +#define XDDR_XMPU4_CFG_R12_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R12_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R12_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R12_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R12_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R12_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R12_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R12_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R12_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR12 + */ +#define XDDR_XMPU4_CFG_R12 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001CCUL ) +#define XDDR_XMPU4_CFG_R12_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R12_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R12_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R12_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R12_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R12_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R12_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R12_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R12_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R12_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R12_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R12_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R12_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R12_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R12_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R12_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R12_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R12_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R12_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R12_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R12_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR13Strt + */ +#define XDDR_XMPU4_CFG_R13_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001D0UL ) +#define XDDR_XMPU4_CFG_R13_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R13_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R13_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R13_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R13_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR13End + */ +#define XDDR_XMPU4_CFG_R13_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001D4UL ) +#define XDDR_XMPU4_CFG_R13_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R13_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R13_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R13_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R13_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR13Mstr + */ +#define XDDR_XMPU4_CFG_R13_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001D8UL ) +#define XDDR_XMPU4_CFG_R13_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R13_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R13_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R13_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R13_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R13_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R13_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R13_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R13_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR13 + */ +#define XDDR_XMPU4_CFG_R13 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001DCUL ) +#define XDDR_XMPU4_CFG_R13_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R13_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R13_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R13_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R13_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R13_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R13_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R13_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R13_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R13_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R13_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R13_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R13_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R13_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R13_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R13_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R13_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R13_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R13_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R13_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R13_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR14Strt + */ +#define XDDR_XMPU4_CFG_R14_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001E0UL ) +#define XDDR_XMPU4_CFG_R14_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R14_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R14_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R14_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R14_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR14End + */ +#define XDDR_XMPU4_CFG_R14_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001E4UL ) +#define XDDR_XMPU4_CFG_R14_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R14_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R14_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R14_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R14_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR14Mstr + */ +#define XDDR_XMPU4_CFG_R14_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001E8UL ) +#define XDDR_XMPU4_CFG_R14_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R14_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R14_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R14_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R14_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R14_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R14_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R14_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R14_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR14 + */ +#define XDDR_XMPU4_CFG_R14 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001ECUL ) +#define XDDR_XMPU4_CFG_R14_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R14_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R14_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R14_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R14_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R14_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R14_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R14_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R14_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R14_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R14_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R14_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R14_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R14_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R14_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R14_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R14_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R14_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R14_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R14_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R14_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR15Strt + */ +#define XDDR_XMPU4_CFG_R15_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001F0UL ) +#define XDDR_XMPU4_CFG_R15_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R15_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R15_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R15_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R15_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR15End + */ +#define XDDR_XMPU4_CFG_R15_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001F4UL ) +#define XDDR_XMPU4_CFG_R15_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R15_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R15_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R15_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R15_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR15Mstr + */ +#define XDDR_XMPU4_CFG_R15_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001F8UL ) +#define XDDR_XMPU4_CFG_R15_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R15_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R15_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R15_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R15_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R15_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R15_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R15_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R15_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR15 + */ +#define XDDR_XMPU4_CFG_R15 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001FCUL ) +#define XDDR_XMPU4_CFG_R15_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R15_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R15_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R15_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R15_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R15_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R15_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R15_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R15_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R15_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R15_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R15_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R15_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R15_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R15_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R15_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R15_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R15_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R15_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R15_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R15_EN_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XDDR_XMPU4_CFG_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu5_cfg.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu5_cfg.h new file mode 100644 index 0000000..6081171 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu5_cfg.h
@@ -0,0 +1,1304 @@ +/* ### HEADER ### */ + +#ifndef __XDDR_XMPU5_CFG_H__ +#define __XDDR_XMPU5_CFG_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XddrXmpu5Cfg Base Address + */ +#define XDDR_XMPU5_CFG_BASEADDR 0xFD050000UL + +/** + * Register: XddrXmpu5CfgCtrl + */ +#define XDDR_XMPU5_CFG_CTRL ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000000UL ) +#define XDDR_XMPU5_CFG_CTRL_RSTVAL 0x00000003UL + +#define XDDR_XMPU5_CFG_CTRL_ALIGNCFG_SHIFT 3UL +#define XDDR_XMPU5_CFG_CTRL_ALIGNCFG_WIDTH 1UL +#define XDDR_XMPU5_CFG_CTRL_ALIGNCFG_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_CTRL_ALIGNCFG_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_CTRL_POISONCFG_SHIFT 2UL +#define XDDR_XMPU5_CFG_CTRL_POISONCFG_WIDTH 1UL +#define XDDR_XMPU5_CFG_CTRL_POISONCFG_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_CTRL_POISONCFG_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_CTRL_DEFWRALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_CTRL_DEFWRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_CTRL_DEFWRALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_CTRL_DEFWRALWD_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_CTRL_DEFRDALWD_SHIFT 0UL +#define XDDR_XMPU5_CFG_CTRL_DEFRDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_CTRL_DEFRDALWD_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_CTRL_DEFRDALWD_DEFVAL 0x1UL + +/** + * Register: XddrXmpu5CfgErrSts1 + */ +#define XDDR_XMPU5_CFG_ERR_STS1 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000004UL ) +#define XDDR_XMPU5_CFG_ERR_STS1_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_ERR_STS1_AXI_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_ERR_STS1_AXI_ADDR_WIDTH 32UL +#define XDDR_XMPU5_CFG_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL +#define XDDR_XMPU5_CFG_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgErrSts2 + */ +#define XDDR_XMPU5_CFG_ERR_STS2 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000008UL ) +#define XDDR_XMPU5_CFG_ERR_STS2_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_ERR_STS2_AXI_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_ERR_STS2_AXI_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_ERR_STS2_AXI_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_ERR_STS2_AXI_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgPoison + */ +#define XDDR_XMPU5_CFG_POISON ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000000CUL ) +#define XDDR_XMPU5_CFG_POISON_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_POISON_ATTRIB_SHIFT 20UL +#define XDDR_XMPU5_CFG_POISON_ATTRIB_WIDTH 12UL +#define XDDR_XMPU5_CFG_POISON_ATTRIB_MASK 0xfff00000UL +#define XDDR_XMPU5_CFG_POISON_ATTRIB_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_POISON_BASE_SHIFT 0UL +#define XDDR_XMPU5_CFG_POISON_BASE_WIDTH 20UL +#define XDDR_XMPU5_CFG_POISON_BASE_MASK 0x000fffffUL +#define XDDR_XMPU5_CFG_POISON_BASE_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgIsr + */ +#define XDDR_XMPU5_CFG_ISR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000010UL ) +#define XDDR_XMPU5_CFG_ISR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_ISR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU5_CFG_ISR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_ISR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_ISR_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_ISR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU5_CFG_ISR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_ISR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_ISR_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_ISR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU5_CFG_ISR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_ISR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_ISR_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_ISR_INV_APB_SHIFT 0UL +#define XDDR_XMPU5_CFG_ISR_INV_APB_WIDTH 1UL +#define XDDR_XMPU5_CFG_ISR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_ISR_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgImr + */ +#define XDDR_XMPU5_CFG_IMR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000014UL ) +#define XDDR_XMPU5_CFG_IMR_RSTVAL 0x0000000fUL + +#define XDDR_XMPU5_CFG_IMR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU5_CFG_IMR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_IMR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_IMR_SECURTYVIO_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_IMR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU5_CFG_IMR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_IMR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_IMR_WRPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_IMR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU5_CFG_IMR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_IMR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_IMR_RDPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_IMR_INV_APB_SHIFT 0UL +#define XDDR_XMPU5_CFG_IMR_INV_APB_WIDTH 1UL +#define XDDR_XMPU5_CFG_IMR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_IMR_INV_APB_DEFVAL 0x1UL + +/** + * Register: XddrXmpu5CfgIen + */ +#define XDDR_XMPU5_CFG_IEN ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000018UL ) +#define XDDR_XMPU5_CFG_IEN_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_IEN_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU5_CFG_IEN_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_IEN_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_IEN_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_IEN_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU5_CFG_IEN_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_IEN_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_IEN_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_IEN_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU5_CFG_IEN_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_IEN_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_IEN_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_IEN_INV_APB_SHIFT 0UL +#define XDDR_XMPU5_CFG_IEN_INV_APB_WIDTH 1UL +#define XDDR_XMPU5_CFG_IEN_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_IEN_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgIds + */ +#define XDDR_XMPU5_CFG_IDS ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000001CUL ) +#define XDDR_XMPU5_CFG_IDS_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_IDS_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU5_CFG_IDS_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_IDS_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_IDS_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_IDS_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU5_CFG_IDS_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_IDS_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_IDS_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_IDS_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU5_CFG_IDS_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_IDS_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_IDS_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_IDS_INV_APB_SHIFT 0UL +#define XDDR_XMPU5_CFG_IDS_INV_APB_WIDTH 1UL +#define XDDR_XMPU5_CFG_IDS_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_IDS_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgLock + */ +#define XDDR_XMPU5_CFG_LOCK ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000020UL ) +#define XDDR_XMPU5_CFG_LOCK_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_LOCK_REGWRDIS_SHIFT 0UL +#define XDDR_XMPU5_CFG_LOCK_REGWRDIS_WIDTH 1UL +#define XDDR_XMPU5_CFG_LOCK_REGWRDIS_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_LOCK_REGWRDIS_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR00Strt + */ +#define XDDR_XMPU5_CFG_R00_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000100UL ) +#define XDDR_XMPU5_CFG_R00_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R00_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R00_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R00_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R00_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR00End + */ +#define XDDR_XMPU5_CFG_R00_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000104UL ) +#define XDDR_XMPU5_CFG_R00_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R00_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R00_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R00_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R00_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR00Mstr + */ +#define XDDR_XMPU5_CFG_R00_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000108UL ) +#define XDDR_XMPU5_CFG_R00_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R00_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R00_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R00_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R00_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R00_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R00_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R00_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R00_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR00 + */ +#define XDDR_XMPU5_CFG_R00 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000010CUL ) +#define XDDR_XMPU5_CFG_R00_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R00_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R00_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R00_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R00_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R00_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R00_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R00_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R00_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R00_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R00_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R00_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R00_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R00_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R00_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R00_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R00_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R00_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R00_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R00_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R00_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR01Strt + */ +#define XDDR_XMPU5_CFG_R01_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000110UL ) +#define XDDR_XMPU5_CFG_R01_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R01_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R01_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R01_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R01_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR01End + */ +#define XDDR_XMPU5_CFG_R01_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000114UL ) +#define XDDR_XMPU5_CFG_R01_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R01_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R01_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R01_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R01_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR01Mstr + */ +#define XDDR_XMPU5_CFG_R01_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000118UL ) +#define XDDR_XMPU5_CFG_R01_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R01_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R01_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R01_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R01_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R01_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R01_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R01_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R01_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR01 + */ +#define XDDR_XMPU5_CFG_R01 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000011CUL ) +#define XDDR_XMPU5_CFG_R01_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R01_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R01_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R01_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R01_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R01_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R01_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R01_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R01_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R01_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R01_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R01_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R01_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R01_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R01_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R01_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R01_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R01_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R01_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R01_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R01_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR02Strt + */ +#define XDDR_XMPU5_CFG_R02_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000120UL ) +#define XDDR_XMPU5_CFG_R02_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R02_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R02_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R02_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R02_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR02End + */ +#define XDDR_XMPU5_CFG_R02_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000124UL ) +#define XDDR_XMPU5_CFG_R02_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R02_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R02_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R02_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R02_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR02Mstr + */ +#define XDDR_XMPU5_CFG_R02_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000128UL ) +#define XDDR_XMPU5_CFG_R02_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R02_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R02_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R02_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R02_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R02_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R02_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R02_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R02_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR02 + */ +#define XDDR_XMPU5_CFG_R02 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000012CUL ) +#define XDDR_XMPU5_CFG_R02_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R02_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R02_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R02_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R02_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R02_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R02_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R02_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R02_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R02_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R02_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R02_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R02_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R02_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R02_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R02_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R02_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R02_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R02_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R02_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R02_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR03Strt + */ +#define XDDR_XMPU5_CFG_R03_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000130UL ) +#define XDDR_XMPU5_CFG_R03_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R03_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R03_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R03_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R03_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR03End + */ +#define XDDR_XMPU5_CFG_R03_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000134UL ) +#define XDDR_XMPU5_CFG_R03_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R03_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R03_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R03_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R03_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR03Mstr + */ +#define XDDR_XMPU5_CFG_R03_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000138UL ) +#define XDDR_XMPU5_CFG_R03_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R03_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R03_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R03_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R03_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R03_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R03_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R03_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R03_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR03 + */ +#define XDDR_XMPU5_CFG_R03 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000013CUL ) +#define XDDR_XMPU5_CFG_R03_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R03_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R03_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R03_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R03_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R03_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R03_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R03_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R03_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R03_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R03_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R03_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R03_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R03_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R03_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R03_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R03_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R03_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R03_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R03_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R03_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR04Strt + */ +#define XDDR_XMPU5_CFG_R04_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000140UL ) +#define XDDR_XMPU5_CFG_R04_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R04_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R04_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R04_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R04_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR04End + */ +#define XDDR_XMPU5_CFG_R04_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000144UL ) +#define XDDR_XMPU5_CFG_R04_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R04_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R04_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R04_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R04_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR04Mstr + */ +#define XDDR_XMPU5_CFG_R04_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000148UL ) +#define XDDR_XMPU5_CFG_R04_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R04_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R04_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R04_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R04_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R04_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R04_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R04_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R04_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR04 + */ +#define XDDR_XMPU5_CFG_R04 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000014CUL ) +#define XDDR_XMPU5_CFG_R04_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R04_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R04_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R04_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R04_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R04_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R04_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R04_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R04_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R04_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R04_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R04_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R04_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R04_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R04_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R04_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R04_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R04_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R04_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R04_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R04_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR05Strt + */ +#define XDDR_XMPU5_CFG_R05_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000150UL ) +#define XDDR_XMPU5_CFG_R05_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R05_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R05_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R05_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R05_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR05End + */ +#define XDDR_XMPU5_CFG_R05_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000154UL ) +#define XDDR_XMPU5_CFG_R05_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R05_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R05_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R05_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R05_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR05Mstr + */ +#define XDDR_XMPU5_CFG_R05_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000158UL ) +#define XDDR_XMPU5_CFG_R05_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R05_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R05_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R05_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R05_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R05_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R05_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R05_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R05_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR05 + */ +#define XDDR_XMPU5_CFG_R05 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000015CUL ) +#define XDDR_XMPU5_CFG_R05_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R05_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R05_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R05_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R05_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R05_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R05_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R05_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R05_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R05_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R05_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R05_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R05_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R05_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R05_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R05_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R05_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R05_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R05_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R05_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R05_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR06Strt + */ +#define XDDR_XMPU5_CFG_R06_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000160UL ) +#define XDDR_XMPU5_CFG_R06_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R06_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R06_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R06_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R06_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR06End + */ +#define XDDR_XMPU5_CFG_R06_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000164UL ) +#define XDDR_XMPU5_CFG_R06_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R06_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R06_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R06_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R06_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR06Mstr + */ +#define XDDR_XMPU5_CFG_R06_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000168UL ) +#define XDDR_XMPU5_CFG_R06_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R06_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R06_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R06_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R06_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R06_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R06_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R06_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R06_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR06 + */ +#define XDDR_XMPU5_CFG_R06 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000016CUL ) +#define XDDR_XMPU5_CFG_R06_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R06_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R06_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R06_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R06_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R06_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R06_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R06_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R06_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R06_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R06_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R06_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R06_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R06_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R06_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R06_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R06_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R06_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R06_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R06_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R06_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR07Strt + */ +#define XDDR_XMPU5_CFG_R07_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000170UL ) +#define XDDR_XMPU5_CFG_R07_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R07_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R07_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R07_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R07_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR07End + */ +#define XDDR_XMPU5_CFG_R07_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000174UL ) +#define XDDR_XMPU5_CFG_R07_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R07_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R07_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R07_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R07_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR07Mstr + */ +#define XDDR_XMPU5_CFG_R07_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000178UL ) +#define XDDR_XMPU5_CFG_R07_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R07_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R07_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R07_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R07_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R07_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R07_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R07_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R07_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR07 + */ +#define XDDR_XMPU5_CFG_R07 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000017CUL ) +#define XDDR_XMPU5_CFG_R07_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R07_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R07_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R07_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R07_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R07_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R07_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R07_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R07_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R07_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R07_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R07_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R07_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R07_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R07_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R07_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R07_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R07_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R07_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R07_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R07_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR08Strt + */ +#define XDDR_XMPU5_CFG_R08_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000180UL ) +#define XDDR_XMPU5_CFG_R08_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R08_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R08_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R08_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R08_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR08End + */ +#define XDDR_XMPU5_CFG_R08_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000184UL ) +#define XDDR_XMPU5_CFG_R08_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R08_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R08_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R08_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R08_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR08Mstr + */ +#define XDDR_XMPU5_CFG_R08_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000188UL ) +#define XDDR_XMPU5_CFG_R08_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R08_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R08_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R08_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R08_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R08_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R08_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R08_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R08_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR08 + */ +#define XDDR_XMPU5_CFG_R08 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000018CUL ) +#define XDDR_XMPU5_CFG_R08_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R08_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R08_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R08_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R08_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R08_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R08_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R08_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R08_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R08_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R08_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R08_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R08_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R08_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R08_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R08_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R08_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R08_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R08_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R08_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R08_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR09Strt + */ +#define XDDR_XMPU5_CFG_R09_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000190UL ) +#define XDDR_XMPU5_CFG_R09_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R09_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R09_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R09_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R09_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR09End + */ +#define XDDR_XMPU5_CFG_R09_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000194UL ) +#define XDDR_XMPU5_CFG_R09_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R09_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R09_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R09_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R09_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR09Mstr + */ +#define XDDR_XMPU5_CFG_R09_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000198UL ) +#define XDDR_XMPU5_CFG_R09_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R09_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R09_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R09_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R09_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R09_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R09_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R09_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R09_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR09 + */ +#define XDDR_XMPU5_CFG_R09 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000019CUL ) +#define XDDR_XMPU5_CFG_R09_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R09_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R09_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R09_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R09_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R09_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R09_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R09_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R09_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R09_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R09_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R09_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R09_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R09_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R09_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R09_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R09_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R09_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R09_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R09_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R09_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR10Strt + */ +#define XDDR_XMPU5_CFG_R10_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001A0UL ) +#define XDDR_XMPU5_CFG_R10_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R10_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R10_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R10_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R10_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR10End + */ +#define XDDR_XMPU5_CFG_R10_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001A4UL ) +#define XDDR_XMPU5_CFG_R10_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R10_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R10_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R10_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R10_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR10Mstr + */ +#define XDDR_XMPU5_CFG_R10_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001A8UL ) +#define XDDR_XMPU5_CFG_R10_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R10_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R10_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R10_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R10_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R10_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R10_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R10_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R10_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR10 + */ +#define XDDR_XMPU5_CFG_R10 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001ACUL ) +#define XDDR_XMPU5_CFG_R10_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R10_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R10_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R10_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R10_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R10_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R10_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R10_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R10_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R10_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R10_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R10_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R10_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R10_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R10_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R10_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R10_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R10_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R10_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R10_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R10_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR11Strt + */ +#define XDDR_XMPU5_CFG_R11_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001B0UL ) +#define XDDR_XMPU5_CFG_R11_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R11_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R11_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R11_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R11_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR11End + */ +#define XDDR_XMPU5_CFG_R11_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001B4UL ) +#define XDDR_XMPU5_CFG_R11_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R11_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R11_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R11_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R11_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR11Mstr + */ +#define XDDR_XMPU5_CFG_R11_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001B8UL ) +#define XDDR_XMPU5_CFG_R11_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R11_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R11_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R11_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R11_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R11_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R11_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R11_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R11_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR11 + */ +#define XDDR_XMPU5_CFG_R11 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001BCUL ) +#define XDDR_XMPU5_CFG_R11_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R11_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R11_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R11_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R11_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R11_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R11_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R11_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R11_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R11_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R11_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R11_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R11_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R11_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R11_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R11_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R11_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R11_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R11_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R11_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R11_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR12Strt + */ +#define XDDR_XMPU5_CFG_R12_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001C0UL ) +#define XDDR_XMPU5_CFG_R12_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R12_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R12_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R12_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R12_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR12End + */ +#define XDDR_XMPU5_CFG_R12_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001C4UL ) +#define XDDR_XMPU5_CFG_R12_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R12_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R12_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R12_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R12_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR12Mstr + */ +#define XDDR_XMPU5_CFG_R12_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001C8UL ) +#define XDDR_XMPU5_CFG_R12_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R12_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R12_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R12_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R12_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R12_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R12_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R12_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R12_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR12 + */ +#define XDDR_XMPU5_CFG_R12 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001CCUL ) +#define XDDR_XMPU5_CFG_R12_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R12_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R12_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R12_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R12_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R12_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R12_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R12_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R12_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R12_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R12_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R12_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R12_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R12_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R12_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R12_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R12_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R12_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R12_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R12_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R12_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR13Strt + */ +#define XDDR_XMPU5_CFG_R13_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001D0UL ) +#define XDDR_XMPU5_CFG_R13_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R13_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R13_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R13_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R13_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR13End + */ +#define XDDR_XMPU5_CFG_R13_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001D4UL ) +#define XDDR_XMPU5_CFG_R13_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R13_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R13_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R13_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R13_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR13Mstr + */ +#define XDDR_XMPU5_CFG_R13_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001D8UL ) +#define XDDR_XMPU5_CFG_R13_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R13_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R13_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R13_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R13_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R13_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R13_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R13_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R13_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR13 + */ +#define XDDR_XMPU5_CFG_R13 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001DCUL ) +#define XDDR_XMPU5_CFG_R13_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R13_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R13_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R13_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R13_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R13_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R13_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R13_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R13_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R13_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R13_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R13_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R13_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R13_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R13_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R13_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R13_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R13_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R13_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R13_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R13_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR14Strt + */ +#define XDDR_XMPU5_CFG_R14_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001E0UL ) +#define XDDR_XMPU5_CFG_R14_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R14_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R14_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R14_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R14_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR14End + */ +#define XDDR_XMPU5_CFG_R14_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001E4UL ) +#define XDDR_XMPU5_CFG_R14_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R14_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R14_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R14_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R14_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR14Mstr + */ +#define XDDR_XMPU5_CFG_R14_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001E8UL ) +#define XDDR_XMPU5_CFG_R14_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R14_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R14_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R14_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R14_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R14_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R14_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R14_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R14_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR14 + */ +#define XDDR_XMPU5_CFG_R14 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001ECUL ) +#define XDDR_XMPU5_CFG_R14_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R14_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R14_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R14_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R14_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R14_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R14_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R14_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R14_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R14_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R14_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R14_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R14_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R14_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R14_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R14_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R14_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R14_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R14_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R14_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R14_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR15Strt + */ +#define XDDR_XMPU5_CFG_R15_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001F0UL ) +#define XDDR_XMPU5_CFG_R15_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R15_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R15_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R15_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R15_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR15End + */ +#define XDDR_XMPU5_CFG_R15_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001F4UL ) +#define XDDR_XMPU5_CFG_R15_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R15_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R15_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R15_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R15_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR15Mstr + */ +#define XDDR_XMPU5_CFG_R15_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001F8UL ) +#define XDDR_XMPU5_CFG_R15_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R15_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R15_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R15_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R15_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R15_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R15_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R15_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R15_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR15 + */ +#define XDDR_XMPU5_CFG_R15 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001FCUL ) +#define XDDR_XMPU5_CFG_R15_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R15_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R15_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R15_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R15_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R15_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R15_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R15_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R15_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R15_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R15_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R15_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R15_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R15_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R15_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R15_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R15_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R15_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R15_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R15_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R15_EN_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XDDR_XMPU5_CFG_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xfpd_slcr.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xfpd_slcr.h new file mode 100644 index 0000000..b565b95 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xfpd_slcr.h
@@ -0,0 +1,382 @@ +/* ### HEADER ### */ + +#ifndef __XFPD_SLCR_H__ +#define __XFPD_SLCR_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XfpdSlcr Base Address + */ +#define XFPD_SLCR_BASEADDR 0xFD610000UL + +/** + * Register: XfpdSlcrWprot0 + */ +#define XFPD_SLCR_WPROT0 ( ( XFPD_SLCR_BASEADDR ) + 0x00000000UL ) +#define XFPD_SLCR_WPROT0_RSTVAL 0x00000001UL + +#define XFPD_SLCR_WPROT0_ACT_SHIFT 0UL +#define XFPD_SLCR_WPROT0_ACT_WIDTH 1UL +#define XFPD_SLCR_WPROT0_ACT_MASK 0x00000001UL +#define XFPD_SLCR_WPROT0_ACT_DEFVAL 0x1UL + +/** + * Register: XfpdSlcrCtrl + */ +#define XFPD_SLCR_CTRL ( ( XFPD_SLCR_BASEADDR ) + 0x00000004UL ) +#define XFPD_SLCR_CTRL_RSTVAL 0x00000000UL + +#define XFPD_SLCR_CTRL_SLVERR_EN_SHIFT 0UL +#define XFPD_SLCR_CTRL_SLVERR_EN_WIDTH 1UL +#define XFPD_SLCR_CTRL_SLVERR_EN_MASK 0x00000001UL +#define XFPD_SLCR_CTRL_SLVERR_EN_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrIsr + */ +#define XFPD_SLCR_ISR ( ( XFPD_SLCR_BASEADDR ) + 0x00000008UL ) +#define XFPD_SLCR_ISR_RSTVAL 0x00000000UL + +#define XFPD_SLCR_ISR_ADDR_DECD_ERR_SHIFT 0UL +#define XFPD_SLCR_ISR_ADDR_DECD_ERR_WIDTH 1UL +#define XFPD_SLCR_ISR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XFPD_SLCR_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrImr + */ +#define XFPD_SLCR_IMR ( ( XFPD_SLCR_BASEADDR ) + 0x0000000CUL ) +#define XFPD_SLCR_IMR_RSTVAL 0x00000001UL + +#define XFPD_SLCR_IMR_ADDR_DECD_ERR_SHIFT 0UL +#define XFPD_SLCR_IMR_ADDR_DECD_ERR_WIDTH 1UL +#define XFPD_SLCR_IMR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XFPD_SLCR_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL + +/** + * Register: XfpdSlcrIer + */ +#define XFPD_SLCR_IER ( ( XFPD_SLCR_BASEADDR ) + 0x00000010UL ) +#define XFPD_SLCR_IER_RSTVAL 0x00000000UL + +#define XFPD_SLCR_IER_ADDR_DECD_ERR_SHIFT 0UL +#define XFPD_SLCR_IER_ADDR_DECD_ERR_WIDTH 1UL +#define XFPD_SLCR_IER_ADDR_DECD_ERR_MASK 0x00000001UL +#define XFPD_SLCR_IER_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrIdr + */ +#define XFPD_SLCR_IDR ( ( XFPD_SLCR_BASEADDR ) + 0x00000014UL ) +#define XFPD_SLCR_IDR_RSTVAL 0x00000000UL + +#define XFPD_SLCR_IDR_ADDR_DECD_ERR_SHIFT 0UL +#define XFPD_SLCR_IDR_ADDR_DECD_ERR_WIDTH 1UL +#define XFPD_SLCR_IDR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XFPD_SLCR_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrItr + */ +#define XFPD_SLCR_ITR ( ( XFPD_SLCR_BASEADDR ) + 0x00000018UL ) +#define XFPD_SLCR_ITR_RSTVAL 0x00000000UL + +#define XFPD_SLCR_ITR_ADDR_DECD_ERR_SHIFT 0UL +#define XFPD_SLCR_ITR_ADDR_DECD_ERR_WIDTH 1UL +#define XFPD_SLCR_ITR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XFPD_SLCR_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrWdtClkSel + */ +#define XFPD_SLCR_WDT_CLK_SEL ( ( XFPD_SLCR_BASEADDR ) + 0x00000100UL ) +#define XFPD_SLCR_WDT_CLK_SEL_RSTVAL 0x00000000UL + +#define XFPD_SLCR_WDT_CLK_SEL_SHIFT 0UL +#define XFPD_SLCR_WDT_CLK_SEL_WIDTH 1UL +#define XFPD_SLCR_WDT_CLK_SEL_MASK 0x00000001UL +#define XFPD_SLCR_WDT_CLK_SEL_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrIntFpd + */ +#define XFPD_SLCR_INT_FPD ( ( XFPD_SLCR_BASEADDR ) + 0x00000200UL ) +#define XFPD_SLCR_INT_FPD_RSTVAL 0x00000000UL + +#define XFPD_SLCR_INT_FPD_GFM_SEL_SHIFT 0UL +#define XFPD_SLCR_INT_FPD_GFM_SEL_WIDTH 1UL +#define XFPD_SLCR_INT_FPD_GFM_SEL_MASK 0x00000001UL +#define XFPD_SLCR_INT_FPD_GFM_SEL_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrGpu + */ +#define XFPD_SLCR_GPU ( ( XFPD_SLCR_BASEADDR ) + 0x0000100CUL ) +#define XFPD_SLCR_GPU_RSTVAL 0x00000007UL + +#define XFPD_SLCR_GPU_ARCACHE_SHIFT 7UL +#define XFPD_SLCR_GPU_ARCACHE_WIDTH 4UL +#define XFPD_SLCR_GPU_ARCACHE_MASK 0x00000780UL +#define XFPD_SLCR_GPU_ARCACHE_DEFVAL 0x0UL + +#define XFPD_SLCR_GPU_AWCACHE_SHIFT 3UL +#define XFPD_SLCR_GPU_AWCACHE_WIDTH 4UL +#define XFPD_SLCR_GPU_AWCACHE_MASK 0x00000078UL +#define XFPD_SLCR_GPU_AWCACHE_DEFVAL 0x0UL + +#define XFPD_SLCR_GPU_PP1_IDLE_SHIFT 2UL +#define XFPD_SLCR_GPU_PP1_IDLE_WIDTH 1UL +#define XFPD_SLCR_GPU_PP1_IDLE_MASK 0x00000004UL +#define XFPD_SLCR_GPU_PP1_IDLE_DEFVAL 0x1UL + +#define XFPD_SLCR_GPU_PP0_IDLE_SHIFT 1UL +#define XFPD_SLCR_GPU_PP0_IDLE_WIDTH 1UL +#define XFPD_SLCR_GPU_PP0_IDLE_MASK 0x00000002UL +#define XFPD_SLCR_GPU_PP0_IDLE_DEFVAL 0x1UL + +#define XFPD_SLCR_GPU_IDLE_SHIFT 0UL +#define XFPD_SLCR_GPU_IDLE_WIDTH 1UL +#define XFPD_SLCR_GPU_IDLE_MASK 0x00000001UL +#define XFPD_SLCR_GPU_IDLE_DEFVAL 0x1UL + +/** + * Register: XfpdSlcrGdmaCfg + */ +#define XFPD_SLCR_GDMA_CFG ( ( XFPD_SLCR_BASEADDR ) + 0x00003000UL ) +#define XFPD_SLCR_GDMA_CFG_RSTVAL 0x00000048UL + +#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_SHIFT 5UL +#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_WIDTH 2UL +#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_MASK 0x00000060UL +#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_DEFVAL 0x2UL + +#define XFPD_SLCR_GDMA_CFG_NUM_CH_SHIFT 0UL +#define XFPD_SLCR_GDMA_CFG_NUM_CH_WIDTH 5UL +#define XFPD_SLCR_GDMA_CFG_NUM_CH_MASK 0x0000001fUL +#define XFPD_SLCR_GDMA_CFG_NUM_CH_DEFVAL 0x8UL + +/** + * Register: XfpdSlcrGdma + */ +#define XFPD_SLCR_GDMA ( ( XFPD_SLCR_BASEADDR ) + 0x00003010UL ) +#define XFPD_SLCR_GDMA_RSTVAL 0x00003b3bUL + +#define XFPD_SLCR_GDMA_RAM1_EMAB_SHIFT 12UL +#define XFPD_SLCR_GDMA_RAM1_EMAB_WIDTH 3UL +#define XFPD_SLCR_GDMA_RAM1_EMAB_MASK 0x00007000UL +#define XFPD_SLCR_GDMA_RAM1_EMAB_DEFVAL 0x3UL + +#define XFPD_SLCR_GDMA_RAM1_EMASA_SHIFT 11UL +#define XFPD_SLCR_GDMA_RAM1_EMASA_WIDTH 1UL +#define XFPD_SLCR_GDMA_RAM1_EMASA_MASK 0x00000800UL +#define XFPD_SLCR_GDMA_RAM1_EMASA_DEFVAL 0x1UL + +#define XFPD_SLCR_GDMA_RAM1_EMAA_SHIFT 8UL +#define XFPD_SLCR_GDMA_RAM1_EMAA_WIDTH 3UL +#define XFPD_SLCR_GDMA_RAM1_EMAA_MASK 0x00000700UL +#define XFPD_SLCR_GDMA_RAM1_EMAA_DEFVAL 0x3UL + +#define XFPD_SLCR_GDMA_RAM0_EMAB_SHIFT 4UL +#define XFPD_SLCR_GDMA_RAM0_EMAB_WIDTH 3UL +#define XFPD_SLCR_GDMA_RAM0_EMAB_MASK 0x00000070UL +#define XFPD_SLCR_GDMA_RAM0_EMAB_DEFVAL 0x3UL + +#define XFPD_SLCR_GDMA_RAM0_EMASA_SHIFT 3UL +#define XFPD_SLCR_GDMA_RAM0_EMASA_WIDTH 1UL +#define XFPD_SLCR_GDMA_RAM0_EMASA_MASK 0x00000008UL +#define XFPD_SLCR_GDMA_RAM0_EMASA_DEFVAL 0x1UL + +#define XFPD_SLCR_GDMA_RAM0_EMAA_SHIFT 0UL +#define XFPD_SLCR_GDMA_RAM0_EMAA_WIDTH 3UL +#define XFPD_SLCR_GDMA_RAM0_EMAA_MASK 0x00000007UL +#define XFPD_SLCR_GDMA_RAM0_EMAA_DEFVAL 0x3UL + +/** + * Register: XfpdSlcrAfiFs + */ +#define XFPD_SLCR_AFI_FS ( ( XFPD_SLCR_BASEADDR ) + 0x00005000UL ) +#define XFPD_SLCR_AFI_FS_RSTVAL 0x00000a00UL + +#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_SHIFT 10UL +#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_WIDTH 2UL +#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_MASK 0x00000c00UL +#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_DEFVAL 0x2UL + +#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_SHIFT 8UL +#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_WIDTH 2UL +#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_MASK 0x00000300UL +#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_DEFVAL 0x2UL + +/** + * Register: XfpdSlcrErrAtbIsr + */ +#define XFPD_SLCR_ERR_ATB_ISR ( ( XFPD_SLCR_BASEADDR ) + 0x00006000UL ) +#define XFPD_SLCR_ERR_ATB_ISR_RSTVAL 0x00000000UL + +#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_SHIFT 2UL +#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_MASK 0x00000004UL +#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_DEFVAL 0x0UL + +#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_SHIFT 1UL +#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_MASK 0x00000002UL +#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_DEFVAL 0x0UL + +#define XFPD_SLCR_ERR_ATB_ISR_FPDS_SHIFT 0UL +#define XFPD_SLCR_ERR_ATB_ISR_FPDS_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_ISR_FPDS_MASK 0x00000001UL +#define XFPD_SLCR_ERR_ATB_ISR_FPDS_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrErrAtbImr + */ +#define XFPD_SLCR_ERR_ATB_IMR ( ( XFPD_SLCR_BASEADDR ) + 0x00006004UL ) +#define XFPD_SLCR_ERR_ATB_IMR_RSTVAL 0x00000007UL + +#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_SHIFT 2UL +#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_MASK 0x00000004UL +#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_DEFVAL 0x1UL + +#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_SHIFT 1UL +#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_MASK 0x00000002UL +#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_DEFVAL 0x1UL + +#define XFPD_SLCR_ERR_ATB_IMR_FPDS_SHIFT 0UL +#define XFPD_SLCR_ERR_ATB_IMR_FPDS_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_IMR_FPDS_MASK 0x00000001UL +#define XFPD_SLCR_ERR_ATB_IMR_FPDS_DEFVAL 0x1UL + +/** + * Register: XfpdSlcrErrAtbIer + */ +#define XFPD_SLCR_ERR_ATB_IER ( ( XFPD_SLCR_BASEADDR ) + 0x00006008UL ) +#define XFPD_SLCR_ERR_ATB_IER_RSTVAL 0x00000000UL + +#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_SHIFT 2UL +#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_MASK 0x00000004UL +#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_DEFVAL 0x0UL + +#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_SHIFT 1UL +#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_MASK 0x00000002UL +#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_DEFVAL 0x0UL + +#define XFPD_SLCR_ERR_ATB_IER_FPDS_SHIFT 0UL +#define XFPD_SLCR_ERR_ATB_IER_FPDS_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_IER_FPDS_MASK 0x00000001UL +#define XFPD_SLCR_ERR_ATB_IER_FPDS_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrErrAtbIdr + */ +#define XFPD_SLCR_ERR_ATB_IDR ( ( XFPD_SLCR_BASEADDR ) + 0x0000600CUL ) +#define XFPD_SLCR_ERR_ATB_IDR_RSTVAL 0x00000000UL + +#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_SHIFT 2UL +#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_MASK 0x00000004UL +#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_DEFVAL 0x0UL + +#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_SHIFT 1UL +#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_MASK 0x00000002UL +#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_DEFVAL 0x0UL + +#define XFPD_SLCR_ERR_ATB_IDR_FPDS_SHIFT 0UL +#define XFPD_SLCR_ERR_ATB_IDR_FPDS_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_IDR_FPDS_MASK 0x00000001UL +#define XFPD_SLCR_ERR_ATB_IDR_FPDS_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrAtbCmdstore + */ +#define XFPD_SLCR_ATB_CMDSTORE ( ( XFPD_SLCR_BASEADDR ) + 0x00006010UL ) +#define XFPD_SLCR_ATB_CMDSTORE_RSTVAL 0x00000007UL + +#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_SHIFT 2UL +#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_WIDTH 1UL +#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_MASK 0x00000004UL +#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_DEFVAL 0x1UL + +#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_SHIFT 1UL +#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_WIDTH 1UL +#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_MASK 0x00000002UL +#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_DEFVAL 0x1UL + +#define XFPD_SLCR_ATB_CMDSTORE_FPDS_SHIFT 0UL +#define XFPD_SLCR_ATB_CMDSTORE_FPDS_WIDTH 1UL +#define XFPD_SLCR_ATB_CMDSTORE_FPDS_MASK 0x00000001UL +#define XFPD_SLCR_ATB_CMDSTORE_FPDS_DEFVAL 0x1UL + +/** + * Register: XfpdSlcrAtbRespEn + */ +#define XFPD_SLCR_ATB_RESP_EN ( ( XFPD_SLCR_BASEADDR ) + 0x00006014UL ) +#define XFPD_SLCR_ATB_RESP_EN_RSTVAL 0x00000000UL + +#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_SHIFT 2UL +#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_WIDTH 1UL +#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_MASK 0x00000004UL +#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_DEFVAL 0x0UL + +#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_SHIFT 1UL +#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_WIDTH 1UL +#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_MASK 0x00000002UL +#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_DEFVAL 0x0UL + +#define XFPD_SLCR_ATB_RESP_EN_FPDS_SHIFT 0UL +#define XFPD_SLCR_ATB_RESP_EN_FPDS_WIDTH 1UL +#define XFPD_SLCR_ATB_RESP_EN_FPDS_MASK 0x00000001UL +#define XFPD_SLCR_ATB_RESP_EN_FPDS_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrAtbResptype + */ +#define XFPD_SLCR_ATB_RESPTYPE ( ( XFPD_SLCR_BASEADDR ) + 0x00006018UL ) +#define XFPD_SLCR_ATB_RESPTYPE_RSTVAL 0x00000007UL + +#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_SHIFT 2UL +#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_WIDTH 1UL +#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_MASK 0x00000004UL +#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_DEFVAL 0x1UL + +#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_SHIFT 1UL +#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_WIDTH 1UL +#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_MASK 0x00000002UL +#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_DEFVAL 0x1UL + +#define XFPD_SLCR_ATB_RESPTYPE_FPDS_SHIFT 0UL +#define XFPD_SLCR_ATB_RESPTYPE_FPDS_WIDTH 1UL +#define XFPD_SLCR_ATB_RESPTYPE_FPDS_MASK 0x00000001UL +#define XFPD_SLCR_ATB_RESPTYPE_FPDS_DEFVAL 0x1UL + +/** + * Register: XfpdSlcrAtbPrescale + */ +#define XFPD_SLCR_ATB_PRESCALE ( ( XFPD_SLCR_BASEADDR ) + 0x00006020UL ) +#define XFPD_SLCR_ATB_PRESCALE_RSTVAL 0x0000ffffUL + +#define XFPD_SLCR_ATB_PRESCALE_EN_SHIFT 16UL +#define XFPD_SLCR_ATB_PRESCALE_EN_WIDTH 1UL +#define XFPD_SLCR_ATB_PRESCALE_EN_MASK 0x00010000UL +#define XFPD_SLCR_ATB_PRESCALE_EN_DEFVAL 0x0UL + +#define XFPD_SLCR_ATB_PRESCALE_VAL_SHIFT 0UL +#define XFPD_SLCR_ATB_PRESCALE_VAL_WIDTH 16UL +#define XFPD_SLCR_ATB_PRESCALE_VAL_MASK 0x0000ffffUL +#define XFPD_SLCR_ATB_PRESCALE_VAL_DEFVAL 0xffffUL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XFPD_SLCR_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xfpd_slcr_secure.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xfpd_slcr_secure.h new file mode 100644 index 0000000..6541a4f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xfpd_slcr_secure.h
@@ -0,0 +1,277 @@ +/* ### HEADER ### */ + +#ifndef __XFPD_SLCR_SECURE_H__ +#define __XFPD_SLCR_SECURE_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XfpdSlcrSecure Base Address + */ +#define XFPD_SLCR_SECURE_BASEADDR 0xFD690000UL + +/** + * Register: XfpdSlcrSecCtrl + */ +#define XFPD_SLCR_SEC_CTRL ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000004UL ) +#define XFPD_SLCR_SEC_CTRL_RSTVAL 0x00000000UL + +#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_SHIFT 0UL +#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_WIDTH 1UL +#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_MASK 0x00000001UL +#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrSecIsr + */ +#define XFPD_SLCR_SEC_ISR ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000008UL ) +#define XFPD_SLCR_SEC_ISR_RSTVAL 0x00000000UL + +#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_SHIFT 0UL +#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_WIDTH 1UL +#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrSecImr + */ +#define XFPD_SLCR_SEC_IMR ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x0000000CUL ) +#define XFPD_SLCR_SEC_IMR_RSTVAL 0x00000001UL + +#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_SHIFT 0UL +#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_WIDTH 1UL +#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL + +/** + * Register: XfpdSlcrSecIer + */ +#define XFPD_SLCR_SEC_IER ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000010UL ) +#define XFPD_SLCR_SEC_IER_RSTVAL 0x00000000UL + +#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_SHIFT 0UL +#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_WIDTH 1UL +#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_MASK 0x00000001UL +#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrSecIdr + */ +#define XFPD_SLCR_SEC_IDR ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000014UL ) +#define XFPD_SLCR_SEC_IDR_RSTVAL 0x00000000UL + +#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_SHIFT 0UL +#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_WIDTH 1UL +#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrSecItr + */ +#define XFPD_SLCR_SEC_ITR ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000018UL ) +#define XFPD_SLCR_SEC_ITR_RSTVAL 0x00000000UL + +#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_SHIFT 0UL +#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_WIDTH 1UL +#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrSecSata + */ +#define XFPD_SLCR_SEC_SATA ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000020UL ) +#define XFPD_SLCR_SEC_SATA_RSTVAL 0x0000000eUL + +#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_SHIFT 3UL +#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_WIDTH 1UL +#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_MASK 0x00000008UL +#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_SHIFT 2UL +#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_WIDTH 1UL +#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_MASK 0x00000004UL +#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_SATA_TZ_AXIS_SHIFT 1UL +#define XFPD_SLCR_SEC_SATA_TZ_AXIS_WIDTH 1UL +#define XFPD_SLCR_SEC_SATA_TZ_AXIS_MASK 0x00000002UL +#define XFPD_SLCR_SEC_SATA_TZ_AXIS_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_SATA_TZ_EN_SHIFT 0UL +#define XFPD_SLCR_SEC_SATA_TZ_EN_WIDTH 1UL +#define XFPD_SLCR_SEC_SATA_TZ_EN_MASK 0x00000001UL +#define XFPD_SLCR_SEC_SATA_TZ_EN_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrSecPcie + */ +#define XFPD_SLCR_SEC_PCIE ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000030UL ) +#define XFPD_SLCR_SEC_PCIE_RSTVAL 0x01ffffffUL + +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_SHIFT 24UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_MASK 0x01000000UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_SHIFT 23UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_MASK 0x00800000UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_SHIFT 22UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_MASK 0x00400000UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_SHIFT 21UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_MASK 0x00200000UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_SHIFT 20UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_MASK 0x00100000UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_SHIFT 19UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_MASK 0x00080000UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_SHIFT 18UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_MASK 0x00040000UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_SHIFT 17UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_MASK 0x00020000UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_SHIFT 16UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_MASK 0x00010000UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_SHIFT 15UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_MASK 0x00008000UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_SHIFT 14UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_MASK 0x00004000UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_SHIFT 13UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_MASK 0x00002000UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_SHIFT 12UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_MASK 0x00001000UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_SHIFT 11UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_MASK 0x00000800UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_SHIFT 10UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_MASK 0x00000400UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_SHIFT 9UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_MASK 0x00000200UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_SHIFT 8UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_MASK 0x00000100UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_SHIFT 7UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_MASK 0x00000080UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_SHIFT 6UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_MASK 0x00000040UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_SHIFT 5UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_MASK 0x00000020UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_SHIFT 4UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_MASK 0x00000010UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_SHIFT 3UL +#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_MASK 0x00000008UL +#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_SHIFT 2UL +#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_MASK 0x00000004UL +#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_SHIFT 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_MASK 0x00000002UL +#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_SHIFT 0UL +#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_MASK 0x00000001UL +#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_DEFVAL 0x1UL + +/** + * Register: XfpdSlcrSecDpdma + */ +#define XFPD_SLCR_SEC_DPDMA ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000040UL ) +#define XFPD_SLCR_SEC_DPDMA_RSTVAL 0x00000001UL + +#define XFPD_SLCR_SEC_DPDMA_TZ_SHIFT 0UL +#define XFPD_SLCR_SEC_DPDMA_TZ_WIDTH 1UL +#define XFPD_SLCR_SEC_DPDMA_TZ_MASK 0x00000001UL +#define XFPD_SLCR_SEC_DPDMA_TZ_DEFVAL 0x1UL + +/** + * Register: XfpdSlcrSecGdma + */ +#define XFPD_SLCR_SEC_GDMA ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000050UL ) +#define XFPD_SLCR_SEC_GDMA_RSTVAL 0x000000ffUL + +#define XFPD_SLCR_SEC_GDMA_TZ_SHIFT 0UL +#define XFPD_SLCR_SEC_GDMA_TZ_WIDTH 8UL +#define XFPD_SLCR_SEC_GDMA_TZ_MASK 0x000000ffUL +#define XFPD_SLCR_SEC_GDMA_TZ_DEFVAL 0xffUL + +/** + * Register: XfpdSlcrSecGic + */ +#define XFPD_SLCR_SEC_GIC ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000060UL ) +#define XFPD_SLCR_SEC_GIC_RSTVAL 0x00000000UL + +#define XFPD_SLCR_SEC_GIC_CFG_DIS_SHIFT 0UL +#define XFPD_SLCR_SEC_GIC_CFG_DIS_WIDTH 1UL +#define XFPD_SLCR_SEC_GIC_CFG_DIS_MASK 0x00000001UL +#define XFPD_SLCR_SEC_GIC_CFG_DIS_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XFPD_SLCR_SECURE_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xfpd_xmpu_cfg.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xfpd_xmpu_cfg.h new file mode 100644 index 0000000..75aef19 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xfpd_xmpu_cfg.h
@@ -0,0 +1,1304 @@ +/* ### HEADER ### */ + +#ifndef __XFPD_XMPU_CFG_H__ +#define __XFPD_XMPU_CFG_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XfpdXmpuCfg Base Address + */ +#define XFPD_XMPU_CFG_BASEADDR 0xFD5D0000UL + +/** + * Register: XfpdXmpuCfgCtrl + */ +#define XFPD_XMPU_CFG_CTRL ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000000UL ) +#define XFPD_XMPU_CFG_CTRL_RSTVAL 0x00000003UL + +#define XFPD_XMPU_CFG_CTRL_ALIGNCFG_SHIFT 3UL +#define XFPD_XMPU_CFG_CTRL_ALIGNCFG_WIDTH 1UL +#define XFPD_XMPU_CFG_CTRL_ALIGNCFG_MASK 0x00000008UL +#define XFPD_XMPU_CFG_CTRL_ALIGNCFG_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_CTRL_POISONCFG_SHIFT 2UL +#define XFPD_XMPU_CFG_CTRL_POISONCFG_WIDTH 1UL +#define XFPD_XMPU_CFG_CTRL_POISONCFG_MASK 0x00000004UL +#define XFPD_XMPU_CFG_CTRL_POISONCFG_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_CTRL_DEFWRALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_CTRL_DEFWRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_CTRL_DEFWRALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_CTRL_DEFWRALWD_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_CTRL_DEFRDALWD_SHIFT 0UL +#define XFPD_XMPU_CFG_CTRL_DEFRDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_CTRL_DEFRDALWD_MASK 0x00000001UL +#define XFPD_XMPU_CFG_CTRL_DEFRDALWD_DEFVAL 0x1UL + +/** + * Register: XfpdXmpuCfgErrSts1 + */ +#define XFPD_XMPU_CFG_ERR_STS1 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000004UL ) +#define XFPD_XMPU_CFG_ERR_STS1_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_ERR_STS1_AXI_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_ERR_STS1_AXI_ADDR_WIDTH 32UL +#define XFPD_XMPU_CFG_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL +#define XFPD_XMPU_CFG_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgErrSts2 + */ +#define XFPD_XMPU_CFG_ERR_STS2 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000008UL ) +#define XFPD_XMPU_CFG_ERR_STS2_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_ERR_STS2_AXI_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_ERR_STS2_AXI_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_ERR_STS2_AXI_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_ERR_STS2_AXI_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgPoison + */ +#define XFPD_XMPU_CFG_POISON ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000000CUL ) +#define XFPD_XMPU_CFG_POISON_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_POISON_ATTRIB_SHIFT 20UL +#define XFPD_XMPU_CFG_POISON_ATTRIB_WIDTH 12UL +#define XFPD_XMPU_CFG_POISON_ATTRIB_MASK 0xfff00000UL +#define XFPD_XMPU_CFG_POISON_ATTRIB_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_POISON_BASE_SHIFT 0UL +#define XFPD_XMPU_CFG_POISON_BASE_WIDTH 20UL +#define XFPD_XMPU_CFG_POISON_BASE_MASK 0x000fffffUL +#define XFPD_XMPU_CFG_POISON_BASE_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgIsr + */ +#define XFPD_XMPU_CFG_ISR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000010UL ) +#define XFPD_XMPU_CFG_ISR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_ISR_SECURTYVIO_SHIFT 3UL +#define XFPD_XMPU_CFG_ISR_SECURTYVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_ISR_SECURTYVIO_MASK 0x00000008UL +#define XFPD_XMPU_CFG_ISR_SECURTYVIO_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_ISR_WRPERMVIO_SHIFT 2UL +#define XFPD_XMPU_CFG_ISR_WRPERMVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_ISR_WRPERMVIO_MASK 0x00000004UL +#define XFPD_XMPU_CFG_ISR_WRPERMVIO_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_ISR_RDPERMVIO_SHIFT 1UL +#define XFPD_XMPU_CFG_ISR_RDPERMVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_ISR_RDPERMVIO_MASK 0x00000002UL +#define XFPD_XMPU_CFG_ISR_RDPERMVIO_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_ISR_INV_APB_SHIFT 0UL +#define XFPD_XMPU_CFG_ISR_INV_APB_WIDTH 1UL +#define XFPD_XMPU_CFG_ISR_INV_APB_MASK 0x00000001UL +#define XFPD_XMPU_CFG_ISR_INV_APB_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgImr + */ +#define XFPD_XMPU_CFG_IMR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000014UL ) +#define XFPD_XMPU_CFG_IMR_RSTVAL 0x0000000fUL + +#define XFPD_XMPU_CFG_IMR_SECURTYVIO_SHIFT 3UL +#define XFPD_XMPU_CFG_IMR_SECURTYVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_IMR_SECURTYVIO_MASK 0x00000008UL +#define XFPD_XMPU_CFG_IMR_SECURTYVIO_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_IMR_WRPERMVIO_SHIFT 2UL +#define XFPD_XMPU_CFG_IMR_WRPERMVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_IMR_WRPERMVIO_MASK 0x00000004UL +#define XFPD_XMPU_CFG_IMR_WRPERMVIO_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_IMR_RDPERMVIO_SHIFT 1UL +#define XFPD_XMPU_CFG_IMR_RDPERMVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_IMR_RDPERMVIO_MASK 0x00000002UL +#define XFPD_XMPU_CFG_IMR_RDPERMVIO_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_IMR_INV_APB_SHIFT 0UL +#define XFPD_XMPU_CFG_IMR_INV_APB_WIDTH 1UL +#define XFPD_XMPU_CFG_IMR_INV_APB_MASK 0x00000001UL +#define XFPD_XMPU_CFG_IMR_INV_APB_DEFVAL 0x1UL + +/** + * Register: XfpdXmpuCfgIen + */ +#define XFPD_XMPU_CFG_IEN ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000018UL ) +#define XFPD_XMPU_CFG_IEN_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_IEN_SECURTYVIO_SHIFT 3UL +#define XFPD_XMPU_CFG_IEN_SECURTYVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_IEN_SECURTYVIO_MASK 0x00000008UL +#define XFPD_XMPU_CFG_IEN_SECURTYVIO_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_IEN_WRPERMVIO_SHIFT 2UL +#define XFPD_XMPU_CFG_IEN_WRPERMVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_IEN_WRPERMVIO_MASK 0x00000004UL +#define XFPD_XMPU_CFG_IEN_WRPERMVIO_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_IEN_RDPERMVIO_SHIFT 1UL +#define XFPD_XMPU_CFG_IEN_RDPERMVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_IEN_RDPERMVIO_MASK 0x00000002UL +#define XFPD_XMPU_CFG_IEN_RDPERMVIO_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_IEN_INV_APB_SHIFT 0UL +#define XFPD_XMPU_CFG_IEN_INV_APB_WIDTH 1UL +#define XFPD_XMPU_CFG_IEN_INV_APB_MASK 0x00000001UL +#define XFPD_XMPU_CFG_IEN_INV_APB_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgIds + */ +#define XFPD_XMPU_CFG_IDS ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000001CUL ) +#define XFPD_XMPU_CFG_IDS_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_IDS_SECURTYVIO_SHIFT 3UL +#define XFPD_XMPU_CFG_IDS_SECURTYVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_IDS_SECURTYVIO_MASK 0x00000008UL +#define XFPD_XMPU_CFG_IDS_SECURTYVIO_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_IDS_WRPERMVIO_SHIFT 2UL +#define XFPD_XMPU_CFG_IDS_WRPERMVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_IDS_WRPERMVIO_MASK 0x00000004UL +#define XFPD_XMPU_CFG_IDS_WRPERMVIO_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_IDS_RDPERMVIO_SHIFT 1UL +#define XFPD_XMPU_CFG_IDS_RDPERMVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_IDS_RDPERMVIO_MASK 0x00000002UL +#define XFPD_XMPU_CFG_IDS_RDPERMVIO_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_IDS_INV_APB_SHIFT 0UL +#define XFPD_XMPU_CFG_IDS_INV_APB_WIDTH 1UL +#define XFPD_XMPU_CFG_IDS_INV_APB_MASK 0x00000001UL +#define XFPD_XMPU_CFG_IDS_INV_APB_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgLock + */ +#define XFPD_XMPU_CFG_LOCK ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000020UL ) +#define XFPD_XMPU_CFG_LOCK_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_LOCK_REGWRDIS_SHIFT 0UL +#define XFPD_XMPU_CFG_LOCK_REGWRDIS_WIDTH 1UL +#define XFPD_XMPU_CFG_LOCK_REGWRDIS_MASK 0x00000001UL +#define XFPD_XMPU_CFG_LOCK_REGWRDIS_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR00Strt + */ +#define XFPD_XMPU_CFG_R00_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000100UL ) +#define XFPD_XMPU_CFG_R00_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R00_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R00_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R00_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R00_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR00End + */ +#define XFPD_XMPU_CFG_R00_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000104UL ) +#define XFPD_XMPU_CFG_R00_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R00_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R00_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R00_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R00_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR00Mstr + */ +#define XFPD_XMPU_CFG_R00_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000108UL ) +#define XFPD_XMPU_CFG_R00_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R00_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R00_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R00_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R00_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R00_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R00_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R00_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R00_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR00 + */ +#define XFPD_XMPU_CFG_R00 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000010CUL ) +#define XFPD_XMPU_CFG_R00_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R00_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R00_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R00_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R00_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R00_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R00_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R00_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R00_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R00_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R00_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R00_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R00_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R00_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R00_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R00_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R00_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R00_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R00_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R00_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R00_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR01Strt + */ +#define XFPD_XMPU_CFG_R01_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000110UL ) +#define XFPD_XMPU_CFG_R01_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R01_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R01_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R01_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R01_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR01End + */ +#define XFPD_XMPU_CFG_R01_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000114UL ) +#define XFPD_XMPU_CFG_R01_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R01_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R01_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R01_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R01_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR01Mstr + */ +#define XFPD_XMPU_CFG_R01_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000118UL ) +#define XFPD_XMPU_CFG_R01_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R01_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R01_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R01_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R01_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R01_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R01_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R01_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R01_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR01 + */ +#define XFPD_XMPU_CFG_R01 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000011CUL ) +#define XFPD_XMPU_CFG_R01_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R01_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R01_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R01_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R01_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R01_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R01_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R01_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R01_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R01_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R01_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R01_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R01_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R01_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R01_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R01_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R01_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R01_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R01_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R01_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R01_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR02Strt + */ +#define XFPD_XMPU_CFG_R02_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000120UL ) +#define XFPD_XMPU_CFG_R02_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R02_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R02_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R02_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R02_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR02End + */ +#define XFPD_XMPU_CFG_R02_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000124UL ) +#define XFPD_XMPU_CFG_R02_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R02_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R02_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R02_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R02_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR02Mstr + */ +#define XFPD_XMPU_CFG_R02_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000128UL ) +#define XFPD_XMPU_CFG_R02_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R02_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R02_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R02_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R02_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R02_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R02_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R02_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R02_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR02 + */ +#define XFPD_XMPU_CFG_R02 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000012CUL ) +#define XFPD_XMPU_CFG_R02_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R02_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R02_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R02_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R02_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R02_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R02_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R02_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R02_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R02_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R02_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R02_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R02_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R02_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R02_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R02_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R02_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R02_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R02_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R02_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R02_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR03Strt + */ +#define XFPD_XMPU_CFG_R03_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000130UL ) +#define XFPD_XMPU_CFG_R03_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R03_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R03_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R03_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R03_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR03End + */ +#define XFPD_XMPU_CFG_R03_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000134UL ) +#define XFPD_XMPU_CFG_R03_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R03_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R03_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R03_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R03_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR03Mstr + */ +#define XFPD_XMPU_CFG_R03_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000138UL ) +#define XFPD_XMPU_CFG_R03_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R03_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R03_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R03_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R03_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R03_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R03_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R03_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R03_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR03 + */ +#define XFPD_XMPU_CFG_R03 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000013CUL ) +#define XFPD_XMPU_CFG_R03_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R03_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R03_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R03_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R03_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R03_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R03_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R03_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R03_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R03_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R03_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R03_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R03_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R03_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R03_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R03_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R03_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R03_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R03_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R03_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R03_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR04Strt + */ +#define XFPD_XMPU_CFG_R04_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000140UL ) +#define XFPD_XMPU_CFG_R04_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R04_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R04_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R04_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R04_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR04End + */ +#define XFPD_XMPU_CFG_R04_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000144UL ) +#define XFPD_XMPU_CFG_R04_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R04_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R04_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R04_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R04_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR04Mstr + */ +#define XFPD_XMPU_CFG_R04_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000148UL ) +#define XFPD_XMPU_CFG_R04_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R04_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R04_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R04_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R04_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R04_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R04_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R04_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R04_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR04 + */ +#define XFPD_XMPU_CFG_R04 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000014CUL ) +#define XFPD_XMPU_CFG_R04_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R04_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R04_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R04_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R04_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R04_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R04_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R04_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R04_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R04_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R04_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R04_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R04_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R04_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R04_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R04_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R04_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R04_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R04_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R04_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R04_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR05Strt + */ +#define XFPD_XMPU_CFG_R05_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000150UL ) +#define XFPD_XMPU_CFG_R05_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R05_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R05_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R05_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R05_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR05End + */ +#define XFPD_XMPU_CFG_R05_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000154UL ) +#define XFPD_XMPU_CFG_R05_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R05_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R05_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R05_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R05_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR05Mstr + */ +#define XFPD_XMPU_CFG_R05_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000158UL ) +#define XFPD_XMPU_CFG_R05_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R05_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R05_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R05_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R05_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R05_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R05_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R05_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R05_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR05 + */ +#define XFPD_XMPU_CFG_R05 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000015CUL ) +#define XFPD_XMPU_CFG_R05_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R05_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R05_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R05_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R05_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R05_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R05_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R05_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R05_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R05_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R05_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R05_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R05_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R05_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R05_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R05_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R05_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R05_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R05_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R05_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R05_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR06Strt + */ +#define XFPD_XMPU_CFG_R06_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000160UL ) +#define XFPD_XMPU_CFG_R06_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R06_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R06_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R06_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R06_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR06End + */ +#define XFPD_XMPU_CFG_R06_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000164UL ) +#define XFPD_XMPU_CFG_R06_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R06_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R06_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R06_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R06_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR06Mstr + */ +#define XFPD_XMPU_CFG_R06_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000168UL ) +#define XFPD_XMPU_CFG_R06_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R06_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R06_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R06_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R06_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R06_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R06_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R06_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R06_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR06 + */ +#define XFPD_XMPU_CFG_R06 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000016CUL ) +#define XFPD_XMPU_CFG_R06_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R06_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R06_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R06_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R06_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R06_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R06_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R06_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R06_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R06_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R06_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R06_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R06_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R06_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R06_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R06_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R06_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R06_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R06_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R06_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R06_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR07Strt + */ +#define XFPD_XMPU_CFG_R07_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000170UL ) +#define XFPD_XMPU_CFG_R07_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R07_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R07_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R07_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R07_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR07End + */ +#define XFPD_XMPU_CFG_R07_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000174UL ) +#define XFPD_XMPU_CFG_R07_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R07_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R07_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R07_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R07_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR07Mstr + */ +#define XFPD_XMPU_CFG_R07_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000178UL ) +#define XFPD_XMPU_CFG_R07_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R07_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R07_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R07_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R07_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R07_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R07_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R07_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R07_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR07 + */ +#define XFPD_XMPU_CFG_R07 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000017CUL ) +#define XFPD_XMPU_CFG_R07_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R07_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R07_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R07_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R07_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R07_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R07_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R07_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R07_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R07_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R07_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R07_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R07_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R07_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R07_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R07_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R07_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R07_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R07_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R07_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R07_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR08Strt + */ +#define XFPD_XMPU_CFG_R08_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000180UL ) +#define XFPD_XMPU_CFG_R08_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R08_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R08_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R08_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R08_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR08End + */ +#define XFPD_XMPU_CFG_R08_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000184UL ) +#define XFPD_XMPU_CFG_R08_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R08_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R08_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R08_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R08_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR08Mstr + */ +#define XFPD_XMPU_CFG_R08_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000188UL ) +#define XFPD_XMPU_CFG_R08_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R08_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R08_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R08_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R08_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R08_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R08_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R08_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R08_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR08 + */ +#define XFPD_XMPU_CFG_R08 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000018CUL ) +#define XFPD_XMPU_CFG_R08_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R08_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R08_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R08_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R08_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R08_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R08_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R08_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R08_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R08_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R08_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R08_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R08_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R08_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R08_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R08_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R08_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R08_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R08_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R08_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R08_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR09Strt + */ +#define XFPD_XMPU_CFG_R09_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000190UL ) +#define XFPD_XMPU_CFG_R09_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R09_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R09_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R09_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R09_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR09End + */ +#define XFPD_XMPU_CFG_R09_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000194UL ) +#define XFPD_XMPU_CFG_R09_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R09_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R09_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R09_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R09_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR09Mstr + */ +#define XFPD_XMPU_CFG_R09_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000198UL ) +#define XFPD_XMPU_CFG_R09_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R09_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R09_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R09_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R09_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R09_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R09_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R09_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R09_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR09 + */ +#define XFPD_XMPU_CFG_R09 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000019CUL ) +#define XFPD_XMPU_CFG_R09_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R09_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R09_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R09_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R09_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R09_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R09_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R09_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R09_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R09_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R09_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R09_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R09_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R09_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R09_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R09_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R09_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R09_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R09_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R09_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R09_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR10Strt + */ +#define XFPD_XMPU_CFG_R10_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001A0UL ) +#define XFPD_XMPU_CFG_R10_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R10_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R10_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R10_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R10_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR10End + */ +#define XFPD_XMPU_CFG_R10_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001A4UL ) +#define XFPD_XMPU_CFG_R10_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R10_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R10_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R10_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R10_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR10Mstr + */ +#define XFPD_XMPU_CFG_R10_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001A8UL ) +#define XFPD_XMPU_CFG_R10_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R10_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R10_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R10_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R10_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R10_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R10_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R10_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R10_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR10 + */ +#define XFPD_XMPU_CFG_R10 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001ACUL ) +#define XFPD_XMPU_CFG_R10_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R10_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R10_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R10_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R10_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R10_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R10_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R10_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R10_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R10_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R10_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R10_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R10_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R10_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R10_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R10_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R10_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R10_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R10_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R10_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R10_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR11Strt + */ +#define XFPD_XMPU_CFG_R11_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001B0UL ) +#define XFPD_XMPU_CFG_R11_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R11_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R11_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R11_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R11_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR11End + */ +#define XFPD_XMPU_CFG_R11_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001B4UL ) +#define XFPD_XMPU_CFG_R11_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R11_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R11_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R11_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R11_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR11Mstr + */ +#define XFPD_XMPU_CFG_R11_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001B8UL ) +#define XFPD_XMPU_CFG_R11_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R11_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R11_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R11_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R11_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R11_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R11_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R11_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R11_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR11 + */ +#define XFPD_XMPU_CFG_R11 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001BCUL ) +#define XFPD_XMPU_CFG_R11_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R11_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R11_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R11_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R11_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R11_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R11_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R11_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R11_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R11_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R11_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R11_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R11_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R11_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R11_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R11_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R11_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R11_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R11_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R11_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R11_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR12Strt + */ +#define XFPD_XMPU_CFG_R12_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001C0UL ) +#define XFPD_XMPU_CFG_R12_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R12_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R12_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R12_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R12_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR12End + */ +#define XFPD_XMPU_CFG_R12_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001C4UL ) +#define XFPD_XMPU_CFG_R12_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R12_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R12_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R12_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R12_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR12Mstr + */ +#define XFPD_XMPU_CFG_R12_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001C8UL ) +#define XFPD_XMPU_CFG_R12_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R12_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R12_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R12_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R12_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R12_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R12_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R12_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R12_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR12 + */ +#define XFPD_XMPU_CFG_R12 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001CCUL ) +#define XFPD_XMPU_CFG_R12_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R12_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R12_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R12_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R12_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R12_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R12_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R12_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R12_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R12_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R12_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R12_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R12_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R12_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R12_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R12_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R12_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R12_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R12_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R12_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R12_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR13Strt + */ +#define XFPD_XMPU_CFG_R13_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001D0UL ) +#define XFPD_XMPU_CFG_R13_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R13_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R13_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R13_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R13_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR13End + */ +#define XFPD_XMPU_CFG_R13_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001D4UL ) +#define XFPD_XMPU_CFG_R13_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R13_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R13_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R13_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R13_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR13Mstr + */ +#define XFPD_XMPU_CFG_R13_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001D8UL ) +#define XFPD_XMPU_CFG_R13_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R13_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R13_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R13_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R13_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R13_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R13_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R13_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R13_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR13 + */ +#define XFPD_XMPU_CFG_R13 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001DCUL ) +#define XFPD_XMPU_CFG_R13_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R13_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R13_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R13_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R13_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R13_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R13_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R13_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R13_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R13_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R13_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R13_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R13_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R13_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R13_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R13_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R13_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R13_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R13_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R13_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R13_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR14Strt + */ +#define XFPD_XMPU_CFG_R14_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001E0UL ) +#define XFPD_XMPU_CFG_R14_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R14_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R14_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R14_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R14_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR14End + */ +#define XFPD_XMPU_CFG_R14_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001E4UL ) +#define XFPD_XMPU_CFG_R14_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R14_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R14_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R14_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R14_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR14Mstr + */ +#define XFPD_XMPU_CFG_R14_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001E8UL ) +#define XFPD_XMPU_CFG_R14_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R14_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R14_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R14_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R14_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R14_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R14_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R14_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R14_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR14 + */ +#define XFPD_XMPU_CFG_R14 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001ECUL ) +#define XFPD_XMPU_CFG_R14_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R14_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R14_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R14_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R14_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R14_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R14_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R14_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R14_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R14_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R14_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R14_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R14_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R14_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R14_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R14_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R14_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R14_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R14_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R14_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R14_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR15Strt + */ +#define XFPD_XMPU_CFG_R15_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001F0UL ) +#define XFPD_XMPU_CFG_R15_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R15_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R15_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R15_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R15_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR15End + */ +#define XFPD_XMPU_CFG_R15_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001F4UL ) +#define XFPD_XMPU_CFG_R15_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R15_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R15_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R15_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R15_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR15Mstr + */ +#define XFPD_XMPU_CFG_R15_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001F8UL ) +#define XFPD_XMPU_CFG_R15_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R15_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R15_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R15_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R15_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R15_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R15_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R15_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R15_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR15 + */ +#define XFPD_XMPU_CFG_R15 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001FCUL ) +#define XFPD_XMPU_CFG_R15_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R15_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R15_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R15_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R15_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R15_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R15_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R15_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R15_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R15_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R15_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R15_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R15_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R15_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R15_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R15_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R15_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R15_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R15_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R15_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R15_EN_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XFPD_XMPU_CFG_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xfpd_xmpu_sink.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xfpd_xmpu_sink.h new file mode 100644 index 0000000..39172f1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xfpd_xmpu_sink.h
@@ -0,0 +1,81 @@ +/* ### HEADER ### */ + +#ifndef __XFPD_XMPU_SINK_H__ +#define __XFPD_XMPU_SINK_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XfpdXmpuSink Base Address + */ +#define XFPD_XMPU_SINK_BASEADDR 0xFD4F0000UL + +/** + * Register: XfpdXmpuSinkErrSts + */ +#define XFPD_XMPU_SINK_ERR_STS ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF00UL ) +#define XFPD_XMPU_SINK_ERR_STS_RSTVAL 0x00000000UL + +#define XFPD_XMPU_SINK_ERR_STS_RDWR_SHIFT 31UL +#define XFPD_XMPU_SINK_ERR_STS_RDWR_WIDTH 1UL +#define XFPD_XMPU_SINK_ERR_STS_RDWR_MASK 0x80000000UL +#define XFPD_XMPU_SINK_ERR_STS_RDWR_DEFVAL 0x0UL + +#define XFPD_XMPU_SINK_ERR_STS_ADDR_SHIFT 0UL +#define XFPD_XMPU_SINK_ERR_STS_ADDR_WIDTH 12UL +#define XFPD_XMPU_SINK_ERR_STS_ADDR_MASK 0x00000fffUL +#define XFPD_XMPU_SINK_ERR_STS_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuSinkIsr + */ +#define XFPD_XMPU_SINK_ISR ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF10UL ) +#define XFPD_XMPU_SINK_ISR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_SINK_ISRADDRDECDERR_SHIFT 0UL +#define XFPD_XMPU_SINK_ISRADDRDECDERR_WIDTH 1UL +#define XFPD_XMPU_SINK_ISRADDRDECDERR_MASK 0x00000001UL +#define XFPD_XMPU_SINK_ISRADDRDECDERR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuSinkImr + */ +#define XFPD_XMPU_SINK_IMR ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF14UL ) +#define XFPD_XMPU_SINK_IMR_RSTVAL 0x00000001UL + +#define XFPD_XMPU_SINK_IMRADDRDECDERR_SHIFT 0UL +#define XFPD_XMPU_SINK_IMRADDRDECDERR_WIDTH 1UL +#define XFPD_XMPU_SINK_IMRADDRDECDERR_MASK 0x00000001UL +#define XFPD_XMPU_SINK_IMRADDRDECDERR_DEFVAL 0x1UL + +/** + * Register: XfpdXmpuSinkIer + */ +#define XFPD_XMPU_SINK_IER ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF18UL ) +#define XFPD_XMPU_SINK_IER_RSTVAL 0x00000000UL + +#define XFPD_XMPU_SINK_IERADDRDECDERR_SHIFT 0UL +#define XFPD_XMPU_SINK_IERADDRDECDERR_WIDTH 1UL +#define XFPD_XMPU_SINK_IERADDRDECDERR_MASK 0x00000001UL +#define XFPD_XMPU_SINK_IERADDRDECDERR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuSinkIdr + */ +#define XFPD_XMPU_SINK_IDR ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF1CUL ) +#define XFPD_XMPU_SINK_IDR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_SINK_IDRADDRDECDERR_SHIFT 0UL +#define XFPD_XMPU_SINK_IDRADDRDECDERR_WIDTH 1UL +#define XFPD_XMPU_SINK_IDRADDRDECDERR_MASK 0x00000001UL +#define XFPD_XMPU_SINK_IDRADDRDECDERR_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XFPD_XMPU_SINK_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xiou_secure_slcr.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xiou_secure_slcr.h new file mode 100644 index 0000000..cb4ad49 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xiou_secure_slcr.h
@@ -0,0 +1,174 @@ +/* ### HEADER ### */ + +#ifndef __XIOU_SECURE_SLCR_H__ +#define __XIOU_SECURE_SLCR_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XiouSecureSlcr Base Address + */ +#define XIOU_SECURE_SLCR_BASEADDR 0xFF240000UL + +/** + * Register: XiouSecSlcrAxiWprtcn + */ +#define XIOU_SEC_SLCR_AXI_WPRTCN ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000000UL ) +#define XIOU_SEC_SLCR_AXI_WPRTCN_RSTVAL 0x00000000UL + +#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_SHIFT 25UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_MASK 0x0e000000UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_SHIFT 22UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_MASK 0x01c00000UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_SHIFT 19UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_MASK 0x00380000UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_SHIFT 16UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_MASK 0x00070000UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT 9UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK 0x00000e00UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT 6UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK 0x000001c0UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT 3UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK 0x00000038UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT 0UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK 0x00000007UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL 0x0UL + +/** + * Register: XiouSecSlcrAxiRprtcn + */ +#define XIOU_SEC_SLCR_AXI_RPRTCN ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000004UL ) +#define XIOU_SEC_SLCR_AXI_RPRTCN_RSTVAL 0x00000000UL + +#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_SHIFT 22UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_MASK 0x01c00000UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_SHIFT 19UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_MASK 0x00380000UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_SHIFT 16UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_MASK 0x00070000UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT 9UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK 0x00000e00UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT 6UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK 0x000001c0UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT 3UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK 0x00000038UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT 0UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK 0x00000007UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL 0x0UL + +/** + * Register: XiouSecSlcrCtrl + */ +#define XIOU_SEC_SLCR_CTRL ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000040UL ) +#define XIOU_SEC_SLCR_CTRL_RSTVAL 0x00000000UL + +#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_SHIFT 0UL +#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_WIDTH 1UL +#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_MASK 0x00000001UL +#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_DEFVAL 0x0UL + +/** + * Register: XiouSecSlcrIsr + */ +#define XIOU_SEC_SLCR_ISR ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000044UL ) +#define XIOU_SEC_SLCR_ISR_RSTVAL 0x00000000UL + +#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_SHIFT 0UL +#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_WIDTH 1UL +#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XiouSecSlcrImr + */ +#define XIOU_SEC_SLCR_IMR ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000048UL ) +#define XIOU_SEC_SLCR_IMR_RSTVAL 0x00000001UL + +#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_SHIFT 0UL +#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_WIDTH 1UL +#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL + +/** + * Register: XiouSecSlcrIer + */ +#define XIOU_SEC_SLCR_IER ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x0000004CUL ) +#define XIOU_SEC_SLCR_IER_RSTVAL 0x00000000UL + +#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_SHIFT 0UL +#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_WIDTH 1UL +#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_MASK 0x00000001UL +#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XiouSecSlcrIdr + */ +#define XIOU_SEC_SLCR_IDR ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000050UL ) +#define XIOU_SEC_SLCR_IDR_RSTVAL 0x00000000UL + +#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_SHIFT 0UL +#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_WIDTH 1UL +#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XiouSecSlcrItr + */ +#define XIOU_SEC_SLCR_ITR ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000054UL ) +#define XIOU_SEC_SLCR_ITR_RSTVAL 0x00000000UL + +#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_SHIFT 0UL +#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_WIDTH 1UL +#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XIOU_SECURE_SLCR_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xiou_slcr.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xiou_slcr.h new file mode 100644 index 0000000..c53954c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xiou_slcr.h
@@ -0,0 +1,4029 @@ +/* ### HEADER ### */ + +#ifndef __XIOU_SLCR_H__ +#define __XIOU_SLCR_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XiouSlcr Base Address + */ +#define XIOU_SLCR_BASEADDR 0xFF180000UL + +/** + * Register: XiouSlcrMioPin0 + */ +#define XIOU_SLCR_MIO_PIN_0 ( ( XIOU_SLCR_BASEADDR ) + 0x00000000UL ) +#define XIOU_SLCR_MIO_PIN_0_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_0_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_0_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_0_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_0_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_0_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_0_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_0_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_0_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin1 + */ +#define XIOU_SLCR_MIO_PIN_1 ( ( XIOU_SLCR_BASEADDR ) + 0x00000004UL ) +#define XIOU_SLCR_MIO_PIN_1_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_1_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_1_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_1_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_1_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_1_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_1_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_1_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_1_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin2 + */ +#define XIOU_SLCR_MIO_PIN_2 ( ( XIOU_SLCR_BASEADDR ) + 0x00000008UL ) +#define XIOU_SLCR_MIO_PIN_2_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_2_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_2_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_2_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_2_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_2_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_2_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_2_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_2_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin3 + */ +#define XIOU_SLCR_MIO_PIN_3 ( ( XIOU_SLCR_BASEADDR ) + 0x0000000CUL ) +#define XIOU_SLCR_MIO_PIN_3_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_3_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_3_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_3_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_3_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_3_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_3_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_3_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_3_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin4 + */ +#define XIOU_SLCR_MIO_PIN_4 ( ( XIOU_SLCR_BASEADDR ) + 0x00000010UL ) +#define XIOU_SLCR_MIO_PIN_4_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_4_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_4_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_4_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_4_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_4_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_4_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_4_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_4_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin5 + */ +#define XIOU_SLCR_MIO_PIN_5 ( ( XIOU_SLCR_BASEADDR ) + 0x00000014UL ) +#define XIOU_SLCR_MIO_PIN_5_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_5_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_5_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_5_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_5_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_5_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_5_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_5_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_5_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin6 + */ +#define XIOU_SLCR_MIO_PIN_6 ( ( XIOU_SLCR_BASEADDR ) + 0x00000018UL ) +#define XIOU_SLCR_MIO_PIN_6_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_6_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_6_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_6_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_6_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_6_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_6_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_6_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_6_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin7 + */ +#define XIOU_SLCR_MIO_PIN_7 ( ( XIOU_SLCR_BASEADDR ) + 0x0000001CUL ) +#define XIOU_SLCR_MIO_PIN_7_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_7_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_7_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_7_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_7_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_7_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_7_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_7_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_7_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin8 + */ +#define XIOU_SLCR_MIO_PIN_8 ( ( XIOU_SLCR_BASEADDR ) + 0x00000020UL ) +#define XIOU_SLCR_MIO_PIN_8_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_8_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_8_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_8_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_8_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_8_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_8_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_8_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_8_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin9 + */ +#define XIOU_SLCR_MIO_PIN_9 ( ( XIOU_SLCR_BASEADDR ) + 0x00000024UL ) +#define XIOU_SLCR_MIO_PIN_9_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_9_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_9_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_9_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_9_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_9_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_9_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_9_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_9_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin10 + */ +#define XIOU_SLCR_MIO_PIN_10 ( ( XIOU_SLCR_BASEADDR ) + 0x00000028UL ) +#define XIOU_SLCR_MIO_PIN_10_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_10_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_10_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_10_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_10_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_10_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_10_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_10_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_10_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin11 + */ +#define XIOU_SLCR_MIO_PIN_11 ( ( XIOU_SLCR_BASEADDR ) + 0x0000002CUL ) +#define XIOU_SLCR_MIO_PIN_11_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_11_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_11_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_11_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_11_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_11_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_11_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_11_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_11_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin12 + */ +#define XIOU_SLCR_MIO_PIN_12 ( ( XIOU_SLCR_BASEADDR ) + 0x00000030UL ) +#define XIOU_SLCR_MIO_PIN_12_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_12_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_12_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_12_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_12_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_12_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_12_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_12_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_12_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin13 + */ +#define XIOU_SLCR_MIO_PIN_13 ( ( XIOU_SLCR_BASEADDR ) + 0x00000034UL ) +#define XIOU_SLCR_MIO_PIN_13_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_13_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_13_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_13_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_13_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_13_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_13_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_13_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_13_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin14 + */ +#define XIOU_SLCR_MIO_PIN_14 ( ( XIOU_SLCR_BASEADDR ) + 0x00000038UL ) +#define XIOU_SLCR_MIO_PIN_14_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_14_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_14_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_14_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_14_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_14_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_14_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_14_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_14_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin15 + */ +#define XIOU_SLCR_MIO_PIN_15 ( ( XIOU_SLCR_BASEADDR ) + 0x0000003CUL ) +#define XIOU_SLCR_MIO_PIN_15_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_15_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_15_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_15_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_15_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_15_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_15_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_15_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_15_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin16 + */ +#define XIOU_SLCR_MIO_PIN_16 ( ( XIOU_SLCR_BASEADDR ) + 0x00000040UL ) +#define XIOU_SLCR_MIO_PIN_16_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_16_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_16_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_16_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_16_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_16_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_16_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_16_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_16_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin17 + */ +#define XIOU_SLCR_MIO_PIN_17 ( ( XIOU_SLCR_BASEADDR ) + 0x00000044UL ) +#define XIOU_SLCR_MIO_PIN_17_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_17_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_17_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_17_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_17_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_17_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_17_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_17_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_17_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin18 + */ +#define XIOU_SLCR_MIO_PIN_18 ( ( XIOU_SLCR_BASEADDR ) + 0x00000048UL ) +#define XIOU_SLCR_MIO_PIN_18_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_18_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_18_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_18_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_18_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_18_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_18_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_18_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_18_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin19 + */ +#define XIOU_SLCR_MIO_PIN_19 ( ( XIOU_SLCR_BASEADDR ) + 0x0000004CUL ) +#define XIOU_SLCR_MIO_PIN_19_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_19_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_19_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_19_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_19_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_19_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_19_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_19_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_19_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin20 + */ +#define XIOU_SLCR_MIO_PIN_20 ( ( XIOU_SLCR_BASEADDR ) + 0x00000050UL ) +#define XIOU_SLCR_MIO_PIN_20_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_20_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_20_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_20_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_20_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_20_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_20_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_20_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_20_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin21 + */ +#define XIOU_SLCR_MIO_PIN_21 ( ( XIOU_SLCR_BASEADDR ) + 0x00000054UL ) +#define XIOU_SLCR_MIO_PIN_21_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_21_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_21_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_21_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_21_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_21_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_21_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_21_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_21_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin22 + */ +#define XIOU_SLCR_MIO_PIN_22 ( ( XIOU_SLCR_BASEADDR ) + 0x00000058UL ) +#define XIOU_SLCR_MIO_PIN_22_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_22_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_22_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_22_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_22_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_22_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_22_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_22_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_22_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin23 + */ +#define XIOU_SLCR_MIO_PIN_23 ( ( XIOU_SLCR_BASEADDR ) + 0x0000005CUL ) +#define XIOU_SLCR_MIO_PIN_23_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_23_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_23_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_23_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_23_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_23_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_23_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_23_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_23_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin24 + */ +#define XIOU_SLCR_MIO_PIN_24 ( ( XIOU_SLCR_BASEADDR ) + 0x00000060UL ) +#define XIOU_SLCR_MIO_PIN_24_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_24_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_24_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_24_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_24_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_24_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_24_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_24_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_24_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin25 + */ +#define XIOU_SLCR_MIO_PIN_25 ( ( XIOU_SLCR_BASEADDR ) + 0x00000064UL ) +#define XIOU_SLCR_MIO_PIN_25_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_25_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_25_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_25_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_25_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_25_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_25_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_25_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_25_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin26 + */ +#define XIOU_SLCR_MIO_PIN_26 ( ( XIOU_SLCR_BASEADDR ) + 0x00000068UL ) +#define XIOU_SLCR_MIO_PIN_26_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_26_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_26_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_26_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_26_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_26_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_26_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_26_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_26_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin27 + */ +#define XIOU_SLCR_MIO_PIN_27 ( ( XIOU_SLCR_BASEADDR ) + 0x0000006CUL ) +#define XIOU_SLCR_MIO_PIN_27_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_27_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_27_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_27_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_27_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_27_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_27_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_27_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_27_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin28 + */ +#define XIOU_SLCR_MIO_PIN_28 ( ( XIOU_SLCR_BASEADDR ) + 0x00000070UL ) +#define XIOU_SLCR_MIO_PIN_28_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_28_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_28_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_28_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_28_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_28_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_28_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_28_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_28_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin29 + */ +#define XIOU_SLCR_MIO_PIN_29 ( ( XIOU_SLCR_BASEADDR ) + 0x00000074UL ) +#define XIOU_SLCR_MIO_PIN_29_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_29_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_29_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_29_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_29_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_29_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_29_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_29_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_29_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin30 + */ +#define XIOU_SLCR_MIO_PIN_30 ( ( XIOU_SLCR_BASEADDR ) + 0x00000078UL ) +#define XIOU_SLCR_MIO_PIN_30_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_30_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_30_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_30_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_30_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_30_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_30_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_30_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_30_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin31 + */ +#define XIOU_SLCR_MIO_PIN_31 ( ( XIOU_SLCR_BASEADDR ) + 0x0000007CUL ) +#define XIOU_SLCR_MIO_PIN_31_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_31_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_31_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_31_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_31_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_31_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_31_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_31_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_31_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin32 + */ +#define XIOU_SLCR_MIO_PIN_32 ( ( XIOU_SLCR_BASEADDR ) + 0x00000080UL ) +#define XIOU_SLCR_MIO_PIN_32_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_32_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_32_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_32_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_32_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_32_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_32_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_32_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_32_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin33 + */ +#define XIOU_SLCR_MIO_PIN_33 ( ( XIOU_SLCR_BASEADDR ) + 0x00000084UL ) +#define XIOU_SLCR_MIO_PIN_33_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_33_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_33_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_33_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_33_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_33_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_33_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_33_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_33_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin34 + */ +#define XIOU_SLCR_MIO_PIN_34 ( ( XIOU_SLCR_BASEADDR ) + 0x00000088UL ) +#define XIOU_SLCR_MIO_PIN_34_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_34_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_34_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_34_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_34_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_34_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_34_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_34_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_34_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_34_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_34_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_34_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_34_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin35 + */ +#define XIOU_SLCR_MIO_PIN_35 ( ( XIOU_SLCR_BASEADDR ) + 0x0000008CUL ) +#define XIOU_SLCR_MIO_PIN_35_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_35_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_35_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_35_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_35_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_35_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_35_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_35_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_35_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_35_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_35_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_35_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_35_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin36 + */ +#define XIOU_SLCR_MIO_PIN_36 ( ( XIOU_SLCR_BASEADDR ) + 0x00000090UL ) +#define XIOU_SLCR_MIO_PIN_36_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_36_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_36_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_36_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_36_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_36_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_36_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_36_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_36_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_36_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_36_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_36_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_36_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin37 + */ +#define XIOU_SLCR_MIO_PIN_37 ( ( XIOU_SLCR_BASEADDR ) + 0x00000094UL ) +#define XIOU_SLCR_MIO_PIN_37_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_37_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_37_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_37_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_37_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_37_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_37_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_37_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_37_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_37_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_37_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_37_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_37_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin38 + */ +#define XIOU_SLCR_MIO_PIN_38 ( ( XIOU_SLCR_BASEADDR ) + 0x00000098UL ) +#define XIOU_SLCR_MIO_PIN_38_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_38_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_38_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_38_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_38_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_38_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_38_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_38_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_38_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin39 + */ +#define XIOU_SLCR_MIO_PIN_39 ( ( XIOU_SLCR_BASEADDR ) + 0x0000009CUL ) +#define XIOU_SLCR_MIO_PIN_39_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_39_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_39_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_39_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_39_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_39_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_39_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_39_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_39_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin40 + */ +#define XIOU_SLCR_MIO_PIN_40 ( ( XIOU_SLCR_BASEADDR ) + 0x000000A0UL ) +#define XIOU_SLCR_MIO_PIN_40_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_40_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_40_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_40_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_40_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_40_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_40_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_40_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_40_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin41 + */ +#define XIOU_SLCR_MIO_PIN_41 ( ( XIOU_SLCR_BASEADDR ) + 0x000000A4UL ) +#define XIOU_SLCR_MIO_PIN_41_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_41_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_41_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_41_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_41_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_41_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_41_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_41_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_41_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin42 + */ +#define XIOU_SLCR_MIO_PIN_42 ( ( XIOU_SLCR_BASEADDR ) + 0x000000A8UL ) +#define XIOU_SLCR_MIO_PIN_42_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_42_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_42_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_42_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_42_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_42_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_42_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_42_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_42_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin43 + */ +#define XIOU_SLCR_MIO_PIN_43 ( ( XIOU_SLCR_BASEADDR ) + 0x000000ACUL ) +#define XIOU_SLCR_MIO_PIN_43_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_43_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_43_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_43_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_43_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_43_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_43_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_43_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_43_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin44 + */ +#define XIOU_SLCR_MIO_PIN_44 ( ( XIOU_SLCR_BASEADDR ) + 0x000000B0UL ) +#define XIOU_SLCR_MIO_PIN_44_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_44_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_44_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_44_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_44_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_44_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_44_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_44_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_44_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin45 + */ +#define XIOU_SLCR_MIO_PIN_45 ( ( XIOU_SLCR_BASEADDR ) + 0x000000B4UL ) +#define XIOU_SLCR_MIO_PIN_45_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_45_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_45_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_45_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_45_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_45_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_45_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_45_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_45_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin46 + */ +#define XIOU_SLCR_MIO_PIN_46 ( ( XIOU_SLCR_BASEADDR ) + 0x000000B8UL ) +#define XIOU_SLCR_MIO_PIN_46_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_46_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_46_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_46_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_46_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_46_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_46_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_46_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_46_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin47 + */ +#define XIOU_SLCR_MIO_PIN_47 ( ( XIOU_SLCR_BASEADDR ) + 0x000000BCUL ) +#define XIOU_SLCR_MIO_PIN_47_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_47_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_47_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_47_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_47_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_47_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_47_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_47_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_47_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin48 + */ +#define XIOU_SLCR_MIO_PIN_48 ( ( XIOU_SLCR_BASEADDR ) + 0x000000C0UL ) +#define XIOU_SLCR_MIO_PIN_48_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_48_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_48_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_48_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_48_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_48_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_48_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_48_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_48_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin49 + */ +#define XIOU_SLCR_MIO_PIN_49 ( ( XIOU_SLCR_BASEADDR ) + 0x000000C4UL ) +#define XIOU_SLCR_MIO_PIN_49_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_49_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_49_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_49_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_49_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_49_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_49_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_49_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_49_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin50 + */ +#define XIOU_SLCR_MIO_PIN_50 ( ( XIOU_SLCR_BASEADDR ) + 0x000000C8UL ) +#define XIOU_SLCR_MIO_PIN_50_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_50_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_50_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_50_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_50_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_50_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_50_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_50_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_50_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin51 + */ +#define XIOU_SLCR_MIO_PIN_51 ( ( XIOU_SLCR_BASEADDR ) + 0x000000CCUL ) +#define XIOU_SLCR_MIO_PIN_51_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_51_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_51_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_51_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_51_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_51_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_51_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_51_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_51_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin52 + */ +#define XIOU_SLCR_MIO_PIN_52 ( ( XIOU_SLCR_BASEADDR ) + 0x000000D0UL ) +#define XIOU_SLCR_MIO_PIN_52_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_52_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_52_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_52_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_52_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_52_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_52_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_52_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_52_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin53 + */ +#define XIOU_SLCR_MIO_PIN_53 ( ( XIOU_SLCR_BASEADDR ) + 0x000000D4UL ) +#define XIOU_SLCR_MIO_PIN_53_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_53_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_53_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_53_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_53_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_53_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_53_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_53_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_53_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin54 + */ +#define XIOU_SLCR_MIO_PIN_54 ( ( XIOU_SLCR_BASEADDR ) + 0x000000D8UL ) +#define XIOU_SLCR_MIO_PIN_54_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_54_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_54_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_54_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_54_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_54_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_54_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_54_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_54_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin55 + */ +#define XIOU_SLCR_MIO_PIN_55 ( ( XIOU_SLCR_BASEADDR ) + 0x000000DCUL ) +#define XIOU_SLCR_MIO_PIN_55_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_55_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_55_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_55_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_55_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_55_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_55_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_55_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_55_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin56 + */ +#define XIOU_SLCR_MIO_PIN_56 ( ( XIOU_SLCR_BASEADDR ) + 0x000000E0UL ) +#define XIOU_SLCR_MIO_PIN_56_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_56_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_56_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_56_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_56_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_56_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_56_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_56_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_56_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin57 + */ +#define XIOU_SLCR_MIO_PIN_57 ( ( XIOU_SLCR_BASEADDR ) + 0x000000E4UL ) +#define XIOU_SLCR_MIO_PIN_57_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_57_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_57_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_57_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_57_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_57_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_57_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_57_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_57_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin58 + */ +#define XIOU_SLCR_MIO_PIN_58 ( ( XIOU_SLCR_BASEADDR ) + 0x000000E8UL ) +#define XIOU_SLCR_MIO_PIN_58_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_58_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_58_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_58_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_58_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_58_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_58_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_58_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_58_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin59 + */ +#define XIOU_SLCR_MIO_PIN_59 ( ( XIOU_SLCR_BASEADDR ) + 0x000000ECUL ) +#define XIOU_SLCR_MIO_PIN_59_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_59_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_59_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_59_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_59_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_59_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_59_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_59_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_59_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin60 + */ +#define XIOU_SLCR_MIO_PIN_60 ( ( XIOU_SLCR_BASEADDR ) + 0x000000F0UL ) +#define XIOU_SLCR_MIO_PIN_60_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_60_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_60_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_60_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_60_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_60_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_60_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_60_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_60_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin61 + */ +#define XIOU_SLCR_MIO_PIN_61 ( ( XIOU_SLCR_BASEADDR ) + 0x000000F4UL ) +#define XIOU_SLCR_MIO_PIN_61_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_61_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_61_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_61_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_61_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_61_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_61_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_61_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_61_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin62 + */ +#define XIOU_SLCR_MIO_PIN_62 ( ( XIOU_SLCR_BASEADDR ) + 0x000000F8UL ) +#define XIOU_SLCR_MIO_PIN_62_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_62_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_62_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_62_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_62_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_62_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_62_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_62_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_62_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin63 + */ +#define XIOU_SLCR_MIO_PIN_63 ( ( XIOU_SLCR_BASEADDR ) + 0x000000FCUL ) +#define XIOU_SLCR_MIO_PIN_63_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_63_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_63_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_63_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_63_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_63_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_63_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_63_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_63_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin64 + */ +#define XIOU_SLCR_MIO_PIN_64 ( ( XIOU_SLCR_BASEADDR ) + 0x00000100UL ) +#define XIOU_SLCR_MIO_PIN_64_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_64_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_64_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_64_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_64_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_64_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_64_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_64_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_64_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin65 + */ +#define XIOU_SLCR_MIO_PIN_65 ( ( XIOU_SLCR_BASEADDR ) + 0x00000104UL ) +#define XIOU_SLCR_MIO_PIN_65_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_65_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_65_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_65_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_65_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_65_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_65_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_65_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_65_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin66 + */ +#define XIOU_SLCR_MIO_PIN_66 ( ( XIOU_SLCR_BASEADDR ) + 0x00000108UL ) +#define XIOU_SLCR_MIO_PIN_66_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_66_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_66_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_66_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_66_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_66_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_66_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_66_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_66_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin67 + */ +#define XIOU_SLCR_MIO_PIN_67 ( ( XIOU_SLCR_BASEADDR ) + 0x0000010CUL ) +#define XIOU_SLCR_MIO_PIN_67_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_67_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_67_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_67_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_67_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_67_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_67_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_67_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_67_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin68 + */ +#define XIOU_SLCR_MIO_PIN_68 ( ( XIOU_SLCR_BASEADDR ) + 0x00000110UL ) +#define XIOU_SLCR_MIO_PIN_68_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_68_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_68_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_68_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_68_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_68_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_68_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_68_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_68_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin69 + */ +#define XIOU_SLCR_MIO_PIN_69 ( ( XIOU_SLCR_BASEADDR ) + 0x00000114UL ) +#define XIOU_SLCR_MIO_PIN_69_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_69_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_69_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_69_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_69_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_69_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_69_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_69_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_69_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin70 + */ +#define XIOU_SLCR_MIO_PIN_70 ( ( XIOU_SLCR_BASEADDR ) + 0x00000118UL ) +#define XIOU_SLCR_MIO_PIN_70_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_70_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_70_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_70_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_70_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_70_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_70_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_70_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_70_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin71 + */ +#define XIOU_SLCR_MIO_PIN_71 ( ( XIOU_SLCR_BASEADDR ) + 0x0000011CUL ) +#define XIOU_SLCR_MIO_PIN_71_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_71_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_71_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_71_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_71_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_71_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_71_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_71_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_71_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin72 + */ +#define XIOU_SLCR_MIO_PIN_72 ( ( XIOU_SLCR_BASEADDR ) + 0x00000120UL ) +#define XIOU_SLCR_MIO_PIN_72_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_72_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_72_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_72_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_72_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_72_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_72_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_72_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_72_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin73 + */ +#define XIOU_SLCR_MIO_PIN_73 ( ( XIOU_SLCR_BASEADDR ) + 0x00000124UL ) +#define XIOU_SLCR_MIO_PIN_73_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_73_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_73_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_73_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_73_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_73_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_73_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_73_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_73_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin74 + */ +#define XIOU_SLCR_MIO_PIN_74 ( ( XIOU_SLCR_BASEADDR ) + 0x00000128UL ) +#define XIOU_SLCR_MIO_PIN_74_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_74_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_74_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_74_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_74_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_74_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_74_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_74_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_74_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin75 + */ +#define XIOU_SLCR_MIO_PIN_75 ( ( XIOU_SLCR_BASEADDR ) + 0x0000012CUL ) +#define XIOU_SLCR_MIO_PIN_75_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_75_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_75_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_75_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_75_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_75_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_75_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_75_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_75_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin76 + */ +#define XIOU_SLCR_MIO_PIN_76 ( ( XIOU_SLCR_BASEADDR ) + 0x00000130UL ) +#define XIOU_SLCR_MIO_PIN_76_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_76_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_76_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_76_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_76_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_76_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_76_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_76_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_76_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin77 + */ +#define XIOU_SLCR_MIO_PIN_77 ( ( XIOU_SLCR_BASEADDR ) + 0x00000134UL ) +#define XIOU_SLCR_MIO_PIN_77_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_77_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_77_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_77_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_77_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_77_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_77_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_77_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_77_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank0Ctrl0 + */ +#define XIOU_SLCR_BANK0_CTRL0 ( ( XIOU_SLCR_BASEADDR ) + 0x00000138UL ) +#define XIOU_SLCR_BANK0_CTRL0_RSTVAL 0x03ffffffUL + +#define XIOU_SLCR_BANK0_CTRL0_DRIVE0_SHIFT 0UL +#define XIOU_SLCR_BANK0_CTRL0_DRIVE0_WIDTH 26UL +#define XIOU_SLCR_BANK0_CTRL0_DRIVE0_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK0_CTRL0_DRIVE0_DEFVAL 0x3ffffffUL + +/** + * Register: XiouSlcrBank0Ctrl1 + */ +#define XIOU_SLCR_BANK0_CTRL1 ( ( XIOU_SLCR_BASEADDR ) + 0x0000013CUL ) +#define XIOU_SLCR_BANK0_CTRL1_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK0_CTRL1_DRIVE1_SHIFT 0UL +#define XIOU_SLCR_BANK0_CTRL1_DRIVE1_WIDTH 26UL +#define XIOU_SLCR_BANK0_CTRL1_DRIVE1_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK0_CTRL1_DRIVE1_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank0Ctrl3 + */ +#define XIOU_SLCR_BANK0_CTRL3 ( ( XIOU_SLCR_BASEADDR ) + 0x00000140UL ) +#define XIOU_SLCR_BANK0_CTRL3_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_SHIFT 0UL +#define XIOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_WIDTH 26UL +#define XIOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank0Ctrl4 + */ +#define XIOU_SLCR_BANK0_CTRL4 ( ( XIOU_SLCR_BASEADDR ) + 0x00000144UL ) +#define XIOU_SLCR_BANK0_CTRL4_RSTVAL 0x03ffffffUL + +#define XIOU_SLCR_BANK0_CTRL4_PULLHILO_N_SHIFT 0UL +#define XIOU_SLCR_BANK0_CTRL4_PULLHILO_N_WIDTH 26UL +#define XIOU_SLCR_BANK0_CTRL4_PULLHILO_N_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK0_CTRL4_PULLHILO_N_DEFVAL 0x3ffffffUL + +/** + * Register: XiouSlcrBank0Ctrl5 + */ +#define XIOU_SLCR_BANK0_CTRL5 ( ( XIOU_SLCR_BASEADDR ) + 0x00000148UL ) +#define XIOU_SLCR_BANK0_CTRL5_RSTVAL 0x03ffffffUL + +#define XIOU_SLCR_BANK0_CTRL5_PULL_EN_SHIFT 0UL +#define XIOU_SLCR_BANK0_CTRL5_PULL_EN_WIDTH 26UL +#define XIOU_SLCR_BANK0_CTRL5_PULL_EN_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK0_CTRL5_PULL_EN_DEFVAL 0x3ffffffUL + +/** + * Register: XiouSlcrBank0Ctrl6 + */ +#define XIOU_SLCR_BANK0_CTRL6 ( ( XIOU_SLCR_BASEADDR ) + 0x0000014CUL ) +#define XIOU_SLCR_BANK0_CTRL6_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_SHIFT 0UL +#define XIOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_WIDTH 26UL +#define XIOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank0Sts + */ +#define XIOU_SLCR_BANK0_STS ( ( XIOU_SLCR_BASEADDR ) + 0x00000150UL ) +#define XIOU_SLCR_BANK0_STS_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK0_STS_VOLTAGE_MODE_SHIFT 0UL +#define XIOU_SLCR_BANK0_STS_VOLTAGE_MODE_WIDTH 1UL +#define XIOU_SLCR_BANK0_STS_VOLTAGE_MODE_MASK 0x00000001UL +#define XIOU_SLCR_BANK0_STS_VOLTAGE_MODE_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank1Ctrl0 + */ +#define XIOU_SLCR_BANK1_CTRL0 ( ( XIOU_SLCR_BASEADDR ) + 0x00000154UL ) +#define XIOU_SLCR_BANK1_CTRL0_RSTVAL 0x03ffffffUL + +#define XIOU_SLCR_BANK1_CTRL0_DRIVE0_SHIFT 0UL +#define XIOU_SLCR_BANK1_CTRL0_DRIVE0_WIDTH 26UL +#define XIOU_SLCR_BANK1_CTRL0_DRIVE0_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK1_CTRL0_DRIVE0_DEFVAL 0x3ffffffUL + +/** + * Register: XiouSlcrBank1Ctrl1 + */ +#define XIOU_SLCR_BANK1_CTRL1 ( ( XIOU_SLCR_BASEADDR ) + 0x00000158UL ) +#define XIOU_SLCR_BANK1_CTRL1_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK1_CTRL1_DRIVE1_SHIFT 0UL +#define XIOU_SLCR_BANK1_CTRL1_DRIVE1_WIDTH 26UL +#define XIOU_SLCR_BANK1_CTRL1_DRIVE1_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK1_CTRL1_DRIVE1_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank1Ctrl3 + */ +#define XIOU_SLCR_BANK1_CTRL3 ( ( XIOU_SLCR_BASEADDR ) + 0x0000015CUL ) +#define XIOU_SLCR_BANK1_CTRL3_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_SHIFT 0UL +#define XIOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_WIDTH 26UL +#define XIOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank1Ctrl4 + */ +#define XIOU_SLCR_BANK1_CTRL4 ( ( XIOU_SLCR_BASEADDR ) + 0x00000160UL ) +#define XIOU_SLCR_BANK1_CTRL4_RSTVAL 0x03ffffffUL + +#define XIOU_SLCR_BANK1_CTRL4_PULLHILO_N_SHIFT 0UL +#define XIOU_SLCR_BANK1_CTRL4_PULLHILO_N_WIDTH 26UL +#define XIOU_SLCR_BANK1_CTRL4_PULLHILO_N_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK1_CTRL4_PULLHILO_N_DEFVAL 0x3ffffffUL + +/** + * Register: XiouSlcrBank1Ctrl5 + */ +#define XIOU_SLCR_BANK1_CTRL5 ( ( XIOU_SLCR_BASEADDR ) + 0x00000164UL ) +#define XIOU_SLCR_BANK1_CTRL5_RSTVAL 0x03ffffffUL + +#define XIOU_SLCR_BANK1_CTRL5_PULL_EN_SHIFT 0UL +#define XIOU_SLCR_BANK1_CTRL5_PULL_EN_WIDTH 26UL +#define XIOU_SLCR_BANK1_CTRL5_PULL_EN_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK1_CTRL5_PULL_EN_DEFVAL 0x3ffffffUL + +/** + * Register: XiouSlcrBank1Ctrl6 + */ +#define XIOU_SLCR_BANK1_CTRL6 ( ( XIOU_SLCR_BASEADDR ) + 0x00000168UL ) +#define XIOU_SLCR_BANK1_CTRL6_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_SHIFT 0UL +#define XIOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_WIDTH 26UL +#define XIOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank1Sts + */ +#define XIOU_SLCR_BANK1_STS ( ( XIOU_SLCR_BASEADDR ) + 0x0000016CUL ) +#define XIOU_SLCR_BANK1_STS_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK1_STS_VOLTAGE_MODE_SHIFT 0UL +#define XIOU_SLCR_BANK1_STS_VOLTAGE_MODE_WIDTH 1UL +#define XIOU_SLCR_BANK1_STS_VOLTAGE_MODE_MASK 0x00000001UL +#define XIOU_SLCR_BANK1_STS_VOLTAGE_MODE_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank2Ctrl0 + */ +#define XIOU_SLCR_BANK2_CTRL0 ( ( XIOU_SLCR_BASEADDR ) + 0x00000170UL ) +#define XIOU_SLCR_BANK2_CTRL0_RSTVAL 0x03ffffffUL + +#define XIOU_SLCR_BANK2_CTRL0_DRIVE0_SHIFT 0UL +#define XIOU_SLCR_BANK2_CTRL0_DRIVE0_WIDTH 26UL +#define XIOU_SLCR_BANK2_CTRL0_DRIVE0_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK2_CTRL0_DRIVE0_DEFVAL 0x3ffffffUL + +/** + * Register: XiouSlcrBank2Ctrl1 + */ +#define XIOU_SLCR_BANK2_CTRL1 ( ( XIOU_SLCR_BASEADDR ) + 0x00000174UL ) +#define XIOU_SLCR_BANK2_CTRL1_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK2_CTRL1_DRIVE1_SHIFT 0UL +#define XIOU_SLCR_BANK2_CTRL1_DRIVE1_WIDTH 26UL +#define XIOU_SLCR_BANK2_CTRL1_DRIVE1_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK2_CTRL1_DRIVE1_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank2Ctrl3 + */ +#define XIOU_SLCR_BANK2_CTRL3 ( ( XIOU_SLCR_BASEADDR ) + 0x00000178UL ) +#define XIOU_SLCR_BANK2_CTRL3_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_SHIFT 0UL +#define XIOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_WIDTH 26UL +#define XIOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank2Ctrl4 + */ +#define XIOU_SLCR_BANK2_CTRL4 ( ( XIOU_SLCR_BASEADDR ) + 0x0000017CUL ) +#define XIOU_SLCR_BANK2_CTRL4_RSTVAL 0x03ffffffUL + +#define XIOU_SLCR_BANK2_CTRL4_PULLHILO_N_SHIFT 0UL +#define XIOU_SLCR_BANK2_CTRL4_PULLHILO_N_WIDTH 26UL +#define XIOU_SLCR_BANK2_CTRL4_PULLHILO_N_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK2_CTRL4_PULLHILO_N_DEFVAL 0x3ffffffUL + +/** + * Register: XiouSlcrBank2Ctrl5 + */ +#define XIOU_SLCR_BANK2_CTRL5 ( ( XIOU_SLCR_BASEADDR ) + 0x00000180UL ) +#define XIOU_SLCR_BANK2_CTRL5_RSTVAL 0x03ffffffUL + +#define XIOU_SLCR_BANK2_CTRL5_PULL_EN_SHIFT 0UL +#define XIOU_SLCR_BANK2_CTRL5_PULL_EN_WIDTH 26UL +#define XIOU_SLCR_BANK2_CTRL5_PULL_EN_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK2_CTRL5_PULL_EN_DEFVAL 0x3ffffffUL + +/** + * Register: XiouSlcrBank2Ctrl6 + */ +#define XIOU_SLCR_BANK2_CTRL6 ( ( XIOU_SLCR_BASEADDR ) + 0x00000184UL ) +#define XIOU_SLCR_BANK2_CTRL6_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_SHIFT 0UL +#define XIOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_WIDTH 26UL +#define XIOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank2Sts + */ +#define XIOU_SLCR_BANK2_STS ( ( XIOU_SLCR_BASEADDR ) + 0x00000188UL ) +#define XIOU_SLCR_BANK2_STS_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK2_STS_VOLTAGE_MODE_SHIFT 0UL +#define XIOU_SLCR_BANK2_STS_VOLTAGE_MODE_WIDTH 1UL +#define XIOU_SLCR_BANK2_STS_VOLTAGE_MODE_MASK 0x00000001UL +#define XIOU_SLCR_BANK2_STS_VOLTAGE_MODE_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioLpbck + */ +#define XIOU_SLCR_MIO_LPBCK ( ( XIOU_SLCR_BASEADDR ) + 0x00000200UL ) +#define XIOU_SLCR_MIO_LPBCK_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_LPBCK_XI2CPS_LOOP_SHIFT 3UL +#define XIOU_SLCR_MIO_LPBCK_XI2CPS_LOOP_WIDTH 1UL +#define XIOU_SLCR_MIO_LPBCK_XI2CPS_LOOP_MASK 0x00000008UL +#define XIOU_SLCR_MIO_LPBCK_XI2CPS_LOOP_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_LPBCK_CAN0_LOOP_CAN1_SHIFT 2UL +#define XIOU_SLCR_MIO_LPBCK_CAN0_LOOP_CAN1_WIDTH 1UL +#define XIOU_SLCR_MIO_LPBCK_CAN0_LOOP_CAN1_MASK 0x00000004UL +#define XIOU_SLCR_MIO_LPBCK_CAN0_LOOP_CAN1_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_LPBCK_UA0_LOOP_UA1_SHIFT 1UL +#define XIOU_SLCR_MIO_LPBCK_UA0_LOOP_UA1_WIDTH 1UL +#define XIOU_SLCR_MIO_LPBCK_UA0_LOOP_UA1_MASK 0x00000002UL +#define XIOU_SLCR_MIO_LPBCK_UA0_LOOP_UA1_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_LPBCK_XSPIPS_LOOP_SHIFT 0UL +#define XIOU_SLCR_MIO_LPBCK_XSPIPS_LOOP_WIDTH 1UL +#define XIOU_SLCR_MIO_LPBCK_XSPIPS_LOOP_MASK 0x00000001UL +#define XIOU_SLCR_MIO_LPBCK_XSPIPS_LOOP_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioMstTri0 + */ +#define XIOU_SLCR_MIO_MST_TRI0 ( ( XIOU_SLCR_BASEADDR ) + 0x00000204UL ) +#define XIOU_SLCR_MIO_MST_TRI0_RSTVAL 0xffffffffUL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT 31UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK 0x80000000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT 30UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK 0x40000000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT 29UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK 0x20000000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT 28UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK 0x10000000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT 27UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK 0x08000000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT 26UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK 0x04000000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT 25UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK 0x02000000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT 24UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK 0x01000000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT 23UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK 0x00800000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT 22UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK 0x00400000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT 21UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK 0x00200000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT 20UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK 0x00100000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT 19UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK 0x00080000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT 18UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK 0x00040000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT 17UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK 0x00020000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT 16UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK 0x00010000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT 15UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK 0x00008000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT 14UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK 0x00004000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT 13UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK 0x00002000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT 12UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK 0x00001000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT 11UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK 0x00000800UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT 10UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK 0x00000400UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT 9UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK 0x00000200UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT 8UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK 0x00000100UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT 7UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK 0x00000080UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT 6UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK 0x00000040UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT 5UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK 0x00000020UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT 4UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK 0x00000010UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT 3UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK 0x00000008UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT 2UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK 0x00000004UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK 0x00000002UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT 0UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK 0x00000001UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL 0x1UL + +/** + * Register: XiouSlcrMioMstTri1 + */ +#define XIOU_SLCR_MIO_MST_TRI1 ( ( XIOU_SLCR_BASEADDR ) + 0x00000208UL ) +#define XIOU_SLCR_MIO_MST_TRI1_RSTVAL 0xffffffffUL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT 31UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK 0x80000000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT 30UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK 0x40000000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT 29UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK 0x20000000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT 28UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK 0x10000000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT 27UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK 0x08000000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT 26UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK 0x04000000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT 25UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK 0x02000000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT 24UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK 0x01000000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT 23UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK 0x00800000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT 22UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK 0x00400000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT 21UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK 0x00200000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT 20UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK 0x00100000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT 19UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK 0x00080000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT 18UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK 0x00040000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT 17UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK 0x00020000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT 16UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK 0x00010000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT 15UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK 0x00008000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT 14UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK 0x00004000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT 13UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK 0x00002000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT 12UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK 0x00001000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT 11UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK 0x00000800UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT 10UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK 0x00000400UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT 9UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK 0x00000200UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT 8UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK 0x00000100UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT 7UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK 0x00000080UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT 6UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK 0x00000040UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT 5UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK 0x00000020UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT 4UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK 0x00000010UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT 3UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK 0x00000008UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT 2UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK 0x00000004UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK 0x00000002UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT 0UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK 0x00000001UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL 0x1UL + +/** + * Register: XiouSlcrMioMstTri2 + */ +#define XIOU_SLCR_MIO_MST_TRI2 ( ( XIOU_SLCR_BASEADDR ) + 0x0000020CUL ) +#define XIOU_SLCR_MIO_MST_TRI2_RSTVAL 0x00003fffUL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT 13UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK 0x00002000UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT 12UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK 0x00001000UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT 11UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK 0x00000800UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT 10UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK 0x00000400UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT 9UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK 0x00000200UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT 8UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK 0x00000100UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT 7UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK 0x00000080UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT 6UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK 0x00000040UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT 5UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK 0x00000020UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT 4UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK 0x00000010UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT 3UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK 0x00000008UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT 2UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK 0x00000004UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK 0x00000002UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT 0UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK 0x00000001UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL 0x1UL + +/** + * Register: XiouSlcrWdtClkSel + */ +#define XIOU_SLCR_WDT_CLK_SEL ( ( XIOU_SLCR_BASEADDR ) + 0x00000300UL ) +#define XIOU_SLCR_WDT_CLK_SEL_RSTVAL 0x00000000UL + +#define XIOU_SLCR_WDT_CLK_SEL_SHIFT 0UL +#define XIOU_SLCR_WDT_CLK_SEL_WIDTH 1UL +#define XIOU_SLCR_WDT_CLK_SEL_MASK 0x00000001UL +#define XIOU_SLCR_WDT_CLK_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrCanMioCtrl + */ +#define XIOU_SLCR_CAN_MIO_CTRL ( ( XIOU_SLCR_BASEADDR ) + 0x00000304UL ) +#define XIOU_SLCR_CAN_MIO_CTRL_RSTVAL 0x00000000UL + +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_RXIN_REG_SHIFT 23UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_RXIN_REG_WIDTH 1UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_RXIN_REG_MASK 0x00800000UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_RXIN_REG_DEFVAL 0x0UL + +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_REF_SEL_SHIFT 22UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_REF_SEL_WIDTH 1UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_REF_SEL_MASK 0x00400000UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_REF_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_MUX_SHIFT 15UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_MUX_WIDTH 7UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_MUX_MASK 0x003f8000UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_MUX_DEFVAL 0x0UL + +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_RXIN_REG_SHIFT 8UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_RXIN_REG_WIDTH 1UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_RXIN_REG_MASK 0x00000100UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_RXIN_REG_DEFVAL 0x0UL + +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_REF_SEL_SHIFT 7UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_REF_SEL_WIDTH 1UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_REF_SEL_MASK 0x00000080UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_REF_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_MUX_SHIFT 0UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_MUX_WIDTH 7UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_MUX_MASK 0x0000007fUL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_MUX_DEFVAL 0x0UL + +/** + * Register: XiouSlcrGemClkCtrl + */ +#define XIOU_SLCR_GEM_CLK_CTRL ( ( XIOU_SLCR_BASEADDR ) + 0x00000308UL ) +#define XIOU_SLCR_GEM_CLK_CTRL_RSTVAL 0x00000000UL + +#define XIOU_SLCR_GEM_CLK_CTRL_TSU_LB_SEL_SHIFT 22UL +#define XIOU_SLCR_GEM_CLK_CTRL_TSU_LB_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_TSU_LB_SEL_MASK 0x00400000UL +#define XIOU_SLCR_GEM_CLK_CTRL_TSU_LB_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_TSU_SEL_SHIFT 20UL +#define XIOU_SLCR_GEM_CLK_CTRL_TSU_SEL_WIDTH 2UL +#define XIOU_SLCR_GEM_CLK_CTRL_TSU_SEL_MASK 0x00300000UL +#define XIOU_SLCR_GEM_CLK_CTRL_TSU_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT 18UL +#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_FIFO_SEL_MASK 0x00040000UL +#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT 17UL +#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH 1UL +#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_SGMII_MODE_MASK 0x00020000UL +#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT 16UL +#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK 0x00010000UL +#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT 15UL +#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK 0x00008000UL +#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT 13UL +#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_FIFO_SEL_MASK 0x00002000UL +#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT 12UL +#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH 1UL +#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_SGMII_MODE_MASK 0x00001000UL +#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT 11UL +#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK 0x00000800UL +#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT 10UL +#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK 0x00000400UL +#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT 8UL +#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_FIFO_SEL_MASK 0x00000100UL +#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT 7UL +#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH 1UL +#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_SGMII_MODE_MASK 0x00000080UL +#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT 6UL +#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK 0x00000040UL +#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT 5UL +#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK 0x00000020UL +#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT 3UL +#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_FIFO_SEL_MASK 0x00000008UL +#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT 2UL +#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH 1UL +#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_SGMII_MODE_MASK 0x00000004UL +#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT 1UL +#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK 0x00000002UL +#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT 0UL +#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK 0x00000001UL +#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrSdioClkCtrl + */ +#define XIOU_SLCR_SDIO_CLK_CTRL ( ( XIOU_SLCR_BASEADDR ) + 0x0000030CUL ) +#define XIOU_SLCR_SDIO_CLK_CTRL_RSTVAL 0x00000000UL + +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_FBCLK_SEL_SHIFT 18UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_FBCLK_SEL_WIDTH 1UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_FBCLK_SEL_MASK 0x00040000UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_FBCLK_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT 17UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_WIDTH 1UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK 0x00020000UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_FBCLK_SEL_SHIFT 2UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_FBCLK_SEL_WIDTH 1UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_FBCLK_SEL_MASK 0x00000004UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_FBCLK_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_RX_SRC_SEL_SHIFT 0UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_RX_SRC_SEL_WIDTH 2UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_RX_SRC_SEL_MASK 0x00000003UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_RX_SRC_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrCtrlRegSd + */ +#define XIOU_SLCR_CTRL_REG_SD ( ( XIOU_SLCR_BASEADDR ) + 0x00000310UL ) +#define XIOU_SLCR_CTRL_REG_SD_RSTVAL 0x00000000UL + +#define XIOU_SLCR_CTRL_REG_SD1_XSDPS_EMMC_SEL_SHIFT 15UL +#define XIOU_SLCR_CTRL_REG_SD1_XSDPS_EMMC_SEL_WIDTH 1UL +#define XIOU_SLCR_CTRL_REG_SD1_XSDPS_EMMC_SEL_MASK 0x00008000UL +#define XIOU_SLCR_CTRL_REG_SD1_XSDPS_EMMC_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_CTRL_REG_SD0_XSDPS_EMMC_SEL_SHIFT 0UL +#define XIOU_SLCR_CTRL_REG_SD0_XSDPS_EMMC_SEL_WIDTH 1UL +#define XIOU_SLCR_CTRL_REG_SD0_XSDPS_EMMC_SEL_MASK 0x00000001UL +#define XIOU_SLCR_CTRL_REG_SD0_XSDPS_EMMC_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrSdItapdly + */ +#define XIOU_SLCR_SD_ITAPDLY ( ( XIOU_SLCR_BASEADDR ) + 0x00000314UL ) +#define XIOU_SLCR_SD_ITAPDLY_RSTVAL 0x00000000UL + +#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPCHGWIN_SHIFT 25UL +#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPCHGWIN_WIDTH 1UL +#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPCHGWIN_MASK 0x02000000UL +#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPCHGWIN_DEFVAL 0x0UL + +#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPDLYENA_SHIFT 24UL +#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPDLYENA_WIDTH 1UL +#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPDLYENA_MASK 0x01000000UL +#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPDLYENA_DEFVAL 0x0UL + +#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPDLYSEL_SHIFT 16UL +#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPDLYSEL_WIDTH 8UL +#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPDLYSEL_MASK 0x00ff0000UL +#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPDLYSEL_DEFVAL 0x0UL + +#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPCHGWIN_SHIFT 9UL +#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPCHGWIN_WIDTH 1UL +#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPCHGWIN_MASK 0x00000200UL +#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPCHGWIN_DEFVAL 0x0UL + +#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPDLYENA_SHIFT 8UL +#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPDLYENA_WIDTH 1UL +#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPDLYENA_MASK 0x00000100UL +#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPDLYENA_DEFVAL 0x0UL + +#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPDLYSEL_SHIFT 0UL +#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPDLYSEL_WIDTH 8UL +#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPDLYSEL_MASK 0x000000ffUL +#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPDLYSEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrSdOtapdlysel + */ +#define XIOU_SLCR_SD_OTAPDLYSEL ( ( XIOU_SLCR_BASEADDR ) + 0x00000318UL ) +#define XIOU_SLCR_SD_OTAPDLYSEL_RSTVAL 0x00000000UL + +#define XIOU_SLCR_SD1_OTAPDLYSEL_XSDPS_OTAPDLYENA_SHIFT 22UL +#define XIOU_SLCR_SD1_OTAPDLYSEL_XSDPS_OTAPDLYENA_WIDTH 1UL +#define XIOU_SLCR_SD1_OTAPDLYSEL_XSDPS_OTAPDLYENA_MASK 0x00400000UL +#define XIOU_SLCR_SD1_OTAPDLYSEL_XSDPS_OTAPDLYENA_DEFVAL 0x0UL + +#define XIOU_SLCR_SD1_OTAPDLYSEL_XSDPS_SHIFT 16UL +#define XIOU_SLCR_SD1_OTAPDLYSEL_XSDPS_WIDTH 6UL +#define XIOU_SLCR_SD1_OTAPDLYSEL_XSDPS_MASK 0x003f0000UL +#define XIOU_SLCR_SD1_OTAPDLYSEL_XSDPS_DEFVAL 0x0UL + +#define XIOU_SLCR_SD0_OTAPDLYSEL_XSDPS_OTAPDLYENA_SHIFT 6UL +#define XIOU_SLCR_SD0_OTAPDLYSEL_XSDPS_OTAPDLYENA_WIDTH 1UL +#define XIOU_SLCR_SD0_OTAPDLYSEL_XSDPS_OTAPDLYENA_MASK 0x00000040UL +#define XIOU_SLCR_SD0_OTAPDLYSEL_XSDPS_OTAPDLYENA_DEFVAL 0x0UL + +#define XIOU_SLCR_SD0_OTAPDLYSEL_XSDPS_SHIFT 0UL +#define XIOU_SLCR_SD0_OTAPDLYSEL_XSDPS_WIDTH 6UL +#define XIOU_SLCR_SD0_OTAPDLYSEL_XSDPS_MASK 0x0000003fUL +#define XIOU_SLCR_SD0_OTAPDLYSEL_XSDPS_DEFVAL 0x0UL + +/** + * Register: XiouSlcrSdCfgReg1 + */ +#define XIOU_SLCR_SD_CFG_REG1 ( ( XIOU_SLCR_BASEADDR ) + 0x0000031CUL ) +#define XIOU_SLCR_SD_CFG_REG1_RSTVAL 0x32403240UL + +#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_BASECLK_SHIFT 23UL +#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_BASECLK_WIDTH 8UL +#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_BASECLK_MASK 0x7f800000UL +#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_BASECLK_DEFVAL 0x64UL + +#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_TUNIGCOUNT_SHIFT 17UL +#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_TUNIGCOUNT_WIDTH 6UL +#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_TUNIGCOUNT_MASK 0x007e0000UL +#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_TUNIGCOUNT_DEFVAL 0x20UL + +#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_ASYNCWKPENA_SHIFT 16UL +#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_ASYNCWKPENA_WIDTH 1UL +#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_ASYNCWKPENA_MASK 0x00010000UL +#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_ASYNCWKPENA_DEFVAL 0x0UL + +#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_BASECLK_SHIFT 7UL +#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_BASECLK_WIDTH 8UL +#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_BASECLK_MASK 0x00007f80UL +#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_BASECLK_DEFVAL 0x64UL + +#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_TUNIGCOUNT_SHIFT 1UL +#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_TUNIGCOUNT_WIDTH 6UL +#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_TUNIGCOUNT_MASK 0x0000007eUL +#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_TUNIGCOUNT_DEFVAL 0x20UL + +#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_ASYNCWKPENA_SHIFT 0UL +#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_ASYNCWKPENA_WIDTH 1UL +#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_ASYNCWKPENA_MASK 0x00000001UL +#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_ASYNCWKPENA_DEFVAL 0x0UL + +/** + * Register: XiouSlcrSdCfgReg2 + */ +#define XIOU_SLCR_SD_CFG_REG2 ( ( XIOU_SLCR_BASEADDR ) + 0x00000320UL ) +#define XIOU_SLCR_SD_CFG_REG2_RSTVAL 0x0ffc0ffcUL + +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SLOTTYPE_SHIFT 28UL +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SLOTTYPE_WIDTH 2UL +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SLOTTYPE_MASK 0x30000000UL +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SLOTTYPE_DEFVAL 0x0UL + +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_ASYCINTR_SHIFT 27UL +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_ASYCINTR_WIDTH 1UL +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_ASYCINTR_MASK 0x08000000UL +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_ASYCINTR_DEFVAL 0x1UL + +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_64BIT_SHIFT 26UL +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_64BIT_WIDTH 1UL +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_64BIT_MASK 0x04000000UL +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_64BIT_DEFVAL 0x1UL + +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_1P8V_SHIFT 25UL +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_1P8V_WIDTH 1UL +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_1P8V_MASK 0x02000000UL +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_1P8V_DEFVAL 0x1UL + +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_3P0V_SHIFT 24UL +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_3P0V_WIDTH 1UL +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_3P0V_MASK 0x01000000UL +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_3P0V_DEFVAL 0x1UL + +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_3P3V_SHIFT 23UL +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_3P3V_WIDTH 1UL +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_3P3V_MASK 0x00800000UL +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_3P3V_DEFVAL 0x1UL + +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SUSPRES_SHIFT 22UL +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SUSPRES_WIDTH 1UL +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SUSPRES_MASK 0x00400000UL +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SUSPRES_DEFVAL 0x1UL + +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SDMA_SHIFT 21UL +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SDMA_WIDTH 1UL +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SDMA_MASK 0x00200000UL +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SDMA_DEFVAL 0x1UL + +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_HIGHSPEED_SHIFT 20UL +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_HIGHSPEED_WIDTH 1UL +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_HIGHSPEED_MASK 0x00100000UL +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_HIGHSPEED_DEFVAL 0x1UL + +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_ADMA2_SHIFT 19UL +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_ADMA2_WIDTH 1UL +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_ADMA2_MASK 0x00080000UL +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_ADMA2_DEFVAL 0x1UL + +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_8BIT_SHIFT 18UL +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_8BIT_WIDTH 1UL +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_8BIT_MASK 0x00040000UL +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_8BIT_DEFVAL 0x1UL + +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_MAXBLK_SHIFT 16UL +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_MAXBLK_WIDTH 2UL +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_MAXBLK_MASK 0x00030000UL +#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_MAXBLK_DEFVAL 0x0UL + +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SLOTTYPE_SHIFT 12UL +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SLOTTYPE_WIDTH 2UL +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SLOTTYPE_MASK 0x00003000UL +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SLOTTYPE_DEFVAL 0x0UL + +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_ASYCINTR_SHIFT 11UL +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_ASYCINTR_WIDTH 1UL +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_ASYCINTR_MASK 0x00000800UL +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_ASYCINTR_DEFVAL 0x1UL + +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_64BIT_SHIFT 10UL +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_64BIT_WIDTH 1UL +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_64BIT_MASK 0x00000400UL +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_64BIT_DEFVAL 0x1UL + +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_1P8V_SHIFT 9UL +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_1P8V_WIDTH 1UL +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_1P8V_MASK 0x00000200UL +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_1P8V_DEFVAL 0x1UL + +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_3P0V_SHIFT 8UL +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_3P0V_WIDTH 1UL +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_3P0V_MASK 0x00000100UL +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_3P0V_DEFVAL 0x1UL + +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_3P3V_SHIFT 7UL +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_3P3V_WIDTH 1UL +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_3P3V_MASK 0x00000080UL +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_3P3V_DEFVAL 0x1UL + +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SUSPRES_SHIFT 6UL +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SUSPRES_WIDTH 1UL +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SUSPRES_MASK 0x00000040UL +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SUSPRES_DEFVAL 0x1UL + +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SDMA_SHIFT 5UL +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SDMA_WIDTH 1UL +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SDMA_MASK 0x00000020UL +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SDMA_DEFVAL 0x1UL + +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_HIGHSPEED_SHIFT 4UL +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_HIGHSPEED_WIDTH 1UL +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_HIGHSPEED_MASK 0x00000010UL +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_HIGHSPEED_DEFVAL 0x1UL + +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_ADMA2_SHIFT 3UL +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_ADMA2_WIDTH 1UL +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_ADMA2_MASK 0x00000008UL +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_ADMA2_DEFVAL 0x1UL + +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_8BIT_SHIFT 2UL +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_8BIT_WIDTH 1UL +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_8BIT_MASK 0x00000004UL +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_8BIT_DEFVAL 0x1UL + +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_MAXBLK_SHIFT 0UL +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_MAXBLK_WIDTH 2UL +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_MAXBLK_MASK 0x00000003UL +#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_MAXBLK_DEFVAL 0x0UL + +/** + * Register: XiouSlcrSdCfgReg3 + */ +#define XIOU_SLCR_SD_CFG_REG3 ( ( XIOU_SLCR_BASEADDR ) + 0x00000324UL ) +#define XIOU_SLCR_SD_CFG_REG3_RSTVAL 0x06070607UL + +#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_TUNINGSDR50_SHIFT 26UL +#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_TUNINGSDR50_WIDTH 1UL +#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_TUNINGSDR50_MASK 0x04000000UL +#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_TUNINGSDR50_DEFVAL 0x1UL + +#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_RETUNETMR_SHIFT 22UL +#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_RETUNETMR_WIDTH 4UL +#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_RETUNETMR_MASK 0x03c00000UL +#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_RETUNETMR_DEFVAL 0x8UL + +#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_DDRIVER_SHIFT 21UL +#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_DDRIVER_WIDTH 1UL +#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_DDRIVER_MASK 0x00200000UL +#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_DDRIVER_DEFVAL 0x0UL + +#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_CDRIVER_SHIFT 20UL +#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_CDRIVER_WIDTH 1UL +#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_CDRIVER_MASK 0x00100000UL +#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_CDRIVER_DEFVAL 0x0UL + +#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_ADRIVER_SHIFT 19UL +#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_ADRIVER_WIDTH 1UL +#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_ADRIVER_MASK 0x00080000UL +#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_ADRIVER_DEFVAL 0x0UL + +#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_DDR50_SHIFT 18UL +#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_DDR50_WIDTH 1UL +#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_DDR50_MASK 0x00040000UL +#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_DDR50_DEFVAL 0x1UL + +#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_SDR104_SHIFT 17UL +#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_SDR104_WIDTH 1UL +#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_SDR104_MASK 0x00020000UL +#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_SDR104_DEFVAL 0x1UL + +#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_SDR50_SHIFT 16UL +#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_SDR50_WIDTH 1UL +#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_SDR50_MASK 0x00010000UL +#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_SDR50_DEFVAL 0x1UL + +#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_TUNINGSDR50_SHIFT 10UL +#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_TUNINGSDR50_WIDTH 1UL +#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_TUNINGSDR50_MASK 0x00000400UL +#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_TUNINGSDR50_DEFVAL 0x1UL + +#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_RETUNETMR_SHIFT 6UL +#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_RETUNETMR_WIDTH 4UL +#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_RETUNETMR_MASK 0x000003c0UL +#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_RETUNETMR_DEFVAL 0x8UL + +#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_DDRIVER_SHIFT 5UL +#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_DDRIVER_WIDTH 1UL +#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_DDRIVER_MASK 0x00000020UL +#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_DDRIVER_DEFVAL 0x0UL + +#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_CDRIVER_SHIFT 4UL +#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_CDRIVER_WIDTH 1UL +#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_CDRIVER_MASK 0x00000010UL +#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_CDRIVER_DEFVAL 0x0UL + +#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_ADRIVER_SHIFT 3UL +#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_ADRIVER_WIDTH 1UL +#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_ADRIVER_MASK 0x00000008UL +#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_ADRIVER_DEFVAL 0x0UL + +#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_DDR50_SHIFT 2UL +#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_DDR50_WIDTH 1UL +#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_DDR50_MASK 0x00000004UL +#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_DDR50_DEFVAL 0x1UL + +#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_SDR104_SHIFT 1UL +#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_SDR104_WIDTH 1UL +#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_SDR104_MASK 0x00000002UL +#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_SDR104_DEFVAL 0x1UL + +#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_SDR50_SHIFT 0UL +#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_SDR50_WIDTH 1UL +#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_SDR50_MASK 0x00000001UL +#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_SDR50_DEFVAL 0x1UL + +/** + * Register: XiouSlcrSdInitpreset + */ +#define XIOU_SLCR_SD_INITPRESET ( ( XIOU_SLCR_BASEADDR ) + 0x00000328UL ) +#define XIOU_SLCR_SD_INITPRESET_RSTVAL 0x01000100UL + +#define XIOU_SLCR_SD1_INITPRESET_XSDPS_SHIFT 16UL +#define XIOU_SLCR_SD1_INITPRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD1_INITPRESET_XSDPS_MASK 0x1fff0000UL +#define XIOU_SLCR_SD1_INITPRESET_XSDPS_DEFVAL 0x100UL + +#define XIOU_SLCR_SD0_INITPRESET_XSDPS_SHIFT 0UL +#define XIOU_SLCR_SD0_INITPRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD0_INITPRESET_XSDPS_MASK 0x00001fffUL +#define XIOU_SLCR_SD0_INITPRESET_XSDPS_DEFVAL 0x100UL + +/** + * Register: XiouSlcrSdDsppreset + */ +#define XIOU_SLCR_SD_DSPPRESET ( ( XIOU_SLCR_BASEADDR ) + 0x0000032CUL ) +#define XIOU_SLCR_SD_DSPPRESET_RSTVAL 0x00040004UL + +#define XIOU_SLCR_SD1_DSPPRESET_XSDPS_SHIFT 16UL +#define XIOU_SLCR_SD1_DSPPRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD1_DSPPRESET_XSDPS_MASK 0x1fff0000UL +#define XIOU_SLCR_SD1_DSPPRESET_XSDPS_DEFVAL 0x4UL + +#define XIOU_SLCR_SD0_DSPPRESET_XSDPS_SHIFT 0UL +#define XIOU_SLCR_SD0_DSPPRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD0_DSPPRESET_XSDPS_MASK 0x00001fffUL +#define XIOU_SLCR_SD0_DSPPRESET_XSDPS_DEFVAL 0x4UL + +/** + * Register: XiouSlcrSdHspdpreset + */ +#define XIOU_SLCR_SD_HSPDPRESET ( ( XIOU_SLCR_BASEADDR ) + 0x00000330UL ) +#define XIOU_SLCR_SD_HSPDPRESET_RSTVAL 0x00020002UL + +#define XIOU_SLCR_SD1_HSPDPRESET_XSDPS_SHIFT 16UL +#define XIOU_SLCR_SD1_HSPDPRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD1_HSPDPRESET_XSDPS_MASK 0x1fff0000UL +#define XIOU_SLCR_SD1_HSPDPRESET_XSDPS_DEFVAL 0x2UL + +#define XIOU_SLCR_SD0_HSPDPRESET_XSDPS_SHIFT 0UL +#define XIOU_SLCR_SD0_HSPDPRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD0_HSPDPRESET_XSDPS_MASK 0x00001fffUL +#define XIOU_SLCR_SD0_HSPDPRESET_XSDPS_DEFVAL 0x2UL + +/** + * Register: XiouSlcrSdSdr12preset + */ +#define XIOU_SLCR_SD_SDR12PRESET ( ( XIOU_SLCR_BASEADDR ) + 0x00000334UL ) +#define XIOU_SLCR_SD_SDR12PRESET_RSTVAL 0x00040004UL + +#define XIOU_SLCR_SD1_SDR12PRESET_XSDPS_SHIFT 16UL +#define XIOU_SLCR_SD1_SDR12PRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD1_SDR12PRESET_XSDPS_MASK 0x1fff0000UL +#define XIOU_SLCR_SD1_SDR12PRESET_XSDPS_DEFVAL 0x4UL + +#define XIOU_SLCR_SD0_SDR12PRESET_XSDPS_SHIFT 0UL +#define XIOU_SLCR_SD0_SDR12PRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD0_SDR12PRESET_XSDPS_MASK 0x00001fffUL +#define XIOU_SLCR_SD0_SDR12PRESET_XSDPS_DEFVAL 0x4UL + +/** + * Register: XiouSlcrSdSdr25preset + */ +#define XIOU_SLCR_SD_SDR25PRESET ( ( XIOU_SLCR_BASEADDR ) + 0x00000338UL ) +#define XIOU_SLCR_SD_SDR25PRESET_RSTVAL 0x00020002UL + +#define XIOU_SLCR_SD1_SDR25PRESET_XSDPS_SHIFT 16UL +#define XIOU_SLCR_SD1_SDR25PRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD1_SDR25PRESET_XSDPS_MASK 0x1fff0000UL +#define XIOU_SLCR_SD1_SDR25PRESET_XSDPS_DEFVAL 0x2UL + +#define XIOU_SLCR_SD0_SDR25PRESET_XSDPS_SHIFT 0UL +#define XIOU_SLCR_SD0_SDR25PRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD0_SDR25PRESET_XSDPS_MASK 0x00001fffUL +#define XIOU_SLCR_SD0_SDR25PRESET_XSDPS_DEFVAL 0x2UL + +/** + * Register: XiouSlcrSdSdr50prset + */ +#define XIOU_SLCR_SD_SDR50PRSET ( ( XIOU_SLCR_BASEADDR ) + 0x0000033CUL ) +#define XIOU_SLCR_SD_SDR50PRSET_RSTVAL 0x00010001UL + +#define XIOU_SLCR_SD1_SDR50PRSET_XSDPS_SDR50PRESET_SHIFT 16UL +#define XIOU_SLCR_SD1_SDR50PRSET_XSDPS_SDR50PRESET_WIDTH 13UL +#define XIOU_SLCR_SD1_SDR50PRSET_XSDPS_SDR50PRESET_MASK 0x1fff0000UL +#define XIOU_SLCR_SD1_SDR50PRSET_XSDPS_SDR50PRESET_DEFVAL 0x1UL + +#define XIOU_SLCR_SD0_SDR50PRSET_XSDPS_SDR50PRESET_SHIFT 0UL +#define XIOU_SLCR_SD0_SDR50PRSET_XSDPS_SDR50PRESET_WIDTH 13UL +#define XIOU_SLCR_SD0_SDR50PRSET_XSDPS_SDR50PRESET_MASK 0x00001fffUL +#define XIOU_SLCR_SD0_SDR50PRSET_XSDPS_SDR50PRESET_DEFVAL 0x1UL + +/** + * Register: XiouSlcrSdSdr104prst + */ +#define XIOU_SLCR_SD_SDR104PRST ( ( XIOU_SLCR_BASEADDR ) + 0x00000340UL ) +#define XIOU_SLCR_SD_SDR104PRST_RSTVAL 0x00000000UL + +#define XIOU_SLCR_SD1_SDR104PRST_XSDPS_SDR104PRESET_SHIFT 16UL +#define XIOU_SLCR_SD1_SDR104PRST_XSDPS_SDR104PRESET_WIDTH 13UL +#define XIOU_SLCR_SD1_SDR104PRST_XSDPS_SDR104PRESET_MASK 0x1fff0000UL +#define XIOU_SLCR_SD1_SDR104PRST_XSDPS_SDR104PRESET_DEFVAL 0x0UL + +#define XIOU_SLCR_SD0_SDR104PRST_XSDPS_SDR104PRESET_SHIFT 0UL +#define XIOU_SLCR_SD0_SDR104PRST_XSDPS_SDR104PRESET_WIDTH 13UL +#define XIOU_SLCR_SD0_SDR104PRST_XSDPS_SDR104PRESET_MASK 0x00001fffUL +#define XIOU_SLCR_SD0_SDR104PRST_XSDPS_SDR104PRESET_DEFVAL 0x0UL + +/** + * Register: XiouSlcrSdDdr50preset + */ +#define XIOU_SLCR_SD_DDR50PRESET ( ( XIOU_SLCR_BASEADDR ) + 0x00000344UL ) +#define XIOU_SLCR_SD_DDR50PRESET_RSTVAL 0x00020002UL + +#define XIOU_SLCR_SD1_DDR50PRESET_XSDPS_SHIFT 16UL +#define XIOU_SLCR_SD1_DDR50PRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD1_DDR50PRESET_XSDPS_MASK 0x1fff0000UL +#define XIOU_SLCR_SD1_DDR50PRESET_XSDPS_DEFVAL 0x2UL + +#define XIOU_SLCR_SD0_DDR50PRESET_XSDPS_SHIFT 0UL +#define XIOU_SLCR_SD0_DDR50PRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD0_DDR50PRESET_XSDPS_MASK 0x00001fffUL +#define XIOU_SLCR_SD0_DDR50PRESET_XSDPS_DEFVAL 0x2UL + +/** + * Register: XiouSlcrSdMaxcur1p8 + */ +#define XIOU_SLCR_SD_MAXCUR1P8 ( ( XIOU_SLCR_BASEADDR ) + 0x0000034CUL ) +#define XIOU_SLCR_SD_MAXCUR1P8_RSTVAL 0x00000000UL + +#define XIOU_SLCR_SD1_MAXCUR1P8_XSDPS_SHIFT 16UL +#define XIOU_SLCR_SD1_MAXCUR1P8_XSDPS_WIDTH 8UL +#define XIOU_SLCR_SD1_MAXCUR1P8_XSDPS_MASK 0x00ff0000UL +#define XIOU_SLCR_SD1_MAXCUR1P8_XSDPS_DEFVAL 0x0UL + +#define XIOU_SLCR_SD0_MAXCUR1P8_XSDPS_SHIFT 0UL +#define XIOU_SLCR_SD0_MAXCUR1P8_XSDPS_WIDTH 8UL +#define XIOU_SLCR_SD0_MAXCUR1P8_XSDPS_MASK 0x000000ffUL +#define XIOU_SLCR_SD0_MAXCUR1P8_XSDPS_DEFVAL 0x0UL + +/** + * Register: XiouSlcrSdMaxcur3p0 + */ +#define XIOU_SLCR_SD_MAXCUR3P0 ( ( XIOU_SLCR_BASEADDR ) + 0x00000350UL ) +#define XIOU_SLCR_SD_MAXCUR3P0_RSTVAL 0x00000000UL + +#define XIOU_SLCR_SD1_MAXCUR3P0_XSDPS_SHIFT 16UL +#define XIOU_SLCR_SD1_MAXCUR3P0_XSDPS_WIDTH 8UL +#define XIOU_SLCR_SD1_MAXCUR3P0_XSDPS_MASK 0x00ff0000UL +#define XIOU_SLCR_SD1_MAXCUR3P0_XSDPS_DEFVAL 0x0UL + +#define XIOU_SLCR_SD0_MAXCUR3P0_XSDPS_SHIFT 0UL +#define XIOU_SLCR_SD0_MAXCUR3P0_XSDPS_WIDTH 8UL +#define XIOU_SLCR_SD0_MAXCUR3P0_XSDPS_MASK 0x000000ffUL +#define XIOU_SLCR_SD0_MAXCUR3P0_XSDPS_DEFVAL 0x0UL + +/** + * Register: XiouSlcrSdMaxcur3p3 + */ +#define XIOU_SLCR_SD_MAXCUR3P3 ( ( XIOU_SLCR_BASEADDR ) + 0x00000354UL ) +#define XIOU_SLCR_SD_MAXCUR3P3_RSTVAL 0x00000000UL + +#define XIOU_SLCR_SD1_MAXCUR3P3_XSDPS_SHIFT 16UL +#define XIOU_SLCR_SD1_MAXCUR3P3_XSDPS_WIDTH 8UL +#define XIOU_SLCR_SD1_MAXCUR3P3_XSDPS_MASK 0x00ff0000UL +#define XIOU_SLCR_SD1_MAXCUR3P3_XSDPS_DEFVAL 0x0UL + +#define XIOU_SLCR_SD0_MAXCUR3P3_XSDPS_SHIFT 0UL +#define XIOU_SLCR_SD0_MAXCUR3P3_XSDPS_WIDTH 8UL +#define XIOU_SLCR_SD0_MAXCUR3P3_XSDPS_MASK 0x000000ffUL +#define XIOU_SLCR_SD0_MAXCUR3P3_XSDPS_DEFVAL 0x0UL + +/** + * Register: XiouSlcrSdDllCtrl + */ +#define XIOU_SLCR_SD_DLL_CTRL ( ( XIOU_SLCR_BASEADDR ) + 0x00000358UL ) +#define XIOU_SLCR_SD_DLL_CTRL_RSTVAL 0x00000000UL + +#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_RST_SHIFT 18UL +#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_RST_WIDTH 1UL +#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_RST_MASK 0x00040000UL +#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_RST_DEFVAL 0x0UL + +#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_TESTMODE_SHIFT 17UL +#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_TESTMODE_WIDTH 1UL +#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_TESTMODE_MASK 0x00020000UL +#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_TESTMODE_DEFVAL 0x0UL + +#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_LOCK_SHIFT 16UL +#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_LOCK_WIDTH 1UL +#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_LOCK_MASK 0x00010000UL +#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_LOCK_DEFVAL 0x0UL + +#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_RST_SHIFT 2UL +#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_RST_WIDTH 1UL +#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_RST_MASK 0x00000004UL +#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_RST_DEFVAL 0x0UL + +#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_TESTMODE_SHIFT 1UL +#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_TESTMODE_WIDTH 1UL +#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_TESTMODE_MASK 0x00000002UL +#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_TESTMODE_DEFVAL 0x0UL + +#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_LOCK_SHIFT 0UL +#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_LOCK_WIDTH 1UL +#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_LOCK_MASK 0x00000001UL +#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_LOCK_DEFVAL 0x0UL + +/** + * Register: XiouSlcrSdCdnCtrl + */ +#define XIOU_SLCR_SD_CDN_CTRL ( ( XIOU_SLCR_BASEADDR ) + 0x0000035CUL ) +#define XIOU_SLCR_SD_CDN_CTRL_RSTVAL 0x00000000UL + +#define XIOU_SLCR_SD1_CDN_CTRL_XSDPS_SHIFT 16UL +#define XIOU_SLCR_SD1_CDN_CTRL_XSDPS_WIDTH 1UL +#define XIOU_SLCR_SD1_CDN_CTRL_XSDPS_MASK 0x00010000UL +#define XIOU_SLCR_SD1_CDN_CTRL_XSDPS_DEFVAL 0x0UL + +#define XIOU_SLCR_SD0_CDN_CTRL_XSDPS_SHIFT 0UL +#define XIOU_SLCR_SD0_CDN_CTRL_XSDPS_WIDTH 1UL +#define XIOU_SLCR_SD0_CDN_CTRL_XSDPS_MASK 0x00000001UL +#define XIOU_SLCR_SD0_CDN_CTRL_XSDPS_DEFVAL 0x0UL + +/** + * Register: XiouSlcrGemCtrl + */ +#define XIOU_SLCR_GEM_CTRL ( ( XIOU_SLCR_BASEADDR ) + 0x00000360UL ) +#define XIOU_SLCR_GEM_CTRL_RSTVAL 0x00000000UL + +#define XIOU_SLCR_GEM3_CTRL_XEMACPS_SGMII_SD_SHIFT 6UL +#define XIOU_SLCR_GEM3_CTRL_XEMACPS_SGMII_SD_WIDTH 2UL +#define XIOU_SLCR_GEM3_CTRL_XEMACPS_SGMII_SD_MASK 0x000000c0UL +#define XIOU_SLCR_GEM3_CTRL_XEMACPS_SGMII_SD_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM2_CTRL_XEMACPS_SGMII_SD_SHIFT 4UL +#define XIOU_SLCR_GEM2_CTRL_XEMACPS_SGMII_SD_WIDTH 2UL +#define XIOU_SLCR_GEM2_CTRL_XEMACPS_SGMII_SD_MASK 0x00000030UL +#define XIOU_SLCR_GEM2_CTRL_XEMACPS_SGMII_SD_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM1_CTRL_XEMACPS_SGMII_SD_SHIFT 2UL +#define XIOU_SLCR_GEM1_CTRL_XEMACPS_SGMII_SD_WIDTH 2UL +#define XIOU_SLCR_GEM1_CTRL_XEMACPS_SGMII_SD_MASK 0x0000000cUL +#define XIOU_SLCR_GEM1_CTRL_XEMACPS_SGMII_SD_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM0_CTRL_XEMACPS_SGMII_SD_SHIFT 0UL +#define XIOU_SLCR_GEM0_CTRL_XEMACPS_SGMII_SD_WIDTH 2UL +#define XIOU_SLCR_GEM0_CTRL_XEMACPS_SGMII_SD_MASK 0x00000003UL +#define XIOU_SLCR_GEM0_CTRL_XEMACPS_SGMII_SD_DEFVAL 0x0UL + +/** + * Register: XiouSlcrTtcApbClk + */ +#define XIOU_SLCR_TTC_APB_CLK ( ( XIOU_SLCR_BASEADDR ) + 0x00000380UL ) +#define XIOU_SLCR_TTC_APB_CLK_RSTVAL 0x00000000UL + +#define XIOU_SLCR_TTC_APB_CLK_TTC3_SEL_SHIFT 6UL +#define XIOU_SLCR_TTC_APB_CLK_TTC3_SEL_WIDTH 2UL +#define XIOU_SLCR_TTC_APB_CLK_TTC3_SEL_MASK 0x000000c0UL +#define XIOU_SLCR_TTC_APB_CLK_TTC3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_TTC_APB_CLK_TTC2_SEL_SHIFT 4UL +#define XIOU_SLCR_TTC_APB_CLK_TTC2_SEL_WIDTH 2UL +#define XIOU_SLCR_TTC_APB_CLK_TTC2_SEL_MASK 0x00000030UL +#define XIOU_SLCR_TTC_APB_CLK_TTC2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_TTC_APB_CLK_TTC1_SEL_SHIFT 2UL +#define XIOU_SLCR_TTC_APB_CLK_TTC1_SEL_WIDTH 2UL +#define XIOU_SLCR_TTC_APB_CLK_TTC1_SEL_MASK 0x0000000cUL +#define XIOU_SLCR_TTC_APB_CLK_TTC1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_TTC_APB_CLK_TTC0_SEL_SHIFT 0UL +#define XIOU_SLCR_TTC_APB_CLK_TTC0_SEL_WIDTH 2UL +#define XIOU_SLCR_TTC_APB_CLK_TTC0_SEL_MASK 0x00000003UL +#define XIOU_SLCR_TTC_APB_CLK_TTC0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrTapdlyBypass + */ +#define XIOU_SLCR_TAPDLY_BYPASS ( ( XIOU_SLCR_BASEADDR ) + 0x00000390UL ) +#define XIOU_SLCR_TAPDLY_BYPASS_RSTVAL 0x00000007UL + +#define XIOU_SLCR_TAPDLY_BYPASS_LQSPI_RX_SHIFT 2UL +#define XIOU_SLCR_TAPDLY_BYPASS_LQSPI_RX_WIDTH 1UL +#define XIOU_SLCR_TAPDLY_BYPASS_LQSPI_RX_MASK 0x00000004UL +#define XIOU_SLCR_TAPDLY_BYPASS_LQSPI_RX_DEFVAL 0x1UL + +#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_OUT_SHIFT 1UL +#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_OUT_WIDTH 1UL +#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_OUT_MASK 0x00000002UL +#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_OUT_DEFVAL 0x1UL + +#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_IN_SHIFT 0UL +#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_IN_WIDTH 1UL +#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_IN_MASK 0x00000001UL +#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_IN_DEFVAL 0x1UL + +/** + * Register: XiouSlcrCoherentCtrl + */ +#define XIOU_SLCR_COHERENT_CTRL ( ( XIOU_SLCR_BASEADDR ) + 0x00000400UL ) +#define XIOU_SLCR_COHERENT_CTRL_RSTVAL 0x00000000UL + +#define XIOU_SLCR_COHERENT_CTRL_XQSPIPSAXI_COH_SHIFT 28UL +#define XIOU_SLCR_COHERENT_CTRL_XQSPIPSAXI_COH_WIDTH 4UL +#define XIOU_SLCR_COHERENT_CTRL_XQSPIPSAXI_COH_MASK 0xf0000000UL +#define XIOU_SLCR_COHERENT_CTRL_XQSPIPSAXI_COH_DEFVAL 0x0UL + +#define XIOU_SLCR_COHERENT_CTRL_XNANDPS8_AXI_COH_SHIFT 24UL +#define XIOU_SLCR_COHERENT_CTRL_XNANDPS8_AXI_COH_WIDTH 4UL +#define XIOU_SLCR_COHERENT_CTRL_XNANDPS8_AXI_COH_MASK 0x0f000000UL +#define XIOU_SLCR_COHERENT_CTRL_XNANDPS8_AXI_COH_DEFVAL 0x0UL + +#define XIOU_SLCR_COHERENT_CTRL_XSDPS1_AXI_COH_SHIFT 20UL +#define XIOU_SLCR_COHERENT_CTRL_XSDPS1_AXI_COH_WIDTH 4UL +#define XIOU_SLCR_COHERENT_CTRL_XSDPS1_AXI_COH_MASK 0x00f00000UL +#define XIOU_SLCR_COHERENT_CTRL_XSDPS1_AXI_COH_DEFVAL 0x0UL + +#define XIOU_SLCR_COHERENT_CTRL_XSDPS0_AXI_COH_SHIFT 16UL +#define XIOU_SLCR_COHERENT_CTRL_XSDPS0_AXI_COH_WIDTH 4UL +#define XIOU_SLCR_COHERENT_CTRL_XSDPS0_AXI_COH_MASK 0x000f0000UL +#define XIOU_SLCR_COHERENT_CTRL_XSDPS0_AXI_COH_DEFVAL 0x0UL + +#define XIOU_SLCR_COHERENT_CTRL_GEM3_AXI_COH_SHIFT 12UL +#define XIOU_SLCR_COHERENT_CTRL_GEM3_AXI_COH_WIDTH 4UL +#define XIOU_SLCR_COHERENT_CTRL_GEM3_AXI_COH_MASK 0x0000f000UL +#define XIOU_SLCR_COHERENT_CTRL_GEM3_AXI_COH_DEFVAL 0x0UL + +#define XIOU_SLCR_COHERENT_CTRL_GEM2_AXI_COH_SHIFT 8UL +#define XIOU_SLCR_COHERENT_CTRL_GEM2_AXI_COH_WIDTH 4UL +#define XIOU_SLCR_COHERENT_CTRL_GEM2_AXI_COH_MASK 0x00000f00UL +#define XIOU_SLCR_COHERENT_CTRL_GEM2_AXI_COH_DEFVAL 0x0UL + +#define XIOU_SLCR_COHERENT_CTRL_GEM1_AXI_COH_SHIFT 4UL +#define XIOU_SLCR_COHERENT_CTRL_GEM1_AXI_COH_WIDTH 4UL +#define XIOU_SLCR_COHERENT_CTRL_GEM1_AXI_COH_MASK 0x000000f0UL +#define XIOU_SLCR_COHERENT_CTRL_GEM1_AXI_COH_DEFVAL 0x0UL + +#define XIOU_SLCR_COHERENT_CTRL_GEM0_AXI_COH_SHIFT 0UL +#define XIOU_SLCR_COHERENT_CTRL_GEM0_AXI_COH_WIDTH 4UL +#define XIOU_SLCR_COHERENT_CTRL_GEM0_AXI_COH_MASK 0x0000000fUL +#define XIOU_SLCR_COHERENT_CTRL_GEM0_AXI_COH_DEFVAL 0x0UL + +/** + * Register: XiouSlcrVideoPssClkSel + */ +#define XIOU_SLCR_VIDEO_PSS_CLK_SEL ( ( XIOU_SLCR_BASEADDR ) + 0x00000404UL ) +#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_RSTVAL 0x00000000UL + +#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_ALT_SHIFT 1UL +#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_ALT_WIDTH 1UL +#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_ALT_MASK 0x00000002UL +#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_ALT_DEFVAL 0x0UL + +#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_SHIFT 0UL +#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_WIDTH 1UL +#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_MASK 0x00000001UL +#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrInterconnectRoute + */ +#define XIOU_SLCR_INTERCONNECT_ROUTE ( ( XIOU_SLCR_BASEADDR ) + 0x00000408UL ) +#define XIOU_SLCR_INTERCONNECT_ROUTE_RSTVAL 0x00000000UL + +#define XIOU_SLCR_INTERCONNECT_ROUTE_XNANDPS8_SHIFT 7UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XNANDPS8_WIDTH 1UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XNANDPS8_MASK 0x00000080UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XNANDPS8_DEFVAL 0x0UL + +#define XIOU_SLCR_INTERCONNECT_ROUTE_QSPI_SHIFT 6UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_QSPI_WIDTH 1UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_QSPI_MASK 0x00000040UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_QSPI_DEFVAL 0x0UL + +#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS1_SHIFT 5UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS1_WIDTH 1UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS1_MASK 0x00000020UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS1_DEFVAL 0x0UL + +#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS0_SHIFT 4UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS0_WIDTH 1UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS0_MASK 0x00000010UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS0_DEFVAL 0x0UL + +#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM3_SHIFT 3UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM3_WIDTH 1UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM3_MASK 0x00000008UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM3_DEFVAL 0x0UL + +#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM2_SHIFT 2UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM2_WIDTH 1UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM2_MASK 0x00000004UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM2_DEFVAL 0x0UL + +#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM1_SHIFT 1UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM1_WIDTH 1UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM1_MASK 0x00000002UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM1_DEFVAL 0x0UL + +#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM0_SHIFT 0UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM0_WIDTH 1UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM0_MASK 0x00000001UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM0_DEFVAL 0x0UL + +/** + * Register: XiouSlcrRamGem0 + */ +#define XIOU_SLCR_RAM_GEM0 ( ( XIOU_SLCR_BASEADDR ) + 0x00000500UL ) +#define XIOU_SLCR_RAM_GEM0_RSTVAL 0x00005b5bUL + +#define XIOU_SLCR_RAM_GEM0_EMASA1_SHIFT 14UL +#define XIOU_SLCR_RAM_GEM0_EMASA1_WIDTH 1UL +#define XIOU_SLCR_RAM_GEM0_EMASA1_MASK 0x00004000UL +#define XIOU_SLCR_RAM_GEM0_EMASA1_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_GEM0_EMAB1_SHIFT 11UL +#define XIOU_SLCR_RAM_GEM0_EMAB1_WIDTH 3UL +#define XIOU_SLCR_RAM_GEM0_EMAB1_MASK 0x00003800UL +#define XIOU_SLCR_RAM_GEM0_EMAB1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_GEM0_EMAA1_SHIFT 8UL +#define XIOU_SLCR_RAM_GEM0_EMAA1_WIDTH 3UL +#define XIOU_SLCR_RAM_GEM0_EMAA1_MASK 0x00000700UL +#define XIOU_SLCR_RAM_GEM0_EMAA1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_GEM0_EMASA0_SHIFT 6UL +#define XIOU_SLCR_RAM_GEM0_EMASA0_WIDTH 1UL +#define XIOU_SLCR_RAM_GEM0_EMASA0_MASK 0x00000040UL +#define XIOU_SLCR_RAM_GEM0_EMASA0_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_GEM0_EMAB0_SHIFT 3UL +#define XIOU_SLCR_RAM_GEM0_EMAB0_WIDTH 3UL +#define XIOU_SLCR_RAM_GEM0_EMAB0_MASK 0x00000038UL +#define XIOU_SLCR_RAM_GEM0_EMAB0_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_GEM0_EMAA0_SHIFT 0UL +#define XIOU_SLCR_RAM_GEM0_EMAA0_WIDTH 3UL +#define XIOU_SLCR_RAM_GEM0_EMAA0_MASK 0x00000007UL +#define XIOU_SLCR_RAM_GEM0_EMAA0_DEFVAL 0x3UL + +/** + * Register: XiouSlcrRamgem1 + */ +#define XIOU_SLCR_RAM_GEM1 ( ( XIOU_SLCR_BASEADDR ) + 0x00000504UL ) +#define XIOU_SLCR_RAM_GEM1_RSTVAL 0x00005b5bUL + +#define XIOU_SLCR_RAM_GEM1_EMASA1_SHIFT 14UL +#define XIOU_SLCR_RAM_GEM1_EMASA1_WIDTH 1UL +#define XIOU_SLCR_RAM_GEM1_EMASA1_MASK 0x00004000UL +#define XIOU_SLCR_RAM_GEM1_EMASA1_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_GEM1_EMAB1_SHIFT 11UL +#define XIOU_SLCR_RAM_GEM1_EMAB1_WIDTH 3UL +#define XIOU_SLCR_RAM_GEM1_EMAB1_MASK 0x00003800UL +#define XIOU_SLCR_RAM_GEM1_EMAB1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_GEM1_EMAA1_SHIFT 8UL +#define XIOU_SLCR_RAM_GEM1_EMAA1_WIDTH 3UL +#define XIOU_SLCR_RAM_GEM1_EMAA1_MASK 0x00000700UL +#define XIOU_SLCR_RAM_GEM1_EMAA1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_GEM1_EMASA0_SHIFT 6UL +#define XIOU_SLCR_RAM_GEM1_EMASA0_WIDTH 1UL +#define XIOU_SLCR_RAM_GEM1_EMASA0_MASK 0x00000040UL +#define XIOU_SLCR_RAM_GEM1_EMASA0_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_GEM1_EMAB0_SHIFT 3UL +#define XIOU_SLCR_RAM_GEM1_EMAB0_WIDTH 3UL +#define XIOU_SLCR_RAM_GEM1_EMAB0_MASK 0x00000038UL +#define XIOU_SLCR_RAM_GEM1_EMAB0_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_GEM1_EMAA0_SHIFT 0UL +#define XIOU_SLCR_RAM_GEM1_EMAA0_WIDTH 3UL +#define XIOU_SLCR_RAM_GEM1_EMAA0_MASK 0x00000007UL +#define XIOU_SLCR_RAM_GEM1_EMAA0_DEFVAL 0x3UL + +/** + * Register: XiouSlcrRamGem2 + */ +#define XIOU_SLCR_RAM_GEM2 ( ( XIOU_SLCR_BASEADDR ) + 0x00000508UL ) +#define XIOU_SLCR_RAM_GEM2_RSTVAL 0x00005b5bUL + +#define XIOU_SLCR_RAM_GEM2_EMASA1_SHIFT 14UL +#define XIOU_SLCR_RAM_GEM2_EMASA1_WIDTH 1UL +#define XIOU_SLCR_RAM_GEM2_EMASA1_MASK 0x00004000UL +#define XIOU_SLCR_RAM_GEM2_EMASA1_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_GEM2_EMAB1_SHIFT 11UL +#define XIOU_SLCR_RAM_GEM2_EMAB1_WIDTH 3UL +#define XIOU_SLCR_RAM_GEM2_EMAB1_MASK 0x00003800UL +#define XIOU_SLCR_RAM_GEM2_EMAB1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_GEM2_EMAA1_SHIFT 8UL +#define XIOU_SLCR_RAM_GEM2_EMAA1_WIDTH 3UL +#define XIOU_SLCR_RAM_GEM2_EMAA1_MASK 0x00000700UL +#define XIOU_SLCR_RAM_GEM2_EMAA1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_GEM2_EMASA0_SHIFT 6UL +#define XIOU_SLCR_RAM_GEM2_EMASA0_WIDTH 1UL +#define XIOU_SLCR_RAM_GEM2_EMASA0_MASK 0x00000040UL +#define XIOU_SLCR_RAM_GEM2_EMASA0_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_GEM2_EMAB0_SHIFT 3UL +#define XIOU_SLCR_RAM_GEM2_EMAB0_WIDTH 3UL +#define XIOU_SLCR_RAM_GEM2_EMAB0_MASK 0x00000038UL +#define XIOU_SLCR_RAM_GEM2_EMAB0_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_GEM2_EMAA0_SHIFT 0UL +#define XIOU_SLCR_RAM_GEM2_EMAA0_WIDTH 3UL +#define XIOU_SLCR_RAM_GEM2_EMAA0_MASK 0x00000007UL +#define XIOU_SLCR_RAM_GEM2_EMAA0_DEFVAL 0x3UL + +/** + * Register: XiouSlcrRamGem3 + */ +#define XIOU_SLCR_RAM_GEM3 ( ( XIOU_SLCR_BASEADDR ) + 0x0000050CUL ) +#define XIOU_SLCR_RAM_GEM3_RSTVAL 0x00005b5bUL + +#define XIOU_SLCR_RAM_GEM3_EMASA1_SHIFT 14UL +#define XIOU_SLCR_RAM_GEM3_EMASA1_WIDTH 1UL +#define XIOU_SLCR_RAM_GEM3_EMASA1_MASK 0x00004000UL +#define XIOU_SLCR_RAM_GEM3_EMASA1_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_GEM3_EMAB1_SHIFT 11UL +#define XIOU_SLCR_RAM_GEM3_EMAB1_WIDTH 3UL +#define XIOU_SLCR_RAM_GEM3_EMAB1_MASK 0x00003800UL +#define XIOU_SLCR_RAM_GEM3_EMAB1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_GEM3_EMAA1_SHIFT 8UL +#define XIOU_SLCR_RAM_GEM3_EMAA1_WIDTH 3UL +#define XIOU_SLCR_RAM_GEM3_EMAA1_MASK 0x00000700UL +#define XIOU_SLCR_RAM_GEM3_EMAA1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_GEM3_EMASA0_SHIFT 6UL +#define XIOU_SLCR_RAM_GEM3_EMASA0_WIDTH 1UL +#define XIOU_SLCR_RAM_GEM3_EMASA0_MASK 0x00000040UL +#define XIOU_SLCR_RAM_GEM3_EMASA0_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_GEM3_EMAB0_SHIFT 3UL +#define XIOU_SLCR_RAM_GEM3_EMAB0_WIDTH 3UL +#define XIOU_SLCR_RAM_GEM3_EMAB0_MASK 0x00000038UL +#define XIOU_SLCR_RAM_GEM3_EMAB0_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_GEM3_EMAA0_SHIFT 0UL +#define XIOU_SLCR_RAM_GEM3_EMAA0_WIDTH 3UL +#define XIOU_SLCR_RAM_GEM3_EMAA0_MASK 0x00000007UL +#define XIOU_SLCR_RAM_GEM3_EMAA0_DEFVAL 0x3UL + +/** + * Register: XiouSlcrRamXsdps0 + */ +#define XIOU_SLCR_RAM_XSDPS0 ( ( XIOU_SLCR_BASEADDR ) + 0x00000510UL ) +#define XIOU_SLCR_RAM_XSDPS0_RSTVAL 0x0000005bUL + +#define XIOU_SLCR_RAM_XSDPS0_EMASA0_SHIFT 6UL +#define XIOU_SLCR_RAM_XSDPS0_EMASA0_WIDTH 1UL +#define XIOU_SLCR_RAM_XSDPS0_EMASA0_MASK 0x00000040UL +#define XIOU_SLCR_RAM_XSDPS0_EMASA0_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_XSDPS0_EMAB0_SHIFT 3UL +#define XIOU_SLCR_RAM_XSDPS0_EMAB0_WIDTH 3UL +#define XIOU_SLCR_RAM_XSDPS0_EMAB0_MASK 0x00000038UL +#define XIOU_SLCR_RAM_XSDPS0_EMAB0_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XSDPS0_EMAA0_SHIFT 0UL +#define XIOU_SLCR_RAM_XSDPS0_EMAA0_WIDTH 3UL +#define XIOU_SLCR_RAM_XSDPS0_EMAA0_MASK 0x00000007UL +#define XIOU_SLCR_RAM_XSDPS0_EMAA0_DEFVAL 0x3UL + +/** + * Register: XiouSlcrRamXsdps1 + */ +#define XIOU_SLCR_RAM_XSDPS1 ( ( XIOU_SLCR_BASEADDR ) + 0x00000514UL ) +#define XIOU_SLCR_RAM_XSDPS1_RSTVAL 0x0000005bUL + +#define XIOU_SLCR_RAM_XSDPS1_EMASA0_SHIFT 6UL +#define XIOU_SLCR_RAM_XSDPS1_EMASA0_WIDTH 1UL +#define XIOU_SLCR_RAM_XSDPS1_EMASA0_MASK 0x00000040UL +#define XIOU_SLCR_RAM_XSDPS1_EMASA0_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_XSDPS1_EMAB0_SHIFT 3UL +#define XIOU_SLCR_RAM_XSDPS1_EMAB0_WIDTH 3UL +#define XIOU_SLCR_RAM_XSDPS1_EMAB0_MASK 0x00000038UL +#define XIOU_SLCR_RAM_XSDPS1_EMAB0_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XSDPS1_EMAA0_SHIFT 0UL +#define XIOU_SLCR_RAM_XSDPS1_EMAA0_WIDTH 3UL +#define XIOU_SLCR_RAM_XSDPS1_EMAA0_MASK 0x00000007UL +#define XIOU_SLCR_RAM_XSDPS1_EMAA0_DEFVAL 0x3UL + +/** + * Register: XiouSlcrRamCan0 + */ +#define XIOU_SLCR_RAM_CAN0 ( ( XIOU_SLCR_BASEADDR ) + 0x00000518UL ) +#define XIOU_SLCR_RAM_CAN0_RSTVAL 0x005b5b5bUL + +#define XIOU_SLCR_RAM_CAN0_EMASA2_SHIFT 22UL +#define XIOU_SLCR_RAM_CAN0_EMASA2_WIDTH 1UL +#define XIOU_SLCR_RAM_CAN0_EMASA2_MASK 0x00400000UL +#define XIOU_SLCR_RAM_CAN0_EMASA2_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_CAN0_EMAB2_SHIFT 19UL +#define XIOU_SLCR_RAM_CAN0_EMAB2_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN0_EMAB2_MASK 0x00380000UL +#define XIOU_SLCR_RAM_CAN0_EMAB2_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_CAN0_EMAA2_SHIFT 16UL +#define XIOU_SLCR_RAM_CAN0_EMAA2_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN0_EMAA2_MASK 0x00070000UL +#define XIOU_SLCR_RAM_CAN0_EMAA2_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_CAN0_EMASA1_SHIFT 14UL +#define XIOU_SLCR_RAM_CAN0_EMASA1_WIDTH 1UL +#define XIOU_SLCR_RAM_CAN0_EMASA1_MASK 0x00004000UL +#define XIOU_SLCR_RAM_CAN0_EMASA1_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_CAN0_EMAB1_SHIFT 11UL +#define XIOU_SLCR_RAM_CAN0_EMAB1_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN0_EMAB1_MASK 0x00003800UL +#define XIOU_SLCR_RAM_CAN0_EMAB1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_CAN0_EMAA1_SHIFT 8UL +#define XIOU_SLCR_RAM_CAN0_EMAA1_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN0_EMAA1_MASK 0x00000700UL +#define XIOU_SLCR_RAM_CAN0_EMAA1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_CAN0_EMASA0_SHIFT 6UL +#define XIOU_SLCR_RAM_CAN0_EMASA0_WIDTH 1UL +#define XIOU_SLCR_RAM_CAN0_EMASA0_MASK 0x00000040UL +#define XIOU_SLCR_RAM_CAN0_EMASA0_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_CAN0_EMAB0_SHIFT 3UL +#define XIOU_SLCR_RAM_CAN0_EMAB0_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN0_EMAB0_MASK 0x00000038UL +#define XIOU_SLCR_RAM_CAN0_EMAB0_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_CAN0_EMAA0_SHIFT 0UL +#define XIOU_SLCR_RAM_CAN0_EMAA0_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN0_EMAA0_MASK 0x00000007UL +#define XIOU_SLCR_RAM_CAN0_EMAA0_DEFVAL 0x3UL + +/** + * Register: XiouSlcrRamCan1 + */ +#define XIOU_SLCR_RAM_CAN1 ( ( XIOU_SLCR_BASEADDR ) + 0x0000051CUL ) +#define XIOU_SLCR_RAM_CAN1_RSTVAL 0x005b5b5bUL + +#define XIOU_SLCR_RAM_CAN1_EMASA2_SHIFT 22UL +#define XIOU_SLCR_RAM_CAN1_EMASA2_WIDTH 1UL +#define XIOU_SLCR_RAM_CAN1_EMASA2_MASK 0x00400000UL +#define XIOU_SLCR_RAM_CAN1_EMASA2_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_CAN1_EMAB2_SHIFT 19UL +#define XIOU_SLCR_RAM_CAN1_EMAB2_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN1_EMAB2_MASK 0x00380000UL +#define XIOU_SLCR_RAM_CAN1_EMAB2_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_CAN1_EMAA2_SHIFT 16UL +#define XIOU_SLCR_RAM_CAN1_EMAA2_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN1_EMAA2_MASK 0x00070000UL +#define XIOU_SLCR_RAM_CAN1_EMAA2_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_CAN1_EMASA1_SHIFT 14UL +#define XIOU_SLCR_RAM_CAN1_EMASA1_WIDTH 1UL +#define XIOU_SLCR_RAM_CAN1_EMASA1_MASK 0x00004000UL +#define XIOU_SLCR_RAM_CAN1_EMASA1_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_CAN1_EMAB1_SHIFT 11UL +#define XIOU_SLCR_RAM_CAN1_EMAB1_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN1_EMAB1_MASK 0x00003800UL +#define XIOU_SLCR_RAM_CAN1_EMAB1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_CAN1_EMAA1_SHIFT 8UL +#define XIOU_SLCR_RAM_CAN1_EMAA1_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN1_EMAA1_MASK 0x00000700UL +#define XIOU_SLCR_RAM_CAN1_EMAA1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_CAN1_EMASA0_SHIFT 6UL +#define XIOU_SLCR_RAM_CAN1_EMASA0_WIDTH 1UL +#define XIOU_SLCR_RAM_CAN1_EMASA0_MASK 0x00000040UL +#define XIOU_SLCR_RAM_CAN1_EMASA0_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_CAN1_EMAB0_SHIFT 3UL +#define XIOU_SLCR_RAM_CAN1_EMAB0_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN1_EMAB0_MASK 0x00000038UL +#define XIOU_SLCR_RAM_CAN1_EMAB0_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_CAN1_EMAA0_SHIFT 0UL +#define XIOU_SLCR_RAM_CAN1_EMAA0_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN1_EMAA0_MASK 0x00000007UL +#define XIOU_SLCR_RAM_CAN1_EMAA0_DEFVAL 0x3UL + +/** + * Register: XiouSlcrRamLqspi + */ +#define XIOU_SLCR_RAM_LQSPI ( ( XIOU_SLCR_BASEADDR ) + 0x00000520UL ) +#define XIOU_SLCR_RAM_LQSPI_RSTVAL 0x00002ddbUL + +#define XIOU_SLCR_RAM_LQSPI_EMASA1_SHIFT 13UL +#define XIOU_SLCR_RAM_LQSPI_EMASA1_WIDTH 1UL +#define XIOU_SLCR_RAM_LQSPI_EMASA1_MASK 0x00002000UL +#define XIOU_SLCR_RAM_LQSPI_EMASA1_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_LQSPI_EMAB1_SHIFT 10UL +#define XIOU_SLCR_RAM_LQSPI_EMAB1_WIDTH 3UL +#define XIOU_SLCR_RAM_LQSPI_EMAB1_MASK 0x00001c00UL +#define XIOU_SLCR_RAM_LQSPI_EMAB1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_LQSPI_EMAA1_SHIFT 7UL +#define XIOU_SLCR_RAM_LQSPI_EMAA1_WIDTH 3UL +#define XIOU_SLCR_RAM_LQSPI_EMAA1_MASK 0x00000380UL +#define XIOU_SLCR_RAM_LQSPI_EMAA1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_LQSPI_EMASA0_SHIFT 6UL +#define XIOU_SLCR_RAM_LQSPI_EMASA0_WIDTH 1UL +#define XIOU_SLCR_RAM_LQSPI_EMASA0_MASK 0x00000040UL +#define XIOU_SLCR_RAM_LQSPI_EMASA0_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_LQSPI_EMAB0_SHIFT 3UL +#define XIOU_SLCR_RAM_LQSPI_EMAB0_WIDTH 3UL +#define XIOU_SLCR_RAM_LQSPI_EMAB0_MASK 0x00000038UL +#define XIOU_SLCR_RAM_LQSPI_EMAB0_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_LQSPI_EMAA0_SHIFT 0UL +#define XIOU_SLCR_RAM_LQSPI_EMAA0_WIDTH 3UL +#define XIOU_SLCR_RAM_LQSPI_EMAA0_MASK 0x00000007UL +#define XIOU_SLCR_RAM_LQSPI_EMAA0_DEFVAL 0x3UL + +/** + * Register: XiouSlcrRamXnandps8 + */ +#define XIOU_SLCR_RAM_XNANDPS8 ( ( XIOU_SLCR_BASEADDR ) + 0x00000524UL ) +#define XIOU_SLCR_RAM_XNANDPS8_RSTVAL 0x0000005bUL + +#define XIOU_SLCR_RAM_XNANDPS8_EMASA0_SHIFT 6UL +#define XIOU_SLCR_RAM_XNANDPS8_EMASA0_WIDTH 1UL +#define XIOU_SLCR_RAM_XNANDPS8_EMASA0_MASK 0x00000040UL +#define XIOU_SLCR_RAM_XNANDPS8_EMASA0_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_XNANDPS8_EMAB0_SHIFT 3UL +#define XIOU_SLCR_RAM_XNANDPS8_EMAB0_WIDTH 3UL +#define XIOU_SLCR_RAM_XNANDPS8_EMAB0_MASK 0x00000038UL +#define XIOU_SLCR_RAM_XNANDPS8_EMAB0_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XNANDPS8_EMAA0_SHIFT 0UL +#define XIOU_SLCR_RAM_XNANDPS8_EMAA0_WIDTH 3UL +#define XIOU_SLCR_RAM_XNANDPS8_EMAA0_MASK 0x00000007UL +#define XIOU_SLCR_RAM_XNANDPS8_EMAA0_DEFVAL 0x3UL + +/** + * Register: XiouSlcrCtrl + */ +#define XIOU_SLCR_CTRL ( ( XIOU_SLCR_BASEADDR ) + 0x00000600UL ) +#define XIOU_SLCR_CTRL_RSTVAL 0x00000000UL + +#define XIOU_SLCR_CTRL_SLVERR_EN_SHIFT 0UL +#define XIOU_SLCR_CTRL_SLVERR_EN_WIDTH 1UL +#define XIOU_SLCR_CTRL_SLVERR_EN_MASK 0x00000001UL +#define XIOU_SLCR_CTRL_SLVERR_EN_DEFVAL 0x0UL + +/** + * Register: XiouSlcrIsr + */ +#define XIOU_SLCR_ISR ( ( XIOU_SLCR_BASEADDR ) + 0x00000700UL ) +#define XIOU_SLCR_ISR_RSTVAL 0x00000000UL + +#define XIOU_SLCR_ISR_ADDR_DECD_ERR_SHIFT 0UL +#define XIOU_SLCR_ISR_ADDR_DECD_ERR_WIDTH 1UL +#define XIOU_SLCR_ISR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XIOU_SLCR_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XiouSlcrImr + */ +#define XIOU_SLCR_IMR ( ( XIOU_SLCR_BASEADDR ) + 0x00000704UL ) +#define XIOU_SLCR_IMR_RSTVAL 0x00000001UL + +#define XIOU_SLCR_IMR_ADDR_DECD_ERR_SHIFT 0UL +#define XIOU_SLCR_IMR_ADDR_DECD_ERR_WIDTH 1UL +#define XIOU_SLCR_IMR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XIOU_SLCR_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL + +/** + * Register: XiouSlcrIer + */ +#define XIOU_SLCR_IER ( ( XIOU_SLCR_BASEADDR ) + 0x00000708UL ) +#define XIOU_SLCR_IER_RSTVAL 0x00000000UL + +#define XIOU_SLCR_IER_ADDR_DECD_ERR_SHIFT 0UL +#define XIOU_SLCR_IER_ADDR_DECD_ERR_WIDTH 1UL +#define XIOU_SLCR_IER_ADDR_DECD_ERR_MASK 0x00000001UL +#define XIOU_SLCR_IER_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XiouSlcrIdr + */ +#define XIOU_SLCR_IDR ( ( XIOU_SLCR_BASEADDR ) + 0x0000070CUL ) +#define XIOU_SLCR_IDR_RSTVAL 0x00000000UL + +#define XIOU_SLCR_IDR_ADDR_DECD_ERR_SHIFT 0UL +#define XIOU_SLCR_IDR_ADDR_DECD_ERR_WIDTH 1UL +#define XIOU_SLCR_IDR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XIOU_SLCR_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XiouSlcrItr + */ +#define XIOU_SLCR_ITR ( ( XIOU_SLCR_BASEADDR ) + 0x00000710UL ) +#define XIOU_SLCR_ITR_RSTVAL 0x00000000UL + +#define XIOU_SLCR_ITR_ADDR_DECD_ERR_SHIFT 0UL +#define XIOU_SLCR_ITR_ADDR_DECD_ERR_WIDTH 1UL +#define XIOU_SLCR_ITR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XIOU_SLCR_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XIOU_SLCR_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xlpd_slcr.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xlpd_slcr.h new file mode 100644 index 0000000..cc05672 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xlpd_slcr.h
@@ -0,0 +1,5667 @@ +/* ### HEADER ### */ + +#ifndef __XLPD_SLCR_H__ +#define __XLPD_SLCR_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XlpdSlcr Base Address + */ +#define XLPD_SLCR_BASEADDR 0xFF410000UL + +/** + * Register: XlpdSlcrWprot0 + */ +#define XLPD_SLCR_WPROT0 ( ( XLPD_SLCR_BASEADDR ) + 0x00000000UL ) +#define XLPD_SLCR_WPROT0_RSTVAL 0x00000001UL + +#define XLPD_SLCR_WPROT0_ACT_SHIFT 0UL +#define XLPD_SLCR_WPROT0_ACT_WIDTH 1UL +#define XLPD_SLCR_WPROT0_ACT_MASK 0x00000001UL +#define XLPD_SLCR_WPROT0_ACT_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrCtrl + */ +#define XLPD_SLCR_CTRL ( ( XLPD_SLCR_BASEADDR ) + 0x00000004UL ) +#define XLPD_SLCR_CTRL_RSTVAL 0x00000000UL + +#define XLPD_SLCR_CTRL_SLVERR_EN_SHIFT 0UL +#define XLPD_SLCR_CTRL_SLVERR_EN_WIDTH 1UL +#define XLPD_SLCR_CTRL_SLVERR_EN_MASK 0x00000001UL +#define XLPD_SLCR_CTRL_SLVERR_EN_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrIsr + */ +#define XLPD_SLCR_ISR ( ( XLPD_SLCR_BASEADDR ) + 0x00000008UL ) +#define XLPD_SLCR_ISR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ISR_ADDR_DECD_ERR_SHIFT 0UL +#define XLPD_SLCR_ISR_ADDR_DECD_ERR_WIDTH 1UL +#define XLPD_SLCR_ISR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XLPD_SLCR_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrImr + */ +#define XLPD_SLCR_IMR ( ( XLPD_SLCR_BASEADDR ) + 0x0000000CUL ) +#define XLPD_SLCR_IMR_RSTVAL 0x00000001UL + +#define XLPD_SLCR_IMR_ADDR_DECD_ERR_SHIFT 0UL +#define XLPD_SLCR_IMR_ADDR_DECD_ERR_WIDTH 1UL +#define XLPD_SLCR_IMR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XLPD_SLCR_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrIer + */ +#define XLPD_SLCR_IER ( ( XLPD_SLCR_BASEADDR ) + 0x00000010UL ) +#define XLPD_SLCR_IER_RSTVAL 0x00000000UL + +#define XLPD_SLCR_IER_ADDR_DECD_ERR_SHIFT 0UL +#define XLPD_SLCR_IER_ADDR_DECD_ERR_WIDTH 1UL +#define XLPD_SLCR_IER_ADDR_DECD_ERR_MASK 0x00000001UL +#define XLPD_SLCR_IER_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrIdr + */ +#define XLPD_SLCR_IDR ( ( XLPD_SLCR_BASEADDR ) + 0x00000014UL ) +#define XLPD_SLCR_IDR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_IDR_ADDR_DECD_ERR_SHIFT 0UL +#define XLPD_SLCR_IDR_ADDR_DECD_ERR_WIDTH 1UL +#define XLPD_SLCR_IDR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XLPD_SLCR_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrItr + */ +#define XLPD_SLCR_ITR ( ( XLPD_SLCR_BASEADDR ) + 0x00000018UL ) +#define XLPD_SLCR_ITR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ITR_ADDR_DECD_ERR_SHIFT 0UL +#define XLPD_SLCR_ITR_ADDR_DECD_ERR_WIDTH 1UL +#define XLPD_SLCR_ITR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XLPD_SLCR_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSafetyChk0 + */ +#define XLPD_SLCR_SAFETY_CHK0 ( ( XLPD_SLCR_BASEADDR ) + 0x00000040UL ) +#define XLPD_SLCR_SAFETY_CHK0_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SAFETY_CHK0_VAL_SHIFT 0UL +#define XLPD_SLCR_SAFETY_CHK0_VAL_WIDTH 32UL +#define XLPD_SLCR_SAFETY_CHK0_VAL_MASK 0xffffffffUL +#define XLPD_SLCR_SAFETY_CHK0_VAL_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSafetyChk1 + */ +#define XLPD_SLCR_SAFETY_CHK1 ( ( XLPD_SLCR_BASEADDR ) + 0x00000044UL ) +#define XLPD_SLCR_SAFETY_CHK1_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SAFETY_CHK1_VAL_SHIFT 0UL +#define XLPD_SLCR_SAFETY_CHK1_VAL_WIDTH 32UL +#define XLPD_SLCR_SAFETY_CHK1_VAL_MASK 0xffffffffUL +#define XLPD_SLCR_SAFETY_CHK1_VAL_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSafetyChk2 + */ +#define XLPD_SLCR_SAFETY_CHK2 ( ( XLPD_SLCR_BASEADDR ) + 0x00000048UL ) +#define XLPD_SLCR_SAFETY_CHK2_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SAFETY_CHK2_VAL_SHIFT 0UL +#define XLPD_SLCR_SAFETY_CHK2_VAL_WIDTH 32UL +#define XLPD_SLCR_SAFETY_CHK2_VAL_MASK 0xffffffffUL +#define XLPD_SLCR_SAFETY_CHK2_VAL_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSafetyChk3 + */ +#define XLPD_SLCR_SAFETY_CHK3 ( ( XLPD_SLCR_BASEADDR ) + 0x0000004CUL ) +#define XLPD_SLCR_SAFETY_CHK3_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SAFETY_CHK3_VAL_SHIFT 0UL +#define XLPD_SLCR_SAFETY_CHK3_VAL_WIDTH 32UL +#define XLPD_SLCR_SAFETY_CHK3_VAL_MASK 0xffffffffUL +#define XLPD_SLCR_SAFETY_CHK3_VAL_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrXcsupmuWdtClkSel + */ +#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL ( ( XLPD_SLCR_BASEADDR ) + 0x00000050UL ) +#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_RSTVAL 0x00000000UL + +#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_SHIFT 0UL +#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_WIDTH 1UL +#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_MASK 0x00000001UL +#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrAdmaCfg + */ +#define XLPD_SLCR_ADMA_CFG ( ( XLPD_SLCR_BASEADDR ) + 0x0000200CUL ) +#define XLPD_SLCR_ADMA_CFG_RSTVAL 0x00000028UL + +#define XLPD_SLCR_ADMA_CFG_BUSWID_SHIFT 5UL +#define XLPD_SLCR_ADMA_CFG_BUSWID_WIDTH 2UL +#define XLPD_SLCR_ADMA_CFG_BUSWID_MASK 0x00000060UL +#define XLPD_SLCR_ADMA_CFG_BUSWID_DEFVAL 0x1UL + +#define XLPD_SLCR_ADMA_CFG_NUM_CH_SHIFT 0UL +#define XLPD_SLCR_ADMA_CFG_NUM_CH_WIDTH 5UL +#define XLPD_SLCR_ADMA_CFG_NUM_CH_MASK 0x0000001fUL +#define XLPD_SLCR_ADMA_CFG_NUM_CH_DEFVAL 0x8UL + +/** + * Register: XlpdSlcrAdmaRam + */ +#define XLPD_SLCR_ADMA_RAM ( ( XLPD_SLCR_BASEADDR ) + 0x00002010UL ) +#define XLPD_SLCR_ADMA_RAM_RSTVAL 0x00003b3bUL + +#define XLPD_SLCR_ADMA_RAM1_EMAB_SHIFT 12UL +#define XLPD_SLCR_ADMA_RAM1_EMAB_WIDTH 3UL +#define XLPD_SLCR_ADMA_RAM1_EMAB_MASK 0x00007000UL +#define XLPD_SLCR_ADMA_RAM1_EMAB_DEFVAL 0x3UL + +#define XLPD_SLCR_ADMA_RAM1_EMASA_SHIFT 11UL +#define XLPD_SLCR_ADMA_RAM1_EMASA_WIDTH 1UL +#define XLPD_SLCR_ADMA_RAM1_EMASA_MASK 0x00000800UL +#define XLPD_SLCR_ADMA_RAM1_EMASA_DEFVAL 0x1UL + +#define XLPD_SLCR_ADMA_RAM1_EMAA_SHIFT 8UL +#define XLPD_SLCR_ADMA_RAM1_EMAA_WIDTH 3UL +#define XLPD_SLCR_ADMA_RAM1_EMAA_MASK 0x00000700UL +#define XLPD_SLCR_ADMA_RAM1_EMAA_DEFVAL 0x3UL + +#define XLPD_SLCR_ADMA_RAM0_EMAB_SHIFT 4UL +#define XLPD_SLCR_ADMA_RAM0_EMAB_WIDTH 3UL +#define XLPD_SLCR_ADMA_RAM0_EMAB_MASK 0x00000070UL +#define XLPD_SLCR_ADMA_RAM0_EMAB_DEFVAL 0x3UL + +#define XLPD_SLCR_ADMA_RAM0_EMASA_SHIFT 3UL +#define XLPD_SLCR_ADMA_RAM0_EMASA_WIDTH 1UL +#define XLPD_SLCR_ADMA_RAM0_EMASA_MASK 0x00000008UL +#define XLPD_SLCR_ADMA_RAM0_EMASA_DEFVAL 0x1UL + +#define XLPD_SLCR_ADMA_RAM0_EMAA_SHIFT 0UL +#define XLPD_SLCR_ADMA_RAM0_EMAA_WIDTH 3UL +#define XLPD_SLCR_ADMA_RAM0_EMAA_MASK 0x00000007UL +#define XLPD_SLCR_ADMA_RAM0_EMAA_DEFVAL 0x3UL + +/** + * Register: XlpdSlcrErrAibaxiIsr + */ +#define XLPD_SLCR_ERR_AIBAXI_ISR ( ( XLPD_SLCR_BASEADDR ) + 0x00003000UL ) +#define XLPD_SLCR_ERR_AIBAXI_ISR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS2_SHIFT 28UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS2_MASK 0x10000000UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS2_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_DDR_SHIFT 27UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_DDR_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_DDR_MASK 0x08000000UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_DDR_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_OCMS_SHIFT 26UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_OCMS_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_OCMS_MASK 0x04000000UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_OCMS_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_MAIN_SHIFT 24UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_MAIN_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_MAIN_MASK 0x01000000UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_MAIN_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_USB1S_SHIFT 23UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_USB1S_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_USB1S_MASK 0x00800000UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_USB1S_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_USB0S_SHIFT 22UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_USB0S_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_USB0S_MASK 0x00400000UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_USB0S_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS1_SHIFT 19UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS1_MASK 0x00080000UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS1_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS0_SHIFT 18UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS0_MASK 0x00040000UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS0_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM1_SHIFT 17UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM1_MASK 0x00020000UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM1_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM0_SHIFT 16UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM0_MASK 0x00010000UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM0_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_OCM_SHIFT 3UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_OCM_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_OCM_MASK 0x00000008UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_OCM_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_LPDIBS_SHIFT 2UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_LPDIBS_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_LPDIBS_MASK 0x00000004UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_LPDIBS_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS1_SHIFT 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS1_MASK 0x00000002UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS1_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS0_SHIFT 0UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS0_MASK 0x00000001UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrErrAibaxiImr + */ +#define XLPD_SLCR_ERR_AIBAXI_IMR ( ( XLPD_SLCR_BASEADDR ) + 0x00003008UL ) +#define XLPD_SLCR_ERR_AIBAXI_IMR_RSTVAL 0x1dcf000fUL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS2_SHIFT 28UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS2_MASK 0x10000000UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS2_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_DDR_SHIFT 27UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_DDR_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_DDR_MASK 0x08000000UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_DDR_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_OCMS_SHIFT 26UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_OCMS_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_OCMS_MASK 0x04000000UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_OCMS_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_MAIN_SHIFT 24UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_MAIN_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_MAIN_MASK 0x01000000UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_MAIN_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_USB1S_SHIFT 23UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_USB1S_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_USB1S_MASK 0x00800000UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_USB1S_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_USB0S_SHIFT 22UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_USB0S_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_USB0S_MASK 0x00400000UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_USB0S_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS1_SHIFT 19UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS1_MASK 0x00080000UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS1_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS0_SHIFT 18UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS0_MASK 0x00040000UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS0_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM1_SHIFT 17UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM1_MASK 0x00020000UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM1_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM0_SHIFT 16UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM0_MASK 0x00010000UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM0_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_OCM_SHIFT 3UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_OCM_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_OCM_MASK 0x00000008UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_OCM_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_LPDIBS_SHIFT 2UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_LPDIBS_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_LPDIBS_MASK 0x00000004UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_LPDIBS_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS1_SHIFT 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS1_MASK 0x00000002UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS1_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS0_SHIFT 0UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS0_MASK 0x00000001UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS0_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrErrAibaxiIer + */ +#define XLPD_SLCR_ERR_AIBAXI_IER ( ( XLPD_SLCR_BASEADDR ) + 0x00003010UL ) +#define XLPD_SLCR_ERR_AIBAXI_IER_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS2_SHIFT 28UL +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS2_MASK 0x10000000UL +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS2_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_DDR_SHIFT 27UL +#define XLPD_SLCR_ERR_AIBAXI_IER_DDR_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_DDR_MASK 0x08000000UL +#define XLPD_SLCR_ERR_AIBAXI_IER_DDR_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_OCMS_SHIFT 26UL +#define XLPD_SLCR_ERR_AIBAXI_IER_OCMS_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_OCMS_MASK 0x04000000UL +#define XLPD_SLCR_ERR_AIBAXI_IER_OCMS_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_MAIN_SHIFT 24UL +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_MAIN_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_MAIN_MASK 0x01000000UL +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_MAIN_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_USB1S_SHIFT 23UL +#define XLPD_SLCR_ERR_AIBAXI_IER_USB1S_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_USB1S_MASK 0x00800000UL +#define XLPD_SLCR_ERR_AIBAXI_IER_USB1S_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_USB0S_SHIFT 22UL +#define XLPD_SLCR_ERR_AIBAXI_IER_USB0S_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_USB0S_MASK 0x00400000UL +#define XLPD_SLCR_ERR_AIBAXI_IER_USB0S_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS1_SHIFT 19UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS1_MASK 0x00080000UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS1_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS0_SHIFT 18UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS0_MASK 0x00040000UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS0_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM1_SHIFT 17UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM1_MASK 0x00020000UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM1_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM0_SHIFT 16UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM0_MASK 0x00010000UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM0_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_OCM_SHIFT 3UL +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_OCM_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_OCM_MASK 0x00000008UL +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_OCM_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_LPDIBS_SHIFT 2UL +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_LPDIBS_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_LPDIBS_MASK 0x00000004UL +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_LPDIBS_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS1_SHIFT 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS1_MASK 0x00000002UL +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS1_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS0_SHIFT 0UL +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS0_MASK 0x00000001UL +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrErrAibaxiIdr + */ +#define XLPD_SLCR_ERR_AIBAXI_IDR ( ( XLPD_SLCR_BASEADDR ) + 0x00003018UL ) +#define XLPD_SLCR_ERR_AIBAXI_IDR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS2_SHIFT 28UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS2_MASK 0x10000000UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS2_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_DDR_SHIFT 27UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_DDR_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_DDR_MASK 0x08000000UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_DDR_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_OCMS_SHIFT 26UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_OCMS_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_OCMS_MASK 0x04000000UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_OCMS_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_MAIN_SHIFT 24UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_MAIN_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_MAIN_MASK 0x01000000UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_MAIN_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_USB1S_SHIFT 23UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_USB1S_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_USB1S_MASK 0x00800000UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_USB1S_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_USB0S_SHIFT 22UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_USB0S_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_USB0S_MASK 0x00400000UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_USB0S_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS1_SHIFT 19UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS1_MASK 0x00080000UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS1_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS0_SHIFT 18UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS0_MASK 0x00040000UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS0_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM1_SHIFT 17UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM1_MASK 0x00020000UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM1_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM0_SHIFT 16UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM0_MASK 0x00010000UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM0_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_OCM_SHIFT 3UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_OCM_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_OCM_MASK 0x00000008UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_OCM_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_LPDIBS_SHIFT 2UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_LPDIBS_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_LPDIBS_MASK 0x00000004UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_LPDIBS_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS1_SHIFT 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS1_MASK 0x00000002UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS1_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS0_SHIFT 0UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS0_MASK 0x00000001UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrErrAibapbIsr + */ +#define XLPD_SLCR_ERR_AIBAPB_ISR ( ( XLPD_SLCR_BASEADDR ) + 0x00003020UL ) +#define XLPD_SLCR_ERR_AIBAPB_ISR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ERR_AIBAPB_ISR_GPU_SHIFT 0UL +#define XLPD_SLCR_ERR_AIBAPB_ISR_GPU_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAPB_ISR_GPU_MASK 0x00000001UL +#define XLPD_SLCR_ERR_AIBAPB_ISR_GPU_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrErrAibapbImr + */ +#define XLPD_SLCR_ERR_AIBAPB_IMR ( ( XLPD_SLCR_BASEADDR ) + 0x00003024UL ) +#define XLPD_SLCR_ERR_AIBAPB_IMR_RSTVAL 0x00000001UL + +#define XLPD_SLCR_ERR_AIBAPB_IMR_GPU_SHIFT 0UL +#define XLPD_SLCR_ERR_AIBAPB_IMR_GPU_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAPB_IMR_GPU_MASK 0x00000001UL +#define XLPD_SLCR_ERR_AIBAPB_IMR_GPU_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrErrAibapbIer + */ +#define XLPD_SLCR_ERR_AIBAPB_IER ( ( XLPD_SLCR_BASEADDR ) + 0x00003028UL ) +#define XLPD_SLCR_ERR_AIBAPB_IER_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ERR_AIBAPB_IER_GPU_SHIFT 0UL +#define XLPD_SLCR_ERR_AIBAPB_IER_GPU_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAPB_IER_GPU_MASK 0x00000001UL +#define XLPD_SLCR_ERR_AIBAPB_IER_GPU_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrErrAibapbIdr + */ +#define XLPD_SLCR_ERR_AIBAPB_IDR ( ( XLPD_SLCR_BASEADDR ) + 0x0000302CUL ) +#define XLPD_SLCR_ERR_AIBAPB_IDR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ERR_AIBAPB_IDR_GPU_SHIFT 0UL +#define XLPD_SLCR_ERR_AIBAPB_IDR_GPU_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAPB_IDR_GPU_MASK 0x00000001UL +#define XLPD_SLCR_ERR_AIBAPB_IDR_GPU_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrIsoAibaxiReq + */ +#define XLPD_SLCR_ISO_AIBAXI_REQ ( ( XLPD_SLCR_BASEADDR ) + 0x00003030UL ) +#define XLPD_SLCR_ISO_AIBAXI_REQ_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS2_SHIFT 28UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS2_MASK 0x10000000UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS2_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_DDR_SHIFT 27UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_DDR_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_DDR_MASK 0x08000000UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_DDR_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_OCMS_SHIFT 26UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_OCMS_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_OCMS_MASK 0x04000000UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_OCMS_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_MAIN_SHIFT 24UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_MAIN_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_MAIN_MASK 0x01000000UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_MAIN_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_USB1S_SHIFT 23UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_USB1S_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_USB1S_MASK 0x00800000UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_USB1S_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_USB0S_SHIFT 22UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_USB0S_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_USB0S_MASK 0x00400000UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_USB0S_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS1_SHIFT 19UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS1_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS1_MASK 0x00080000UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS1_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS0_SHIFT 18UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS0_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS0_MASK 0x00040000UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS0_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM1_SHIFT 17UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM1_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM1_MASK 0x00020000UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM1_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM0_SHIFT 16UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM0_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM0_MASK 0x00010000UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM0_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_OCM_SHIFT 3UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_OCM_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_OCM_MASK 0x00000008UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_OCM_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_LPDIBS_SHIFT 2UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_LPDIBS_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_LPDIBS_MASK 0x00000004UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_LPDIBS_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS1_SHIFT 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS1_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS1_MASK 0x00000002UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS1_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS0_SHIFT 0UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS0_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS0_MASK 0x00000001UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrIsoAibaxiType + */ +#define XLPD_SLCR_ISO_AIBAXI_TYPE ( ( XLPD_SLCR_BASEADDR ) + 0x00003038UL ) +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RSTVAL 0x19cf000fUL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS2_SHIFT 28UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS2_MASK 0x10000000UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS2_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_DDR_SHIFT 27UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_DDR_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_DDR_MASK 0x08000000UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_DDR_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_OCMS_SHIFT 26UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_OCMS_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_OCMS_MASK 0x04000000UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_OCMS_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_MAIN_SHIFT 24UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_MAIN_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_MAIN_MASK 0x01000000UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_MAIN_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB1S_SHIFT 23UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB1S_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB1S_MASK 0x00800000UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB1S_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB0S_SHIFT 22UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB0S_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB0S_MASK 0x00400000UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB0S_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS1_SHIFT 19UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS1_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS1_MASK 0x00080000UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS1_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS0_SHIFT 18UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS0_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS0_MASK 0x00040000UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS0_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM1_SHIFT 17UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM1_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM1_MASK 0x00020000UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM1_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM0_SHIFT 16UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM0_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM0_MASK 0x00010000UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM0_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_OCM_SHIFT 3UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_OCM_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_OCM_MASK 0x00000008UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_OCM_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_LPDIBS_SHIFT 2UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_LPDIBS_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_LPDIBS_MASK 0x00000004UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_LPDIBS_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS1_SHIFT 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS1_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS1_MASK 0x00000002UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS1_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS0_SHIFT 0UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS0_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS0_MASK 0x00000001UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS0_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrIsoAibaxiAck + */ +#define XLPD_SLCR_ISO_AIBAXI_ACK ( ( XLPD_SLCR_BASEADDR ) + 0x00003040UL ) +#define XLPD_SLCR_ISO_AIBAXI_ACK_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS2_SHIFT 28UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS2_MASK 0x10000000UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS2_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_DDR_SHIFT 27UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_DDR_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_DDR_MASK 0x08000000UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_DDR_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_OCMS_SHIFT 26UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_OCMS_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_OCMS_MASK 0x04000000UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_OCMS_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_MAIN_SHIFT 24UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_MAIN_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_MAIN_MASK 0x01000000UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_MAIN_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_USB1S_SHIFT 23UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_USB1S_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_USB1S_MASK 0x00800000UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_USB1S_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_USB0S_SHIFT 22UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_USB0S_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_USB0S_MASK 0x00400000UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_USB0S_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS1_SHIFT 19UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS1_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS1_MASK 0x00080000UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS1_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS0_SHIFT 18UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS0_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS0_MASK 0x00040000UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS0_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM1_SHIFT 17UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM1_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM1_MASK 0x00020000UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM1_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM0_SHIFT 16UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM0_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM0_MASK 0x00010000UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM0_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_OCM_SHIFT 3UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_OCM_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_OCM_MASK 0x00000008UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_OCM_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_LPDIBS_SHIFT 2UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_LPDIBS_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_LPDIBS_MASK 0x00000004UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_LPDIBS_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS1_SHIFT 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS1_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS1_MASK 0x00000002UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS1_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS0_SHIFT 0UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS0_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS0_MASK 0x00000001UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrIsoAibapbReq + */ +#define XLPD_SLCR_ISO_AIBAPB_REQ ( ( XLPD_SLCR_BASEADDR ) + 0x00003048UL ) +#define XLPD_SLCR_ISO_AIBAPB_REQ_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ISO_AIBAPB_REQ_GPU_SHIFT 0UL +#define XLPD_SLCR_ISO_AIBAPB_REQ_GPU_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAPB_REQ_GPU_MASK 0x00000001UL +#define XLPD_SLCR_ISO_AIBAPB_REQ_GPU_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrIsoAibapbType + */ +#define XLPD_SLCR_ISO_AIBAPB_TYPE ( ( XLPD_SLCR_BASEADDR ) + 0x0000304CUL ) +#define XLPD_SLCR_ISO_AIBAPB_TYPE_RSTVAL 0x00000001UL + +#define XLPD_SLCR_ISO_AIBAPB_TYPE_GPU_SHIFT 0UL +#define XLPD_SLCR_ISO_AIBAPB_TYPE_GPU_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAPB_TYPE_GPU_MASK 0x00000001UL +#define XLPD_SLCR_ISO_AIBAPB_TYPE_GPU_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrIsoAibapbAck + */ +#define XLPD_SLCR_ISO_AIBAPB_ACK ( ( XLPD_SLCR_BASEADDR ) + 0x00003050UL ) +#define XLPD_SLCR_ISO_AIBAPB_ACK_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ISO_AIBAPB_ACK_GPU_SHIFT 0UL +#define XLPD_SLCR_ISO_AIBAPB_ACK_GPU_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAPB_ACK_GPU_MASK 0x00000001UL +#define XLPD_SLCR_ISO_AIBAPB_ACK_GPU_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrErrAtbIsr + */ +#define XLPD_SLCR_ERR_ATB_ISR ( ( XLPD_SLCR_BASEADDR ) + 0x00006000UL ) +#define XLPD_SLCR_ERR_ATB_ISR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ERR_ATB_ISR_AFIFS2_SHIFT 1UL +#define XLPD_SLCR_ERR_ATB_ISR_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ERR_ATB_ISR_AFIFS2_MASK 0x00000002UL +#define XLPD_SLCR_ERR_ATB_ISR_AFIFS2_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_ATB_ISR_LPDM_SHIFT 0UL +#define XLPD_SLCR_ERR_ATB_ISR_LPDM_WIDTH 1UL +#define XLPD_SLCR_ERR_ATB_ISR_LPDM_MASK 0x00000001UL +#define XLPD_SLCR_ERR_ATB_ISR_LPDM_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrErrAtbImr + */ +#define XLPD_SLCR_ERR_ATB_IMR ( ( XLPD_SLCR_BASEADDR ) + 0x00006004UL ) +#define XLPD_SLCR_ERR_ATB_IMR_RSTVAL 0x00000003UL + +#define XLPD_SLCR_ERR_ATB_IMR_AFIFS2_SHIFT 1UL +#define XLPD_SLCR_ERR_ATB_IMR_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ERR_ATB_IMR_AFIFS2_MASK 0x00000002UL +#define XLPD_SLCR_ERR_ATB_IMR_AFIFS2_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_ATB_IMR_LPDM_SHIFT 0UL +#define XLPD_SLCR_ERR_ATB_IMR_LPDM_WIDTH 1UL +#define XLPD_SLCR_ERR_ATB_IMR_LPDM_MASK 0x00000001UL +#define XLPD_SLCR_ERR_ATB_IMR_LPDM_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrErrAtbIer + */ +#define XLPD_SLCR_ERR_ATB_IER ( ( XLPD_SLCR_BASEADDR ) + 0x00006008UL ) +#define XLPD_SLCR_ERR_ATB_IER_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ERR_ATB_IER_AFIFS2_SHIFT 1UL +#define XLPD_SLCR_ERR_ATB_IER_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ERR_ATB_IER_AFIFS2_MASK 0x00000002UL +#define XLPD_SLCR_ERR_ATB_IER_AFIFS2_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_ATB_IER_LPDM_SHIFT 0UL +#define XLPD_SLCR_ERR_ATB_IER_LPDM_WIDTH 1UL +#define XLPD_SLCR_ERR_ATB_IER_LPDM_MASK 0x00000001UL +#define XLPD_SLCR_ERR_ATB_IER_LPDM_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrErrAtbIdr + */ +#define XLPD_SLCR_ERR_ATB_IDR ( ( XLPD_SLCR_BASEADDR ) + 0x0000600CUL ) +#define XLPD_SLCR_ERR_ATB_IDR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ERR_ATB_IDR_AFIFS2_SHIFT 1UL +#define XLPD_SLCR_ERR_ATB_IDR_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ERR_ATB_IDR_AFIFS2_MASK 0x00000002UL +#define XLPD_SLCR_ERR_ATB_IDR_AFIFS2_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_ATB_IDR_LPDM_SHIFT 0UL +#define XLPD_SLCR_ERR_ATB_IDR_LPDM_WIDTH 1UL +#define XLPD_SLCR_ERR_ATB_IDR_LPDM_MASK 0x00000001UL +#define XLPD_SLCR_ERR_ATB_IDR_LPDM_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrAtbCmdStoreEn + */ +#define XLPD_SLCR_ATB_CMD_STORE_EN ( ( XLPD_SLCR_BASEADDR ) + 0x00006010UL ) +#define XLPD_SLCR_ATB_CMD_STORE_EN_RSTVAL 0x00000003UL + +#define XLPD_SLCR_ATB_CMD_STORE_EN_AFIFS2_SHIFT 1UL +#define XLPD_SLCR_ATB_CMD_STORE_EN_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ATB_CMD_STORE_EN_AFIFS2_MASK 0x00000002UL +#define XLPD_SLCR_ATB_CMD_STORE_EN_AFIFS2_DEFVAL 0x1UL + +#define XLPD_SLCR_ATB_CMD_STORE_EN_LPDM_SHIFT 0UL +#define XLPD_SLCR_ATB_CMD_STORE_EN_LPDM_WIDTH 1UL +#define XLPD_SLCR_ATB_CMD_STORE_EN_LPDM_MASK 0x00000001UL +#define XLPD_SLCR_ATB_CMD_STORE_EN_LPDM_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrAtbRespEn + */ +#define XLPD_SLCR_ATB_RESP_EN ( ( XLPD_SLCR_BASEADDR ) + 0x00006014UL ) +#define XLPD_SLCR_ATB_RESP_EN_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ATB_RESP_EN_AFIFS2_SHIFT 1UL +#define XLPD_SLCR_ATB_RESP_EN_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ATB_RESP_EN_AFIFS2_MASK 0x00000002UL +#define XLPD_SLCR_ATB_RESP_EN_AFIFS2_DEFVAL 0x0UL + +#define XLPD_SLCR_ATB_RESP_EN_LPDM_SHIFT 0UL +#define XLPD_SLCR_ATB_RESP_EN_LPDM_WIDTH 1UL +#define XLPD_SLCR_ATB_RESP_EN_LPDM_MASK 0x00000001UL +#define XLPD_SLCR_ATB_RESP_EN_LPDM_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrAtbRespType + */ +#define XLPD_SLCR_ATB_RESP_TYPE ( ( XLPD_SLCR_BASEADDR ) + 0x00006018UL ) +#define XLPD_SLCR_ATB_RESP_TYPE_RSTVAL 0x00000003UL + +#define XLPD_SLCR_ATB_RESP_TYPE_AFIFS2_SHIFT 1UL +#define XLPD_SLCR_ATB_RESP_TYPE_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ATB_RESP_TYPE_AFIFS2_MASK 0x00000002UL +#define XLPD_SLCR_ATB_RESP_TYPE_AFIFS2_DEFVAL 0x1UL + +#define XLPD_SLCR_ATB_RESP_TYPE_LPDM_SHIFT 0UL +#define XLPD_SLCR_ATB_RESP_TYPE_LPDM_WIDTH 1UL +#define XLPD_SLCR_ATB_RESP_TYPE_LPDM_MASK 0x00000001UL +#define XLPD_SLCR_ATB_RESP_TYPE_LPDM_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrAtbPrescale + */ +#define XLPD_SLCR_ATB_PRESCALE ( ( XLPD_SLCR_BASEADDR ) + 0x00006020UL ) +#define XLPD_SLCR_ATB_PRESCALE_RSTVAL 0x0000ffffUL + +#define XLPD_SLCR_ATB_PRESCALE_EN_SHIFT 16UL +#define XLPD_SLCR_ATB_PRESCALE_EN_WIDTH 1UL +#define XLPD_SLCR_ATB_PRESCALE_EN_MASK 0x00010000UL +#define XLPD_SLCR_ATB_PRESCALE_EN_DEFVAL 0x0UL + +#define XLPD_SLCR_ATB_PRESCALE_VAL_SHIFT 0UL +#define XLPD_SLCR_ATB_PRESCALE_VAL_WIDTH 16UL +#define XLPD_SLCR_ATB_PRESCALE_VAL_MASK 0x0000ffffUL +#define XLPD_SLCR_ATB_PRESCALE_VAL_DEFVAL 0xffffUL + +/** + * Register: XlpdSlcrMutex0 + */ +#define XLPD_SLCR_MUTEX0 ( ( XLPD_SLCR_BASEADDR ) + 0x00007000UL ) +#define XLPD_SLCR_MUTEX0_RSTVAL 0x00000000UL + +#define XLPD_SLCR_MUTEX0_ID_SHIFT 0UL +#define XLPD_SLCR_MUTEX0_ID_WIDTH 32UL +#define XLPD_SLCR_MUTEX0_ID_MASK 0xffffffffUL +#define XLPD_SLCR_MUTEX0_ID_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrMutex1 + */ +#define XLPD_SLCR_MUTEX1 ( ( XLPD_SLCR_BASEADDR ) + 0x00007004UL ) +#define XLPD_SLCR_MUTEX1_RSTVAL 0x00000000UL + +#define XLPD_SLCR_MUTEX1_ID_SHIFT 0UL +#define XLPD_SLCR_MUTEX1_ID_WIDTH 32UL +#define XLPD_SLCR_MUTEX1_ID_MASK 0xffffffffUL +#define XLPD_SLCR_MUTEX1_ID_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrMutex2 + */ +#define XLPD_SLCR_MUTEX2 ( ( XLPD_SLCR_BASEADDR ) + 0x00007008UL ) +#define XLPD_SLCR_MUTEX2_RSTVAL 0x00000000UL + +#define XLPD_SLCR_MUTEX2_ID_SHIFT 0UL +#define XLPD_SLCR_MUTEX2_ID_WIDTH 32UL +#define XLPD_SLCR_MUTEX2_ID_MASK 0xffffffffUL +#define XLPD_SLCR_MUTEX2_ID_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrMutex3 + */ +#define XLPD_SLCR_MUTEX3 ( ( XLPD_SLCR_BASEADDR ) + 0x0000700CUL ) +#define XLPD_SLCR_MUTEX3_RSTVAL 0x00000000UL + +#define XLPD_SLCR_MUTEX3_ID_SHIFT 0UL +#define XLPD_SLCR_MUTEX3_ID_WIDTH 32UL +#define XLPD_SLCR_MUTEX3_ID_MASK 0xffffffffUL +#define XLPD_SLCR_MUTEX3_ID_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp0IrqSts + */ +#define XLPD_SLCR_GICP0_IRQ_STS ( ( XLPD_SLCR_BASEADDR ) + 0x00008000UL ) +#define XLPD_SLCR_GICP0_IRQ_STS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp0IrqMsk + */ +#define XLPD_SLCR_GICP0_IRQ_MSK ( ( XLPD_SLCR_BASEADDR ) + 0x00008004UL ) +#define XLPD_SLCR_GICP0_IRQ_MSK_RSTVAL 0xffffffffUL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC31_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC30_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC29_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC28_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC27_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC26_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC25_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC24_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC23_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC22_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC21_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC20_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC19_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC18_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC17_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC16_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC15_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC14_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC13_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC12_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC11_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC10_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC9_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC8_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC7_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC6_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC5_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC4_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC3_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC2_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC1_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC0_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrGicp0IrqEn + */ +#define XLPD_SLCR_GICP0_IRQ_EN ( ( XLPD_SLCR_BASEADDR ) + 0x00008008UL ) +#define XLPD_SLCR_GICP0_IRQ_EN_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp0IrqDis + */ +#define XLPD_SLCR_GICP0_IRQ_DIS ( ( XLPD_SLCR_BASEADDR ) + 0x0000800CUL ) +#define XLPD_SLCR_GICP0_IRQ_DIS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp0IrqTrig + */ +#define XLPD_SLCR_GICP0_IRQ_TRIG ( ( XLPD_SLCR_BASEADDR ) + 0x00008010UL ) +#define XLPD_SLCR_GICP0_IRQ_TRIG_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp1IrqSts + */ +#define XLPD_SLCR_GICP1_IRQ_STS ( ( XLPD_SLCR_BASEADDR ) + 0x00008014UL ) +#define XLPD_SLCR_GICP1_IRQ_STS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp1IrqMsk + */ +#define XLPD_SLCR_GICP1_IRQ_MSK ( ( XLPD_SLCR_BASEADDR ) + 0x00008018UL ) +#define XLPD_SLCR_GICP1_IRQ_MSK_RSTVAL 0xffffffffUL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC31_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC30_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC29_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC28_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC27_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC26_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC25_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC24_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC23_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC22_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC21_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC20_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC19_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC18_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC17_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC16_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC15_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC14_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC13_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC12_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC11_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC10_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC9_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC8_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC7_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC6_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC5_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC4_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC3_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC2_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC1_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC0_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrGicp1IrqEn + */ +#define XLPD_SLCR_GICP1_IRQ_EN ( ( XLPD_SLCR_BASEADDR ) + 0x0000801CUL ) +#define XLPD_SLCR_GICP1_IRQ_EN_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp1IrqDis + */ +#define XLPD_SLCR_GICP1_IRQ_DIS ( ( XLPD_SLCR_BASEADDR ) + 0x00008020UL ) +#define XLPD_SLCR_GICP1_IRQ_DIS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp1IrqTrig + */ +#define XLPD_SLCR_GICP1_IRQ_TRIG ( ( XLPD_SLCR_BASEADDR ) + 0x00008024UL ) +#define XLPD_SLCR_GICP1_IRQ_TRIG_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp2IrqSts + */ +#define XLPD_SLCR_GICP2_IRQ_STS ( ( XLPD_SLCR_BASEADDR ) + 0x00008028UL ) +#define XLPD_SLCR_GICP2_IRQ_STS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp2IrqMsk + */ +#define XLPD_SLCR_GICP2_IRQ_MSK ( ( XLPD_SLCR_BASEADDR ) + 0x0000802CUL ) +#define XLPD_SLCR_GICP2_IRQ_MSK_RSTVAL 0xffffffffUL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC31_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC30_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC29_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC28_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC27_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC26_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC25_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC24_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC23_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC22_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC21_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC20_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC19_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC18_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC17_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC16_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC15_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC14_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC13_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC12_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC11_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC10_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC9_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC8_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC7_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC6_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC5_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC4_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC3_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC2_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC1_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC0_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrGicp2IrqEn + */ +#define XLPD_SLCR_GICP2_IRQ_EN ( ( XLPD_SLCR_BASEADDR ) + 0x00008030UL ) +#define XLPD_SLCR_GICP2_IRQ_EN_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp2IrqDis + */ +#define XLPD_SLCR_GICP2_IRQ_DIS ( ( XLPD_SLCR_BASEADDR ) + 0x00008034UL ) +#define XLPD_SLCR_GICP2_IRQ_DIS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp2IrqTrig + */ +#define XLPD_SLCR_GICP2_IRQ_TRIG ( ( XLPD_SLCR_BASEADDR ) + 0x00008038UL ) +#define XLPD_SLCR_GICP2_IRQ_TRIG_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp3IrqSts + */ +#define XLPD_SLCR_GICP3_IRQ_STS ( ( XLPD_SLCR_BASEADDR ) + 0x0000803CUL ) +#define XLPD_SLCR_GICP3_IRQ_STS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp3IrqMsk + */ +#define XLPD_SLCR_GICP3_IRQ_MSK ( ( XLPD_SLCR_BASEADDR ) + 0x00008040UL ) +#define XLPD_SLCR_GICP3_IRQ_MSK_RSTVAL 0xffffffffUL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC31_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC30_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC29_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC28_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC27_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC26_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC25_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC24_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC23_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC22_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC21_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC20_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC19_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC18_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC17_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC16_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC15_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC14_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC13_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC12_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC11_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC10_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC9_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC8_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC7_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC6_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC5_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC4_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC3_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC2_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC1_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC0_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrGicp3IrqEn + */ +#define XLPD_SLCR_GICP3_IRQ_EN ( ( XLPD_SLCR_BASEADDR ) + 0x00008044UL ) +#define XLPD_SLCR_GICP3_IRQ_EN_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp3IrqDis + */ +#define XLPD_SLCR_GICP3_IRQ_DIS ( ( XLPD_SLCR_BASEADDR ) + 0x00008048UL ) +#define XLPD_SLCR_GICP3_IRQ_DIS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp3IrqTrig + */ +#define XLPD_SLCR_GICP3_IRQ_TRIG ( ( XLPD_SLCR_BASEADDR ) + 0x0000804CUL ) +#define XLPD_SLCR_GICP3_IRQ_TRIG_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp4IrqSts + */ +#define XLPD_SLCR_GICP4_IRQ_STS ( ( XLPD_SLCR_BASEADDR ) + 0x00008050UL ) +#define XLPD_SLCR_GICP4_IRQ_STS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp4IrqMsk + */ +#define XLPD_SLCR_GICP4_IRQ_MSK ( ( XLPD_SLCR_BASEADDR ) + 0x00008054UL ) +#define XLPD_SLCR_GICP4_IRQ_MSK_RSTVAL 0xffffffffUL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC31_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC30_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC29_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC28_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC27_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC26_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC25_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC24_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC23_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC22_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC21_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC20_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC19_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC18_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC17_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC16_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC15_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC14_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC13_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC12_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC11_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC10_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC9_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC8_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC7_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC6_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC5_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC4_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC3_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC2_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC1_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC0_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrGicp4IrqEn + */ +#define XLPD_SLCR_GICP4_IRQ_EN ( ( XLPD_SLCR_BASEADDR ) + 0x00008058UL ) +#define XLPD_SLCR_GICP4_IRQ_EN_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp4IrqDis + */ +#define XLPD_SLCR_GICP4_IRQ_DIS ( ( XLPD_SLCR_BASEADDR ) + 0x0000805CUL ) +#define XLPD_SLCR_GICP4_IRQ_DIS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp4IrqTrig + */ +#define XLPD_SLCR_GICP4_IRQ_TRIG ( ( XLPD_SLCR_BASEADDR ) + 0x00008060UL ) +#define XLPD_SLCR_GICP4_IRQ_TRIG_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicpPmuIrqSts + */ +#define XLPD_SLCR_GICP_PMU_IRQ_STS ( ( XLPD_SLCR_BASEADDR ) + 0x000080A0UL ) +#define XLPD_SLCR_GICP_PMU_IRQ_STS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicpPmuIrqMsk + */ +#define XLPD_SLCR_GICP_PMU_IRQ_MSK ( ( XLPD_SLCR_BASEADDR ) + 0x000080A4UL ) +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_RSTVAL 0x000000ffUL + +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC7_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC6_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC5_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC4_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC3_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC2_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC1_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC0_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrGicpPmuIrqEn + */ +#define XLPD_SLCR_GICP_PMU_IRQ_EN ( ( XLPD_SLCR_BASEADDR ) + 0x000080A8UL ) +#define XLPD_SLCR_GICP_PMU_IRQ_EN_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicpPmuIrqDis + */ +#define XLPD_SLCR_GICP_PMU_IRQ_DIS ( ( XLPD_SLCR_BASEADDR ) + 0x000080ACUL ) +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicpPmuIrqTrig + */ +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG ( ( XLPD_SLCR_BASEADDR ) + 0x000080B0UL ) +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrAfiFs + */ +#define XLPD_SLCR_AFI_FS ( ( XLPD_SLCR_BASEADDR ) + 0x00009000UL ) +#define XLPD_SLCR_AFI_FS_RSTVAL 0x00000200UL + +#define XLPD_SLCR_AFI_FS_DW_SS2_SEL_SHIFT 8UL +#define XLPD_SLCR_AFI_FS_DW_SS2_SEL_WIDTH 2UL +#define XLPD_SLCR_AFI_FS_DW_SS2_SEL_MASK 0x00000300UL +#define XLPD_SLCR_AFI_FS_DW_SS2_SEL_DEFVAL 0x2UL + +/** + * Register: XlpdSlcrCci + */ +#define XLPD_SLCR_CCI ( ( XLPD_SLCR_BASEADDR ) + 0x0000A000UL ) +#define XLPD_SLCR_CCI_RSTVAL 0x03801c07UL + +#define XLPD_SLCR_CCI_SPR_SHIFT 28UL +#define XLPD_SLCR_CCI_SPR_WIDTH 4UL +#define XLPD_SLCR_CCI_SPR_MASK 0xf0000000UL +#define XLPD_SLCR_CCI_SPR_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_QVNVNETS4_SHIFT 27UL +#define XLPD_SLCR_CCI_QVNVNETS4_WIDTH 1UL +#define XLPD_SLCR_CCI_QVNVNETS4_MASK 0x08000000UL +#define XLPD_SLCR_CCI_QVNVNETS4_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_QVNVNETS3_SHIFT 26UL +#define XLPD_SLCR_CCI_QVNVNETS3_WIDTH 1UL +#define XLPD_SLCR_CCI_QVNVNETS3_MASK 0x04000000UL +#define XLPD_SLCR_CCI_QVNVNETS3_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_QVNVNETS2_SHIFT 25UL +#define XLPD_SLCR_CCI_QVNVNETS2_WIDTH 1UL +#define XLPD_SLCR_CCI_QVNVNETS2_MASK 0x02000000UL +#define XLPD_SLCR_CCI_QVNVNETS2_DEFVAL 0x1UL + +#define XLPD_SLCR_CCI_QVNVNETS1_SHIFT 24UL +#define XLPD_SLCR_CCI_QVNVNETS1_WIDTH 1UL +#define XLPD_SLCR_CCI_QVNVNETS1_MASK 0x01000000UL +#define XLPD_SLCR_CCI_QVNVNETS1_DEFVAL 0x1UL + +#define XLPD_SLCR_CCI_QVNVNETS0_SHIFT 23UL +#define XLPD_SLCR_CCI_QVNVNETS0_WIDTH 1UL +#define XLPD_SLCR_CCI_QVNVNETS0_MASK 0x00800000UL +#define XLPD_SLCR_CCI_QVNVNETS0_DEFVAL 0x1UL + +#define XLPD_SLCR_CCI_QOS_OVRRD_SHIFT 18UL +#define XLPD_SLCR_CCI_QOS_OVRRD_WIDTH 5UL +#define XLPD_SLCR_CCI_QOS_OVRRD_MASK 0x007c0000UL +#define XLPD_SLCR_CCI_QOS_OVRRD_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_QVN_EN_M2_SHIFT 17UL +#define XLPD_SLCR_CCI_QVN_EN_M2_WIDTH 1UL +#define XLPD_SLCR_CCI_QVN_EN_M2_MASK 0x00020000UL +#define XLPD_SLCR_CCI_QVN_EN_M2_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_QVN_EN_M1_SHIFT 16UL +#define XLPD_SLCR_CCI_QVN_EN_M1_WIDTH 1UL +#define XLPD_SLCR_CCI_QVN_EN_M1_MASK 0x00010000UL +#define XLPD_SLCR_CCI_QVN_EN_M1_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_STRPG_GRAN_SHIFT 13UL +#define XLPD_SLCR_CCI_STRPG_GRAN_WIDTH 3UL +#define XLPD_SLCR_CCI_STRPG_GRAN_MASK 0x0000e000UL +#define XLPD_SLCR_CCI_STRPG_GRAN_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ACCHNLLEN4_SHIFT 12UL +#define XLPD_SLCR_CCI_ACCHNLLEN4_WIDTH 1UL +#define XLPD_SLCR_CCI_ACCHNLLEN4_MASK 0x00001000UL +#define XLPD_SLCR_CCI_ACCHNLLEN4_DEFVAL 0x1UL + +#define XLPD_SLCR_CCI_ACCHNLLEN3_SHIFT 11UL +#define XLPD_SLCR_CCI_ACCHNLLEN3_WIDTH 1UL +#define XLPD_SLCR_CCI_ACCHNLLEN3_MASK 0x00000800UL +#define XLPD_SLCR_CCI_ACCHNLLEN3_DEFVAL 0x1UL + +#define XLPD_SLCR_CCI_ACCHNLLEN0_SHIFT 10UL +#define XLPD_SLCR_CCI_ACCHNLLEN0_WIDTH 1UL +#define XLPD_SLCR_CCI_ACCHNLLEN0_MASK 0x00000400UL +#define XLPD_SLCR_CCI_ACCHNLLEN0_DEFVAL 0x1UL + +#define XLPD_SLCR_CCI_ECOREVNUM_SHIFT 6UL +#define XLPD_SLCR_CCI_ECOREVNUM_WIDTH 4UL +#define XLPD_SLCR_CCI_ECOREVNUM_MASK 0x000003c0UL +#define XLPD_SLCR_CCI_ECOREVNUM_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ASA2_SHIFT 5UL +#define XLPD_SLCR_CCI_ASA2_WIDTH 1UL +#define XLPD_SLCR_CCI_ASA2_MASK 0x00000020UL +#define XLPD_SLCR_CCI_ASA2_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ASA1_SHIFT 4UL +#define XLPD_SLCR_CCI_ASA1_WIDTH 1UL +#define XLPD_SLCR_CCI_ASA1_MASK 0x00000010UL +#define XLPD_SLCR_CCI_ASA1_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ASA0_SHIFT 3UL +#define XLPD_SLCR_CCI_ASA0_WIDTH 1UL +#define XLPD_SLCR_CCI_ASA0_MASK 0x00000008UL +#define XLPD_SLCR_CCI_ASA0_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_OWO2_SHIFT 2UL +#define XLPD_SLCR_CCI_OWO2_WIDTH 1UL +#define XLPD_SLCR_CCI_OWO2_MASK 0x00000004UL +#define XLPD_SLCR_CCI_OWO2_DEFVAL 0x1UL + +#define XLPD_SLCR_CCI_OWO1_SHIFT 1UL +#define XLPD_SLCR_CCI_OWO1_WIDTH 1UL +#define XLPD_SLCR_CCI_OWO1_MASK 0x00000002UL +#define XLPD_SLCR_CCI_OWO1_DEFVAL 0x1UL + +#define XLPD_SLCR_CCI_OWO0_SHIFT 0UL +#define XLPD_SLCR_CCI_OWO0_WIDTH 1UL +#define XLPD_SLCR_CCI_OWO0_MASK 0x00000001UL +#define XLPD_SLCR_CCI_OWO0_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrCciAddrmap + */ +#define XLPD_SLCR_CCI_ADDRMAP ( ( XLPD_SLCR_BASEADDR ) + 0x0000A004UL ) +#define XLPD_SLCR_CCI_ADDRMAP_RSTVAL 0x00c000ffUL + +#define XLPD_SLCR_CCI_ADDRMAP_15_SHIFT 30UL +#define XLPD_SLCR_CCI_ADDRMAP_15_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_15_MASK 0xc0000000UL +#define XLPD_SLCR_CCI_ADDRMAP_15_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ADDRMAP_14_SHIFT 28UL +#define XLPD_SLCR_CCI_ADDRMAP_14_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_14_MASK 0x30000000UL +#define XLPD_SLCR_CCI_ADDRMAP_14_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ADDRMAP_13_SHIFT 26UL +#define XLPD_SLCR_CCI_ADDRMAP_13_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_13_MASK 0x0c000000UL +#define XLPD_SLCR_CCI_ADDRMAP_13_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ADDRMAP_12_SHIFT 24UL +#define XLPD_SLCR_CCI_ADDRMAP_12_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_12_MASK 0x03000000UL +#define XLPD_SLCR_CCI_ADDRMAP_12_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ADDRMAP_11_SHIFT 22UL +#define XLPD_SLCR_CCI_ADDRMAP_11_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_11_MASK 0x00c00000UL +#define XLPD_SLCR_CCI_ADDRMAP_11_DEFVAL 0x3UL + +#define XLPD_SLCR_CCI_ADDRMAP_10_SHIFT 20UL +#define XLPD_SLCR_CCI_ADDRMAP_10_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_10_MASK 0x00300000UL +#define XLPD_SLCR_CCI_ADDRMAP_10_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ADDRMAP_9_SHIFT 18UL +#define XLPD_SLCR_CCI_ADDRMAP_9_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_9_MASK 0x000c0000UL +#define XLPD_SLCR_CCI_ADDRMAP_9_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ADDRMAP_8_SHIFT 16UL +#define XLPD_SLCR_CCI_ADDRMAP_8_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_8_MASK 0x00030000UL +#define XLPD_SLCR_CCI_ADDRMAP_8_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ADDRMAP_7_SHIFT 14UL +#define XLPD_SLCR_CCI_ADDRMAP_7_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_7_MASK 0x0000c000UL +#define XLPD_SLCR_CCI_ADDRMAP_7_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ADDRMAP_6_SHIFT 12UL +#define XLPD_SLCR_CCI_ADDRMAP_6_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_6_MASK 0x00003000UL +#define XLPD_SLCR_CCI_ADDRMAP_6_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ADDRMAP_5_SHIFT 10UL +#define XLPD_SLCR_CCI_ADDRMAP_5_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_5_MASK 0x00000c00UL +#define XLPD_SLCR_CCI_ADDRMAP_5_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ADDRMAP_4_SHIFT 8UL +#define XLPD_SLCR_CCI_ADDRMAP_4_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_4_MASK 0x00000300UL +#define XLPD_SLCR_CCI_ADDRMAP_4_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ADDRMAP_3_SHIFT 6UL +#define XLPD_SLCR_CCI_ADDRMAP_3_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_3_MASK 0x000000c0UL +#define XLPD_SLCR_CCI_ADDRMAP_3_DEFVAL 0x3UL + +#define XLPD_SLCR_CCI_ADDRMAP_2_SHIFT 4UL +#define XLPD_SLCR_CCI_ADDRMAP_2_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_2_MASK 0x00000030UL +#define XLPD_SLCR_CCI_ADDRMAP_2_DEFVAL 0x3UL + +#define XLPD_SLCR_CCI_ADDRMAP_1_SHIFT 2UL +#define XLPD_SLCR_CCI_ADDRMAP_1_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_1_MASK 0x0000000cUL +#define XLPD_SLCR_CCI_ADDRMAP_1_DEFVAL 0x3UL + +#define XLPD_SLCR_CCI_ADDRMAP_0_SHIFT 0UL +#define XLPD_SLCR_CCI_ADDRMAP_0_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_0_MASK 0x00000003UL +#define XLPD_SLCR_CCI_ADDRMAP_0_DEFVAL 0x3UL + +/** + * Register: XlpdSlcrCciQvnprealloc + */ +#define XLPD_SLCR_CCI_QVNPREALLOC ( ( XLPD_SLCR_BASEADDR ) + 0x0000A008UL ) +#define XLPD_SLCR_CCI_QVNPREALLOC_RSTVAL 0x00330330UL + +#define XLPD_SLCR_CCI_QVNPREALLOC_WM2_SHIFT 20UL +#define XLPD_SLCR_CCI_QVNPREALLOC_WM2_WIDTH 4UL +#define XLPD_SLCR_CCI_QVNPREALLOC_WM2_MASK 0x00f00000UL +#define XLPD_SLCR_CCI_QVNPREALLOC_WM2_DEFVAL 0x3UL + +#define XLPD_SLCR_CCI_QVNPREALLOC_WM1_SHIFT 16UL +#define XLPD_SLCR_CCI_QVNPREALLOC_WM1_WIDTH 4UL +#define XLPD_SLCR_CCI_QVNPREALLOC_WM1_MASK 0x000f0000UL +#define XLPD_SLCR_CCI_QVNPREALLOC_WM1_DEFVAL 0x3UL + +#define XLPD_SLCR_CCI_QVNPREALLOC_RM2_SHIFT 8UL +#define XLPD_SLCR_CCI_QVNPREALLOC_RM2_WIDTH 4UL +#define XLPD_SLCR_CCI_QVNPREALLOC_RM2_MASK 0x00000f00UL +#define XLPD_SLCR_CCI_QVNPREALLOC_RM2_DEFVAL 0x3UL + +#define XLPD_SLCR_CCI_QVNPREALLOC_RM1_SHIFT 4UL +#define XLPD_SLCR_CCI_QVNPREALLOC_RM1_WIDTH 4UL +#define XLPD_SLCR_CCI_QVNPREALLOC_RM1_MASK 0x000000f0UL +#define XLPD_SLCR_CCI_QVNPREALLOC_RM1_DEFVAL 0x3UL + +/** + * Register: XlpdSlcrSmmu + */ +#define XLPD_SLCR_SMMU ( ( XLPD_SLCR_BASEADDR ) + 0x0000A020UL ) +#define XLPD_SLCR_SMMU_RSTVAL 0x0000003fUL + +#define XLPD_SLCR_SMMU_INTG_SEC_OVRRDE_SHIFT 7UL +#define XLPD_SLCR_SMMU_INTG_SEC_OVRRDE_WIDTH 1UL +#define XLPD_SLCR_SMMU_INTG_SEC_OVRRDE_MASK 0x00000080UL +#define XLPD_SLCR_SMMU_INTG_SEC_OVRRDE_DEFVAL 0x0UL + +#define XLPD_SLCR_SMMU_CTTW_SHIFT 6UL +#define XLPD_SLCR_SMMU_CTTW_WIDTH 1UL +#define XLPD_SLCR_SMMU_CTTW_MASK 0x00000040UL +#define XLPD_SLCR_SMMU_CTTW_DEFVAL 0x0UL + +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU5_SHIFT 5UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU5_WIDTH 1UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU5_MASK 0x00000020UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU5_DEFVAL 0x1UL + +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU4_SHIFT 4UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU4_WIDTH 1UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU4_MASK 0x00000010UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU4_DEFVAL 0x1UL + +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU3_SHIFT 3UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU3_WIDTH 1UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU3_MASK 0x00000008UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU3_DEFVAL 0x1UL + +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU2_SHIFT 2UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU2_WIDTH 1UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU2_MASK 0x00000004UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU2_DEFVAL 0x1UL + +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU1_SHIFT 1UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU1_WIDTH 1UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU1_MASK 0x00000002UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU1_DEFVAL 0x1UL + +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU0_SHIFT 0UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU0_WIDTH 1UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU0_MASK 0x00000001UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU0_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrApu + */ +#define XLPD_SLCR_APU ( ( XLPD_SLCR_BASEADDR ) + 0x0000A040UL ) +#define XLPD_SLCR_APU_RSTVAL 0x00000001UL + +#define XLPD_SLCR_APU_BRDC_BARRIER_SHIFT 3UL +#define XLPD_SLCR_APU_BRDC_BARRIER_WIDTH 1UL +#define XLPD_SLCR_APU_BRDC_BARRIER_MASK 0x00000008UL +#define XLPD_SLCR_APU_BRDC_BARRIER_DEFVAL 0x0UL + +#define XLPD_SLCR_APU_BRDC_CMNT_SHIFT 2UL +#define XLPD_SLCR_APU_BRDC_CMNT_WIDTH 1UL +#define XLPD_SLCR_APU_BRDC_CMNT_MASK 0x00000004UL +#define XLPD_SLCR_APU_BRDC_CMNT_DEFVAL 0x0UL + +#define XLPD_SLCR_APU_BRDC_INNER_SHIFT 1UL +#define XLPD_SLCR_APU_BRDC_INNER_WIDTH 1UL +#define XLPD_SLCR_APU_BRDC_INNER_MASK 0x00000002UL +#define XLPD_SLCR_APU_BRDC_INNER_DEFVAL 0x0UL + +#define XLPD_SLCR_APU_BRDC_OUTER_SHIFT 0UL +#define XLPD_SLCR_APU_BRDC_OUTER_WIDTH 1UL +#define XLPD_SLCR_APU_BRDC_OUTER_MASK 0x00000001UL +#define XLPD_SLCR_APU_BRDC_OUTER_DEFVAL 0x1UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XLPD_SLCR_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xlpd_slcr_secure.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xlpd_slcr_secure.h new file mode 100644 index 0000000..aff3bf2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xlpd_slcr_secure.h
@@ -0,0 +1,141 @@ +/* ### HEADER ### */ + +#ifndef __XLPD_SLCR_SECURE_H__ +#define __XLPD_SLCR_SECURE_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XlpdSlcrSecure Base Address + */ +#define XLPD_SLCR_SECURE_BASEADDR 0xFF4B0000UL + +/** + * Register: XlpdSlcrSecCtrl + */ +#define XLPD_SLCR_SEC_CTRL ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000004UL ) +#define XLPD_SLCR_SEC_CTRL_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_SHIFT 0UL +#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_WIDTH 1UL +#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_MASK 0x00000001UL +#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSecIsr + */ +#define XLPD_SLCR_SEC_ISR ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000008UL ) +#define XLPD_SLCR_SEC_ISR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_SHIFT 0UL +#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_WIDTH 1UL +#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSecImr + */ +#define XLPD_SLCR_SEC_IMR ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x0000000CUL ) +#define XLPD_SLCR_SEC_IMR_RSTVAL 0x00000001UL + +#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_SHIFT 0UL +#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_WIDTH 1UL +#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrSecIer + */ +#define XLPD_SLCR_SEC_IER ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000010UL ) +#define XLPD_SLCR_SEC_IER_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_SHIFT 0UL +#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_WIDTH 1UL +#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_MASK 0x00000001UL +#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSecIdr + */ +#define XLPD_SLCR_SEC_IDR ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000014UL ) +#define XLPD_SLCR_SEC_IDR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_SHIFT 0UL +#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_WIDTH 1UL +#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSecItr + */ +#define XLPD_SLCR_SEC_ITR ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000018UL ) +#define XLPD_SLCR_SEC_ITR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_SHIFT 0UL +#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_WIDTH 1UL +#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSecRpu + */ +#define XLPD_SLCR_SEC_RPU ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000020UL ) +#define XLPD_SLCR_SEC_RPU_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SEC_RPU_TZ_R5_1_SHIFT 1UL +#define XLPD_SLCR_SEC_RPU_TZ_R5_1_WIDTH 1UL +#define XLPD_SLCR_SEC_RPU_TZ_R5_1_MASK 0x00000002UL +#define XLPD_SLCR_SEC_RPU_TZ_R5_1_DEFVAL 0x0UL + +#define XLPD_SLCR_SEC_RPU_TZ_R5_0_SHIFT 0UL +#define XLPD_SLCR_SEC_RPU_TZ_R5_0_WIDTH 1UL +#define XLPD_SLCR_SEC_RPU_TZ_R5_0_MASK 0x00000001UL +#define XLPD_SLCR_SEC_RPU_TZ_R5_0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSecAdma + */ +#define XLPD_SLCR_SEC_ADMA ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000024UL ) +#define XLPD_SLCR_SEC_ADMA_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SEC_ADMA_TZ_SHIFT 0UL +#define XLPD_SLCR_SEC_ADMA_TZ_WIDTH 8UL +#define XLPD_SLCR_SEC_ADMA_TZ_MASK 0x000000ffUL +#define XLPD_SLCR_SEC_ADMA_TZ_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSecSafetyChk + */ +#define XLPD_SLCR_SEC_SAFETY_CHK ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000030UL ) +#define XLPD_SLCR_SEC_SAFETY_CHK_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_SHIFT 0UL +#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_WIDTH 32UL +#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_MASK 0xffffffffUL +#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSecUsb + */ +#define XLPD_SLCR_SEC_USB ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000034UL ) +#define XLPD_SLCR_SEC_USB_RSTVAL 0x00000003UL + +#define XLPD_SLCR_SEC_USB_TZ_USB3_1_SHIFT 1UL +#define XLPD_SLCR_SEC_USB_TZ_USB3_1_WIDTH 1UL +#define XLPD_SLCR_SEC_USB_TZ_USB3_1_MASK 0x00000002UL +#define XLPD_SLCR_SEC_USB_TZ_USB3_1_DEFVAL 0x1UL + +#define XLPD_SLCR_SEC_USB_TZ_USB3_0_SHIFT 0UL +#define XLPD_SLCR_SEC_USB_TZ_USB3_0_WIDTH 1UL +#define XLPD_SLCR_SEC_USB_TZ_USB3_0_MASK 0x00000001UL +#define XLPD_SLCR_SEC_USB_TZ_USB3_0_DEFVAL 0x1UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XLPD_SLCR_SECURE_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xlpd_xppu.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xlpd_xppu.h new file mode 100644 index 0000000..a5145ea --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xlpd_xppu.h
@@ -0,0 +1,858 @@ +/* ### HEADER ### */ + +#ifndef __XLPD_XPPU_H__ +#define __XLPD_XPPU_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XlpdXppu Base Address + */ +#define XLPD_XPPU_BASEADDR 0xFF980000UL + +/** + * Register: XlpdXppuCtrl + */ +#define XLPD_XPPU_CTRL ( ( XLPD_XPPU_BASEADDR ) + 0x00000000UL ) +#define XLPD_XPPU_CTRL_RSTVAL 0x00000000UL + +#define XLPD_XPPU_CTRL_APER_PARITY_EN_SHIFT 2UL +#define XLPD_XPPU_CTRL_APER_PARITY_EN_WIDTH 1UL +#define XLPD_XPPU_CTRL_APER_PARITY_EN_MASK 0x00000004UL +#define XLPD_XPPU_CTRL_APER_PARITY_EN_DEFVAL 0x0UL + +#define XLPD_XPPU_CTRL_MID_PARITY_EN_SHIFT 1UL +#define XLPD_XPPU_CTRL_MID_PARITY_EN_WIDTH 1UL +#define XLPD_XPPU_CTRL_MID_PARITY_EN_MASK 0x00000002UL +#define XLPD_XPPU_CTRL_MID_PARITY_EN_DEFVAL 0x0UL + +#define XLPD_XPPU_CTRL_EN_SHIFT 0UL +#define XLPD_XPPU_CTRL_EN_WIDTH 1UL +#define XLPD_XPPU_CTRL_EN_MASK 0x00000001UL +#define XLPD_XPPU_CTRL_EN_DEFVAL 0x0UL + +/** + * Register: XlpdXppuErrSts1 + */ +#define XLPD_XPPU_ERR_STS1 ( ( XLPD_XPPU_BASEADDR ) + 0x00000004UL ) +#define XLPD_XPPU_ERR_STS1_RSTVAL 0x00000000UL + +#define XLPD_XPPU_ERR_STS1_AXI_ADDR_SHIFT 0UL +#define XLPD_XPPU_ERR_STS1_AXI_ADDR_WIDTH 32UL +#define XLPD_XPPU_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL +#define XLPD_XPPU_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL + +/** + * Register: XlpdXppuErrSts2 + */ +#define XLPD_XPPU_ERR_STS2 ( ( XLPD_XPPU_BASEADDR ) + 0x00000008UL ) +#define XLPD_XPPU_ERR_STS2_RSTVAL 0x00000000UL + +#define XLPD_XPPU_ERR_STS2_AXI_ID_SHIFT 0UL +#define XLPD_XPPU_ERR_STS2_AXI_ID_WIDTH 16UL +#define XLPD_XPPU_ERR_STS2_AXI_ID_MASK 0x0000ffffUL +#define XLPD_XPPU_ERR_STS2_AXI_ID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuPoison + */ +#define XLPD_XPPU_POISON ( ( XLPD_XPPU_BASEADDR ) + 0x0000000CUL ) +#define XLPD_XPPU_POISON_RSTVAL 0x00000000UL + +#define XLPD_XPPU_POISON_BASE_SHIFT 0UL +#define XLPD_XPPU_POISON_BASE_WIDTH 20UL +#define XLPD_XPPU_POISON_BASE_MASK 0x000fffffUL +#define XLPD_XPPU_POISON_BASE_DEFVAL 0x0UL + +/** + * Register: XlpdXppuIsr + */ +#define XLPD_XPPU_ISR ( ( XLPD_XPPU_BASEADDR ) + 0x00000010UL ) +#define XLPD_XPPU_ISR_RSTVAL 0x00000000UL + +#define XLPD_XPPU_ISR_APER_PARITY_SHIFT 7UL +#define XLPD_XPPU_ISR_APER_PARITY_WIDTH 1UL +#define XLPD_XPPU_ISR_APER_PARITY_MASK 0x00000080UL +#define XLPD_XPPU_ISR_APER_PARITY_DEFVAL 0x0UL + +#define XLPD_XPPU_ISR_APER_TZ_SHIFT 6UL +#define XLPD_XPPU_ISR_APER_TZ_WIDTH 1UL +#define XLPD_XPPU_ISR_APER_TZ_MASK 0x00000040UL +#define XLPD_XPPU_ISR_APER_TZ_DEFVAL 0x0UL + +#define XLPD_XPPU_ISR_APER_PERM_SHIFT 5UL +#define XLPD_XPPU_ISR_APER_PERM_WIDTH 1UL +#define XLPD_XPPU_ISR_APER_PERM_MASK 0x00000020UL +#define XLPD_XPPU_ISR_APER_PERM_DEFVAL 0x0UL + +#define XLPD_XPPU_ISR_MID_PARITY_SHIFT 3UL +#define XLPD_XPPU_ISR_MID_PARITY_WIDTH 1UL +#define XLPD_XPPU_ISR_MID_PARITY_MASK 0x00000008UL +#define XLPD_XPPU_ISR_MID_PARITY_DEFVAL 0x0UL + +#define XLPD_XPPU_ISR_MID_RO_SHIFT 2UL +#define XLPD_XPPU_ISR_MID_RO_WIDTH 1UL +#define XLPD_XPPU_ISR_MID_RO_MASK 0x00000004UL +#define XLPD_XPPU_ISR_MID_RO_DEFVAL 0x0UL + +#define XLPD_XPPU_ISR_MID_MISS_SHIFT 1UL +#define XLPD_XPPU_ISR_MID_MISS_WIDTH 1UL +#define XLPD_XPPU_ISR_MID_MISS_MASK 0x00000002UL +#define XLPD_XPPU_ISR_MID_MISS_DEFVAL 0x0UL + +#define XLPD_XPPU_ISR_INV_APB_SHIFT 0UL +#define XLPD_XPPU_ISR_INV_APB_WIDTH 1UL +#define XLPD_XPPU_ISR_INV_APB_MASK 0x00000001UL +#define XLPD_XPPU_ISR_INV_APB_DEFVAL 0x0UL + +/** + * Register: XlpdXppuImr + */ +#define XLPD_XPPU_IMR ( ( XLPD_XPPU_BASEADDR ) + 0x00000014UL ) +#define XLPD_XPPU_IMR_RSTVAL 0x000000efUL + +#define XLPD_XPPU_IMR_APER_PARITY_SHIFT 7UL +#define XLPD_XPPU_IMR_APER_PARITY_WIDTH 1UL +#define XLPD_XPPU_IMR_APER_PARITY_MASK 0x00000080UL +#define XLPD_XPPU_IMR_APER_PARITY_DEFVAL 0x1UL + +#define XLPD_XPPU_IMR_APER_TZ_SHIFT 6UL +#define XLPD_XPPU_IMR_APER_TZ_WIDTH 1UL +#define XLPD_XPPU_IMR_APER_TZ_MASK 0x00000040UL +#define XLPD_XPPU_IMR_APER_TZ_DEFVAL 0x1UL + +#define XLPD_XPPU_IMR_APER_PERM_SHIFT 5UL +#define XLPD_XPPU_IMR_APER_PERM_WIDTH 1UL +#define XLPD_XPPU_IMR_APER_PERM_MASK 0x00000020UL +#define XLPD_XPPU_IMR_APER_PERM_DEFVAL 0x1UL + +#define XLPD_XPPU_IMR_MID_PARITY_SHIFT 3UL +#define XLPD_XPPU_IMR_MID_PARITY_WIDTH 1UL +#define XLPD_XPPU_IMR_MID_PARITY_MASK 0x00000008UL +#define XLPD_XPPU_IMR_MID_PARITY_DEFVAL 0x1UL + +#define XLPD_XPPU_IMR_MID_RO_SHIFT 2UL +#define XLPD_XPPU_IMR_MID_RO_WIDTH 1UL +#define XLPD_XPPU_IMR_MID_RO_MASK 0x00000004UL +#define XLPD_XPPU_IMR_MID_RO_DEFVAL 0x1UL + +#define XLPD_XPPU_IMR_MID_MISS_SHIFT 1UL +#define XLPD_XPPU_IMR_MID_MISS_WIDTH 1UL +#define XLPD_XPPU_IMR_MID_MISS_MASK 0x00000002UL +#define XLPD_XPPU_IMR_MID_MISS_DEFVAL 0x1UL + +#define XLPD_XPPU_IMR_INV_APB_SHIFT 0UL +#define XLPD_XPPU_IMR_INV_APB_WIDTH 1UL +#define XLPD_XPPU_IMR_INV_APB_MASK 0x00000001UL +#define XLPD_XPPU_IMR_INV_APB_DEFVAL 0x1UL + +/** + * Register: XlpdXppuIen + */ +#define XLPD_XPPU_IEN ( ( XLPD_XPPU_BASEADDR ) + 0x00000018UL ) +#define XLPD_XPPU_IEN_RSTVAL 0x00000000UL + +#define XLPD_XPPU_IEN_APER_PARITY_SHIFT 7UL +#define XLPD_XPPU_IEN_APER_PARITY_WIDTH 1UL +#define XLPD_XPPU_IEN_APER_PARITY_MASK 0x00000080UL +#define XLPD_XPPU_IEN_APER_PARITY_DEFVAL 0x0UL + +#define XLPD_XPPU_IEN_APER_TZ_SHIFT 6UL +#define XLPD_XPPU_IEN_APER_TZ_WIDTH 1UL +#define XLPD_XPPU_IEN_APER_TZ_MASK 0x00000040UL +#define XLPD_XPPU_IEN_APER_TZ_DEFVAL 0x0UL + +#define XLPD_XPPU_IEN_APER_PERM_SHIFT 5UL +#define XLPD_XPPU_IEN_APER_PERM_WIDTH 1UL +#define XLPD_XPPU_IEN_APER_PERM_MASK 0x00000020UL +#define XLPD_XPPU_IEN_APER_PERM_DEFVAL 0x0UL + +#define XLPD_XPPU_IEN_MID_PARITY_SHIFT 3UL +#define XLPD_XPPU_IEN_MID_PARITY_WIDTH 1UL +#define XLPD_XPPU_IEN_MID_PARITY_MASK 0x00000008UL +#define XLPD_XPPU_IEN_MID_PARITY_DEFVAL 0x0UL + +#define XLPD_XPPU_IEN_MID_RO_SHIFT 2UL +#define XLPD_XPPU_IEN_MID_RO_WIDTH 1UL +#define XLPD_XPPU_IEN_MID_RO_MASK 0x00000004UL +#define XLPD_XPPU_IEN_MID_RO_DEFVAL 0x0UL + +#define XLPD_XPPU_IEN_MID_MISS_SHIFT 1UL +#define XLPD_XPPU_IEN_MID_MISS_WIDTH 1UL +#define XLPD_XPPU_IEN_MID_MISS_MASK 0x00000002UL +#define XLPD_XPPU_IEN_MID_MISS_DEFVAL 0x0UL + +#define XLPD_XPPU_IEN_INV_APB_SHIFT 0UL +#define XLPD_XPPU_IEN_INV_APB_WIDTH 1UL +#define XLPD_XPPU_IEN_INV_APB_MASK 0x00000001UL +#define XLPD_XPPU_IEN_INV_APB_DEFVAL 0x0UL + +/** + * Register: XlpdXppuIds + */ +#define XLPD_XPPU_IDS ( ( XLPD_XPPU_BASEADDR ) + 0x0000001CUL ) +#define XLPD_XPPU_IDS_RSTVAL 0x00000000UL + +#define XLPD_XPPU_IDS_APER_PARITY_SHIFT 7UL +#define XLPD_XPPU_IDS_APER_PARITY_WIDTH 1UL +#define XLPD_XPPU_IDS_APER_PARITY_MASK 0x00000080UL +#define XLPD_XPPU_IDS_APER_PARITY_DEFVAL 0x0UL + +#define XLPD_XPPU_IDS_APER_TZ_SHIFT 6UL +#define XLPD_XPPU_IDS_APER_TZ_WIDTH 1UL +#define XLPD_XPPU_IDS_APER_TZ_MASK 0x00000040UL +#define XLPD_XPPU_IDS_APER_TZ_DEFVAL 0x0UL + +#define XLPD_XPPU_IDS_APER_PERM_SHIFT 5UL +#define XLPD_XPPU_IDS_APER_PERM_WIDTH 1UL +#define XLPD_XPPU_IDS_APER_PERM_MASK 0x00000020UL +#define XLPD_XPPU_IDS_APER_PERM_DEFVAL 0x0UL + +#define XLPD_XPPU_IDS_MID_PARITY_SHIFT 3UL +#define XLPD_XPPU_IDS_MID_PARITY_WIDTH 1UL +#define XLPD_XPPU_IDS_MID_PARITY_MASK 0x00000008UL +#define XLPD_XPPU_IDS_MID_PARITY_DEFVAL 0x0UL + +#define XLPD_XPPU_IDS_MID_RO_SHIFT 2UL +#define XLPD_XPPU_IDS_MID_RO_WIDTH 1UL +#define XLPD_XPPU_IDS_MID_RO_MASK 0x00000004UL +#define XLPD_XPPU_IDS_MID_RO_DEFVAL 0x0UL + +#define XLPD_XPPU_IDS_MID_MISS_SHIFT 1UL +#define XLPD_XPPU_IDS_MID_MISS_WIDTH 1UL +#define XLPD_XPPU_IDS_MID_MISS_MASK 0x00000002UL +#define XLPD_XPPU_IDS_MID_MISS_DEFVAL 0x0UL + +#define XLPD_XPPU_IDS_INV_APB_SHIFT 0UL +#define XLPD_XPPU_IDS_INV_APB_WIDTH 1UL +#define XLPD_XPPU_IDS_INV_APB_MASK 0x00000001UL +#define XLPD_XPPU_IDS_INV_APB_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMMstrIds + */ +#define XLPD_XPPU_M_MSTR_IDS ( ( XLPD_XPPU_BASEADDR ) + 0x0000003CUL ) +#define XLPD_XPPU_M_MSTR_IDS_RSTVAL 0x00000014UL + +#define XLPD_XPPU_M_MSTR_IDS_NO_SHIFT 0UL +#define XLPD_XPPU_M_MSTR_IDS_NO_WIDTH 32UL +#define XLPD_XPPU_M_MSTR_IDS_NO_MASK 0xffffffffUL +#define XLPD_XPPU_M_MSTR_IDS_NO_DEFVAL 0x14UL + +/** + * Register: XlpdXppuMAperture32b + */ +#define XLPD_XPPU_M_APERTURE_32B ( ( XLPD_XPPU_BASEADDR ) + 0x00000040UL ) +#define XLPD_XPPU_M_APERTURE_32B_RSTVAL 0x00000080UL + +#define XLPD_XPPU_M_APERTURE_32B_NO_SHIFT 0UL +#define XLPD_XPPU_M_APERTURE_32B_NO_WIDTH 32UL +#define XLPD_XPPU_M_APERTURE_32B_NO_MASK 0xffffffffUL +#define XLPD_XPPU_M_APERTURE_32B_NO_DEFVAL 0x80UL + +/** + * Register: XlpdXppuMAperture64kb + */ +#define XLPD_XPPU_M_APERTURE_64KB ( ( XLPD_XPPU_BASEADDR ) + 0x00000044UL ) +#define XLPD_XPPU_M_APERTURE_64KB_RSTVAL 0x00000100UL + +#define XLPD_XPPU_M_APERTURE_64KB_NO_SHIFT 0UL +#define XLPD_XPPU_M_APERTURE_64KB_NO_WIDTH 32UL +#define XLPD_XPPU_M_APERTURE_64KB_NO_MASK 0xffffffffUL +#define XLPD_XPPU_M_APERTURE_64KB_NO_DEFVAL 0x100UL + +/** + * Register: XlpdXppuMAperture1mb + */ +#define XLPD_XPPU_M_APERTURE_1MB ( ( XLPD_XPPU_BASEADDR ) + 0x00000048UL ) +#define XLPD_XPPU_M_APERTURE_1MB_RSTVAL 0x00000010UL + +#define XLPD_XPPU_M_APERTURE_1MB_NO_SHIFT 0UL +#define XLPD_XPPU_M_APERTURE_1MB_NO_WIDTH 32UL +#define XLPD_XPPU_M_APERTURE_1MB_NO_MASK 0xffffffffUL +#define XLPD_XPPU_M_APERTURE_1MB_NO_DEFVAL 0x10UL + +/** + * Register: XlpdXppuMAperture512mb + */ +#define XLPD_XPPU_M_APERTURE_512MB ( ( XLPD_XPPU_BASEADDR ) + 0x0000004CUL ) +#define XLPD_XPPU_M_APERTURE_512MB_RSTVAL 0x00000001UL + +#define XLPD_XPPU_M_APERTURE_512MB_NO_SHIFT 0UL +#define XLPD_XPPU_M_APERTURE_512MB_NO_WIDTH 32UL +#define XLPD_XPPU_M_APERTURE_512MB_NO_MASK 0xffffffffUL +#define XLPD_XPPU_M_APERTURE_512MB_NO_DEFVAL 0x1UL + +/** + * Register: XlpdXppuBase32b + */ +#define XLPD_XPPU_BASE_32B ( ( XLPD_XPPU_BASEADDR ) + 0x00000050UL ) +#define XLPD_XPPU_BASE_32B_RSTVAL 0xff990000UL + +#define XLPD_XPPU_BASE_32B_ADDR_SHIFT 0UL +#define XLPD_XPPU_BASE_32B_ADDR_WIDTH 32UL +#define XLPD_XPPU_BASE_32B_ADDR_MASK 0xffffffffUL +#define XLPD_XPPU_BASE_32B_ADDR_DEFVAL 0xff990000UL + +/** + * Register: XlpdXppuBase64kb + */ +#define XLPD_XPPU_BASE_64KB ( ( XLPD_XPPU_BASEADDR ) + 0x00000054UL ) +#define XLPD_XPPU_BASE_64KB_RSTVAL 0xff000000UL + +#define XLPD_XPPU_BASE_64KB_ADDR_SHIFT 0UL +#define XLPD_XPPU_BASE_64KB_ADDR_WIDTH 32UL +#define XLPD_XPPU_BASE_64KB_ADDR_MASK 0xffffffffUL +#define XLPD_XPPU_BASE_64KB_ADDR_DEFVAL 0xff000000UL + +/** + * Register: XlpdXppuBase1mb + */ +#define XLPD_XPPU_BASE_1MB ( ( XLPD_XPPU_BASEADDR ) + 0x00000058UL ) +#define XLPD_XPPU_BASE_1MB_RSTVAL 0xfe000000UL + +#define XLPD_XPPU_BASE_1MB_ADDR_SHIFT 0UL +#define XLPD_XPPU_BASE_1MB_ADDR_WIDTH 32UL +#define XLPD_XPPU_BASE_1MB_ADDR_MASK 0xffffffffUL +#define XLPD_XPPU_BASE_1MB_ADDR_DEFVAL 0xfe000000UL + +/** + * Register: XlpdXppuBase512mb + */ +#define XLPD_XPPU_BASE_512MB ( ( XLPD_XPPU_BASEADDR ) + 0x0000005CUL ) +#define XLPD_XPPU_BASE_512MB_RSTVAL 0xc0000000UL + +#define XLPD_XPPU_BASE_512MB_ADDR_SHIFT 0UL +#define XLPD_XPPU_BASE_512MB_ADDR_WIDTH 32UL +#define XLPD_XPPU_BASE_512MB_ADDR_MASK 0xffffffffUL +#define XLPD_XPPU_BASE_512MB_ADDR_DEFVAL 0xc0000000UL + +/** + * Register: XlpdXppuMstrId00 + */ +#define XLPD_XPPU_MSTR_ID00 ( ( XLPD_XPPU_BASEADDR ) + 0x00000100UL ) +#define XLPD_XPPU_MSTR_ID00_RSTVAL 0x83ff0040UL + +#define XLPD_XPPU_MSTR_ID00_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID00_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID00_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID00_MIDP_DEFVAL 0x1UL + +#define XLPD_XPPU_MSTR_ID00_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID00_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID00_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID00_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID00_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID00_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID00_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID00_MIDM_DEFVAL 0x3ffUL + +#define XLPD_XPPU_MSTR_ID00_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID00_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID00_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID00_MID_DEFVAL 0x40UL + +/** + * Register: XlpdXppuMstrId01 + */ +#define XLPD_XPPU_MSTR_ID01 ( ( XLPD_XPPU_BASEADDR ) + 0x00000104UL ) +#define XLPD_XPPU_MSTR_ID01_RSTVAL 0x03f00000UL + +#define XLPD_XPPU_MSTR_ID01_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID01_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID01_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID01_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID01_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID01_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID01_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID01_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID01_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID01_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID01_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID01_MIDM_DEFVAL 0x3f0UL + +#define XLPD_XPPU_MSTR_ID01_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID01_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID01_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID01_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId02 + */ +#define XLPD_XPPU_MSTR_ID02 ( ( XLPD_XPPU_BASEADDR ) + 0x00000108UL ) +#define XLPD_XPPU_MSTR_ID02_RSTVAL 0x83f00010UL + +#define XLPD_XPPU_MSTR_ID02_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID02_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID02_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID02_MIDP_DEFVAL 0x1UL + +#define XLPD_XPPU_MSTR_ID02_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID02_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID02_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID02_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID02_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID02_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID02_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID02_MIDM_DEFVAL 0x3f0UL + +#define XLPD_XPPU_MSTR_ID02_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID02_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID02_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID02_MID_DEFVAL 0x10UL + +/** + * Register: XlpdXppuMstrId03 + */ +#define XLPD_XPPU_MSTR_ID03 ( ( XLPD_XPPU_BASEADDR ) + 0x0000010CUL ) +#define XLPD_XPPU_MSTR_ID03_RSTVAL 0x83c00080UL + +#define XLPD_XPPU_MSTR_ID03_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID03_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID03_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID03_MIDP_DEFVAL 0x1UL + +#define XLPD_XPPU_MSTR_ID03_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID03_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID03_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID03_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID03_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID03_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID03_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID03_MIDM_DEFVAL 0x3c0UL + +#define XLPD_XPPU_MSTR_ID03_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID03_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID03_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID03_MID_DEFVAL 0x80UL + +/** + * Register: XlpdXppuMstrId04 + */ +#define XLPD_XPPU_MSTR_ID04 ( ( XLPD_XPPU_BASEADDR ) + 0x00000110UL ) +#define XLPD_XPPU_MSTR_ID04_RSTVAL 0x83c30080UL + +#define XLPD_XPPU_MSTR_ID04_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID04_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID04_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID04_MIDP_DEFVAL 0x1UL + +#define XLPD_XPPU_MSTR_ID04_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID04_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID04_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID04_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID04_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID04_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID04_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID04_MIDM_DEFVAL 0x3c3UL + +#define XLPD_XPPU_MSTR_ID04_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID04_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID04_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID04_MID_DEFVAL 0x80UL + +/** + * Register: XlpdXppuMstrId05 + */ +#define XLPD_XPPU_MSTR_ID05 ( ( XLPD_XPPU_BASEADDR ) + 0x00000114UL ) +#define XLPD_XPPU_MSTR_ID05_RSTVAL 0x03c30081UL + +#define XLPD_XPPU_MSTR_ID05_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID05_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID05_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID05_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID05_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID05_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID05_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID05_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID05_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID05_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID05_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID05_MIDM_DEFVAL 0x3c3UL + +#define XLPD_XPPU_MSTR_ID05_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID05_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID05_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID05_MID_DEFVAL 0x81UL + +/** + * Register: XlpdXppuMstrId06 + */ +#define XLPD_XPPU_MSTR_ID06 ( ( XLPD_XPPU_BASEADDR ) + 0x00000118UL ) +#define XLPD_XPPU_MSTR_ID06_RSTVAL 0x03c30082UL + +#define XLPD_XPPU_MSTR_ID06_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID06_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID06_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID06_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID06_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID06_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID06_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID06_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID06_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID06_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID06_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID06_MIDM_DEFVAL 0x3c3UL + +#define XLPD_XPPU_MSTR_ID06_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID06_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID06_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID06_MID_DEFVAL 0x82UL + +/** + * Register: XlpdXppuMstrId07 + */ +#define XLPD_XPPU_MSTR_ID07 ( ( XLPD_XPPU_BASEADDR ) + 0x0000011CUL ) +#define XLPD_XPPU_MSTR_ID07_RSTVAL 0x83c30083UL + +#define XLPD_XPPU_MSTR_ID07_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID07_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID07_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID07_MIDP_DEFVAL 0x1UL + +#define XLPD_XPPU_MSTR_ID07_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID07_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID07_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID07_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID07_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID07_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID07_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID07_MIDM_DEFVAL 0x3c3UL + +#define XLPD_XPPU_MSTR_ID07_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID07_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID07_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID07_MID_DEFVAL 0x83UL + +/** + * Register: XlpdXppuMstrId08 + */ +#define XLPD_XPPU_MSTR_ID08 ( ( XLPD_XPPU_BASEADDR ) + 0x00000120UL ) +#define XLPD_XPPU_MSTR_ID08_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID08_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID08_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID08_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID08_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID08_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID08_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID08_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID08_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID08_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID08_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID08_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID08_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID08_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID08_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID08_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID08_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId09 + */ +#define XLPD_XPPU_MSTR_ID09 ( ( XLPD_XPPU_BASEADDR ) + 0x00000124UL ) +#define XLPD_XPPU_MSTR_ID09_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID09_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID09_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID09_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID09_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID09_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID09_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID09_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID09_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID09_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID09_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID09_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID09_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID09_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID09_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID09_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID09_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId10 + */ +#define XLPD_XPPU_MSTR_ID10 ( ( XLPD_XPPU_BASEADDR ) + 0x00000128UL ) +#define XLPD_XPPU_MSTR_ID10_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID10_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID10_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID10_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID10_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID10_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID10_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID10_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID10_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID10_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID10_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID10_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID10_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID10_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID10_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID10_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID10_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId11 + */ +#define XLPD_XPPU_MSTR_ID11 ( ( XLPD_XPPU_BASEADDR ) + 0x0000012CUL ) +#define XLPD_XPPU_MSTR_ID11_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID11_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID11_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID11_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID11_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID11_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID11_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID11_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID11_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID11_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID11_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID11_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID11_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID11_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID11_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID11_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID11_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId12 + */ +#define XLPD_XPPU_MSTR_ID12 ( ( XLPD_XPPU_BASEADDR ) + 0x00000130UL ) +#define XLPD_XPPU_MSTR_ID12_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID12_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID12_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID12_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID12_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID12_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID12_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID12_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID12_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID12_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID12_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID12_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID12_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID12_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID12_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID12_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID12_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId13 + */ +#define XLPD_XPPU_MSTR_ID13 ( ( XLPD_XPPU_BASEADDR ) + 0x00000134UL ) +#define XLPD_XPPU_MSTR_ID13_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID13_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID13_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID13_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID13_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID13_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID13_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID13_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID13_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID13_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID13_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID13_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID13_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID13_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID13_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID13_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID13_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId14 + */ +#define XLPD_XPPU_MSTR_ID14 ( ( XLPD_XPPU_BASEADDR ) + 0x00000138UL ) +#define XLPD_XPPU_MSTR_ID14_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID14_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID14_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID14_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID14_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID14_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID14_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID14_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID14_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID14_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID14_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID14_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID14_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID14_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID14_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID14_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID14_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId15 + */ +#define XLPD_XPPU_MSTR_ID15 ( ( XLPD_XPPU_BASEADDR ) + 0x0000013CUL ) +#define XLPD_XPPU_MSTR_ID15_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID15_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID15_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID15_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID15_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID15_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID15_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID15_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID15_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID15_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID15_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID15_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID15_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID15_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID15_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID15_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID15_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId16 + */ +#define XLPD_XPPU_MSTR_ID16 ( ( XLPD_XPPU_BASEADDR ) + 0x00000140UL ) +#define XLPD_XPPU_MSTR_ID16_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID16_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID16_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID16_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID16_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID16_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID16_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID16_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID16_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID16_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID16_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID16_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID16_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID16_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID16_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID16_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID16_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId17 + */ +#define XLPD_XPPU_MSTR_ID17 ( ( XLPD_XPPU_BASEADDR ) + 0x00000144UL ) +#define XLPD_XPPU_MSTR_ID17_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID17_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID17_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID17_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID17_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID17_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID17_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID17_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID17_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID17_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID17_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID17_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID17_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID17_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID17_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID17_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID17_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId18 + */ +#define XLPD_XPPU_MSTR_ID18 ( ( XLPD_XPPU_BASEADDR ) + 0x00000148UL ) +#define XLPD_XPPU_MSTR_ID18_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID18_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID18_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID18_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID18_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID18_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID18_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID18_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID18_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID18_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID18_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID18_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID18_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID18_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID18_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID18_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID18_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId19 + */ +#define XLPD_XPPU_MSTR_ID19 ( ( XLPD_XPPU_BASEADDR ) + 0x0000014CUL ) +#define XLPD_XPPU_MSTR_ID19_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID19_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID19_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID19_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID19_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID19_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID19_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID19_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID19_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID19_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID19_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID19_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID19_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID19_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID19_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID19_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID19_MID_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XLPD_XPPU_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xlpd_xppu_sink.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xlpd_xppu_sink.h new file mode 100644 index 0000000..95f7e20 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xlpd_xppu_sink.h
@@ -0,0 +1,81 @@ +/* ### HEADER ### */ + +#ifndef __XLPD_XPPU_SINK_H__ +#define __XLPD_XPPU_SINK_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XlpdXppuSink Base Address + */ +#define XLPD_XPPU_SINK_BASEADDR 0xFF9C0000UL + +/** + * Register: XlpdXppuSinkErrSts + */ +#define XLPD_XPPU_SINK_ERR_STS ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF00UL ) +#define XLPD_XPPU_SINK_ERR_STS_RSTVAL 0x00000000UL + +#define XLPD_XPPU_SINK_ERR_STS_RDWR_SHIFT 31UL +#define XLPD_XPPU_SINK_ERR_STS_RDWR_WIDTH 1UL +#define XLPD_XPPU_SINK_ERR_STS_RDWR_MASK 0x80000000UL +#define XLPD_XPPU_SINK_ERR_STS_RDWR_DEFVAL 0x0UL + +#define XLPD_XPPU_SINK_ERR_STS_ADDR_SHIFT 0UL +#define XLPD_XPPU_SINK_ERR_STS_ADDR_WIDTH 12UL +#define XLPD_XPPU_SINK_ERR_STS_ADDR_MASK 0x00000fffUL +#define XLPD_XPPU_SINK_ERR_STS_ADDR_DEFVAL 0x0UL + +/** + * Register: XlpdXppuSinkIsr + */ +#define XLPD_XPPU_SINK_ISR ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF10UL ) +#define XLPD_XPPU_SINK_ISR_RSTVAL 0x00000000UL + +#define XLPD_XPPU_SINK_ISRADDRDECDERR_SHIFT 0UL +#define XLPD_XPPU_SINK_ISRADDRDECDERR_WIDTH 1UL +#define XLPD_XPPU_SINK_ISRADDRDECDERR_MASK 0x00000001UL +#define XLPD_XPPU_SINK_ISRADDRDECDERR_DEFVAL 0x0UL + +/** + * Register: XlpdXppuSinkImr + */ +#define XLPD_XPPU_SINK_IMR ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF14UL ) +#define XLPD_XPPU_SINK_IMR_RSTVAL 0x00000001UL + +#define XLPD_XPPU_SINK_IMRADDRDECDERR_SHIFT 0UL +#define XLPD_XPPU_SINK_IMRADDRDECDERR_WIDTH 1UL +#define XLPD_XPPU_SINK_IMRADDRDECDERR_MASK 0x00000001UL +#define XLPD_XPPU_SINK_IMRADDRDECDERR_DEFVAL 0x1UL + +/** + * Register: XlpdXppuSinkIer + */ +#define XLPD_XPPU_SINK_IER ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF18UL ) +#define XLPD_XPPU_SINK_IER_RSTVAL 0x00000000UL + +#define XLPD_XPPU_SINK_IERADDRDECDERR_SHIFT 0UL +#define XLPD_XPPU_SINK_IERADDRDECDERR_WIDTH 1UL +#define XLPD_XPPU_SINK_IERADDRDECDERR_MASK 0x00000001UL +#define XLPD_XPPU_SINK_IERADDRDECDERR_DEFVAL 0x0UL + +/** + * Register: XlpdXppuSinkIdr + */ +#define XLPD_XPPU_SINK_IDR ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF1CUL ) +#define XLPD_XPPU_SINK_IDR_RSTVAL 0x00000000UL + +#define XLPD_XPPU_SINK_IDRADDRDECDERR_SHIFT 0UL +#define XLPD_XPPU_SINK_IDRADDRDECDERR_WIDTH 1UL +#define XLPD_XPPU_SINK_IDRADDRDECDERR_MASK 0x00000001UL +#define XLPD_XPPU_SINK_IDRADDRDECDERR_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XLPD_XPPU_SINK_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xocm_xmpu_cfg.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xocm_xmpu_cfg.h new file mode 100644 index 0000000..5e3631f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xocm_xmpu_cfg.h
@@ -0,0 +1,1304 @@ +/* ### HEADER ### */ + +#ifndef __XOCM_XMPU_CFG_H__ +#define __XOCM_XMPU_CFG_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XocmXmpuCfg Base Address + */ +#define XOCM_XMPU_CFG_BASEADDR 0xFFA70000UL + +/** + * Register: XocmXmpuCfgCtrl + */ +#define XOCM_XMPU_CFG_CTRL ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000000UL ) +#define XOCM_XMPU_CFG_CTRL_RSTVAL 0x00000003UL + +#define XOCM_XMPU_CFG_CTRL_ALIGNCFG_SHIFT 3UL +#define XOCM_XMPU_CFG_CTRL_ALIGNCFG_WIDTH 1UL +#define XOCM_XMPU_CFG_CTRL_ALIGNCFG_MASK 0x00000008UL +#define XOCM_XMPU_CFG_CTRL_ALIGNCFG_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_CTRL_POISONCFG_SHIFT 2UL +#define XOCM_XMPU_CFG_CTRL_POISONCFG_WIDTH 1UL +#define XOCM_XMPU_CFG_CTRL_POISONCFG_MASK 0x00000004UL +#define XOCM_XMPU_CFG_CTRL_POISONCFG_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_CTRL_DEFWRALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_CTRL_DEFWRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_CTRL_DEFWRALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_CTRL_DEFWRALWD_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_CTRL_DEFRDALWD_SHIFT 0UL +#define XOCM_XMPU_CFG_CTRL_DEFRDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_CTRL_DEFRDALWD_MASK 0x00000001UL +#define XOCM_XMPU_CFG_CTRL_DEFRDALWD_DEFVAL 0x1UL + +/** + * Register: XocmXmpuCfgErrSts1 + */ +#define XOCM_XMPU_CFG_ERR_STS1 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000004UL ) +#define XOCM_XMPU_CFG_ERR_STS1_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_ERR_STS1_AXI_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_ERR_STS1_AXI_ADDR_WIDTH 32UL +#define XOCM_XMPU_CFG_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL +#define XOCM_XMPU_CFG_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgErrSts2 + */ +#define XOCM_XMPU_CFG_ERR_STS2 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000008UL ) +#define XOCM_XMPU_CFG_ERR_STS2_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_ERR_STS2_AXI_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_ERR_STS2_AXI_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_ERR_STS2_AXI_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_ERR_STS2_AXI_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgPoison + */ +#define XOCM_XMPU_CFG_POISON ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000000CUL ) +#define XOCM_XMPU_CFG_POISON_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_POISON_ATTRIB_SHIFT 20UL +#define XOCM_XMPU_CFG_POISON_ATTRIB_WIDTH 12UL +#define XOCM_XMPU_CFG_POISON_ATTRIB_MASK 0xfff00000UL +#define XOCM_XMPU_CFG_POISON_ATTRIB_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_POISON_BASE_SHIFT 0UL +#define XOCM_XMPU_CFG_POISON_BASE_WIDTH 20UL +#define XOCM_XMPU_CFG_POISON_BASE_MASK 0x000fffffUL +#define XOCM_XMPU_CFG_POISON_BASE_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgIsr + */ +#define XOCM_XMPU_CFG_ISR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000010UL ) +#define XOCM_XMPU_CFG_ISR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_ISR_SECURTYVIO_SHIFT 3UL +#define XOCM_XMPU_CFG_ISR_SECURTYVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_ISR_SECURTYVIO_MASK 0x00000008UL +#define XOCM_XMPU_CFG_ISR_SECURTYVIO_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_ISR_WRPERMVIO_SHIFT 2UL +#define XOCM_XMPU_CFG_ISR_WRPERMVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_ISR_WRPERMVIO_MASK 0x00000004UL +#define XOCM_XMPU_CFG_ISR_WRPERMVIO_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_ISR_RDPERMVIO_SHIFT 1UL +#define XOCM_XMPU_CFG_ISR_RDPERMVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_ISR_RDPERMVIO_MASK 0x00000002UL +#define XOCM_XMPU_CFG_ISR_RDPERMVIO_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_ISR_INV_APB_SHIFT 0UL +#define XOCM_XMPU_CFG_ISR_INV_APB_WIDTH 1UL +#define XOCM_XMPU_CFG_ISR_INV_APB_MASK 0x00000001UL +#define XOCM_XMPU_CFG_ISR_INV_APB_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgImr + */ +#define XOCM_XMPU_CFG_IMR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000014UL ) +#define XOCM_XMPU_CFG_IMR_RSTVAL 0x0000000fUL + +#define XOCM_XMPU_CFG_IMR_SECURTYVIO_SHIFT 3UL +#define XOCM_XMPU_CFG_IMR_SECURTYVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_IMR_SECURTYVIO_MASK 0x00000008UL +#define XOCM_XMPU_CFG_IMR_SECURTYVIO_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_IMR_WRPERMVIO_SHIFT 2UL +#define XOCM_XMPU_CFG_IMR_WRPERMVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_IMR_WRPERMVIO_MASK 0x00000004UL +#define XOCM_XMPU_CFG_IMR_WRPERMVIO_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_IMR_RDPERMVIO_SHIFT 1UL +#define XOCM_XMPU_CFG_IMR_RDPERMVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_IMR_RDPERMVIO_MASK 0x00000002UL +#define XOCM_XMPU_CFG_IMR_RDPERMVIO_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_IMR_INV_APB_SHIFT 0UL +#define XOCM_XMPU_CFG_IMR_INV_APB_WIDTH 1UL +#define XOCM_XMPU_CFG_IMR_INV_APB_MASK 0x00000001UL +#define XOCM_XMPU_CFG_IMR_INV_APB_DEFVAL 0x1UL + +/** + * Register: XocmXmpuCfgIen + */ +#define XOCM_XMPU_CFG_IEN ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000018UL ) +#define XOCM_XMPU_CFG_IEN_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_IEN_SECURTYVIO_SHIFT 3UL +#define XOCM_XMPU_CFG_IEN_SECURTYVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_IEN_SECURTYVIO_MASK 0x00000008UL +#define XOCM_XMPU_CFG_IEN_SECURTYVIO_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_IEN_WRPERMVIO_SHIFT 2UL +#define XOCM_XMPU_CFG_IEN_WRPERMVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_IEN_WRPERMVIO_MASK 0x00000004UL +#define XOCM_XMPU_CFG_IEN_WRPERMVIO_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_IEN_RDPERMVIO_SHIFT 1UL +#define XOCM_XMPU_CFG_IEN_RDPERMVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_IEN_RDPERMVIO_MASK 0x00000002UL +#define XOCM_XMPU_CFG_IEN_RDPERMVIO_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_IEN_INV_APB_SHIFT 0UL +#define XOCM_XMPU_CFG_IEN_INV_APB_WIDTH 1UL +#define XOCM_XMPU_CFG_IEN_INV_APB_MASK 0x00000001UL +#define XOCM_XMPU_CFG_IEN_INV_APB_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgIds + */ +#define XOCM_XMPU_CFG_IDS ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000001CUL ) +#define XOCM_XMPU_CFG_IDS_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_IDS_SECURTYVIO_SHIFT 3UL +#define XOCM_XMPU_CFG_IDS_SECURTYVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_IDS_SECURTYVIO_MASK 0x00000008UL +#define XOCM_XMPU_CFG_IDS_SECURTYVIO_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_IDS_WRPERMVIO_SHIFT 2UL +#define XOCM_XMPU_CFG_IDS_WRPERMVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_IDS_WRPERMVIO_MASK 0x00000004UL +#define XOCM_XMPU_CFG_IDS_WRPERMVIO_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_IDS_RDPERMVIO_SHIFT 1UL +#define XOCM_XMPU_CFG_IDS_RDPERMVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_IDS_RDPERMVIO_MASK 0x00000002UL +#define XOCM_XMPU_CFG_IDS_RDPERMVIO_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_IDS_INV_APB_SHIFT 0UL +#define XOCM_XMPU_CFG_IDS_INV_APB_WIDTH 1UL +#define XOCM_XMPU_CFG_IDS_INV_APB_MASK 0x00000001UL +#define XOCM_XMPU_CFG_IDS_INV_APB_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgLock + */ +#define XOCM_XMPU_CFG_LOCK ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000020UL ) +#define XOCM_XMPU_CFG_LOCK_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_LOCK_REGWRDIS_SHIFT 0UL +#define XOCM_XMPU_CFG_LOCK_REGWRDIS_WIDTH 1UL +#define XOCM_XMPU_CFG_LOCK_REGWRDIS_MASK 0x00000001UL +#define XOCM_XMPU_CFG_LOCK_REGWRDIS_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR00Strt + */ +#define XOCM_XMPU_CFG_R00_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000100UL ) +#define XOCM_XMPU_CFG_R00_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R00_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R00_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R00_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R00_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR00End + */ +#define XOCM_XMPU_CFG_R00_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000104UL ) +#define XOCM_XMPU_CFG_R00_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R00_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R00_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R00_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R00_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR00Mstr + */ +#define XOCM_XMPU_CFG_R00_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000108UL ) +#define XOCM_XMPU_CFG_R00_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R00_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R00_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R00_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R00_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R00_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R00_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R00_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R00_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR00 + */ +#define XOCM_XMPU_CFG_R00 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000010CUL ) +#define XOCM_XMPU_CFG_R00_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R00_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R00_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R00_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R00_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R00_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R00_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R00_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R00_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R00_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R00_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R00_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R00_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R00_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R00_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R00_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R00_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R00_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R00_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R00_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R00_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR01Strt + */ +#define XOCM_XMPU_CFG_R01_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000110UL ) +#define XOCM_XMPU_CFG_R01_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R01_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R01_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R01_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R01_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR01End + */ +#define XOCM_XMPU_CFG_R01_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000114UL ) +#define XOCM_XMPU_CFG_R01_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R01_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R01_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R01_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R01_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR01Mstr + */ +#define XOCM_XMPU_CFG_R01_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000118UL ) +#define XOCM_XMPU_CFG_R01_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R01_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R01_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R01_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R01_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R01_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R01_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R01_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R01_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR01 + */ +#define XOCM_XMPU_CFG_R01 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000011CUL ) +#define XOCM_XMPU_CFG_R01_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R01_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R01_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R01_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R01_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R01_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R01_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R01_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R01_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R01_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R01_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R01_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R01_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R01_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R01_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R01_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R01_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R01_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R01_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R01_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R01_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR02Strt + */ +#define XOCM_XMPU_CFG_R02_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000120UL ) +#define XOCM_XMPU_CFG_R02_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R02_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R02_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R02_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R02_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR02End + */ +#define XOCM_XMPU_CFG_R02_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000124UL ) +#define XOCM_XMPU_CFG_R02_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R02_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R02_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R02_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R02_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR02Mstr + */ +#define XOCM_XMPU_CFG_R02_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000128UL ) +#define XOCM_XMPU_CFG_R02_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R02_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R02_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R02_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R02_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R02_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R02_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R02_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R02_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR02 + */ +#define XOCM_XMPU_CFG_R02 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000012CUL ) +#define XOCM_XMPU_CFG_R02_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R02_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R02_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R02_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R02_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R02_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R02_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R02_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R02_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R02_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R02_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R02_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R02_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R02_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R02_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R02_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R02_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R02_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R02_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R02_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R02_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR03Strt + */ +#define XOCM_XMPU_CFG_R03_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000130UL ) +#define XOCM_XMPU_CFG_R03_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R03_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R03_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R03_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R03_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR03End + */ +#define XOCM_XMPU_CFG_R03_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000134UL ) +#define XOCM_XMPU_CFG_R03_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R03_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R03_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R03_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R03_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR03Mstr + */ +#define XOCM_XMPU_CFG_R03_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000138UL ) +#define XOCM_XMPU_CFG_R03_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R03_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R03_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R03_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R03_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R03_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R03_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R03_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R03_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR03 + */ +#define XOCM_XMPU_CFG_R03 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000013CUL ) +#define XOCM_XMPU_CFG_R03_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R03_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R03_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R03_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R03_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R03_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R03_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R03_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R03_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R03_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R03_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R03_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R03_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R03_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R03_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R03_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R03_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R03_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R03_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R03_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R03_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR04Strt + */ +#define XOCM_XMPU_CFG_R04_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000140UL ) +#define XOCM_XMPU_CFG_R04_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R04_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R04_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R04_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R04_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR04End + */ +#define XOCM_XMPU_CFG_R04_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000144UL ) +#define XOCM_XMPU_CFG_R04_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R04_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R04_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R04_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R04_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR04Mstr + */ +#define XOCM_XMPU_CFG_R04_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000148UL ) +#define XOCM_XMPU_CFG_R04_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R04_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R04_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R04_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R04_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R04_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R04_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R04_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R04_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR04 + */ +#define XOCM_XMPU_CFG_R04 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000014CUL ) +#define XOCM_XMPU_CFG_R04_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R04_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R04_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R04_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R04_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R04_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R04_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R04_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R04_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R04_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R04_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R04_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R04_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R04_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R04_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R04_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R04_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R04_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R04_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R04_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R04_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR05Strt + */ +#define XOCM_XMPU_CFG_R05_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000150UL ) +#define XOCM_XMPU_CFG_R05_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R05_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R05_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R05_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R05_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR05End + */ +#define XOCM_XMPU_CFG_R05_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000154UL ) +#define XOCM_XMPU_CFG_R05_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R05_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R05_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R05_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R05_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR05Mstr + */ +#define XOCM_XMPU_CFG_R05_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000158UL ) +#define XOCM_XMPU_CFG_R05_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R05_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R05_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R05_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R05_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R05_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R05_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R05_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R05_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR05 + */ +#define XOCM_XMPU_CFG_R05 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000015CUL ) +#define XOCM_XMPU_CFG_R05_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R05_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R05_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R05_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R05_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R05_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R05_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R05_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R05_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R05_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R05_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R05_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R05_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R05_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R05_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R05_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R05_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R05_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R05_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R05_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R05_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR06Strt + */ +#define XOCM_XMPU_CFG_R06_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000160UL ) +#define XOCM_XMPU_CFG_R06_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R06_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R06_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R06_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R06_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR06End + */ +#define XOCM_XMPU_CFG_R06_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000164UL ) +#define XOCM_XMPU_CFG_R06_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R06_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R06_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R06_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R06_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR06Mstr + */ +#define XOCM_XMPU_CFG_R06_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000168UL ) +#define XOCM_XMPU_CFG_R06_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R06_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R06_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R06_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R06_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R06_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R06_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R06_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R06_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR06 + */ +#define XOCM_XMPU_CFG_R06 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000016CUL ) +#define XOCM_XMPU_CFG_R06_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R06_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R06_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R06_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R06_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R06_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R06_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R06_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R06_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R06_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R06_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R06_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R06_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R06_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R06_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R06_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R06_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R06_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R06_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R06_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R06_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR07Strt + */ +#define XOCM_XMPU_CFG_R07_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000170UL ) +#define XOCM_XMPU_CFG_R07_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R07_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R07_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R07_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R07_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR07End + */ +#define XOCM_XMPU_CFG_R07_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000174UL ) +#define XOCM_XMPU_CFG_R07_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R07_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R07_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R07_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R07_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR07Mstr + */ +#define XOCM_XMPU_CFG_R07_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000178UL ) +#define XOCM_XMPU_CFG_R07_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R07_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R07_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R07_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R07_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R07_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R07_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R07_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R07_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR07 + */ +#define XOCM_XMPU_CFG_R07 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000017CUL ) +#define XOCM_XMPU_CFG_R07_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R07_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R07_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R07_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R07_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R07_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R07_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R07_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R07_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R07_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R07_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R07_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R07_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R07_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R07_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R07_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R07_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R07_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R07_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R07_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R07_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR08Strt + */ +#define XOCM_XMPU_CFG_R08_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000180UL ) +#define XOCM_XMPU_CFG_R08_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R08_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R08_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R08_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R08_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR08End + */ +#define XOCM_XMPU_CFG_R08_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000184UL ) +#define XOCM_XMPU_CFG_R08_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R08_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R08_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R08_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R08_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR08Mstr + */ +#define XOCM_XMPU_CFG_R08_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000188UL ) +#define XOCM_XMPU_CFG_R08_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R08_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R08_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R08_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R08_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R08_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R08_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R08_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R08_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR08 + */ +#define XOCM_XMPU_CFG_R08 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000018CUL ) +#define XOCM_XMPU_CFG_R08_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R08_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R08_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R08_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R08_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R08_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R08_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R08_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R08_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R08_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R08_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R08_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R08_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R08_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R08_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R08_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R08_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R08_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R08_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R08_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R08_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR09Strt + */ +#define XOCM_XMPU_CFG_R09_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000190UL ) +#define XOCM_XMPU_CFG_R09_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R09_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R09_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R09_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R09_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR09End + */ +#define XOCM_XMPU_CFG_R09_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000194UL ) +#define XOCM_XMPU_CFG_R09_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R09_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R09_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R09_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R09_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR09Mstr + */ +#define XOCM_XMPU_CFG_R09_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000198UL ) +#define XOCM_XMPU_CFG_R09_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R09_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R09_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R09_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R09_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R09_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R09_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R09_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R09_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR09 + */ +#define XOCM_XMPU_CFG_R09 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000019CUL ) +#define XOCM_XMPU_CFG_R09_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R09_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R09_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R09_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R09_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R09_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R09_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R09_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R09_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R09_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R09_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R09_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R09_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R09_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R09_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R09_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R09_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R09_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R09_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R09_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R09_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR10Strt + */ +#define XOCM_XMPU_CFG_R10_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001A0UL ) +#define XOCM_XMPU_CFG_R10_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R10_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R10_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R10_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R10_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR10End + */ +#define XOCM_XMPU_CFG_R10_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001A4UL ) +#define XOCM_XMPU_CFG_R10_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R10_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R10_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R10_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R10_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR10Mstr + */ +#define XOCM_XMPU_CFG_R10_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001A8UL ) +#define XOCM_XMPU_CFG_R10_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R10_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R10_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R10_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R10_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R10_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R10_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R10_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R10_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR10 + */ +#define XOCM_XMPU_CFG_R10 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001ACUL ) +#define XOCM_XMPU_CFG_R10_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R10_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R10_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R10_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R10_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R10_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R10_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R10_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R10_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R10_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R10_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R10_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R10_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R10_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R10_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R10_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R10_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R10_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R10_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R10_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R10_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR11Strt + */ +#define XOCM_XMPU_CFG_R11_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001B0UL ) +#define XOCM_XMPU_CFG_R11_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R11_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R11_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R11_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R11_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR11End + */ +#define XOCM_XMPU_CFG_R11_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001B4UL ) +#define XOCM_XMPU_CFG_R11_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R11_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R11_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R11_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R11_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR11Mstr + */ +#define XOCM_XMPU_CFG_R11_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001B8UL ) +#define XOCM_XMPU_CFG_R11_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R11_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R11_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R11_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R11_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R11_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R11_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R11_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R11_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR11 + */ +#define XOCM_XMPU_CFG_R11 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001BCUL ) +#define XOCM_XMPU_CFG_R11_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R11_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R11_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R11_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R11_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R11_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R11_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R11_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R11_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R11_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R11_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R11_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R11_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R11_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R11_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R11_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R11_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R11_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R11_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R11_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R11_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR12Strt + */ +#define XOCM_XMPU_CFG_R12_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001C0UL ) +#define XOCM_XMPU_CFG_R12_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R12_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R12_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R12_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R12_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR12End + */ +#define XOCM_XMPU_CFG_R12_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001C4UL ) +#define XOCM_XMPU_CFG_R12_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R12_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R12_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R12_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R12_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR12Mstr + */ +#define XOCM_XMPU_CFG_R12_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001C8UL ) +#define XOCM_XMPU_CFG_R12_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R12_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R12_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R12_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R12_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R12_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R12_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R12_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R12_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR12 + */ +#define XOCM_XMPU_CFG_R12 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001CCUL ) +#define XOCM_XMPU_CFG_R12_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R12_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R12_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R12_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R12_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R12_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R12_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R12_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R12_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R12_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R12_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R12_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R12_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R12_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R12_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R12_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R12_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R12_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R12_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R12_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R12_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR13Strt + */ +#define XOCM_XMPU_CFG_R13_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001D0UL ) +#define XOCM_XMPU_CFG_R13_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R13_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R13_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R13_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R13_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR13End + */ +#define XOCM_XMPU_CFG_R13_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001D4UL ) +#define XOCM_XMPU_CFG_R13_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R13_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R13_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R13_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R13_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR13Mstr + */ +#define XOCM_XMPU_CFG_R13_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001D8UL ) +#define XOCM_XMPU_CFG_R13_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R13_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R13_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R13_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R13_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R13_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R13_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R13_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R13_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR13 + */ +#define XOCM_XMPU_CFG_R13 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001DCUL ) +#define XOCM_XMPU_CFG_R13_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R13_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R13_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R13_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R13_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R13_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R13_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R13_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R13_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R13_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R13_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R13_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R13_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R13_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R13_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R13_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R13_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R13_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R13_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R13_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R13_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR14Strt + */ +#define XOCM_XMPU_CFG_R14_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001E0UL ) +#define XOCM_XMPU_CFG_R14_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R14_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R14_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R14_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R14_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR14End + */ +#define XOCM_XMPU_CFG_R14_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001E4UL ) +#define XOCM_XMPU_CFG_R14_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R14_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R14_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R14_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R14_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR14Mstr + */ +#define XOCM_XMPU_CFG_R14_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001E8UL ) +#define XOCM_XMPU_CFG_R14_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R14_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R14_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R14_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R14_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R14_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R14_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R14_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R14_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR14 + */ +#define XOCM_XMPU_CFG_R14 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001ECUL ) +#define XOCM_XMPU_CFG_R14_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R14_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R14_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R14_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R14_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R14_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R14_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R14_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R14_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R14_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R14_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R14_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R14_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R14_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R14_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R14_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R14_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R14_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R14_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R14_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R14_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR15Strt + */ +#define XOCM_XMPU_CFG_R15_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001F0UL ) +#define XOCM_XMPU_CFG_R15_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R15_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R15_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R15_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R15_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR15End + */ +#define XOCM_XMPU_CFG_R15_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001F4UL ) +#define XOCM_XMPU_CFG_R15_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R15_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R15_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R15_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R15_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR15Mstr + */ +#define XOCM_XMPU_CFG_R15_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001F8UL ) +#define XOCM_XMPU_CFG_R15_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R15_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R15_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R15_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R15_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R15_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R15_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R15_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R15_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR15 + */ +#define XOCM_XMPU_CFG_R15 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001FCUL ) +#define XOCM_XMPU_CFG_R15_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R15_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R15_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R15_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R15_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R15_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R15_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R15_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R15_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R15_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R15_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R15_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R15_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R15_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R15_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R15_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R15_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R15_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R15_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R15_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R15_EN_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XOCM_XMPU_CFG_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/initialise_monitor_handles.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/initialise_monitor_handles.c new file mode 100644 index 0000000..a2494c5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/initialise_monitor_handles.c
@@ -0,0 +1,52 @@ +/****************************************************************************** +* +* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file initialise_monitor_handles.c +* +* Contains blank function to avoid compilation error +* +* @note +* +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- -------- -------- ----------------------------------------------- +* 5.00 pkp 05/29/14 First release +* </pre> +******************************************************************************/ +__attribute__((weak)) void initialise_monitor_handles(){ + +}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/isatty.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/isatty.c new file mode 100644 index 0000000..f142515 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/isatty.c
@@ -0,0 +1,56 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +#include <unistd.h> +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) sint32 _isatty(sint32 fd); +} +#endif + +/* + * isatty -- returns 1 if connected to a terminal device, + * returns 0 if not. Since we're hooked up to a + * serial port, we'll say yes _AND return a 1. + */ +__attribute__((weak)) sint32 isatty(sint32 fd) +{ + (void)fd; + return (1); +} + +__attribute__((weak)) sint32 _isatty(sint32 fd) +{ + (void)fd; + return (1); +}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/kill.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/kill.c new file mode 100644 index 0000000..fc2f89d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/kill.c
@@ -0,0 +1,60 @@ +/****************************************************************************** +* +* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +#include <signal.h> +#include <unistd.h> +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) int _kill(pid_t pid, int sig); +} +#endif + +/* + * kill -- go out via exit... + */ + +__attribute__((weak)) int kill(pid_t pid, int sig) +{ + if(pid == 1) { + _exit(sig); + } + return 0; +} + +__attribute__((weak)) int _kill(pid_t pid, int sig) +{ + if(pid == 1) { + _exit(sig); + } + return 0; +}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/lseek.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/lseek.c new file mode 100644 index 0000000..106c45c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/lseek.c
@@ -0,0 +1,61 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include <sys/types.h> +#include <errno.h> +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence); +} +#endif +/* + * lseek -- Since a serial port is non-seekable, we return an error. + */ +__attribute__((weak)) off_t lseek(s32 fd, off_t offset, s32 whence) +{ + (void)fd; + (void)offset; + (void)whence; + errno = ESPIPE; + return ((off_t)-1); +} + +__attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence) +{ + (void)fd; + (void)offset; + (void)whence; + errno = ESPIPE; + return ((off_t)-1); +}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/open.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/open.c new file mode 100644 index 0000000..85e9ce4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/open.c
@@ -0,0 +1,53 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +#ifndef UNDEFINE_FILE_OPS +#include <errno.h> +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode); +} +#endif +/* + * open -- open a file descriptor. We don't have a filesystem, so + * we return an error. + */ +__attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode) +{ + (void)buf; + (void)flags; + (void)mode; + errno = EIO; + return (-1); +} +#endif
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/outbyte.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/outbyte.c new file mode 100644 index 0000000..3c64308 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/outbyte.c
@@ -0,0 +1,15 @@ +#include "xparameters.h" +#include "xuartps_hw.h" + +#ifdef __cplusplus +extern "C" { +#endif +void outbyte(char c); + +#ifdef __cplusplus +} +#endif + +void outbyte(char c) { + XUartPs_SendByte(STDOUT_BASEADDRESS, c); +}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/print.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/print.c new file mode 100644 index 0000000..da7e768 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/print.c
@@ -0,0 +1,36 @@ +/* print.c -- print a string on the output device. + * + * Copyright (c) 1995 Cygnus Support + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + * + */ + +/* + * print -- do a raw print of a string + */ +#include "xil_printf.h" + +void print(const char8 *ptr) +{ +#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE + XPVXenConsole_Write(ptr); +#else +#ifdef STDOUT_BASEADDRESS + while (*ptr != (char8)0) { + outbyte (*ptr); + ptr++; + } +#else +(void)ptr; +#endif +#endif +}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/putnum.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/putnum.c new file mode 100644 index 0000000..aaf9ede --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/putnum.c
@@ -0,0 +1,59 @@ +/* putnum.c -- put a hex number on the output device. + * + * Copyright (c) 1995 Cygnus Support + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + */ + +/* + * putnum -- print a 32 bit number in hex + */ + +/***************************** Include Files *********************************/ +#include "xil_types.h" + +/************************** Function Prototypes ******************************/ +extern void print (const char8 *ptr); +void putnum(u32 num); + +void putnum(u32 num) +{ + char8 buf[9]; + s32 cnt; + s32 i; + char8 *ptr; + u32 digit; + for(i = 0; i<9; i++) { + buf[i] = '0'; + } + + ptr = buf; + for (cnt = 7 ; cnt >= 0 ; cnt--) { + digit = (num >> (cnt * 4U)) & 0x0000000fU; + + if ((digit <= 9U) && (ptr != NULL)) { + digit += (u32)'0'; + *ptr = ((char8) digit); + ptr += 1; + } else if (ptr != NULL) { + digit += ((u32)'a' - (u32)10); + *ptr = ((char8)digit); + ptr += 1; + } else { + /*Made for MisraC Compliance*/; + } + } + + if(ptr != NULL) { + *ptr = (char8) 0; + } + print (buf); +}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/read.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/read.c new file mode 100644 index 0000000..7f7b7d2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/read.c
@@ -0,0 +1,104 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/* read.c -- read bytes from a input device. + */ +#ifndef UNDEFINE_FILE_OPS +#include "xil_printf.h" +#include "xparameters.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) s32 _read (s32 fd, char8* buf, s32 nbytes); +} +#endif + +/* + * read -- read bytes from the serial port. Ignore fd, since + * we only have stdin. + */ +__attribute__((weak)) s32 +read (s32 fd, char8* buf, s32 nbytes) +{ +#ifdef STDIN_BASEADDRESS + s32 i; + s32 numbytes = 0; + char8* LocalBuf = buf; + + (void)fd; + if(LocalBuf != NULL) { + for (i = 0; i < nbytes; i++) { + numbytes++; + *(LocalBuf + i) = inbyte(); + if ((*(LocalBuf + i) == '\n' )|| (*(LocalBuf + i) == '\r')) { + break; + } + } + } + + return numbytes; +#else + (void)fd; + (void)buf; + (void)nbytes; + return 0; +#endif +} + +__attribute__((weak)) s32 +_read (s32 fd, char8* buf, s32 nbytes) +{ +#ifdef STDIN_BASEADDRESS + s32 i; + s32 numbytes = 0; + char8* LocalBuf = buf; + + (void)fd; + if(LocalBuf != NULL) { + for (i = 0; i < nbytes; i++) { + numbytes++; + *(LocalBuf + i) = inbyte(); + if ((*(LocalBuf + i) == '\n' )|| (*(LocalBuf + i) == '\r')) { + break; + } + } + } + + return numbytes; +#else + (void)fd; + (void)buf; + (void)nbytes; + return 0; +#endif +} +#endif
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/sbrk.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/sbrk.c new file mode 100644 index 0000000..87a753d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/sbrk.c
@@ -0,0 +1,61 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include <errno.h> +#include "xil_types.h" +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) char8 *sbrk (s32 nbytes); +} +#endif + +extern u8 _heap_start[]; +extern u8 _heap_end[]; +extern char8 HeapBase[]; +extern char8 HeapLimit[]; + + + +__attribute__((weak)) char8 *sbrk (s32 nbytes) +{ + char8 *base; + static char8 *heap_ptr = HeapBase; + + base = heap_ptr; + if((heap_ptr != NULL) && (heap_ptr + nbytes <= (char8 *)&HeapLimit + 1)) { + heap_ptr += nbytes; + return base; + } else { + errno = ENOMEM; + return ((char8 *)-1); + } +}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/sleep.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/sleep.c new file mode 100644 index 0000000..c3c65dc --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/sleep.c
@@ -0,0 +1,138 @@ +/****************************************************************************** +* +* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/***************************************************************************** +* +* @file sleep.c +* +* This function provides a second delay using the Global Timer register in +* the ARM Cortex A53 MP core. +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- -------- -------- ----------------------------------------------- +* 5.00 pkp 05/29/14 First release +* 5.04 pkp 28/01/16 Modified the sleep API to configure Time Stamp +* generator only when disable using frequency from +* xparamters.h instead of hardcoding +* 5.05 pkp 13/04/16 Modified sleep routine to call XTime_StartTimer +* which enables timer only when it is disabled and +* read counter value directly from register instead +* of calling XTime_GetTime for optimization +* 6.0 asa 08/15/16 Updated the sleep/usleep signature. Fix for CR#956899. +* 6.6 srm 10/18/17 Updated sleep routines to support user configurable +* implementation. Now sleep routines will use Timer +* specified by the user (i.e. Global timer/TTC timer) +* srm 01/11/18 Fixed the compilation warning. +* </pre> +* +******************************************************************************/ +/***************************** Include Files *********************************/ + +#include "sleep.h" +#include "xtime_l.h" +#include "xparameters.h" + +#if defined (SLEEP_TIMER_BASEADDR) +#include "xil_sleeptimer.h" +#endif +/**************************** Constant Definitions ************************/ + +#if defined (SLEEP_TIMER_BASEADDR) +#define COUNTS_PER_USECOND (COUNTS_PER_SECOND / 1000000 ) +#else +/* Global Timer is always clocked at half of the CPU frequency */ +#define COUNTS_PER_USECOND (COUNTS_PER_SECOND / 1000000 ) +#endif + +/************************************************************************/ +#if !defined (SLEEP_TIMER_BASEADDR) +static void sleep_common(u32 n, u32 count) +{ + XTime tEnd, tCur; + /* Start global timer counter, it will only be enabled if it is disabled */ + XTime_StartTimer(); + + tCur = mfcp(CNTPCT_EL0); + tEnd = tCur + (((XTime) n) * count); + do { + tCur = mfcp(CNTPCT_EL0); + } while (tCur < tEnd); +} +#endif +/*****************************************************************************/ +/** +* +* This API gives a delay in microseconds +* +* @param useconds requested +* +* @return 0 if the delay can be achieved, -1 if the requested delay +* is out of range +* +* @note None. +* +****************************************************************************/ +int usleep_A53(unsigned long useconds) +{ +#if defined (SLEEP_TIMER_BASEADDR) + Xil_SleepTTCCommon(useconds, COUNTS_PER_USECOND); +#else + sleep_common((u32)useconds, COUNTS_PER_USECOND); +#endif + + return 0; +} + +/*****************************************************************************/ +/* +* +* This API is used to provide delays in seconds +* +* @param seconds requested +* +* @return 0 always +* +* @note None. +* +****************************************************************************/ +unsigned sleep_A53(unsigned int seconds) +{ +#if defined (SLEEP_TIMER_BASEADDR) + Xil_SleepTTCCommon(seconds, COUNTS_PER_SECOND); +#else + sleep_common(seconds, COUNTS_PER_SECOND); +#endif + + return 0; +}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/sleep.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/sleep.h new file mode 100644 index 0000000..f53b2d8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/sleep.h
@@ -0,0 +1,119 @@ +/****************************************************************************** +* +* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/*****************************************************************************/ +/** +* @file sleep.h +* +* This header file contains ARM Cortex A53,A9,R5,Microblaze specific sleep +* related APIs. +* +* <pre> +* MODIFICATION HISTORY : +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 6.6 srm 11/02/17 Added processor specific sleep rountines +* function prototypes. +* +* </pre> +* +******************************************************************************/ + +#ifndef SLEEP_H +#define SLEEP_H + +#include "xil_types.h" +#include "xil_io.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/*****************************************************************************/ +/** +* +* This macro polls an address periodically until a condition is met or till the +* timeout occurs. +* The minimum timeout for calling this macro is 100us. If the timeout is less +* than 100us, it still waits for 100us. Also the unit for the timeout is 100us. +* If the timeout is not a multiple of 100us, it waits for a timeout of +* the next usec value which is a multiple of 100us. +* +* @param IO_func - accessor function to read the register contents. +* Depends on the register width. +* @param ADDR - Address to be polled +* @param VALUE - variable to read the value +* @param COND - Condition to checked (usually involves VALUE) +* @param TIMEOUT_US - timeout in micro seconds +* +* @return 0 - when the condition is met +* -1 - when the condition is not met till the timeout period +* +* @note none +* +*****************************************************************************/ +#define Xil_poll_timeout(IO_func, ADDR, VALUE, COND, TIMEOUT_US) \ + ( { \ + u64 timeout = TIMEOUT_US/100; \ + if(TIMEOUT_US%100!=0) \ + timeout++; \ + for(;;) { \ + VALUE = IO_func(ADDR); \ + if(COND) \ + break; \ + else { \ + usleep(100); \ + timeout--; \ + if(timeout==0) \ + break; \ + } \ + } \ + (timeout>0) ? 0 : -1; \ + } ) + +void usleep(unsigned long useconds); +void sleep(unsigned int seconds); +int usleep_R5(unsigned long useconds); +unsigned sleep_R5(unsigned int seconds); +int usleep_MB(unsigned long useconds); +unsigned sleep_MB(unsigned int seconds); +int usleep_A53(unsigned long useconds); +unsigned sleep_A53(unsigned int seconds); +int usleep_A9(unsigned long useconds); +unsigned sleep_A9(unsigned int seconds); + +#ifdef __cplusplus +} +#endif + +#endif
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/translation_table.S b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/translation_table.S new file mode 100644 index 0000000..b72abe0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/translation_table.S
@@ -0,0 +1,273 @@ +/****************************************************************************** +* +* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file translation_table.s +* +* @addtogroup a53_64_boot_code +* @{ +* <h2> translation_table.S </h2> +* translation_table.S contains a static page table required by MMU for +* cortex-A53. This translation table is flat mapped (input address = output +* address) with default memory attributes defined for zynq ultrascale+ +* architecture. It utilizes translation granual size of 4KB with 2MB section +* size for initial 4GB memory and 1GB section size for memory after 4GB. +* The overview of translation table memory attributes is described below. +* +*| | Memory Range | Definition in Translation Table | +*|-----------------------|-----------------------------|-----------------------------------| +*| DDR | 0x0000000000 - 0x007FFFFFFF | Normal write-back Cacheable | +*| PL | 0x0080000000 - 0x00BFFFFFFF | Strongly Ordered | +*| QSPI, lower PCIe | 0x00C0000000 - 0x00EFFFFFFF | Strongly Ordere | +*| Reserved | 0x00F0000000 - 0x00F7FFFFFF | Unassigned | +*| STM Coresight | 0x00F8000000 - 0x00F8FFFFFF | Strongly Ordered | +*| GIC | 0x00F9000000 - 0x00F91FFFFF | Strongly Ordered | +*| Reserved | 0x00F9200000 - 0x00FCFFFFFF | Unassigned | +*| FPS, LPS slaves | 0x00FD000000 - 0x00FFBFFFFF | Strongly Ordered | +*| CSU, PMU | 0x00FFC00000 - 0x00FFDFFFFF | Strongly Ordered | +*| TCM, OCM | 0x00FFE00000 - 0x00FFFFFFFF | Normal inner write-back cacheable | +*| Reserved | 0x0100000000 - 0x03FFFFFFFF | Unassigned | +*| PL, PCIe | 0x0400000000 - 0x07FFFFFFFF | Strongly Ordered | +*| DDR | 0x0800000000 - 0x0FFFFFFFFF | Normal inner write-back cacheable | +*| PL, PCIe | 0x1000000000 - 0xBFFFFFFFFF | Strongly Ordered | +*| Reserved | 0xC000000000 - 0xFFFFFFFFFF | Unassigned | +* +* @note +* +* For DDR region 0x0000000000 - 0x007FFFFFFF, a system where DDR is less than +* 2GB, region after DDR and before PL is marked as undefined/reserved in +* translation table. Region 0xF9100000 - 0xF91FFFFF is reserved memory in +* 0x00F9000000 - 0x00F91FFFFF range, but it is marked as strongly ordered +* because minimum section size in translation table section is 2MB. Region +* 0x00FFC00000 - 0x00FFDFFFFF contains CSU and PMU memory which are marked as +* Device since it is less than 1MB and falls in a region with device memory. +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- --------------------------------------------------- +* 5.00 pkp 05/21/14 Initial version +* 5.04 pkp 12/18/15 Updated the address map according to proper address map +* 6.0 mus 07/20/16 Added warning for ddrless HW design CR-954977 +* 6.2 pkp 12/14/16 DDR memory in 0x800000000 - 0xFFFFFFFFF range is marked +* as normal writeback for the size defined in hdf and rest +* of the memory in that 32GB range is marked as reserved. +* 6.4 mus 08/10/17 Marked memory as a outer shareable for EL1 NS execution, +* to support CCI enabled IP's. +* +* +******************************************************************************/ +#include "xparameters.h" +#include "bspconfig.h" + + .globl MMUTableL0 + .globl MMUTableL1 + .globl MMUTableL2 + + .set reserved, 0x0 /* Fault*/ + #if EL1_NONSECURE + .set Memory, 0x405 | (2 << 8) | (0x0) /* normal writeback write allocate outer shared read write */ + #else + .set Memory, 0x405 | (3 << 8) | (0x0) /* normal writeback write allocate inner shared read write */ + #endif + .set Device, 0x409 | (1 << 53)| (1 << 54) |(0x0) /* strongly ordered read write non executable*/ + .section .mmu_tbl0,"a" + +MMUTableL0: + +.set SECT, MMUTableL1 /* 0x0000_0000 - 0x7F_FFFF_FFFF */ +.8byte SECT + 0x3 +.set SECT, MMUTableL1+0x1000 /* 0x80_0000_0000 - 0xFF_FFFF_FFFF */ +.8byte SECT + 0x3 + + .section .mmu_tbl1,"a" + +MMUTableL1: + +.set SECT, MMUTableL2 /* 0x0000_0000 - 0x3FFF_FFFF */ +.8byte SECT + 0x3 /* 1GB DDR */ + +.rept 0x3 /* 0x4000_0000 - 0xFFFF_FFFF */ +.set SECT, SECT + 0x1000 /*1GB DDR, 1GB PL, 2GB other devices n memory */ +.8byte SECT + 0x3 +.endr + +.set SECT,0x100000000 +.rept 0xC /* 0x0001_0000_0000 - 0x0003_FFFF_FFFF */ +.8byte SECT + reserved /* 12GB Reserved */ +.set SECT, SECT + 0x40000000 +.endr + +.rept 0x10 /* 0x0004_0000_0000 - 0x0007_FFFF_FFFF */ +.8byte SECT + Device /* 8GB PL, 8GB PCIe */ +.set SECT, SECT + 0x40000000 +.endr + + +#ifdef XPAR_PSU_DDR_1_S_AXI_BASEADDR +.set DDR_1_START, XPAR_PSU_DDR_1_S_AXI_BASEADDR +.set DDR_1_END, XPAR_PSU_DDR_1_S_AXI_HIGHADDR +.set DDR_1_SIZE, (DDR_1_END - DDR_1_START)+1 +.if DDR_1_SIZE > 0x800000000 +/* If DDR size is larger than 32GB, truncate to 32GB */ +.set DDR_1_REG, 0x20 +.else +.set DDR_1_REG, DDR_1_SIZE/0x40000000 +.endif +#else +.set DDR_1_REG, 0 +#warning "There's no DDR_1 in the HW design. MMU translation table marks 32 GB DDR address space as undefined" +#endif + +.set UNDEF_1_REG, 0x20 - DDR_1_REG + +.rept DDR_1_REG /* DDR based on size in hdf*/ +.8byte SECT + Memory +.set SECT, SECT+0x40000000 +.endr + +.rept UNDEF_1_REG /* reserved for region where ddr is absent */ +.8byte SECT + reserved +.set SECT, SECT+0x40000000 +.endr + +.rept 0x1C0 /* 0x0010_0000_0000 - 0x007F_FFFF_FFFF */ +.8byte SECT + Device /* 448 GB PL */ +.set SECT, SECT + 0x40000000 +.endr + + +.rept 0x100 /* 0x0080_0000_0000 - 0x00BF_FFFF_FFFF */ +.8byte SECT + Device /* 256GB PCIe */ +.set SECT, SECT + 0x40000000 +.endr + + +.rept 0x100 /* 0x00C0_0000_0000 - 0x00FF_FFFF_FFFF */ +.8byte SECT + reserved /* 256GB reserved */ +.set SECT, SECT + 0x40000000 +.endr + + +.section .mmu_tbl2,"a" + +MMUTableL2: + +.set SECT, 0 + +#ifdef XPAR_PSU_DDR_0_S_AXI_BASEADDR +.set DDR_0_START, XPAR_PSU_DDR_0_S_AXI_BASEADDR +.set DDR_0_END, XPAR_PSU_DDR_0_S_AXI_HIGHADDR +.set DDR_0_SIZE, (DDR_0_END - DDR_0_START)+1 +.if DDR_0_SIZE > 0x80000000 +/* If DDR size is larger than 2GB, truncate to 2GB */ +.set DDR_0_REG, 0x400 +.else +.set DDR_0_REG, DDR_0_SIZE/0x200000 +.endif +#else +.set DDR_0_REG, 0 +#warning "There's no DDR_0 in the HW design. MMU translation table marks 2 GB DDR address space as undefined" +#endif + +.set UNDEF_0_REG, 0x400 - DDR_0_REG + +.rept DDR_0_REG /* DDR based on size in hdf*/ +.8byte SECT + Memory +.set SECT, SECT+0x200000 +.endr + +.rept UNDEF_0_REG /* reserved for region where ddr is absent */ +.8byte SECT + reserved +.set SECT, SECT+0x200000 +.endr + +.rept 0x0200 /* 0x8000_0000 - 0xBFFF_FFFF */ +.8byte SECT + Device /* 1GB lower PL */ +.set SECT, SECT+0x200000 +.endr + +.rept 0x0100 /* 0xC000_0000 - 0xDFFF_FFFF */ +.8byte SECT + Device /* 512MB QSPI */ +.set SECT, SECT+0x200000 +.endr + +.rept 0x080 /* 0xE000_0000 - 0xEFFF_FFFF */ +.8byte SECT + Device /* 256MB lower PCIe */ +.set SECT, SECT+0x200000 +.endr + +.rept 0x040 /* 0xF000_0000 - 0xF7FF_FFFF */ +.8byte SECT + reserved /* 128MB Reserved */ +.set SECT, SECT+0x200000 +.endr + +.rept 0x8 /* 0xF800_0000 - 0xF8FF_FFFF */ +.8byte SECT + Device /* 16MB coresight */ +.set SECT, SECT+0x200000 +.endr + +/* 1MB RPU LLP is marked for 2MB region as the minimum block size in + translation table is 2MB and adjacent 63MB reserved region is + converted to 62MB */ + +.rept 0x1 /* 0xF900_0000 - 0xF91F_FFFF */ +.8byte SECT + Device /* 2MB RPU low latency port */ +.set SECT, SECT+0x200000 +.endr + +.rept 0x1F /* 0xF920_0000 - 0xFCFF_FFFF */ +.8byte SECT + reserved /* 62MB Reserved */ +.set SECT, SECT+0x200000 +.endr + +.rept 0x8 /* 0xFD00_0000 - 0xFDFF_FFFF */ +.8byte SECT + Device /* 16MB FPS */ +.set SECT, SECT+0x200000 +.endr + +.rept 0xE /* 0xFE00_0000 - 0xFFBF_FFFF */ +.8byte SECT + Device /* 28MB LPS */ +.set SECT, SECT+0x200000 +.endr + + /* 0xFFC0_0000 - 0xFFDF_FFFF */ +.8byte SECT + Device /*2MB PMU/CSU */ + +.set SECT, SECT+0x200000 /* 0xFFE0_0000 - 0xFFFF_FFFF*/ +.8byte SECT + Memory /*2MB OCM/TCM*/ + +.end +/** +* @} End of "addtogroup a53_64_boot_code". +*/
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/uart.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/uart.c new file mode 100644 index 0000000..ae67006 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/uart.c
@@ -0,0 +1,162 @@ +/****************************************************************************** +* +* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file uart.c +* +* This file contains APIs for configuring the UART. +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- --------------------------------------------------- +* 5.00 pkp 05/29/14 First release +* </pre> +* +* @note +* +* None. +* +******************************************************************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" +#include "xparameters.h" + +/* Register offsets */ +#define UART_CR_OFFSET 0x00000000U +#define UART_MR_OFFSET 0x00000004U +#define UART_BAUDGEN_OFFSET 0x00000018U +#define UART_BAUDDIV_OFFSET 0x00000034U + +#define MAX_BAUD_ERROR_RATE 3U /* max % error allowed */ +#define UART_BAUDRATE 115200U +#define CSU_VERSION_REG 0xFFCA0044U + +void Init_Uart(void); + +void Init_Uart(void) +{ +#ifdef STDOUT_BASEADDRESS + u8 IterBAUDDIV; /* Iterator for available baud divisor values */ + u32 BRGR_Value; /* Calculated value for baud rate generator */ + u32 CalcBaudRate; /* Calculated baud rate */ + u32 BaudError; /* Diff between calculated and requested baud + * rate */ + u32 Best_BRGR = 0U; /* Best value for baud rate generator */ + u8 Best_BAUDDIV = 0U; /* Best value for baud divisor */ + u32 Best_Error = 0xFFFFFFFFU; + u32 PercentError; + u32 InputClk; + u32 BaudRate = UART_BAUDRATE; + + /* set CD and BDIV */ + +#if (STDOUT_BASEADDRESS == XPAR_XUARTPS_0_BASEADDR) + InputClk = XPAR_XUARTPS_0_UART_CLK_FREQ_HZ; +#elif (STDOUT_BASEADDRESS == XPAR_XUARTPS_1_BASEADDR) + InputClk = XPAR_XUARTPS_1_UART_CLK_FREQ_HZ; +#else + /* STDIO is not set or axi_uart is being used for STDIO */ + return; +#endif +InputClk = 25000000U; + /* + * Determine the Baud divider. It can be 4to 254. + * Loop through all possible combinations + */ + for (IterBAUDDIV = 4U; IterBAUDDIV < 255U; IterBAUDDIV++) { + + /* + * Calculate the value for BRGR register + */ + BRGR_Value = InputClk / (BaudRate * ((u32)IterBAUDDIV + 1U)); + + /* + * Calculate the baud rate from the BRGR value + */ + CalcBaudRate = InputClk/ (BRGR_Value * ((u32)IterBAUDDIV + 1U)); + + /* + * Avoid unsigned integer underflow + */ + if (BaudRate > CalcBaudRate) { + BaudError = BaudRate - CalcBaudRate; + } else { + BaudError = CalcBaudRate - BaudRate; + } + + /* + * Find the calculated baud rate closest to requested baud rate. + */ + if (Best_Error > BaudError) { + + Best_BRGR = BRGR_Value; + Best_BAUDDIV = IterBAUDDIV; + Best_Error = BaudError; + } + } + + /* + * Make sure the best error is not too large. + */ + PercentError = (Best_Error * 100U) / BaudRate; + if (((u32)MAX_BAUD_ERROR_RATE) < PercentError) { + return; + } + + /* set CD and BDIV */ + Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDGEN_OFFSET, Best_BRGR); + Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDDIV_OFFSET, (u32)Best_BAUDDIV); + + /* + * Veloce specific code + */ + if((Xil_In32(CSU_VERSION_REG) & 0x0000F000U) == 0x00002000U ) { + Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDGEN_OFFSET, 2U); + Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDDIV_OFFSET, 4U); + } + + /* + * 8 data, 1 stop, 0 parity bits + * sel_clk=uart_clk=APB clock + */ + Xil_Out32(STDOUT_BASEADDRESS + UART_MR_OFFSET, 0x00000020U); + + /* enable Tx/Rx and reset Tx/Rx data path */ + Xil_Out32((STDOUT_BASEADDRESS + UART_CR_OFFSET), 0x00000017U); + + return; +#endif +}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/unlink.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/unlink.c new file mode 100644 index 0000000..d0cc680 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/unlink.c
@@ -0,0 +1,50 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include <errno.h> +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) sint32 unlink(char8 *path); +} +#endif +/* + * unlink -- since we have no file system, + * we just return an error. + */ +__attribute__((weak)) sint32 unlink(char8 *path) +{ + (void) path; + errno = EIO; + return (-1); +}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/vectors.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/vectors.c new file mode 100644 index 0000000..0a36163 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/vectors.c
@@ -0,0 +1,231 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file vectors.c +* +* This file contains the C level vectors for the ARM Cortex A9 core. +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- --------------------------------------------------- +* 1.00a ecm 10/20/09 Initial version, moved over from bsp area +* 6.0 mus 27/07/16 Consolidated vectors for a53,a9 and r5 processor +* and added UndefinedException for a53 32 bit and r5 +* processor +* </pre> +* +* @note +* +* None. +* +******************************************************************************/ +/***************************** Include Files *********************************/ + +#include "xil_exception.h" +#include "vectors.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +typedef struct { + Xil_ExceptionHandler Handler; + void *Data; +} XExc_VectorTableEntry; + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Variable Definitions *****************************/ + +extern XExc_VectorTableEntry XExc_VectorTable[]; + +/************************** Function Prototypes ******************************/ + + +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the FIQ interrupt called from the vectors.s +* file. +* +* @param None. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void FIQInterrupt(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_FIQ_INT].Handler(XExc_VectorTable[ + XIL_EXCEPTION_ID_FIQ_INT].Data); +} + +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the IRQ interrupt called from the vectors.s +* file. +* +* @param None. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void IRQInterrupt(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_IRQ_INT].Handler(XExc_VectorTable[ + XIL_EXCEPTION_ID_IRQ_INT].Data); +} + +#if !defined (__aarch64__) +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the Undefined exception called from the +* vectors.s file. +* +* @param None. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void UndefinedException(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_UNDEFINED_INT].Handler(XExc_VectorTable[ + XIL_EXCEPTION_ID_UNDEFINED_INT].Data); +} + +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the SW Interrupt called from the vectors.s +* file. +* +* @param None. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void SWInterrupt(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_SWI_INT].Handler(XExc_VectorTable[ + XIL_EXCEPTION_ID_SWI_INT].Data); +} + +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the DataAbort Interrupt called from the +* vectors.s file. +* +* @param None. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void DataAbortInterrupt(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Handler( + XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Data); +} + +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the PrefetchAbort Interrupt called from the +* vectors.s file. +* +* @param None. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void PrefetchAbortInterrupt(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Handler( + XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Data); +} +#else + +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the Synchronous Interrupt called from the vectors.s +* file. +* +* @param None. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void SynchronousInterrupt(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_SYNC_INT].Handler(XExc_VectorTable[ + XIL_EXCEPTION_ID_SYNC_INT].Data); +} + +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the SError Interrupt called from the +* vectors.s file. +* +* @param None. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void SErrorInterrupt(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Handler( + XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Data); +} + +#endif
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/vectors.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/vectors.h new file mode 100644 index 0000000..bb599b5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/vectors.h
@@ -0,0 +1,88 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file vectors.h +* +* This file contains the C level vector prototypes for the ARM Cortex A9 core. +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- --------------------------------------------------- +* 1.00a ecm 10/20/10 Initial version, moved over from bsp area +* 6.0 mus 07/27/16 Consolidated vectors for a9,a53 and r5 processors +* </pre> +* +* @note +* +* None. +* +******************************************************************************/ + +#ifndef _VECTORS_H_ +#define _VECTORS_H_ + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +void FIQInterrupt(void); +void IRQInterrupt(void); +#if !defined (__aarch64__) +void SWInterrupt(void); +void DataAbortInterrupt(void); +void PrefetchAbortInterrupt(void); +void UndefinedException(void); +#else +void SynchronousInterrupt(void); +void SErrorInterrupt(void); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/write.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/write.c new file mode 100644 index 0000000..9389f61 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/write.c
@@ -0,0 +1,121 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/* write.c -- write bytes to an output device. + */ +#ifndef UNDEFINE_FILE_OPS +#include "xil_printf.h" +#include "xparameters.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) sint32 _write (sint32 fd, char8* buf, sint32 nbytes); +} +#endif + +/* + * write -- write bytes to the serial port. Ignore fd, since + * stdout and stderr are the same. Since we have no filesystem, + * open will only return an error. + */ +__attribute__((weak)) sint32 +write (sint32 fd, char8* buf, sint32 nbytes) + +{ +#ifdef STDOUT_BASEADDRESS + s32 i; + char8* LocalBuf = buf; + + (void)fd; + for (i = 0; i < nbytes; i++) { + if(LocalBuf != NULL) { + LocalBuf += i; + } + if(LocalBuf != NULL) { + if (*LocalBuf == '\n') { + outbyte ('\r'); + } + outbyte (*LocalBuf); + } + if(LocalBuf != NULL) { + LocalBuf -= i; + } + } + return (nbytes); +#else + (void)fd; + (void)buf; + (void)nbytes; + return 0; +#endif +} + +__attribute__((weak)) sint32 +_write (sint32 fd, char8* buf, sint32 nbytes) +{ +#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE + sint32 length; + + (void)fd; + (void)nbytes; + length = XPVXenConsole_Write(buf); + return length; +#else +#ifdef STDOUT_BASEADDRESS + s32 i; + char8* LocalBuf = buf; + + (void)fd; + for (i = 0; i < nbytes; i++) { + if(LocalBuf != NULL) { + LocalBuf += i; + } + if(LocalBuf != NULL) { + if (*LocalBuf == '\n') { + outbyte ('\r'); + } + outbyte (*LocalBuf); + } + if(LocalBuf != NULL) { + LocalBuf -= i; + } + } + return (nbytes); +#else + (void)fd; + (void)buf; + (void)nbytes; + return 0; +#endif +#endif +} +#endif
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xbasic_types.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xbasic_types.h new file mode 100644 index 0000000..787212c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xbasic_types.h
@@ -0,0 +1,119 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xbasic_types.h +* +* +* @note Dummy File for backwards compatibility +* + +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 1.00a adk 1/31/14 Added in bsp common folder for backward compatibility +* </pre> +* +******************************************************************************/ + +#ifndef XBASIC_TYPES_H /* prevent circular inclusions */ +#define XBASIC_TYPES_H /* by using protection macros */ + +/** @name Legacy types + * Deprecated legacy types. + * @{ + */ +typedef unsigned char Xuint8; /**< unsigned 8-bit */ +typedef char Xint8; /**< signed 8-bit */ +typedef unsigned short Xuint16; /**< unsigned 16-bit */ +typedef short Xint16; /**< signed 16-bit */ +typedef unsigned long Xuint32; /**< unsigned 32-bit */ +typedef long Xint32; /**< signed 32-bit */ +typedef float Xfloat32; /**< 32-bit floating point */ +typedef double Xfloat64; /**< 64-bit double precision FP */ +typedef unsigned long Xboolean; /**< boolean (XTRUE or XFALSE) */ + +#if !defined __XUINT64__ +typedef struct +{ + Xuint32 Upper; + Xuint32 Lower; +} Xuint64; +#endif + +/** @name New types + * New simple types. + * @{ + */ +#ifndef __KERNEL__ +#ifndef XIL_TYPES_H +typedef Xuint32 u32; +typedef Xuint16 u16; +typedef Xuint8 u8; +#endif +#else +#include <linux/types.h> +#endif + +#ifndef TRUE +# define TRUE 1U +#endif + +#ifndef FALSE +# define FALSE 0U +#endif + +#ifndef NULL +#define NULL 0U +#endif + +/* + * Xilinx NULL, TRUE and FALSE legacy support. Deprecated. + * Please use NULL, TRUE and FALSE + */ +#define XNULL NULL +#define XTRUE TRUE +#define XFALSE FALSE + +/* + * This file is deprecated and users + * should use xil_types.h and xil_assert.h\n\r + */ +#warning The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert. +#warning Please refer the Standalone BSP UG647 for further details + + +#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xdebug.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xdebug.h new file mode 100644 index 0000000..650946b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xdebug.h
@@ -0,0 +1,32 @@ +#ifndef XDEBUG /* prevent circular inclusions */ +#define XDEBUG /* by using protection macros */ + +#if defined(DEBUG) && !defined(NDEBUG) + +#ifndef XDEBUG_WARNING +#define XDEBUG_WARNING +#warning DEBUG is enabled +#endif + +int printf(const char *format, ...); + +#define XDBG_DEBUG_ERROR 0x00000001U /* error condition messages */ +#define XDBG_DEBUG_GENERAL 0x00000002U /* general debug messages */ +#define XDBG_DEBUG_ALL 0xFFFFFFFFU /* all debugging data */ + +#define xdbg_current_types (XDBG_DEBUG_GENERAL) + +#define xdbg_stmnt(x) x + +#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0) + + +#else /* defined(DEBUG) && !defined(NDEBUG) */ + +#define xdbg_stmnt(x) + +#define xdbg_printf(...) + +#endif /* defined(DEBUG) && !defined(NDEBUG) */ + +#endif /* XDEBUG */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xenv.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xenv.h new file mode 100644 index 0000000..3d97beb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xenv.h
@@ -0,0 +1,187 @@ +/****************************************************************************** +* +* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xenv.h +* +* Defines common services that are typically found in a host operating. +* environment. This include file simply includes an OS specific file based +* on the compile-time constant BUILD_ENV_*, where * is the name of the target +* environment. +* +* All services are defined as macros. +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ----------------------------------------------- +* 1.00b ch 10/24/02 Added XENV_LINUX +* 1.00a rmm 04/17/02 First release +* </pre> +* +******************************************************************************/ + +#ifndef XENV_H /* prevent circular inclusions */ +#define XENV_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Select which target environment we are operating under + */ + +/* VxWorks target environment */ +#if defined XENV_VXWORKS +#include "xenv_vxworks.h" + +/* Linux target environment */ +#elif defined XENV_LINUX +#include "xenv_linux.h" + +/* Unit test environment */ +#elif defined XENV_UNITTEST +#include "ut_xenv.h" + +/* Integration test environment */ +#elif defined XENV_INTTEST +#include "int_xenv.h" + +/* Standalone environment selected */ +#else +#include "xenv_standalone.h" +#endif + + +/* + * The following comments specify the types and macro wrappers that are + * expected to be defined by the target specific header files + */ + +/**************************** Type Definitions *******************************/ + +/*****************************************************************************/ +/** + * + * XENV_TIME_STAMP + * + * A structure that contains a time stamp used by other time stamp macros + * defined below. This structure is processor dependent. + */ + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/*****************************************************************************/ +/** + * + * XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes) + * + * Copies a non-overlapping block of memory. + * + * @param DestPtr is the destination address to copy data to. + * @param SrcPtr is the source address to copy data from. + * @param Bytes is the number of bytes to copy. + * + * @return None + */ + +/*****************************************************************************/ +/** + * + * XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes) + * + * Fills an area of memory with constant data. + * + * @param DestPtr is the destination address to set. + * @param Data contains the value to set. + * @param Bytes is the number of bytes to set. + * + * @return None + */ +/*****************************************************************************/ +/** + * + * XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr) + * + * Samples the processor's or external timer's time base counter. + * + * @param StampPtr is the storage for the retrieved time stamp. + * + * @return None + */ + +/*****************************************************************************/ +/** + * + * XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr) + * + * Computes the delta between the two time stamps. + * + * @param Stamp1Ptr - First sampled time stamp. + * @param Stamp1Ptr - Sedond sampled time stamp. + * + * @return An unsigned int value with units of microseconds. + */ + +/*****************************************************************************/ +/** + * + * XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr) + * + * Computes the delta between the two time stamps. + * + * @param Stamp1Ptr - First sampled time stamp. + * @param Stamp1Ptr - Sedond sampled time stamp. + * + * @return An unsigned int value with units of milliseconds. + */ + +/*****************************************************************************//** + * + * XENV_USLEEP(unsigned delay) + * + * Delay the specified number of microseconds. + * + * @param delay is the number of microseconds to delay. + * + * @return None + */ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xenv_standalone.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xenv_standalone.h new file mode 100644 index 0000000..f186018 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xenv_standalone.h
@@ -0,0 +1,368 @@ +/****************************************************************************** +* +* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xenv_standalone.h +* +* Defines common services specified by xenv.h. +* +* @note +* This file is not intended to be included directly by driver code. +* Instead, the generic xenv.h file is intended to be included by driver +* code. +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ----------------------------------------------- +* 1.00a wgr 02/28/07 Added cache handling macros. +* 1.00a wgr 02/27/07 Simplified code. Deprecated old-style macro names. +* 1.00a rmm 01/24/06 Implemented XENV_USLEEP. Assume implementation is being +* used under Xilinx standalone BSP. +* 1.00a xd 11/03/04 Improved support for doxygen. +* 1.00a rmm 03/21/02 First release +* 1.00a wgr 03/22/07 Converted to new coding style. +* 1.00a rpm 06/29/07 Added udelay macro for standalone +* 1.00a xd 07/19/07 Included xparameters.h as XPAR_ constants are referred +* to in MICROBLAZE section +* 1.00a ecm 09/19/08 updated for v7.20 of Microblaze, new functionality +* +* </pre> +* +* +******************************************************************************/ + +#ifndef XENV_STANDALONE_H +#define XENV_STANDALONE_H + +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +/****************************************************************************** + * + * Get the processor dependent includes + * + ******************************************************************************/ + +#include <string.h> + +#if defined __MICROBLAZE__ +# include "mb_interface.h" +# include "xparameters.h" /* XPAR constants used below in MB section */ + +#elif defined __PPC__ +# include "sleep.h" +# include "xcache_l.h" /* also include xcache_l.h for caching macros */ +#endif + +/****************************************************************************** + * + * MEMCPY / MEMSET related macros. + * + * The following are straight forward implementations of memset and memcpy. + * + * NOTE: memcpy may not work if source and target memory area are overlapping. + * + ******************************************************************************/ +/*****************************************************************************/ +/** + * + * Copies a non-overlapping block of memory. + * + * @param DestPtr + * Destination address to copy data to. + * + * @param SrcPtr + * Source address to copy data from. + * + * @param Bytes + * Number of bytes to copy. + * + * @return None. + * + * @note + * The use of XENV_MEM_COPY is deprecated. Use memcpy() instead. + * + * @note + * This implemention MAY BREAK work if source and target memory + * area are overlapping. + * + *****************************************************************************/ + +#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \ + memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes) + + + +/*****************************************************************************/ +/** + * + * Fills an area of memory with constant data. + * + * @param DestPtr + * Destination address to copy data to. + * + * @param Data + * Value to set. + * + * @param Bytes + * Number of bytes to copy. + * + * @return None. + * + * @note + * The use of XENV_MEM_FILL is deprecated. Use memset() instead. + * + *****************************************************************************/ + +#define XENV_MEM_FILL(DestPtr, Data, Bytes) \ + memset((void *) DestPtr, (s32) Data, (size_t) Bytes) + + + +/****************************************************************************** + * + * TIME related macros + * + ******************************************************************************/ + +/** + * A structure that contains a time stamp used by other time stamp macros + * defined below. This structure is processor dependent. + */ +typedef s32 XENV_TIME_STAMP; + +/*****************************************************************************/ +/** + * + * Time is derived from the 64 bit PPC timebase register + * + * @param StampPtr is the storage for the retrieved time stamp. + * + * @return None. + * + * @note + * + * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr) + * <br><br> + * This macro must be implemented by the user. + * + *****************************************************************************/ +#define XENV_TIME_STAMP_GET(StampPtr) + +/*****************************************************************************/ +/** + * + * This macro is not yet implemented and always returns 0. + * + * @param Stamp1Ptr is the first sampled time stamp. + * @param Stamp2Ptr is the second sampled time stamp. + * + * @return 0 + * + * @note + * + * This macro must be implemented by the user. + * + *****************************************************************************/ +#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0) + +/*****************************************************************************/ +/** + * + * This macro is not yet implemented and always returns 0. + * + * @param Stamp1Ptr is the first sampled time stamp. + * @param Stamp2Ptr is the second sampled time stamp. + * + * @return 0 + * + * @note + * + * This macro must be implemented by the user. + * + *****************************************************************************/ +#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0) + +/*****************************************************************************/ +/** + * XENV_USLEEP(unsigned delay) + * + * Delay the specified number of microseconds. Not implemented without OS + * support. + * + * @param delay + * Number of microseconds to delay. + * + * @return None. + * + *****************************************************************************/ + +#ifdef __PPC__ +#define XENV_USLEEP(delay) usleep(delay) +#define udelay(delay) usleep(delay) +#else +#define XENV_USLEEP(delay) +#define udelay(delay) +#endif + + +/****************************************************************************** + * + * CACHE handling macros / mappings + * + ******************************************************************************/ +/****************************************************************************** + * + * Processor independent macros + * + ******************************************************************************/ + +#define XCACHE_ENABLE_CACHE() \ + { XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); } + +#define XCACHE_DISABLE_CACHE() \ + { XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); } + + +/****************************************************************************** + * + * MicroBlaze case + * + * NOTE: Currently the following macros will only work on systems that contain + * only ONE MicroBlaze processor. Also, the macros will only be enabled if the + * system is built using a xparameters.h file. + * + ******************************************************************************/ + +#if defined __MICROBLAZE__ + +/* Check if MicroBlaze data cache was built into the core. + */ +#if (XPAR_MICROBLAZE_USE_DCACHE == 1) +# define XCACHE_ENABLE_DCACHE() microblaze_enable_dcache() +# define XCACHE_DISABLE_DCACHE() microblaze_disable_dcache() +# define XCACHE_INVALIDATE_DCACHE() microblaze_invalidate_dcache() + +# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \ + microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len)) + +#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1) +# define XCACHE_FLUSH_DCACHE() microblaze_flush_dcache() +# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \ + microblaze_flush_dcache_range((s32)(Addr), (s32)(Len)) +#else +# define XCACHE_FLUSH_DCACHE() microblaze_invalidate_dcache() +# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \ + microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len)) +#endif /*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/ + +#else +# define XCACHE_ENABLE_DCACHE() +# define XCACHE_DISABLE_DCACHE() +# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) +# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) +#endif /*XPAR_MICROBLAZE_USE_DCACHE*/ + + +/* Check if MicroBlaze instruction cache was built into the core. + */ +#if (XPAR_MICROBLAZE_USE_ICACHE == 1) +# define XCACHE_ENABLE_ICACHE() microblaze_enable_icache() +# define XCACHE_DISABLE_ICACHE() microblaze_disable_icache() + +# define XCACHE_INVALIDATE_ICACHE() microblaze_invalidate_icache() + +# define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \ + microblaze_invalidate_icache_range((s32)(Addr), (s32)(Len)) + +#else +# define XCACHE_ENABLE_ICACHE() +# define XCACHE_DISABLE_ICACHE() +#endif /*XPAR_MICROBLAZE_USE_ICACHE*/ + + +/****************************************************************************** + * + * PowerPC case + * + * Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a + * specific memory region (0x80000001). Each bit (0-30) in the regions + * bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB + * range. + * + * regions --> cached address range + * ------------|-------------------------------------------------- + * 0x80000000 | [0, 0x7FFFFFF] + * 0x00000001 | [0xF8000000, 0xFFFFFFFF] + * 0x80000001 | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF] + * + ******************************************************************************/ + +#elif defined __PPC__ + +#define XCACHE_ENABLE_DCACHE() XCache_EnableDCache(0x80000001) +#define XCACHE_DISABLE_DCACHE() XCache_DisableDCache() +#define XCACHE_ENABLE_ICACHE() XCache_EnableICache(0x80000001) +#define XCACHE_DISABLE_ICACHE() XCache_DisableICache() + +#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \ + XCache_InvalidateDCacheRange((u32)(Addr), (u32)(Len)) + +#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \ + XCache_FlushDCacheRange((u32)(Addr), (u32)(Len)) + +#define XCACHE_INVALIDATE_ICACHE() XCache_InvalidateICache() + + +/****************************************************************************** + * + * Unknown processor / architecture + * + ******************************************************************************/ + +#else +/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */ +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef XENV_STANDALONE_H */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil-crt0.S b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil-crt0.S new file mode 100644 index 0000000..7ac77b6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil-crt0.S
@@ -0,0 +1,144 @@ +/****************************************************************************** +* +* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xil-crt0.S +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- --------------------------------------------------- +* 5.00 pkp 05/21/14 Initial version +* 5.04 pkp 12/18/15 Initialized global constructor for C++ applications +* 5.04 pkp 01/05/16 Set the reset vector register RVBAR equivalent to +* vector table base address +* 6.02 pkp 01/22/17 Added support for EL1 non-secure +* 6.6 srm 10/18/17 Added timer configuration using XTime_StartTTCTimer API. +* Now the TTC instance as specified by the user will be +* started. +* 6.6 mus 01/29/18 Initialized the xen PV console for Cortexa53 64 bit +* EL1 NS BSP. +* </pre> +* +* @note +* +* None. +* +******************************************************************************/ +#include "xparameters.h" +#include "bspconfig.h" + .file "xil-crt0.S" + .section ".got2","aw" + .align 2 + + .text +.Lsbss_start: + .quad __sbss_start + +.Lsbss_end: + .quad __sbss_end + +.Lbss_start: + .quad __bss_start__ + +.Lbss_end: + .quad __bss_end__ + + +.set APU_PWRCTL, 0xFD5C0090 + + .globl _startup +_startup: + + mov x0, #0 +.if (EL3 == 1) + /* Check whether the clearing of bss sections shall be skipped */ + ldr x10, =APU_PWRCTL /* Load PWRCTRL address */ + ldr w11, [x10] /* Read PWRCTRL register */ + mrs x2, MPIDR_EL1 /* Read MPIDR_EL1 */ + ubfx x2, x2, #0, #8 /* Extract CPU ID (affinity level 0) */ + mov w1, #1 + lsl w2, w1, w2 /* Shift CPU ID to get one-hot ID */ + ands w11, w11, w2 /* Get PWRCTRL bit for this core */ + bne .Lenclbss /* Skip BSS and SBSS clearing */ +.endif + /* clear sbss */ + ldr x1,.Lsbss_start /* calculate beginning of the SBSS */ + ldr x2,.Lsbss_end /* calculate end of the SBSS */ + +.Lloop_sbss: + cmp x1,x2 + bge .Lenclsbss /* If no SBSS, no clearing required */ + str x0, [x1], #8 + b .Lloop_sbss + +.Lenclsbss: + /* clear bss */ + ldr x1,.Lbss_start /* calculate beginning of the BSS */ + ldr x2,.Lbss_end /* calculate end of the BSS */ + +.Lloop_bss: + cmp x1,x2 + bge .Lenclbss /* If no BSS, no clearing required */ + str x0, [x1], #8 + b .Lloop_bss + +.Lenclbss: + /* run global constructors */ + bl __libc_init_array + + /* Reset and start Triple Timer Counter */ + #if defined (SLEEP_TIMER_BASEADDR) + bl XTime_StartTTCTimer + #endif + + .if (EL1_NONSECURE == 1 && HYP_GUEST == 1 && \ + XEN_USE_PV_CONSOLE == 1) + bl XPVXenConsole_Init + .endif + /* make sure argc and argv are valid */ + mov x0, #0 + mov x1, #0 + + bl main /* Jump to main C code */ + + /* Cleanup global constructors */ + bl __libc_fini_array + + bl exit + +.Lexit: /* should never get here */ + b .Lexit + +.Lstart: + .size _startup,.Lstart-_startup
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_assert.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_assert.c new file mode 100644 index 0000000..59b3c1c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_assert.c
@@ -0,0 +1,147 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_assert.c +* +* This file contains basic assert related functions for Xilinx software IP. +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 1.00a hbm 07/14/09 Initial release +* 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable +* </pre> +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Variable Definitions *****************************/ + +/** + * This variable allows testing to be done easier with asserts. An assert + * sets this variable such that a driver can evaluate this variable + * to determine if an assert occurred. + */ +u32 Xil_AssertStatus; + +/** + * This variable allows the assert functionality to be changed for testing + * such that it does not wait infinitely. Use the debugger to disable the + * waiting during testing of asserts. + */ +s32 Xil_AssertWait = 1; + +/* The callback function to be invoked when an assert is taken */ +static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL; + +/************************** Function Prototypes ******************************/ + +/*****************************************************************************/ +/** +* +* @brief Implement assert. Currently, it calls a user-defined callback +* function if one has been set. Then, it potentially enters an +* infinite loop depending on the value of the Xil_AssertWait +* variable. +* +* @param file: filename of the source +* @param line: linenumber within File +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void Xil_Assert(const char8 *File, s32 Line) +{ + /* if the callback has been set then invoke it */ + if (Xil_AssertCallbackRoutine != 0) { + (*Xil_AssertCallbackRoutine)(File, Line); + } + + /* if specified, wait indefinitely such that the assert will show up + * in testing + */ + while (Xil_AssertWait != 0) { + } +} + +/*****************************************************************************/ +/** +* +* @brief Set up a callback function to be invoked when an assert occurs. +* If a callback is already installed, then it will be replaced. +* +* @param routine: callback to be invoked when an assert is taken +* +* @return None. +* +* @note This function has no effect if NDEBUG is set +* +******************************************************************************/ +void Xil_AssertSetCallback(Xil_AssertCallback Routine) +{ + Xil_AssertCallbackRoutine = Routine; +} + +/*****************************************************************************/ +/** +* +* @brief Null handler function. This follows the XInterruptHandler +* signature for interrupt handlers. It can be used to assign a null +* handler (a stub) to an interrupt controller vector table. +* +* @param NullParameter: arbitrary void pointer and not used. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XNullHandler(void *NullParameter) +{ + (void) NullParameter; +}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_assert.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_assert.h new file mode 100644 index 0000000..add4124 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_assert.h
@@ -0,0 +1,195 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_assert.h +* +* @addtogroup common_assert_apis Assert APIs and Macros +* +* The xil_assert.h file contains assert related functions and macros. +* Assert APIs/Macros specifies that a application program satisfies certain +* conditions at particular points in its execution. These function can be +* used by application programs to ensure that, application code is satisfying +* certain conditions. +* +* @{ +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 1.00a hbm 07/14/09 First release +* 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable +* </pre> +* +******************************************************************************/ + +#ifndef XIL_ASSERT_H /* prevent circular inclusions */ +#define XIL_ASSERT_H /* by using protection macros */ + +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/***************************** Include Files *********************************/ + + +/************************** Constant Definitions *****************************/ + +#define XIL_ASSERT_NONE 0U +#define XIL_ASSERT_OCCURRED 1U +#define XNULL NULL + +extern u32 Xil_AssertStatus; +extern s32 Xil_AssertWait; +extern void Xil_Assert(const char8 *File, s32 Line); +void XNullHandler(void *NullParameter); + +/** + * This data type defines a callback to be invoked when an + * assert occurs. The callback is invoked only when asserts are enabled + */ +typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line); + +/***************** Macros (Inline Functions) Definitions *********************/ + +#ifndef NDEBUG + +/*****************************************************************************/ +/** +* @brief This assert macro is to be used for void functions. This in +* conjunction with the Xil_AssertWait boolean can be used to +* accomodate tests so that asserts which fail allow execution to +* continue. +* +* @param Expression: expression to be evaluated. If it evaluates to +* false, the assert occurs. +* +* @return Returns void unless the Xil_AssertWait variable is true, in which +* case no return is made and an infinite loop is entered. +* +******************************************************************************/ +#define Xil_AssertVoid(Expression) \ +{ \ + if (Expression) { \ + Xil_AssertStatus = XIL_ASSERT_NONE; \ + } else { \ + Xil_Assert(__FILE__, __LINE__); \ + Xil_AssertStatus = XIL_ASSERT_OCCURRED; \ + return; \ + } \ +} + +/*****************************************************************************/ +/** +* @brief This assert macro is to be used for functions that do return a +* value. This in conjunction with the Xil_AssertWait boolean can be +* used to accomodate tests so that asserts which fail allow execution +* to continue. +* +* @param Expression: expression to be evaluated. If it evaluates to false, +* the assert occurs. +* +* @return Returns 0 unless the Xil_AssertWait variable is true, in which +* case no return is made and an infinite loop is entered. +* +******************************************************************************/ +#define Xil_AssertNonvoid(Expression) \ +{ \ + if (Expression) { \ + Xil_AssertStatus = XIL_ASSERT_NONE; \ + } else { \ + Xil_Assert(__FILE__, __LINE__); \ + Xil_AssertStatus = XIL_ASSERT_OCCURRED; \ + return 0; \ + } \ +} + +/*****************************************************************************/ +/** +* @brief Always assert. This assert macro is to be used for void functions. +* Use for instances where an assert should always occur. +* +* @return Returns void unless the Xil_AssertWait variable is true, in which +* case no return is made and an infinite loop is entered. +* +******************************************************************************/ +#define Xil_AssertVoidAlways() \ +{ \ + Xil_Assert(__FILE__, __LINE__); \ + Xil_AssertStatus = XIL_ASSERT_OCCURRED; \ + return; \ +} + +/*****************************************************************************/ +/** +* @brief Always assert. This assert macro is to be used for functions that +* do return a value. Use for instances where an assert should always +* occur. +* +* @return Returns void unless the Xil_AssertWait variable is true, in which +* case no return is made and an infinite loop is entered. +* +******************************************************************************/ +#define Xil_AssertNonvoidAlways() \ +{ \ + Xil_Assert(__FILE__, __LINE__); \ + Xil_AssertStatus = XIL_ASSERT_OCCURRED; \ + return 0; \ +} + + +#else + +#define Xil_AssertVoid(Expression) +#define Xil_AssertVoidAlways() +#define Xil_AssertNonvoid(Expression) +#define Xil_AssertNonvoidAlways() + +#endif + +/************************** Function Prototypes ******************************/ + +void Xil_AssertSetCallback(Xil_AssertCallback Routine); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** +* @} End of "addtogroup common_assert_apis". +*/ \ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_cache.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_cache.c new file mode 100644 index 0000000..312b7b0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_cache.c
@@ -0,0 +1,847 @@ +/****************************************************************************** +* +* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_cache.c +* +* Contains required functions for the ARM cache functionality. +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ----------------------------------------------- +* 5.0 pkp 05/29/14 First release +* 5.5 pkp 04/15/16 Updated the Xil_DCacheInvalidate, +* Xil_DCacheInvalidateLine and Xil_DCacheInvalidateRange +* functions description for proper explaination +* 6.2 pkp 01/22/17 Added support for EL1 non-secure +* 6.2 asa 01/31/17 The existing Xil_DCacheDisable API first flushes the +* D caches and then disables it. The problem with that is, +* potentially there will be a small window after the cache +* flush operation and before the we disable D caches where +* we might have valid data in cache lines. In such a +* scenario disabling the D cache can lead to unknown behavior. +* The ideal solution to this is to use assembly code for +* the complete API and avoid any memory accesses. But with +* that we will end up having a huge amount on assembly code +* which is not maintainable. Changes are done to use a mix +* of assembly and C code. All local variables are put in +* registers. Also function calls are avoided in the API to +* avoid using stack memory. +* These changes fix CR#966220. +* 6.2 mus 02/13/17 The new api Xil_ConfigureL1Prefetch is added to disable pre-fetching/configure +* the maximum number of outstanding data prefetches allowed in +* L1 cache system.It fixes CR#967864. +* 6.6 mus 02/27/18 Updated Xil_DCacheInvalidateRange and +* Xil_ICacheInvalidateRange APIs to change the data type of +* "cacheline" variable as "INTPTR", This change has been done +* to avoid the truncation of upper DDR addreses to 32 bit.It +* fixes CR#995581. +* 6.6 mus 03/15/18 By default CPUACTLR_EL1 is accessible only from EL3, it +* results into abort if accessed from EL1 non secure privilege +* level. Updated Xil_ConfigureL1Prefetch function to access +* CPUACTLR_EL1 only for EL3. +* +* </pre> +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xil_cache.h" +#include "xil_io.h" +#include "xpseudo_asm.h" +#include "xparameters.h" +#include "xreg_cortexa53.h" +#include "xil_exception.h" +#include "bspconfig.h" + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ +#define IRQ_FIQ_MASK 0xC0U /* Mask IRQ and FIQ interrupts in cpsr */ + +/****************************************************************************/ +/** +* @brief Enable the Data cache. +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_DCacheEnable(void) +{ + u32 CtrlReg; + + if (EL3 == 1) { + CtrlReg = mfcp(SCTLR_EL3); + } else if (EL1_NONSECURE == 1) { + CtrlReg = mfcp(SCTLR_EL1); + } + + /* enable caches only if they are disabled */ + if((CtrlReg & XREG_CONTROL_DCACHE_BIT) == 0X00000000U){ + + /* invalidate the Data cache */ + Xil_DCacheInvalidate(); + + CtrlReg |= XREG_CONTROL_DCACHE_BIT; + + if (EL3 == 1) { + /* enable the Data cache for el3*/ + mtcp(SCTLR_EL3,CtrlReg); + } else if (EL1_NONSECURE == 1) { + /* enable the Data cache for el1*/ + mtcp(SCTLR_EL1,CtrlReg); + } + } +} + +/****************************************************************************/ +/** +* @brief Disable the Data cache. +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_DCacheDisable(void) +{ + register u32 CsidReg; + register u32 C7Reg; + register u32 LineSize; + register u32 NumWays; + register u32 Way; + register u32 WayIndex; + register u32 WayAdjust; + register u32 Set; + register u32 SetIndex; + register u32 NumSet; + register u32 CacheLevel; + + dsb(); + asm( + "mov x0, #0\n\t" +#if EL3==1 + "mrs x0, sctlr_el3 \n\t" + "and w0, w0, #0xfffffffb\n\t" + "msr sctlr_el3, x0\n\t" +#elif EL1_NONSECURE==1 + "mrs x0, sctlr_el1 \n\t" + "and w0, w0, #0xfffffffb\n\t" + "msr sctlr_el1, x0\n\t" +#endif + "dsb sy\n\t" + ); + + /* Number of level of cache*/ + CacheLevel = 0U; + /* Select cache level 0 and D cache in CSSR */ + mtcp(CSSELR_EL1,CacheLevel); + isb(); + + CsidReg = mfcp(CCSIDR_EL1); + + /* Get the cacheline size, way size, index size from csidr */ + LineSize = (CsidReg & 0x00000007U) + 0x00000004U; + + /* Number of Ways */ + NumWays = (CsidReg & 0x00001FFFU) >> 3U; + NumWays += 0x00000001U; + + /*Number of Set*/ + NumSet = (CsidReg >> 13U) & 0x00007FFFU; + NumSet += 0x00000001U; + + WayAdjust = clz(NumWays) - (u32)0x0000001FU; + + Way = 0U; + Set = 0U; + + /* Flush all the cachelines */ + for (WayIndex = 0U; WayIndex < NumWays; WayIndex++) { + for (SetIndex = 0U; SetIndex < NumSet; SetIndex++) { + C7Reg = Way | Set | CacheLevel; + mtcpdc(CISW,C7Reg); + Set += (0x00000001U << LineSize); + } + Set = 0U; + Way += (0x00000001U << WayAdjust); + } + + /* Wait for Flush to complete */ + dsb(); + + /* Select cache level 1 and D cache in CSSR */ + CacheLevel += (0x00000001U << 1U); + mtcp(CSSELR_EL1,CacheLevel); + isb(); + + CsidReg = mfcp(CCSIDR_EL1); + + /* Get the cacheline size, way size, index size from csidr */ + LineSize = (CsidReg & 0x00000007U) + 0x00000004U; + + /* Number of Ways */ + NumWays = (CsidReg & 0x00001FFFU) >> 3U; + NumWays += 0x00000001U; + + /* Number of Sets */ + NumSet = (CsidReg >> 13U) & 0x00007FFFU; + NumSet += 0x00000001U; + + WayAdjust=clz(NumWays) - (u32)0x0000001FU; + + Way = 0U; + Set = 0U; + + /* Flush all the cachelines */ + for (WayIndex =0U; WayIndex < NumWays; WayIndex++) { + for (SetIndex =0U; SetIndex < NumSet; SetIndex++) { + C7Reg = Way | Set | CacheLevel; + mtcpdc(CISW,C7Reg); + Set += (0x00000001U << LineSize); + } + Set=0U; + Way += (0x00000001U<<WayAdjust); + } + /* Wait for Flush to complete */ + dsb(); + + asm( +#if EL3==1 + "tlbi ALLE3\n\t" +#elif EL1_NONSECURE==1 + "tlbi VMALLE1\n\t" +#endif + "dsb sy\r\n" + "isb\n\t" + ); +} + +/****************************************************************************/ +/** +* @brief Invalidate the Data cache. The contents present in the cache are +* cleaned and invalidated. +* +* @param None. +* +* @return None. +* +* @note In Cortex-A53, functionality to simply invalide the cachelines +* is not present. Such operations are a problem for an environment +* that supports virtualisation. It would allow one OS to invalidate +* a line belonging to another OS. This could lead to the other OS +* crashing because of the loss of essential data. Hence, such +* operations are promoted to clean and invalidate which avoids such +* corruption. +* +****************************************************************************/ +void Xil_DCacheInvalidate(void) +{ + register u32 CsidReg, C7Reg; + u32 LineSize, NumWays; + u32 Way, WayIndex,WayAdjust, Set, SetIndex, NumSet, CacheLevel; + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + + /* Number of level of cache*/ + + CacheLevel=0U; + /* Select cache level 0 and D cache in CSSR */ + mtcp(CSSELR_EL1,CacheLevel); + isb(); + + CsidReg = mfcp(CCSIDR_EL1); + + /* Get the cacheline size, way size, index size from csidr */ + LineSize = (CsidReg & 0x00000007U) + 0x00000004U; + + /* Number of Ways */ + NumWays = (CsidReg & 0x00001FFFU) >> 3U; + NumWays += 0X00000001U; + + /*Number of Set*/ + NumSet = (CsidReg >> 13U) & 0x00007FFFU; + NumSet += 0X00000001U; + + WayAdjust = clz(NumWays) - (u32)0x0000001FU; + + Way = 0U; + Set = 0U; + + /* Invalidate all the cachelines */ + for (WayIndex =0U; WayIndex < NumWays; WayIndex++) { + for (SetIndex =0U; SetIndex < NumSet; SetIndex++) { + C7Reg = Way | Set | CacheLevel; + mtcpdc(ISW,C7Reg); + Set += (0x00000001U << LineSize); + } + Set = 0U; + Way += (0x00000001U << WayAdjust); + } + + /* Wait for invalidate to complete */ + dsb(); + + /* Select cache level 1 and D cache in CSSR */ + CacheLevel += (0x00000001U<<1U) ; + mtcp(CSSELR_EL1,CacheLevel); + isb(); + + CsidReg = mfcp(CCSIDR_EL1); + + /* Get the cacheline size, way size, index size from csidr */ + LineSize = (CsidReg & 0x00000007U) + 0x00000004U; + + /* Number of Ways */ + NumWays = (CsidReg & 0x00001FFFU) >> 3U; + NumWays += 0x00000001U; + + /* Number of Sets */ + NumSet = (CsidReg >> 13U) & 0x00007FFFU; + NumSet += 0x00000001U; + + WayAdjust = clz(NumWays) - (u32)0x0000001FU; + + Way = 0U; + Set = 0U; + + /* Invalidate all the cachelines */ + for (WayIndex = 0U; WayIndex < NumWays; WayIndex++) { + for (SetIndex = 0U; SetIndex < NumSet; SetIndex++) { + C7Reg = Way | Set | CacheLevel; + mtcpdc(ISW,C7Reg); + Set += (0x00000001U << LineSize); + } + Set = 0U; + Way += (0x00000001U << WayAdjust); + } + /* Wait for invalidate to complete */ + dsb(); + + mtcpsr(currmask); +} + +/****************************************************************************/ +/** +* @brief Invalidate a Data cache line. The cacheline is cleaned and +* invalidated. +* +* @param adr: 64bit address of the data to be flushed. +* +* @return None. +* +* @note In Cortex-A53, functionality to simply invalide the cachelines +* is not present. Such operations are a problem for an environment +* that supports virtualisation. It would allow one OS to invalidate +* a line belonging to another OS. This could lead to the other OS +* crashing because of the loss of essential data. Hence, such +* operations are promoted to clean and invalidate which avoids such +* corruption. +* +****************************************************************************/ +void Xil_DCacheInvalidateLine(INTPTR adr) +{ + + u32 currmask; + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + /* Select cache level 0 and D cache in CSSR */ + mtcp(CSSELR_EL1,0x0); + mtcpdc(IVAC,(adr & (~0x3F))); + /* Wait for invalidate to complete */ + dsb(); + /* Select cache level 1 and D cache in CSSR */ + mtcp(CSSELR_EL1,0x2); + mtcpdc(IVAC,(adr & (~0x3F))); + /* Wait for invalidate to complete */ + dsb(); + mtcpsr(currmask); +} + +/****************************************************************************/ +/** +* @brief Invalidate the Data cache for the given address range. +* The cachelines present in the adderss range are cleaned and +* invalidated +* +* @param adr: 64bit start address of the range to be invalidated. +* @param len: Length of the range to be invalidated in bytes. +* +* @return None. +* +* @note In Cortex-A53, functionality to simply invalide the cachelines +* is not present. Such operations are a problem for an environment +* that supports virtualisation. It would allow one OS to invalidate +* a line belonging to another OS. This could lead to the other OS +* crashing because of the loss of essential data. Hence, such +* operations are promoted to clean and invalidate which avoids such +* corruption. +* +****************************************************************************/ +void Xil_DCacheInvalidateRange(INTPTR adr, INTPTR len) +{ + const INTPTR cacheline = 64U; + INTPTR end; + INTPTR tempadr = adr; + INTPTR tempend; + u32 currmask; + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + if (len != 0U) { + end = tempadr + len; + tempend = end; + + if ((tempadr & (cacheline-1U)) != 0U) { + tempadr &= (~(cacheline - 1U)); + Xil_DCacheFlushLine(tempadr); + tempadr += cacheline; + } + if ((tempend & (cacheline-1U)) != 0U) { + tempend &= (~(cacheline - 1U)); + Xil_DCacheFlushLine(tempend); + } + + while (tempadr < tempend) { + /* Select cache level 0 and D cache in CSSR */ + mtcp(CSSELR_EL1,0x0); + /* Invalidate Data cache line */ + mtcpdc(IVAC,(tempadr & (~0x3F))); + /* Wait for invalidate to complete */ + dsb(); + /* Select cache level 0 and D cache in CSSR */ + mtcp(CSSELR_EL1,0x2); + /* Invalidate Data cache line */ + mtcpdc(IVAC,(tempadr & (~0x3F))); + /* Wait for invalidate to complete */ + dsb(); + tempadr += cacheline; + } + } + mtcpsr(currmask); +} + +/****************************************************************************/ +/** +* @brief Flush the Data cache. +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_DCacheFlush(void) +{ + register u32 CsidReg, C7Reg; + u32 LineSize, NumWays; + u32 Way, WayIndex,WayAdjust, Set, SetIndex, NumSet, CacheLevel; + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + + /* Number of level of cache*/ + + CacheLevel = 0U; + /* Select cache level 0 and D cache in CSSR */ + mtcp(CSSELR_EL1,CacheLevel); + isb(); + + CsidReg = mfcp(CCSIDR_EL1); + + /* Get the cacheline size, way size, index size from csidr */ + LineSize = (CsidReg & 0x00000007U) + 0x00000004U; + + /* Number of Ways */ + NumWays = (CsidReg & 0x00001FFFU) >> 3U; + NumWays += 0x00000001U; + + /*Number of Set*/ + NumSet = (CsidReg >> 13U) & 0x00007FFFU; + NumSet += 0x00000001U; + + WayAdjust = clz(NumWays) - (u32)0x0000001FU; + + Way = 0U; + Set = 0U; + + /* Flush all the cachelines */ + for (WayIndex = 0U; WayIndex < NumWays; WayIndex++) { + for (SetIndex = 0U; SetIndex < NumSet; SetIndex++) { + C7Reg = Way | Set | CacheLevel; + mtcpdc(CISW,C7Reg); + Set += (0x00000001U << LineSize); + } + Set = 0U; + Way += (0x00000001U << WayAdjust); + } + + /* Wait for Flush to complete */ + dsb(); + + /* Select cache level 1 and D cache in CSSR */ + CacheLevel += (0x00000001U << 1U); + mtcp(CSSELR_EL1,CacheLevel); + isb(); + + CsidReg = mfcp(CCSIDR_EL1); + + /* Get the cacheline size, way size, index size from csidr */ + LineSize = (CsidReg & 0x00000007U) + 0x00000004U; + + /* Number of Ways */ + NumWays = (CsidReg & 0x00001FFFU) >> 3U; + NumWays += 0x00000001U; + + /* Number of Sets */ + NumSet = (CsidReg >> 13U) & 0x00007FFFU; + NumSet += 0x00000001U; + + WayAdjust=clz(NumWays) - (u32)0x0000001FU; + + Way = 0U; + Set = 0U; + + /* Flush all the cachelines */ + for (WayIndex =0U; WayIndex < NumWays; WayIndex++) { + for (SetIndex =0U; SetIndex < NumSet; SetIndex++) { + C7Reg = Way | Set | CacheLevel; + mtcpdc(CISW,C7Reg); + Set += (0x00000001U << LineSize); + } + Set=0U; + Way += (0x00000001U<<WayAdjust); + } + /* Wait for Flush to complete */ + dsb(); + + mtcpsr(currmask); +} + +/****************************************************************************/ +/** +* @brief Flush a Data cache line. If the byte specified by the address (adr) +* is cached by the Data cache, the cacheline containing that byte is +* invalidated. If the cacheline is modified (dirty), the entire +* contents of the cacheline are written to system memory before the +* line is invalidated. +* +* @param adr: 64bit address of the data to be flushed. +* +* @return None. +* +* @note The bottom 6 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_DCacheFlushLine(INTPTR adr) +{ + u32 currmask; + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + /* Select cache level 0 and D cache in CSSR */ + mtcp(CSSELR_EL1,0x0); + mtcpdc(CIVAC,(adr & (~0x3F))); + /* Wait for flush to complete */ + dsb(); + /* Select cache level 1 and D cache in CSSR */ + mtcp(CSSELR_EL1,0x2); + mtcpdc(CIVAC,(adr & (~0x3F))); + /* Wait for flush to complete */ + dsb(); + mtcpsr(currmask); +} +/****************************************************************************/ +/* +* @brief Flush the Data cache for the given address range. +* If the bytes specified by the address range are cached by the Data +* cache, the cachelines containing those bytes are invalidated. If +* the cachelines are modified (dirty), they are written to system +* memory before the lines are invalidated. +* +* @param adr: 64bit start address of the range to be flushed. +* @param len: Length of the range to be flushed in bytes. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_DCacheFlushRange(INTPTR adr, INTPTR len) +{ + const u32 cacheline = 64U; + INTPTR end; + INTPTR tempadr = adr; + INTPTR tempend; + u32 currmask; + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + if (len != 0x00000000U) { + end = tempadr + len; + tempend = end; + if ((tempadr & (0x3F)) != 0) { + tempadr &= ~(0x3F); + Xil_DCacheFlushLine(tempadr); + tempadr += cacheline; + } + if ((tempend & (0x3F)) != 0) { + tempend &= ~(0x3F); + Xil_DCacheFlushLine(tempend); + } + + while (tempadr < tempend) { + /* Select cache level 0 and D cache in CSSR */ + mtcp(CSSELR_EL1,0x0); + /* Flush Data cache line */ + mtcpdc(CIVAC,(tempadr & (~0x3F))); + /* Wait for flush to complete */ + dsb(); + /* Select cache level 1 and D cache in CSSR */ + mtcp(CSSELR_EL1,0x2); + /* Flush Data cache line */ + mtcpdc(CIVAC,(tempadr & (~0x3F))); + /* Wait for flush to complete */ + dsb(); + tempadr += cacheline; + } + } + + mtcpsr(currmask); +} + +/****************************************************************************/ +/** +* @brief Enable the instruction cache. +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_ICacheEnable(void) +{ + u32 CtrlReg; + + if (EL3 == 1) { + CtrlReg = mfcp(SCTLR_EL3); + } else if (EL1_NONSECURE == 1) { + CtrlReg = mfcp(SCTLR_EL1); + } + + /* enable caches only if they are disabled */ + if((CtrlReg & XREG_CONTROL_ICACHE_BIT)==0x00000000U){ + /* invalidate the instruction cache */ + Xil_ICacheInvalidate(); + + CtrlReg |= XREG_CONTROL_ICACHE_BIT; + + if (EL3 == 1) { + /* enable the instruction cache for el3*/ + mtcp(SCTLR_EL3,CtrlReg); + } else if (EL1_NONSECURE == 1) { + /* enable the instruction cache for el1*/ + mtcp(SCTLR_EL1,CtrlReg); + } + } +} + +/****************************************************************************/ +/** +* @brief Disable the instruction cache. +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_ICacheDisable(void) +{ + u32 CtrlReg; + + if (EL3 == 1) { + CtrlReg = mfcp(SCTLR_EL3); + } else if (EL1_NONSECURE == 1) { + CtrlReg = mfcp(SCTLR_EL1); + } + /* invalidate the instruction cache */ + Xil_ICacheInvalidate(); + CtrlReg &= ~(XREG_CONTROL_ICACHE_BIT); + + if (EL3 == 1) { + /* disable the instruction cache */ + mtcp(SCTLR_EL3,CtrlReg); + } else if (EL1_NONSECURE == 1) { + /* disable the instruction cache */ + mtcp(SCTLR_EL1,CtrlReg); + } + + +} + +/****************************************************************************/ +/** +* @brief Invalidate the entire instruction cache. +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_ICacheInvalidate(void) +{ + unsigned int currmask; + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + mtcp(CSSELR_EL1,0x1); + dsb(); + /* invalidate the instruction cache */ + mtcpicall(IALLU); + /* Wait for invalidate to complete */ + dsb(); + mtcpsr(currmask); +} + +/****************************************************************************/ +/** +* @brief Invalidate an instruction cache line. If the instruction specified +* by the parameter adr is cached by the instruction cache, the +* cacheline containing that instruction is invalidated. +* +* @param adr: 64bit address of the instruction to be invalidated. +* +* @return None. +* +* @note The bottom 6 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_ICacheInvalidateLine(INTPTR adr) +{ + u32 currmask; + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + mtcp(CSSELR_EL1,0x1); + /*Invalidate I Cache line*/ + mtcpic(IVAU,adr & (~0x3F)); + /* Wait for invalidate to complete */ + dsb(); + mtcpsr(currmask); +} + +/****************************************************************************/ +/** +* @brief Invalidate the instruction cache for the given address range. +* If the instructions specified by the address range are cached by +* the instrunction cache, the cachelines containing those +* instructions are invalidated. +* +* @param adr: 64bit start address of the range to be invalidated. +* @param len: Length of the range to be invalidated in bytes. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_ICacheInvalidateRange(INTPTR adr, INTPTR len) +{ + const INTPTR cacheline = 64U; + INTPTR end; + INTPTR tempadr = adr; + INTPTR tempend; + u32 currmask; + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + if (len != 0x00000000U) { + end = tempadr + len; + tempend = end; + tempadr &= ~(cacheline - 0x00000001U); + + /* Select cache Level 0 I-cache in CSSR */ + mtcp(CSSELR_EL1,0x1); + while (tempadr < tempend) { + /*Invalidate I Cache line*/ + mtcpic(IVAU,adr & (~0x3F)); + + tempadr += cacheline; + } + } +/* Wait for invalidate to complete */ + dsb(); + mtcpsr(currmask); +} + +/****************************************************************************/ +/** +* @brief Configure the maximum number of outstanding data prefetches +* allowed in L1 cache. +* +* @param num: maximum number of outstanding data prefetches allowed, +* valid values are 0-7. +* +* @return None. +* +* @note This function is implemented only for EL3 privilege level. +* +*****************************************************************************/ +void Xil_ConfigureL1Prefetch (u8 num) { +#if EL3 + u64 val=0; + + val= mfcp(S3_1_C15_C2_0 ); + val &= ~(L1_DATA_PREFETCH_CONTROL_MASK); + val |= (num << L1_DATA_PREFETCH_CONTROL_SHIFT); + mtcp(S3_1_C15_C2_0,val); +#endif +}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_cache.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_cache.h new file mode 100644 index 0000000..56c00f3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_cache.h
@@ -0,0 +1,91 @@ +/****************************************************************************** +* +* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_cache.h +* +* @addtogroup a53_64_cache_apis Cortex A53 64bit Processor Cache Functions +* +* Cache functions provide access to cache related operations such as flush +* and invalidate for instruction and data caches. It gives option to perform +* the cache operations on a single cacheline, a range of memory and an entire +* cache. +* +* @{ +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ----------------------------------------------- +* 5.00 pkp 05/29/14 First release +* </pre> +* +******************************************************************************/ +#ifndef XIL_CACHE_H +#define XIL_CACHE_H + +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ +#define L1_DATA_PREFETCH_CONTROL_MASK 0xE000 +#define L1_DATA_PREFETCH_CONTROL_SHIFT 13 + +/************************** Function Prototypes ******************************/ +void Xil_DCacheEnable(void); +void Xil_DCacheDisable(void); +void Xil_DCacheInvalidate(void); +void Xil_DCacheInvalidateRange(INTPTR adr, INTPTR len); +void Xil_DCacheInvalidateLine(INTPTR adr); +void Xil_DCacheFlush(void); +void Xil_DCacheFlushRange(INTPTR adr, INTPTR len); +void Xil_DCacheFlushLine(INTPTR adr); + +void Xil_ICacheEnable(void); +void Xil_ICacheDisable(void); +void Xil_ICacheInvalidate(void); +void Xil_ICacheInvalidateRange(INTPTR adr, INTPTR len); +void Xil_ICacheInvalidateLine(INTPTR adr); +void Xil_ConfigureL1Prefetch(u8 num); +#ifdef __cplusplus +} +#endif + +#endif +/** +* @} End of "addtogroup a53_64_cache_apis". +*/
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_cache_vxworks.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_cache_vxworks.h new file mode 100644 index 0000000..6e8cfa7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_cache_vxworks.h
@@ -0,0 +1,93 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_cache_vxworks.h +* +* Contains the cache related functions for VxWorks that is wrapped by +* xil_cache. +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 1.00a hbm 12/11/09 Initial release +* +* </pre> +* +* @note +* +******************************************************************************/ + +#ifndef XIL_CACHE_VXWORKS_H +#define XIL_CACHE_VXWORKS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "vxWorks.h" +#include "vxLib.h" +#include "sysLibExtra.h" +#include "cacheLib.h" + +#if (CPU_FAMILY==PPC) + +#define Xil_DCacheEnable() cacheEnable(DATA_CACHE) + +#define Xil_DCacheDisable() cacheDisable(DATA_CACHE) + +#define Xil_DCacheInvalidateRange(Addr, Len) \ + cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len)) + +#define Xil_DCacheFlushRange(Addr, Len) \ + cacheFlush(DATA_CACHE, (void *)(Addr), (Len)) + +#define Xil_ICacheEnable() cacheEnable(INSTRUCTION_CACHE) + +#define Xil_ICacheDisable() cacheDisable(INSTRUCTION_CACHE) + +#define Xil_ICacheInvalidateRange(Addr, Len) \ + cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len)) + + +#else +#error "Unknown processor / architecture. Must be PPC for VxWorks." +#endif + +#ifdef __cplusplus +} +#endif + +#endif
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_errata.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_errata.h new file mode 100644 index 0000000..bab74ba --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_errata.h
@@ -0,0 +1,85 @@ +/****************************************************************************** +* +* Copyright (C) 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_errata.h +* +* @addtogroup a53_errata Cortex A53 64 bit Processor Errata Support +* @{ +* Various ARM errata are handled in the standalone BSP. The implementation for +* errata handling follows ARM guidelines and is based on the open source Linux +* support for these errata. +* +* @note +* The errata handling is enabled by default. To disable handling of all the +* errata globally, un-define the macro ENABLE_ARM_ERRATA in xil_errata.h. To +* disable errata on a per-erratum basis, un-define relevant macros in +* xil_errata.h. +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ----------------------------------------------- +* 6.4 mus 08/11/17 First release +* </pre> +* +******************************************************************************/ +#ifndef XIL_ERRATA_H +#define XIL_ERRATA_H + +/** + * @name errata_definitions + * + * The errata conditions handled in the standalone BSP are listed below + * @{ + */ + +#define ENABLE_ARM_ERRATA 1 + +#ifdef ENABLE_ARM_ERRATA + +/** + * Errata No: 855873 + * Description: An eviction might overtake a cache clean operation + */ +#define CONFIG_ARM_ERRATA_855873 1 + + +/*@}*/ +#endif /* ENABLE_ARM_ERRATA */ + +#endif /* XIL_ERRATA_H */ +/** +* @} End of "addtogroup a53_errata". +*/ \ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_exception.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_exception.c new file mode 100644 index 0000000..4a2f2cf --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_exception.c
@@ -0,0 +1,334 @@ +/****************************************************************************** +* +* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xil_exception.c +* +* This file contains low-level driver functions for the Cortex A53,A9,R5 exception +* Handler. +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- -------- -------- ----------------------------------------------- +* 5.2 pkp 28/05/15 First release +* 6.0 mus 27/07/16 Consolidated exceptions for a53,a9 and r5 +* processors and added Xil_UndefinedExceptionHandler +* for a53 32 bit and r5 as well. +* 6.4 mus 08/06/17 Updated debug prints to replace %x with the %lx, to +* fix the warnings. +* </pre> +* +*****************************************************************************/ + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_exception.h" +#include "xpseudo_asm.h" +#include "xdebug.h" +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + +typedef struct { + Xil_ExceptionHandler Handler; + void *Data; +} XExc_VectorTableEntry; + +/***************** Macros (Inline Functions) Definitions ********************/ + +/************************** Function Prototypes *****************************/ +static void Xil_ExceptionNullHandler(void *Data); +/************************** Variable Definitions *****************************/ +/* + * Exception vector table to store handlers for each exception vector. + */ +#if defined (__aarch64__) +XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] = +{ + {Xil_ExceptionNullHandler, NULL}, + {Xil_SyncAbortHandler, NULL}, + {Xil_ExceptionNullHandler, NULL}, + {Xil_ExceptionNullHandler, NULL}, + {Xil_SErrorAbortHandler, NULL}, + +}; +#else +XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] = +{ + {Xil_ExceptionNullHandler, NULL}, + {Xil_UndefinedExceptionHandler, NULL}, + {Xil_ExceptionNullHandler, NULL}, + {Xil_PrefetchAbortHandler, NULL}, + {Xil_DataAbortHandler, NULL}, + {Xil_ExceptionNullHandler, NULL}, + {Xil_ExceptionNullHandler, NULL}, +}; +#endif +#if !defined (__aarch64__) +u32 DataAbortAddr; /* Address of instruction causing data abort */ +u32 PrefetchAbortAddr; /* Address of instruction causing prefetch abort */ +u32 UndefinedExceptionAddr; /* Address of instruction causing Undefined + exception */ +#endif + +/*****************************************************************************/ + +/****************************************************************************/ +/** +* +* This function is a stub Handler that is the default Handler that gets called +* if the application has not setup a Handler for a specific exception. The +* function interface has to match the interface specified for a Handler even +* though none of the arguments are used. +* +* @param Data is unused by this function. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +static void Xil_ExceptionNullHandler(void *Data) +{ + (void) Data; +DieLoop: goto DieLoop; +} + +/****************************************************************************/ +/** +* @brief The function is a common API used to initialize exception handlers +* across all supported arm processors. For ARM Cortex-A53, Cortex-R5, +* and Cortex-A9, the exception handlers are being initialized +* statically and this function does not do anything. +* However, it is still present to take care of backward compatibility +* issues (in earlier versions of BSPs, this API was being used to +* initialize exception handlers). +* +* @param None. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void Xil_ExceptionInit(void) +{ + return; +} + +/*****************************************************************************/ +/** +* @brief Register a handler for a specific exception. This handler is being +* called when the processor encounters the specified exception. +* +* @param exception_id contains the ID of the exception source and should +* be in the range of 0 to XIL_EXCEPTION_ID_LAST. +* See xil_exception.h for further information. +* @param Handler to the Handler for that exception. +* @param Data is a reference to Data that will be passed to the +* Handler when it gets called. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_ExceptionRegisterHandler(u32 Exception_id, + Xil_ExceptionHandler Handler, + void *Data) +{ + XExc_VectorTable[Exception_id].Handler = Handler; + XExc_VectorTable[Exception_id].Data = Data; +} + +/*****************************************************************************/ +/** +* +* @brief Removes the Handler for a specific exception Id. The stub Handler +* is then registered for this exception Id. +* +* @param exception_id contains the ID of the exception source and should +* be in the range of 0 to XIL_EXCEPTION_ID_LAST. +* See xil_exception.h for further information. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_ExceptionRemoveHandler(u32 Exception_id) +{ + Xil_ExceptionRegisterHandler(Exception_id, + Xil_ExceptionNullHandler, + NULL); +} + +#if defined (__aarch64__) +/*****************************************************************************/ +/** +* +* Default Synchronous abort handler which prints a debug message on console if +* Debug flag is enabled +* +* @param None +* +* @return None. +* +* @note None. +* +****************************************************************************/ + +void Xil_SyncAbortHandler(void *CallBackRef){ + (void) CallBackRef; + xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n"); + while(1) { + ; + } +} + +/*****************************************************************************/ +/** +* +* Default SError abort handler which prints a debug message on console if +* Debug flag is enabled +* +* @param None +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_SErrorAbortHandler(void *CallBackRef){ + (void) CallBackRef; + xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n"); + while(1) { + ; + } +} +#else +/*****************************************************************************/ +/* +* +* Default Data abort handler which prints data fault status register through +* which information about data fault can be acquired +* +* @param None +* +* @return None. +* +* @note None. +* +****************************************************************************/ + +void Xil_DataAbortHandler(void *CallBackRef){ + (void) CallBackRef; +#ifdef DEBUG + u32 FaultStatus; + + xdbg_printf(XDBG_DEBUG_ERROR, "Data abort \n"); + #ifdef __GNUC__ + FaultStatus = mfcp(XREG_CP15_DATA_FAULT_STATUS); + #elif defined (__ICCARM__) + mfcp(XREG_CP15_DATA_FAULT_STATUS,FaultStatus); + #else + { volatile register u32 Reg __asm(XREG_CP15_DATA_FAULT_STATUS); + FaultStatus = Reg; } + #endif + xdbg_printf(XDBG_DEBUG_GENERAL, "Data abort with Data Fault Status Register %lx\n",FaultStatus); + xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instruction causing Data abort %lx\n",DataAbortAddr); +#endif + while(1) { + ; + } +} + +/*****************************************************************************/ +/* +* +* Default Prefetch abort handler which prints prefetch fault status register through +* which information about instruction prefetch fault can be acquired +* +* @param None +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_PrefetchAbortHandler(void *CallBackRef){ + (void) CallBackRef; +#ifdef DEBUG + u32 FaultStatus; + + xdbg_printf(XDBG_DEBUG_ERROR, "Prefetch abort \n"); + #ifdef __GNUC__ + FaultStatus = mfcp(XREG_CP15_INST_FAULT_STATUS); + #elif defined (__ICCARM__) + mfcp(XREG_CP15_INST_FAULT_STATUS,FaultStatus); + #else + { volatile register u32 Reg __asm(XREG_CP15_INST_FAULT_STATUS); + FaultStatus = Reg; } + #endif + xdbg_printf(XDBG_DEBUG_GENERAL, "Prefetch abort with Instruction Fault Status Register %lx\n",FaultStatus); + xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instruction causing Prefetch abort %lx\n",PrefetchAbortAddr); +#endif + while(1) { + ; + } +} +/*****************************************************************************/ +/* +* +* Default undefined exception handler which prints address of the undefined +* instruction if debug prints are enabled +* +* @param None +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_UndefinedExceptionHandler(void *CallBackRef){ + (void) CallBackRef; + xdbg_printf(XDBG_DEBUG_GENERAL, "Address of the undefined instruction %lx\n",UndefinedExceptionAddr); + while(1) { + ; + } +} +#endif
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_exception.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_exception.h new file mode 100644 index 0000000..ad48222 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_exception.h
@@ -0,0 +1,256 @@ +/****************************************************************************** +* +* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_exception.h +* +* This header file contains ARM Cortex A53,A9,R5 specific exception related APIs. +* For exception related functions that can be used across all Xilinx supported +* processors, please use xil_exception.h. +* +* @addtogroup arm_exception_apis ARM Processor Exception Handling +* @{ +* ARM processors specific exception related APIs for cortex A53,A9 and R5 can +* utilized for enabling/disabling IRQ, registering/removing handler for +* exceptions or initializing exception vector table with null handler. +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- -------- -------- ----------------------------------------------- +* 5.2 pkp 28/05/15 First release +* 6.0 mus 27/07/16 Consolidated file for a53,a9 and r5 processors +* </pre> +* +******************************************************************************/ + +#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */ +#define XIL_EXCEPTION_H /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xpseudo_asm.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions ****************************/ + +#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE +#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE +#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE) + +#define XIL_EXCEPTION_ID_FIRST 0U +#if defined (__aarch64__) +#define XIL_EXCEPTION_ID_SYNC_INT 1U +#define XIL_EXCEPTION_ID_IRQ_INT 2U +#define XIL_EXCEPTION_ID_FIQ_INT 3U +#define XIL_EXCEPTION_ID_SERROR_ABORT_INT 4U +#define XIL_EXCEPTION_ID_LAST 5U +#else +#define XIL_EXCEPTION_ID_RESET 0U +#define XIL_EXCEPTION_ID_UNDEFINED_INT 1U +#define XIL_EXCEPTION_ID_SWI_INT 2U +#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3U +#define XIL_EXCEPTION_ID_DATA_ABORT_INT 4U +#define XIL_EXCEPTION_ID_IRQ_INT 5U +#define XIL_EXCEPTION_ID_FIQ_INT 6U +#define XIL_EXCEPTION_ID_LAST 6U +#endif + +/* + * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors. + */ +#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT + +/**************************** Type Definitions ******************************/ + +/** + * This typedef is the exception handler function. + */ +typedef void (*Xil_ExceptionHandler)(void *data); +typedef void (*Xil_InterruptHandler)(void *data); + +/***************** Macros (Inline Functions) Definitions ********************/ + +/****************************************************************************/ +/** +* @brief Enable Exceptions. +* +* @param Mask: Value for enabling the exceptions. +* +* @return None. +* +* @note If bit is 0, exception is enabled. +* C-Style signature: void Xil_ExceptionEnableMask(Mask) +* +******************************************************************************/ +#if defined (__GNUC__) || defined (__ICCARM__) +#define Xil_ExceptionEnableMask(Mask) \ + mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL)) +#else +#define Xil_ExceptionEnableMask(Mask) \ + { \ + register u32 Reg __asm("cpsr"); \ + mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \ + } +#endif +/****************************************************************************/ +/** +* @brief Enable the IRQ exception. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +#define Xil_ExceptionEnable() \ + Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ) + +/****************************************************************************/ +/** +* @brief Disable Exceptions. +* +* @param Mask: Value for disabling the exceptions. +* +* @return None. +* +* @note If bit is 1, exception is disabled. +* C-Style signature: Xil_ExceptionDisableMask(Mask) +* +******************************************************************************/ +#if defined (__GNUC__) || defined (__ICCARM__) +#define Xil_ExceptionDisableMask(Mask) \ + mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL)) +#else +#define Xil_ExceptionDisableMask(Mask) \ + { \ + register u32 Reg __asm("cpsr"); \ + mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \ + } +#endif +/****************************************************************************/ +/** +* Disable the IRQ exception. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +#define Xil_ExceptionDisable() \ + Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ) + +#if !defined (__aarch64__) && !defined (ARMA53_32) +/****************************************************************************/ +/** +* @brief Enable nested interrupts by clearing the I and F bits in CPSR. This +* API is defined for cortex-a9 and cortex-r5. +* +* @return None. +* +* @note This macro is supposed to be used from interrupt handlers. In the +* interrupt handler the interrupts are disabled by default (I and F +* are 1). To allow nesting of interrupts, this macro should be +* used. It clears the I and F bits by changing the ARM mode to +* system mode. Once these bits are cleared and provided the +* preemption of interrupt conditions are met in the GIC, nesting of +* interrupts will start happening. +* Caution: This macro must be used with caution. Before calling this +* macro, the user must ensure that the source of the current IRQ +* is appropriately cleared. Otherwise, as soon as we clear the I and +* F bits, there can be an infinite loop of interrupts with an +* eventual crash (all the stack space getting consumed). +******************************************************************************/ +#define Xil_EnableNestedInterrupts() \ + __asm__ __volatile__ ("stmfd sp!, {lr}"); \ + __asm__ __volatile__ ("mrs lr, spsr"); \ + __asm__ __volatile__ ("stmfd sp!, {lr}"); \ + __asm__ __volatile__ ("msr cpsr_c, #0x1F"); \ + __asm__ __volatile__ ("stmfd sp!, {lr}"); + +/****************************************************************************/ +/** +* @brief Disable the nested interrupts by setting the I and F bits. This API +* is defined for cortex-a9 and cortex-r5. +* +* @return None. +* +* @note This macro is meant to be called in the interrupt service routines. +* This macro cannot be used independently. It can only be used when +* nesting of interrupts have been enabled by using the macro +* Xil_EnableNestedInterrupts(). In a typical flow, the user first +* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate +* point. The user then must call this macro before exiting the interrupt +* service routine. This macro puts the ARM back in IRQ/FIQ mode and +* hence sets back the I and F bits. +******************************************************************************/ +#define Xil_DisableNestedInterrupts() \ + __asm__ __volatile__ ("ldmfd sp!, {lr}"); \ + __asm__ __volatile__ ("msr cpsr_c, #0x92"); \ + __asm__ __volatile__ ("ldmfd sp!, {lr}"); \ + __asm__ __volatile__ ("msr spsr_cxsf, lr"); \ + __asm__ __volatile__ ("ldmfd sp!, {lr}"); \ + +#endif +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ + +extern void Xil_ExceptionRegisterHandler(u32 Exception_id, + Xil_ExceptionHandler Handler, + void *Data); + +extern void Xil_ExceptionRemoveHandler(u32 Exception_id); + +extern void Xil_ExceptionInit(void); +#if defined (__aarch64__) +void Xil_SyncAbortHandler(void *CallBackRef); +void Xil_SErrorAbortHandler(void *CallBackRef); +#else +extern void Xil_DataAbortHandler(void *CallBackRef); +extern void Xil_PrefetchAbortHandler(void *CallBackRef); +extern void Xil_UndefinedExceptionHandler(void *CallBackRef); +#endif + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XIL_EXCEPTION_H */ +/** +* @} End of "addtogroup arm_exception_apis". +*/ \ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_hal.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_hal.h new file mode 100644 index 0000000..d4434d0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_hal.h
@@ -0,0 +1,61 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_hal.h +* +* Contains all the HAL header files. +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 1.00a hbm 07/28/09 Initial release +* +* </pre> +* +* @note +* +******************************************************************************/ + +#ifndef XIL_HAL_H +#define XIL_HAL_H + +#include "xil_cache.h" +#include "xil_io.h" +#include "xil_assert.h" +#include "xil_exception.h" +#include "xil_types.h" + +#endif
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_io.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_io.c new file mode 100644 index 0000000..90bfc81 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_io.c
@@ -0,0 +1,102 @@ +/****************************************************************************** +* +* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_io.c +* +* Contains I/O functions for memory-mapped or non-memory-mapped I/O +* architectures. +* +* @note +* +* This file contains architecture-dependent code. +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- -------- -------- ----------------------------------------------- +* 5.00 pkp 05/29/14 First release +* </pre> +******************************************************************************/ + + +/***************************** Include Files *********************************/ +#include "xil_io.h" +#include "xil_types.h" +#include "xil_assert.h" + +/*****************************************************************************/ +/** +* +* @brief Perform a 16-bit endian converion. +* +* @param Data: 16 bit value to be converted +* +* @return 16 bit Data with converted endianess +* +******************************************************************************/ +u16 Xil_EndianSwap16(u16 Data) +{ + return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U)); +} + +/*****************************************************************************/ +/** +* +* @brief Perform a 32-bit endian converion. +* +* @param Data: 32 bit value to be converted +* +* @return 32 bit data with converted endianess +* +******************************************************************************/ +u32 Xil_EndianSwap32(u32 Data) +{ + u16 LoWord; + u16 HiWord; + + /* get each of the half words from the 32 bit word */ + + LoWord = (u16) (Data & 0x0000FFFFU); + HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U); + + /* byte swap each of the 16 bit half words */ + + LoWord = (((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U)); + HiWord = (((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U)); + + /* swap the half words before returning the value */ + + return ((((u32)LoWord) << (u32)16U) | (u32)HiWord); +}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_io.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_io.h new file mode 100644 index 0000000..9c5aa43 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_io.h
@@ -0,0 +1,345 @@ +/****************************************************************************** +* +* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_io.h +* +* @addtogroup common_io_interfacing_apis Register IO interfacing APIs +* +* The xil_io.h file contains the interface for the general I/O component, which +* encapsulates the Input/Output functions for the processors that do not +* require any special I/O handling. +* +* @{ +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- -------- -------- ----------------------------------------------- +* 5.00 pkp 05/29/14 First release +* 6.00 mus 08/19/16 Remove checking of __LITTLE_ENDIAN__ flag for +* ARM processors +* </pre> +******************************************************************************/ + +#ifndef XIL_IO_H /* prevent circular inclusions */ +#define XIL_IO_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_printf.h" + +#if defined (__MICROBLAZE__) +#include "mb_interface.h" +#else +#include "xpseudo_asm.h" +#endif + +/************************** Function Prototypes ******************************/ +u16 Xil_EndianSwap16(u16 Data); +u32 Xil_EndianSwap32(u32 Data); +#ifdef ENABLE_SAFETY +extern u32 XStl_RegUpdate(u32 RegAddr, u32 RegVal); +#endif + +/***************** Macros (Inline Functions) Definitions *********************/ +#if defined __GNUC__ +#if defined (__MICROBLAZE__) +# define INST_SYNC mbar(0) +# define DATA_SYNC mbar(1) +# else +# define SYNCHRONIZE_IO dmb() +# define INST_SYNC isb() +# define DATA_SYNC dsb() +# endif +#else +# define SYNCHRONIZE_IO +# define INST_SYNC +# define DATA_SYNC +# define INST_SYNC +# define DATA_SYNC +#endif + +#if defined (__GNUC__) || defined (__ICCARM__) || defined (__MICROBLAZE__) +#define INLINE inline +#else +#define INLINE __inline +#endif + +/*****************************************************************************/ +/** +* +* @brief Performs an input operation for a memory location by reading +* from the specified address and returning the 8 bit Value read from +* that address. +* +* @param Addr: contains the address to perform the input operation +* +* @return The 8 bit Value read from the specified input address. + +* +******************************************************************************/ +static INLINE u8 Xil_In8(UINTPTR Addr) +{ + return *(volatile u8 *) Addr; +} + +/*****************************************************************************/ +/** +* +* @brief Performs an input operation for a memory location by reading from +* the specified address and returning the 16 bit Value read from that +* address. +* +* @param Addr: contains the address to perform the input operation +* +* @return The 16 bit Value read from the specified input address. +* +******************************************************************************/ +static INLINE u16 Xil_In16(UINTPTR Addr) +{ + return *(volatile u16 *) Addr; +} + +/*****************************************************************************/ +/** +* +* @brief Performs an input operation for a memory location by +* reading from the specified address and returning the 32 bit Value +* read from that address. +* +* @param Addr: contains the address to perform the input operation +* +* @return The 32 bit Value read from the specified input address. +* +******************************************************************************/ +static INLINE u32 Xil_In32(UINTPTR Addr) +{ + return *(volatile u32 *) Addr; +} + +/*****************************************************************************/ +/** +* +* @brief Performs an input operation for a memory location by reading the +* 64 bit Value read from that address. +* +* +* @param Addr: contains the address to perform the input operation +* +* @return The 64 bit Value read from the specified input address. +* +******************************************************************************/ +static INLINE u64 Xil_In64(UINTPTR Addr) +{ + return *(volatile u64 *) Addr; +} + +/*****************************************************************************/ +/** +* +* @brief Performs an output operation for an memory location by +* writing the 8 bit Value to the the specified address. +* +* @param Addr: contains the address to perform the output operation +* @param Value: contains the 8 bit Value to be written at the specified +* address. +* +* @return None. +* +******************************************************************************/ +static INLINE void Xil_Out8(UINTPTR Addr, u8 Value) +{ + volatile u8 *LocalAddr = (volatile u8 *)Addr; + *LocalAddr = Value; +} + +/*****************************************************************************/ +/** +* +* @brief Performs an output operation for a memory location by writing the +* 16 bit Value to the the specified address. +* +* @param Addr contains the address to perform the output operation +* @param Value contains the Value to be written at the specified address. +* +* @return None. +* +******************************************************************************/ +static INLINE void Xil_Out16(UINTPTR Addr, u16 Value) +{ + volatile u16 *LocalAddr = (volatile u16 *)Addr; + *LocalAddr = Value; +} + +/*****************************************************************************/ +/** +* +* @brief Performs an output operation for a memory location by writing the +* 32 bit Value to the the specified address. +* +* @param Addr contains the address to perform the output operation +* @param Value contains the 32 bit Value to be written at the specified +* address. +* +* @return None. +* +******************************************************************************/ +static INLINE void Xil_Out32(UINTPTR Addr, u32 Value) +{ +#ifndef ENABLE_SAFETY + volatile u32 *LocalAddr = (volatile u32 *)Addr; + *LocalAddr = Value; +#else + XStl_RegUpdate(Addr, Value); +#endif +} + +/*****************************************************************************/ +/** +* +* @brief Performs an output operation for a memory location by writing the +* 64 bit Value to the the specified address. +* +* @param Addr contains the address to perform the output operation +* @param Value contains 64 bit Value to be written at the specified address. +* +* @return None. +* +******************************************************************************/ +static INLINE void Xil_Out64(UINTPTR Addr, u64 Value) +{ + volatile u64 *LocalAddr = (volatile u64 *)Addr; + *LocalAddr = Value; +} + +#if defined (__MICROBLAZE__) +#ifdef __LITTLE_ENDIAN__ +# define Xil_In16LE Xil_In16 +# define Xil_In32LE Xil_In32 +# define Xil_Out16LE Xil_Out16 +# define Xil_Out32LE Xil_Out32 +# define Xil_Htons Xil_EndianSwap16 +# define Xil_Htonl Xil_EndianSwap32 +# define Xil_Ntohs Xil_EndianSwap16 +# define Xil_Ntohl Xil_EndianSwap32 +# else +# define Xil_In16BE Xil_In16 +# define Xil_In32BE Xil_In32 +# define Xil_Out16BE Xil_Out16 +# define Xil_Out32BE Xil_Out32 +# define Xil_Htons(Data) (Data) +# define Xil_Htonl(Data) (Data) +# define Xil_Ntohs(Data) (Data) +# define Xil_Ntohl(Data) (Data) +#endif +#else +# define Xil_In16LE Xil_In16 +# define Xil_In32LE Xil_In32 +# define Xil_Out16LE Xil_Out16 +# define Xil_Out32LE Xil_Out32 +# define Xil_Htons Xil_EndianSwap16 +# define Xil_Htonl Xil_EndianSwap32 +# define Xil_Ntohs Xil_EndianSwap16 +# define Xil_Ntohl Xil_EndianSwap32 +#endif + +#if defined (__MICROBLAZE__) +#ifdef __LITTLE_ENDIAN__ +static INLINE u16 Xil_In16BE(UINTPTR Addr) +#else +static INLINE u16 Xil_In16LE(UINTPTR Addr) +#endif +#else +static INLINE u16 Xil_In16BE(UINTPTR Addr) +#endif +{ + u16 value = Xil_In16(Addr); + return Xil_EndianSwap16(value); +} + +#if defined (__MICROBLAZE__) +#ifdef __LITTLE_ENDIAN__ +static INLINE u32 Xil_In32BE(UINTPTR Addr) +#else +static INLINE u32 Xil_In32LE(UINTPTR Addr) +#endif +#else +static INLINE u32 Xil_In32BE(UINTPTR Addr) +#endif +{ + u32 value = Xil_In32(Addr); + return Xil_EndianSwap32(value); +} + +#if defined (__MICROBLAZE__) +#ifdef __LITTLE_ENDIAN__ +static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value) +#else +static INLINE void Xil_Out16LE(UINTPTR Addr, u16 Value) +#endif +#else +static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value) +#endif +{ + Value = Xil_EndianSwap16(Value); + Xil_Out16(Addr, Value); +} + +#if defined (__MICROBLAZE__) +#ifdef __LITTLE_ENDIAN__ +static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value) +#else +static INLINE void Xil_Out32LE(UINTPTR Addr, u32 Value) +#endif +#else +static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value) +#endif +{ + Value = Xil_EndianSwap32(Value); + Xil_Out32(Addr, Value); +} + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** +* @} End of "addtogroup common_io_interfacing_apis". +*/
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_macroback.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_macroback.h new file mode 100644 index 0000000..ebafde8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_macroback.h
@@ -0,0 +1,1052 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/*********************************************************************/ +/** + * @file xil_macroback.h + * + * This header file is meant to bring back the removed _m macros. + * This header file must be included last. + * The following macros are not defined here due to the driver change: + * XGpio_mSetDataDirection + * XGpio_mGetDataReg + * XGpio_mSetDataReg + * XIIC_RESET + * XIIC_CLEAR_STATS + * XSpi_mReset + * XSysAce_mSetCfgAddr + * XSysAce_mIsCfgDone + * XTft_mSetPixel + * XTft_mGetPixel + * XWdtTb_mEnableWdt + * XWdtTb_mDisbleWdt + * XWdtTb_mRestartWdt + * XWdtTb_mGetTimebaseReg + * XWdtTb_mHasReset + * + * Please refer the corresonding driver document for replacement. + * + *********************************************************************/ + +#ifndef XIL_MACROBACK_H +#define XIL_MACROBACK_H + +/*********************************************************************/ +/** + * Macros for Driver XCan + * + *********************************************************************/ +#ifndef XCan_mReadReg +#define XCan_mReadReg XCan_ReadReg +#endif + +#ifndef XCan_mWriteReg +#define XCan_mWriteReg XCan_WriteReg +#endif + +#ifndef XCan_mIsTxDone +#define XCan_mIsTxDone XCan_IsTxDone +#endif + +#ifndef XCan_mIsTxFifoFull +#define XCan_mIsTxFifoFull XCan_IsTxFifoFull +#endif + +#ifndef XCan_mIsHighPriorityBufFull +#define XCan_mIsHighPriorityBufFull XCan_IsHighPriorityBufFull +#endif + +#ifndef XCan_mIsRxEmpty +#define XCan_mIsRxEmpty XCan_IsRxEmpty +#endif + +#ifndef XCan_mIsAcceptFilterBusy +#define XCan_mIsAcceptFilterBusy XCan_IsAcceptFilterBusy +#endif + +#ifndef XCan_mCreateIdValue +#define XCan_mCreateIdValue XCan_CreateIdValue +#endif + +#ifndef XCan_mCreateDlcValue +#define XCan_mCreateDlcValue XCan_CreateDlcValue +#endif + +/*********************************************************************/ +/** + * Macros for Driver XDmaCentral + * + *********************************************************************/ +#ifndef XDmaCentral_mWriteReg +#define XDmaCentral_mWriteReg XDmaCentral_WriteReg +#endif + +#ifndef XDmaCentral_mReadReg +#define XDmaCentral_mReadReg XDmaCentral_ReadReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XDsAdc + * + *********************************************************************/ +#ifndef XDsAdc_mWriteReg +#define XDsAdc_mWriteReg XDsAdc_WriteReg +#endif + +#ifndef XDsAdc_mReadReg +#define XDsAdc_mReadReg XDsAdc_ReadReg +#endif + +#ifndef XDsAdc_mIsEmpty +#define XDsAdc_mIsEmpty XDsAdc_IsEmpty +#endif + +#ifndef XDsAdc_mSetFstmReg +#define XDsAdc_mSetFstmReg XDsAdc_SetFstmReg +#endif + +#ifndef XDsAdc_mGetFstmReg +#define XDsAdc_mGetFstmReg XDsAdc_GetFstmReg +#endif + +#ifndef XDsAdc_mEnableConversion +#define XDsAdc_mEnableConversion XDsAdc_EnableConversion +#endif + +#ifndef XDsAdc_mDisableConversion +#define XDsAdc_mDisableConversion XDsAdc_DisableConversion +#endif + +#ifndef XDsAdc_mGetFifoOccyReg +#define XDsAdc_mGetFifoOccyReg XDsAdc_GetFifoOccyReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XDsDac + * + *********************************************************************/ +#ifndef XDsDac_mWriteReg +#define XDsDac_mWriteReg XDsDac_WriteReg +#endif + +#ifndef XDsDac_mReadReg +#define XDsDac_mReadReg XDsDac_ReadReg +#endif + +#ifndef XDsDac_mIsEmpty +#define XDsDac_mIsEmpty XDsDac_IsEmpty +#endif + +#ifndef XDsDac_mFifoIsFull +#define XDsDac_mFifoIsFull XDsDac_FifoIsFull +#endif + +#ifndef XDsDac_mGetVacancy +#define XDsDac_mGetVacancy XDsDac_GetVacancy +#endif + +/*********************************************************************/ +/** + * Macros for Driver XEmacLite + * + *********************************************************************/ +#ifndef XEmacLite_mReadReg +#define XEmacLite_mReadReg XEmacLite_ReadReg +#endif + +#ifndef XEmacLite_mWriteReg +#define XEmacLite_mWriteReg XEmacLite_WriteReg +#endif + +#ifndef XEmacLite_mGetTxStatus +#define XEmacLite_mGetTxStatus XEmacLite_GetTxStatus +#endif + +#ifndef XEmacLite_mSetTxStatus +#define XEmacLite_mSetTxStatus XEmacLite_SetTxStatus +#endif + +#ifndef XEmacLite_mGetRxStatus +#define XEmacLite_mGetRxStatus XEmacLite_GetRxStatus +#endif + +#ifndef XEmacLite_mSetRxStatus +#define XEmacLite_mSetRxStatus XEmacLite_SetRxStatus +#endif + +#ifndef XEmacLite_mIsTxDone +#define XEmacLite_mIsTxDone XEmacLite_IsTxDone +#endif + +#ifndef XEmacLite_mIsRxEmpty +#define XEmacLite_mIsRxEmpty XEmacLite_IsRxEmpty +#endif + +#ifndef XEmacLite_mNextTransmitAddr +#define XEmacLite_mNextTransmitAddr XEmacLite_NextTransmitAddr +#endif + +#ifndef XEmacLite_mNextReceiveAddr +#define XEmacLite_mNextReceiveAddr XEmacLite_NextReceiveAddr +#endif + +#ifndef XEmacLite_mIsMdioConfigured +#define XEmacLite_mIsMdioConfigured XEmacLite_IsMdioConfigured +#endif + +#ifndef XEmacLite_mIsLoopbackConfigured +#define XEmacLite_mIsLoopbackConfigured XEmacLite_IsLoopbackConfigured +#endif + +#ifndef XEmacLite_mGetReceiveDataLength +#define XEmacLite_mGetReceiveDataLength XEmacLite_GetReceiveDataLength +#endif + +#ifndef XEmacLite_mGetTxActive +#define XEmacLite_mGetTxActive XEmacLite_GetTxActive +#endif + +#ifndef XEmacLite_mSetTxActive +#define XEmacLite_mSetTxActive XEmacLite_SetTxActive +#endif + +/*********************************************************************/ +/** + * Macros for Driver XGpio + * + *********************************************************************/ +#ifndef XGpio_mWriteReg +#define XGpio_mWriteReg XGpio_WriteReg +#endif + +#ifndef XGpio_mReadReg +#define XGpio_mReadReg XGpio_ReadReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XHwIcap + * + *********************************************************************/ +#ifndef XHwIcap_mFifoWrite +#define XHwIcap_mFifoWrite XHwIcap_FifoWrite +#endif + +#ifndef XHwIcap_mFifoRead +#define XHwIcap_mFifoRead XHwIcap_FifoRead +#endif + +#ifndef XHwIcap_mSetSizeReg +#define XHwIcap_mSetSizeReg XHwIcap_SetSizeReg +#endif + +#ifndef XHwIcap_mGetControlReg +#define XHwIcap_mGetControlReg XHwIcap_GetControlReg +#endif + +#ifndef XHwIcap_mStartConfig +#define XHwIcap_mStartConfig XHwIcap_StartConfig +#endif + +#ifndef XHwIcap_mStartReadBack +#define XHwIcap_mStartReadBack XHwIcap_StartReadBack +#endif + +#ifndef XHwIcap_mGetStatusReg +#define XHwIcap_mGetStatusReg XHwIcap_GetStatusReg +#endif + +#ifndef XHwIcap_mIsTransferDone +#define XHwIcap_mIsTransferDone XHwIcap_IsTransferDone +#endif + +#ifndef XHwIcap_mIsDeviceBusy +#define XHwIcap_mIsDeviceBusy XHwIcap_IsDeviceBusy +#endif + +#ifndef XHwIcap_mIntrGlobalEnable +#define XHwIcap_mIntrGlobalEnable XHwIcap_IntrGlobalEnable +#endif + +#ifndef XHwIcap_mIntrGlobalDisable +#define XHwIcap_mIntrGlobalDisable XHwIcap_IntrGlobalDisable +#endif + +#ifndef XHwIcap_mIntrGetStatus +#define XHwIcap_mIntrGetStatus XHwIcap_IntrGetStatus +#endif + +#ifndef XHwIcap_mIntrDisable +#define XHwIcap_mIntrDisable XHwIcap_IntrDisable +#endif + +#ifndef XHwIcap_mIntrEnable +#define XHwIcap_mIntrEnable XHwIcap_IntrEnable +#endif + +#ifndef XHwIcap_mIntrGetEnabled +#define XHwIcap_mIntrGetEnabled XHwIcap_IntrGetEnabled +#endif + +#ifndef XHwIcap_mIntrClear +#define XHwIcap_mIntrClear XHwIcap_IntrClear +#endif + +#ifndef XHwIcap_mGetWrFifoVacancy +#define XHwIcap_mGetWrFifoVacancy XHwIcap_GetWrFifoVacancy +#endif + +#ifndef XHwIcap_mGetRdFifoOccupancy +#define XHwIcap_mGetRdFifoOccupancy XHwIcap_GetRdFifoOccupancy +#endif + +#ifndef XHwIcap_mSliceX2Col +#define XHwIcap_mSliceX2Col XHwIcap_SliceX2Col +#endif + +#ifndef XHwIcap_mSliceY2Row +#define XHwIcap_mSliceY2Row XHwIcap_SliceY2Row +#endif + +#ifndef XHwIcap_mSliceXY2Slice +#define XHwIcap_mSliceXY2Slice XHwIcap_SliceXY2Slice +#endif + +#ifndef XHwIcap_mReadReg +#define XHwIcap_mReadReg XHwIcap_ReadReg +#endif + +#ifndef XHwIcap_mWriteReg +#define XHwIcap_mWriteReg XHwIcap_WriteReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XIic + * + *********************************************************************/ +#ifndef XIic_mReadReg +#define XIic_mReadReg XIic_ReadReg +#endif + +#ifndef XIic_mWriteReg +#define XIic_mWriteReg XIic_WriteReg +#endif + +#ifndef XIic_mEnterCriticalRegion +#define XIic_mEnterCriticalRegion XIic_IntrGlobalDisable +#endif + +#ifndef XIic_mExitCriticalRegion +#define XIic_mExitCriticalRegion XIic_IntrGlobalEnable +#endif + +#ifndef XIIC_GINTR_DISABLE +#define XIIC_GINTR_DISABLE XIic_IntrGlobalDisable +#endif + +#ifndef XIIC_GINTR_ENABLE +#define XIIC_GINTR_ENABLE XIic_IntrGlobalEnable +#endif + +#ifndef XIIC_IS_GINTR_ENABLED +#define XIIC_IS_GINTR_ENABLED XIic_IsIntrGlobalEnabled +#endif + +#ifndef XIIC_WRITE_IISR +#define XIIC_WRITE_IISR XIic_WriteIisr +#endif + +#ifndef XIIC_READ_IISR +#define XIIC_READ_IISR XIic_ReadIisr +#endif + +#ifndef XIIC_WRITE_IIER +#define XIIC_WRITE_IIER XIic_WriteIier +#endif + +#ifndef XIic_mClearIisr +#define XIic_mClearIisr XIic_ClearIisr +#endif + +#ifndef XIic_mSend7BitAddress +#define XIic_mSend7BitAddress XIic_Send7BitAddress +#endif + +#ifndef XIic_mDynSend7BitAddress +#define XIic_mDynSend7BitAddress XIic_DynSend7BitAddress +#endif + +#ifndef XIic_mDynSendStartStopAddress +#define XIic_mDynSendStartStopAddress XIic_DynSendStartStopAddress +#endif + +#ifndef XIic_mDynSendStop +#define XIic_mDynSendStop XIic_DynSendStop +#endif + +#ifndef XIic_mSend10BitAddrByte1 +#define XIic_mSend10BitAddrByte1 XIic_Send10BitAddrByte1 +#endif + +#ifndef XIic_mSend10BitAddrByte2 +#define XIic_mSend10BitAddrByte2 XIic_Send10BitAddrByte2 +#endif + +#ifndef XIic_mSend7BitAddr +#define XIic_mSend7BitAddr XIic_Send7BitAddr +#endif + +#ifndef XIic_mDisableIntr +#define XIic_mDisableIntr XIic_DisableIntr +#endif + +#ifndef XIic_mEnableIntr +#define XIic_mEnableIntr XIic_EnableIntr +#endif + +#ifndef XIic_mClearIntr +#define XIic_mClearIntr XIic_ClearIntr +#endif + +#ifndef XIic_mClearEnableIntr +#define XIic_mClearEnableIntr XIic_ClearEnableIntr +#endif + +#ifndef XIic_mFlushRxFifo +#define XIic_mFlushRxFifo XIic_FlushRxFifo +#endif + +#ifndef XIic_mFlushTxFifo +#define XIic_mFlushTxFifo XIic_FlushTxFifo +#endif + +#ifndef XIic_mReadRecvByte +#define XIic_mReadRecvByte XIic_ReadRecvByte +#endif + +#ifndef XIic_mWriteSendByte +#define XIic_mWriteSendByte XIic_WriteSendByte +#endif + +#ifndef XIic_mSetControlRegister +#define XIic_mSetControlRegister XIic_SetControlRegister +#endif + +/*********************************************************************/ +/** + * Macros for Driver XIntc + * + *********************************************************************/ +#ifndef XIntc_mMasterEnable +#define XIntc_mMasterEnable XIntc_MasterEnable +#endif + +#ifndef XIntc_mMasterDisable +#define XIntc_mMasterDisable XIntc_MasterDisable +#endif + +#ifndef XIntc_mEnableIntr +#define XIntc_mEnableIntr XIntc_EnableIntr +#endif + +#ifndef XIntc_mDisableIntr +#define XIntc_mDisableIntr XIntc_DisableIntr +#endif + +#ifndef XIntc_mAckIntr +#define XIntc_mAckIntr XIntc_AckIntr +#endif + +#ifndef XIntc_mGetIntrStatus +#define XIntc_mGetIntrStatus XIntc_GetIntrStatus +#endif + +/*********************************************************************/ +/** + * Macros for Driver XLlDma + * + *********************************************************************/ +#ifndef XLlDma_mBdRead +#define XLlDma_mBdRead XLlDma_BdRead +#endif + +#ifndef XLlDma_mBdWrite +#define XLlDma_mBdWrite XLlDma_BdWrite +#endif + +#ifndef XLlDma_mWriteReg +#define XLlDma_mWriteReg XLlDma_WriteReg +#endif + +#ifndef XLlDma_mReadReg +#define XLlDma_mReadReg XLlDma_ReadReg +#endif + +#ifndef XLlDma_mBdClear +#define XLlDma_mBdClear XLlDma_BdClear +#endif + +#ifndef XLlDma_mBdSetStsCtrl +#define XLlDma_mBdSetStsCtrl XLlDma_BdSetStsCtrl +#endif + +#ifndef XLlDma_mBdGetStsCtrl +#define XLlDma_mBdGetStsCtrl XLlDma_BdGetStsCtrl +#endif + +#ifndef XLlDma_mBdSetLength +#define XLlDma_mBdSetLength XLlDma_BdSetLength +#endif + +#ifndef XLlDma_mBdGetLength +#define XLlDma_mBdGetLength XLlDma_BdGetLength +#endif + +#ifndef XLlDma_mBdSetId +#define XLlDma_mBdSetId XLlDma_BdSetId +#endif + +#ifndef XLlDma_mBdGetId +#define XLlDma_mBdGetId XLlDma_BdGetId +#endif + +#ifndef XLlDma_mBdSetBufAddr +#define XLlDma_mBdSetBufAddr XLlDma_BdSetBufAddr +#endif + +#ifndef XLlDma_mBdGetBufAddr +#define XLlDma_mBdGetBufAddr XLlDma_BdGetBufAddr +#endif + +#ifndef XLlDma_mBdGetLength +#define XLlDma_mBdGetLength XLlDma_BdGetLength +#endif + +#ifndef XLlDma_mGetTxRing +#define XLlDma_mGetTxRing XLlDma_GetTxRing +#endif + +#ifndef XLlDma_mGetRxRing +#define XLlDma_mGetRxRing XLlDma_GetRxRing +#endif + +#ifndef XLlDma_mGetCr +#define XLlDma_mGetCr XLlDma_GetCr +#endif + +#ifndef XLlDma_mSetCr +#define XLlDma_mSetCr XLlDma_SetCr +#endif + +#ifndef XLlDma_mBdRingCntCalc +#define XLlDma_mBdRingCntCalc XLlDma_BdRingCntCalc +#endif + +#ifndef XLlDma_mBdRingMemCalc +#define XLlDma_mBdRingMemCalc XLlDma_BdRingMemCalc +#endif + +#ifndef XLlDma_mBdRingGetCnt +#define XLlDma_mBdRingGetCnt XLlDma_BdRingGetCnt +#endif + +#ifndef XLlDma_mBdRingGetFreeCnt +#define XLlDma_mBdRingGetFreeCnt XLlDma_BdRingGetFreeCnt +#endif + +#ifndef XLlDma_mBdRingSnapShotCurrBd +#define XLlDma_mBdRingSnapShotCurrBd XLlDma_BdRingSnapShotCurrBd +#endif + +#ifndef XLlDma_mBdRingNext +#define XLlDma_mBdRingNext XLlDma_BdRingNext +#endif + +#ifndef XLlDma_mBdRingPrev +#define XLlDma_mBdRingPrev XLlDma_BdRingPrev +#endif + +#ifndef XLlDma_mBdRingGetSr +#define XLlDma_mBdRingGetSr XLlDma_BdRingGetSr +#endif + +#ifndef XLlDma_mBdRingSetSr +#define XLlDma_mBdRingSetSr XLlDma_BdRingSetSr +#endif + +#ifndef XLlDma_mBdRingGetCr +#define XLlDma_mBdRingGetCr XLlDma_BdRingGetCr +#endif + +#ifndef XLlDma_mBdRingSetCr +#define XLlDma_mBdRingSetCr XLlDma_BdRingSetCr +#endif + +#ifndef XLlDma_mBdRingBusy +#define XLlDma_mBdRingBusy XLlDma_BdRingBusy +#endif + +#ifndef XLlDma_mBdRingIntEnable +#define XLlDma_mBdRingIntEnable XLlDma_BdRingIntEnable +#endif + +#ifndef XLlDma_mBdRingIntDisable +#define XLlDma_mBdRingIntDisable XLlDma_BdRingIntDisable +#endif + +#ifndef XLlDma_mBdRingIntGetEnabled +#define XLlDma_mBdRingIntGetEnabled XLlDma_BdRingIntGetEnabled +#endif + +#ifndef XLlDma_mBdRingGetIrq +#define XLlDma_mBdRingGetIrq XLlDma_BdRingGetIrq +#endif + +#ifndef XLlDma_mBdRingAckIrq +#define XLlDma_mBdRingAckIrq XLlDma_BdRingAckIrq +#endif + +/*********************************************************************/ +/** + * Macros for Driver XMbox + * + *********************************************************************/ +#ifndef XMbox_mWriteReg +#define XMbox_mWriteReg XMbox_WriteReg +#endif + +#ifndef XMbox_mReadReg +#define XMbox_mReadReg XMbox_ReadReg +#endif + +#ifndef XMbox_mWriteMBox +#define XMbox_mWriteMBox XMbox_WriteMBox +#endif + +#ifndef XMbox_mReadMBox +#define XMbox_mReadMBox XMbox_ReadMBox +#endif + +#ifndef XMbox_mFSLReadMBox +#define XMbox_mFSLReadMBox XMbox_FSLReadMBox +#endif + +#ifndef XMbox_mFSLWriteMBox +#define XMbox_mFSLWriteMBox XMbox_FSLWriteMBox +#endif + +#ifndef XMbox_mFSLIsEmpty +#define XMbox_mFSLIsEmpty XMbox_FSLIsEmpty +#endif + +#ifndef XMbox_mFSLIsFull +#define XMbox_mFSLIsFull XMbox_FSLIsFull +#endif + +#ifndef XMbox_mIsEmpty +#define XMbox_mIsEmpty XMbox_IsEmptyHw +#endif + +#ifndef XMbox_mIsFull +#define XMbox_mIsFull XMbox_IsFullHw +#endif + +/*********************************************************************/ +/** + * Macros for Driver XMpmc + * + *********************************************************************/ +#ifndef XMpmc_mReadReg +#define XMpmc_mReadReg XMpmc_ReadReg +#endif + +#ifndef XMpmc_mWriteReg +#define XMpmc_mWriteReg XMpmc_WriteReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XMutex + * + *********************************************************************/ +#ifndef XMutex_mWriteReg +#define XMutex_mWriteReg XMutex_WriteReg +#endif + +#ifndef XMutex_mReadReg +#define XMutex_mReadReg XMutex_ReadReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XPcie + * + *********************************************************************/ +#ifndef XPcie_mReadReg +#define XPcie_mReadReg XPcie_ReadReg +#endif + +#ifndef XPcie_mWriteReg +#define XPcie_mWriteReg XPcie_WriteReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XSpi + * + *********************************************************************/ +#ifndef XSpi_mIntrGlobalEnable +#define XSpi_mIntrGlobalEnable XSpi_IntrGlobalEnable +#endif + +#ifndef XSpi_mIntrGlobalDisable +#define XSpi_mIntrGlobalDisable XSpi_IntrGlobalDisable +#endif + +#ifndef XSpi_mIsIntrGlobalEnabled +#define XSpi_mIsIntrGlobalEnabled XSpi_IsIntrGlobalEnabled +#endif + +#ifndef XSpi_mIntrGetStatus +#define XSpi_mIntrGetStatus XSpi_IntrGetStatus +#endif + +#ifndef XSpi_mIntrClear +#define XSpi_mIntrClear XSpi_IntrClear +#endif + +#ifndef XSpi_mIntrEnable +#define XSpi_mIntrEnable XSpi_IntrEnable +#endif + +#ifndef XSpi_mIntrDisable +#define XSpi_mIntrDisable XSpi_IntrDisable +#endif + +#ifndef XSpi_mIntrGetEnabled +#define XSpi_mIntrGetEnabled XSpi_IntrGetEnabled +#endif + +#ifndef XSpi_mSetControlReg +#define XSpi_mSetControlReg XSpi_SetControlReg +#endif + +#ifndef XSpi_mGetControlReg +#define XSpi_mGetControlReg XSpi_GetControlReg +#endif + +#ifndef XSpi_mGetStatusReg +#define XSpi_mGetStatusReg XSpi_GetStatusReg +#endif + +#ifndef XSpi_mSetSlaveSelectReg +#define XSpi_mSetSlaveSelectReg XSpi_SetSlaveSelectReg +#endif + +#ifndef XSpi_mGetSlaveSelectReg +#define XSpi_mGetSlaveSelectReg XSpi_GetSlaveSelectReg +#endif + +#ifndef XSpi_mEnable +#define XSpi_mEnable XSpi_Enable +#endif + +#ifndef XSpi_mDisable +#define XSpi_mDisable XSpi_Disable +#endif + +/*********************************************************************/ +/** + * Macros for Driver XSysAce + * + *********************************************************************/ +#ifndef XSysAce_mGetControlReg +#define XSysAce_mGetControlReg XSysAce_GetControlReg +#endif + +#ifndef XSysAce_mSetControlReg +#define XSysAce_mSetControlReg XSysAce_SetControlReg +#endif + +#ifndef XSysAce_mOrControlReg +#define XSysAce_mOrControlReg XSysAce_OrControlReg +#endif + +#ifndef XSysAce_mAndControlReg +#define XSysAce_mAndControlReg XSysAce_AndControlReg +#endif + +#ifndef XSysAce_mGetErrorReg +#define XSysAce_mGetErrorReg XSysAce_GetErrorReg +#endif + +#ifndef XSysAce_mGetStatusReg +#define XSysAce_mGetStatusReg XSysAce_GetStatusReg +#endif + +#ifndef XSysAce_mWaitForLock +#define XSysAce_mWaitForLock XSysAce_WaitForLock +#endif + +#ifndef XSysAce_mEnableIntr +#define XSysAce_mEnableIntr XSysAce_EnableIntr +#endif + +#ifndef XSysAce_mDisableIntr +#define XSysAce_mDisableIntr XSysAce_DisableIntr +#endif + +#ifndef XSysAce_mIsReadyForCmd +#define XSysAce_mIsReadyForCmd XSysAce_IsReadyForCmd +#endif + +#ifndef XSysAce_mIsMpuLocked +#define XSysAce_mIsMpuLocked XSysAce_IsMpuLocked +#endif + +#ifndef XSysAce_mIsIntrEnabled +#define XSysAce_mIsIntrEnabled XSysAce_IsIntrEnabled +#endif + +/*********************************************************************/ +/** + * Macros for Driver XSysMon + * + *********************************************************************/ +#ifndef XSysMon_mIsEventSamplingModeSet +#define XSysMon_mIsEventSamplingModeSet XSysMon_IsEventSamplingModeSet +#endif + +#ifndef XSysMon_mIsDrpBusy +#define XSysMon_mIsDrpBusy XSysMon_IsDrpBusy +#endif + +#ifndef XSysMon_mIsDrpLocked +#define XSysMon_mIsDrpLocked XSysMon_IsDrpLocked +#endif + +#ifndef XSysMon_mRawToTemperature +#define XSysMon_mRawToTemperature XSysMon_RawToTemperature +#endif + +#ifndef XSysMon_mRawToVoltage +#define XSysMon_mRawToVoltage XSysMon_RawToVoltage +#endif + +#ifndef XSysMon_mTemperatureToRaw +#define XSysMon_mTemperatureToRaw XSysMon_TemperatureToRaw +#endif + +#ifndef XSysMon_mVoltageToRaw +#define XSysMon_mVoltageToRaw XSysMon_VoltageToRaw +#endif + +#ifndef XSysMon_mReadReg +#define XSysMon_mReadReg XSysMon_ReadReg +#endif + +#ifndef XSysMon_mWriteReg +#define XSysMon_mWriteReg XSysMon_WriteReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XTmrCtr + * + *********************************************************************/ +#ifndef XTimerCtr_mReadReg +#define XTimerCtr_mReadReg XTimerCtr_ReadReg +#endif + +#ifndef XTmrCtr_mWriteReg +#define XTmrCtr_mWriteReg XTmrCtr_WriteReg +#endif + +#ifndef XTmrCtr_mSetControlStatusReg +#define XTmrCtr_mSetControlStatusReg XTmrCtr_SetControlStatusReg +#endif + +#ifndef XTmrCtr_mGetControlStatusReg +#define XTmrCtr_mGetControlStatusReg XTmrCtr_GetControlStatusReg +#endif + +#ifndef XTmrCtr_mGetTimerCounterReg +#define XTmrCtr_mGetTimerCounterReg XTmrCtr_GetTimerCounterReg +#endif + +#ifndef XTmrCtr_mSetLoadReg +#define XTmrCtr_mSetLoadReg XTmrCtr_SetLoadReg +#endif + +#ifndef XTmrCtr_mGetLoadReg +#define XTmrCtr_mGetLoadReg XTmrCtr_GetLoadReg +#endif + +#ifndef XTmrCtr_mEnable +#define XTmrCtr_mEnable XTmrCtr_Enable +#endif + +#ifndef XTmrCtr_mDisable +#define XTmrCtr_mDisable XTmrCtr_Disable +#endif + +#ifndef XTmrCtr_mEnableIntr +#define XTmrCtr_mEnableIntr XTmrCtr_EnableIntr +#endif + +#ifndef XTmrCtr_mDisableIntr +#define XTmrCtr_mDisableIntr XTmrCtr_DisableIntr +#endif + +#ifndef XTmrCtr_mLoadTimerCounterReg +#define XTmrCtr_mLoadTimerCounterReg XTmrCtr_LoadTimerCounterReg +#endif + +#ifndef XTmrCtr_mHasEventOccurred +#define XTmrCtr_mHasEventOccurred XTmrCtr_HasEventOccurred +#endif + +/*********************************************************************/ +/** + * Macros for Driver XUartLite + * + *********************************************************************/ +#ifndef XUartLite_mUpdateStats +#define XUartLite_mUpdateStats XUartLite_UpdateStats +#endif + +#ifndef XUartLite_mWriteReg +#define XUartLite_mWriteReg XUartLite_WriteReg +#endif + +#ifndef XUartLite_mReadReg +#define XUartLite_mReadReg XUartLite_ReadReg +#endif + +#ifndef XUartLite_mClearStats +#define XUartLite_mClearStats XUartLite_ClearStats +#endif + +#ifndef XUartLite_mSetControlReg +#define XUartLite_mSetControlReg XUartLite_SetControlReg +#endif + +#ifndef XUartLite_mGetStatusReg +#define XUartLite_mGetStatusReg XUartLite_GetStatusReg +#endif + +#ifndef XUartLite_mIsReceiveEmpty +#define XUartLite_mIsReceiveEmpty XUartLite_IsReceiveEmpty +#endif + +#ifndef XUartLite_mIsTransmitFull +#define XUartLite_mIsTransmitFull XUartLite_IsTransmitFull +#endif + +#ifndef XUartLite_mIsIntrEnabled +#define XUartLite_mIsIntrEnabled XUartLite_IsIntrEnabled +#endif + +#ifndef XUartLite_mEnableIntr +#define XUartLite_mEnableIntr XUartLite_EnableIntr +#endif + +#ifndef XUartLite_mDisableIntr +#define XUartLite_mDisableIntr XUartLite_DisableIntr +#endif + +/*********************************************************************/ +/** + * Macros for Driver XUartNs550 + * + *********************************************************************/ +#ifndef XUartNs550_mUpdateStats +#define XUartNs550_mUpdateStats XUartNs550_UpdateStats +#endif + +#ifndef XUartNs550_mReadReg +#define XUartNs550_mReadReg XUartNs550_ReadReg +#endif + +#ifndef XUartNs550_mWriteReg +#define XUartNs550_mWriteReg XUartNs550_WriteReg +#endif + +#ifndef XUartNs550_mClearStats +#define XUartNs550_mClearStats XUartNs550_ClearStats +#endif + +#ifndef XUartNs550_mGetLineStatusReg +#define XUartNs550_mGetLineStatusReg XUartNs550_GetLineStatusReg +#endif + +#ifndef XUartNs550_mGetLineControlReg +#define XUartNs550_mGetLineControlReg XUartNs550_GetLineControlReg +#endif + +#ifndef XUartNs550_mSetLineControlReg +#define XUartNs550_mSetLineControlReg XUartNs550_SetLineControlReg +#endif + +#ifndef XUartNs550_mEnableIntr +#define XUartNs550_mEnableIntr XUartNs550_EnableIntr +#endif + +#ifndef XUartNs550_mDisableIntr +#define XUartNs550_mDisableIntr XUartNs550_DisableIntr +#endif + +#ifndef XUartNs550_mIsReceiveData +#define XUartNs550_mIsReceiveData XUartNs550_IsReceiveData +#endif + +#ifndef XUartNs550_mIsTransmitEmpty +#define XUartNs550_mIsTransmitEmpty XUartNs550_IsTransmitEmpty +#endif + +/*********************************************************************/ +/** + * Macros for Driver XUsb + * + *********************************************************************/ +#ifndef XUsb_mReadReg +#define XUsb_mReadReg XUsb_ReadReg +#endif + +#ifndef XUsb_mWriteReg +#define XUsb_mWriteReg XUsb_WriteReg +#endif + +#endif
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_mem.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_mem.c new file mode 100644 index 0000000..0929a68 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_mem.c
@@ -0,0 +1,83 @@ +/******************************************************************************/ +/** +* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* @file xil_mem.c +* +* This file contains xil mem copy function to use in case of word aligned +* data copies. +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- -------- -------- ----------------------------------------------- +* 6.1 nsk 11/07/16 First release. +* +* </pre> +* +*****************************************************************************/ + +/***************************** Include Files ********************************/ + +#include "xil_types.h" + +/***************** Inline Functions Definitions ********************/ +/*****************************************************************************/ +/** +* @brief This function copies memory from once location to other. +* +* @param dst: pointer pointing to destination memory +* +* @param src: pointer pointing to source memory +* +* @param cnt: 32 bit length of bytes to be copied +* +*****************************************************************************/ +void Xil_MemCpy(void* dst, const void* src, u32 cnt) +{ + char *d = (char*)(void *)dst; + const char *s = src; + + while (cnt >= sizeof (int)) { + *(int*)d = *(int*)s; + d += sizeof (int); + s += sizeof (int); + cnt -= sizeof (int); + } + while ((cnt) > 0U){ + *d = *s; + d += 1U; + s += 1U; + cnt -= 1U; + } +}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_mem.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_mem.h new file mode 100644 index 0000000..a2d5e66 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_mem.h
@@ -0,0 +1,59 @@ +/******************************************************************************/ +/** +* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* @file xil_mem.h +* +* @addtogroup common_mem_operation_api Customized APIs for Memory Operations +* +* The xil_mem.h file contains prototype for functions related +* to memory operations. These APIs are applicable for all processors supported +* by Xilinx. +* +* @{ +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- -------- -------- ----------------------------------------------- +* 6.1 nsk 11/07/16 First release. +* +* </pre> +* +*****************************************************************************/ + +/************************** Function Prototypes *****************************/ + +void Xil_MemCpy(void* dst, const void* src, u32 cnt); +/** +* @} End of "addtogroup common_mem_operation_api". +*/ \ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_mmu.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_mmu.c new file mode 100644 index 0000000..87b9886 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_mmu.c
@@ -0,0 +1,129 @@ +/****************************************************************************** +* +* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xil_mmu.c +* +* This file provides APIs for enabling/disabling MMU and setting the memory +* attributes for sections, in the MMU translation table. +* MMU APIs are yet to be implemented. They are left blank to avoid any +* compilation error +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- --------------------------------------------------- +* 5.00 pkp 05/29/14 First release +* 6.02 pkp 01/22/17 Added support for EL1 non-secure +* </pre> +* +* @note +* +* None. +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xil_cache.h" +#include "xpseudo_asm.h" +#include "xil_types.h" +#include "xil_mmu.h" +#include "bspconfig.h" +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +#define BLOCK_SIZE_2MB 0x200000U +#define BLOCK_SIZE_1GB 0x40000000U +#define ADDRESS_LIMIT_4GB 0x100000000UL + +/************************** Variable Definitions *****************************/ + +extern INTPTR MMUTableL1; +extern INTPTR MMUTableL2; + +/************************** Function Prototypes ******************************/ +/*****************************************************************************/ +/** +* brief It sets the memory attributes for a section, in the translation +* table. If the address (defined by Addr) is less than 4GB, the +* memory attribute(attrib) is set for a section of 2MB memory. If the +* address (defined by Addr) is greater than 4GB, the memory attribute +* (attrib) is set for a section of 1GB memory. +* +* @param Addr: 64-bit address for which attributes are to be set. +* @param attrib: Attribute for the specified memory region. xil_mmu.h +* contains commonly used memory attributes definitions which can be +* utilized for this function. +* +* @return None. +* +* @note The MMU and D-cache need not be disabled before changing an +* translation table attribute. +* +******************************************************************************/ +void Xil_SetTlbAttributes(UINTPTR Addr, u64 attrib) +{ + INTPTR *ptr; + INTPTR section; + u64 block_size; + /* if region is less than 4GB MMUTable level 2 need to be modified */ + if(Addr < ADDRESS_LIMIT_4GB){ + /* block size is 2MB for addressed < 4GB*/ + block_size = BLOCK_SIZE_2MB; + section = Addr / block_size; + ptr = &MMUTableL2 + section; + } + /* if region is greater than 4GB MMUTable level 1 need to be modified */ + else{ + /* block size is 1GB for addressed > 4GB */ + block_size = BLOCK_SIZE_1GB; + section = Addr / block_size; + ptr = &MMUTableL1 + section; + } + *ptr = (Addr & (~(block_size-1))) | attrib; + + Xil_DCacheFlush(); + + if (EL3 == 1) + mtcptlbi(ALLE3); + else if (EL1_NONSECURE == 1) + mtcptlbi(VMALLE1); + + dsb(); /* ensure completion of the BP and TLB invalidation */ + isb(); /* synchronize context on this processor */ + +}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_mmu.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_mmu.h new file mode 100644 index 0000000..0f2db84 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_mmu.h
@@ -0,0 +1,113 @@ +/****************************************************************************** +* +* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xil_mmu.h +* +* @addtogroup a53_64_mmu_apis Cortex A53 64bit Processor MMU Handling +* +* MMU function equip users to modify default memory attributes of MMU table as +* per the need. +* +* @{ +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- --------------------------------------------------- +* 5.00 pkp 05/29/14 First release +* </pre> +* +* @note +* +* None. +* +******************************************************************************/ + +#ifndef XIL_MMU_H +#define XIL_MMU_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/***************************** Include Files *********************************/ + +#include "xil_types.h" + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +/* Memory type */ +#define NORM_NONCACHE 0x401UL /* Normal Non-cacheable*/ +#define STRONG_ORDERED 0x409UL /* Strongly ordered (Device-nGnRnE)*/ +#define DEVICE_MEMORY 0x40DUL /* Device memory (Device-nGnRE)*/ +#define RESERVED 0x0UL /* reserved memory*/ + +/* Normal write-through cacheable inner shareable*/ +#define NORM_WT_CACHE 0x711UL + +/* Normal write back cacheable inner-shareable */ +#define NORM_WB_CACHE 0x705UL + +/* + * shareability attribute only applicable to + * normal cacheable memory + */ +#define INNER_SHAREABLE (0x3 << 8) +#define OUTER_SHAREABLE (0x2 << 8) +#define NON_SHAREABLE (~(0x3 << 8)) + +/* Execution type */ +#define EXECUTE_NEVER ((0x1 << 53) | (0x1 << 54)) + +/* Security type */ +#define NON_SECURE (0x1 << 5) + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +void Xil_SetTlbAttributes(UINTPTR Addr, u64 attrib); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XIL_MMU_H */ +/** +* @} End of "addtogroup a53_64_mmu_apis". +*/ \ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_printf.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_printf.c new file mode 100644 index 0000000..dc0897f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_printf.c
@@ -0,0 +1,443 @@ +/*---------------------------------------------------*/ +/* Modified from : */ +/* Public Domain version of printf */ +/* Rud Merriam, Compsult, Inc. Houston, Tx. */ +/* For Embedded Systems Programming, 1991 */ +/* */ +/*---------------------------------------------------*/ +#include "xil_printf.h" +#include "xil_types.h" +#include "xil_assert.h" +#include <ctype.h> +#include <string.h> +#include <stdarg.h> + +static void padding( const s32 l_flag,const struct params_s *par); +static void outs(const charptr lp, struct params_s *par); +static s32 getnum( charptr* linep); + +typedef struct params_s { + s32 len; + s32 num1; + s32 num2; + char8 pad_character; + s32 do_padding; + s32 left_flag; + s32 unsigned_flag; +} params_t; + + +/*---------------------------------------------------*/ +/* The purpose of this routine is to output data the */ +/* same as the standard printf function without the */ +/* overhead most run-time libraries involve. Usually */ +/* the printf brings in many kilobytes of code and */ +/* that is unacceptable in most embedded systems. */ +/*---------------------------------------------------*/ + + +/*---------------------------------------------------*/ +/* */ +/* This routine puts pad characters into the output */ +/* buffer. */ +/* */ +static void padding( const s32 l_flag, const struct params_s *par) +{ + s32 i; + + if ((par->do_padding != 0) && (l_flag != 0) && (par->len < par->num1)) { + i=(par->len); + for (; i<(par->num1); i++) { +#ifdef STDOUT_BASEADDRESS + outbyte( par->pad_character); +#endif + } + } +} + +/*---------------------------------------------------*/ +/* */ +/* This routine moves a string to the output buffer */ +/* as directed by the padding and positioning flags. */ +/* */ +static void outs(const charptr lp, struct params_s *par) +{ + charptr LocalPtr; + LocalPtr = lp; + /* pad on left if needed */ + if(LocalPtr != NULL) { + par->len = (s32)strlen( LocalPtr); + } + padding( !(par->left_flag), par); + + /* Move string to the buffer */ + while (((*LocalPtr) != (char8)0) && ((par->num2) != 0)) { + (par->num2)--; +#ifdef STDOUT_BASEADDRESS + outbyte(*LocalPtr); +#endif + LocalPtr += 1; +} + + /* Pad on right if needed */ + /* CR 439175 - elided next stmt. Seemed bogus. */ + /* par->len = strlen( lp) */ + padding( par->left_flag, par); +} + +/*---------------------------------------------------*/ +/* */ +/* This routine moves a number to the output buffer */ +/* as directed by the padding and positioning flags. */ +/* */ + +static void outnum( const s32 n, const s32 base, struct params_s *par) +{ + s32 negative; + s32 i; + char8 outbuf[32]; + const char8 digits[] = "0123456789ABCDEF"; + u32 num; + for(i = 0; i<32; i++) { + outbuf[i] = '0'; + } + + /* Check if number is negative */ + if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) { + negative = 1; + num =(-(n)); + } + else{ + num = n; + negative = 0; + } + + /* Build number (backwards) in outbuf */ + i = 0; + do { + outbuf[i] = digits[(num % base)]; + i++; + num /= base; + } while (num > 0); + + if (negative != 0) { + outbuf[i] = '-'; + i++; + } + + outbuf[i] = 0; + i--; + + /* Move the converted number to the buffer and */ + /* add in the padding where needed. */ + par->len = (s32)strlen(outbuf); + padding( !(par->left_flag), par); + while (&outbuf[i] >= outbuf) { +#ifdef STDOUT_BASEADDRESS + outbyte( outbuf[i] ); +#endif + i--; +} + padding( par->left_flag, par); +} +/*---------------------------------------------------*/ +/* */ +/* This routine moves a 64-bit number to the output */ +/* buffer as directed by the padding and positioning */ +/* flags. */ +/* */ +#if defined (__aarch64__) +static void outnum1( const s64 n, const s32 base, params_t *par) +{ + s32 negative; + s32 i; + char8 outbuf[64]; + const char8 digits[] = "0123456789ABCDEF"; + u64 num; + for(i = 0; i<64; i++) { + outbuf[i] = '0'; + } + + /* Check if number is negative */ + if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) { + negative = 1; + num =(-(n)); + } + else{ + num = (n); + negative = 0; + } + + /* Build number (backwards) in outbuf */ + i = 0; + do { + outbuf[i] = digits[(num % base)]; + i++; + num /= base; + } while (num > 0); + + if (negative != 0) { + outbuf[i] = '-'; + i++; + } + + outbuf[i] = 0; + i--; + + /* Move the converted number to the buffer and */ + /* add in the padding where needed. */ + par->len = (s32)strlen(outbuf); + padding( !(par->left_flag), par); + while (&outbuf[i] >= outbuf) { + outbyte( outbuf[i] ); + i--; +} + padding( par->left_flag, par); +} +#endif +/*---------------------------------------------------*/ +/* */ +/* This routine gets a number from the format */ +/* string. */ +/* */ +static s32 getnum( charptr* linep) +{ + s32 n; + s32 ResultIsDigit = 0; + charptr cptr; + n = 0; + cptr = *linep; + if(cptr != NULL){ + ResultIsDigit = isdigit(((s32)*cptr)); + } + while (ResultIsDigit != 0) { + if(cptr != NULL){ + n = ((n*10) + (((s32)*cptr) - (s32)'0')); + cptr += 1; + if(cptr != NULL){ + ResultIsDigit = isdigit(((s32)*cptr)); + } + } + ResultIsDigit = isdigit(((s32)*cptr)); + } + *linep = ((charptr )(cptr)); + return(n); +} + +/*---------------------------------------------------*/ +/* */ +/* This routine operates just like a printf/sprintf */ +/* routine. It outputs a set of data under the */ +/* control of a formatting string. Not all of the */ +/* standard C format control are supported. The ones */ +/* provided are primarily those needed for embedded */ +/* systems work. Primarily the floating point */ +/* routines are omitted. Other formats could be */ +/* added easily by following the examples shown for */ +/* the supported formats. */ +/* */ + +/* void esp_printf( const func_ptr f_ptr, + const charptr ctrl1, ...) */ +#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE +void xil_printf( const char8 *ctrl1, ...){ + XPVXenConsole_Printf(ctrl1); +} +#else +void xil_printf( const char8 *ctrl1, ...) +{ + s32 Check; +#if defined (__aarch64__) + s32 long_flag; +#endif + s32 dot_flag; + + params_t par; + + char8 ch; + va_list argp; + char8 *ctrl = (char8 *)ctrl1; + + va_start( argp, ctrl1); + + while ((ctrl != NULL) && (*ctrl != (char8)0)) { + + /* move format string chars to buffer until a */ + /* format control is found. */ + if (*ctrl != '%') { +#ifdef STDOUT_BASEADDRESS + outbyte(*ctrl); +#endif + ctrl += 1; + continue; + } + + /* initialize all the flags for this format. */ + dot_flag = 0; +#if defined (__aarch64__) + long_flag = 0; +#endif + par.unsigned_flag = 0; + par.left_flag = 0; + par.do_padding = 0; + par.pad_character = ' '; + par.num2=32767; + par.num1=0; + par.len=0; + + try_next: + if(ctrl != NULL) { + ctrl += 1; + } + if(ctrl != NULL) { + ch = *ctrl; + } + else { + ch = *ctrl; + } + + if (isdigit((s32)ch) != 0) { + if (dot_flag != 0) { + par.num2 = getnum(&ctrl); + } + else { + if (ch == '0') { + par.pad_character = '0'; + } + if(ctrl != NULL) { + par.num1 = getnum(&ctrl); + } + par.do_padding = 1; + } + if(ctrl != NULL) { + ctrl -= 1; + } + goto try_next; + } + + switch (tolower((s32)ch)) { + case '%': +#ifdef STDOUT_BASEADDRESS + outbyte( '%'); +#endif + Check = 1; + break; + + case '-': + par.left_flag = 1; + Check = 0; + break; + + case '.': + dot_flag = 1; + Check = 0; + break; + + case 'l': + #if defined (__aarch64__) + long_flag = 1; + #endif + Check = 0; + break; + + case 'u': + par.unsigned_flag = 1; + /* fall through */ + case 'i': + case 'd': + #if defined (__aarch64__) + if (long_flag != 0){ + outnum1((s64)va_arg(argp, s64), 10L, &par); + } + else { + outnum( va_arg(argp, s32), 10L, &par); + } + #else + outnum( va_arg(argp, s32), 10L, &par); + #endif + Check = 1; + break; + case 'p': + #if defined (__aarch64__) + par.unsigned_flag = 1; + outnum1((s64)va_arg(argp, s64), 16L, &par); + Check = 1; + break; + #endif + case 'X': + case 'x': + par.unsigned_flag = 1; + #if defined (__aarch64__) + if (long_flag != 0) { + outnum1((s64)va_arg(argp, s64), 16L, &par); + } + else { + outnum((s32)va_arg(argp, s32), 16L, &par); + } + #else + outnum((s32)va_arg(argp, s32), 16L, &par); + #endif + Check = 1; + break; + + case 's': + outs( va_arg( argp, char *), &par); + Check = 1; + break; + + case 'c': +#ifdef STDOUT_BASEADDRESS + outbyte( va_arg( argp, s32)); +#endif + Check = 1; + break; + + case '\\': + switch (*ctrl) { + case 'a': +#ifdef STDOUT_BASEADDRESS + outbyte( ((char8)0x07)); +#endif + break; + case 'h': +#ifdef STDOUT_BASEADDRESS + outbyte( ((char8)0x08)); +#endif + break; + case 'r': +#ifdef STDOUT_BASEADDRESS + outbyte( ((char8)0x0D)); +#endif + break; + case 'n': +#ifdef STDOUT_BASEADDRESS + outbyte( ((char8)0x0D)); + outbyte( ((char8)0x0A)); +#endif + break; + default: +#ifdef STDOUT_BASEADDRESS + outbyte( *ctrl); +#endif + break; + } + ctrl += 1; + Check = 0; + break; + + default: + Check = 1; + break; + } + if(Check == 1) { + if(ctrl != NULL) { + ctrl += 1; + } + continue; + } + goto try_next; + } + va_end( argp); +} +#endif +/*---------------------------------------------------*/
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_printf.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_printf.h new file mode 100644 index 0000000..016ae3b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_printf.h
@@ -0,0 +1,48 @@ + #ifndef XIL_PRINTF_H + #define XIL_PRINTF_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include <ctype.h> +#include <string.h> +#include <stdarg.h> +#include "xil_types.h" +#include "xparameters.h" +#include "bspconfig.h" +#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE +#include "xen_console.h" +#endif + +/*----------------------------------------------------*/ +/* Use the following parameter passing structure to */ +/* make xil_printf re-entrant. */ +/*----------------------------------------------------*/ + +struct params_s; + + +/*---------------------------------------------------*/ +/* The purpose of this routine is to output data the */ +/* same as the standard printf function without the */ +/* overhead most run-time libraries involve. Usually */ +/* the printf brings in many kilobytes of code and */ +/* that is unacceptable in most embedded systems. */ +/*---------------------------------------------------*/ + +typedef char8* charptr; +typedef s32 (*func_ptr)(int c); + +/* */ + +void xil_printf( const char8 *ctrl1, ...); +void print( const char8 *ptr); +extern void outbyte (char8 c); +extern char8 inbyte(void); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_sleepcommon.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_sleepcommon.c new file mode 100644 index 0000000..972a310 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_sleepcommon.c
@@ -0,0 +1,106 @@ +/****************************************************************************** +* +* Copyright (C) 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +*@file xil_sleepcommon.c +* +* This file contains the sleep API's +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- -------- -------- ----------------------------------------------- +* 6.6 srm 11/02/17 First release +* </pre> +******************************************************************************/ + + +/***************************** Include Files *********************************/ +#include "xil_io.h" +#include "sleep.h" + +/**************************** Constant Definitions *************************/ + + +/*****************************************************************************/ +/** +* +* This API gives delay in sec +* +* @param seconds - delay time in seconds +* +* @return none +* +* @note none +* +*****************************************************************************/ + void sleep(unsigned int seconds) + { +#if defined (ARMR5) + sleep_R5(seconds); +#elif defined (__aarch64__) || defined (ARMA53_32) + sleep_A53(seconds); +#elif defined (__MICROBLAZE__) + sleep_MB(seconds); +#else + sleep_A9(seconds); +#endif + + } + +/****************************************************************************/ +/** +* +* This API gives delay in usec +* +* @param useconds - delay time in useconds +* +* @return none +* +* @note none +* +*****************************************************************************/ + void usleep(unsigned long useconds) + { +#if defined (ARMR5) + usleep_R5(useconds); +#elif defined (__aarch64__) || defined (ARMA53_32) + usleep_A53(useconds); +#elif defined (__MICROBLAZE__) + usleep_MB(useconds); +#else + usleep_A9(useconds); +#endif + + }
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_sleeptimer.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_sleeptimer.c new file mode 100644 index 0000000..4772606 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_sleeptimer.c
@@ -0,0 +1,161 @@ +/****************************************************************************** +* +* Copyright (C) 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_sleeptimer.c +* +* This file provides the common helper routines for the sleep API's +* +* <pre> +* MODIFICATION HISTORY : +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 6.6 srm 10/18/17 First Release. +* +* </pre> +*****************************************************************************/ + +/**************************** Include Files ********************************/ + +#include "xil_io.h" +#include "xil_sleeptimer.h" +#include "xtime_l.h" + +/**************************** Constant Definitions *************************/ + + +/* Function definitions are applicable only when TTC3 is present*/ +#if defined (SLEEP_TIMER_BASEADDR) +/****************************************************************************/ +/** +* +* This is a helper function used by sleep/usleep APIs to +* have delay in sec/usec +* +* @param delay - delay time in seconds/micro seconds +* +* @param frequency - Number of counts per second/micro second +* +* @return none +* +* @note none +* +*****************************************************************************/ +void Xil_SleepTTCCommon(u32 delay, u64 frequency) +{ + INTPTR tEnd = 0U; + INTPTR tCur = 0U; + XCntrVal TimeHighVal = 0U; + XCntrVal TimeLowVal1 = 0U; + XCntrVal TimeLowVal2 = 0U; + + TimeLowVal1 = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR + + XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET); + tEnd = (INTPTR)TimeLowVal1 + ((INTPTR)(delay) * frequency); + do + { + TimeLowVal2 = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR + + XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET); + if (TimeLowVal2 < TimeLowVal1) { + TimeHighVal++; + } + TimeLowVal1 = TimeLowVal2; + tCur = (((INTPTR) TimeHighVal) << XSLEEP_TIMER_REG_SHIFT) | + (INTPTR)TimeLowVal2; + }while (tCur < tEnd); +} + + +/*****************************************************************************/ +/** +* +* This API starts the Triple Timer Counter +* +* @param none +* +* @return none +* +* @note none +* +*****************************************************************************/ +void XTime_StartTTCTimer() +{ + u32 TimerPrescalar; + u32 TimerCntrl; + +#if (defined (__aarch64__) && EL3==1) || defined (ARMR5) || defined (ARMA53_32) + u32 LpdRst; + + LpdRst = XSleep_ReadCounterVal(RST_LPD_IOU2); + + /* check if the timer is reset */ + if (((LpdRst & (RST_LPD_IOU2_TTC_BASE_RESET_MASK << + XSLEEP_TTC_INSTANCE)) != 0 )) { + LpdRst = LpdRst & (~(RST_LPD_IOU2_TTC_BASE_RESET_MASK << + XSLEEP_TTC_INSTANCE)); + Xil_Out32(RST_LPD_IOU2, LpdRst); + } else { +#endif + TimerCntrl = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR + + XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET); + /* check if Timer is disabled */ + if ((TimerCntrl & XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK) == 0) { + TimerPrescalar = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR + + XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET); + /* check if Timer is configured with proper functionalty for sleep */ + if ((TimerPrescalar & XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK) == 0) + return; + } +#if (defined (__aarch64__) && EL3==1) || defined (ARMR5) || defined (ARMA53_32) + } +#endif + /* Disable the timer to configure */ + TimerCntrl = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR + + XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET); + TimerCntrl = TimerCntrl | XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK; + Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET, + TimerCntrl); + /* Disable the prescalar */ + TimerPrescalar = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR + + XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET); + TimerPrescalar = TimerPrescalar & (~XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK); + Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET, + TimerPrescalar); + /* Enable the Timer */ + TimerCntrl = TimerCntrl & (~XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK); + Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET, + TimerCntrl); +} +#endif
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_sleeptimer.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_sleeptimer.h new file mode 100644 index 0000000..4bfac0a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_sleeptimer.h
@@ -0,0 +1,116 @@ +/****************************************************************************** +* +* Copyright (C) 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_sleeptimer.h +* +* This header file contains ARM Cortex A53,A9,R5 specific sleep related APIs. +* For sleep related functions that can be used across all Xilinx supported +* processors, please use xil_sleeptimer.h. +* +* +* <pre> +* MODIFICATION HISTORY : +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 6.6 srm 10/18/17 First Release. +* +* </pre> +*****************************************************************************/ + +#ifndef XIL_SLEEPTIMER_H /* prevent circular inclusions */ +#define XIL_SLEEPTIMER_H /* by using protection macros */ +/**************************** Include Files ********************************/ + +#include "xil_io.h" +#include "xparameters.h" +#include "bspconfig.h" + +/************************** Constant Definitions *****************************/ + +#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) +#define XSLEEP_TIMER_REG_SHIFT 32U +#define XSleep_ReadCounterVal Xil_In32 +#define XCntrVal u32 +#else +#define XSLEEP_TIMER_REG_SHIFT 16U +#define XSleep_ReadCounterVal Xil_In16 +#define XCntrVal u16 +#endif + +#if defined(ARMR5) || (defined (__aarch64__) && EL3==1) || defined (ARMA53_32) +#define RST_LPD_IOU2 0xFF5E0238U +#define RST_LPD_IOU2_TTC_BASE_RESET_MASK 0x00000800U +#endif + +#if defined (SLEEP_TIMER_BASEADDR) +/** @name Register Map +* +* Register offsets from the base address of the TTC device +* +* @{ +*/ + #define XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET 0x00000000U + /**< Clock Control Register */ + #define XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET 0x0000000CU + /**< Counter Control Register*/ + #define XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET 0x00000018U + /**< Current Counter Value */ +/* @} */ +/** @name Clock Control Register +* Clock Control Register definitions of TTC +* @{ +*/ + #define XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK 0x00000001U + /**< Prescale enable */ +/* @} */ +/** @name Counter Control Register +* Counter Control Register definitions of TTC +* @{ +*/ +#define XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK 0x00000001U + /**< Disable the counter */ +#define XSLEEP_TIMER_TTC_CNT_CNTRL_RST_MASK 0x00000010U + /**< Reset counter */ +/* @} */ + +/**************************** Type Definitions *******************************/ + +/************************** Function Prototypes ******************************/ + +void Xil_SleepTTCCommon(u32 delay, u64 frequency); +void XTime_StartTTCTimer(); + +#endif +#endif /* XIL_SLEEPTIMER_H */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_smc.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_smc.c new file mode 100644 index 0000000..7d9ee9b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_smc.c
@@ -0,0 +1,110 @@ +/****************************************************************************** +* +* Copyright (C) 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xil_smc.c +* +* This file contains function for initiating SMC call +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- -------- -------- ----------------------------------------------- +* 6.2 pkp 02/16/17 First release +* </pre> +* +*****************************************************************************/ + +/***************************** Include Files ********************************/ +#include "xil_types.h" +#include "xil_smc.h" + +#if EL1_NONSECURE +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/************************** Function Prototypes *****************************/ + +/************************** Variable Definitions *****************************/ +XSmc_OutVar SmcResult; + +/*****************************************************************************/ +/** +* @brief Initiate SMC call to EL3 secure monitor to request for secure +* service. This function is only applicable for EL1 Non-secure bsp. +* +* @param FunctionID is the SMC identifier for a particular secure service +* request +* @param Arg1 to Arg6 is the arguements passed to EL3 secure monitor +* @param Arg7 is Hypervisor Client ID register +* +* @return Result from secure payload service +* @note FunctionID and Arg1-Arg7 should be as per SMC calling convention +* +******************************************************************************/ +XSmc_OutVar Xil_Smc(u64 FunctionID, u64 Arg1, u64 Arg2, u64 Arg3, u64 Arg4, + u64 Arg5, u64 Arg6, u64 Arg7){ + + /* + * Since registers x8 to x17 are not saved by secure monitor during SMC + * it must be preserved. + */ + XSave_X8toX17(); + + /* Moving to EL3 secure monitor with smc call. */ + + __asm__ __volatile__ ("smc #0x0"); + + /* + * The result of the secure services are stored in x0 - x3. They are + * moved to SmcResult to return the result. + */ + __asm__ __volatile__("mov x8, x0"); + __asm__ __volatile__("mov x9, x1"); + __asm__ __volatile__("mov x10, x2"); + __asm__ __volatile__("mov x11, x3"); + + __asm__ __volatile__("mov %0, x8" : "=r" (SmcResult.Arg0)); + __asm__ __volatile__("mov %0, x9" : "=r" (SmcResult.Arg1)); + __asm__ __volatile__("mov %0, x10" : "=r" (SmcResult.Arg2)); + __asm__ __volatile__("mov %0, x11" : "=r" (SmcResult.Arg3)); + + XRestore_X8toX17(); + + return SmcResult; +} +#endif \ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_smc.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_smc.h new file mode 100644 index 0000000..4f0738c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_smc.h
@@ -0,0 +1,118 @@ +/****************************************************************************** +* +* Copyright (C) 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_smc.h +* +* @addtogroup a53_64_smc_api Cortex A53 64bit EL1 Non-secure SMC Call +* +* Cortex A53 64bit EL1 Non-secure SMC Call provides a C wrapper for calling +* SMC from EL1 Non-secure application to request Secure monitor for secure +* services. SMC calling conventions should be followed. +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- -------- -------- ----------------------------------------------- +* 6.2 pkp 02/16/17 First release +* 6.4 mus 08/17/17 Added constant define for SMC ID , which is +* intended to read the version/idcode of the +* platform +* +* +* </pre> +* +******************************************************************************/ + +#ifndef XIL_SMC_H /* prevent circular inclusions */ +#define XIL_SMC_H /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "bspconfig.h" + +#ifdef __cplusplus +extern "C" { +#endif +#if EL1_NONSECURE +/************************** Constant Definitions ****************************/ +#define SMC_FID_START 0xF2000000 +#define SMC_FID_END 0xFF00FFFF + +#define XILSP_INIT_DONE 0xF2000000 +#define ARITH_SMC_FID 0xF2000001 + +#define PM_ASSERT_SMC_FID 0xC2000011 +#define PM_GETSTATUS_SMC_FID 0xC2000012 +#define MMIO_WRITE_SMC_FID 0xC2000013 +#define MMIO_READ_SMC_FID 0xC2000014 +#define GET_CHIPID_SMC_FID 0xC2000018 +/**************************** Type Definitions ******************************/ +typedef struct { + u64 Arg0; + u64 Arg1; + u64 Arg2; + u64 Arg3; +} XSmc_OutVar; +/***************** Macros (Inline Functions) Definitions ********************/ + +#define XSave_X8toX17() \ + __asm__ __volatile__ ("stp X8, X9, [sp,#-0x10]!");\ + __asm__ __volatile__ ("stp X10, X11, [sp,#-0x10]!");\ + __asm__ __volatile__ ("stp X12, X13, [sp,#-0x10]!");\ + __asm__ __volatile__ ("stp X14, X15, [sp,#-0x10]!");\ + __asm__ __volatile__ ("stp X16, X17, [sp,#-0x10]!"); + +#define XRestore_X8toX17() \ + __asm__ __volatile__ ("ldp X16, X17, [sp], #0x10");\ + __asm__ __volatile__ ("ldp X14, X15, [sp], #0x10");\ + __asm__ __volatile__ ("ldp X12, X13, [sp], #0x10");\ + __asm__ __volatile__ ("ldp X10, X11, [sp], #0x10");\ + __asm__ __volatile__ ("ldp X8, X9, [sp], #0x10"); + +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ +XSmc_OutVar Xil_Smc(u64 FunctionID, u64 Arg1, u64 Arg2, u64 Arg3, u64 Arg4, + u64 Arg5, u64 Arg6, u64 Arg7); +#endif +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XIL_SMC_H */ +/** +* @} End of "addtogroup a53_64_smc_api". +*/
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_testcache.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_testcache.c new file mode 100644 index 0000000..157ad08 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_testcache.c
@@ -0,0 +1,371 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_testcache.c +* +* Contains utility functions to test cache. +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 1.00a hbm 07/28/09 Initial release +* 4.1 asa 05/09/14 Ensured that the address uses for cache test is aligned +* cache line. +* </pre> +* +* @note +* This file contain functions that all operate on HAL. +* +******************************************************************************/ +#ifdef __ARM__ +#include "xil_cache.h" +#include "xil_testcache.h" +#include "xil_types.h" +#include "xpseudo_asm.h" +#ifdef __aarch64__ +#include "xreg_cortexa53.h" +#else +#include "xreg_cortexr5.h" +#endif + +#include "xil_types.h" + +extern void xil_printf(const char8 *ctrl1, ...); + +#define DATA_LENGTH 128 + +#ifdef __aarch64__ +static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(64))); +#else +static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(32))); +#endif + + +/*****************************************************************************/ +/** +* +* @brief Perform DCache range related API test such as Xil_DCacheFlushRange +* and Xil_DCacheInvalidateRange. This test function writes a constant +* value to the Data array, flushes the range, writes a new value, then +* invalidates the corresponding range. +* @param None +* +* @return +* - -1 is returned for a failure +* - 0 is returned for a pass +* +*****************************************************************************/ +s32 Xil_TestDCacheRange(void) +{ + s32 Index; + s32 Status = 0; + u32 CtrlReg; + INTPTR Value; + + xil_printf("-- Cache Range Test --\n\r"); + + for (Index = 0; Index < DATA_LENGTH; Index++) + Data[Index] = 0xA0A00505; + + xil_printf(" initialize Data done:\r\n"); + + Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR)); + + xil_printf(" flush range done\r\n"); + + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); + + Status = 0; + + for (Index = 0; Index < DATA_LENGTH; Index++) { + Value = Data[Index]; + if (Value != 0xA0A00505) { + Status = -1; + xil_printf("Data[%d] = %x\r\n", Index, Value); + break; + } + } + + if (!Status) { + xil_printf(" Flush worked\r\n"); + } + else { + xil_printf("Error: flush dcache range not working\r\n"); + } + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg |= (XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg |= (XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); + for (Index = 0; Index < DATA_LENGTH; Index++) + Data[Index] = 0xA0A0C505; + + + + Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR)); + + for (Index = 0; Index < DATA_LENGTH; Index++) + Data[Index] = Index + 3; + + Xil_DCacheInvalidateRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR)); + + xil_printf(" invalidate dcache range done\r\n"); + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); + for (Index = 0; Index < DATA_LENGTH; Index++) + Data[Index] = 0xA0A0A05; + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg |= (XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg |= (XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); + + Status = 0; + + for (Index = 0; Index < DATA_LENGTH; Index++) { + Value = Data[Index]; + if (Value != 0xA0A0A05) { + Status = -1; + xil_printf("Data[%d] = %x\r\n", Index, Value); + break; + } + } + + + if (!Status) { + xil_printf(" Invalidate worked\r\n"); + } + else { + xil_printf("Error: Invalidate dcache range not working\r\n"); + } + xil_printf("-- Cache Range Test Complete --\r\n"); + return Status; + +} + +/*****************************************************************************/ +/** +* @brief Perform DCache all related API test such as Xil_DCacheFlush and +* Xil_DCacheInvalidate. This test function writes a constant value +* to the Data array, flushes the DCache, writes a new value, +* then invalidates the DCache. +* +* @return +* - 0 is returned for a pass +* - -1 is returned for a failure +*****************************************************************************/ +s32 Xil_TestDCacheAll(void) +{ + s32 Index; + s32 Status; + INTPTR Value; + u32 CtrlReg; + + xil_printf("-- Cache All Test --\n\r"); + + for (Index = 0; Index < DATA_LENGTH; Index++) + Data[Index] = 0x50500A0A; + xil_printf(" initialize Data done:\r\n"); + + Xil_DCacheFlush(); + xil_printf(" flush all done\r\n"); + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); + Status = 0; + + for (Index = 0; Index < DATA_LENGTH; Index++) { + Value = Data[Index]; + + if (Value != 0x50500A0A) { + Status = -1; + xil_printf("Data[%d] = %x\r\n", Index, Value); + break; + } + } + + if (!Status) { + xil_printf(" Flush all worked\r\n"); + } + else { + xil_printf("Error: Flush dcache all not working\r\n"); + } + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg |= (XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg |= (XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); + for (Index = 0; Index < DATA_LENGTH; Index++) + Data[Index] = 0x505FFA0A; + + Xil_DCacheFlush(); + + + for (Index = 0; Index < DATA_LENGTH; Index++) + Data[Index] = Index + 3; + + Xil_DCacheInvalidate(); + + xil_printf(" invalidate all done\r\n"); + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); + for (Index = 0; Index < DATA_LENGTH; Index++) + Data[Index] = 0x50CFA0A; + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg |= (XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg |= (XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); + Status = 0; + + for (Index = 0; Index < DATA_LENGTH; Index++) { + Value = Data[Index]; + if (Value != 0x50CFA0A) { + Status = -1; + xil_printf("Data[%d] = %x\r\n", Index, Value); + break; + } + } + + if (!Status) { + xil_printf(" Invalidate all worked\r\n"); + } + else { + xil_printf("Error: Invalidate dcache all not working\r\n"); + } + + xil_printf("-- DCache all Test Complete --\n\r"); + + return Status; +} + +/*****************************************************************************/ +/** +* @brief Perform Xil_ICacheInvalidateRange() on a few function pointers. +* +* @return +* - 0 is returned for a pass +* @note +* The function will hang if it fails. +*****************************************************************************/ +s32 Xil_TestICacheRange(void) +{ + + Xil_ICacheInvalidateRange((INTPTR)Xil_TestICacheRange, 1024); + Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheRange, 1024); + Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheAll, 1024); + + xil_printf("-- Invalidate icache range done --\r\n"); + + return 0; +} + +/*****************************************************************************/ +/** +* @brief Perform Xil_ICacheInvalidate() on a few function pointers. +* +* @return +* - 0 is returned for a pass +* @note +* The function will hang if it fails. +*****************************************************************************/ +s32 Xil_TestICacheAll(void) +{ + Xil_ICacheInvalidate(); + xil_printf("-- Invalidate icache all done --\r\n"); + return 0; +} +#endif
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_testcache.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_testcache.h new file mode 100644 index 0000000..c35e9a4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_testcache.h
@@ -0,0 +1,71 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_testcache.h +* +* @addtogroup common_test_utils +* <h2>Cache test </h2> +* The xil_testcache.h file contains utility functions to test cache. +* +* @{ +* <pre> +* Ver Who Date Changes +* ----- ---- -------- ----------------------------------------------- +* 1.00a hbm 07/29/09 First release +* </pre> +* +******************************************************************************/ + +#ifndef XIL_TESTCACHE_H /* prevent circular inclusions */ +#define XIL_TESTCACHE_H /* by using protection macros */ + +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +extern s32 Xil_TestDCacheRange(void); +extern s32 Xil_TestDCacheAll(void); +extern s32 Xil_TestICacheRange(void); +extern s32 Xil_TestICacheAll(void); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** +* @} End of "addtogroup common_test_utils". +*/ \ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_testio.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_testio.c new file mode 100644 index 0000000..e6a3680 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_testio.c
@@ -0,0 +1,299 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_testio.c +* +* Contains the memory test utility functions. +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ----------------------------------------------- +* 1.00a hbm 08/25/09 First release +* </pre> +* +*****************************************************************************/ + +/***************************** Include Files ********************************/ +#include "xil_testio.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions ****************************/ +/************************** Function Prototypes *****************************/ + + + +/** + * + * Endian swap a 16-bit word. + * @param Data is the 16-bit word to be swapped. + * @return The endian swapped value. + * + */ +static u16 Swap16(u16 Data) +{ + return ((Data >> 8U) & 0x00FFU) | ((Data << 8U) & 0xFF00U); +} + +/** + * + * Endian swap a 32-bit word. + * @param Data is the 32-bit word to be swapped. + * @return The endian swapped value. + * + */ +static u32 Swap32(u32 Data) +{ + u16 Lo16; + u16 Hi16; + + u16 Swap16Lo; + u16 Swap16Hi; + + Hi16 = (u16)((Data >> 16U) & 0x0000FFFFU); + Lo16 = (u16)(Data & 0x0000FFFFU); + + Swap16Lo = Swap16(Lo16); + Swap16Hi = Swap16(Hi16); + + return (((u32)(Swap16Lo)) << 16U) | ((u32)Swap16Hi); +} + +/*****************************************************************************/ +/** +* +* @brief Perform a destructive 8-bit wide register IO test where the +* register is accessed using Xil_Out8 and Xil_In8, and comparing +* the written values by reading them back. +* +* @param Addr: a pointer to the region of memory to be tested. +* @param Length: Length of the block. +* @param Value: constant used for writting the memory. +* +* @return +* - -1 is returned for a failure +* - 0 is returned for a pass +* +*****************************************************************************/ + +s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value) +{ + u8 ValueIn; + s32 Index; + s32 Status = 0; + + for (Index = 0; Index < Length; Index++) { + Xil_Out8((INTPTR)Addr, Value); + + ValueIn = Xil_In8((INTPTR)Addr); + + if ((Value != ValueIn) && (Status == 0)) { + Status = -1; + break; + } + } + return Status; + +} + +/*****************************************************************************/ +/** +* +* @brief Perform a destructive 16-bit wide register IO test. Each location +* is tested by sequentially writing a 16-bit wide register, reading +* the register, and comparing value. This function tests three kinds +* of register IO functions, normal register IO, little-endian register +* IO, and big-endian register IO. When testing little/big-endian IO, +* the function performs the following sequence, Xil_Out16LE/Xil_Out16BE, +* Xil_In16, Compare In-Out values, Xil_Out16, Xil_In16LE/Xil_In16BE, +* Compare In-Out values. Whether to swap the read-in value before +* comparing is controlled by the 5th argument. +* +* @param Addr: a pointer to the region of memory to be tested. +* @param Length: Length of the block. +* @param Value: constant used for writting the memory. +* @param Kind: Type of test. Acceptable values are: +* XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE. +* @param Swap: indicates whether to byte swap the read-in value. +* +* @return +* - -1 is returned for a failure +* - 0 is returned for a pass +* +*****************************************************************************/ + +s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap) +{ + u16 *TempAddr16; + u16 ValueIn = 0U; + s32 Index; + TempAddr16 = Addr; + Xil_AssertNonvoid(TempAddr16 != NULL); + + for (Index = 0; Index < Length; Index++) { + switch (Kind) { + case XIL_TESTIO_LE: + Xil_Out16LE((INTPTR)TempAddr16, Value); + break; + case XIL_TESTIO_BE: + Xil_Out16BE((INTPTR)TempAddr16, Value); + break; + default: + Xil_Out16((INTPTR)TempAddr16, Value); + break; + } + + ValueIn = Xil_In16((INTPTR)TempAddr16); + + if ((Kind != 0) && (Swap != 0)) { + ValueIn = Swap16(ValueIn); + } + + if (Value != ValueIn) { + return -1; + } + + /* second round */ + Xil_Out16((INTPTR)TempAddr16, Value); + + switch (Kind) { + case XIL_TESTIO_LE: + ValueIn = Xil_In16LE((INTPTR)TempAddr16); + break; + case XIL_TESTIO_BE: + ValueIn = Xil_In16BE((INTPTR)TempAddr16); + break; + default: + ValueIn = Xil_In16((INTPTR)TempAddr16); + break; + } + + + if ((Kind != 0) && (Swap != 0)) { + ValueIn = Swap16(ValueIn); + } + + if (Value != ValueIn) { + return -1; + } + TempAddr16 += sizeof(u16); + } + return 0; +} + + +/*****************************************************************************/ +/** +* +* @brief Perform a destructive 32-bit wide register IO test. Each location +* is tested by sequentially writing a 32-bit wide regsiter, reading +* the register, and comparing value. This function tests three kinds +* of register IO functions, normal register IO, little-endian register IO, +* and big-endian register IO. When testing little/big-endian IO, +* the function perform the following sequence, Xil_Out32LE/ +* Xil_Out32BE, Xil_In32, Compare, Xil_Out32, Xil_In32LE/Xil_In32BE, Compare. +* Whether to swap the read-in value *before comparing is controlled +* by the 5th argument. +* @param Addr: a pointer to the region of memory to be tested. +* @param Length: Length of the block. +* @param Value: constant used for writting the memory. +* @param Kind: type of test. Acceptable values are: +* XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE. +* @param Swap: indicates whether to byte swap the read-in value. +* +* @return +* - -1 is returned for a failure +* - 0 is returned for a pass +* +*****************************************************************************/ +s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap) +{ + u32 *TempAddr; + u32 ValueIn = 0U; + s32 Index; + TempAddr = Addr; + Xil_AssertNonvoid(TempAddr != NULL); + + for (Index = 0; Index < Length; Index++) { + switch (Kind) { + case XIL_TESTIO_LE: + Xil_Out32LE((INTPTR)TempAddr, Value); + break; + case XIL_TESTIO_BE: + Xil_Out32BE((INTPTR)TempAddr, Value); + break; + default: + Xil_Out32((INTPTR)TempAddr, Value); + break; + } + + ValueIn = Xil_In32((INTPTR)TempAddr); + + if ((Kind != 0) && (Swap != 0)) { + ValueIn = Swap32(ValueIn); + } + + if (Value != ValueIn) { + return -1; + } + + /* second round */ + Xil_Out32((INTPTR)TempAddr, Value); + + + switch (Kind) { + case XIL_TESTIO_LE: + ValueIn = Xil_In32LE((INTPTR)TempAddr); + break; + case XIL_TESTIO_BE: + ValueIn = Xil_In32BE((INTPTR)TempAddr); + break; + default: + ValueIn = Xil_In32((INTPTR)TempAddr); + break; + } + + if ((Kind != 0) && (Swap != 0)) { + ValueIn = Swap32(ValueIn); + } + + if (Value != ValueIn) { + return -1; + } + TempAddr += sizeof(u32); + } + return 0; +}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_testio.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_testio.h new file mode 100644 index 0000000..ad68ead --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_testio.h
@@ -0,0 +1,94 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_testio.h +* +* @addtogroup common_test_utils Test Utilities +* <h2>I/O test </h2> +* The xil_testio.h file contains utility functions to test endian related memory +* IO functions. +* +* A subset of the memory tests can be selected or all of the tests can be run +* in order. If there is an error detected by a subtest, the test stops and the +* failure code is returned. Further tests are not run even if all of the tests +* are selected. +* +* @{ +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ----------------------------------------------- +* 1.00 hbm 08/05/09 First release +* </pre> +* +******************************************************************************/ + +#ifndef XIL_TESTIO_H /* prevent circular inclusions */ +#define XIL_TESTIO_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xil_types.h" + +/************************** Constant Definitions *****************************/ + + +#define XIL_TESTIO_DEFAULT 0 +#define XIL_TESTIO_LE 1 +#define XIL_TESTIO_BE 2 + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +extern s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value); +extern s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap); +extern s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** +* @} End of "addtogroup common_test_utils". +*/
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_testmem.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_testmem.c new file mode 100644 index 0000000..87426d1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_testmem.c
@@ -0,0 +1,868 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_testmem.c +* +* Contains the memory test utility functions. +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ----------------------------------------------- +* 1.00a hbm 08/25/09 First release +* </pre> +* +*****************************************************************************/ + +/***************************** Include Files ********************************/ +#include "xil_testmem.h" +#include "xil_io.h" +#include "xil_assert.h" + +/************************** Constant Definitions ****************************/ +/************************** Function Prototypes *****************************/ + +static u32 RotateLeft(u32 Input, u8 Width); + +/* define ROTATE_RIGHT to give access to this functionality */ +/* #define ROTATE_RIGHT */ +#ifdef ROTATE_RIGHT +static u32 RotateRight(u32 Input, u8 Width); +#endif /* ROTATE_RIGHT */ + + +/*****************************************************************************/ +/** +* +* @brief Perform a destructive 32-bit wide memory test. +* +* @param Addr: pointer to the region of memory to be tested. +* @param Words: length of the block. +* @param Pattern: constant used for the constant pattern test, if 0, +* 0xDEADBEEF is used. +* @param Subtest: test type selected. See xil_testmem.h for possible +* values. +* +* @return +* - 0 is returned for a pass +* - 1 is returned for a failure +* +* @note +* Used for spaces where the address range of the region is smaller than +* the data width. If the memory range is greater than 2 ** Width, +* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will +* repeat on a boundry of a power of two making it more difficult to detect +* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR +* tests suffer the same problem. Ideally, if large blocks of memory are to be +* tested, break them up into smaller regions of memory to allow the test +* patterns used not to repeat over the region tested. +* +*****************************************************************************/ +s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest) +{ + u32 I; + u32 j; + u32 Val; + u32 FirtVal; + u32 WordMem32; + s32 Status = 0; + + Xil_AssertNonvoid(Words != (u32)0); + Xil_AssertNonvoid(Subtest <= (u8)XIL_TESTMEM_MAXTEST); + Xil_AssertNonvoid(Addr != NULL); + + /* + * variable initialization + */ + Val = XIL_TESTMEM_INIT_VALUE; + FirtVal = XIL_TESTMEM_INIT_VALUE; + + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { + /* + * Fill the memory with incrementing + * values starting from 'FirtVal' + */ + for (I = 0U; I < Words; I++) { + *(Addr+I) = Val; + Val++; + } + + /* + * Restore the reference 'Val' to the + * initial value + */ + Val = FirtVal; + + /* + * Check every word within the words + * of tested memory and compare it + * with the incrementing reference + * Val + */ + + for (I = 0U; I < Words; I++) { + WordMem32 = *(Addr+I); + + if (WordMem32 != Val) { + Status = -1; + goto End_Label; + } + + Val++; + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { + /* + * set up to cycle through all possible initial + * test Patterns for walking ones test + */ + + for (j = 0U; j < (u32)32; j++) { + /* + * Generate an initial value for walking ones test + * to test for bad data bits + */ + + Val = (1U << j); + + /* + * START walking ones test + * Write a one to each data bit indifferent locations + */ + + for (I = 0U; I < (u32)32; I++) { + /* write memory location */ + *(Addr+I) = Val; + Val = (u32) RotateLeft(Val, 32U); + } + + /* + * Restore the reference 'val' to the + * initial value + */ + Val = 1U << j; + + /* Read the values from each location that was + * written */ + for (I = 0U; I < (u32)32; I++) { + /* read memory location */ + + WordMem32 = *(Addr+I); + + if (WordMem32 != Val) { + Status = -1; + goto End_Label; + } + + Val = (u32)RotateLeft(Val, 32U); + } + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { + /* + * set up to cycle through all possible + * initial test Patterns for walking zeros test + */ + + for (j = 0U; j < (u32)32; j++) { + + /* + * Generate an initial value for walking ones test + * to test for bad data bits + */ + + Val = ~(1U << j); + + /* + * START walking zeros test + * Write a one to each data bit indifferent locations + */ + + for (I = 0U; I < (u32)32; I++) { + /* write memory location */ + *(Addr+I) = Val; + Val = ~((u32)RotateLeft(~Val, 32U)); + } + + /* + * Restore the reference 'Val' to the + * initial value + */ + + Val = ~(1U << j); + + /* Read the values from each location that was + * written */ + for (I = 0U; I < (u32)32; I++) { + /* read memory location */ + WordMem32 = *(Addr+I); + if (WordMem32 != Val) { + Status = -1; + goto End_Label; + } + Val = ~((u32)RotateLeft(~Val, 32U)); + } + + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { + /* Fill the memory with inverse of address */ + for (I = 0U; I < Words; I++) { + /* write memory location */ + Val = (u32) (~((INTPTR) (&Addr[I]))); + *(Addr+I) = Val; + } + + /* + * Check every word within the words + * of tested memory + */ + + for (I = 0U; I < Words; I++) { + /* Read the location */ + WordMem32 = *(Addr+I); + Val = (u32) (~((INTPTR) (&Addr[I]))); + + if ((WordMem32 ^ Val) != 0x00000000U) { + Status = -1; + goto End_Label; + } + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { + /* + * Generate an initial value for + * memory testing + */ + + if (Pattern == (u32)0) { + Val = 0xDEADBEEFU; + } + else { + Val = Pattern; + } + + /* + * Fill the memory with fixed Pattern + */ + + for (I = 0U; I < Words; I++) { + /* write memory location */ + *(Addr+I) = Val; + } + + /* + * Check every word within the words + * of tested memory and compare it + * with the fixed Pattern + */ + + for (I = 0U; I < Words; I++) { + + /* read memory location */ + + WordMem32 = *(Addr+I); + if (WordMem32 != Val) { + Status = -1; + goto End_Label; + } + } + } + +End_Label: + return Status; +} + +/*****************************************************************************/ +/** +* +* @brief Perform a destructive 16-bit wide memory test. +* +* @param Addr: pointer to the region of memory to be tested. +* @param Words: length of the block. +* @param Pattern: constant used for the constant Pattern test, if 0, +* 0xDEADBEEF is used. +* @param Subtest: type of test selected. See xil_testmem.h for possible +* values. +* +* @return +* +* - -1 is returned for a failure +* - 0 is returned for a pass +* +* @note +* Used for spaces where the address range of the region is smaller than +* the data width. If the memory range is greater than 2 ** Width, +* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will +* repeat on a boundry of a power of two making it more difficult to detect +* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR +* tests suffer the same problem. Ideally, if large blocks of memory are to be +* tested, break them up into smaller regions of memory to allow the test +* patterns used not to repeat over the region tested. +* +*****************************************************************************/ +s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest) +{ + u32 I; + u32 j; + u16 Val; + u16 FirtVal; + u16 WordMem16; + s32 Status = 0; + + Xil_AssertNonvoid(Words != (u32)0); + Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST); + Xil_AssertNonvoid(Addr != NULL); + + /* + * variable initialization + */ + Val = XIL_TESTMEM_INIT_VALUE; + FirtVal = XIL_TESTMEM_INIT_VALUE; + + /* + * selectthe proper Subtest(s) + */ + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { + /* + * Fill the memory with incrementing + * values starting from 'FirtVal' + */ + for (I = 0U; I < Words; I++) { + /* write memory location */ + *(Addr+I) = Val; + Val++; + } + /* + * Restore the reference 'Val' to the + * initial value + */ + Val = FirtVal; + + /* + * Check every word within the words + * of tested memory and compare it + * with the incrementing reference val + */ + + for (I = 0U; I < Words; I++) { + /* read memory location */ + WordMem16 = *(Addr+I); + if (WordMem16 != Val) { + Status = -1; + goto End_Label; + } + Val++; + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { + /* + * set up to cycle through all possible initial test + * Patterns for walking ones test + */ + + for (j = 0U; j < (u32)16; j++) { + /* + * Generate an initial value for walking ones test + * to test for bad data bits + */ + + Val = (u16)((u32)1 << j); + /* + * START walking ones test + * Write a one to each data bit indifferent locations + */ + + for (I = 0U; I < (u32)16; I++) { + /* write memory location */ + *(Addr+I) = Val; + Val = (u16)RotateLeft(Val, 16U); + } + /* + * Restore the reference 'Val' to the + * initial value + */ + Val = (u16)((u32)1 << j); + /* Read the values from each location that was written */ + for (I = 0U; I < (u32)16; I++) { + /* read memory location */ + WordMem16 = *(Addr+I); + if (WordMem16 != Val) { + Status = -1; + goto End_Label; + } + Val = (u16)RotateLeft(Val, 16U); + } + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { + /* + * set up to cycle through all possible initial + * test Patterns for walking zeros test + */ + + for (j = 0U; j < (u32)16; j++) { + /* + * Generate an initial value for walking ones + * test to test for bad + * data bits + */ + + Val = ~(1U << j); + /* + * START walking zeros test + * Write a one to each data bit indifferent locations + */ + + for (I = 0U; I < (u32)16; I++) { + /* write memory location */ + *(Addr+I) = Val; + Val = ~((u16)RotateLeft(~Val, 16U)); + } + /* + * Restore the reference 'Val' to the + * initial value + */ + Val = ~(1U << j); + /* Read the values from each location that was written */ + for (I = 0U; I < (u32)16; I++) { + /* read memory location */ + WordMem16 = *(Addr+I); + if (WordMem16 != Val) { + Status = -1; + goto End_Label; + } + Val = ~((u16)RotateLeft(~Val, 16U)); + } + + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { + /* Fill the memory with inverse of address */ + for (I = 0U; I < Words; I++) { + /* write memory location */ + Val = (u16) (~((INTPTR)(&Addr[I]))); + *(Addr+I) = Val; + } + /* + * Check every word within the words + * of tested memory + */ + + for (I = 0U; I < Words; I++) { + /* read memory location */ + WordMem16 = *(Addr+I); + Val = (u16) (~((INTPTR) (&Addr[I]))); + if ((WordMem16 ^ Val) != 0x0000U) { + Status = -1; + goto End_Label; + } + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { + /* + * Generate an initial value for + * memory testing + */ + if (Pattern == (u16)0) { + Val = 0xDEADU; + } + else { + Val = Pattern; + } + + /* + * Fill the memory with fixed pattern + */ + + for (I = 0U; I < Words; I++) { + /* write memory location */ + *(Addr+I) = Val; + } + + /* + * Check every word within the words + * of tested memory and compare it + * with the fixed pattern + */ + + for (I = 0U; I < Words; I++) { + /* read memory location */ + WordMem16 = *(Addr+I); + if (WordMem16 != Val) { + Status = -1; + goto End_Label; + } + } + } + +End_Label: + return Status; +} + + +/*****************************************************************************/ +/** +* +* @brief Perform a destructive 8-bit wide memory test. +* +* @param Addr: pointer to the region of memory to be tested. +* @param Words: length of the block. +* @param Pattern: constant used for the constant pattern test, if 0, +* 0xDEADBEEF is used. +* @param Subtest: type of test selected. See xil_testmem.h for possible +* values. +* +* @return +* - -1 is returned for a failure +* - 0 is returned for a pass +* +* @note +* Used for spaces where the address range of the region is smaller than +* the data width. If the memory range is greater than 2 ** Width, +* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will +* repeat on a boundry of a power of two making it more difficult to detect +* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR +* tests suffer the same problem. Ideally, if large blocks of memory are to be +* tested, break them up into smaller regions of memory to allow the test +* patterns used not to repeat over the region tested. +* +*****************************************************************************/ +s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest) +{ + u32 I; + u32 j; + u8 Val; + u8 FirtVal; + u8 WordMem8; + s32 Status = 0; + + Xil_AssertNonvoid(Words != (u32)0); + Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST); + Xil_AssertNonvoid(Addr != NULL); + + /* + * variable initialization + */ + Val = XIL_TESTMEM_INIT_VALUE; + FirtVal = XIL_TESTMEM_INIT_VALUE; + + /* + * select the proper Subtest(s) + */ + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { + /* + * Fill the memory with incrementing + * values starting from 'FirtVal' + */ + for (I = 0U; I < Words; I++) { + /* write memory location */ + *(Addr+I) = Val; + Val++; + } + /* + * Restore the reference 'Val' to the + * initial value + */ + Val = FirtVal; + /* + * Check every word within the words + * of tested memory and compare it + * with the incrementing reference + * Val + */ + + for (I = 0U; I < Words; I++) { + /* read memory location */ + WordMem8 = *(Addr+I); + if (WordMem8 != Val) { + Status = -1; + goto End_Label; + } + Val++; + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { + /* + * set up to cycle through all possible initial + * test Patterns for walking ones test + */ + + for (j = 0U; j < (u32)8; j++) { + /* + * Generate an initial value for walking ones test + * to test for bad data bits + */ + Val = (u8)((u32)1 << j); + /* + * START walking ones test + * Write a one to each data bit indifferent locations + */ + for (I = 0U; I < (u32)8; I++) { + /* write memory location */ + *(Addr+I) = Val; + Val = (u8)RotateLeft(Val, 8U); + } + /* + * Restore the reference 'Val' to the + * initial value + */ + Val = (u8)((u32)1 << j); + /* Read the values from each location that was written */ + for (I = 0U; I < (u32)8; I++) { + /* read memory location */ + WordMem8 = *(Addr+I); + if (WordMem8 != Val) { + Status = -1; + goto End_Label; + } + Val = (u8)RotateLeft(Val, 8U); + } + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { + /* + * set up to cycle through all possible initial test + * Patterns for walking zeros test + */ + + for (j = 0U; j < (u32)8; j++) { + /* + * Generate an initial value for walking ones test to test + * for bad data bits + */ + Val = ~(1U << j); + /* + * START walking zeros test + * Write a one to each data bit indifferent locations + */ + for (I = 0U; I < (u32)8; I++) { + /* write memory location */ + *(Addr+I) = Val; + Val = ~((u8)RotateLeft(~Val, 8U)); + } + /* + * Restore the reference 'Val' to the + * initial value + */ + Val = ~(1U << j); + /* Read the values from each location that was written */ + for (I = 0U; I < (u32)8; I++) { + /* read memory location */ + WordMem8 = *(Addr+I); + if (WordMem8 != Val) { + Status = -1; + goto End_Label; + } + + Val = ~((u8)RotateLeft(~Val, 8U)); + } + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { + /* Fill the memory with inverse of address */ + for (I = 0U; I < Words; I++) { + /* write memory location */ + Val = (u8) (~((INTPTR) (&Addr[I]))); + *(Addr+I) = Val; + } + + /* + * Check every word within the words + * of tested memory + */ + + for (I = 0U; I < Words; I++) { + /* read memory location */ + WordMem8 = *(Addr+I); + Val = (u8) (~((INTPTR) (&Addr[I]))); + if ((WordMem8 ^ Val) != 0x00U) { + Status = -1; + goto End_Label; + } + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { + /* + * Generate an initial value for + * memory testing + */ + + if (Pattern == (u8)0) { + Val = 0xA5U; + } + else { + Val = Pattern; + } + /* + * Fill the memory with fixed Pattern + */ + for (I = 0U; I < Words; I++) { + /* write memory location */ + *(Addr+I) = Val; + } + /* + * Check every word within the words + * of tested memory and compare it + * with the fixed Pattern + */ + + for (I = 0U; I < Words; I++) { + /* read memory location */ + WordMem8 = *(Addr+I); + if (WordMem8 != Val) { + Status = -1; + goto End_Label; + } + } + } + +End_Label: + return Status; +} + + +/*****************************************************************************/ +/** +* +* @brief Rotates the provided value to the left one bit position +* +* @param Input is value to be rotated to the left +* @param Width is the number of bits in the input data +* +* @return +* The resulting unsigned long value of the rotate left +* +* +*****************************************************************************/ +static u32 RotateLeft(u32 Input, u8 Width) +{ + u32 Msb; + u32 ReturnVal; + u32 WidthMask; + u32 MsbMask; + u32 LocalInput = Input; + + /* + * set up the WidthMask and the MsbMask + */ + + MsbMask = 1U << (Width - 1U); + + WidthMask = (MsbMask << (u32)1) - (u32)1; + + /* + * set the Width of the Input to the correct width + */ + + LocalInput = LocalInput & WidthMask; + + Msb = LocalInput & MsbMask; + + ReturnVal = LocalInput << 1U; + + if (Msb != 0x00000000U) { + ReturnVal = ReturnVal | (u32)0x00000001; + } + + ReturnVal = ReturnVal & WidthMask; + + return ReturnVal; + +} + +#ifdef ROTATE_RIGHT +/*****************************************************************************/ +/** +* +* @brief Rotates the provided value to the right one bit position +* +* @param Input: value to be rotated to the right +* @param Width: number of bits in the input data +* +* @return +* The resulting u32 value of the rotate right +* +*****************************************************************************/ +static u32 RotateRight(u32 Input, u8 Width) +{ + u32 Lsb; + u32 ReturnVal; + u32 WidthMask; + u32 MsbMask; + u32 LocalInput = Input; + /* + * set up the WidthMask and the MsbMask + */ + + MsbMask = 1U << (Width - 1U); + + WidthMask = (MsbMask << 1U) - 1U; + + /* + * set the width of the input to the correct width + */ + + LocalInput = LocalInput & WidthMask; + + ReturnVal = LocalInput >> 1U; + + Lsb = LocalInput & 0x00000001U; + + if (Lsb != 0x00000000U) { + ReturnVal = ReturnVal | MsbMask; + } + + ReturnVal = ReturnVal & WidthMask; + + return ReturnVal; + +} +#endif /* ROTATE_RIGHT */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_testmem.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_testmem.h new file mode 100644 index 0000000..c204728 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_testmem.h
@@ -0,0 +1,158 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_testmem.h +* @addtogroup common_test_utils +* +* <h2>Memory test</h2> +* +* The xil_testmem.h file contains utility functions to test memory. +* A subset of the memory tests can be selected or all of the tests can be run +* in order. If there is an error detected by a subtest, the test stops and the +* failure code is returned. Further tests are not run even if all of the tests +* are selected. +* Following list describes the supported memory tests: +* +* - XIL_TESTMEM_ALLMEMTESTS: This test runs all of the subtests. +* +* - XIL_TESTMEM_INCREMENT: This test +* starts at 'XIL_TESTMEM_INIT_VALUE' and uses the incrementing value as the +* test value for memory. +* +* - XIL_TESTMEM_WALKONES: Also known as the Walking ones test. This test +* uses a walking '1' as the test value for memory. +* @code +* location 1 = 0x00000001 +* location 2 = 0x00000002 +* ... +* @endcode +* +* - XIL_TESTMEM_WALKZEROS: Also known as the Walking zero's test. +* This test uses the inverse value of the walking ones test +* as the test value for memory. +* @code +* location 1 = 0xFFFFFFFE +* location 2 = 0xFFFFFFFD +* ... +*@endcode +* +* - XIL_TESTMEM_INVERSEADDR: Also known as the inverse address test. +* This test uses the inverse of the address of the location under test +* as the test value for memory. +* +* - XIL_TESTMEM_FIXEDPATTERN: Also known as the fixed pattern test. +* This test uses the provided patters as the test value for memory. +* If zero is provided as the pattern the test uses '0xDEADBEEF". +* +* @warning +* The tests are <b>DESTRUCTIVE</b>. Run before any initialized memory spaces +* have been set up. +* The address provided to the memory tests is not checked for +* validity except for the NULL case. It is possible to provide a code-space +* pointer for this test to start with and ultimately destroy executable code +* causing random failures. +* +* @note +* Used for spaces where the address range of the region is smaller than +* the data width. If the memory range is greater than 2 ** width, +* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will +* repeat on a boundry of a power of two making it more difficult to detect +* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR +* tests suffer the same problem. Ideally, if large blocks of memory are to be +* tested, break them up into smaller regions of memory to allow the test +* patterns used not to repeat over the region tested. +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ----------------------------------------------- +* 1.00a hbm 08/25/09 First release +* </pre> +* +******************************************************************************/ + +#ifndef XIL_TESTMEM_H /* prevent circular inclusions */ +#define XIL_TESTMEM_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xil_types.h" + +/************************** Constant Definitions *****************************/ + + +/**************************** Type Definitions *******************************/ + +/* xutil_memtest defines */ + +#define XIL_TESTMEM_INIT_VALUE 1U + +/** @name Memory subtests + * @{ + */ +/** + * See the detailed description of the subtests in the file description. + */ +#define XIL_TESTMEM_ALLMEMTESTS 0x00U +#define XIL_TESTMEM_INCREMENT 0x01U +#define XIL_TESTMEM_WALKONES 0x02U +#define XIL_TESTMEM_WALKZEROS 0x03U +#define XIL_TESTMEM_INVERSEADDR 0x04U +#define XIL_TESTMEM_FIXEDPATTERN 0x05U +#define XIL_TESTMEM_MAXTEST XIL_TESTMEM_FIXEDPATTERN +/* @} */ + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +/* xutil_testmem prototypes */ + +extern s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest); +extern s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest); +extern s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** +* @} End of "addtogroup common_test_utils". +*/
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_types.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_types.h new file mode 100644 index 0000000..8143aff --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_types.h
@@ -0,0 +1,209 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_types.h +* +* @addtogroup common_types Basic Data types for Xilinx® Software IP +* +* The xil_types.h file contains basic types for Xilinx software IP. These data types +* are applicable for all processors supported by Xilinx. +* @{ +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 1.00a hbm 07/14/09 First release +* 3.03a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros +* 5.00 pkp 05/29/14 Made changes for 64 bit architecture +* srt 07/14/14 Use standard definitions from stdint.h and stddef.h +* Define LONG and ULONG datatypes and mask values +* </pre> +* +******************************************************************************/ + +#ifndef XIL_TYPES_H /* prevent circular inclusions */ +#define XIL_TYPES_H /* by using protection macros */ + +#include <stdint.h> +#include <stddef.h> + +/************************** Constant Definitions *****************************/ + +#ifndef TRUE +# define TRUE 1U +#endif + +#ifndef FALSE +# define FALSE 0U +#endif + +#ifndef NULL +#define NULL 0U +#endif + +#define XIL_COMPONENT_IS_READY 0x11111111U /**< In device drivers, This macro will be + assigend to "IsReady" member of driver + instance to indicate that driver + instance is initialized and ready to use. */ +#define XIL_COMPONENT_IS_STARTED 0x22222222U /**< In device drivers, This macro will be assigend to + "IsStarted" member of driver instance + to indicate that driver instance is + started and it can be enabled. */ + +/* @name New types + * New simple types. + * @{ + */ +#ifndef __KERNEL__ +#ifndef XBASIC_TYPES_H +/* + * guarded against xbasic_types.h. + */ +typedef uint8_t u8; +typedef uint16_t u16; +typedef uint32_t u32; +/** @}*/ +#define __XUINT64__ +typedef struct +{ + u32 Upper; + u32 Lower; +} Xuint64; + + +/*****************************************************************************/ +/** +* @brief Return the most significant half of the 64 bit data type. +* +* @param x is the 64 bit word. +* +* @return The upper 32 bits of the 64 bit word. +* +******************************************************************************/ +#define XUINT64_MSW(x) ((x).Upper) + +/*****************************************************************************/ +/** +* @brief Return the least significant half of the 64 bit data type. +* +* @param x is the 64 bit word. +* +* @return The lower 32 bits of the 64 bit word. +* +******************************************************************************/ +#define XUINT64_LSW(x) ((x).Lower) + +#endif /* XBASIC_TYPES_H */ + +/* + * xbasic_types.h does not typedef s* or u64 + */ +/** @{ */ +typedef char char8; +typedef int8_t s8; +typedef int16_t s16; +typedef int32_t s32; +typedef int64_t s64; +typedef uint64_t u64; +typedef int sint32; + +typedef intptr_t INTPTR; +typedef uintptr_t UINTPTR; +typedef ptrdiff_t PTRDIFF; +/** @}*/ +#if !defined(LONG) || !defined(ULONG) +typedef long LONG; +typedef unsigned long ULONG; +#endif + +#define ULONG64_HI_MASK 0xFFFFFFFF00000000U +#define ULONG64_LO_MASK ~ULONG64_HI_MASK + +#else +#include <linux/types.h> +#endif + +/** @{ */ +/** + * This data type defines an interrupt handler for a device. + * The argument points to the instance of the component + */ +typedef void (*XInterruptHandler) (void *InstancePtr); + +/** + * This data type defines an exception handler for a processor. + * The argument points to the instance of the component + */ +typedef void (*XExceptionHandler) (void *InstancePtr); + +/** + * @brief Returns 32-63 bits of a number. + * @param n : Number being accessed. + * @return Bits 32-63 of number. + * + * @note A basic shift-right of a 64- or 32-bit quantity. + * Use this to suppress the "right shift count >= width of type" + * warning when that quantity is 32-bits. + */ +#define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16)) + +/** + * @brief Returns 0-31 bits of a number + * @param n : Number being accessed. + * @return Bits 0-31 of number + */ +#define LOWER_32_BITS(n) ((u32)(n)) + + + + +/************************** Constant Definitions *****************************/ + +#ifndef TRUE +#define TRUE 1U +#endif + +#ifndef FALSE +#define FALSE 0U +#endif + +#ifndef NULL +#define NULL 0U +#endif + +#endif /* end of protection macro */ +/** +* @} End of "addtogroup common_types". +*/
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xparameters_ps.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xparameters_ps.h new file mode 100644 index 0000000..a19e172 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xparameters_ps.h
@@ -0,0 +1,342 @@ +/****************************************************************************** +* +* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xparameters_ps.h +* +* This file contains the address definitions for the hard peripherals +* attached to the ARM Cortex A53 core. +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ------- -------- --------------------------------------------------- +* 5.00 pkp 05/29/14 First release +* </pre> +* +* @note +* +* None. +* +******************************************************************************/ + +#ifndef _XPARAMETERS_PS_H_ +#define _XPARAMETERS_PS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + + +/************************** Constant Definitions *****************************/ + +/* + * This block contains constant declarations for the peripherals + * within the hardblock + */ + +/* Canonical definitions for DDR MEMORY */ +#define XPAR_DDR_MEM_BASEADDR 0x00000000U +#define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFFU + +/* Canonical definitions for Interrupts */ +#define XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID +#define XPAR_XUARTPS_1_INTR XPS_UART1_INT_ID +#define XPAR_XIICPS_0_INTR XPS_I2C0_INT_ID +#define XPAR_XIICPS_1_INTR XPS_I2C1_INT_ID +#define XPAR_XSPIPS_0_INTR XPS_SPI0_INT_ID +#define XPAR_XSPIPS_1_INTR XPS_SPI1_INT_ID +#define XPAR_XCANPS_0_INTR XPS_CAN0_INT_ID +#define XPAR_XCANPS_1_INTR XPS_CAN1_INT_ID +#define XPAR_XGPIOPS_0_INTR XPS_GPIO_INT_ID +#define XPAR_XEMACPS_0_INTR XPS_GEM0_INT_ID +#define XPAR_XEMACPS_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID +#define XPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID +#define XPAR_XEMACPS_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID +#define XPAR_XEMACPS_2_INTR XPS_GEM2_INT_ID +#define XPAR_XEMACPS_2_WAKE_INTR XPS_GEM2_WAKE_INT_ID +#define XPAR_XEMACPS_3_INTR XPS_GEM3_INT_ID +#define XPAR_XEMACPS_3_WAKE_INTR XPS_GEM3_WAKE_INT_ID +#define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID +#define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID +#define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID +#define XPAR_XWDTPS_0_INTR XPS_LPD_SWDT_INT_ID +#define XPAR_XWDTPS_1_INTR XPS_FPD_SWDT_INT_ID +#define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID +#define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID +#define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID +#define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID +#define XPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_ID +#define XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_ID +#define XPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID +#define XPAR_XTTCPS_6_INTR XPS_TTC2_0_INT_ID +#define XPAR_XTTCPS_7_INTR XPS_TTC2_1_INT_ID +#define XPAR_XTTCPS_8_INTR XPS_TTC2_2_INT_ID +#define XPAR_XTTCPS_9_INTR XPS_TTC3_0_INT_ID +#define XPAR_XTTCPS_10_INTR XPS_TTC3_1_INT_ID +#define XPAR_XTTCPS_11_INTR XPS_TTC3_2_INT_ID +#define XPAR_XNANDPS8_0_INTR XPS_NAND_INT_ID +#define XPAR_XADMAPS_0_INTR XPS_ADMA_CH0_INT_ID +#define XPAR_XADMAPS_1_INTR XPS_ADMA_CH1_INT_ID +#define XPAR_XADMAPS_2_INTR XPS_ADMA_CH2_INT_ID +#define XPAR_XADMAPS_3_INTR XPS_ADMA_CH3_INT_ID +#define XPAR_XADMAPS_4_INTR XPS_ADMA_CH4_INT_ID +#define XPAR_XADMAPS_5_INTR XPS_ADMA_CH5_INT_ID +#define XPAR_XADMAPS_6_INTR XPS_ADMA_CH6_INT_ID +#define XPAR_XADMAPS_7_INTR XPS_ADMA_CH7_INT_ID +#define XPAR_XCSUDMA_INTR XPS_CSU_DMA_INT_ID +#define XPAR_PSU_ADMA_0_INTR XPS_ADMA_CH0_INT_ID +#define XPAR_PSU_ADMA_1_INTR XPS_ADMA_CH1_INT_ID +#define XPAR_PSU_ADMA_2_INTR XPS_ADMA_CH2_INT_ID +#define XPAR_PSU_ADMA_3_INTR XPS_ADMA_CH3_INT_ID +#define XPAR_PSU_ADMA_4_INTR XPS_ADMA_CH4_INT_ID +#define XPAR_PSU_ADMA_5_INTR XPS_ADMA_CH5_INT_ID +#define XPAR_PSU_ADMA_6_INTR XPS_ADMA_CH6_INT_ID +#define XPAR_PSU_ADMA_7_INTR XPS_ADMA_CH7_INT_ID +#define XPAR_PSU_CSUDMA_INTR XPS_CSU_DMA_INT_ID +#define XPAR_XMPU_LPD_INTR XPS_XMPU_LPD_INT_ID +#define XPAR_XZDMAPS_0_INTR XPS_ZDMA_CH0_INT_ID +#define XPAR_XZDMAPS_1_INTR XPS_ZDMA_CH1_INT_ID +#define XPAR_XZDMAPS_2_INTR XPS_ZDMA_CH2_INT_ID +#define XPAR_XZDMAPS_3_INTR XPS_ZDMA_CH3_INT_ID +#define XPAR_XZDMAPS_4_INTR XPS_ZDMA_CH4_INT_ID +#define XPAR_XZDMAPS_5_INTR XPS_ZDMA_CH5_INT_ID +#define XPAR_XZDMAPS_6_INTR XPS_ZDMA_CH6_INT_ID +#define XPAR_XZDMAPS_7_INTR XPS_ZDMA_CH7_INT_ID +#define XPAR_PSU_GDMA_0_INTR XPS_ZDMA_CH0_INT_ID +#define XPAR_PSU_GDMA_1_INTR XPS_ZDMA_CH1_INT_ID +#define XPAR_PSU_GDMA_2_INTR XPS_ZDMA_CH2_INT_ID +#define XPAR_PSU_GDMA_3_INTR XPS_ZDMA_CH3_INT_ID +#define XPAR_PSU_GDMA_4_INTR XPS_ZDMA_CH4_INT_ID +#define XPAR_PSU_GDMA_5_INTR XPS_ZDMA_CH5_INT_ID +#define XPAR_PSU_GDMA_6_INTR XPS_ZDMA_CH6_INT_ID +#define XPAR_PSU_GDMA_7_INTR XPS_ZDMA_CH7_INT_ID +#define XPAR_XMPU_FPD_INTR XPS_XMPU_FPD_INT_ID +#define XPAR_XCCI_FPD_INTR XPS_FPD_CCI_INT_ID +#define XPAR_XSMMU_FPD_INTR XPS_FPD_SMMU_INT_ID +#define XPAR_XUSBPS_0_INTR XPS_USB3_0_ENDPT_INT_ID +#define XPAR_XUSBPS_1_INTR XPS_USB3_1_ENDPT_INT_ID +#define XPAR_XUSBPS_0_WAKE_INTR XPS_USB3_0_WAKE_INT_ID +#define XPAR_XUSBPS_1_WAKE_INTR XPS_USB3_1_WAKE_INT_ID +#define XPAR_XRTCPSU_ALARM_INTR XPS_RTC_ALARM_INT_ID +#define XPAR_XRTCPSU_SECONDS_INTR XPS_RTC_SEC_INT_ID +#define XPAR_XAPMPS_0_INTR XPS_APM0_INT_ID +#define XPAR_XAPMPS_1_INTR XPS_APM1_INT_ID +#define XPAR_XAPMPS_2_INTR XPS_APM2_INT_ID +#define XPAR_XAPMPS_5_INTR XPS_APM5_INT_ID +#define XPAR_XSYSMONPSU_INTR XPS_AMS_INT_ID + +/* Canonical definitions for SCU GIC */ +#define XPAR_SCUGIC_NUM_INSTANCES 1U +#define XPAR_SCUGIC_SINGLE_DEVICE_ID 0U +#define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00001000U) +#define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00002000U) +#define XPAR_SCUGIC_ACK_BEFORE 0U + +#define XPAR_CPU_CORTEXA53_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA53_0_CPU_CLK_FREQ_HZ + + +/* + * This block contains constant declarations for the peripherals + * within the hardblock. These have been put for backwards compatibilty + */ + + +#define XPS_SYS_CTRL_BASEADDR 0xFF180000U +#define XPS_SCU_PERIPH_BASE 0xF9000000U + + + +/* Shared Peripheral Interrupts (SPI) */ +#define XPS_FPGA0_INT_ID 121U +#define XPS_FPGA1_INT_ID 122U +#define XPS_FPGA2_INT_ID 123U +#define XPS_FPGA3_INT_ID 124U +#define XPS_FPGA4_INT_ID 125U +#define XPS_FPGA5_INT_ID 126U +#define XPS_FPGA6_INT_ID 127U +#define XPS_FPGA7_INT_ID 128U +#define XPS_FPGA8_INT_ID 136U +#define XPS_FPGA9_INT_ID 137U +#define XPS_FPGA10_INT_ID 138U +#define XPS_FPGA11_INT_ID 139U +#define XPS_FPGA12_INT_ID 140U +#define XPS_FPGA13_INT_ID 141U +#define XPS_FPGA14_INT_ID 142U +#define XPS_FPGA15_INT_ID 143U + +/* Updated Interrupt-IDs */ +#define XPS_OCMINTR_INT_ID (10U + 32U) +#define XPS_NAND_INT_ID (14U + 32U) +#define XPS_QSPI_INT_ID (15U + 32U) +#define XPS_GPIO_INT_ID (16U + 32U) +#define XPS_I2C0_INT_ID (17U + 32U) +#define XPS_I2C1_INT_ID (18U + 32U) +#define XPS_SPI0_INT_ID (19U + 32U) +#define XPS_SPI1_INT_ID (20U + 32U) +#define XPS_UART0_INT_ID (21U + 32U) +#define XPS_UART1_INT_ID (22U + 32U) +#define XPS_CAN0_INT_ID (23U + 32U) +#define XPS_CAN1_INT_ID (24U + 32U) +#define XPS_RTC_ALARM_INT_ID (26U + 32U) +#define XPS_RTC_SEC_INT_ID (27U + 32U) +#define XPS_LPD_SWDT_INT_ID (52U + 32U) +#define XPS_FPD_SWDT_INT_ID (113U + 32U) +#define XPS_TTC0_0_INT_ID (36U + 32U) +#define XPS_TTC0_1_INT_ID (37U + 32U) +#define XPS_TTC0_2_INT_ID (38U + 32U) +#define XPS_TTC1_0_INT_ID (39U + 32U) +#define XPS_TTC1_1_INT_ID (40U + 32U) +#define XPS_TTC1_2_INT_ID (41U + 32U) +#define XPS_TTC2_0_INT_ID (42U + 32U) +#define XPS_TTC2_1_INT_ID (43U + 32U) +#define XPS_TTC2_2_INT_ID (44U + 32U) +#define XPS_TTC3_0_INT_ID (45U + 32U) +#define XPS_TTC3_1_INT_ID (46U + 32U) +#define XPS_TTC3_2_INT_ID (47U + 32U) +#define XPS_SDIO0_INT_ID (48U + 32U) +#define XPS_SDIO1_INT_ID (49U + 32U) +#define XPS_AMS_INT_ID (56U + 32U) +#define XPS_GEM0_INT_ID (57U + 32U) +#define XPS_GEM0_WAKE_INT_ID (58U + 32U) +#define XPS_GEM1_INT_ID (59U + 32U) +#define XPS_GEM1_WAKE_INT_ID (60U + 32U) +#define XPS_GEM2_INT_ID (61U + 32U) +#define XPS_GEM2_WAKE_INT_ID (62U + 32U) +#define XPS_GEM3_INT_ID (63U + 32U) +#define XPS_GEM3_WAKE_INT_ID (64U + 32U) +#define XPS_USB3_0_ENDPT_INT_ID (65U + 32U) +#define XPS_USB3_1_ENDPT_INT_ID (70U + 32U) +#define XPS_USB3_0_WAKE_INT_ID (75U + 32U) +#define XPS_USB3_1_WAKE_INT_ID (76U + 32U) +#define XPS_ADMA_CH0_INT_ID (77U + 32U) +#define XPS_ADMA_CH1_INT_ID (78U + 32U) +#define XPS_ADMA_CH2_INT_ID (79U + 32U) +#define XPS_ADMA_CH3_INT_ID (80U + 32U) +#define XPS_ADMA_CH4_INT_ID (81U + 32U) +#define XPS_ADMA_CH5_INT_ID (82U + 32U) +#define XPS_ADMA_CH6_INT_ID (83U + 32U) +#define XPS_ADMA_CH7_INT_ID (84U + 32U) +#define XPS_CSU_DMA_INT_ID (86U + 32U) +#define XPS_XMPU_LPD_INT_ID (88U + 32U) +#define XPS_ZDMA_CH0_INT_ID (124U + 32U) +#define XPS_ZDMA_CH1_INT_ID (125U + 32U) +#define XPS_ZDMA_CH2_INT_ID (126U + 32U) +#define XPS_ZDMA_CH3_INT_ID (127U + 32U) +#define XPS_ZDMA_CH4_INT_ID (128U + 32U) +#define XPS_ZDMA_CH5_INT_ID (129U + 32U) +#define XPS_ZDMA_CH6_INT_ID (130U + 32U) +#define XPS_ZDMA_CH7_INT_ID (131U + 32U) +#define XPS_XMPU_FPD_INT_ID (134U + 32U) +#define XPS_FPD_CCI_INT_ID (154U + 32U) +#define XPS_FPD_SMMU_INT_ID (155U + 32U) +#define XPS_APM0_INT_ID (123U + 32U) +#define XPS_APM1_INT_ID (25U + 32U) +#define XPS_APM2_INT_ID (25U + 32U) +#define XPS_APM5_INT_ID (123U + 32U) + +/* REDEFINES for TEST APP */ +#define XPAR_PSU_UART_0_INTR XPS_UART0_INT_ID +#define XPAR_PSU_UART_1_INTR XPS_UART1_INT_ID +#define XPAR_PSU_USB_0_INTR XPS_USB0_INT_ID +#define XPAR_PSU_USB_1_INTR XPS_USB1_INT_ID +#define XPAR_PSU_I2C_0_INTR XPS_I2C0_INT_ID +#define XPAR_PSU_I2C_1_INTR XPS_I2C1_INT_ID +#define XPAR_PSU_SPI_0_INTR XPS_SPI0_INT_ID +#define XPAR_PSU_SPI_1_INTR XPS_SPI1_INT_ID +#define XPAR_PSU_CAN_0_INTR XPS_CAN0_INT_ID +#define XPAR_PSU_CAN_1_INTR XPS_CAN1_INT_ID +#define XPAR_PSU_GPIO_0_INTR XPS_GPIO_INT_ID +#define XPAR_PSU_ETHERNET_0_INTR XPS_GEM0_INT_ID +#define XPAR_PSU_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID +#define XPAR_PSU_ETHERNET_1_INTR XPS_GEM1_INT_ID +#define XPAR_PSU_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID +#define XPAR_PSU_ETHERNET_2_INTR XPS_GEM2_INT_ID +#define XPAR_PSU_ETHERNET_2_WAKE_INTR XPS_GEM2_WAKE_INT_ID +#define XPAR_PSU_ETHERNET_3_INTR XPS_GEM3_INT_ID +#define XPAR_PSU_ETHERNET_3_WAKE_INTR XPS_GEM3_WAKE_INT_ID +#define XPAR_PSU_QSPI_0_INTR XPS_QSPI_INT_ID +#define XPAR_PSU_WDT_0_INTR XPS_LPD_SWDT_INT_ID +#define XPAR_PSU_WDT_1_INTR XPS_FPD_SWDT_INT_ID +#define XPAR_PSU_XADC_0_INTR XPS_SYSMON_INT_ID +#define XPAR_PSU_TTC_0_INTR XPS_TTC0_0_INT_ID +#define XPAR_PSU_TTC_1_INTR XPS_TTC0_1_INT_ID +#define XPAR_PSU_TTC_2_INTR XPS_TTC0_2_INT_ID +#define XPAR_PSU_TTC_3_INTR XPS_TTC1_0_INT_ID +#define XPAR_PSU_TTC_4_INTR XPS_TTC1_1_INT_ID +#define XPAR_PSU_TTC_5_INTR XPS_TTC1_2_INT_ID +#define XPAR_PSU_TTC_6_INTR XPS_TTC2_0_INT_ID +#define XPAR_PSU_TTC_7_INTR XPS_TTC2_1_INT_ID +#define XPAR_PSU_TTC_8_INTR XPS_TTC2_2_INT_ID +#define XPAR_PSU_TTC_9_INTR XPS_TTC3_0_INT_ID +#define XPAR_PSU_TTC_10_INTR XPS_TTC3_1_INT_ID +#define XPAR_PSU_TTC_11_INTR XPS_TTC3_2_INT_ID +#define XPAR_PSU_AMS_INTR XPS_AMS_INT_ID + +#define XPAR_XADCPS_NUM_INSTANCES 1U +#define XPAR_XADCPS_0_DEVICE_ID 0U +#define XPAR_XADCPS_0_BASEADDR (0xF8007000U) +#define XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID + +/* For backwards compatibilty */ +#define XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ +#define XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ +#define XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ +#define XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZ +#define XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZ + +#define XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ + +#ifdef XPAR_CPU_CORTEXA53_0_CPU_CLK_FREQ_HZ +#define XPAR_CPU_CORTEXA53_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA53_0_CPU_CLK_FREQ_HZ +#endif + +#ifdef XPAR_CPU_CORTEXA53_1_CPU_CLK_FREQ_HZ +#define XPAR_CPU_CORTEXA53_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA53_1_CPU_CLK_FREQ_HZ +#endif + +#define XPAR_SCUWDT_DEVICE_ID 0U + + +#ifdef __cplusplus +} +#endif + +#endif /* protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xplatform_info.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xplatform_info.c new file mode 100644 index 0000000..2c08e5f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xplatform_info.c
@@ -0,0 +1,161 @@ +/****************************************************************************** +* +* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xplatform_info.c +* +* This file contains information about hardware for which the code is built +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 5.00 pkp 12/15/14 Initial release +* 5.04 pkp 01/12/16 Added platform information support for Cortex-A53 32bit +* mode +* 6.00 mus 17/08/16 Removed unused variable from XGetPlatform_Info +* 6.4 ms 05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info +* function for PMUFW. +* ms 06/13/17 Added PSU_PMU macro to provide support of +* XGetPlatform_Info function for PMUFW. +* mus 08/17/17 Add EL1 NS mode support for +* XGet_Zynq_UltraMp_Platform_info and XGetPSVersion_Info +* APIs. +* </pre> +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_io.h" +#include "xplatform_info.h" +#if defined (__aarch64__) +#include "bspconfig.h" +#include "xil_smc.h" +#endif +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Variable Definitions *****************************/ + + +/************************** Function Prototypes ******************************/ + +/*****************************************************************************/ +/** +* +* @brief This API is used to provide information about platform +* +* @param None. +* +* @return The information about platform defined in xplatform_info.h +* +******************************************************************************/ +u32 XGetPlatform_Info() +{ + +#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU) + return XPLAT_ZYNQ_ULTRA_MP; +#elif (__microblaze__) + return XPLAT_MICROBLAZE; +#else + return XPLAT_ZYNQ; +#endif +} + +/*****************************************************************************/ +/** +* +* @brief This API is used to provide information about zynq ultrascale MP platform +* +* @param None. +* +* @return The information about zynq ultrascale MP platform defined in +* xplatform_info.h +* +******************************************************************************/ +#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) +u32 XGet_Zynq_UltraMp_Platform_info() +{ +#if EL1_NONSECURE + XSmc_OutVar reg; + /* + * This SMC call will return, + * idcode - upper 32 bits of reg.Arg0 + * version - lower 32 bits of reg.Arg1 + */ + reg = Xil_Smc(GET_CHIPID_SMC_FID,0,0, 0, 0, 0, 0, 0); + return (u32)((reg.Arg1 >> XPLAT_INFO_SHIFT) & XPLAT_INFO_MASK); +#else + u32 reg; + reg = ((Xil_In32(XPAR_CSU_BASEADDR + XPAR_CSU_VER_OFFSET) >> 12U )& XPLAT_INFO_MASK); + return reg; +#endif +} +#endif + +/*****************************************************************************/ +/** +* +* @brief This API is used to provide information about PS Silicon version +* +* @param None. +* +* @return The information about PS Silicon version. +* +******************************************************************************/ +#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU) +u32 XGetPSVersion_Info() +{ +#if EL1_NONSECURE + /* + * This SMC call will return, + * idcode - upper 32 bits of reg.Arg0 + * version - lower 32 bits of reg.Arg1 + */ + XSmc_OutVar reg; + reg = Xil_Smc(GET_CHIPID_SMC_FID,0,0, 0, 0, 0, 0, 0); + return (u32)(reg.Arg1 & XPS_VERSION_INFO_MASK); +#else + u32 reg; + reg = (Xil_In32(XPAR_CSU_BASEADDR + XPAR_CSU_VER_OFFSET) + & XPS_VERSION_INFO_MASK); + return reg; +#endif +} +#endif
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xplatform_info.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xplatform_info.h new file mode 100644 index 0000000..0582222 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xplatform_info.h
@@ -0,0 +1,109 @@ +/****************************************************************************** +* +* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xplatform_info.h +* +* @addtogroup common_platform_info APIs to Get Platform Information +* +* The xplatform_info.h file contains definitions for various available Xilinx® +* platforms. Also, it contains prototype of APIs, which can be used to get the +* platform information. +* +* @{ +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- --------- ------------------------------------------------------- +* 6.4 ms 05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info +* function for PMUFW. +* </pre> +* +******************************************************************************/ + +#ifndef XPLATFORM_INFO_H /* prevent circular inclusions */ +#define XPLATFORM_INFO_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" + +/************************** Constant Definitions *****************************/ + +#define XPAR_CSU_BASEADDR 0xFFCA0000U +#define XPAR_CSU_VER_OFFSET 0x00000044U + +#define XPLAT_ZYNQ_ULTRA_MP_SILICON 0x0 +#define XPLAT_ZYNQ_ULTRA_MP 0x1 +#define XPLAT_ZYNQ_ULTRA_MPVEL 0x2 +#define XPLAT_ZYNQ_ULTRA_MPQEMU 0x3 +#define XPLAT_ZYNQ 0x4 +#define XPLAT_MICROBLAZE 0x5 + +#define XPS_VERSION_1 0x0 +#define XPS_VERSION_2 0x1 + +#define XPLAT_INFO_MASK (0xF) +#define XPLAT_INFO_SHIFT (0xC) +#define XPS_VERSION_INFO_MASK (0xF) + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + + +u32 XGetPlatform_Info(); + +#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU) +u32 XGetPSVersion_Info(); +#endif + +#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) +u32 XGet_Zynq_UltraMp_Platform_info(); +#endif +/************************** Function Prototypes ******************************/ + + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** +* @} End of "addtogroup common_platform_info". +*/
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xpseudo_asm.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xpseudo_asm.h new file mode 100644 index 0000000..48e180e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xpseudo_asm.h
@@ -0,0 +1,69 @@ +/****************************************************************************** +* +* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xpseudo_asm.h +* +* @addtogroup a53_64_specific Cortex A53 64bit Processor Specific Include Files +* +* The xpseudo_asm.h includes xreg_cortexa53.h and xpseudo_asm_gcc.h. +* The xreg_cortexa53.h file contains definitions for inline assembler code. +* It provides inline definitions for Cortex A53 GPRs, SPRs and floating point +* registers. +* +* The xpseudo_asm_gcc.h contains the definitions for the most often used inline +* assembler instructions, available as macros. These can be very useful for +* tasks such as setting or getting special purpose registers, synchronization, +* or cache manipulation etc. These inline assembler instructions can be used +* from drivers and user applications written in C. +* +* @{ +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ----------------------------------------------- +* 5.00 pkp 05/29/14 First release +* </pre> +* +******************************************************************************/ +#ifndef XPSEUDO_ASM_H +#define XPSEUDO_ASM_H +#include "xreg_cortexa53.h" +#include "xpseudo_asm_gcc.h" + +#endif /* XPSEUDO_ASM_H */ +/** +* @} End of "addtogroup a53_64_specific". +*/
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xpseudo_asm_gcc.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xpseudo_asm_gcc.h new file mode 100644 index 0000000..1b67263 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xpseudo_asm_gcc.h
@@ -0,0 +1,249 @@ +/****************************************************************************** +* +* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xpseudo_asm_gcc.h +* +* This header file contains macros for using inline assembler code. It is +* written specifically for the GNU compiler. +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- -------- -------- ----------------------------------------------- +* 5.00 pkp 05/21/14 First release +* 6.0 mus 07/27/16 Consolidated file for a53,a9 and r5 processors +* </pre> +* +******************************************************************************/ + +#ifndef XPSEUDO_ASM_GCC_H /* prevent circular inclusions */ +#define XPSEUDO_ASM_GCC_H /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/* necessary for pre-processor */ +#define stringify(s) tostring(s) +#define tostring(s) #s + +#if defined (__aarch64__) +/* pseudo assembler instructions */ +#define mfcpsr() ({u32 rval = 0U; \ + asm volatile("mrs %0, DAIF" : "=r" (rval));\ + rval;\ + }) + +#define mtcpsr(v) __asm__ __volatile__ ("msr DAIF, %0" : : "r" (v)) + +#define cpsiei() //__asm__ __volatile__("cpsie i\n") +#define cpsidi() //__asm__ __volatile__("cpsid i\n") + +#define cpsief() //__asm__ __volatile__("cpsie f\n") +#define cpsidf() //__asm__ __volatile__("cpsid f\n") + + + +#define mtgpr(rn, v) /*__asm__ __volatile__(\ + "mov r" stringify(rn) ", %0 \n"\ + : : "r" (v)\ + )*/ + +#define mfgpr(rn) /*({u32 rval; \ + __asm__ __volatile__(\ + "mov %0,r" stringify(rn) "\n"\ + : "=r" (rval)\ + );\ + rval;\ + })*/ + +/* memory synchronization operations */ + +/* Instruction Synchronization Barrier */ +#define isb() __asm__ __volatile__ ("isb sy") + +/* Data Synchronization Barrier */ +#define dsb() __asm__ __volatile__("dsb sy") + +/* Data Memory Barrier */ +#define dmb() __asm__ __volatile__("dmb sy") + + +/* Memory Operations */ +#define ldr(adr) ({u64 rval; \ + __asm__ __volatile__(\ + "ldr %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) + +#else + +/* pseudo assembler instructions */ +#define mfcpsr() ({u32 rval = 0U; \ + __asm__ __volatile__(\ + "mrs %0, cpsr\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) + +#define mtcpsr(v) __asm__ __volatile__(\ + "msr cpsr,%0\n"\ + : : "r" (v)\ + ) + +#define cpsiei() __asm__ __volatile__("cpsie i\n") +#define cpsidi() __asm__ __volatile__("cpsid i\n") + +#define cpsief() __asm__ __volatile__("cpsie f\n") +#define cpsidf() __asm__ __volatile__("cpsid f\n") + + + +#define mtgpr(rn, v) __asm__ __volatile__(\ + "mov r" stringify(rn) ", %0 \n"\ + : : "r" (v)\ + ) + +#define mfgpr(rn) ({u32 rval; \ + __asm__ __volatile__(\ + "mov %0,r" stringify(rn) "\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) + +/* memory synchronization operations */ + +/* Instruction Synchronization Barrier */ +#define isb() __asm__ __volatile__ ("isb" : : : "memory") + +/* Data Synchronization Barrier */ +#define dsb() __asm__ __volatile__ ("dsb" : : : "memory") + +/* Data Memory Barrier */ +#define dmb() __asm__ __volatile__ ("dmb" : : : "memory") + + +/* Memory Operations */ +#define ldr(adr) ({u32 rval; \ + __asm__ __volatile__(\ + "ldr %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) + +#endif + +#define ldrb(adr) ({u8 rval; \ + __asm__ __volatile__(\ + "ldrb %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) + +#define str(adr, val) __asm__ __volatile__(\ + "str %0,[%1]\n"\ + : : "r" (val), "r" (adr)\ + ) + +#define strb(adr, val) __asm__ __volatile__(\ + "strb %0,[%1]\n"\ + : : "r" (val), "r" (adr)\ + ) + +/* Count leading zeroes (clz) */ +#define clz(arg) ({u8 rval; \ + __asm__ __volatile__(\ + "clz %0,%1"\ + : "=r" (rval) : "r" (arg)\ + );\ + rval;\ + }) + +#if defined (__aarch64__) +#define mtcpdc(reg,val) __asm__ __volatile__("dc " #reg ",%0" : : "r" (val)) +#define mtcpic(reg,val) __asm__ __volatile__("ic " #reg ",%0" : : "r" (val)) + +#define mtcpicall(reg) __asm__ __volatile__("ic " #reg) +#define mtcptlbi(reg) __asm__ __volatile__("tlbi " #reg) +#define mtcpat(reg,val) __asm__ __volatile__("at " #reg ",%0" : : "r" (val)) +/* CP15 operations */ +#define mfcp(reg) ({u64 rval = 0U;\ + __asm__ __volatile__("mrs %0, " #reg : "=r" (rval));\ + rval;\ + }) + +#define mtcp(reg,val) __asm__ __volatile__("msr " #reg ",%0" : : "r" (val)) + +#else +/* CP15 operations */ +#define mtcp(rn, v) __asm__ __volatile__(\ + "mcr " rn "\n"\ + : : "r" (v)\ + ); + +#define mfcp(rn) ({u32 rval = 0U; \ + __asm__ __volatile__(\ + "mrc " rn "\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) +#endif + +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XPSEUDO_ASM_GCC_H */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xreg_cortexa53.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xreg_cortexa53.h new file mode 100644 index 0000000..ce9af4c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xreg_cortexa53.h
@@ -0,0 +1,182 @@ +/****************************************************************************** +* +* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xreg_cortexa53.h +* +* This header file contains definitions for using inline assembler code. It is +* written specifically for the GNU compiler. +* +* All of the ARM Cortex A53 GPRs, SPRs, and Debug Registers are defined along +* with the positions of the bits within the registers. +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- -------- -------- ----------------------------------------------- +* 5.00 pkp 05/29/14 First release +* </pre> +* +******************************************************************************/ +#ifndef XREG_CORTEXA53_H +#define XREG_CORTEXA53_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + + +/* GPRs */ +#define XREG_GPR0 x0 +#define XREG_GPR1 x1 +#define XREG_GPR2 x2 +#define XREG_GPR3 x3 +#define XREG_GPR4 x4 +#define XREG_GPR5 x5 +#define XREG_GPR6 x6 +#define XREG_GPR7 x7 +#define XREG_GPR8 x8 +#define XREG_GPR9 x9 +#define XREG_GPR10 x10 +#define XREG_GPR11 x11 +#define XREG_GPR12 x12 +#define XREG_GPR13 x13 +#define XREG_GPR14 x14 +#define XREG_GPR15 x15 +#define XREG_GPR16 x16 +#define XREG_GPR17 x17 +#define XREG_GPR18 x18 +#define XREG_GPR19 x19 +#define XREG_GPR20 x20 +#define XREG_GPR21 x21 +#define XREG_GPR22 x22 +#define XREG_GPR23 x23 +#define XREG_GPR24 x24 +#define XREG_GPR25 x25 +#define XREG_GPR26 x26 +#define XREG_GPR27 x27 +#define XREG_GPR28 x28 +#define XREG_GPR29 x29 +#define XREG_GPR30 x30 +#define XREG_CPSR cpsr + +/* Current Processor Status Register (CPSR) Bits */ +#define XREG_CPSR_MODE_BITS 0x1F +#define XREG_CPSR_EL3h_MODE 0xD +#define XREG_CPSR_EL3t_MODE 0xC +#define XREG_CPSR_EL2h_MODE 0x9 +#define XREG_CPSR_EL2t_MODE 0x8 +#define XREG_CPSR_EL1h_MODE 0x5 +#define XREG_CPSR_EL1t_MODE 0x4 +#define XREG_CPSR_EL0t_MODE 0x0 + +#define XREG_CPSR_IRQ_ENABLE 0x80 +#define XREG_CPSR_FIQ_ENABLE 0x40 + +#define XREG_CPSR_N_BIT 0x80000000U +#define XREG_CPSR_Z_BIT 0x40000000U +#define XREG_CPSR_C_BIT 0x20000000U +#define XREG_CPSR_V_BIT 0x10000000U + +/* FPSID bits */ +#define XREG_FPSID_IMPLEMENTER_BIT (24U) +#define XREG_FPSID_IMPLEMENTER_MASK (0x000000FFU << FPSID_IMPLEMENTER_BIT) +#define XREG_FPSID_SOFTWARE (0X00000001U<<23U) +#define XREG_FPSID_ARCH_BIT (16U) +#define XREG_FPSID_ARCH_MASK (0x0000000FU << FPSID_ARCH_BIT) +#define XREG_FPSID_PART_BIT (8U) +#define XREG_FPSID_PART_MASK (0x000000FFU << FPSID_PART_BIT) +#define XREG_FPSID_VARIANT_BIT (4U) +#define XREG_FPSID_VARIANT_MASK (0x0000000FU << FPSID_VARIANT_BIT) +#define XREG_FPSID_REV_BIT (0U) +#define XREG_FPSID_REV_MASK (0x0000000FU << FPSID_REV_BIT) + +/* FPSCR bits */ +#define XREG_FPSCR_N_BIT (0X00000001U << 31U) +#define XREG_FPSCR_Z_BIT (0X00000001U << 30U) +#define XREG_FPSCR_C_BIT (0X00000001U << 29U) +#define XREG_FPSCR_V_BIT (0X00000001U << 28U) +#define XREG_FPSCR_QC (0X00000001U << 27U) +#define XREG_FPSCR_AHP (0X00000001U << 26U) +#define XREG_FPSCR_DEFAULT_NAN (0X00000001U << 25U) +#define XREG_FPSCR_FLUSHTOZERO (0X00000001U << 24U) +#define XREG_FPSCR_ROUND_NEAREST (0X00000000U << 22U) +#define XREG_FPSCR_ROUND_PLUSINF (0X00000001U << 22U) +#define XREG_FPSCR_ROUND_MINUSINF (0X00000002U << 22U) +#define XREG_FPSCR_ROUND_TOZERO (0X00000003U << 22U) +#define XREG_FPSCR_RMODE_BIT (22U) +#define XREG_FPSCR_RMODE_MASK (0X00000003U << FPSCR_RMODE_BIT) +#define XREG_FPSCR_STRIDE_BIT (20U) +#define XREG_FPSCR_STRIDE_MASK (0X00000003U << FPSCR_STRIDE_BIT) +#define XREG_FPSCR_LENGTH_BIT (16U) +#define XREG_FPSCR_LENGTH_MASK (0X00000007U << FPSCR_LENGTH_BIT) +#define XREG_FPSCR_IDC (0X00000001U << 7U) +#define XREG_FPSCR_IXC (0X00000001U << 4U) +#define XREG_FPSCR_UFC (0X00000001U << 3U) +#define XREG_FPSCR_OFC (0X00000001U << 2U) +#define XREG_FPSCR_DZC (0X00000001U << 1U) +#define XREG_FPSCR_IOC (0X00000001U << 0U) + +/* MVFR0 bits */ +#define XREG_MVFR0_RMODE_BIT (28U) +#define XREG_MVFR0_RMODE_MASK (0x0000000FU << XREG_MVFR0_RMODE_BIT) +#define XREG_MVFR0_SHORT_VEC_BIT (24U) +#define XREG_MVFR0_SHORT_VEC_MASK (0x0000000FU << XREG_MVFR0_SHORT_VEC_BIT) +#define XREG_MVFR0_SQRT_BIT (20U) +#define XREG_MVFR0_SQRT_MASK (0x0000000FU << XREG_MVFR0_SQRT_BIT) +#define XREG_MVFR0_DIVIDE_BIT (16U) +#define XREG_MVFR0_DIVIDE_MASK (0x0000000FU << XREG_MVFR0_DIVIDE_BIT) +#define XREG_MVFR0_EXEC_TRAP_BIT (0X00000012U) +#define XREG_MVFR0_EXEC_TRAP_MASK (0X0000000FU << XREG_MVFR0_EXEC_TRAP_BIT) +#define XREG_MVFR0_DP_BIT (8U) +#define XREG_MVFR0_DP_MASK (0x0000000FU << XREG_MVFR0_DP_BIT) +#define XREG_MVFR0_SP_BIT (4U) +#define XREG_MVFR0_SP_MASK (0x0000000FU << XREG_MVFR0_SP_BIT) +#define XREG_MVFR0_A_SIMD_BIT (0U) +#define XREG_MVFR0_A_SIMD_MASK (0x0000000FU << MVFR0_A_SIMD_BIT) + +/* FPEXC bits */ +#define XREG_FPEXC_EX (0X00000001U << 31U) +#define XREG_FPEXC_EN (0X00000001U << 30U) +#define XREG_FPEXC_DEX (0X00000001U << 29U) + + +#define XREG_CONTROL_DCACHE_BIT (0X00000001U<<2U) +#define XREG_CONTROL_ICACHE_BIT (0X00000001U<<12U) + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XREG_CORTEXA53_H */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xstatus.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xstatus.h new file mode 100644 index 0000000..9937475 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xstatus.h
@@ -0,0 +1,535 @@ +/****************************************************************************** +* +* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xstatus.h +* +* @addtogroup common_status_codes Xilinx® software status codes +* +* The xstatus.h file contains the Xilinx® software status codes.These codes are +* used throughout the Xilinx device drivers. +* +* @{ +******************************************************************************/ + +#ifndef XSTATUS_H /* prevent circular inclusions */ +#define XSTATUS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" + +/************************** Constant Definitions *****************************/ + +/*********************** Common statuses 0 - 500 *****************************/ +/** +@name Common Status Codes for All Device Drivers +@{ +*/ +#define XST_SUCCESS 0L +#define XST_FAILURE 1L +#define XST_DEVICE_NOT_FOUND 2L +#define XST_DEVICE_BLOCK_NOT_FOUND 3L +#define XST_INVALID_VERSION 4L +#define XST_DEVICE_IS_STARTED 5L +#define XST_DEVICE_IS_STOPPED 6L +#define XST_FIFO_ERROR 7L /*!< An error occurred during an + operation with a FIFO such as + an underrun or overrun, this + error requires the device to + be reset */ +#define XST_RESET_ERROR 8L /*!< An error occurred which requires + the device to be reset */ +#define XST_DMA_ERROR 9L /*!< A DMA error occurred, this error + typically requires the device + using the DMA to be reset */ +#define XST_NOT_POLLED 10L /*!< The device is not configured for + polled mode operation */ +#define XST_FIFO_NO_ROOM 11L /*!< A FIFO did not have room to put + the specified data into */ +#define XST_BUFFER_TOO_SMALL 12L /*!< The buffer is not large enough + to hold the expected data */ +#define XST_NO_DATA 13L /*!< There was no data available */ +#define XST_REGISTER_ERROR 14L /*!< A register did not contain the + expected value */ +#define XST_INVALID_PARAM 15L /*!< An invalid parameter was passed + into the function */ +#define XST_NOT_SGDMA 16L /*!< The device is not configured for + scatter-gather DMA operation */ +#define XST_LOOPBACK_ERROR 17L /*!< A loopback test failed */ +#define XST_NO_CALLBACK 18L /*!< A callback has not yet been + registered */ +#define XST_NO_FEATURE 19L /*!< Device is not configured with + the requested feature */ +#define XST_NOT_INTERRUPT 20L /*!< Device is not configured for + interrupt mode operation */ +#define XST_DEVICE_BUSY 21L /*!< Device is busy */ +#define XST_ERROR_COUNT_MAX 22L /*!< The error counters of a device + have maxed out */ +#define XST_IS_STARTED 23L /*!< Used when part of device is + already started i.e. + sub channel */ +#define XST_IS_STOPPED 24L /*!< Used when part of device is + already stopped i.e. + sub channel */ +#define XST_DATA_LOST 26L /*!< Driver defined error */ +#define XST_RECV_ERROR 27L /*!< Generic receive error */ +#define XST_SEND_ERROR 28L /*!< Generic transmit error */ +#define XST_NOT_ENABLED 29L /*!< A requested service is not + available because it has not + been enabled */ +/** @} */ +/***************** Utility Component statuses 401 - 500 *********************/ +/** +@name Utility Component Status Codes 401 - 500 +@{ +*/ +#define XST_MEMTEST_FAILED 401L /*!< Memory test failed */ + +/** @} */ +/***************** Common Components statuses 501 - 1000 *********************/ +/** +@name Packet Fifo Status Codes 501 - 510 +@{ +*/ +/********************* Packet Fifo statuses 501 - 510 ************************/ + +#define XST_PFIFO_LACK_OF_DATA 501L /*!< Not enough data in FIFO */ +#define XST_PFIFO_NO_ROOM 502L /*!< Not enough room in FIFO */ +#define XST_PFIFO_BAD_REG_VALUE 503L /*!< Self test, a register value + was invalid after reset */ +#define XST_PFIFO_ERROR 504L /*!< Generic packet FIFO error */ +#define XST_PFIFO_DEADLOCK 505L /*!< Packet FIFO is reporting + * empty and full simultaneously + */ +/** @} */ +/** +@name DMA Status Codes 511 - 530 +@{ +*/ +/************************** DMA statuses 511 - 530 ***************************/ + +#define XST_DMA_TRANSFER_ERROR 511L /*!< Self test, DMA transfer + failed */ +#define XST_DMA_RESET_REGISTER_ERROR 512L /*!< Self test, a register value + was invalid after reset */ +#define XST_DMA_SG_LIST_EMPTY 513L /*!< Scatter gather list contains + no buffer descriptors ready + to be processed */ +#define XST_DMA_SG_IS_STARTED 514L /*!< Scatter gather not stopped */ +#define XST_DMA_SG_IS_STOPPED 515L /*!< Scatter gather not running */ +#define XST_DMA_SG_LIST_FULL 517L /*!< All the buffer desciptors of + the scatter gather list are + being used */ +#define XST_DMA_SG_BD_LOCKED 518L /*!< The scatter gather buffer + descriptor which is to be + copied over in the scatter + list is locked */ +#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /*!< No buffer descriptors have been + put into the scatter gather + list to be commited */ +#define XST_DMA_SG_COUNT_EXCEEDED 521L /*!< The packet count threshold + specified was larger than the + total # of buffer descriptors + in the scatter gather list */ +#define XST_DMA_SG_LIST_EXISTS 522L /*!< The scatter gather list has + already been created */ +#define XST_DMA_SG_NO_LIST 523L /*!< No scatter gather list has + been created */ +#define XST_DMA_SG_BD_NOT_COMMITTED 524L /*!< The buffer descriptor which was + being started was not committed + to the list */ +#define XST_DMA_SG_NO_DATA 525L /*!< The buffer descriptor to start + has already been used by the + hardware so it can't be reused + */ +#define XST_DMA_SG_LIST_ERROR 526L /*!< General purpose list access + error */ +#define XST_DMA_BD_ERROR 527L /*!< General buffer descriptor + error */ +/** @} */ +/** +@name IPIF Status Codes Codes 531 - 550 +@{ +*/ +/************************** IPIF statuses 531 - 550 ***************************/ + +#define XST_IPIF_REG_WIDTH_ERROR 531L /*!< An invalid register width + was passed into the function */ +#define XST_IPIF_RESET_REGISTER_ERROR 532L /*!< The value of a register at + reset was not valid */ +#define XST_IPIF_DEVICE_STATUS_ERROR 533L /*!< A write to the device interrupt + status register did not read + back correctly */ +#define XST_IPIF_DEVICE_ACK_ERROR 534L /*!< The device interrupt status + register did not reset when + acked */ +#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /*!< The device interrupt enable + register was not updated when + other registers changed */ +#define XST_IPIF_IP_STATUS_ERROR 536L /*!< A write to the IP interrupt + status register did not read + back correctly */ +#define XST_IPIF_IP_ACK_ERROR 537L /*!< The IP interrupt status register + did not reset when acked */ +#define XST_IPIF_IP_ENABLE_ERROR 538L /*!< IP interrupt enable register was + not updated correctly when other + registers changed */ +#define XST_IPIF_DEVICE_PENDING_ERROR 539L /*!< The device interrupt pending + register did not indicate the + expected value */ +#define XST_IPIF_DEVICE_ID_ERROR 540L /*!< The device interrupt ID register + did not indicate the expected + value */ +#define XST_IPIF_ERROR 541L /*!< Generic ipif error */ +/** @} */ + +/****************** Device specific statuses 1001 - 4095 *********************/ +/** +@name Ethernet Status Codes 1001 - 1050 +@{ +*/ +/********************* Ethernet statuses 1001 - 1050 *************************/ + +#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /*!< Memory space is not big enough + * to hold the minimum number of + * buffers or descriptors */ +#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /*!< Memory allocation failed */ +#define XST_EMAC_MII_READ_ERROR 1003L /*!< MII read error */ +#define XST_EMAC_MII_BUSY 1004L /*!< An MII operation is in progress */ +#define XST_EMAC_OUT_OF_BUFFERS 1005L /*!< Driver is out of buffers */ +#define XST_EMAC_PARSE_ERROR 1006L /*!< Invalid driver init string */ +#define XST_EMAC_COLLISION_ERROR 1007L /*!< Excess deferral or late + * collision on polled send */ +/** @} */ +/** +@name UART Status Codes 1051 - 1075 +@{ +*/ +/*********************** UART statuses 1051 - 1075 ***************************/ +#define XST_UART + +#define XST_UART_INIT_ERROR 1051L +#define XST_UART_START_ERROR 1052L +#define XST_UART_CONFIG_ERROR 1053L +#define XST_UART_TEST_FAIL 1054L +#define XST_UART_BAUD_ERROR 1055L +#define XST_UART_BAUD_RANGE 1056L + +/** @} */ +/** +@name IIC Status Codes 1076 - 1100 +@{ +*/ +/************************ IIC statuses 1076 - 1100 ***************************/ + +#define XST_IIC_SELFTEST_FAILED 1076 /*!< self test failed */ +#define XST_IIC_BUS_BUSY 1077 /*!< bus found busy */ +#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /*!< mastersend attempted with */ + /* general call address */ +#define XST_IIC_STAND_REG_RESET_ERROR 1079 /*!< A non parameterizable reg */ + /* value after reset not valid */ +#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /*!< Tx fifo included in design */ + /* value after reset not valid */ +#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /*!< Rx fifo included in design */ + /* value after reset not valid */ +#define XST_IIC_TBA_REG_RESET_ERROR 1082 /*!< 10 bit addr incl in design */ + /* value after reset not valid */ +#define XST_IIC_CR_READBACK_ERROR 1083 /*!< Read of the control register */ + /* didn't return value written */ +#define XST_IIC_DTR_READBACK_ERROR 1084 /*!< Read of the data Tx reg */ + /* didn't return value written */ +#define XST_IIC_DRR_READBACK_ERROR 1085 /*!< Read of the data Receive reg */ + /* didn't return value written */ +#define XST_IIC_ADR_READBACK_ERROR 1086 /*!< Read of the data Tx reg */ + /* didn't return value written */ +#define XST_IIC_TBA_READBACK_ERROR 1087 /*!< Read of the 10 bit addr reg */ + /* didn't return written value */ +#define XST_IIC_NOT_SLAVE 1088 /*!< The device isn't a slave */ +/** @} */ +/** +@name ATMC Status Codes 1101 - 1125 +@{ +*/ +/*********************** ATMC statuses 1101 - 1125 ***************************/ + +#define XST_ATMC_ERROR_COUNT_MAX 1101L /*!< the error counters in the ATM + controller hit the max value + which requires the statistics + to be cleared */ +/** @} */ +/** +@name Flash Status Codes 1126 - 1150 +@{ +*/ +/*********************** Flash statuses 1126 - 1150 **************************/ + +#define XST_FLASH_BUSY 1126L /*!< Flash is erasing or programming + */ +#define XST_FLASH_READY 1127L /*!< Flash is ready for commands */ +#define XST_FLASH_ERROR 1128L /*!< Flash had detected an internal + error. Use XFlash_DeviceControl + to retrieve device specific codes + */ +#define XST_FLASH_ERASE_SUSPENDED 1129L /*!< Flash is in suspended erase state + */ +#define XST_FLASH_WRITE_SUSPENDED 1130L /*!< Flash is in suspended write state + */ +#define XST_FLASH_PART_NOT_SUPPORTED 1131L /*!< Flash type not supported by + driver */ +#define XST_FLASH_NOT_SUPPORTED 1132L /*!< Operation not supported */ +#define XST_FLASH_TOO_MANY_REGIONS 1133L /*!< Too many erase regions */ +#define XST_FLASH_TIMEOUT_ERROR 1134L /*!< Programming or erase operation + aborted due to a timeout */ +#define XST_FLASH_ADDRESS_ERROR 1135L /*!< Accessed flash outside its + addressible range */ +#define XST_FLASH_ALIGNMENT_ERROR 1136L /*!< Write alignment error */ +#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /*!< Couldn't return immediately from + write/erase function with + XFL_NON_BLOCKING_WRITE/ERASE + option cleared */ +#define XST_FLASH_CFI_QUERY_ERROR 1138L /*!< Failed to query the device */ +/** @} */ +/** +@name SPI Status Codes 1151 - 1175 +@{ +*/ +/*********************** SPI statuses 1151 - 1175 ****************************/ + +#define XST_SPI_MODE_FAULT 1151 /*!< master was selected as slave */ +#define XST_SPI_TRANSFER_DONE 1152 /*!< data transfer is complete */ +#define XST_SPI_TRANSMIT_UNDERRUN 1153 /*!< slave underruns transmit register */ +#define XST_SPI_RECEIVE_OVERRUN 1154 /*!< device overruns receive register */ +#define XST_SPI_NO_SLAVE 1155 /*!< no slave has been selected yet */ +#define XST_SPI_TOO_MANY_SLAVES 1156 /*!< more than one slave is being + * selected */ +#define XST_SPI_NOT_MASTER 1157 /*!< operation is valid only as master */ +#define XST_SPI_SLAVE_ONLY 1158 /*!< device is configured as slave-only + */ +#define XST_SPI_SLAVE_MODE_FAULT 1159 /*!< slave was selected while disabled */ +#define XST_SPI_SLAVE_MODE 1160 /*!< device has been addressed as slave */ +#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /*!< device received data in slave mode */ + +#define XST_SPI_COMMAND_ERROR 1162 /*!< unrecognised command - qspi only */ +#define XST_SPI_POLL_DONE 1163 /*!< controller completed polling the + device for status */ +/** @} */ +/** +@name OPB Arbiter Status Codes 1176 - 1200 +@{ +*/ +/********************** OPB Arbiter statuses 1176 - 1200 *********************/ + +#define XST_OPBARB_INVALID_PRIORITY 1176 /*!< the priority registers have either + * one master assigned to two or more + * priorities, or one master not + * assigned to any priority + */ +#define XST_OPBARB_NOT_SUSPENDED 1177 /*!< an attempt was made to modify the + * priority levels without first + * suspending the use of priority + * levels + */ +#define XST_OPBARB_PARK_NOT_ENABLED 1178 /*!< bus parking by id was enabled but + * bus parking was not enabled + */ +#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /*!< the arbiter must be in fixed + * priority mode to allow the + * priorities to be changed + */ +/** @} */ +/** +@name INTC Status Codes 1201 - 1225 +@{ +*/ +/************************ Intc statuses 1201 - 1225 **************************/ + +#define XST_INTC_FAIL_SELFTEST 1201 /*!< self test failed */ +#define XST_INTC_CONNECT_ERROR 1202 /*!< interrupt already in use */ +/** @} */ +/** +@name TmrCtr Status Codes 1226 - 1250 +@{ +*/ +/********************** TmrCtr statuses 1226 - 1250 **************************/ + +#define XST_TMRCTR_TIMER_FAILED 1226 /*!< self test failed */ +/** @} */ +/** +@name WdtTb Status Codes 1251 - 1275 +@{ +*/ +/********************** WdtTb statuses 1251 - 1275 ***************************/ + +#define XST_WDTTB_TIMER_FAILED 1251L +/** @} */ +/** +@name PlbArb status Codes 1276 - 1300 +@{ +*/ +/********************** PlbArb statuses 1276 - 1300 **************************/ + +#define XST_PLBARB_FAIL_SELFTEST 1276L +/** @} */ +/** +@name Plb2Opb Status Codes 1301 - 1325 +@{ +*/ +/********************** Plb2Opb statuses 1301 - 1325 *************************/ + +#define XST_PLB2OPB_FAIL_SELFTEST 1301L +/** @} */ +/** +@name Opb2Plb Status 1326 - 1350 +@{ +*/ +/********************** Opb2Plb statuses 1326 - 1350 *************************/ + +#define XST_OPB2PLB_FAIL_SELFTEST 1326L +/** @} */ +/** +@name SysAce Status Codes 1351 - 1360 +@{ +*/ +/********************** SysAce statuses 1351 - 1360 **************************/ + +#define XST_SYSACE_NO_LOCK 1351L /*!< No MPU lock has been granted */ +/** @} */ +/** +@name PCI Bridge Status Codes 1361 - 1375 +@{ +*/ +/********************** PCI Bridge statuses 1361 - 1375 **********************/ + +#define XST_PCI_INVALID_ADDRESS 1361L +/** @} */ +/** +@name FlexRay Constants 1400 - 1409 +@{ +*/ +/********************** FlexRay constants 1400 - 1409 *************************/ + +#define XST_FR_TX_ERROR 1400 +#define XST_FR_TX_BUSY 1401 +#define XST_FR_BUF_LOCKED 1402 +#define XST_FR_NO_BUF 1403 +/** @} */ +/** +@name USB constants 1410 - 1420 +@{ +*/ +/****************** USB constants 1410 - 1420 *******************************/ + +#define XST_USB_ALREADY_CONFIGURED 1410 +#define XST_USB_BUF_ALIGN_ERROR 1411 +#define XST_USB_NO_DESC_AVAILABLE 1412 +#define XST_USB_BUF_TOO_BIG 1413 +#define XST_USB_NO_BUF 1414 +/** @} */ +/** +@name HWICAP constants 1421 - 1429 +@{ +*/ +/****************** HWICAP constants 1421 - 1429 *****************************/ + +#define XST_HWICAP_WRITE_DONE 1421 + +/** @} */ +/** +@name AXI VDMA constants 1430 - 1440 +@{ +*/ +/****************** AXI VDMA constants 1430 - 1440 *****************************/ + +#define XST_VDMA_MISMATCH_ERROR 1430 +/** @} */ +/** +@name NAND Flash Status Codes 1441 - 1459 +@{ +*/ +/*********************** NAND Flash statuses 1441 - 1459 *********************/ + +#define XST_NAND_BUSY 1441L /*!< Flash is erasing or + * programming + */ +#define XST_NAND_READY 1442L /*!< Flash is ready for commands + */ +#define XST_NAND_ERROR 1443L /*!< Flash had detected an + * internal error. + */ +#define XST_NAND_PART_NOT_SUPPORTED 1444L /*!< Flash type not supported by + * driver + */ +#define XST_NAND_OPT_NOT_SUPPORTED 1445L /*!< Operation not supported + */ +#define XST_NAND_TIMEOUT_ERROR 1446L /*!< Programming or erase + * operation aborted due to a + * timeout + */ +#define XST_NAND_ADDRESS_ERROR 1447L /*!< Accessed flash outside its + * addressible range + */ +#define XST_NAND_ALIGNMENT_ERROR 1448L /*!< Write alignment error + */ +#define XST_NAND_PARAM_PAGE_ERROR 1449L /*!< Failed to read parameter + * page of the device + */ +#define XST_NAND_CACHE_ERROR 1450L /*!< Flash page buffer error + */ + +#define XST_NAND_WRITE_PROTECTED 1451L /*!< Flash is write protected + */ +/** @} */ + +/**************************** Type Definitions *******************************/ + +typedef s32 XStatus; + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** +* @} End of "addtogroup common_status_codes". +*/
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xtime_l.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xtime_l.c new file mode 100644 index 0000000..b04adef --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xtime_l.c
@@ -0,0 +1,144 @@ +/****************************************************************************** +* +* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xtime_l.c +* +* This file contains low level functions to get/set time from the Global Timer +* register in the ARM Cortex A53 MP core. +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ------ -------- --------------------------------------------------- +* 5.00 pkp 05/29/14 First release +* 5.05 pkp 04/13/16 Added XTime_StartTimer API to start the global timer +* counter if it is disabled. Also XTime_GetTime calls +* this API to ensure the global timer counter is enabled +* 6.02 pkp 01/22/17 Added support for EL1 non-secure +* </pre> +* +* @note None. +* +******************************************************************************/ +/***************************** Include Files *********************************/ + +#include "xtime_l.h" +#include "xpseudo_asm.h" +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" +#include "bspconfig.h" + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +/****************************************************************************/ +/** +* @brief Start the 64-bit physical timer counter. +* +* @param None. +* +* @return None. +* +* @note The timer is initialized only if it is disabled. If the timer is +* already running this function does not perform any operation. This +* API is effective only if BSP is built for EL3. For EL1 Non-secure, +* it simply exits. +* +****************************************************************************/ +void XTime_StartTimer(void) +{ + if (EL3 == 1){ + /* Enable the global timer counter only if it is disabled */ + if(((Xil_In32(XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_CNT_CNTRL_REG_OFFSET)) + & XIOU_SCNTRS_CNT_CNTRL_REG_EN_MASK) != + XIOU_SCNTRS_CNT_CNTRL_REG_EN){ + /*write frequency to System Time Stamp Generator Register*/ + Xil_Out32((XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_FREQ_REG_OFFSET), + XIOU_SCNTRS_FREQ); + /*Enable the timer/counter*/ + Xil_Out32((XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_CNT_CNTRL_REG_OFFSET) + ,XIOU_SCNTRS_CNT_CNTRL_REG_EN); + } + } +} +/****************************************************************************/ +/** +* @brief Timer of A53 runs continuously and the time can not be set as +* desired. This API doesn't contain anything. It is defined to have +* uniformity across platforms. +* +* @param Xtime_Global: 64bit value to be written to the physical timer +* counter register. Since API does not do anything, the value is +* not utilized. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void XTime_SetTime(XTime Xtime_Global) +{ + (void) Xtime_Global; +/*As the generic timer of A53 runs constantly time can not be set as desired +so the API is left unimplemented*/ +} + +/****************************************************************************/ +/** +* @brief Get the time from the physical timer counter register. +* +* @param Xtime_Global: Pointer to the 64-bit location to be updated with the +* current value of physical timer counter register. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void XTime_GetTime(XTime *Xtime_Global) +{ + if (EL3 == 1) + /* Start global timer counter, it will only be enabled if it is disabled */ + XTime_StartTimer(); + + *Xtime_Global = mfcp(CNTPCT_EL0); +}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xtime_l.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xtime_l.h new file mode 100644 index 0000000..a36d7fa --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xtime_l.h
@@ -0,0 +1,105 @@ +/****************************************************************************** +* +* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xtime_l.h +* +* @addtogroup a53_64_time_apis Cortex A53 64bit Mode Time Functions +* xtime_l.h provides access to the 64-bit physical timer counter. +* +* @{ +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ------ -------- --------------------------------------------------- +* 5.00 pkp 05/29/14 First release +* 6.6 srm 10/23/17 Updated the macros to support user configurable sleep +* implementation +* </pre> +* +* +******************************************************************************/ + +#ifndef XTIME_H /* prevent circular inclusions */ +#define XTIME_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xparameters.h" + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +typedef u64 XTime; + +/************************** Constant Definitions *****************************/ + +#if defined (SLEEP_TIMER_BASEADDR) +#define COUNTS_PER_SECOND SLEEP_TIMER_FREQUENCY +#else +#define COUNTS_PER_SECOND XPAR_CPU_CORTEXA53_0_TIMESTAMP_CLK_FREQ +#endif + +#if defined (XSLEEP_TIMER_IS_DEFAULT_TIMER) +#pragma message ("For the sleep routines, Global timer is being used") +#endif + +#define XIOU_SCNTRS_BASEADDR 0xFF260000U +#define XIOU_SCNTRS_CNT_CNTRL_REG_OFFSET 0x00000000U +#define XIOU_SCNTRS_FREQ_REG_OFFSET 0x00000020U +#define XIOU_SCNTRS_FREQ XPAR_CPU_CORTEXA53_0_TIMESTAMP_CLK_FREQ +#define XIOU_SCNTRS_CNT_CNTRL_REG_EN 0x00000001U +#define XIOU_SCNTRS_CNT_CNTRL_REG_EN_MASK 0x00000001U +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +void XTime_StartTimer(void); +void XTime_SetTime(XTime Xtime_Global); +void XTime_GetTime(XTime *Xtime_Global); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XTIME_H */ +/** +* @} End of "addtogroup a53_64_time_apis". +*/