Update Zynq, MPSoc Cortex-A53 and MPSoc Cortex-R5 demo projects to build with the 18.1 version of the Xilinx SDK - building BUT NOT YET TESTED.
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.cproject b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.cproject index 805e98f..fc930db 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.cproject +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.cproject
@@ -1,8 +1,8 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> <storageModule moduleId="org.eclipse.cdt.core.settings"> - <cconfiguration id="org.eclipse.cdt.core.default.config.690704917"> - <storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.690704917" moduleId="org.eclipse.cdt.core.settings" name="Configuration"> + <cconfiguration id="org.eclipse.cdt.core.default.config.911506109"> + <storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.911506109" moduleId="org.eclipse.cdt.core.settings" name="Configuration"> <externalSettings/> <extensions/> </storageModule>
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.project b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.project index ed0ff0f..7960aa3 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.project +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.project
@@ -1,7 +1,7 @@ <?xml version="1.0" encoding="UTF-8"?> <projectDescription> <name>RTOSDemo_R5_bsp</name> - <comment>Created by SDK v2016.4</comment> + <comment>Created by SDK v2018.1</comment> <projects> </projects> <buildSpec>
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/Makefile index 071f646..610ec1a 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/Makefile +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/Makefile
@@ -16,16 +16,20 @@ libs: $(addsuffix /make.libs,$(SUBDIRS)) +clean: $(addsuffix /make.clean,$(SUBDIRS)) + $(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a cp -f $< $@ %/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,) @echo "Running Make include in $(subst /make.include,,$@)" - $(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=armr5-none-eabi-gcc" "ARCHIVER=armr5-none-eabi-ar" "COMPILER_FLAGS= -O2 -c -mcpu=cortex-r5" "EXTRA_COMPILER_FLAGS=-g -DARMR5" + $(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=armr5-none-eabi-gcc" "ARCHIVER=armr5-none-eabi-ar" "COMPILER_FLAGS= -O2 -c -mcpu=cortex-r5" "EXTRA_COMPILER_FLAGS=-g -DARMR5 -Wall -Wextra -mfloat-abi=hard -mfpu=vfpv3-d16" %/make.libs: include @echo "Running Make libs in $(subst /make.libs,,$@)" - $(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=armr5-none-eabi-gcc" "ARCHIVER=armr5-none-eabi-ar" "COMPILER_FLAGS= -O2 -c -mcpu=cortex-r5" "EXTRA_COMPILER_FLAGS=-g -DARMR5" + $(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=armr5-none-eabi-gcc" "ARCHIVER=armr5-none-eabi-ar" "COMPILER_FLAGS= -O2 -c -mcpu=cortex-r5" "EXTRA_COMPILER_FLAGS=-g -DARMR5 -Wall -Wextra -mfloat-abi=hard -mfpu=vfpv3-d16" +%/make.clean: + $(MAKE) -C $(subst /make.clean,,$@) -s clean clean: rm -f ${PROCESSOR}/lib/libxil.a
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/include/xparameters.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/include/xparameters.h index c85fe0a..38c98f9 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/include/xparameters.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/include/xparameters.h
@@ -1,20 +1,23 @@ +#ifndef XPARAMETERS_H /* prevent circular inclusions */ +#define XPARAMETERS_H /* by using protection macros */ + /* Definition for CPU ID */ -#define XPAR_CPU_ID 0 +#define XPAR_CPU_ID 0U /* Definitions for peripheral PSU_CORTEXR5_0 */ -#define XPAR_PSU_CORTEXR5_0_CPU_CLK_FREQ_HZ 499994995 +#define XPAR_PSU_CORTEXR5_0_CPU_CLK_FREQ_HZ 499950000 /******************************************************************/ /* Canonical definitions for peripheral PSU_CORTEXR5_0 */ -#define XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ 499994995 +#define XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ 499950000 /******************************************************************/ /* Definition for PSS REF CLK FREQUENCY */ -#define XPAR_PSU_PSS_REF_CLK_FREQ_HZ 33333000U +#define XPAR_PSU_PSS_REF_CLK_FREQ_HZ 33330000U #include "xparameters_ps.h" @@ -22,15 +25,9 @@ /******************************************************************/ -/* - * Definitions of PSU_TTC_3 counter 0 base address and frequency used - * by sleep and usleep APIs - */ - -#define SLEEP_TIMER_BASEADDR 0xFF140000 -#define SLEEP_TIMER_FREQUENCY 100000000 - -/******************************************************************/ + /*Definitions for peripheral PSU_R5_DDR_1 */ +#define XPAR_PSU_R5_DDR_1_S_AXI_BASEADDR 0x0 +#define XPAR_PSU_R5_DDR_1_S_AXI_HIGHADDR 0x7fffffff /* Number of Fabric Resets */ @@ -41,190 +38,223 @@ /******************************************************************/ +/* Platform specific definitions */ +#define PLATFORM_ZYNQMP + +/* Definitions for debug logic configuration in lockstep mode */ +#define LOCKSTEP_MODE_DEBUG 0U + +/* Definitions for sleep timer configuration */ +#define SLEEP_TIMER_BASEADDR XPAR_PSU_TTC_9_BASEADDR +#define SLEEP_TIMER_FREQUENCY XPAR_PSU_TTC_9_TTC_CLK_FREQ_HZ +#define XSLEEP_TTC_INSTANCE 3 +#define XSLEEP_TIMER_IS_DEFAULT_TIMER + + +/******************************************************************/ +/* Definitions for driver AVBUF */ +#define XPAR_XAVBUF_NUM_INSTANCES 1 + +/* Definitions for peripheral PSU_DP */ +#define XPAR_PSU_DP_DEVICE_ID 0 +#define XPAR_PSU_DP_BASEADDR 0xFD4A0000 +#define XPAR_PSU_DP_HIGHADDR 0xFD4AFFFF + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_DP */ +#define XPAR_XAVBUF_0_DEVICE_ID XPAR_PSU_DP_DEVICE_ID +#define XPAR_XAVBUF_0_BASEADDR 0xFD4A0000 +#define XPAR_XAVBUF_0_HIGHADDR 0xFD4AFFFF + + +/******************************************************************/ + /* Definitions for driver AXIPMON */ -#define XPAR_XAXIPMON_NUM_INSTANCES 4 +#define XPAR_XAXIPMON_NUM_INSTANCES 4U /* Definitions for peripheral PSU_APM_0 */ -#define XPAR_PSU_APM_0_DEVICE_ID 0 -#define XPAR_PSU_APM_0_BASEADDR 0xFD0B0000 -#define XPAR_PSU_APM_0_HIGHADDR 0xFD0BFFFF -#define XPAR_PSU_APM_0_GLOBAL_COUNT_WIDTH 32 -#define XPAR_PSU_APM_0_METRICS_SAMPLE_COUNT_WIDTH 32 -#define XPAR_PSU_APM_0_ENABLE_EVENT_COUNT 1 -#define XPAR_PSU_APM_0_NUM_MONITOR_SLOTS 6 -#define XPAR_PSU_APM_0_NUM_OF_COUNTERS 10 -#define XPAR_PSU_APM_0_HAVE_SAMPLED_METRIC_CNT 1 -#define XPAR_PSU_APM_0_ENABLE_EVENT_LOG 0 -#define XPAR_PSU_APM_0_FIFO_AXIS_DEPTH 32 -#define XPAR_PSU_APM_0_FIFO_AXIS_TDATA_WIDTH 56 -#define XPAR_PSU_APM_0_FIFO_AXIS_TID_WIDTH 1 -#define XPAR_PSU_APM_0_METRIC_COUNT_SCALE 1 -#define XPAR_PSU_APM_0_ENABLE_ADVANCED 1 -#define XPAR_PSU_APM_0_ENABLE_PROFILE 0 -#define XPAR_PSU_APM_0_ENABLE_TRACE 0 -#define XPAR_PSU_APM_0_S_AXI4_BASEADDR 0x00000000 -#define XPAR_PSU_APM_0_S_AXI4_HIGHADDR 0x00000000 -#define XPAR_PSU_APM_0_ENABLE_32BIT_FILTER_ID 1 +#define XPAR_PSU_APM_0_DEVICE_ID 0U +#define XPAR_PSU_APM_0_BASEADDR 0xFD0B0000U +#define XPAR_PSU_APM_0_HIGHADDR 0xFD0BFFFFU +#define XPAR_PSU_APM_0_GLOBAL_COUNT_WIDTH 32U +#define XPAR_PSU_APM_0_METRICS_SAMPLE_COUNT_WIDTH 32U +#define XPAR_PSU_APM_0_ENABLE_EVENT_COUNT 1U +#define XPAR_PSU_APM_0_NUM_MONITOR_SLOTS 6U +#define XPAR_PSU_APM_0_NUM_OF_COUNTERS 10U +#define XPAR_PSU_APM_0_HAVE_SAMPLED_METRIC_CNT 1U +#define XPAR_PSU_APM_0_ENABLE_EVENT_LOG 0U +#define XPAR_PSU_APM_0_FIFO_AXIS_DEPTH 32U +#define XPAR_PSU_APM_0_FIFO_AXIS_TDATA_WIDTH 56U +#define XPAR_PSU_APM_0_FIFO_AXIS_TID_WIDTH 1U +#define XPAR_PSU_APM_0_METRIC_COUNT_SCALE 1U +#define XPAR_PSU_APM_0_ENABLE_ADVANCED 1U +#define XPAR_PSU_APM_0_ENABLE_PROFILE 0U +#define XPAR_PSU_APM_0_ENABLE_TRACE 0U +#define XPAR_PSU_APM_0_S_AXI4_BASEADDR 0x00000000U +#define XPAR_PSU_APM_0_S_AXI4_HIGHADDR 0x00000000U +#define XPAR_PSU_APM_0_ENABLE_32BIT_FILTER_ID 1U /* Definitions for peripheral PSU_APM_1 */ -#define XPAR_PSU_APM_1_DEVICE_ID 1 -#define XPAR_PSU_APM_1_BASEADDR 0xFFA00000 -#define XPAR_PSU_APM_1_HIGHADDR 0xFFA0FFFF -#define XPAR_PSU_APM_1_GLOBAL_COUNT_WIDTH 32 -#define XPAR_PSU_APM_1_METRICS_SAMPLE_COUNT_WIDTH 32 -#define XPAR_PSU_APM_1_ENABLE_EVENT_COUNT 1 -#define XPAR_PSU_APM_1_NUM_MONITOR_SLOTS 1 -#define XPAR_PSU_APM_1_NUM_OF_COUNTERS 3 -#define XPAR_PSU_APM_1_HAVE_SAMPLED_METRIC_CNT 1 -#define XPAR_PSU_APM_1_ENABLE_EVENT_LOG 0 -#define XPAR_PSU_APM_1_FIFO_AXIS_DEPTH 32 -#define XPAR_PSU_APM_1_FIFO_AXIS_TDATA_WIDTH 56 -#define XPAR_PSU_APM_1_FIFO_AXIS_TID_WIDTH 1 -#define XPAR_PSU_APM_1_METRIC_COUNT_SCALE 1 -#define XPAR_PSU_APM_1_ENABLE_ADVANCED 1 -#define XPAR_PSU_APM_1_ENABLE_PROFILE 0 -#define XPAR_PSU_APM_1_ENABLE_TRACE 0 -#define XPAR_PSU_APM_1_S_AXI4_BASEADDR 0x00000000 -#define XPAR_PSU_APM_1_S_AXI4_HIGHADDR 0x00000000 -#define XPAR_PSU_APM_1_ENABLE_32BIT_FILTER_ID 1 +#define XPAR_PSU_APM_1_DEVICE_ID 1U +#define XPAR_PSU_APM_1_BASEADDR 0xFFA00000U +#define XPAR_PSU_APM_1_HIGHADDR 0xFFA0FFFFU +#define XPAR_PSU_APM_1_GLOBAL_COUNT_WIDTH 32U +#define XPAR_PSU_APM_1_METRICS_SAMPLE_COUNT_WIDTH 32U +#define XPAR_PSU_APM_1_ENABLE_EVENT_COUNT 1U +#define XPAR_PSU_APM_1_NUM_MONITOR_SLOTS 1U +#define XPAR_PSU_APM_1_NUM_OF_COUNTERS 3U +#define XPAR_PSU_APM_1_HAVE_SAMPLED_METRIC_CNT 1U +#define XPAR_PSU_APM_1_ENABLE_EVENT_LOG 0U +#define XPAR_PSU_APM_1_FIFO_AXIS_DEPTH 32U +#define XPAR_PSU_APM_1_FIFO_AXIS_TDATA_WIDTH 56U +#define XPAR_PSU_APM_1_FIFO_AXIS_TID_WIDTH 1U +#define XPAR_PSU_APM_1_METRIC_COUNT_SCALE 1U +#define XPAR_PSU_APM_1_ENABLE_ADVANCED 1U +#define XPAR_PSU_APM_1_ENABLE_PROFILE 0U +#define XPAR_PSU_APM_1_ENABLE_TRACE 0U +#define XPAR_PSU_APM_1_S_AXI4_BASEADDR 0x00000000U +#define XPAR_PSU_APM_1_S_AXI4_HIGHADDR 0x00000000U +#define XPAR_PSU_APM_1_ENABLE_32BIT_FILTER_ID 1U /* Definitions for peripheral PSU_APM_2 */ -#define XPAR_PSU_APM_2_DEVICE_ID 2 -#define XPAR_PSU_APM_2_BASEADDR 0xFFA10000 -#define XPAR_PSU_APM_2_HIGHADDR 0xFFA1FFFF -#define XPAR_PSU_APM_2_GLOBAL_COUNT_WIDTH 32 -#define XPAR_PSU_APM_2_METRICS_SAMPLE_COUNT_WIDTH 32 -#define XPAR_PSU_APM_2_ENABLE_EVENT_COUNT 1 -#define XPAR_PSU_APM_2_NUM_MONITOR_SLOTS 1 -#define XPAR_PSU_APM_2_NUM_OF_COUNTERS 3 -#define XPAR_PSU_APM_2_HAVE_SAMPLED_METRIC_CNT 1 -#define XPAR_PSU_APM_2_ENABLE_EVENT_LOG 0 -#define XPAR_PSU_APM_2_FIFO_AXIS_DEPTH 32 -#define XPAR_PSU_APM_2_FIFO_AXIS_TDATA_WIDTH 56 -#define XPAR_PSU_APM_2_FIFO_AXIS_TID_WIDTH 1 -#define XPAR_PSU_APM_2_METRIC_COUNT_SCALE 1 -#define XPAR_PSU_APM_2_ENABLE_ADVANCED 1 -#define XPAR_PSU_APM_2_ENABLE_PROFILE 0 -#define XPAR_PSU_APM_2_ENABLE_TRACE 0 -#define XPAR_PSU_APM_2_S_AXI4_BASEADDR 0x00000000 -#define XPAR_PSU_APM_2_S_AXI4_HIGHADDR 0x00000000 -#define XPAR_PSU_APM_2_ENABLE_32BIT_FILTER_ID 1 +#define XPAR_PSU_APM_2_DEVICE_ID 2U +#define XPAR_PSU_APM_2_BASEADDR 0xFFA10000U +#define XPAR_PSU_APM_2_HIGHADDR 0xFFA1FFFFU +#define XPAR_PSU_APM_2_GLOBAL_COUNT_WIDTH 32U +#define XPAR_PSU_APM_2_METRICS_SAMPLE_COUNT_WIDTH 32U +#define XPAR_PSU_APM_2_ENABLE_EVENT_COUNT 1U +#define XPAR_PSU_APM_2_NUM_MONITOR_SLOTS 1U +#define XPAR_PSU_APM_2_NUM_OF_COUNTERS 3U +#define XPAR_PSU_APM_2_HAVE_SAMPLED_METRIC_CNT 1U +#define XPAR_PSU_APM_2_ENABLE_EVENT_LOG 0U +#define XPAR_PSU_APM_2_FIFO_AXIS_DEPTH 32U +#define XPAR_PSU_APM_2_FIFO_AXIS_TDATA_WIDTH 56U +#define XPAR_PSU_APM_2_FIFO_AXIS_TID_WIDTH 1U +#define XPAR_PSU_APM_2_METRIC_COUNT_SCALE 1U +#define XPAR_PSU_APM_2_ENABLE_ADVANCED 1U +#define XPAR_PSU_APM_2_ENABLE_PROFILE 0U +#define XPAR_PSU_APM_2_ENABLE_TRACE 0U +#define XPAR_PSU_APM_2_S_AXI4_BASEADDR 0x00000000U +#define XPAR_PSU_APM_2_S_AXI4_HIGHADDR 0x00000000U +#define XPAR_PSU_APM_2_ENABLE_32BIT_FILTER_ID 1U /* Definitions for peripheral PSU_APM_5 */ -#define XPAR_PSU_APM_5_DEVICE_ID 3 -#define XPAR_PSU_APM_5_BASEADDR 0xFD490000 -#define XPAR_PSU_APM_5_HIGHADDR 0xFD49FFFF -#define XPAR_PSU_APM_5_GLOBAL_COUNT_WIDTH 32 -#define XPAR_PSU_APM_5_METRICS_SAMPLE_COUNT_WIDTH 32 -#define XPAR_PSU_APM_5_ENABLE_EVENT_COUNT 1 -#define XPAR_PSU_APM_5_NUM_MONITOR_SLOTS 1 -#define XPAR_PSU_APM_5_NUM_OF_COUNTERS 3 -#define XPAR_PSU_APM_5_HAVE_SAMPLED_METRIC_CNT 1 -#define XPAR_PSU_APM_5_ENABLE_EVENT_LOG 0 -#define XPAR_PSU_APM_5_FIFO_AXIS_DEPTH 32 -#define XPAR_PSU_APM_5_FIFO_AXIS_TDATA_WIDTH 56 -#define XPAR_PSU_APM_5_FIFO_AXIS_TID_WIDTH 1 -#define XPAR_PSU_APM_5_METRIC_COUNT_SCALE 1 -#define XPAR_PSU_APM_5_ENABLE_ADVANCED 1 -#define XPAR_PSU_APM_5_ENABLE_PROFILE 0 -#define XPAR_PSU_APM_5_ENABLE_TRACE 0 -#define XPAR_PSU_APM_5_S_AXI4_BASEADDR 0x00000000 -#define XPAR_PSU_APM_5_S_AXI4_HIGHADDR 0x00000000 -#define XPAR_PSU_APM_5_ENABLE_32BIT_FILTER_ID 1 +#define XPAR_PSU_APM_5_DEVICE_ID 3U +#define XPAR_PSU_APM_5_BASEADDR 0xFD490000U +#define XPAR_PSU_APM_5_HIGHADDR 0xFD49FFFFU +#define XPAR_PSU_APM_5_GLOBAL_COUNT_WIDTH 32U +#define XPAR_PSU_APM_5_METRICS_SAMPLE_COUNT_WIDTH 32U +#define XPAR_PSU_APM_5_ENABLE_EVENT_COUNT 1U +#define XPAR_PSU_APM_5_NUM_MONITOR_SLOTS 1U +#define XPAR_PSU_APM_5_NUM_OF_COUNTERS 3U +#define XPAR_PSU_APM_5_HAVE_SAMPLED_METRIC_CNT 1U +#define XPAR_PSU_APM_5_ENABLE_EVENT_LOG 0U +#define XPAR_PSU_APM_5_FIFO_AXIS_DEPTH 32U +#define XPAR_PSU_APM_5_FIFO_AXIS_TDATA_WIDTH 56U +#define XPAR_PSU_APM_5_FIFO_AXIS_TID_WIDTH 1U +#define XPAR_PSU_APM_5_METRIC_COUNT_SCALE 1U +#define XPAR_PSU_APM_5_ENABLE_ADVANCED 1U +#define XPAR_PSU_APM_5_ENABLE_PROFILE 0U +#define XPAR_PSU_APM_5_ENABLE_TRACE 0U +#define XPAR_PSU_APM_5_S_AXI4_BASEADDR 0x00000000U +#define XPAR_PSU_APM_5_S_AXI4_HIGHADDR 0x00000000U +#define XPAR_PSU_APM_5_ENABLE_32BIT_FILTER_ID 1U /******************************************************************/ /* Canonical definitions for peripheral PSU_APM_0 */ #define XPAR_AXIPMON_0_DEVICE_ID XPAR_PSU_APM_0_DEVICE_ID -#define XPAR_AXIPMON_0_BASEADDR 0xFD0B0000 -#define XPAR_AXIPMON_0_HIGHADDR 0xFD0BFFFF -#define XPAR_AXIPMON_0_GLOBAL_COUNT_WIDTH 32 -#define XPAR_AXIPMON_0_METRICS_SAMPLE_COUNT_WIDTH 32 -#define XPAR_AXIPMON_0_ENABLE_EVENT_COUNT 1 -#define XPAR_AXIPMON_0_NUM_MONITOR_SLOTS 6 -#define XPAR_AXIPMON_0_NUM_OF_COUNTERS 10 -#define XPAR_AXIPMON_0_HAVE_SAMPLED_METRIC_CNT 1 -#define XPAR_AXIPMON_0_ENABLE_EVENT_LOG 0 -#define XPAR_AXIPMON_0_FIFO_AXIS_DEPTH 32 -#define XPAR_AXIPMON_0_FIFO_AXIS_TDATA_WIDTH 56 -#define XPAR_AXIPMON_0_FIFO_AXIS_TID_WIDTH 1 -#define XPAR_AXIPMON_0_METRIC_COUNT_SCALE 1 -#define XPAR_AXIPMON_0_ENABLE_ADVANCED 1 -#define XPAR_AXIPMON_0_ENABLE_PROFILE 0 -#define XPAR_AXIPMON_0_ENABLE_TRACE 0 -#define XPAR_AXIPMON_0_S_AXI4_BASEADDR 0x00000000 -#define XPAR_AXIPMON_0_S_AXI4_HIGHADDR 0x00000000 -#define XPAR_AXIPMON_0_ENABLE_32BIT_FILTER_ID 1 +#define XPAR_AXIPMON_0_BASEADDR 0xFD0B0000U +#define XPAR_AXIPMON_0_HIGHADDR 0xFD0BFFFFU +#define XPAR_AXIPMON_0_GLOBAL_COUNT_WIDTH 32U +#define XPAR_AXIPMON_0_METRICS_SAMPLE_COUNT_WIDTH 32U +#define XPAR_AXIPMON_0_ENABLE_EVENT_COUNT 1U +#define XPAR_AXIPMON_0_NUM_MONITOR_SLOTS 6U +#define XPAR_AXIPMON_0_NUM_OF_COUNTERS 10U +#define XPAR_AXIPMON_0_HAVE_SAMPLED_METRIC_CNT 1U +#define XPAR_AXIPMON_0_ENABLE_EVENT_LOG 0U +#define XPAR_AXIPMON_0_FIFO_AXIS_DEPTH 32U +#define XPAR_AXIPMON_0_FIFO_AXIS_TDATA_WIDTH 56U +#define XPAR_AXIPMON_0_FIFO_AXIS_TID_WIDTH 1U +#define XPAR_AXIPMON_0_METRIC_COUNT_SCALE 1U +#define XPAR_AXIPMON_0_ENABLE_ADVANCED 1U +#define XPAR_AXIPMON_0_ENABLE_PROFILE 0U +#define XPAR_AXIPMON_0_ENABLE_TRACE 0U +#define XPAR_AXIPMON_0_S_AXI4_BASEADDR 0x00000000U +#define XPAR_AXIPMON_0_S_AXI4_HIGHADDR 0x00000000U +#define XPAR_AXIPMON_0_ENABLE_32BIT_FILTER_ID 1U /* Canonical definitions for peripheral PSU_APM_1 */ #define XPAR_AXIPMON_1_DEVICE_ID XPAR_PSU_APM_1_DEVICE_ID -#define XPAR_AXIPMON_1_BASEADDR 0xFFA00000 -#define XPAR_AXIPMON_1_HIGHADDR 0xFFA0FFFF -#define XPAR_AXIPMON_1_GLOBAL_COUNT_WIDTH 32 -#define XPAR_AXIPMON_1_METRICS_SAMPLE_COUNT_WIDTH 32 -#define XPAR_AXIPMON_1_ENABLE_EVENT_COUNT 1 -#define XPAR_AXIPMON_1_NUM_MONITOR_SLOTS 1 -#define XPAR_AXIPMON_1_NUM_OF_COUNTERS 3 -#define XPAR_AXIPMON_1_HAVE_SAMPLED_METRIC_CNT 1 -#define XPAR_AXIPMON_1_ENABLE_EVENT_LOG 0 -#define XPAR_AXIPMON_1_FIFO_AXIS_DEPTH 32 -#define XPAR_AXIPMON_1_FIFO_AXIS_TDATA_WIDTH 56 -#define XPAR_AXIPMON_1_FIFO_AXIS_TID_WIDTH 1 -#define XPAR_AXIPMON_1_METRIC_COUNT_SCALE 1 -#define XPAR_AXIPMON_1_ENABLE_ADVANCED 1 -#define XPAR_AXIPMON_1_ENABLE_PROFILE 0 -#define XPAR_AXIPMON_1_ENABLE_TRACE 0 -#define XPAR_AXIPMON_1_S_AXI4_BASEADDR 0x00000000 -#define XPAR_AXIPMON_1_S_AXI4_HIGHADDR 0x00000000 -#define XPAR_AXIPMON_1_ENABLE_32BIT_FILTER_ID 1 +#define XPAR_AXIPMON_1_BASEADDR 0xFFA00000U +#define XPAR_AXIPMON_1_HIGHADDR 0xFFA0FFFFU +#define XPAR_AXIPMON_1_GLOBAL_COUNT_WIDTH 32U +#define XPAR_AXIPMON_1_METRICS_SAMPLE_COUNT_WIDTH 32U +#define XPAR_AXIPMON_1_ENABLE_EVENT_COUNT 1U +#define XPAR_AXIPMON_1_NUM_MONITOR_SLOTS 1U +#define XPAR_AXIPMON_1_NUM_OF_COUNTERS 3U +#define XPAR_AXIPMON_1_HAVE_SAMPLED_METRIC_CNT 1U +#define XPAR_AXIPMON_1_ENABLE_EVENT_LOG 0U +#define XPAR_AXIPMON_1_FIFO_AXIS_DEPTH 32U +#define XPAR_AXIPMON_1_FIFO_AXIS_TDATA_WIDTH 56U +#define XPAR_AXIPMON_1_FIFO_AXIS_TID_WIDTH 1U +#define XPAR_AXIPMON_1_METRIC_COUNT_SCALE 1U +#define XPAR_AXIPMON_1_ENABLE_ADVANCED 1U +#define XPAR_AXIPMON_1_ENABLE_PROFILE 0U +#define XPAR_AXIPMON_1_ENABLE_TRACE 0U +#define XPAR_AXIPMON_1_S_AXI4_BASEADDR 0x00000000U +#define XPAR_AXIPMON_1_S_AXI4_HIGHADDR 0x00000000U +#define XPAR_AXIPMON_1_ENABLE_32BIT_FILTER_ID 1U /* Canonical definitions for peripheral PSU_APM_2 */ #define XPAR_AXIPMON_2_DEVICE_ID XPAR_PSU_APM_2_DEVICE_ID -#define XPAR_AXIPMON_2_BASEADDR 0xFFA10000 -#define XPAR_AXIPMON_2_HIGHADDR 0xFFA1FFFF -#define XPAR_AXIPMON_2_GLOBAL_COUNT_WIDTH 32 -#define XPAR_AXIPMON_2_METRICS_SAMPLE_COUNT_WIDTH 32 -#define XPAR_AXIPMON_2_ENABLE_EVENT_COUNT 1 -#define XPAR_AXIPMON_2_NUM_MONITOR_SLOTS 1 -#define XPAR_AXIPMON_2_NUM_OF_COUNTERS 3 -#define XPAR_AXIPMON_2_HAVE_SAMPLED_METRIC_CNT 1 -#define XPAR_AXIPMON_2_ENABLE_EVENT_LOG 0 -#define XPAR_AXIPMON_2_FIFO_AXIS_DEPTH 32 -#define XPAR_AXIPMON_2_FIFO_AXIS_TDATA_WIDTH 56 -#define XPAR_AXIPMON_2_FIFO_AXIS_TID_WIDTH 1 -#define XPAR_AXIPMON_2_METRIC_COUNT_SCALE 1 -#define XPAR_AXIPMON_2_ENABLE_ADVANCED 1 -#define XPAR_AXIPMON_2_ENABLE_PROFILE 0 -#define XPAR_AXIPMON_2_ENABLE_TRACE 0 -#define XPAR_AXIPMON_2_S_AXI4_BASEADDR 0x00000000 -#define XPAR_AXIPMON_2_S_AXI4_HIGHADDR 0x00000000 -#define XPAR_AXIPMON_2_ENABLE_32BIT_FILTER_ID 1 +#define XPAR_AXIPMON_2_BASEADDR 0xFFA10000U +#define XPAR_AXIPMON_2_HIGHADDR 0xFFA1FFFFU +#define XPAR_AXIPMON_2_GLOBAL_COUNT_WIDTH 32U +#define XPAR_AXIPMON_2_METRICS_SAMPLE_COUNT_WIDTH 32U +#define XPAR_AXIPMON_2_ENABLE_EVENT_COUNT 1U +#define XPAR_AXIPMON_2_NUM_MONITOR_SLOTS 1U +#define XPAR_AXIPMON_2_NUM_OF_COUNTERS 3U +#define XPAR_AXIPMON_2_HAVE_SAMPLED_METRIC_CNT 1U +#define XPAR_AXIPMON_2_ENABLE_EVENT_LOG 0U +#define XPAR_AXIPMON_2_FIFO_AXIS_DEPTH 32U +#define XPAR_AXIPMON_2_FIFO_AXIS_TDATA_WIDTH 56U +#define XPAR_AXIPMON_2_FIFO_AXIS_TID_WIDTH 1U +#define XPAR_AXIPMON_2_METRIC_COUNT_SCALE 1U +#define XPAR_AXIPMON_2_ENABLE_ADVANCED 1U +#define XPAR_AXIPMON_2_ENABLE_PROFILE 0U +#define XPAR_AXIPMON_2_ENABLE_TRACE 0U +#define XPAR_AXIPMON_2_S_AXI4_BASEADDR 0x00000000U +#define XPAR_AXIPMON_2_S_AXI4_HIGHADDR 0x00000000U +#define XPAR_AXIPMON_2_ENABLE_32BIT_FILTER_ID 1U /* Canonical definitions for peripheral PSU_APM_5 */ #define XPAR_AXIPMON_3_DEVICE_ID XPAR_PSU_APM_5_DEVICE_ID -#define XPAR_AXIPMON_3_BASEADDR 0xFD490000 -#define XPAR_AXIPMON_3_HIGHADDR 0xFD49FFFF -#define XPAR_AXIPMON_3_GLOBAL_COUNT_WIDTH 32 -#define XPAR_AXIPMON_3_METRICS_SAMPLE_COUNT_WIDTH 32 -#define XPAR_AXIPMON_3_ENABLE_EVENT_COUNT 1 -#define XPAR_AXIPMON_3_NUM_MONITOR_SLOTS 1 -#define XPAR_AXIPMON_3_NUM_OF_COUNTERS 3 -#define XPAR_AXIPMON_3_HAVE_SAMPLED_METRIC_CNT 1 -#define XPAR_AXIPMON_3_ENABLE_EVENT_LOG 0 -#define XPAR_AXIPMON_3_FIFO_AXIS_DEPTH 32 -#define XPAR_AXIPMON_3_FIFO_AXIS_TDATA_WIDTH 56 -#define XPAR_AXIPMON_3_FIFO_AXIS_TID_WIDTH 1 -#define XPAR_AXIPMON_3_METRIC_COUNT_SCALE 1 -#define XPAR_AXIPMON_3_ENABLE_ADVANCED 1 -#define XPAR_AXIPMON_3_ENABLE_PROFILE 0 -#define XPAR_AXIPMON_3_ENABLE_TRACE 0 -#define XPAR_AXIPMON_3_S_AXI4_BASEADDR 0x00000000 -#define XPAR_AXIPMON_3_S_AXI4_HIGHADDR 0x00000000 -#define XPAR_AXIPMON_3_ENABLE_32BIT_FILTER_ID 1 +#define XPAR_AXIPMON_3_BASEADDR 0xFD490000U +#define XPAR_AXIPMON_3_HIGHADDR 0xFD49FFFFU +#define XPAR_AXIPMON_3_GLOBAL_COUNT_WIDTH 32U +#define XPAR_AXIPMON_3_METRICS_SAMPLE_COUNT_WIDTH 32U +#define XPAR_AXIPMON_3_ENABLE_EVENT_COUNT 1U +#define XPAR_AXIPMON_3_NUM_MONITOR_SLOTS 1U +#define XPAR_AXIPMON_3_NUM_OF_COUNTERS 3U +#define XPAR_AXIPMON_3_HAVE_SAMPLED_METRIC_CNT 1U +#define XPAR_AXIPMON_3_ENABLE_EVENT_LOG 0U +#define XPAR_AXIPMON_3_FIFO_AXIS_DEPTH 32U +#define XPAR_AXIPMON_3_FIFO_AXIS_TDATA_WIDTH 56U +#define XPAR_AXIPMON_3_FIFO_AXIS_TID_WIDTH 1U +#define XPAR_AXIPMON_3_METRIC_COUNT_SCALE 1U +#define XPAR_AXIPMON_3_ENABLE_ADVANCED 1U +#define XPAR_AXIPMON_3_ENABLE_PROFILE 0U +#define XPAR_AXIPMON_3_ENABLE_TRACE 0U +#define XPAR_AXIPMON_3_S_AXI4_BASEADDR 0x00000000U +#define XPAR_AXIPMON_3_S_AXI4_HIGHADDR 0x00000000U +#define XPAR_AXIPMON_3_ENABLE_32BIT_FILTER_ID 1U /******************************************************************/ @@ -236,7 +266,7 @@ #define XPAR_PSU_CAN_1_DEVICE_ID 0 #define XPAR_PSU_CAN_1_BASEADDR 0xFF070000 #define XPAR_PSU_CAN_1_HIGHADDR 0xFF07FFFF -#define XPAR_PSU_CAN_1_CAN_CLK_FREQ_HZ 99998999 +#define XPAR_PSU_CAN_1_CAN_CLK_FREQ_HZ 99990000 /******************************************************************/ @@ -245,7 +275,7 @@ #define XPAR_XCANPS_0_DEVICE_ID XPAR_PSU_CAN_1_DEVICE_ID #define XPAR_XCANPS_0_BASEADDR 0xFF070000 #define XPAR_XCANPS_0_HIGHADDR 0xFF07FFFF -#define XPAR_XCANPS_0_CAN_CLK_FREQ_HZ 99998999 +#define XPAR_XCANPS_0_CAN_CLK_FREQ_HZ 99990000 /******************************************************************/ @@ -279,7 +309,7 @@ #define XPAR_PSU_DDRC_0_BASEADDR 0xFD070000 #define XPAR_PSU_DDRC_0_HIGHADDR 0xFD070FFF #define XPAR_PSU_DDRC_0_HAS_ECC 0 -#define XPAR_PSU_DDRC_0_DDRC_CLK_FREQ_HZ 533328002 +#define XPAR_PSU_DDRC_0_DDRC_CLK_FREQ_HZ 533280000 /******************************************************************/ @@ -288,7 +318,26 @@ #define XPAR_DDRCPSU_0_DEVICE_ID XPAR_PSU_DDRC_0_DEVICE_ID #define XPAR_DDRCPSU_0_BASEADDR 0xFD070000 #define XPAR_DDRCPSU_0_HIGHADDR 0xFD070FFF -#define XPAR_DDRCPSU_0_DDRC_CLK_FREQ_HZ 533328002 +#define XPAR_DDRCPSU_0_DDRC_CLK_FREQ_HZ 533280000 + + +/******************************************************************/ + +/* Definitions for driver DPDMA */ +#define XPAR_XDPDMA_NUM_INSTANCES 1 + +/* Definitions for peripheral PSU_DPDMA */ +#define XPAR_PSU_DPDMA_DEVICE_ID 0 +#define XPAR_PSU_DPDMA_BASEADDR 0xFD4C0000 +#define XPAR_PSU_DPDMA_HIGHADDR 0xFD4CFFFF + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_DPDMA */ +#define XPAR_XDPDMA_0_DEVICE_ID XPAR_PSU_DPDMA_DEVICE_ID +#define XPAR_XDPDMA_0_BASEADDR 0xFD4C0000 +#define XPAR_XDPDMA_0_HIGHADDR 0xFD4CFFFF /******************************************************************/ @@ -300,28 +349,31 @@ #define XPAR_PSU_ETHERNET_3_DEVICE_ID 0 #define XPAR_PSU_ETHERNET_3_BASEADDR 0xFF0E0000 #define XPAR_PSU_ETHERNET_3_HIGHADDR 0xFF0EFFFF -#define XPAR_PSU_ETHERNET_3_ENET_CLK_FREQ_HZ 124998749 +#define XPAR_PSU_ETHERNET_3_ENET_CLK_FREQ_HZ 124987500 #define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV0 12 #define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV1 1 #define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV0 60 #define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV1 1 #define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV0 60 #define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV1 10 +#define XPAR_PSU_ETHERNET_3_ENET_TSU_CLK_FREQ_HZ 249975000 /******************************************************************/ +#define XPAR_PSU_ETHERNET_3_IS_CACHE_COHERENT 0 /* Canonical definitions for peripheral PSU_ETHERNET_3 */ #define XPAR_XEMACPS_0_DEVICE_ID XPAR_PSU_ETHERNET_3_DEVICE_ID #define XPAR_XEMACPS_0_BASEADDR 0xFF0E0000 #define XPAR_XEMACPS_0_HIGHADDR 0xFF0EFFFF -#define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 124998749 +#define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 124987500 #define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 12 #define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1 #define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 60 #define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 1 #define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 60 #define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 10 +#define XPAR_XEMACPS_0_ENET_TSU_CLK_FREQ_HZ 249975000 /******************************************************************/ @@ -377,16 +429,16 @@ #define XPAR_PSU_CCI_REG_S_AXI_HIGHADDR 0xFD5EFFFF -/* Definitions for peripheral PSU_CRF_APB */ -#define XPAR_PSU_CRF_APB_S_AXI_BASEADDR 0xFD1A0000 -#define XPAR_PSU_CRF_APB_S_AXI_HIGHADDR 0xFD2DFFFF - - /* Definitions for peripheral PSU_CRL_APB */ #define XPAR_PSU_CRL_APB_S_AXI_BASEADDR 0xFF5E0000 #define XPAR_PSU_CRL_APB_S_AXI_HIGHADDR 0xFF85FFFF +/* Definitions for peripheral PSU_CTRL_IPI */ +#define XPAR_PSU_CTRL_IPI_S_AXI_BASEADDR 0xFF380000 +#define XPAR_PSU_CTRL_IPI_S_AXI_HIGHADDR 0xFF3FFFFF + + /* Definitions for peripheral PSU_DDR_PHY */ #define XPAR_PSU_DDR_PHY_S_AXI_BASEADDR 0xFD080000 #define XPAR_PSU_DDR_PHY_S_AXI_HIGHADDR 0xFD08FFFF @@ -427,16 +479,6 @@ #define XPAR_PSU_DDR_XMPU5_CFG_S_AXI_HIGHADDR 0xFD05FFFF -/* Definitions for peripheral PSU_DP */ -#define XPAR_PSU_DP_S_AXI_BASEADDR 0xFD4A0000 -#define XPAR_PSU_DP_S_AXI_HIGHADDR 0xFD4AFFFF - - -/* Definitions for peripheral PSU_DPDMA */ -#define XPAR_PSU_DPDMA_S_AXI_BASEADDR 0xFD4C0000 -#define XPAR_PSU_DPDMA_S_AXI_HIGHADDR 0xFD4CFFFF - - /* Definitions for peripheral PSU_EFUSE */ #define XPAR_PSU_EFUSE_S_AXI_BASEADDR 0xFFCC0000 #define XPAR_PSU_EFUSE_S_AXI_HIGHADDR 0xFFCCFFFF @@ -517,6 +559,11 @@ #define XPAR_PSU_MBISTJTAG_S_AXI_HIGHADDR 0xFFCFFFFF +/* Definitions for peripheral PSU_MESSAGE_BUFFERS */ +#define XPAR_PSU_MESSAGE_BUFFERS_S_AXI_BASEADDR 0xFF990000 +#define XPAR_PSU_MESSAGE_BUFFERS_S_AXI_HIGHADDR 0xFF99FFFF + + /* Definitions for peripheral PSU_OCM */ #define XPAR_PSU_OCM_S_AXI_BASEADDR 0xFF960000 #define XPAR_PSU_OCM_S_AXI_HIGHADDR 0xFF96FFFF @@ -524,7 +571,7 @@ /* Definitions for peripheral PSU_OCM_RAM_0 */ #define XPAR_PSU_OCM_RAM_0_S_AXI_BASEADDR 0xFFFC0000 -#define XPAR_PSU_OCM_RAM_0_S_AXI_HIGHADDR 0xFFFEFFFF +#define XPAR_PSU_OCM_RAM_0_S_AXI_HIGHADDR 0xFFFFFFFF /* Definitions for peripheral PSU_OCM_XMPU_CFG */ @@ -547,6 +594,16 @@ #define XPAR_PSU_PCIE_DMA_S_AXI_HIGHADDR 0xFD0FFFFF +/* Definitions for peripheral PSU_PCIE_HIGH1 */ +#define XPAR_PSU_PCIE_HIGH1_S_AXI_BASEADDR 0x600000000 +#define XPAR_PSU_PCIE_HIGH1_S_AXI_HIGHADDR 0x7FFFFFFFF + + +/* Definitions for peripheral PSU_PCIE_HIGH2 */ +#define XPAR_PSU_PCIE_HIGH2_S_AXI_BASEADDR 0x8000000000 +#define XPAR_PSU_PCIE_HIGH2_S_AXI_HIGHADDR 0xBFFFFFFFFF + + /* Definitions for peripheral PSU_PCIE_LOW */ #define XPAR_PSU_PCIE_LOW_S_AXI_BASEADDR 0xE0000000 #define XPAR_PSU_PCIE_LOW_S_AXI_HIGHADDR 0xEFFFFFFF @@ -557,11 +614,6 @@ #define XPAR_PSU_PMU_GLOBAL_0_S_AXI_HIGHADDR 0xFFDBFFFF -/* Definitions for peripheral PSU_PMU_IOMODULE */ -#define XPAR_PSU_PMU_IOMODULE_S_AXI_BASEADDR 0xFFD40000 -#define XPAR_PSU_PMU_IOMODULE_S_AXI_HIGHADDR 0xFFD5FFFF - - /* Definitions for peripheral PSU_QSPI_LINEAR_0 */ #define XPAR_PSU_QSPI_LINEAR_0_S_AXI_BASEADDR 0xC0000000 #define XPAR_PSU_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xDFFFFFFF @@ -579,7 +631,7 @@ /* Definitions for peripheral PSU_R5_DDR_0 */ #define XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR 0x00100000 -#define XPAR_PSU_R5_DDR_0_S_AXI_HIGHADDR 0xFFFFFFFF +#define XPAR_PSU_R5_DDR_0_S_AXI_HIGHADDR 0x7FFFFFFF /* Definitions for peripheral PSU_R5_TCM_RAM_0 */ @@ -622,6 +674,11 @@ #define XPAR_PSU_SMMU_REG_S_AXI_HIGHADDR 0xFD5FFFFF +/* Definitions for peripheral PSU_USB_0 */ +#define XPAR_PSU_USB_0_S_AXI_BASEADDR 0xFF9D0000 +#define XPAR_PSU_USB_0_S_AXI_HIGHADDR 0xFF9DFFFF + + /******************************************************************/ /* Definitions for driver GPIOPS */ @@ -650,14 +707,14 @@ #define XPAR_PSU_I2C_0_DEVICE_ID 0 #define XPAR_PSU_I2C_0_BASEADDR 0xFF020000 #define XPAR_PSU_I2C_0_HIGHADDR 0xFF02FFFF -#define XPAR_PSU_I2C_0_I2C_CLK_FREQ_HZ 99998999 +#define XPAR_PSU_I2C_0_I2C_CLK_FREQ_HZ 99990000 /* Definitions for peripheral PSU_I2C_1 */ #define XPAR_PSU_I2C_1_DEVICE_ID 1 #define XPAR_PSU_I2C_1_BASEADDR 0xFF030000 #define XPAR_PSU_I2C_1_HIGHADDR 0xFF03FFFF -#define XPAR_PSU_I2C_1_I2C_CLK_FREQ_HZ 99998999 +#define XPAR_PSU_I2C_1_I2C_CLK_FREQ_HZ 99990000 /******************************************************************/ @@ -666,25 +723,25 @@ #define XPAR_XIICPS_0_DEVICE_ID XPAR_PSU_I2C_0_DEVICE_ID #define XPAR_XIICPS_0_BASEADDR 0xFF020000 #define XPAR_XIICPS_0_HIGHADDR 0xFF02FFFF -#define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 99998999 +#define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 99990000 /* Canonical definitions for peripheral PSU_I2C_1 */ #define XPAR_XIICPS_1_DEVICE_ID XPAR_PSU_I2C_1_DEVICE_ID #define XPAR_XIICPS_1_BASEADDR 0xFF030000 #define XPAR_XIICPS_1_HIGHADDR 0xFF03FFFF -#define XPAR_XIICPS_1_I2C_CLK_FREQ_HZ 99998999 +#define XPAR_XIICPS_1_I2C_CLK_FREQ_HZ 99990000 /******************************************************************/ -#define XPAR_XIPIPSU_NUM_INSTANCES 1 +#define XPAR_XIPIPSU_NUM_INSTANCES 1U /* Parameter definitions for peripheral psu_ipi_1 */ -#define XPAR_PSU_IPI_1_DEVICE_ID 0 -#define XPAR_PSU_IPI_1_BASE_ADDRESS 0xFF310000 -#define XPAR_PSU_IPI_1_BIT_MASK 0x00000100 -#define XPAR_PSU_IPI_1_BUFFER_INDEX 0 -#define XPAR_PSU_IPI_1_INT_ID 65 +#define XPAR_PSU_IPI_1_DEVICE_ID 0U +#define XPAR_PSU_IPI_1_BASE_ADDRESS 0xFF310000U +#define XPAR_PSU_IPI_1_BIT_MASK 0x00000100U +#define XPAR_PSU_IPI_1_BUFFER_INDEX 0U +#define XPAR_PSU_IPI_1_INT_ID 65U /* Canonical definitions for peripheral psu_ipi_1 */ #define XPAR_XIPIPSU_0_DEVICE_ID XPAR_PSU_IPI_1_DEVICE_ID @@ -693,58 +750,50 @@ #define XPAR_XIPIPSU_0_BUFFER_INDEX XPAR_PSU_IPI_1_BUFFER_INDEX #define XPAR_XIPIPSU_0_INT_ID XPAR_PSU_IPI_1_INT_ID -#define XPAR_XIPIPSU_NUM_TARGETS 11 +#define XPAR_XIPIPSU_NUM_TARGETS 7U -#define XPAR_PSU_IPI_0_BIT_MASK 0x00000001 -#define XPAR_PSU_IPI_0_BUFFER_INDEX 2 -#define XPAR_PSU_IPI_1_BIT_MASK 0x00000100 -#define XPAR_PSU_IPI_1_BUFFER_INDEX 0 -#define XPAR_PSU_IPI_2_BIT_MASK 0x00000200 -#define XPAR_PSU_IPI_2_BUFFER_INDEX 1 -#define XPAR_PSU_IPI_3_BIT_MASK 0x00010000 -#define XPAR_PSU_IPI_3_BUFFER_INDEX 7 -#define XPAR_PSU_IPI_4_BIT_MASK 0x00020000 -#define XPAR_PSU_IPI_4_BUFFER_INDEX 7 -#define XPAR_PSU_IPI_5_BIT_MASK 0x00040000 -#define XPAR_PSU_IPI_5_BUFFER_INDEX 7 -#define XPAR_PSU_IPI_6_BIT_MASK 0x00080000 -#define XPAR_PSU_IPI_6_BUFFER_INDEX 7 -#define XPAR_PSU_IPI_7_BIT_MASK 0x01000000 -#define XPAR_PSU_IPI_7_BUFFER_INDEX 3 -#define XPAR_PSU_IPI_8_BIT_MASK 0x02000000 -#define XPAR_PSU_IPI_8_BUFFER_INDEX 4 -#define XPAR_PSU_IPI_9_BIT_MASK 0x04000000 -#define XPAR_PSU_IPI_9_BUFFER_INDEX 5 -#define XPAR_PSU_IPI_10_BIT_MASK 0x08000000 -#define XPAR_PSU_IPI_10_BUFFER_INDEX 6 +#define XPAR_PSU_IPI_0_BIT_MASK 0x00000001U +#define XPAR_PSU_IPI_0_BUFFER_INDEX 2U +#define XPAR_PSU_IPI_1_BIT_MASK 0x00000100U +#define XPAR_PSU_IPI_1_BUFFER_INDEX 0U +#define XPAR_PSU_IPI_2_BIT_MASK 0x00000200U +#define XPAR_PSU_IPI_2_BUFFER_INDEX 1U +#define XPAR_PSU_IPI_3_BIT_MASK 0x00010000U +#define XPAR_PSU_IPI_3_BUFFER_INDEX 7U +#define XPAR_PSU_IPI_4_BIT_MASK 0x00020000U +#define XPAR_PSU_IPI_4_BUFFER_INDEX 7U +#define XPAR_PSU_IPI_5_BIT_MASK 0x00040000U +#define XPAR_PSU_IPI_5_BUFFER_INDEX 7U +#define XPAR_PSU_IPI_6_BIT_MASK 0x00080000U +#define XPAR_PSU_IPI_6_BUFFER_INDEX 7U /* Target List for referring to processor IPI Targets */ #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK -#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_INDEX 0 +#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_INDEX 0U #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK -#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_INDEX 0 +#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_INDEX 0U #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK -#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_INDEX 0 +#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_INDEX 0U #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK -#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_INDEX 0 +#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_INDEX 0U #define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_MASK XPAR_PSU_IPI_1_BIT_MASK -#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_INDEX 1 +#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_INDEX 1U #define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH0_MASK XPAR_PSU_IPI_2_BIT_MASK -#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH0_INDEX 2 +#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH0_INDEX 2U #define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_MASK XPAR_PSU_IPI_3_BIT_MASK -#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_INDEX 3 +#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_INDEX 3U #define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_MASK XPAR_PSU_IPI_4_BIT_MASK -#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_INDEX 4 +#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_INDEX 4U #define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_MASK XPAR_PSU_IPI_5_BIT_MASK -#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_INDEX 5 +#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_INDEX 5U #define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_MASK XPAR_PSU_IPI_6_BIT_MASK -#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_INDEX 6 +#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_INDEX 6U /* Definitions for driver QSPIPSU */ #define XPAR_XQSPIPSU_NUM_INSTANCES 1 @@ -753,24 +802,33 @@ #define XPAR_PSU_QSPI_0_DEVICE_ID 0 #define XPAR_PSU_QSPI_0_BASEADDR 0xFF0F0000 #define XPAR_PSU_QSPI_0_HIGHADDR 0xFF0FFFFF -#define XPAR_PSU_QSPI_0_QSPI_CLK_FREQ_HZ 124998749 +#define XPAR_PSU_QSPI_0_QSPI_CLK_FREQ_HZ 124987500 #define XPAR_PSU_QSPI_0_QSPI_MODE 2 #define XPAR_PSU_QSPI_0_QSPI_BUS_WIDTH 2 /******************************************************************/ +#define XPAR_PSU_QSPI_0_IS_CACHE_COHERENT 0 /* Canonical definitions for peripheral PSU_QSPI_0 */ #define XPAR_XQSPIPSU_0_DEVICE_ID XPAR_PSU_QSPI_0_DEVICE_ID #define XPAR_XQSPIPSU_0_BASEADDR 0xFF0F0000 #define XPAR_XQSPIPSU_0_HIGHADDR 0xFF0FFFFF -#define XPAR_XQSPIPSU_0_QSPI_CLK_FREQ_HZ 124998749 +#define XPAR_XQSPIPSU_0_QSPI_CLK_FREQ_HZ 124987500 #define XPAR_XQSPIPSU_0_QSPI_MODE 2 #define XPAR_XQSPIPSU_0_QSPI_BUS_WIDTH 2 /******************************************************************/ +/* Definitions for driver RESETPS */ +#define XPAR_XRESETPS_NUM_INSTANCES 1U +/* Definitions for peripheral RESETPS */ +#define XPAR_XRESETPS_DEVICE_ID 0 +#define XPAR_XRESETPS_BASEADDR 0xFFFFFFFFU + +/******************************************************************/ + /* Definitions for driver RTCPSU */ #define XPAR_XRTCPSU_NUM_INSTANCES 1 @@ -791,22 +849,22 @@ /******************************************************************/ /* Definitions for driver SCUGIC */ -#define XPAR_XSCUGIC_NUM_INSTANCES 1 +#define XPAR_XSCUGIC_NUM_INSTANCES 1U /* Definitions for peripheral PSU_RCPU_GIC */ -#define XPAR_PSU_RCPU_GIC_DEVICE_ID 0 -#define XPAR_PSU_RCPU_GIC_BASEADDR 0xF9001000 -#define XPAR_PSU_RCPU_GIC_HIGHADDR 0xF9001FFF -#define XPAR_PSU_RCPU_GIC_DIST_BASEADDR 0xF9000000 +#define XPAR_PSU_RCPU_GIC_DEVICE_ID 0U +#define XPAR_PSU_RCPU_GIC_BASEADDR 0xF9001000U +#define XPAR_PSU_RCPU_GIC_HIGHADDR 0xF9001FFFU +#define XPAR_PSU_RCPU_GIC_DIST_BASEADDR 0xF9000000U /******************************************************************/ /* Canonical definitions for peripheral PSU_RCPU_GIC */ -#define XPAR_SCUGIC_0_DEVICE_ID 0 -#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF9001000 -#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF9001FFF -#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF9000000 +#define XPAR_SCUGIC_0_DEVICE_ID 0U +#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF9001000U +#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF9001FFFU +#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF9000000U /******************************************************************/ @@ -818,24 +876,25 @@ #define XPAR_PSU_SD_1_DEVICE_ID 0 #define XPAR_PSU_SD_1_BASEADDR 0xFF170000 #define XPAR_PSU_SD_1_HIGHADDR 0xFF17FFFF -#define XPAR_PSU_SD_1_SDIO_CLK_FREQ_HZ 199998006 +#define XPAR_PSU_SD_1_SDIO_CLK_FREQ_HZ 187481250 #define XPAR_PSU_SD_1_HAS_CD 1 #define XPAR_PSU_SD_1_HAS_WP 1 -#define XPAR_PSU_SD_1_BUS_WIDTH 4 +#define XPAR_PSU_SD_1_BUS_WIDTH 8 #define XPAR_PSU_SD_1_MIO_BANK 1 #define XPAR_PSU_SD_1_HAS_EMIO 0 /******************************************************************/ +#define XPAR_PSU_SD_1_IS_CACHE_COHERENT 0 /* Canonical definitions for peripheral PSU_SD_1 */ #define XPAR_XSDPS_0_DEVICE_ID XPAR_PSU_SD_1_DEVICE_ID #define XPAR_XSDPS_0_BASEADDR 0xFF170000 #define XPAR_XSDPS_0_HIGHADDR 0xFF17FFFF -#define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 199998006 +#define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 187481250 #define XPAR_XSDPS_0_HAS_CD 1 #define XPAR_XSDPS_0_HAS_WP 1 -#define XPAR_XSDPS_0_BUS_WIDTH 4 +#define XPAR_XSDPS_0_BUS_WIDTH 8 #define XPAR_XSDPS_0_MIO_BANK 1 #define XPAR_XSDPS_0_HAS_EMIO 0 @@ -853,6 +912,7 @@ /******************************************************************/ +#define XPAR_PSU_AMS_REF_FREQMHZ 49.995 /* Canonical definitions for peripheral PSU_AMS */ #define XPAR_XSYSMONPSU_0_DEVICE_ID XPAR_PSU_AMS_DEVICE_ID #define XPAR_XSYSMONPSU_0_BASEADDR 0xFFA50000 @@ -862,133 +922,133 @@ /******************************************************************/ /* Definitions for driver TTCPS */ -#define XPAR_XTTCPS_NUM_INSTANCES 12 +#define XPAR_XTTCPS_NUM_INSTANCES 12U /* Definitions for peripheral PSU_TTC_0 */ -#define XPAR_PSU_TTC_0_DEVICE_ID 0 -#define XPAR_PSU_TTC_0_BASEADDR 0XFF110000 -#define XPAR_PSU_TTC_0_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_PSU_TTC_0_TTC_CLK_CLKSRC 0 -#define XPAR_PSU_TTC_1_DEVICE_ID 1 -#define XPAR_PSU_TTC_1_BASEADDR 0XFF110004 -#define XPAR_PSU_TTC_1_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_PSU_TTC_1_TTC_CLK_CLKSRC 0 -#define XPAR_PSU_TTC_2_DEVICE_ID 2 -#define XPAR_PSU_TTC_2_BASEADDR 0XFF110008 -#define XPAR_PSU_TTC_2_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_PSU_TTC_2_TTC_CLK_CLKSRC 0 +#define XPAR_PSU_TTC_0_DEVICE_ID 0U +#define XPAR_PSU_TTC_0_BASEADDR 0XFF110000U +#define XPAR_PSU_TTC_0_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_0_TTC_CLK_CLKSRC 0U +#define XPAR_PSU_TTC_1_DEVICE_ID 1U +#define XPAR_PSU_TTC_1_BASEADDR 0XFF110004U +#define XPAR_PSU_TTC_1_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_1_TTC_CLK_CLKSRC 0U +#define XPAR_PSU_TTC_2_DEVICE_ID 2U +#define XPAR_PSU_TTC_2_BASEADDR 0XFF110008U +#define XPAR_PSU_TTC_2_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_2_TTC_CLK_CLKSRC 0U /* Definitions for peripheral PSU_TTC_1 */ -#define XPAR_PSU_TTC_3_DEVICE_ID 3 -#define XPAR_PSU_TTC_3_BASEADDR 0XFF120000 -#define XPAR_PSU_TTC_3_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_PSU_TTC_3_TTC_CLK_CLKSRC 0 -#define XPAR_PSU_TTC_4_DEVICE_ID 4 -#define XPAR_PSU_TTC_4_BASEADDR 0XFF120004 -#define XPAR_PSU_TTC_4_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_PSU_TTC_4_TTC_CLK_CLKSRC 0 -#define XPAR_PSU_TTC_5_DEVICE_ID 5 -#define XPAR_PSU_TTC_5_BASEADDR 0XFF120008 -#define XPAR_PSU_TTC_5_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_PSU_TTC_5_TTC_CLK_CLKSRC 0 +#define XPAR_PSU_TTC_3_DEVICE_ID 3U +#define XPAR_PSU_TTC_3_BASEADDR 0XFF120000U +#define XPAR_PSU_TTC_3_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_3_TTC_CLK_CLKSRC 0U +#define XPAR_PSU_TTC_4_DEVICE_ID 4U +#define XPAR_PSU_TTC_4_BASEADDR 0XFF120004U +#define XPAR_PSU_TTC_4_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_4_TTC_CLK_CLKSRC 0U +#define XPAR_PSU_TTC_5_DEVICE_ID 5U +#define XPAR_PSU_TTC_5_BASEADDR 0XFF120008U +#define XPAR_PSU_TTC_5_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_5_TTC_CLK_CLKSRC 0U /* Definitions for peripheral PSU_TTC_2 */ -#define XPAR_PSU_TTC_6_DEVICE_ID 6 -#define XPAR_PSU_TTC_6_BASEADDR 0XFF130000 -#define XPAR_PSU_TTC_6_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_PSU_TTC_6_TTC_CLK_CLKSRC 0 -#define XPAR_PSU_TTC_7_DEVICE_ID 7 -#define XPAR_PSU_TTC_7_BASEADDR 0XFF130004 -#define XPAR_PSU_TTC_7_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_PSU_TTC_7_TTC_CLK_CLKSRC 0 -#define XPAR_PSU_TTC_8_DEVICE_ID 8 -#define XPAR_PSU_TTC_8_BASEADDR 0XFF130008 -#define XPAR_PSU_TTC_8_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_PSU_TTC_8_TTC_CLK_CLKSRC 0 +#define XPAR_PSU_TTC_6_DEVICE_ID 6U +#define XPAR_PSU_TTC_6_BASEADDR 0XFF130000U +#define XPAR_PSU_TTC_6_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_6_TTC_CLK_CLKSRC 0U +#define XPAR_PSU_TTC_7_DEVICE_ID 7U +#define XPAR_PSU_TTC_7_BASEADDR 0XFF130004U +#define XPAR_PSU_TTC_7_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_7_TTC_CLK_CLKSRC 0U +#define XPAR_PSU_TTC_8_DEVICE_ID 8U +#define XPAR_PSU_TTC_8_BASEADDR 0XFF130008U +#define XPAR_PSU_TTC_8_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_8_TTC_CLK_CLKSRC 0U /* Definitions for peripheral PSU_TTC_3 */ -#define XPAR_PSU_TTC_9_DEVICE_ID 9 -#define XPAR_PSU_TTC_9_BASEADDR 0XFF140000 -#define XPAR_PSU_TTC_9_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_PSU_TTC_9_TTC_CLK_CLKSRC 0 -#define XPAR_PSU_TTC_10_DEVICE_ID 10 -#define XPAR_PSU_TTC_10_BASEADDR 0XFF140004 -#define XPAR_PSU_TTC_10_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_PSU_TTC_10_TTC_CLK_CLKSRC 0 -#define XPAR_PSU_TTC_11_DEVICE_ID 11 -#define XPAR_PSU_TTC_11_BASEADDR 0XFF140008 -#define XPAR_PSU_TTC_11_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_PSU_TTC_11_TTC_CLK_CLKSRC 0 +#define XPAR_PSU_TTC_9_DEVICE_ID 9U +#define XPAR_PSU_TTC_9_BASEADDR 0XFF140000U +#define XPAR_PSU_TTC_9_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_9_TTC_CLK_CLKSRC 0U +#define XPAR_PSU_TTC_10_DEVICE_ID 10U +#define XPAR_PSU_TTC_10_BASEADDR 0XFF140004U +#define XPAR_PSU_TTC_10_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_10_TTC_CLK_CLKSRC 0U +#define XPAR_PSU_TTC_11_DEVICE_ID 11U +#define XPAR_PSU_TTC_11_BASEADDR 0XFF140008U +#define XPAR_PSU_TTC_11_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_11_TTC_CLK_CLKSRC 0U /******************************************************************/ /* Canonical definitions for peripheral PSU_TTC_0 */ #define XPAR_XTTCPS_0_DEVICE_ID XPAR_PSU_TTC_0_DEVICE_ID -#define XPAR_XTTCPS_0_BASEADDR 0xFF110000 -#define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0 +#define XPAR_XTTCPS_0_BASEADDR 0xFF110000U +#define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0U #define XPAR_XTTCPS_1_DEVICE_ID XPAR_PSU_TTC_1_DEVICE_ID -#define XPAR_XTTCPS_1_BASEADDR 0xFF110004 -#define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0 +#define XPAR_XTTCPS_1_BASEADDR 0xFF110004U +#define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0U #define XPAR_XTTCPS_2_DEVICE_ID XPAR_PSU_TTC_2_DEVICE_ID -#define XPAR_XTTCPS_2_BASEADDR 0xFF110008 -#define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0 +#define XPAR_XTTCPS_2_BASEADDR 0xFF110008U +#define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0U /* Canonical definitions for peripheral PSU_TTC_1 */ #define XPAR_XTTCPS_3_DEVICE_ID XPAR_PSU_TTC_3_DEVICE_ID -#define XPAR_XTTCPS_3_BASEADDR 0xFF120000 -#define XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_XTTCPS_3_TTC_CLK_CLKSRC 0 +#define XPAR_XTTCPS_3_BASEADDR 0xFF120000U +#define XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_3_TTC_CLK_CLKSRC 0U #define XPAR_XTTCPS_4_DEVICE_ID XPAR_PSU_TTC_4_DEVICE_ID -#define XPAR_XTTCPS_4_BASEADDR 0xFF120004 -#define XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_XTTCPS_4_TTC_CLK_CLKSRC 0 +#define XPAR_XTTCPS_4_BASEADDR 0xFF120004U +#define XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_4_TTC_CLK_CLKSRC 0U #define XPAR_XTTCPS_5_DEVICE_ID XPAR_PSU_TTC_5_DEVICE_ID -#define XPAR_XTTCPS_5_BASEADDR 0xFF120008 -#define XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_XTTCPS_5_TTC_CLK_CLKSRC 0 +#define XPAR_XTTCPS_5_BASEADDR 0xFF120008U +#define XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_5_TTC_CLK_CLKSRC 0U /* Canonical definitions for peripheral PSU_TTC_2 */ #define XPAR_XTTCPS_6_DEVICE_ID XPAR_PSU_TTC_6_DEVICE_ID -#define XPAR_XTTCPS_6_BASEADDR 0xFF130000 -#define XPAR_XTTCPS_6_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_XTTCPS_6_TTC_CLK_CLKSRC 0 +#define XPAR_XTTCPS_6_BASEADDR 0xFF130000U +#define XPAR_XTTCPS_6_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_6_TTC_CLK_CLKSRC 0U #define XPAR_XTTCPS_7_DEVICE_ID XPAR_PSU_TTC_7_DEVICE_ID -#define XPAR_XTTCPS_7_BASEADDR 0xFF130004 -#define XPAR_XTTCPS_7_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_XTTCPS_7_TTC_CLK_CLKSRC 0 +#define XPAR_XTTCPS_7_BASEADDR 0xFF130004U +#define XPAR_XTTCPS_7_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_7_TTC_CLK_CLKSRC 0U #define XPAR_XTTCPS_8_DEVICE_ID XPAR_PSU_TTC_8_DEVICE_ID -#define XPAR_XTTCPS_8_BASEADDR 0xFF130008 -#define XPAR_XTTCPS_8_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_XTTCPS_8_TTC_CLK_CLKSRC 0 +#define XPAR_XTTCPS_8_BASEADDR 0xFF130008U +#define XPAR_XTTCPS_8_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_8_TTC_CLK_CLKSRC 0U /* Canonical definitions for peripheral PSU_TTC_3 */ #define XPAR_XTTCPS_9_DEVICE_ID XPAR_PSU_TTC_9_DEVICE_ID -#define XPAR_XTTCPS_9_BASEADDR 0xFF140000 -#define XPAR_XTTCPS_9_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_XTTCPS_9_TTC_CLK_CLKSRC 0 +#define XPAR_XTTCPS_9_BASEADDR 0xFF140000U +#define XPAR_XTTCPS_9_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_9_TTC_CLK_CLKSRC 0U #define XPAR_XTTCPS_10_DEVICE_ID XPAR_PSU_TTC_10_DEVICE_ID -#define XPAR_XTTCPS_10_BASEADDR 0xFF140004 -#define XPAR_XTTCPS_10_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_XTTCPS_10_TTC_CLK_CLKSRC 0 +#define XPAR_XTTCPS_10_BASEADDR 0xFF140004U +#define XPAR_XTTCPS_10_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_10_TTC_CLK_CLKSRC 0U #define XPAR_XTTCPS_11_DEVICE_ID XPAR_PSU_TTC_11_DEVICE_ID -#define XPAR_XTTCPS_11_BASEADDR 0xFF140008 -#define XPAR_XTTCPS_11_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_XTTCPS_11_TTC_CLK_CLKSRC 0 +#define XPAR_XTTCPS_11_BASEADDR 0xFF140008U +#define XPAR_XTTCPS_11_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_11_TTC_CLK_CLKSRC 0U /******************************************************************/ @@ -1000,7 +1060,7 @@ #define XPAR_PSU_UART_0_DEVICE_ID 0 #define XPAR_PSU_UART_0_BASEADDR 0xFF000000 #define XPAR_PSU_UART_0_HIGHADDR 0xFF00FFFF -#define XPAR_PSU_UART_0_UART_CLK_FREQ_HZ 99998999 +#define XPAR_PSU_UART_0_UART_CLK_FREQ_HZ 99990000 #define XPAR_PSU_UART_0_HAS_MODEM 0 @@ -1008,7 +1068,7 @@ #define XPAR_PSU_UART_1_DEVICE_ID 1 #define XPAR_PSU_UART_1_BASEADDR 0xFF010000 #define XPAR_PSU_UART_1_HIGHADDR 0xFF01FFFF -#define XPAR_PSU_UART_1_UART_CLK_FREQ_HZ 99998999 +#define XPAR_PSU_UART_1_UART_CLK_FREQ_HZ 99990000 #define XPAR_PSU_UART_1_HAS_MODEM 0 @@ -1018,14 +1078,14 @@ #define XPAR_XUARTPS_0_DEVICE_ID XPAR_PSU_UART_0_DEVICE_ID #define XPAR_XUARTPS_0_BASEADDR 0xFF000000 #define XPAR_XUARTPS_0_HIGHADDR 0xFF00FFFF -#define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 99998999 +#define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 99990000 #define XPAR_XUARTPS_0_HAS_MODEM 0 /* Canonical definitions for peripheral PSU_UART_1 */ #define XPAR_XUARTPS_1_DEVICE_ID XPAR_PSU_UART_1_DEVICE_ID #define XPAR_XUARTPS_1_BASEADDR 0xFF010000 #define XPAR_XUARTPS_1_HIGHADDR 0xFF01FFFF -#define XPAR_XUARTPS_1_UART_CLK_FREQ_HZ 99998999 +#define XPAR_XUARTPS_1_UART_CLK_FREQ_HZ 99990000 #define XPAR_XUARTPS_1_HAS_MODEM 0 @@ -1034,16 +1094,17 @@ /* Definitions for driver USBPSU */ #define XPAR_XUSBPSU_NUM_INSTANCES 1 -/* Definitions for peripheral PSU_USB_0 */ -#define XPAR_PSU_USB_0_DEVICE_ID 0 -#define XPAR_PSU_USB_0_BASEADDR 0xFE200000 -#define XPAR_PSU_USB_0_HIGHADDR 0xFE20FFFF +/* Definitions for peripheral PSU_USB_XHCI_0 */ +#define XPAR_PSU_USB_XHCI_0_DEVICE_ID 0 +#define XPAR_PSU_USB_XHCI_0_BASEADDR 0xFE200000 +#define XPAR_PSU_USB_XHCI_0_HIGHADDR 0xFE20FFFF /******************************************************************/ -/* Canonical definitions for peripheral PSU_USB_0 */ -#define XPAR_XUSBPSU_0_DEVICE_ID XPAR_PSU_USB_0_DEVICE_ID +#define XPAR_PSU_USB_XHCI_0_IS_CACHE_COHERENT 0 +/* Canonical definitions for peripheral PSU_USB_XHCI_0 */ +#define XPAR_XUSBPSU_0_DEVICE_ID XPAR_PSU_USB_XHCI_0_DEVICE_ID #define XPAR_XUSBPSU_0_BASEADDR 0xFE200000 #define XPAR_XUSBPSU_0_HIGHADDR 0xFE20FFFF @@ -1051,35 +1112,48 @@ /******************************************************************/ /* Definitions for driver WDTPS */ -#define XPAR_XWDTPS_NUM_INSTANCES 2 +#define XPAR_XWDTPS_NUM_INSTANCES 3 + +/* Definitions for peripheral PSU_CSU_WDT */ +#define XPAR_PSU_CSU_WDT_DEVICE_ID 0 +#define XPAR_PSU_CSU_WDT_BASEADDR 0xFFCB0000 +#define XPAR_PSU_CSU_WDT_HIGHADDR 0xFFCBFFFF +#define XPAR_PSU_CSU_WDT_WDT_CLK_FREQ_HZ 100000000 + /* Definitions for peripheral PSU_WDT_0 */ -#define XPAR_PSU_WDT_0_DEVICE_ID 0 +#define XPAR_PSU_WDT_0_DEVICE_ID 1 #define XPAR_PSU_WDT_0_BASEADDR 0xFF150000 #define XPAR_PSU_WDT_0_HIGHADDR 0xFF15FFFF -#define XPAR_PSU_WDT_0_WDT_CLK_FREQ_HZ 99999001 +#define XPAR_PSU_WDT_0_WDT_CLK_FREQ_HZ 99989998 /* Definitions for peripheral PSU_WDT_1 */ -#define XPAR_PSU_WDT_1_DEVICE_ID 1 +#define XPAR_PSU_WDT_1_DEVICE_ID 2 #define XPAR_PSU_WDT_1_BASEADDR 0xFD4D0000 #define XPAR_PSU_WDT_1_HIGHADDR 0xFD4DFFFF -#define XPAR_PSU_WDT_1_WDT_CLK_FREQ_HZ 99999001 +#define XPAR_PSU_WDT_1_WDT_CLK_FREQ_HZ 99989998 /******************************************************************/ +/* Canonical definitions for peripheral PSU_CSU_WDT */ +#define XPAR_XWDTPS_0_DEVICE_ID XPAR_PSU_CSU_WDT_DEVICE_ID +#define XPAR_XWDTPS_0_BASEADDR 0xFFCB0000 +#define XPAR_XWDTPS_0_HIGHADDR 0xFFCBFFFF +#define XPAR_XWDTPS_0_WDT_CLK_FREQ_HZ 100000000 + /* Canonical definitions for peripheral PSU_WDT_0 */ -#define XPAR_XWDTPS_0_DEVICE_ID XPAR_PSU_WDT_0_DEVICE_ID -#define XPAR_XWDTPS_0_BASEADDR 0xFF150000 -#define XPAR_XWDTPS_0_HIGHADDR 0xFF15FFFF -#define XPAR_XWDTPS_0_WDT_CLK_FREQ_HZ 99999001 +#define XPAR_XWDTPS_1_DEVICE_ID XPAR_PSU_WDT_0_DEVICE_ID +#define XPAR_XWDTPS_1_BASEADDR 0xFF150000 +#define XPAR_XWDTPS_1_HIGHADDR 0xFF15FFFF +#define XPAR_XWDTPS_1_WDT_CLK_FREQ_HZ 99989998 /* Canonical definitions for peripheral PSU_WDT_1 */ -#define XPAR_XWDTPS_1_DEVICE_ID XPAR_PSU_WDT_1_DEVICE_ID -#define XPAR_XWDTPS_1_BASEADDR 0xFD4D0000 -#define XPAR_XWDTPS_1_HIGHADDR 0xFD4DFFFF -#define XPAR_XWDTPS_1_WDT_CLK_FREQ_HZ 99999001 +#define XPAR_XWDTPS_2_DEVICE_ID XPAR_PSU_WDT_1_DEVICE_ID +#define XPAR_XWDTPS_2_BASEADDR 0xFD4D0000 +#define XPAR_XWDTPS_2_HIGHADDR 0xFD4DFFFF +#define XPAR_XWDTPS_2_WDT_CLK_FREQ_HZ 99989998 /******************************************************************/ @@ -1217,6 +1291,22 @@ /******************************************************************/ +#define XPAR_PSU_ADMA_0_IS_CACHE_COHERENT 0 +#define XPAR_PSU_ADMA_1_IS_CACHE_COHERENT 0 +#define XPAR_PSU_ADMA_2_IS_CACHE_COHERENT 0 +#define XPAR_PSU_ADMA_3_IS_CACHE_COHERENT 0 +#define XPAR_PSU_ADMA_4_IS_CACHE_COHERENT 0 +#define XPAR_PSU_ADMA_5_IS_CACHE_COHERENT 0 +#define XPAR_PSU_ADMA_6_IS_CACHE_COHERENT 0 +#define XPAR_PSU_ADMA_7_IS_CACHE_COHERENT 0 +#define XPAR_PSU_GDMA_0_IS_CACHE_COHERENT 0 +#define XPAR_PSU_GDMA_1_IS_CACHE_COHERENT 0 +#define XPAR_PSU_GDMA_2_IS_CACHE_COHERENT 0 +#define XPAR_PSU_GDMA_3_IS_CACHE_COHERENT 0 +#define XPAR_PSU_GDMA_4_IS_CACHE_COHERENT 0 +#define XPAR_PSU_GDMA_5_IS_CACHE_COHERENT 0 +#define XPAR_PSU_GDMA_6_IS_CACHE_COHERENT 0 +#define XPAR_PSU_GDMA_7_IS_CACHE_COHERENT 0 /* Canonical definitions for peripheral PSU_ADMA_0 */ #define XPAR_XZDMA_0_DEVICE_ID XPAR_PSU_ADMA_0_DEVICE_ID #define XPAR_XZDMA_0_BASEADDR 0xFFA80000 @@ -1332,3 +1422,4 @@ /******************************************************************/ +#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/Makefile new file mode 100644 index 0000000..2a2195c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/Makefile
@@ -0,0 +1,40 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +CC_FLAGS = $(COMPILER_FLAGS) +ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +OUTS = *.o + +LIBSOURCES:=*.c +INCLUDEFILES:=*.h + +OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) + +libs: banner avbuf_libs clean + +%.o: %.c + ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< + +banner: + echo "Compiling avbuf" + +avbuf_libs: ${OBJECTS} + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} + +.PHONY: include +include: avbuf_includes + +avbuf_includes: + ${CP} ${INCLUDEFILES} ${INCLUDEDIR} + +clean: + rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/xavbuf.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/xavbuf.c new file mode 100644 index 0000000..34e841f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/xavbuf.c
@@ -0,0 +1,1092 @@ +/******************************************************************************* + * + * Copyright (C) 2017 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xavbuf.c + * + * This file implements all the functions related to the Video Pipeline of the + * DisplayPort Subsystem. See xavbuf.h for the detailed description of the + * driver. + * + * @note None. + * + * <pre> + * MODIFICATION HISTORY: + * + * Ver Who Date Changes + * ----- ---- -------- ----------------------------------------------- + * 1.0 aad 06/24/17 Initial release. + * 2.0 aad 10/08/17 Some APIs to use enums instead of Macros. + * Some bug fixes. + * </pre> + * +*******************************************************************************/ +/******************************* Include Files ********************************/ +#include "xavbuf.h" +#include "xstatus.h" + +/**************************** Constant Definitions ****************************/ +const XAVBuf_VideoAttribute XAVBuf_SupportedFormats[XAVBUF_NUM_SUPPORTED]; + +/******************************************************************************/ +/** + * This function sets the scaling factors depending on the source video stream. + * + * @param InstancePtr is a pointer to the XAVBuf instance. + * @param RegOffset is the register offset of the SF0 register from the + * DP BaseAddress. + * @param Scaling Factors is a pointer to the scaling factors needed for + * scaling colors to 12 BPC. + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +static void XAVBuf_SetScalingFactors(XAVBuf *InstancePtr, u32 RegOffset, + u32 *ScalingFactors) +{ + u32 Index = 0; + for (Index = 0; Index < 3; Index++) { + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, + RegOffset + (Index * 4), ScalingFactors[Index]); + } + +} + +/******************************************************************************/ +/** + * This function sets the Layer Control for Video and Graphics layers. + * + * @param InstancePtr is a pointer to the XAVBuf instance. + * @param RegOffset is the register offset of Video Layer or Graphics + * Layer from the base address + * @param Video is a pointer to the XAVBuf_VideoAttribute struct which + * has been configured for the particular layer + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +static void XAVBuf_SetLayerControl(XAVBuf *InstancePtr, u32 RegOffset, + XAVBuf_VideoAttribute *Video) +{ + u32 RegVal = 0; + + RegVal = (Video->IsRGB << + XAVBUF_V_BLEND_LAYER0_CONTROL_RGB_MODE_SHIFT) | + Video->SamplingEn; + + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, RegOffset, RegVal); +} + +/******************************************************************************/ +/** + * This function applies Attributes for Live source(Video/Graphics). + * + * @param InstancePtr is an pointer to the XAVBuf Instance. + * @param RegConfig is a register offset for Video or Graphics config + * register + * @param Video is a pointer to the attributes of the video to be applied + * + * @return None. + * + * @note Live source can be live Video or Live Graphics. +******************************************************************************/ +static void XAVBuf_SetLiveVideoAttributes(XAVBuf *InstancePtr, u32 RegConfig, + XAVBuf_VideoAttribute *Video) +{ + u32 RegVal = 0; + + RegVal |= Video->Value << XAVBUF_BUF_LIVE_VID_CFG_FORMAT_SHIFT; + RegVal |= Video->BPP/6 - 3; + RegVal |= Video->Swap << XAVBUF_BUF_LIVE_VID_CFG_CB_FIRST_SHIFT; + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, RegConfig, RegVal); +} + +/******************************************************************************/ +/** + * This function applies Attributes for Non - Live source(Video/Graphics). + * + * @param InstancePtr is an pointer to the XAVBuf Instance. + * @param VideoSrc is the source of the Non-Live Video + * @param Video is a pointer to the attributes of the video to be applied + * + * @return None. + * + * @note Non Live source can be Non Live Video or Non Live Graphics. +******************************************************************************/ +static void XAVBuf_SetNonLiveVideoAttributes(XAVBuf *InstancePtr, u32 VideoSrc, + XAVBuf_VideoAttribute *Video) +{ + u32 RegVal = 0; + + RegVal = XAVBuf_ReadReg(InstancePtr->Config.BaseAddr, + XAVBUF_BUF_FORMAT); + if(VideoSrc == XAVBUF_VIDSTREAM1_NONLIVE) { + RegVal &= ~XAVBUF_BUF_FORMAT_NL_VID_FORMAT_MASK; + RegVal |= Video->Value; + } + else if (VideoSrc == XAVBUF_VIDSTREAM2_NONLIVE_GFX) { + RegVal &= ~XAVBUF_BUF_FORMAT_NL_GRAPHX_FORMAT_MASK; + RegVal |= (Video->Value) << + XAVBUF_BUF_FORMAT_NL_GRAPHX_FORMAT_SHIFT; + } + + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_BUF_FORMAT, + RegVal); +} + +/******************************************************************************/ +/** + * This function programs the coeffitients for Color Space Conversion. + * + * @param InstancePtr is an pointer to the XAVBuf Instance. + * @param RegOffset is a register offset for Video or Graphics config + * register + * @param Video is a pointer to the XAVBuf_Attribute structure + * + * @return None. + * + * @note None. +******************************************************************************/ +static void XAVBuf_InConvertToRGB(XAVBuf *InstancePtr, u32 RegOffset, + XAVBuf_VideoAttribute *Video) +{ + u16 Index; + u16 *CSCMatrix; + u16 *OffsetMatrix; + + /* SDTV Coefficients */ + u16 CSCCoeffs[] = { 0x1000, 0x0000, 0x166F, + 0x1000, 0x7A7F, 0x7493, + 0x1000, 0x1C5A, 0x0000 }; + u16 CSCOffset[] = { 0x0000, 0x1800, 0x1800 }; + u16 RGBCoeffs[] = { 0x1000, 0x0000, 0x0000, + 0x0000, 0x1000, 0x0000, + 0x0000, 0x0000, 0x1000 }; + u16 RGBOffset[] = { 0x0000, 0x0000, 0x0000 }; + if(Video->IsRGB) { + CSCMatrix = RGBCoeffs; + OffsetMatrix = RGBOffset; + } + else { + CSCMatrix = CSCCoeffs; + OffsetMatrix = CSCOffset; + } + /* Program Colorspace conversion coefficients */ + for (Index = 9; Index < 12; Index++) { + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, + RegOffset + (Index * 4), + OffsetMatrix[Index - 9]); + } + + /* Program Colorspace conversion matrix */ + for (Index = 0; Index < 9; Index++) { + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, + RegOffset + (Index * 4), CSCMatrix[Index]); + } + +} + +/******************************************************************************/ +/** + * This function converts the Blender output to the desired output format. + * + * @param InstancePtr is an pointer to the XAVBuf Instance. + * @param RegConfig is a register offset for Video or Graphics config + * register + * @param Video is a pointer to the XAVBuf_Attribute structure + * + * @return None. + * + * @note None. +******************************************************************************/ +static void XAVBuf_InConvertToOutputFormat(XAVBuf *InstancePtr, + XAVBuf_VideoAttribute *Video) + +{ u32 Index = 0; + u32 RegOffset = XAVBUF_V_BLEND_RGB2YCBCR_COEFF0; + u32 ColorOffset = XAVBUF_V_BLEND_LUMA_OUTCSC_OFFSET; + u8 Value = Video->Value; + u16 *MatrixCoeff; + u16 *MatrixOffset; + + /* SDTV Coeffitients */ + u16 CSCCoeffs[] = { 0x04C8, 0x0964, 0x01D3, + 0x7D4C, 0x7AB4, 0x0800, + 0x0800, 0x7945, 0x7EB5 }; + u16 CSCOffset[] = { 0x0000, 0x800, 0x800 }; + u16 RGBCoeffs[] = { 0x1000, 0x0000, 0x0000, + 0x0000, 0x1000, 0x0000, + 0x0000, 0x0000, 0x1000 }; + u16 RGBOffset[] = { 0x0000, 0x0000, 0x0000 }; + + + if(Value) { + MatrixCoeff = CSCCoeffs; + MatrixOffset = CSCOffset; + + } + else { + MatrixCoeff = RGBCoeffs; + MatrixOffset = RGBOffset; + } + + for (Index = 0; Index < 9; Index++) { + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, + RegOffset + (Index * 4), MatrixCoeff[Index]); + } + for (Index = 0; Index < 3; Index++) { + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, + ColorOffset + (Index * 4), + (MatrixOffset[Index] << + XAVBUF_V_BLEND_LUMA_IN1CSC_OFFSET_POST_OFFSET_SHIFT)); + } +} +/******************************************************************************/ +/** + * This function configures the Video Pipeline for the selected source + * + * @param InstancePtr is an pointer to the XAVBuf Instance. + * @param VideoSrc is a parameter which indicates which Video Source + * selected + * + * @return None. + * + * @note None. +******************************************************************************/ +static int XAVBuf_ConfigureVideo(XAVBuf *InstancePtr, u8 VideoSrc) +{ + + u32 RegConfig = 0; + u32 ScalingOffset = 0; + u32 LayerOffset = 0; + u32 CSCOffset = 0; + XAVBuf_VideoAttribute *Video = NULL; + u32 *ScalingFactors = NULL; + + Xil_AssertNonvoid(InstancePtr != NULL); + switch(VideoSrc) { + case XAVBUF_VIDSTREAM1_LIVE: + RegConfig = XAVBUF_BUF_LIVE_VID_CFG; + ScalingOffset = XAVBUF_BUF_LIVE_VID_COMP0_SF; + LayerOffset = XAVBUF_V_BLEND_LAYER0_CONTROL; + CSCOffset = XAVBUF_V_BLEND_IN1CSC_COEFF0; + Video = InstancePtr->AVMode.LiveVideo; + ScalingFactors = Video->SF; + + /* Set the Video Attributes */ + XAVBuf_SetLiveVideoAttributes(InstancePtr, RegConfig, + Video); + break; + + case XAVBUF_VIDSTREAM2_LIVE_GFX: + RegConfig = XAVBUF_BUF_LIVE_GFX_CFG; + ScalingOffset = XAVBUF_BUF_LIVE_GFX_COMP0_SF; + LayerOffset = XAVBUF_V_BLEND_LAYER1_CONTROL; + CSCOffset = XAVBUF_V_BLEND_IN2CSC_COEFF0; + Video = InstancePtr->AVMode.LiveGraphics; + ScalingFactors = Video->SF; + + /* Set the Video Attributes */ + XAVBuf_SetLiveVideoAttributes(InstancePtr, RegConfig, + Video); + break; + + case XAVBUF_VIDSTREAM1_NONLIVE: + RegConfig = XAVBUF_BUF_LIVE_GFX_CFG; + ScalingOffset = XAVBUF_BUF_VID_COMP0_SCALE_FACTOR; + LayerOffset = XAVBUF_V_BLEND_LAYER0_CONTROL; + CSCOffset = XAVBUF_V_BLEND_IN1CSC_COEFF0; + Video = InstancePtr->AVMode.NonLiveVideo; + ScalingFactors = Video->SF; + + /* Set the Video Attributes */ + XAVBuf_SetNonLiveVideoAttributes(InstancePtr, VideoSrc, + Video); + break; + + case XAVBUF_VIDSTREAM2_NONLIVE_GFX: + RegConfig = XAVBUF_BUF_LIVE_GFX_CFG; + ScalingOffset = XAVBUF_BUF_GRAPHICS_COMP0_SCALE_FACTOR; + LayerOffset = XAVBUF_V_BLEND_LAYER1_CONTROL; + CSCOffset = XAVBUF_V_BLEND_IN2CSC_COEFF0; + Video = InstancePtr->AVMode.NonLiveGraphics; + ScalingFactors = Video->SF; + + /* Set the Video Attributes */ + XAVBuf_SetNonLiveVideoAttributes(InstancePtr, VideoSrc, + Video); + break; + case XAVBUF_VIDSTREAM1_TPG: + RegConfig |= 1 << + XAVBUF_V_BLEND_LAYER0_CONTROL_RGB_MODE_SHIFT; + RegConfig |= 1 << + XAVBUF_V_BLEND_LAYER0_CONTROL_BYPASS_SHIFT; + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, + XAVBUF_V_BLEND_LAYER0_CONTROL, + RegConfig); + break; + default: + return XST_FAILURE; + } + /* Setting the scaling factors */ + XAVBuf_SetScalingFactors(InstancePtr, ScalingOffset, ScalingFactors); + /* Layer Control */ + XAVBuf_SetLayerControl(InstancePtr, LayerOffset, Video); + /* Colorspace conversion */ + XAVBuf_InConvertToRGB(InstancePtr, CSCOffset, Video); + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function intializes the configuration for the AVBuf Instance. + * + * @param InstancePtr is a pointer to the XAVBuf instance. + * @param BaseAddr sets the base address of the AVBuf instance + * @param Deviceid is the id of the device from the design. + * + * @return None. + * + * @note Base address and DeviceId is same as the DP Core driver. + * +*******************************************************************************/ +void XAVBuf_CfgInitialize(XAVBuf *InstancePtr, u32 BaseAddr, u16 DeviceId) +{ + Xil_AssertVoid(InstancePtr != NULL); + + InstancePtr->Config.DeviceId = DeviceId; + InstancePtr->Config.BaseAddr = BaseAddr; +} + +/******************************************************************************/ +/** + * This function initializes all the data structures of the XAVBuf Instance. + * + * @param InstancePtr is a pointer to the XAVBuf instance. + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +void XAVBuf_Initialize(XAVBuf *InstancePtr) +{ + Xil_AssertVoid(InstancePtr != NULL); + + InstancePtr->AVMode.NonLiveVideo = NULL; + InstancePtr->AVMode.LiveVideo = NULL; + InstancePtr->AVMode.LiveGraphics = NULL; + InstancePtr->AVMode.NonLiveGraphics = NULL; + InstancePtr->AVMode.VideoSrc = XAVBUF_VIDSTREAM1_NONE; + InstancePtr->AVMode.GraphicsSrc = XAVBUF_VIDSTREAM2_NONE; + InstancePtr->AVMode.Audio = NULL; + InstancePtr->AVMode.GraphicsAudio = NULL; + InstancePtr->AVMode.AudioSrc1 = XAVBUF_AUDSTREAM1_NO_AUDIO; + InstancePtr->AVMode.AudioSrc2 = XAVBUF_AUDSTREAM2_NO_AUDIO; + + InstancePtr->Blender.GlobalAlphaEn = 0; + InstancePtr->Blender.Alpha = 0; + InstancePtr->Blender.OutputVideo = NULL; + + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_AUD_SOFT_RST, 0); +} + +/******************************************************************************/ +/** + * This function selects the source for the Video and Graphics streams that are + * passed on to the blender block. + * + * @param InstancePtr is a pointer to the XAVBuf instance. + * @param VidStream selects the stream coming from the video sources + * @param GfxStream selects the stream coming from the graphics sources + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +void XAVBuf_InputVideoSelect(XAVBuf *InstancePtr, XAVBuf_VideoStream VidStream, + XAVBuf_GfxStream GfxStream) +{ + + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid((VidStream != XAVBUF_VIDSTREAM1_LIVE) | + (VidStream != XAVBUF_VIDSTREAM1_NONLIVE) | + (VidStream != XAVBUF_VIDSTREAM1_TPG) | + (VidStream != XAVBUF_VIDSTREAM1_NONE)); + Xil_AssertVoid((GfxStream != XAVBUF_VIDSTREAM2_DISABLEGFX) | + (GfxStream != XAVBUF_VIDSTREAM2_NONLIVE_GFX) | + (GfxStream != XAVBUF_VIDSTREAM2_LIVE_GFX) | + (GfxStream != XAVBUF_VIDSTREAM2_NONE)); + + InstancePtr->AVMode.VideoSrc = VidStream; + InstancePtr->AVMode.GraphicsSrc = GfxStream; + u32 RegVal; + RegVal = XAVBuf_ReadReg(InstancePtr->Config.BaseAddr, + XAVBUF_BUF_OUTPUT_AUD_VID_SELECT); + RegVal &= ~(XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_VID_STREAM2_SEL_MASK | + XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_VID_STREAM1_SEL_MASK); + RegVal |= VidStream | GfxStream; + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, + XAVBUF_BUF_OUTPUT_AUD_VID_SELECT, RegVal); +} + +/******************************************************************************/ +/** + * This function sets the video format for the non-live video + * + * @param InstancePtr is a pointer to the XAVBuf instance. + * @param Format is the enum for the non-live video format + * + * @return XST_SUCCESS if the correct format has been set. + * XST_FAILURE if the format is invalid. + * + * @note None. +*******************************************************************************/ +int XAVBuf_SetInputNonLiveVideoFormat(XAVBuf *InstancePtr, + XAVBuf_VideoFormat Format) +{ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid((Format >= CbY0CrY1) | (Format <= YV16Ci2_420_10BPC)); + + InstancePtr->AVMode.NonLiveVideo = + XAVBuf_GetNLiveVideoAttribute(Format); + if(InstancePtr->AVMode.NonLiveVideo == NULL) + return XST_FAILURE; + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function sets the graphics format for the non-live video + * + * @param InstancePtr is a pointer to the XAVBuf instance. + * @param Format is the enum for the non-live video format + * + * @return XST_SUCCESS if the correct format has been set. + * XST_FAILURE if the format is invalid. + * + * @note None. +*******************************************************************************/ +int XAVBuf_SetInputNonLiveGraphicsFormat(XAVBuf *InstancePtr, + XAVBuf_VideoFormat Format) +{ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid((Format >= RGBA8888) |( Format <= YOnly)); + + InstancePtr->AVMode.NonLiveGraphics = + XAVBuf_GetNLGraphicsAttribute(Format); + if(InstancePtr->AVMode.NonLiveGraphics == NULL) + return XST_FAILURE; + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function sets the video format for the live video + * + * @param InstancePtr is a pointer to the XAVBuf instance. + * @param Format is the enum for the non-live video format + * + * @return XST_SUCCESS if the correct format has been set. + * XST_FAILURE if the format is invalid. + * + * @note None. +*******************************************************************************/ +int XAVBuf_SetInputLiveVideoFormat(XAVBuf *InstancePtr, + XAVBuf_VideoFormat Format) +{ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid((Format >= RGB_6BPC) | (Format <= YOnly_12BPC)); + + InstancePtr->AVMode.LiveVideo = XAVBuf_GetLiveVideoAttribute(Format); + if(InstancePtr->AVMode.LiveVideo == NULL) + return XST_FAILURE; + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function sets the graphics format for the live video + * + * @param InstancePtr is a pointer to the XAVBuf instance. + * @param Format is the enum for the non-live video format + * + * @return XST_SUCCESS if the correct format has been set. + * XST_FAILURE if the format is invalid. + * + * @note None. +*******************************************************************************/ +int XAVBuf_SetInputLiveGraphicsFormat(XAVBuf *InstancePtr, + XAVBuf_VideoFormat Format) +{ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid((Format >= RGB_6BPC) | (Format <= YOnly_12BPC)); + + InstancePtr->AVMode.LiveGraphics = + XAVBuf_GetLiveVideoAttribute(Format); + if(InstancePtr->AVMode.LiveGraphics == NULL) + return XST_FAILURE; + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function sets the Output Video Format + * + * @param InstancePtr is a pointer to the XAVBuf instance. + * @param Format is the enum for the non-live video format + * + * @return XST_SUCCESS if the correct format has been set. + * XST_FAILURE if the format is invalid. + * + * @note None. +*******************************************************************************/ +int XAVBuf_SetOutputVideoFormat(XAVBuf *InstancePtr, XAVBuf_VideoFormat Format) +{ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid((Format >= RGB_6BPC) | (Format <= YOnly_12BPC)); + + InstancePtr->Blender.OutputVideo = + XAVBuf_GetLiveVideoAttribute(Format); + if(InstancePtr->Blender.OutputVideo == NULL) + return XST_FAILURE; + else + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function sets the Audio and Video Clock Source and the video timing + * source. + * + * @param InstancePtr is a pointer to the XAVBuf instance. + * @param VideoClk selects the Video Clock Source + * @param AudioClk selects the Audio Clock Source + * + * @return None. + * + * @note System uses PL Clock for Video when Live source is in use. + * +*******************************************************************************/ +void XAVBuf_SetAudioVideoClkSrc(XAVBuf *InstancePtr, u8 VideoClk, u8 AudioClk) +{ + + u32 RegVal = 0; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid((VideoClk != XAVBUF_PS_CLK) | + (VideoClk!= XAVBUF_PL_CLK)); + Xil_AssertVoid((AudioClk != XAVBUF_PS_CLK) | + (AudioClk!= XAVBUF_PL_CLK)); + + if((InstancePtr->AVMode.VideoSrc != XAVBUF_VIDSTREAM1_LIVE) && + (InstancePtr->AVMode.GraphicsSrc != XAVBUF_VIDSTREAM2_LIVE_GFX)) { + RegVal = 1 << + XAVBUF_BUF_AUD_VID_CLK_SOURCE_VID_TIMING_SRC_SHIFT; + } + else if((InstancePtr->AVMode.VideoSrc == XAVBUF_VIDSTREAM1_LIVE) || + (InstancePtr->AVMode.GraphicsSrc == + XAVBUF_VIDSTREAM2_LIVE_GFX)) { + VideoClk = XAVBUF_PL_CLK; + } + + RegVal |= (VideoClk << + XAVBUF_BUF_AUD_VID_CLK_SOURCE_VID_CLK_SRC_SHIFT) | + (AudioClk << + XAVBUF_BUF_AUD_VID_CLK_SOURCE_AUD_CLK_SRC_SHIFT); + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, + XAVBUF_BUF_AUD_VID_CLK_SOURCE, RegVal); + /*Soft Reset VideoPipeline when changing the clock source*/ + XAVBuf_SoftReset(InstancePtr); +} + +/******************************************************************************/ +/** + * This function applies a soft reset to the Audio Video pipeline. + * + * @param InstancePtr is a pointer to the XAVBuf instance. + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +void XAVBuf_SoftReset(XAVBuf *InstancePtr) +{ + Xil_AssertVoid(InstancePtr != NULL); + + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_BUF_SRST_REG, + XAVBUF_BUF_SRST_REG_VID_RST_MASK); + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_BUF_SRST_REG, 0); +} + +/******************************************************************************/ +/** + * This function looks up if the video format is valid or not for the non-live + * video datapath and returns a pointer to the attributes of the video. + * + * @param Format takes in the video format for which attributes are being + * requested. + * + * @return A pointer to the structure XAVBuf_VideoAttribute if the video + * format is valid, else returns NULL. + * @note None. +*******************************************************************************/ +XAVBuf_VideoAttribute *XAVBuf_GetLiveVideoAttribute(XAVBuf_VideoFormat Format) +{ + u8 Index = 0; + XAVBuf_VideoAttribute *VideoAttribute; + Xil_AssertNonvoid((Format >= RGB_6BPC) | (Format <= YOnly_12BPC)); + + for (Index = RGB_6BPC; Index <= YOnly_12BPC; Index++) { + VideoAttribute = (XAVBuf_VideoAttribute *) + &XAVBuf_SupportedFormats[Index]; + if(Format == VideoAttribute->VideoFormat) { + return VideoAttribute; + } + } + return NULL; +} + +/******************************************************************************/ +/** + * This function looks up if the video format is valid or not and returns a + * pointer to the attributes of the video. + * + * @param Format takes in the video format for which attributes are being + * requested. + * + * @return A pointer to the structure XAVBuf_VideoAttribute if the video + * format is valid, else returns NULL. + * @note None. +*******************************************************************************/ +XAVBuf_VideoAttribute *XAVBuf_GetNLiveVideoAttribute(XAVBuf_VideoFormat Format) +{ + u8 Index = 0; + XAVBuf_VideoAttribute *VideoAttribute; + + Xil_AssertNonvoid((Format >= CbY0CrY1) | (Format <= YV16Ci2_420_10BPC)); + + for (Index = CbY0CrY1; Index <= YV16Ci2_420_10BPC; Index++) { + VideoAttribute = (XAVBuf_VideoAttribute *) + &XAVBuf_SupportedFormats[Index]; + if(Format == VideoAttribute->VideoFormat) { + return VideoAttribute; + } + } + return NULL; +} + +/******************************************************************************/ +/** + * This function looks up if the video format is valid or not and returns a + * pointer to the attributes of the video. + * + * @param Format takes in the video format for which attributes are being + * requested. + * + * @return A pointer to the structure XAVBuf_VideoAttribute if the video + * format is valid, else returns NULL. + * @note None. +*******************************************************************************/ +XAVBuf_VideoAttribute *XAVBuf_GetNLGraphicsAttribute(XAVBuf_VideoFormat Format) +{ + u32 Index = 0; + XAVBuf_VideoAttribute *VideoAttribute; + + Xil_AssertNonvoid((Format >= RGBA8888) | (Format <= YOnly)); + + for(Index = RGBA8888; Index <= YOnly; Index++) { + VideoAttribute = (XAVBuf_VideoAttribute *) + &XAVBuf_SupportedFormats[Index]; + if(Format == VideoAttribute->VideoFormat) { + return VideoAttribute; + } + } + return NULL; +} + +/******************************************************************************/ +/** + * This function configures the Video Pipeline + * + * @param InstancePtr is an pointer to the XAVBuf Instance. + * + * @return None. + * + * @note None. +******************************************************************************/ +void XAVBuf_ConfigureVideoPipeline(XAVBuf *InstancePtr) +{ + Xil_AssertVoid(InstancePtr != NULL); + + XAVBuf_ConfigureVideo(InstancePtr, InstancePtr->AVMode.VideoSrc); +} + +/******************************************************************************/ +/** + * This function configures the Graphics Pipeline + * + * @param InstancePtr is an pointer to the XAVBuf Instance. + * + * @return None. + * + * @note None. +******************************************************************************/ +void XAVBuf_ConfigureGraphicsPipeline(XAVBuf *InstancePtr) +{ + Xil_AssertVoid(InstancePtr != NULL); + XAVBuf_ConfigureVideo(InstancePtr, InstancePtr->AVMode.GraphicsSrc); +} + +/******************************************************************************/ +/** + * This function sets the blender background color + * + * @param InstancePtr is an pointer to the XAVBuf Instance. + * @param Color is a pointer to the structure XAVBuf_BlenderBgClr + * + * @return None. + * + * @note None. +******************************************************************************/ +void XAVBuf_BlendSetBgColor(XAVBuf *InstancePtr, XAVBuf_BlenderBgClr *Color) +{ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(Color != NULL); + + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_V_BLEND_BG_CLR_0, + Color->RCr); + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_V_BLEND_BG_CLR_1, + Color->GY); + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_V_BLEND_BG_CLR_2, + Color->BCb); +} + +/******************************************************************************/ +/** + * This function enables or disables global alpha + * + * @param InstancePtr is an pointer to the XAVBuf Instance. + * @param Enable sets a software flag for global alpha + * @param Alpha sets the value for the global alpha blending + * + * @return None. + * + * @note GlobalAlphaEn = 1, enables the global alpha. + * GlobalAlphaEn = 0, disables the global alpha. + * Alpha = 0, passes stream2 + * Alpha = 255, passes stream1 +******************************************************************************/ +void XAVBuf_SetBlenderAlpha(XAVBuf *InstancePtr, u8 Alpha, u8 Enable) +{ + u32 RegVal; + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid((Enable !=0) | (Enable != 1)); + + InstancePtr->Blender.GlobalAlphaEn = Enable; + InstancePtr->Blender.Alpha = Alpha; + + RegVal = Enable; + RegVal |= Alpha << XAVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG_VALUE_SHIFT; + + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, + XAVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG, RegVal); +} + +/******************************************************************************/ +/** + * This function configures the Output of the Video Pipeline + * + * @param InstancePtr is an pointer to the XAVBuf Instance. + * @param OutputVideo is a pointer to the XAVBuf_VideoAttribute. + * + * @return None. + * + * @note None. +******************************************************************************/ +void XAVBuf_ConfigureOutputVideo(XAVBuf *InstancePtr) +{ + u32 RegVal = 0; + XAVBuf_VideoAttribute *OutputVideo = InstancePtr->Blender.OutputVideo; + + RegVal |= OutputVideo->SamplingEn << + XAVBUF_V_BLEND_OUTPUT_VID_FORMAT_EN_DOWNSAMPLE_SHIFT; + RegVal |= OutputVideo->Value; + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, + XAVBUF_V_BLEND_OUTPUT_VID_FORMAT, RegVal); + + XAVBuf_InConvertToOutputFormat(InstancePtr, OutputVideo); +} + +/******************************************************************************/ +/** + * This function selects the source for audio streams corresponding to the + * Video and Graphics streams that are passed on to the blender + * + * @param InstancePtr is a pointer to the XAVBuf instance. + * @param AudStream1 selects the audio stream source corresponding to + * the video source selected + * @param AudStream2 selects the audio stream source corresponding to + * the graphics source selected. + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +void XAVBuf_InputAudioSelect(XAVBuf *InstancePtr, XAVBuf_AudioStream1 AudStream1, + XAVBuf_AudioStream2 AudStream2) +{ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid((AudStream1 != XAVBUF_AUDSTREAM1_NONLIVE) | + (AudStream1 != XAVBUF_AUDSTREAM1_LIVE) | + (AudStream1 != XAVBUF_AUDSTREAM1_TPG)); + Xil_AssertVoid((AudStream2 != XAVBUF_AUDSTREAM2_NO_AUDIO) | + (AudStream2 != XAVBUF_AUDSTREAM2_AUDIOGFX)); + + u32 RegVal; + RegVal = XAVBuf_ReadReg(InstancePtr->Config.BaseAddr, + XAVBUF_BUF_OUTPUT_AUD_VID_SELECT); + RegVal &= ~(XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_AUD_STREAM2_SEL_MASK | + XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_AUD_STREAM1_SEL_MASK); + RegVal |= AudStream1 | AudStream2; + + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, + XAVBUF_BUF_OUTPUT_AUD_VID_SELECT, RegVal); +} + +/******************************************************************************/ +/** + * This function sets up the scaling factor for Audio Mixer Volume Control. + * + * @param InstancePtr is a pointer to the XAVBuf instance. + * @param Channel0Volume is the volume to be set for Audio from Channel0 + * @param Channel1Volume is the volume to be set for Audio from Channel1 + * + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +void XAVBuf_AudioMixerVolumeControl(XAVBuf *InstancePtr, u8 Channel0Volume, + u8 Channel1Volume) +{ + u32 Val; + Xil_AssertVoid(InstancePtr != NULL); + Val = Channel1Volume << + XAVBUF_AUD_MIXER_VOLUME_CONTROL_VOL_CTRL_CH1_SHIFT; + Val |= Channel0Volume; + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, + XAVBUF_AUD_MIXER_VOLUME_CONTROL, Val); +} + +/******************************************************************************/ +/** + * This function resets the Audio Pipe. + * + * @param InstancePtr is a pointer to the XAVBuf Instance. + * + * @returns None. + * + * @note Needed when non-live audio is disabled. + * + * + ******************************************************************************/ +void XAVBuf_AudioSoftReset(XAVBuf *InstancePtr) +{ + u32 RegVal = 0; + Xil_AssertVoid(InstancePtr != NULL); + RegVal = XAVBuf_ReadReg(InstancePtr->Config.BaseAddr, + XAVBUF_AUD_SOFT_RST); + RegVal |= XAVBUF_AUD_SOFT_RST_AUD_SRST_MASK; + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_AUD_SOFT_RST, + RegVal); + RegVal &= ~XAVBUF_AUD_SOFT_RST_AUD_SRST_MASK; + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_AUD_SOFT_RST, 0); + +} + +/******************************************************************************/ +/** + * This function enables End of Line Reset for reduced blanking resolutions. + * + * @param InstancePtr is a pointer to the XAVBuf Instance. + * @param Disable is to be set while using Reduced Blanking Resolutions. + * + * @returns None. + * + * @note None. + * + ******************************************************************************/ +void XABuf_LineResetDisable(XAVBuf *InstancePtr, u8 Disable) +{ + u32 RegVal = 0; + Xil_AssertVoid(InstancePtr != NULL); + RegVal = XAVBuf_ReadReg(InstancePtr->Config.BaseAddr, + XAVBUF_AUD_SOFT_RST); + if(Disable) + RegVal |= XAVBUF_AUD_SOFT_RST_LINE_RST_DISABLE_MASK; + else + RegVal &= ~XAVBUF_AUD_SOFT_RST_LINE_RST_DISABLE_MASK; + + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_AUD_SOFT_RST, + RegVal); +} + +/******************************************************************************/ +/** + * This function enables the video channel interface between the DPDMA and the + * AVBuf + * + * @param InstancePtr is a pointer to the XAVBuf Instance. + * @param Enable sets the corresponding buffers. + * + * @returns None. + * + * @note None. + * + ******************************************************************************/ +void XAVBuf_EnableVideoBuffers(XAVBuf *InstancePtr, u8 Enable) +{ + u8 Index; + u32 RegVal = 0; + u8 NumPlanes = InstancePtr->AVMode.NonLiveVideo->Mode; + + RegVal = (0xF << XAVBUF_CHBUF0_BURST_LEN_SHIFT) | + (XAVBUF_CHBUF0_FLUSH_MASK); + + for (Index = 0; Index <= NumPlanes; Index++) { + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, + XAVBUF_CHBUF0 + (Index * 4), RegVal); + } + if(Enable) { + RegVal = (0xF << XAVBUF_CHBUF0_BURST_LEN_SHIFT) | + XAVBUF_CHBUF0_EN_MASK; + for (Index = 0; Index <= NumPlanes; Index++) { + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, + XAVBUF_CHBUF0 + (Index * 4), RegVal); + } + } +} +/******************************************************************************/ +/** + * This function enables the graphics interface between the DPDMA and the AVBuf. + * + * @param InstancePtr is a pointer to the XAVBuf Instance. + * @param Enable sets the corresponding buffers. + * + * @returns None. + * + * @note None. + * + ******************************************************************************/ +void XAVBuf_EnableGraphicsBuffers(XAVBuf *InstancePtr, u8 Enable) +{ + u32 RegVal = 0; + + RegVal = (0xF << XAVBUF_CHBUF3_BURST_LEN_SHIFT) | + XAVBUF_CHBUF3_FLUSH_MASK; + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_CHBUF3, RegVal); + if(Enable) { + RegVal = (0xF << XAVBUF_CHBUF3_BURST_LEN_SHIFT) | + XAVBUF_CHBUF0_EN_MASK; + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_CHBUF3, + RegVal); + } +} + +/******************************************************************************/ +/** + * This function enables the audio interface between the DPDMA and the AVBuf + * + * @param InstancePtr is a pointer to the XAVBuf Instance. + * @param Enable sets the corresponding buffers. + * + * @returns None. + * + * @note None. + * + ******************************************************************************/ +void XAVBuf_EnableAudio0Buffers(XAVBuf *InstancePtr, u8 Enable) +{ + u32 RegVal = 0; + + RegVal = (0x3 << XAVBUF_CHBUF4_BURST_LEN_SHIFT) | + XAVBUF_CHBUF4_FLUSH_MASK; + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_CHBUF4, RegVal); + if(Enable) { + RegVal = (0x3 << XAVBUF_CHBUF4_BURST_LEN_SHIFT) | + XAVBUF_CHBUF4_EN_MASK; + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_CHBUF4, + RegVal); + } +} + +/******************************************************************************/ +/** + * This function enables the audio interface between the DPDMA and the AVBuf + * + * @param InstancePtr is a pointer to the XAVBuf Instance. + * @param Enable sets the corresponding buffers. + * + * @returns None. + * + * @note None. + * + ******************************************************************************/ +void XAVBuf_EnableAudio1Buffers(XAVBuf *InstancePtr, u8 Enable) +{ + u32 RegVal = 0; + + RegVal = (0x3 << XAVBUF_CHBUF5_BURST_LEN_SHIFT) | + XAVBUF_CHBUF5_FLUSH_MASK; + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_CHBUF5, RegVal); + if(Enable) { + RegVal = (0x3 << XAVBUF_CHBUF5_BURST_LEN_SHIFT) | + XAVBUF_CHBUF5_EN_MASK; + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_CHBUF5, + RegVal); + } +}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/xavbuf.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/xavbuf.h new file mode 100644 index 0000000..386bfba --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/xavbuf.h
@@ -0,0 +1,302 @@ +/******************************************************************************* + * + * Copyright (C) 2017 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xavbuf.h + * + * This file implements all the functions related to the Video Pipeline of the + * DisplayPort Subsystem. + * + * Features supported by this driver + * - Live Video and Graphics input. + * - Non-Live Video Graphics input. + * - Output Formats Supported - RGB, YUV444, YUV4222. + * + * + * <pre> + * MODIFICATION HISTORY: + * + * Ver Who Date Changes + * ----- ---- -------- ----------------------------------------------- + * 1.0 aad 06/24/17 Initial release. + * 2.0 aad 10/07/17 Added Enums for Video and Audio sources. + * </pre> + * +*******************************************************************************/ +#ifndef XAVBUF_H_ +/* Prevent circular inclusions by using protection macros. */ +#define XAVBUF_H_ + + +/******************************* Include Files ********************************/ +#include "xavbuf_hw.h" +#include "sleep.h" +/****************************** Type Definitions ******************************/ +/** + * This typedef describes all the Video Formats supported by the driver + */ +typedef enum { + //Non-Live Video Formats + CbY0CrY1, + CrY0CbY1, + Y0CrY1Cb, + Y0CbY1Cr, + YV16, + YV24, + YV16Ci, + MONOCHROME, + YV16Ci2, + YUV444, + RGB888, + RGBA8880, + RGB888_10BPC, + YUV444_10BPC, + YV16Ci2_10BPC, + YV16Ci_10BPC, + YV16_10BPC, + YV24_10BPC, + MONOCHROME_10BPC, + YV16_420, + YV16Ci_420, + YV16Ci2_420, + YV16_420_10BPC, + YV16Ci_420_10BPC, + YV16Ci2_420_10BPC, + + // Non-Live Graphics formats + RGBA8888, + ABGR8888, + RGB888_GFX, + BGR888, + RGBA5551, + RGBA4444, + RGB565, + BPP8, + BPP4, + BPP2, + BPP1, + YUV422, + YOnly, + + //Live Input/Output Video/Graphics Formats + RGB_6BPC, + RGB_8BPC, + RGB_10BPC, + RGB_12BPC, + YCbCr444_6BPC, + YCbCr444_8BPC, + YCbCr444_10BPC, + YCbCr444_12BPC, + YCbCr422_8BPC, + YCbCr422_10BPC, + YCbCr422_12BPC, + YOnly_8BPC, + YOnly_10BPC, + YOnly_12BPC, +} XAVBuf_VideoFormat; + +/** + * This data structure describes video planes. + */ +typedef enum { + Interleaved, + SemiPlanar, + Planar +} XAVBuf_VideoModes; + +/** + * This typedef describes the video source list + */ +typedef enum { + XAVBUF_VIDSTREAM1_LIVE, + XAVBUF_VIDSTREAM1_NONLIVE, + XAVBUF_VIDSTREAM1_TPG, + XAVBUF_VIDSTREAM1_NONE, +} XAVBuf_VideoStream; + +/** + * This typedef describes the graphics source list + */ +typedef enum { + XAVBUF_VIDSTREAM2_DISABLEGFX = 0x0, + XAVBUF_VIDSTREAM2_NONLIVE_GFX = 0x4, + XAVBUF_VIDSTREAM2_LIVE_GFX = 0x8, + XAVBUF_VIDSTREAM2_NONE = 0xC0, +} XAVBuf_GfxStream; + +/** + * This typedef describes the audio stream 1 source list + */ +typedef enum { + XAVBUF_AUDSTREAM1_LIVE = 0x00, + XAVBUF_AUDSTREAM1_NONLIVE = 0x10, + XAVBUF_AUDSTREAM1_TPG = 0x20, + XAVBUF_AUDSTREAM1_NO_AUDIO = 0x30, +} XAVBuf_AudioStream1; + +/** + * This typedef describes the audio stream 2 source list + */ +typedef enum { + XAVBUF_AUDSTREAM2_NO_AUDIO = 0X00, + XAVBUF_AUDSTREAM2_AUDIOGFX = 0X40, +} XAVBuf_AudioStream2; + +/** + * This typedef describes the attributes associated with the video formats. + */ +typedef struct { + XAVBuf_VideoFormat VideoFormat; + u8 Value; + XAVBuf_VideoModes Mode; + u32 SF[3]; + u8 SamplingEn; + u8 IsRGB; + u8 Swap; + u8 BPP; +} XAVBuf_VideoAttribute; + +/** + * This typedef stores the attributes of an audio stream + */ +typedef struct { + u32 Volume; + u8 SwapLR; +} XAVBuf_AudioAttribute; + +/** + * This typedef stores the data associated with the Audio Video input modes. + */ +typedef struct { + XAVBuf_VideoAttribute *NonLiveVideo, *NonLiveGraphics; + XAVBuf_VideoAttribute *LiveVideo, *LiveGraphics; + XAVBuf_AudioAttribute *Audio, *GraphicsAudio; + XAVBuf_VideoStream VideoSrc; + XAVBuf_GfxStream GraphicsSrc; + XAVBuf_AudioStream1 AudioSrc1; + XAVBuf_AudioStream2 AudioSrc2; + u8 AudioClk, VideoClk; +} XAVBuf_AVModes; + +/** + * This structure stores the background color information. + */ +typedef struct { + u16 RCr; + u16 GY; + u16 BCb; +} XAVBuf_BlenderBgClr; + +/** + * This typedef stores the AVBuf Configuration information. + */ +typedef struct { + u16 DeviceId; + u32 BaseAddr; +} XAVBuf_Config; + +/** + * This typedef stores all the attributes associated to the Blender block of the + * DisplayPort Subsystem + */ +typedef struct { + u8 GlobalAlphaEn; + u8 Alpha; + XAVBuf_VideoAttribute *OutputVideo; +} XAVBuf_Blender; + +/** + * The XAVBuf driver instance data. The user is required to allocate a variable + * of this type for every XAVBUF instance in the system. A pointer to this type + * is then passed to the driver API functions + */ +typedef struct { + XAVBuf_Config Config; + XAVBuf_AVModes AVMode; + XAVBuf_Blender Blender; +} XAVBuf; + + +/**************************** Function Prototypes *****************************/ + +/* xavbuf.c: Setup and initialization functions. */ +void XAVBuf_CfgInitialize(XAVBuf *InstancePtr, u32 BaseAddr, u16 DeviceId); + +/* xavbuf.c: Functions to setup the Input Video and Audio sources */ +void XAVBuf_InputVideoSelect(XAVBuf *InstancePtr, XAVBuf_VideoStream VidStream, + XAVBuf_GfxStream GfxStream); +void XAVBuf_InputAudioSelect(XAVBuf *InstancePtr, XAVBuf_AudioStream1 AudStream, + XAVBuf_AudioStream2 AudioStream2); + +/* xavbuf.c: Functions to setup the Video Format attributes */ +int XAVBuf_SetInputNonLiveVideoFormat(XAVBuf *InstancePtr, + XAVBuf_VideoFormat Format); +int XAVBuf_SetInputNonLiveGraphicsFormat(XAVBuf *InstancePtr, + XAVBuf_VideoFormat Format); +int XAVBuf_SetInputLiveVideoFormat(XAVBuf *InstancePtr, + XAVBuf_VideoFormat Format); +int XAVBuf_SetInputLiveGraphicsFormat(XAVBuf *InstancePtr, + XAVBuf_VideoFormat Format); +int XAVBuf_SetOutputVideoFormat(XAVBuf *InstancePtr, XAVBuf_VideoFormat Format); +XAVBuf_VideoAttribute *XAVBuf_GetLiveVideoAttribute(XAVBuf_VideoFormat Format); +XAVBuf_VideoAttribute *XAVBuf_GetNLiveVideoAttribute(XAVBuf_VideoFormat Format); +XAVBuf_VideoAttribute *XAVBuf_GetNLGraphicsAttribute(XAVBuf_VideoFormat Format); + +/* xavbuf.c: Functions to setup the clock sources for video and audio */ +void XAVBuf_SetAudioVideoClkSrc(XAVBuf *InstancePtr, u8 VideoClk, u8 AudioClk); + +/* xavbuf.c: Functions that setup Video and Graphics pipeline depending on the + * sources and format selected. + */ +void XAVBuf_ConfigureVideoPipeline(XAVBuf *InstancePtr); +void XAVBuf_ConfigureGraphicsPipeline(XAVBuf *InstancePtr); + +/* Functions to setup Blender Properties */ +void XAVBuf_BlendSetBgColor(XAVBuf *InstancePtr, XAVBuf_BlenderBgClr *Color); +void XAVBuf_SetBlenderAlpha(XAVBuf *InstancePtr, u8 Alpha, u8 Enable); +void XAVBuf_SoftReset(XAVBuf *InstancePtr); +void XABuf_LineResetDisable(XAVBuf *InstancePtr, u8 Disable); +void XAVBuf_ConfigureOutputVideo(XAVBuf *InstancePtr); + +/* Audio Configuration functions */ +void XAVBuf_AudioSoftReset(XAVBuf *InstancePtr); +void XAVBuf_AudioMixerVolumeControl(XAVBuf *InstancePtr, u8 Channel0Volume, + u8 Channel1Volume); + +/* DPDMA Interface functions */ +void XAVBuf_EnableGraphicsBuffers(XAVBuf *InstancePtr, u8 Enable); +void XAVBuf_EnableVideoBuffers(XAVBuf *InstancePtr, u8 Enable); +void XAVBuf_EnableAudio0Buffers(XAVBuf *InstancePtr, u8 Enable); +void XAVBuf_EnableAudio1Buffers(XAVBuf *InstancePtr, u8 Enable); + +#endif //XAVBUF_H_
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/xavbuf_clk.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/xavbuf_clk.c new file mode 100644 index 0000000..6ef5d70 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/xavbuf_clk.c
@@ -0,0 +1,561 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xavbuf.c + * + * This header file contains PLL configuring functions. These Functions + * calculates and configures the PLL depending on desired frequency. + * + * @note None. + * + * <pre> + * MODIFICATION HISTORY: + * + * Ver Who Date Changes + * ----- ---- -------- ----------------------------------------------- + * 1.0 mh 06/24/17 Initial release. + * 2.1 tu 12/29/17 LPD and FPD offsets adjusted + * </pre> + * +*******************************************************************************/ +/******************************* Include Files ********************************/ +#include "xavbuf_clk.h" + +/**************************** Constant Definitions ****************************/ +/*Input Frequency for the PLL with precision upto two decimals*/ +#define XAVBUF_INPUT_REF_CLK 3333333333 + +/*Frequency of VCO before divider to meet jitter requirement*/ +#define XAVBUF_PLL_OUT_FREQ 1450000000 + +/* Precision of Input Ref Frequency for PLL*/ +#define XAVBUF_INPUT_FREQ_PRECISION 100 + +/* 16 bit fractional shift to get Integer */ +#define XAVBUF_PRECISION 16 +#define XAVBUF_SHIFT_DECIMAL (1 << XAVBUF_PRECISION) +#define XAVBUF_DECIMAL (XAVBUF_SHIFT_DECIMAL - 1) +#define XDPSSU_MAX_VIDEO_FREQ 300000000 + +#define XAVBUF_AUDIO_SAMPLES 512 +#define XAVBUF_AUDIO_SAMPLE_RATE_44_1 44100 +#define XAVBUF_AUDIO_SAMPLE_RATE_48_0 48000 +#define XAVBUF_EXTERNAL_DIVIDER 2 + +/* Register offsets for address manipulation */ +#define XAVBUF_REG_OFFSET 4 +#define XAVBUF_FPD_CTRL_OFFSET 12 +#define XAVBUF_LPD_CTRL_OFFSET 16 +#define MOD_3(a) ((a) % (3)) + +/*************************** Constant Variable Definitions ********************/ +/** + * This typedef enumerates capacitor resistor and lock values to be programmed. + */ +typedef struct{ + u16 cp; + u16 res; + u16 lfhf; + u16 lock_dly; + u16 lock_cnt; +}PllConfig; + +/* PLL fractional divide programming table*/ +static const PllConfig PllFracDivideTable[] = { + {3, 5, 3, 63, 1000}, + {3, 5, 3, 63, 1000}, + {3, 9, 3, 63, 1000}, + {3, 9, 3, 63, 1000}, + {3, 9, 3, 63, 1000}, + {3, 9, 3, 63, 1000}, + {3, 14, 3, 63, 1000}, + {3, 14, 3, 63, 1000}, + {3, 14, 3, 63, 1000}, + {3, 14, 3, 63, 1000}, + {3, 14, 3, 63, 1000}, + {3, 14, 3, 63, 1000}, + {3, 14, 3, 63, 1000}, + {3, 14, 3, 63, 975}, + {3, 14, 3, 63, 950}, + {3, 14, 3, 63, 925}, + {3, 1, 3, 63, 900}, + {3, 1, 3, 63, 875}, + {3, 1, 3, 63, 850}, + {3, 1, 3, 63, 850}, + {3, 1, 3, 63, 825}, + {3, 1, 3, 63, 800}, + {3, 1, 3, 63, 775}, + {3, 6, 3, 63, 775}, + {3, 6, 3, 63, 750}, + {3, 6, 3, 63, 725}, + {3, 6, 3, 63, 700}, + {3, 6, 3, 63, 700}, + {3, 6, 3, 63, 675}, + {3, 6, 3, 63, 675}, + {3, 6, 3, 63, 650}, + {3, 6, 3, 63, 650}, + {3, 6, 3, 63, 625}, + {3, 6, 3, 63, 625}, + {3, 6, 3, 63, 625}, + {3, 6, 3, 63, 600}, + {3, 6, 3, 63, 600}, + {3, 6, 3, 63, 600}, + {3, 6, 3, 63, 600}, + {3, 6, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {4, 6, 3, 63, 600}, + {4, 6, 3, 63, 600}, + {4, 6, 3, 63, 600}, + {4, 6, 3, 63, 600}, + {4, 6, 3, 63, 600}, + {4, 6, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600} +}; + +/******************************************************************************/ +/** + * This function initializes the parameters required to configure PLL. + * + * @param PllInstancePtr is pointer to the XAVBuf_Pll instance. + * @param Pll is the PLL chosen to be configured. + * @param Pll is the PLL chosen to be configured. + * @param CrossDomain is the bool which is used to mention if the PLL + * outputs in other domain. + * @param ExtDividerCnt is number of external divider out of VCO. + * + * @return XST_SUCCESS if PLL is configured without an error. + * XST_FAILURE otherwise. + * + * @note In order to avoid floating point usage we have a 16bit + * fractional fixed point arithmetic implementation + * +*******************************************************************************/ +static void XAVBuf_PllInitialize(XAVBuf_Pll *PllInstancePtr, + u8 Pll, u8 CrossDomain , u8 ExtDividerCnt) +{ + /* Instantiate input frequency. */ + PllInstancePtr->InputRefClk = XAVBUF_Pss_Ref_Clk; + PllInstancePtr->RefClkFreqhz = XAVBUF_INPUT_REF_CLK; + /* Turn on internal Divider*/ + PllInstancePtr->Divider = 1; + PllInstancePtr->Pll = Pll; + PllInstancePtr->ExtDividerCnt = ExtDividerCnt; + + //Check if CrossDomain is requested + if(CrossDomain) + PllInstancePtr->DomainSwitchDiv = 6; + else + PllInstancePtr->DomainSwitchDiv = 1; + //Check where PLL falls + if (Pll>2){ + PllInstancePtr->Fpd = 0; + PllInstancePtr->BaseAddress = XAVBUF_CLK_LPD_BASEADDR; + PllInstancePtr->Offset = XAVBUF_LPD_CTRL_OFFSET; + } + else{ + PllInstancePtr->Fpd = 1; + PllInstancePtr->BaseAddress = XAVBUF_CLK_FPD_BASEADDR; + PllInstancePtr->Offset = XAVBUF_FPD_CTRL_OFFSET; + } + +} + +/******************************************************************************/ +/** + * This function calculates the parameters which are required to configure PLL + * depending upon the requested frequency. + * + * @param PllInstancePtr is pointer to the XAVBuf_Pll instance + * @param FreqHz is the requested frequency to DP in Hz + * + * @return XST_SUCCESS if parameters are calculated + * XST_FAILURE otherwise. + * + * @note In order to avoid floating point usage we have a 16bit + * fractional fixed point arithmetic implementation + * +*******************************************************************************/ +static int XAVBuf_PllCalcParameterValues(XAVBuf_Pll *PllInstancePtr, + u64 FreqHz) +{ + u64 ExtDivider, Vco, VcoIntFrac; + + /* Instantiate input frequency. */ + PllInstancePtr->InputRefClk = XAVBUF_Pss_Ref_Clk; + PllInstancePtr->RefClkFreqhz = XAVBUF_INPUT_REF_CLK ; + /* Turn on internal Divider*/ + PllInstancePtr->Divider = 1; + PllInstancePtr->DomainSwitchDiv = 1; + + /* Estimate the total divider. */ + ExtDivider = (XAVBUF_PLL_OUT_FREQ / FreqHz) / + PllInstancePtr->DomainSwitchDiv; + if(ExtDivider > 63 && PllInstancePtr->ExtDividerCnt == 2){ + PllInstancePtr->ExtDivider0 = 63; + PllInstancePtr->ExtDivider1 = ExtDivider / 63; + } + else if(ExtDivider < 63){ + PllInstancePtr->ExtDivider0 = ExtDivider; + PllInstancePtr->ExtDivider1 = 1; + } + else + return XST_FAILURE; + + Vco = FreqHz *(PllInstancePtr->ExtDivider1 * + PllInstancePtr->ExtDivider0 * 2) * + PllInstancePtr->DomainSwitchDiv; + /* Calculate integer and fractional part. */ + VcoIntFrac = (Vco * XAVBUF_INPUT_FREQ_PRECISION * + XAVBUF_SHIFT_DECIMAL) / + PllInstancePtr->RefClkFreqhz ; + PllInstancePtr->Fractional = VcoIntFrac & XAVBUF_DECIMAL; + PllInstancePtr->FracIntegerFBDIV = VcoIntFrac >> XAVBUF_PRECISION; + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function will Read modify and write into corresponding registers. + * + * @param BaseAddress is the base address to which the value has to be + * written. + * @param RegOffset is the relative offset from Base address. + * @param Mask is used to select the number of bits to be modified. + * @param Shift is the number bits to be shifted from LSB. + * @param Data is the Data to be written. + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +static void XAVBuf_ReadModifyWriteReg(u32 BaseAddress, u32 RegOffset, u32 Mask, + u32 Shift, u32 Data) +{ + u32 RegValue; + + RegValue = XAVBuf_ReadReg(BaseAddress, RegOffset); + RegValue = (RegValue & ~Mask) | (Data << Shift); + XAVBuf_WriteReg(BaseAddress, RegOffset, RegValue); +} + +/******************************************************************************/ +/** + * This function configures PLL. + * + * @param PllInstancePtr is pointer to the XAVBuf_Pll instance. + * + * @return XST_SUCCESS if PLL is configured without an error. + * XST_FAILURE otherwise. + * + * @note None. + * +*******************************************************************************/ +static int XAVBuf_ConfigurePll(XAVBuf_Pll *PllInstancePtr) +{ + u64 BaseAddress = PllInstancePtr->BaseAddress; + u64 timer = 0; + u32 RegPll = 0; + u8 Pll = PllInstancePtr->Pll; + + RegPll |= XAVBUF_ENABLE_BIT << XAVBUF_PLL_CTRL_BYPASS_SHIFT; + RegPll |= PllInstancePtr->FracIntegerFBDIV << + XAVBUF_PLL_CTRL_FBDIV_SHIFT; + RegPll |= PllInstancePtr->Divider << XAVBUF_PLL_CTRL_DIV2_SHIFT; + RegPll |= PllInstancePtr->InputRefClk << XAVBUF_PLL_CTRL_PRE_SRC_SHIFT; + XAVBuf_WriteReg(BaseAddress, XAVBUF_PLL_CTRL + (MOD_3(Pll) * + PllInstancePtr->Offset), RegPll); + RegPll = 0; + /* Set the values for lock dly, lock counter, capacitor and resistor. */ + RegPll |= + PllFracDivideTable[PllInstancePtr->FracIntegerFBDIV -25].cp + << XAVBUF_PLL_CFG_CP_SHIFT; + RegPll |= + PllFracDivideTable[PllInstancePtr->FracIntegerFBDIV -25].res + << XAVBUF_PLL_CFG_RES_SHIFT; + RegPll |= + PllFracDivideTable[PllInstancePtr->FracIntegerFBDIV -25].lfhf + << XAVBUF_PLL_CFG_LFHF_SHIFT; + RegPll |= + PllFracDivideTable[PllInstancePtr->FracIntegerFBDIV -25].lock_dly + << XAVBUF_PLL_CFG_LOCK_DLY_SHIFT; + RegPll |= + PllFracDivideTable[PllInstancePtr->FracIntegerFBDIV -25].lock_cnt + << XAVBUF_PLL_CFG_LOCK_CNT_SHIFT; + XAVBuf_WriteReg(BaseAddress, XAVBUF_PLL_CFG + (MOD_3(Pll) * + PllInstancePtr->Offset), RegPll); + /* Enable and set Fractional Data. */ + XAVBuf_WriteReg(BaseAddress, XAVBUF_PLL_FRAC_CFG + (MOD_3(Pll) * + PllInstancePtr->Offset), (1 << XAVBUF_PLL_FRAC_CFG_ENABLED_SHIFT) | + (PllInstancePtr->Fractional << + XAVBUF_PLL_FRAC_CFG_DATA_SHIFT)); + /* Assert reset to the PLL. */ + XAVBuf_ReadModifyWriteReg(BaseAddress, XAVBUF_PLL_CTRL + (MOD_3(Pll) * + PllInstancePtr->Offset), + XAVBUF_PLL_CTRL_RESET_MASK, XAVBUF_PLL_CTRL_RESET_SHIFT, + XAVBUF_ENABLE_BIT); + + /* Deassert reset to the PLL. */ + XAVBuf_ReadModifyWriteReg(BaseAddress, XAVBUF_PLL_CTRL + (MOD_3(Pll) * + PllInstancePtr->Offset), + XAVBUF_PLL_CTRL_RESET_MASK, XAVBUF_PLL_CTRL_RESET_SHIFT, + XAVBUF_DISABLE_BIT); + + while(!(XAVBuf_ReadReg(BaseAddress, XAVBUF_PLL_STATUS - + ((1 - PllInstancePtr->Fpd) * XAVBUF_REG_OFFSET)) & + (1 << MOD_3(Pll)))) + if(++timer > 1000) + return XST_FAILURE; + + /* Deassert Bypass. */ + XAVBuf_ReadModifyWriteReg(BaseAddress, XAVBUF_PLL_CTRL + (MOD_3(Pll) * + PllInstancePtr->Offset), + XAVBUF_PLL_CTRL_BYPASS_MASK, XAVBUF_PLL_CTRL_BYPASS_SHIFT, + XAVBUF_DISABLE_BIT); + + if(PllInstancePtr->DomainSwitchDiv != 1) + XAVBuf_ReadModifyWriteReg(BaseAddress, (XAVBUF_DOMAIN_SWITCH_CTRL + + (MOD_3(Pll) * XAVBUF_REG_OFFSET) - ((1 - PllInstancePtr->Fpd) + * XAVBUF_REG_OFFSET)), + XAVBUF_DOMAIN_SWITCH_DIVISOR0_MASK, + XAVBUF_DOMAIN_SWITCH_DIVISOR0_SHIFT, + PllInstancePtr->DomainSwitchDiv); + usleep(1); + + return XST_SUCCESS; + +} + +/******************************************************************************/ +/** + * This function configures Configures external divider. + * + * @param PllInstancePtr is pointer to the XAVBuf_Pll instance. + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +static void XAVBuf_ConfigureExtDivider(XAVBuf_Pll *PllInstancePtr, + u64 BaseAddress, u32 Offset) +{ + XAVBuf_ReadModifyWriteReg(BaseAddress, Offset, + XAVBUF_VIDEO_REF_CTRL_CLKACT_MASK, + XAVBUF_VIDEO_REF_CTRL_CLKACT_SHIFT, XAVBUF_DISABLE_BIT); + XAVBuf_ReadModifyWriteReg(BaseAddress, Offset, + XAVBUF_VIDEO_REF_CTRL_DIVISOR1_MASK, + XAVBUF_VIDEO_REF_CTRL_DIVISOR1_SHIFT, + PllInstancePtr->ExtDivider1); + XAVBuf_ReadModifyWriteReg(BaseAddress, Offset, + XAVBUF_VIDEO_REF_CTRL_DIVISOR0_MASK, + XAVBUF_VIDEO_REF_CTRL_DIVISOR0_SHIFT, + PllInstancePtr->ExtDivider0); + XAVBuf_ReadModifyWriteReg(BaseAddress, Offset, + XAVBUF_VIDEO_REF_CTRL_CLKACT_MASK, + XAVBUF_VIDEO_REF_CTRL_CLKACT_SHIFT, XAVBUF_ENABLE_BIT); + XAVBuf_WriteReg(BaseAddress, Offset, 0x1011003); +} + +/******************************************************************************/ +/** + * This function calls API to calculate and configure PLL with desired frequency + * for Video. + * + * @param FreqHz is the desired frequency in Hz. + * + * @return XST_SUCCESS if PLL is configured without an error. + * XST_FAILURE otherwise. + * + * @note The Pll used is design specific. + * +*******************************************************************************/ +int XAVBuf_SetPixelClock(u64 FreqHz) +{ + u32 PllAssigned; + XAVBuf_Pll PllInstancePtr; + u8 Pll, CrossDomain, Flag; + + /*Verify Input Arguments*/ + Xil_AssertNonvoid(FreqHz < XDPSSU_MAX_VIDEO_FREQ); + + PllAssigned = XAVBuf_ReadReg(XAVBUF_CLK_FPD_BASEADDR, + XAVBUF_VIDEO_REF_CTRL) & XAVBUF_VIDEO_REF_CTRL_SRCSEL_MASK; + + switch (PllAssigned) { + case XAVBUF_VPLL_SRC_SEL: + Pll = VPLL; + CrossDomain = 0; + break; + case XAVBUF_DPLL_SRC_SEL: + Pll = DPLL; + CrossDomain = 0; + break; + case XAVBUF_RPLL_TO_FPD_SRC_SEL: + Pll = RPLL; + CrossDomain = 1; + break; + default: + return XST_FAILURE; + } + + /*Calculate configure PLL and External Divider*/ + XAVBuf_PllInitialize(&PllInstancePtr, Pll, CrossDomain, + XAVBUF_EXTERNAL_DIVIDER); + Flag = XAVBuf_PllCalcParameterValues(&PllInstancePtr, FreqHz); + if(Flag != 0) + return XST_FAILURE; + Flag = XAVBuf_ConfigurePll(&PllInstancePtr); + if(Flag != 0) + return XST_FAILURE; + XAVBuf_ConfigureExtDivider(&PllInstancePtr, XAVBUF_CLK_FPD_BASEADDR, + XAVBUF_VIDEO_REF_CTRL); + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function calls API to calculate and configure PLL with desired + * frequency for Audio. + * + * @param FreqHz is the desired frequency in Hz. + * + * @return XST_SUCCESS if PLL is configured without an error. + * XST_FAILURE otherwise. + * + * @note The Pll used is design specific. + * +*******************************************************************************/ +int XAVBuf_SetAudioClock(u64 FreqHz) +{ + u32 Flag, PllAssigned; + u8 Pll, CrossDomain; + XAVBuf_Pll XAVBuf_RPllInstancePtr; + + /*Verify Input Arguments*/ + Flag = (FreqHz == (XAVBUF_AUDIO_SAMPLE_RATE_44_1 * + XAVBUF_AUDIO_SAMPLES)) || + (FreqHz == (XAVBUF_AUDIO_SAMPLE_RATE_48_0 * + XAVBUF_AUDIO_SAMPLES)); + Xil_AssertNonvoid(Flag); + + PllAssigned = XAVBuf_ReadReg(XAVBUF_CLK_FPD_BASEADDR, + XAVBUF_AUDIO_REF_CTRL) & + XAVBUF_AUDIO_REF_CTRL_SRCSEL_MASK; + + switch (PllAssigned) { + case XAVBUF_VPLL_SRC_SEL: + Pll = VPLL; + CrossDomain = 0; + break; + case XAVBUF_DPLL_SRC_SEL: + Pll = DPLL; + CrossDomain = 0; + break; + case XAVBUF_RPLL_TO_FPD_SRC_SEL: + Pll = RPLL; + CrossDomain = 1; + break; + default: + return XST_FAILURE; + } + + /*Calculate configure PLL and External Divider*/ + XAVBuf_PllInitialize(&XAVBuf_RPllInstancePtr, Pll, CrossDomain, + XAVBUF_EXTERNAL_DIVIDER); + Flag = XAVBuf_PllCalcParameterValues(&XAVBuf_RPllInstancePtr, FreqHz); + if(Flag != 0) + return XST_FAILURE; + Flag = XAVBuf_ConfigurePll(&XAVBuf_RPllInstancePtr); + if(Flag != 0) + return XST_FAILURE; + XAVBuf_ConfigureExtDivider(&XAVBuf_RPllInstancePtr, + XAVBUF_CLK_FPD_BASEADDR, XAVBUF_AUDIO_REF_CTRL); + + return XST_SUCCESS; +}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/xavbuf_clk.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/xavbuf_clk.h new file mode 100644 index 0000000..91ca3b5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/xavbuf_clk.h
@@ -0,0 +1,97 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xavbuf_clk.h + * + * This header file contains the identifiers and low-level driver functions (or + * macros) that can be used to configure PLL to generate required frequency. + * + * @note None. + * + * <pre> + * MODIFICATION HISTORY: + * + * Ver Who Date Changes + * ----- ---- -------- ----------------------------------------------- + * 1.0 mh 06/24/17 Initial release. + * 2.1 tu 12/29/17 LPD and FPD offsets adjusted + * </pre> + * +*******************************************************************************/ + +#ifndef XAVBUF_CLK_H_ +#define XAVBUF_CLK_H_ + +/******************************* Include Files ********************************/ +#include "xavbuf_hw.h" +#include "xstatus.h" +#include "sleep.h" + +/****************************** Type Definitions ******************************/ +/** + * This enum enumerates various PLL + */ +enum PLL{ + APLL = 0, + DPLL = 1, + VPLL = 2, + IOPLL = 3, + RPLL = 4 +}; + +/** + * This typedef enumerates various variables used to configure Pll + */ +typedef struct { + u64 BaseAddress; + u64 Fractional; + u64 RefClkFreqhz; + u32 Divider; + u8 Offset; + u8 ClkDividBy2; + u8 ExtDivider0; + u8 ExtDivider1; + u8 ExtDividerCnt; + u8 DomainSwitchDiv; + u8 FracIntegerFBDIV; + u8 IntegerFBDIV; + u8 InputRefClk; + u8 Fpd; + u8 Pll; +}XAVBuf_Pll; + +/**************************** Function Prototypes *****************************/ +int XAVBuf_SetPixelClock(u64 FreqHz); +int XAVBuf_SetAudioClock(u64 FreqHz); +#endif /* XAVBUF_CLK_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/xavbuf_g.c similarity index 89% copy from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_g.c copy to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/xavbuf_g.c index 5913cd8..325e01b 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_g.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/xavbuf_g.c
@@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -38,17 +38,17 @@ *******************************************************************/ #include "xparameters.h" -#include "xrtcpsu.h" +#include "xavbuf.h" /* * The configuration table for devices */ -XRtcPsu_Config XRtcPsu_ConfigTable[] = +XAVBuf_Config XAVBuf_ConfigTable[XPAR_XAVBUF_NUM_INSTANCES] = { { - XPAR_PSU_RTC_DEVICE_ID, - XPAR_PSU_RTC_BASEADDR + XPAR_PSU_DP_DEVICE_ID, + XPAR_PSU_DP_BASEADDR } };
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/xavbuf_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/xavbuf_hw.h new file mode 100644 index 0000000..3454fa0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/xavbuf_hw.h
@@ -0,0 +1,1675 @@ +/******************************************************************************* + * + * Copyright C 2014 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xavbuf_hw.h + * + * This header file contains macros that can be used to access the device + * + * @note None. + * + * <pre> + * MODIFICATION HISTORY: + * + * Ver Who Date Changes + * ----- ---- -------- ----------------------------------------------- + * 1.0 aad 02/24/17 Initial Release + * 1.0 mh 06/24/17 Added Clock related register information + * 2.0 aad 10/07/17 Removed Macros related to Video and Audio Src + * </pre> + * +*******************************************************************************/ +#ifndef XAVBUF_HW_H_ +/* Prevent circular inclusions by using protection macros. */ +#define XAVBUF_HW_H_ + +#ifdef __cplusplus +extern "C" { +#endif +/***************************** Include Files **********************************/ + +#include "xil_io.h" +#include "xil_types.h" + +/************************** Constant Definitions ******************************/ + +/******************************************************************************/ +/** + * Address mapping for the DisplayPort TX core. + * +*******************************************************************************/ + +#define XAVBUF_BASEADDR 0xFD4A0000 +/** + * * Register: XAVBUF_V_BLEND_BG_CLR_0 + * */ +#define XAVBUF_V_BLEND_BG_CLR_0 0X0000A000 + +#define XAVBUF_V_BLEND_BG_CLR_0_CLR0_SHIFT 0 +#define XAVBUF_V_BLEND_BG_CLR_0_CLR0_WIDTH 12 +#define XAVBUF_V_BLEND_BG_CLR_0_CLR0_MASK 0X00000FFF + +/** + * * Register: XAVBUF_V_BLEND_BG_CLR_1 + * */ +#define XAVBUF_V_BLEND_BG_CLR_1 0X0000A004 + +#define XAVBUF_V_BLEND_BG_CLR_1_CLR1_SHIFT 0 +#define XAVBUF_V_BLEND_BG_CLR_1_CLR1_WIDTH 12 +#define XAVBUF_V_BLEND_BG_CLR_1_CLR1_MASK 0X00000FFF + +/** + * * Register: XAVBUF_V_BLEND_BG_CLR_2 + * */ +#define XAVBUF_V_BLEND_BG_CLR_2 0X0000A008 + +#define XAVBUF_V_BLEND_BG_CLR_2_CLR2_SHIFT 0 +#define XAVBUF_V_BLEND_BG_CLR_2_CLR2_WIDTH 12 +#define XAVBUF_V_BLEND_BG_CLR_2_CLR2_MASK 0X00000FFF + +/** + * * Register: XAVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG + * */ +#define XAVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG 0X0000A00C + +#define XAVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG_VALUE_SHIFT 1 +#define XAVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG_VALUE_WIDTH 8 +#define XAVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG_VALUE_MASK 0X000001FE + +#define XAVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG_EN_SHIFT 0 +#define XAVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG_EN_WIDTH 1 +#define XAVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG_EN_MASK 0X00000001 + +/** + * * Register: XAVBUF_V_BLEND_OUTPUT_VID_FORMAT + * */ +#define XAVBUF_V_BLEND_OUTPUT_VID_FORMAT 0X0000A014 + +#define XAVBUF_V_BLEND_OUTPUT_VID_FORMAT_EN_DOWNSAMPLE_SHIFT 4 +#define XAVBUF_V_BLEND_OUTPUT_VID_FORMAT_EN_DOWNSAMPLE_WIDTH 1 +#define XAVBUF_V_BLEND_OUTPUT_VID_FORMAT_EN_DOWNSAMPLE_MASK 0X00000010 + +#define XAVBUF_V_BLEND_OUTPUT_VID_FORMAT_VID_FORMAT_SHIFT 0 +#define XAVBUF_V_BLEND_OUTPUT_VID_FORMAT_VID_FORMAT_WIDTH 3 +#define XAVBUF_V_BLEND_OUTPUT_VID_FORMAT_VID_FORMAT_MASK 0X00000007 + +/** + * * Register: XAVBUF_V_BLEND_LAYER0_CONTROL + * */ +#define XAVBUF_V_BLEND_LAYER0_CONTROL 0X0000A018 + +#define XAVBUF_V_BLEND_LAYER0_CONTROL_BYPASS_SHIFT 8 +#define XAVBUF_V_BLEND_LAYER0_CONTROL_BYPASS_WIDTH 1 +#define XAVBUF_V_BLEND_LAYER0_CONTROL_BYPASS_MASK 0X00000100 + +#define XAVBUF_V_BLEND_LAYER0_CONTROL_RGB_MODE_SHIFT 1 +#define XAVBUF_V_BLEND_LAYER0_CONTROL_RGB_MODE_WIDTH 1 +#define XAVBUF_V_BLEND_LAYER0_CONTROL_RGB_MODE_MASK 0X00000002 + +#define XAVBUF_V_BLEND_LAYER0_CONTROL_EN_US_SHIFT 0 +#define XAVBUF_V_BLEND_LAYER0_CONTROL_EN_US_WIDTH 1 +#define XAVBUF_V_BLEND_LAYER0_CONTROL_EN_US_MASK 0X00000001 + +/** + * * Register: XAVBUF_V_BLEND_LAYER1_CONTROL + * */ +#define XAVBUF_V_BLEND_LAYER1_CONTROL 0X0000A01C + +#define XAVBUF_V_BLEND_LAYER1_CONTROL_BYPASS_SHIFT 8 +#define XAVBUF_V_BLEND_LAYER1_CONTROL_BYPASS_WIDTH 1 +#define XAVBUF_V_BLEND_LAYER1_CONTROL_BYPASS_MASK 0X00000100 + +#define XAVBUF_V_BLEND_LAYER1_CONTROL_RGB_MODE_SHIFT 1 +#define XAVBUF_V_BLEND_LAYER1_CONTROL_RGB_MODE_WIDTH 1 +#define XAVBUF_V_BLEND_LAYER1_CONTROL_RGB_MODE_MASK 0X00000002 + +#define XAVBUF_V_BLEND_LAYER1_CONTROL_EN_US_SHIFT 0 +#define XAVBUF_V_BLEND_LAYER1_CONTROL_EN_US_WIDTH 1 +#define XAVBUF_V_BLEND_LAYER1_CONTROL_EN_US_MASK 0X00000001 + +/** + * * Register: XAVBUF_V_BLEND_RGB2YCBCR_COEFF0 + * */ +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF0 0X0000A020 + +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF0_RGB2Y_C0_SHIFT 0 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF0_RGB2Y_C0_WIDTH 15 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF0_RGB2Y_C0_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_RGB2YCBCR_COEFF1 + * */ +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF1 0X0000A024 + +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF1_RGB2Y_C1_SHIFT 0 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF1_RGB2Y_C1_WIDTH 15 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF1_RGB2Y_C1_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_RGB2YCBCR_COEFF2 + * */ +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF2 0X0000A028 + +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF2_RGB2Y_C2_SHIFT 0 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF2_RGB2Y_C2_WIDTH 15 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF2_RGB2Y_C2_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_RGB2YCBCR_COEFF3 + * */ +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF3 0X0000A02C + +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF3_RGB2Y_C3_SHIFT 0 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF3_RGB2Y_C3_WIDTH 15 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF3_RGB2Y_C3_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_RGB2YCBCR_COEFF4 + * */ +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF4 0X0000A030 + +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF4_RGB2Y_C4_SHIFT 0 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF4_RGB2Y_C4_WIDTH 15 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF4_RGB2Y_C4_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_RGB2YCBCR_COEFF5 + * */ +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF5 0X0000A034 + +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF5_RGB2Y_C5_SHIFT 0 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF5_RGB2Y_C5_WIDTH 15 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF5_RGB2Y_C5_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_RGB2YCBCR_COEFF6 + * */ +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF6 0X0000A038 + +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF6_RGB2Y_C6_SHIFT 0 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF6_RGB2Y_C6_WIDTH 15 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF6_RGB2Y_C6_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_RGB2YCBCR_COEFF7 + * */ +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF7 0X0000A03C + +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF7_RGB2Y_C7_SHIFT 0 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF7_RGB2Y_C7_WIDTH 15 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF7_RGB2Y_C7_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_RGB2YCBCR_COEFF8 + * */ +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF8 0X0000A040 + +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF8_RGB2Y_C8_SHIFT 0 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF8_RGB2Y_C8_WIDTH 15 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF8_RGB2Y_C8_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN1CSC_COEFF0 + * */ +#define XAVBUF_V_BLEND_IN1CSC_COEFF0 0X0000A044 + +#define XAVBUF_V_BLEND_IN1CSC_COEFF0_Y2R_C0_SHIFT 0 +#define XAVBUF_V_BLEND_IN1CSC_COEFF0_Y2R_C0_WIDTH 15 +#define XAVBUF_V_BLEND_IN1CSC_COEFF0_Y2R_C0_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN1CSC_COEFF1 + * */ +#define XAVBUF_V_BLEND_IN1CSC_COEFF1 0X0000A048 + +#define XAVBUF_V_BLEND_IN1CSC_COEFF1_Y2R_C1_SHIFT 0 +#define XAVBUF_V_BLEND_IN1CSC_COEFF1_Y2R_C1_WIDTH 15 +#define XAVBUF_V_BLEND_IN1CSC_COEFF1_Y2R_C1_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN1CSC_COEFF2 + * */ +#define XAVBUF_V_BLEND_IN1CSC_COEFF2 0X0000A04C + +#define XAVBUF_V_BLEND_IN1CSC_COEFF2_Y2R_C2_SHIFT 0 +#define XAVBUF_V_BLEND_IN1CSC_COEFF2_Y2R_C2_WIDTH 15 +#define XAVBUF_V_BLEND_IN1CSC_COEFF2_Y2R_C2_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN1CSC_COEFF3 + * */ +#define XAVBUF_V_BLEND_IN1CSC_COEFF3 0X0000A050 + +#define XAVBUF_V_BLEND_IN1CSC_COEFF3_Y2R_C3_SHIFT 0 +#define XAVBUF_V_BLEND_IN1CSC_COEFF3_Y2R_C3_WIDTH 15 +#define XAVBUF_V_BLEND_IN1CSC_COEFF3_Y2R_C3_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN1CSC_COEFF4 + * */ +#define XAVBUF_V_BLEND_IN1CSC_COEFF4 0X0000A054 + +#define XAVBUF_V_BLEND_IN1CSC_COEFF4_Y2R_C4_SHIFT 0 +#define XAVBUF_V_BLEND_IN1CSC_COEFF4_Y2R_C4_WIDTH 15 +#define XAVBUF_V_BLEND_IN1CSC_COEFF4_Y2R_C4_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN1CSC_COEFF5 + * */ +#define XAVBUF_V_BLEND_IN1CSC_COEFF5 0X0000A058 + +#define XAVBUF_V_BLEND_IN1CSC_COEFF5_Y2R_C5_SHIFT 0 +#define XAVBUF_V_BLEND_IN1CSC_COEFF5_Y2R_C5_WIDTH 15 +#define XAVBUF_V_BLEND_IN1CSC_COEFF5_Y2R_C5_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN1CSC_COEFF6 + * */ +#define XAVBUF_V_BLEND_IN1CSC_COEFF6 0X0000A05C + +#define XAVBUF_V_BLEND_IN1CSC_COEFF6_Y2R_C6_SHIFT 0 +#define XAVBUF_V_BLEND_IN1CSC_COEFF6_Y2R_C6_WIDTH 15 +#define XAVBUF_V_BLEND_IN1CSC_COEFF6_Y2R_C6_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN1CSC_COEFF7 + * */ +#define XAVBUF_V_BLEND_IN1CSC_COEFF7 0X0000A060 + +#define XAVBUF_V_BLEND_IN1CSC_COEFF7_Y2R_C7_SHIFT 0 +#define XAVBUF_V_BLEND_IN1CSC_COEFF7_Y2R_C7_WIDTH 15 +#define XAVBUF_V_BLEND_IN1CSC_COEFF7_Y2R_C7_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN1CSC_COEFF8 + * */ +#define XAVBUF_V_BLEND_IN1CSC_COEFF8 0X0000A064 + +#define XAVBUF_V_BLEND_IN1CSC_COEFF8_Y2R_C8_SHIFT 0 +#define XAVBUF_V_BLEND_IN1CSC_COEFF8_Y2R_C8_WIDTH 15 +#define XAVBUF_V_BLEND_IN1CSC_COEFF8_Y2R_C8_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_LUMA_IN1CSC_OFFSET + * */ +#define XAVBUF_V_BLEND_LUMA_IN1CSC_OFFSET 0X0000A068 + +#define XAVBUF_V_BLEND_LUMA_IN1CSC_OFFSET_POST_OFFSET_SHIFT 16 +#define XAVBUF_V_BLEND_LUMA_IN1CSC_OFFSET_POST_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_LUMA_IN1CSC_OFFSET_POST_OFFSET_MASK 0X1FFF0000 + +#define XAVBUF_V_BLEND_LUMA_IN1CSC_OFFSET_PRE_OFFSET_SHIFT 0 +#define XAVBUF_V_BLEND_LUMA_IN1CSC_OFFSET_PRE_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_LUMA_IN1CSC_OFFSET_PRE_OFFSET_MASK 0X00001FFF + +/** + * * Register: XAVBUF_V_BLEND_CR_IN1CSC_OFFSET + * */ +#define XAVBUF_V_BLEND_CR_IN1CSC_OFFSET 0X0000A06C + +#define XAVBUF_V_BLEND_CR_IN1CSC_OFFSET_POST_OFFSET_SHIFT 16 +#define XAVBUF_V_BLEND_CR_IN1CSC_OFFSET_POST_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_CR_IN1CSC_OFFSET_POST_OFFSET_MASK 0X1FFF0000 + +#define XAVBUF_V_BLEND_CR_IN1CSC_OFFSET_PRE_OFFSET_SHIFT 0 +#define XAVBUF_V_BLEND_CR_IN1CSC_OFFSET_PRE_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_CR_IN1CSC_OFFSET_PRE_OFFSET_MASK 0X00001FFF + +/** + * * Register: XAVBUF_V_BLEND_CB_IN1CSC_OFFSET + * */ +#define XAVBUF_V_BLEND_CB_IN1CSC_OFFSET 0X0000A070 + +#define XAVBUF_V_BLEND_CB_IN1CSC_OFFSET_POST_OFFSET_SHIFT 16 +#define XAVBUF_V_BLEND_CB_IN1CSC_OFFSET_POST_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_CB_IN1CSC_OFFSET_POST_OFFSET_MASK 0X1FFF0000 + +#define XAVBUF_V_BLEND_CB_IN1CSC_OFFSET_PRE_OFFSET_SHIFT 0 +#define XAVBUF_V_BLEND_CB_IN1CSC_OFFSET_PRE_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_CB_IN1CSC_OFFSET_PRE_OFFSET_MASK 0X00001FFF + +/** + * * Register: XAVBUF_V_BLEND_LUMA_OUTCSC_OFFSET + * */ +#define XAVBUF_V_BLEND_LUMA_OUTCSC_OFFSET 0X0000A074 + +#define XAVBUF_V_BLEND_LUMA_OUTCSC_OFFSET_POST_OFFSET_SHIFT 16 +#define XAVBUF_V_BLEND_LUMA_OUTCSC_OFFSET_POST_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_LUMA_OUTCSC_OFFSET_POST_OFFSET_MASK 0X1FFF0000 + +#define XAVBUF_V_BLEND_LUMA_OUTCSC_OFFSET_PRE_OFFSET_SHIFT 0 +#define XAVBUF_V_BLEND_LUMA_OUTCSC_OFFSET_PRE_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_LUMA_OUTCSC_OFFSET_PRE_OFFSET_MASK 0X00001FFF + +/** + * * Register: XAVBUF_V_BLEND_CR_OUTCSC_OFFSET + * */ +#define XAVBUF_V_BLEND_CR_OUTCSC_OFFSET 0X0000A078 + +#define XAVBUF_V_BLEND_CR_OUTCSC_OFFSET_POST_OFFSET_SHIFT 16 +#define XAVBUF_V_BLEND_CR_OUTCSC_OFFSET_POST_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_CR_OUTCSC_OFFSET_POST_OFFSET_MASK 0X1FFF0000 + +#define XAVBUF_V_BLEND_CR_OUTCSC_OFFSET_PRE_OFFSET_SHIFT 0 +#define XAVBUF_V_BLEND_CR_OUTCSC_OFFSET_PRE_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_CR_OUTCSC_OFFSET_PRE_OFFSET_MASK 0X00001FFF + +/** + * * Register: XAVBUF_V_BLEND_CB_OUTCSC_OFFSET + * */ +#define XAVBUF_V_BLEND_CB_OUTCSC_OFFSET 0X0000A07C + +#define XAVBUF_V_BLEND_CB_OUTCSC_OFFSET_POST_OFFSET_SHIFT 16 +#define XAVBUF_V_BLEND_CB_OUTCSC_OFFSET_POST_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_CB_OUTCSC_OFFSET_POST_OFFSET_MASK 0X1FFF0000 + +#define XAVBUF_V_BLEND_CB_OUTCSC_OFFSET_PRE_OFFSET_SHIFT 0 +#define XAVBUF_V_BLEND_CB_OUTCSC_OFFSET_PRE_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_CB_OUTCSC_OFFSET_PRE_OFFSET_MASK 0X00001FFF + +/** + * * Register: XAVBUF_V_BLEND_IN2CSC_COEFF0 + * */ +#define XAVBUF_V_BLEND_IN2CSC_COEFF0 0X0000A080 + +#define XAVBUF_V_BLEND_IN2CSC_COEFF0_Y2R_C0_SHIFT 0 +#define XAVBUF_V_BLEND_IN2CSC_COEFF0_Y2R_C0_WIDTH 15 +#define XAVBUF_V_BLEND_IN2CSC_COEFF0_Y2R_C0_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN2CSC_COEFF1 + * */ +#define XAVBUF_V_BLEND_IN2CSC_COEFF1 0X0000A084 + +#define XAVBUF_V_BLEND_IN2CSC_COEFF1_Y2R_C1_SHIFT 0 +#define XAVBUF_V_BLEND_IN2CSC_COEFF1_Y2R_C1_WIDTH 15 +#define XAVBUF_V_BLEND_IN2CSC_COEFF1_Y2R_C1_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN2CSC_COEFF2 + * */ +#define XAVBUF_V_BLEND_IN2CSC_COEFF2 0X0000A088 + +#define XAVBUF_V_BLEND_IN2CSC_COEFF2_Y2R_C2_SHIFT 0 +#define XAVBUF_V_BLEND_IN2CSC_COEFF2_Y2R_C2_WIDTH 15 +#define XAVBUF_V_BLEND_IN2CSC_COEFF2_Y2R_C2_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN2CSC_COEFF3 + * */ +#define XAVBUF_V_BLEND_IN2CSC_COEFF3 0X0000A08C + +#define XAVBUF_V_BLEND_IN2CSC_COEFF3_Y2R_C3_SHIFT 0 +#define XAVBUF_V_BLEND_IN2CSC_COEFF3_Y2R_C3_WIDTH 15 +#define XAVBUF_V_BLEND_IN2CSC_COEFF3_Y2R_C3_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN2CSC_COEFF4 + * */ +#define XAVBUF_V_BLEND_IN2CSC_COEFF4 0X0000A090 + +#define XAVBUF_V_BLEND_IN2CSC_COEFF4_Y2R_C4_SHIFT 0 +#define XAVBUF_V_BLEND_IN2CSC_COEFF4_Y2R_C4_WIDTH 15 +#define XAVBUF_V_BLEND_IN2CSC_COEFF4_Y2R_C4_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN2CSC_COEFF5 + * */ +#define XAVBUF_V_BLEND_IN2CSC_COEFF5 0X0000A094 + +#define XAVBUF_V_BLEND_IN2CSC_COEFF5_Y2R_C5_SHIFT 0 +#define XAVBUF_V_BLEND_IN2CSC_COEFF5_Y2R_C5_WIDTH 15 +#define XAVBUF_V_BLEND_IN2CSC_COEFF5_Y2R_C5_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN2CSC_COEFF6 + * */ +#define XAVBUF_V_BLEND_IN2CSC_COEFF6 0X0000A098 + +#define XAVBUF_V_BLEND_IN2CSC_COEFF6_Y2R_C6_SHIFT 0 +#define XAVBUF_V_BLEND_IN2CSC_COEFF6_Y2R_C6_WIDTH 15 +#define XAVBUF_V_BLEND_IN2CSC_COEFF6_Y2R_C6_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN2CSC_COEFF7 + * */ +#define XAVBUF_V_BLEND_IN2CSC_COEFF7 0X0000A09C + +#define XAVBUF_V_BLEND_IN2CSC_COEFF7_Y2R_C7_SHIFT 0 +#define XAVBUF_V_BLEND_IN2CSC_COEFF7_Y2R_C7_WIDTH 15 +#define XAVBUF_V_BLEND_IN2CSC_COEFF7_Y2R_C7_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN2CSC_COEFF8 + * */ +#define XAVBUF_V_BLEND_IN2CSC_COEFF8 0X0000A0A0 + +#define XAVBUF_V_BLEND_IN2CSC_COEFF8_Y2R_C8_SHIFT 0 +#define XAVBUF_V_BLEND_IN2CSC_COEFF8_Y2R_C8_WIDTH 15 +#define XAVBUF_V_BLEND_IN2CSC_COEFF8_Y2R_C8_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_LUMA_IN2CSC_OFFSET + * */ +#define XAVBUF_V_BLEND_LUMA_IN2CSC_OFFSET 0X0000A0A4 + +#define XAVBUF_V_BLEND_LUMA_IN2CSC_OFFSET_POST_OFFSET_SHIFT 16 +#define XAVBUF_V_BLEND_LUMA_IN2CSC_OFFSET_POST_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_LUMA_IN2CSC_OFFSET_POST_OFFSET_MASK 0X1FFF0000 + +#define XAVBUF_V_BLEND_LUMA_IN2CSC_OFFSET_PRE_OFFSET_SHIFT 0 +#define XAVBUF_V_BLEND_LUMA_IN2CSC_OFFSET_PRE_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_LUMA_IN2CSC_OFFSET_PRE_OFFSET_MASK 0X00001FFF + +/** + * * Register: XAVBUF_V_BLEND_CR_IN2CSC_OFFSET + * */ +#define XAVBUF_V_BLEND_CR_IN2CSC_OFFSET 0X0000A0A8 + +#define XAVBUF_V_BLEND_CR_IN2CSC_OFFSET_POST_OFFSET_SHIFT 16 +#define XAVBUF_V_BLEND_CR_IN2CSC_OFFSET_POST_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_CR_IN2CSC_OFFSET_POST_OFFSET_MASK 0X1FFF0000 + +#define XAVBUF_V_BLEND_CR_IN2CSC_OFFSET_PRE_OFFSET_SHIFT 0 +#define XAVBUF_V_BLEND_CR_IN2CSC_OFFSET_PRE_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_CR_IN2CSC_OFFSET_PRE_OFFSET_MASK 0X00001FFF + +/** + * * Register: XAVBUF_V_BLEND_CB_IN2CSC_OFFSET + * */ +#define XAVBUF_V_BLEND_CB_IN2CSC_OFFSET 0X0000A0AC + +#define XAVBUF_V_BLEND_CB_IN2CSC_OFFSET_POST_OFFSET_SHIFT 16 +#define XAVBUF_V_BLEND_CB_IN2CSC_OFFSET_POST_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_CB_IN2CSC_OFFSET_POST_OFFSET_MASK 0X1FFF0000 + +#define XAVBUF_V_BLEND_CB_IN2CSC_OFFSET_PRE_OFFSET_SHIFT 0 +#define XAVBUF_V_BLEND_CB_IN2CSC_OFFSET_PRE_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_CB_IN2CSC_OFFSET_PRE_OFFSET_MASK 0X00001FFF + +/** + * * Register: XAVBUF_V_BLEND_CHROMA_KEY_ENABLE + * */ +#define XAVBUF_V_BLEND_CHROMA_KEY_ENABLE 0X0000A1D0 + +#define XAVBUF_V_BLEND_CHROMA_KEY_ENABLE_M_SEL_SHIFT 1 +#define XAVBUF_V_BLEND_CHROMA_KEY_ENABLE_M_SEL_WIDTH 1 +#define XAVBUF_V_BLEND_CHROMA_KEY_ENABLE_M_SEL_MASK 0X00000002 + +#define XAVBUF_V_BLEND_CHROMA_KEY_ENABLE_EN_SHIFT 0 +#define XAVBUF_V_BLEND_CHROMA_KEY_ENABLE_EN_WIDTH 1 +#define XAVBUF_V_BLEND_CHROMA_KEY_ENABLE_EN_MASK 0X00000001 + +/** + * * Register: XAVBUF_V_BLEND_CHROMA_KEY_COMP1 + * */ +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP1 0X0000A1D4 + +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP1_MAX_SHIFT 16 +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP1_MAX_WIDTH 12 +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP1_MAX_MASK 0X0FFF0000 + +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP1_MIN_SHIFT 0 +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP1_MIN_WIDTH 12 +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP1_MIN_MASK 0X00000FFF + +/** + * * Register: XAVBUF_V_BLEND_CHROMA_KEY_COMP2 + * */ +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP2 0X0000A1D8 + +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP2_MAX_SHIFT 16 +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP2_MAX_WIDTH 12 +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP2_MAX_MASK 0X0FFF0000 + +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP2_MIN_SHIFT 0 +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP2_MIN_WIDTH 12 +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP2_MIN_MASK 0X00000FFF + +/** + * * Register: XAVBUF_V_BLEND_CHROMA_KEY_COMP3 + * */ +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP3 0X0000A1DC + +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP3_MAX_SHIFT 16 +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP3_MAX_WIDTH 12 +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP3_MAX_MASK 0X0FFF0000 + +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP3_MIN_SHIFT 0 +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP3_MIN_WIDTH 12 +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP3_MIN_MASK 0X00000FFF + +/** + * * Register: XAVBUF_BUF_FORMAT + * */ +#define XAVBUF_BUF_FORMAT 0X0000B000 + +#define XAVBUF_BUF_FORMAT_NL_GRAPHX_FORMAT_SHIFT 8 +#define XAVBUF_BUF_FORMAT_NL_GRAPHX_FORMAT_WIDTH 4 +#define XAVBUF_BUF_FORMAT_NL_GRAPHX_FORMAT_MASK 0X00000F00 + +#define XAVBUF_BUF_FORMAT_NL_VID_FORMAT_SHIFT 0 +#define XAVBUF_BUF_FORMAT_NL_VID_FORMAT_WIDTH 5 +#define XAVBUF_BUF_FORMAT_NL_VID_FORMAT_MASK 0X0000001F + +/** + * * Register: XAVBUF_BUF_NON_LIVE_LATENCY + * */ +#define XAVBUF_BUF_NON_LIVE_LATENCY 0X0000B008 + +#define XAVBUF_BUF_NON_LIVE_LATENCY_NL_LATENCY_SHIFT 0 +#define XAVBUF_BUF_NON_LIVE_LATENCY_NL_LATENCY_WIDTH 10 +#define XAVBUF_BUF_NON_LIVE_LATENCY_NL_LATENCY_MASK 0X000003FF + +/** + * * Register: XAVBUF_CHBUF0 + * */ +#define XAVBUF_CHBUF0 0X0000B010 + +#define XAVBUF_CHBUF0_BURST_LEN_SHIFT 2 +#define XAVBUF_CHBUF0_BURST_LEN_WIDTH 5 +#define XAVBUF_CHBUF0_BURST_LEN_MASK 0X0000007C + +#define XAVBUF_CHBUF0_FLUSH_SHIFT 1 +#define XAVBUF_CHBUF0_FLUSH_WIDTH 1 +#define XAVBUF_CHBUF0_FLUSH_MASK 0X00000002 + +#define XAVBUF_CHBUF0_EN_SHIFT 0 +#define XAVBUF_CHBUF0_EN_WIDTH 1 +#define XAVBUF_CHBUF0_EN_MASK 0X00000001 + +/** + * * Register: XAVBUF_CHBUF1 + * */ +#define XAVBUF_CHBUF1 0X0000B014 + +#define XAVBUF_CHBUF1_BURST_LEN_SHIFT 2 +#define XAVBUF_CHBUF1_BURST_LEN_WIDTH 5 +#define XAVBUF_CHBUF1_BURST_LEN_MASK 0X0000007C + +#define XAVBUF_CHBUF1_FLUSH_SHIFT 1 +#define XAVBUF_CHBUF1_FLUSH_WIDTH 1 +#define XAVBUF_CHBUF1_FLUSH_MASK 0X00000002 + +#define XAVBUF_CHBUF1_EN_SHIFT 0 +#define XAVBUF_CHBUF1_EN_WIDTH 1 +#define XAVBUF_CHBUF1_EN_MASK 0X00000001 + +/** + * * Register: XAVBUF_CHBUF2 + * */ +#define XAVBUF_CHBUF2 0X0000B018 + +#define XAVBUF_CHBUF2_BURST_LEN_SHIFT 2 +#define XAVBUF_CHBUF2_BURST_LEN_WIDTH 5 +#define XAVBUF_CHBUF2_BURST_LEN_MASK 0X0000007C + +#define XAVBUF_CHBUF2_FLUSH_SHIFT 1 +#define XAVBUF_CHBUF2_FLUSH_WIDTH 1 +#define XAVBUF_CHBUF2_FLUSH_MASK 0X00000002 + +#define XAVBUF_CHBUF2_EN_SHIFT 0 +#define XAVBUF_CHBUF2_EN_WIDTH 1 +#define XAVBUF_CHBUF2_EN_MASK 0X00000001 + +/** + * * Register: XAVBUF_CHBUF3 + * */ +#define XAVBUF_CHBUF3 0X0000B01C + +#define XAVBUF_CHBUF3_BURST_LEN_SHIFT 2 +#define XAVBUF_CHBUF3_BURST_LEN_WIDTH 5 +#define XAVBUF_CHBUF3_BURST_LEN_MASK 0X0000007C + +#define XAVBUF_CHBUF3_FLUSH_SHIFT 1 +#define XAVBUF_CHBUF3_FLUSH_WIDTH 1 +#define XAVBUF_CHBUF3_FLUSH_MASK 0X00000002 + +#define XAVBUF_CHBUF3_EN_SHIFT 0 +#define XAVBUF_CHBUF3_EN_WIDTH 1 +#define XAVBUF_CHBUF3_EN_MASK 0X00000001 + +/** + * * Register: XAVBUF_CHBUF4 + * */ +#define XAVBUF_CHBUF4 0X0000B020 + +#define XAVBUF_CHBUF4_BURST_LEN_SHIFT 2 +#define XAVBUF_CHBUF4_BURST_LEN_WIDTH 5 +#define XAVBUF_CHBUF4_BURST_LEN_MASK 0X0000007C + +#define XAVBUF_CHBUF4_FLUSH_SHIFT 1 +#define XAVBUF_CHBUF4_FLUSH_WIDTH 1 +#define XAVBUF_CHBUF4_FLUSH_MASK 0X00000002 + +#define XAVBUF_CHBUF4_EN_SHIFT 0 +#define XAVBUF_CHBUF4_EN_WIDTH 1 +#define XAVBUF_CHBUF4_EN_MASK 0X00000001 + +/** + * * Register: XAVBUF_CHBUF5 + * */ +#define XAVBUF_CHBUF5 0X0000B024 + +#define XAVBUF_CHBUF5_BURST_LEN_SHIFT 2 +#define XAVBUF_CHBUF5_BURST_LEN_WIDTH 5 +#define XAVBUF_CHBUF5_BURST_LEN_MASK 0X0000007C + +#define XAVBUF_CHBUF5_FLUSH_SHIFT 1 +#define XAVBUF_CHBUF5_FLUSH_WIDTH 1 +#define XAVBUF_CHBUF5_FLUSH_MASK 0X00000002 + +#define XAVBUF_CHBUF5_EN_SHIFT 0 +#define XAVBUF_CHBUF5_EN_WIDTH 1 +#define XAVBUF_CHBUF5_EN_MASK 0X00000001 + +/** + * * Register: XAVBUF_BUF_STC_CONTROL + * */ +#define XAVBUF_BUF_STC_CONTROL 0X0000B02C + +#define XAVBUF_BUF_STC_CONTROL_EN_SHIFT 0 +#define XAVBUF_BUF_STC_CONTROL_EN_WIDTH 1 +#define XAVBUF_BUF_STC_CONTROL_EN_MASK 0X00000001 + +/** + * * Register: XAVBUF_BUF_STC_INIT_VALUE0 + * */ +#define XAVBUF_BUF_STC_INIT_VALUE0 0X0000B030 + +#define XAVBUF_BUF_STC_INIT_VALUE0_INIT_VALUE0_SHIFT 0 +#define XAVBUF_BUF_STC_INIT_VALUE0_INIT_VALUE0_WIDTH 32 +#define XAVBUF_BUF_STC_INIT_VALUE0_INIT_VALUE0_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_BUF_STC_INIT_VALUE1 + * */ +#define XAVBUF_BUF_STC_INIT_VALUE1 0X0000B034 + +#define XAVBUF_BUF_STC_INIT_VALUE1_INIT_VALUE1_SHIFT 0 +#define XAVBUF_BUF_STC_INIT_VALUE1_INIT_VALUE1_WIDTH 10 +#define XAVBUF_BUF_STC_INIT_VALUE1_INIT_VALUE1_MASK 0X000003FF + +/** + * * Register: XAVBUF_BUF_STC_ADJ + * */ +#define XAVBUF_BUF_STC_ADJ 0X0000B038 + +#define XAVBUF_BUF_STC_ADJ_SIGN_SHIFT 31 +#define XAVBUF_BUF_STC_ADJ_SIGN_WIDTH 1 +#define XAVBUF_BUF_STC_ADJ_SIGN_MASK 0X80000000 + +#define XAVBUF_BUF_STC_ADJ_VALUE_SHIFT 0 +#define XAVBUF_BUF_STC_ADJ_VALUE_WIDTH 31 +#define XAVBUF_BUF_STC_ADJ_VALUE_MASK 0X7FFFFFFF + +/** + * * Register: XAVBUF_BUF_STC_VID_VSYNC_TS_REG0 + * */ +#define XAVBUF_BUF_STC_VID_VSYNC_TS_REG0 0X0000B03C + +#define XAVBUF_BUF_STC_VID_VSYNC_TS_REG0_VSYNC_TS0_SHIFT 0 +#define XAVBUF_BUF_STC_VID_VSYNC_TS_REG0_VSYNC_TS0_WIDTH 32 +#define XAVBUF_BUF_STC_VID_VSYNC_TS_REG0_VSYNC_TS0_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_BUF_STC_VID_VSYNC_TS_REG1 + * */ +#define XAVBUF_BUF_STC_VID_VSYNC_TS_REG1 0X0000B040 + +#define XAVBUF_BUF_STC_VID_VSYNC_TS_REG1_VSYNC_TS1_SHIFT 0 +#define XAVBUF_BUF_STC_VID_VSYNC_TS_REG1_VSYNC_TS1_WIDTH 10 +#define XAVBUF_BUF_STC_VID_VSYNC_TS_REG1_VSYNC_TS1_MASK 0X000003FF + +/** + * * Register: XAVBUF_BUF_STC_EXT_VSYNC_TS_REG0 + * */ +#define XAVBUF_BUF_STC_EXT_VSYNC_TS_REG0 0X0000B044 + +#define XAVBUF_BUF_STC_EXT_VSYNC_TS_REG0_EXT_VSYNC_TS0_SHIFT 0 +#define XAVBUF_BUF_STC_EXT_VSYNC_TS_REG0_EXT_VSYNC_TS0_WIDTH 32 +#define XAVBUF_BUF_STC_EXT_VSYNC_TS_REG0_EXT_VSYNC_TS0_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_BUF_STC_EXT_VSYNC_TS_REG1 + * */ +#define XAVBUF_BUF_STC_EXT_VSYNC_TS_REG1 0X0000B048 + +#define XAVBUF_BUF_STC_EXT_VSYNC_TS_REG1_EXT_VSYNC_TS1_SHIFT 0 +#define XAVBUF_BUF_STC_EXT_VSYNC_TS_REG1_EXT_VSYNC_TS1_WIDTH 10 +#define XAVBUF_BUF_STC_EXT_VSYNC_TS_REG1_EXT_VSYNC_TS1_MASK 0X000003FF + +/** + * * Register: XAVBUF_BUF_STC_CUSTOM_EVENT_TS_REG0 + * */ +#define XAVBUF_BUF_STC_CUSTOM_EVENT_TS_REG0 0X0000B04C + +#define XAVBUF_BUF_STC_CUSTOM_EVENT_TS_REG0_CUST_EVENT_TS0_SHIFT 0 +#define XAVBUF_BUF_STC_CUSTOM_EVENT_TS_REG0_CUST_EVENT_TS0_WIDTH 32 +#define XAVBUF_BUF_STC_CUSTOM_EVENT_TS_REG0_CUST_EVENT_TS0_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_BUF_STC_CUSTOM_EVENT_TS_REG1 + * */ +#define XAVBUF_BUF_STC_CUSTOM_EVENT_TS_REG1 0X0000B050 + +#define XAVBUF_BUF_STC_CUSTOM_EVENT_TS_REG1_CUST_EVENT_TS1_SHIFT 0 +#define XAVBUF_BUF_STC_CUSTOM_EVENT_TS_REG1_CUST_EVENT_TS1_WIDTH 10 +#define XAVBUF_BUF_STC_CUSTOM_EVENT_TS_REG1_CUST_EVENT_TS1_MASK 0X000003FF + +/** + * * Register: XAVBUF_BUF_STC_CUSTOM_EVENT2_TS_REG0 + * */ +#define XAVBUF_BUF_STC_CUSTOM_EVENT2_TS_REG0 0X0000B054 + +#define XAVBUF_BUF_STC_CUSTOM_EVENT2_TS_REG0_CUST_EVENT2_TS0_SHIFT 0 +#define XAVBUF_BUF_STC_CUSTOM_EVENT2_TS_REG0_CUST_EVENT2_TS0_WIDTH 32 +#define XAVBUF_BUF_STC_CUSTOM_EVENT2_TS_REG0_CUST_EVENT2_TS0_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_BUF_STC_CUSTOM_EVENT2_TS_REG1 + * */ +#define XAVBUF_BUF_STC_CUSTOM_EVENT2_TS_REG1 0X0000B058 + +#define XAVBUF_BUF_STC_CUSTOM_EVENT2_TS_REG1_CUST_EVENT2_TS1_SHIFT 0 +#define XAVBUF_BUF_STC_CUSTOM_EVENT2_TS_REG1_CUST_EVENT2_TS1_WIDTH 10 +#define XAVBUF_BUF_STC_CUSTOM_EVENT2_TS_REG1_CUST_EVENT2_TS1_MASK 0X000003FF + +/** + * * Register: XAVBUF_BUF_STC_SNAPSHOT0 + * */ +#define XAVBUF_BUF_STC_SNAPSHOT0 0X0000B060 + +#define XAVBUF_BUF_STC_SNAPSHOT0_STC0_SHIFT 0 +#define XAVBUF_BUF_STC_SNAPSHOT0_STC0_WIDTH 32 +#define XAVBUF_BUF_STC_SNAPSHOT0_STC0_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_BUF_STC_SNAPSHOT1 + * */ +#define XAVBUF_BUF_STC_SNAPSHOT1 0X0000B064 + +#define XAVBUF_BUF_STC_SNAPSHOT1_STC1_SHIFT 0 +#define XAVBUF_BUF_STC_SNAPSHOT1_STC1_WIDTH 10 +#define XAVBUF_BUF_STC_SNAPSHOT1_STC1_MASK 0X000003FF + +/** + * * Register: XAVBUF_BUF_OUTPUT_AUD_VID_SELECT + * */ +#define XAVBUF_BUF_OUTPUT_AUD_VID_SELECT 0X0000B070 + +#define XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_AUD_STREAM2_SEL_SHIFT 6 +#define XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_AUD_STREAM2_SEL_WIDTH 1 +#define XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_AUD_STREAM2_SEL_MASK 0X00000040 + +#define XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_AUD_STREAM1_SEL_SHIFT 4 +#define XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_AUD_STREAM1_SEL_WIDTH 2 +#define XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_AUD_STREAM1_SEL_MASK 0X00000030 + +#define XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_VID_STREAM2_SEL_SHIFT 2 +#define XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_VID_STREAM2_SEL_WIDTH 2 +#define XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_VID_STREAM2_SEL_MASK 0X0000000C + +#define XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_VID_STREAM1_SEL_SHIFT 0 +#define XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_VID_STREAM1_SEL_WIDTH 2 +#define XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_VID_STREAM1_SEL_MASK 0X00000003 + +/** + * * Register: XAVBUF_BUF_HCOUNT_VCOUNT_INT0 + * */ +#define XAVBUF_BUF_HCOUNT_VCOUNT_INT0 0X0000B074 + +#define XAVBUF_BUF_HCOUNT_VCOUNT_INT0_HCOUNT_SHIFT 16 +#define XAVBUF_BUF_HCOUNT_VCOUNT_INT0_HCOUNT_WIDTH 14 +#define XAVBUF_BUF_HCOUNT_VCOUNT_INT0_HCOUNT_MASK 0X3FFF0000 + +#define XAVBUF_BUF_HCOUNT_VCOUNT_INT0_VCOUNT_SHIFT 0 +#define XAVBUF_BUF_HCOUNT_VCOUNT_INT0_VCOUNT_WIDTH 14 +#define XAVBUF_BUF_HCOUNT_VCOUNT_INT0_VCOUNT_MASK 0X00003FFF + +/** + * * Register: XAVBUF_BUF_HCOUNT_VCOUNT_INT1 + * */ +#define XAVBUF_BUF_HCOUNT_VCOUNT_INT1 0X0000B078 + +#define XAVBUF_BUF_HCOUNT_VCOUNT_INT1_HCOUNT_SHIFT 16 +#define XAVBUF_BUF_HCOUNT_VCOUNT_INT1_HCOUNT_WIDTH 14 +#define XAVBUF_BUF_HCOUNT_VCOUNT_INT1_HCOUNT_MASK 0X3FFF0000 + +#define XAVBUF_BUF_HCOUNT_VCOUNT_INT1_VCOUNT_SHIFT 0 +#define XAVBUF_BUF_HCOUNT_VCOUNT_INT1_VCOUNT_WIDTH 14 +#define XAVBUF_BUF_HCOUNT_VCOUNT_INT1_VCOUNT_MASK 0X00003FFF + +/** + * * Register: XAVBUF_BUF_DITHER_CFG + * */ +#define XAVBUF_BUF_DITHER_CFG 0X0000B07C + +#define XAVBUF_BUF_DITHER_CFG_TAP_MSB_SHIFT 10 +#define XAVBUF_BUF_DITHER_CFG_TAP_MSB_WIDTH 1 +#define XAVBUF_BUF_DITHER_CFG_TAP_MSB_MASK 0X00000400 + +#define XAVBUF_BUF_DITHER_CFG_DW_SEL_SHIFT 9 +#define XAVBUF_BUF_DITHER_CFG_DW_SEL_WIDTH 1 +#define XAVBUF_BUF_DITHER_CFG_DW_SEL_MASK 0X00000200 + +#define XAVBUF_BUF_DITHER_CFG_LD_SHIFT 8 +#define XAVBUF_BUF_DITHER_CFG_LD_WIDTH 1 +#define XAVBUF_BUF_DITHER_CFG_LD_MASK 0X00000100 + +#define XAVBUF_BUF_DITHER_CFG_TRUNC_PT_SHIFT 5 +#define XAVBUF_BUF_DITHER_CFG_TRUNC_PT_WIDTH 3 +#define XAVBUF_BUF_DITHER_CFG_TRUNC_PT_MASK 0X000000E0 + +#define XAVBUF_BUF_DITHER_CFG_MODE_SHIFT 3 +#define XAVBUF_BUF_DITHER_CFG_MODE_WIDTH 2 +#define XAVBUF_BUF_DITHER_CFG_MODE_MASK 0X00000018 + +#define XAVBUF_BUF_DITHER_CFG_SIZE_SHIFT 0 +#define XAVBUF_BUF_DITHER_CFG_SIZE_WIDTH 3 +#define XAVBUF_BUF_DITHER_CFG_SIZE_MASK 0X00000007 + +/** + * * Register: XAVBUF_DITHER_CFG_SEED0 + * */ +#define XAVBUF_DITHER_CFG_SEED0 0X0000B080 + +#define XAVBUF_DITHER_CFG_SEED0_COLR0_SHIFT 0 +#define XAVBUF_DITHER_CFG_SEED0_COLR0_WIDTH 16 +#define XAVBUF_DITHER_CFG_SEED0_COLR0_MASK 0X0000FFFF + +/** + * * Register: XAVBUF_DITHER_CFG_SEED1 + * */ +#define XAVBUF_DITHER_CFG_SEED1 0X0000B084 + +#define XAVBUF_DITHER_CFG_SEED1_COLR1_SHIFT 0 +#define XAVBUF_DITHER_CFG_SEED1_COLR1_WIDTH 16 +#define XAVBUF_DITHER_CFG_SEED1_COLR1_MASK 0X0000FFFF + +/** + * * Register: XAVBUF_DITHER_CFG_SEED2 + * */ +#define XAVBUF_DITHER_CFG_SEED2 0X0000B088 + +#define XAVBUF_DITHER_CFG_SEED2_COLR2_SHIFT 0 +#define XAVBUF_DITHER_CFG_SEED2_COLR2_WIDTH 16 +#define XAVBUF_DITHER_CFG_SEED2_COLR2_MASK 0X0000FFFF + +/** + * * Register: XAVBUF_DITHER_CFG_MAX + * */ +#define XAVBUF_DITHER_CFG_MAX 0X0000B08C + +#define XAVBUF_DITHER_CFG_MAX_COLR_MAX_SHIFT 0 +#define XAVBUF_DITHER_CFG_MAX_COLR_MAX_WIDTH 12 +#define XAVBUF_DITHER_CFG_MAX_COLR_MAX_MASK 0X00000FFF + +/** + * * Register: XAVBUF_DITHER_CFG_MIN + * */ +#define XAVBUF_DITHER_CFG_MIN 0X0000B090 + +#define XAVBUF_DITHER_CFG_MIN_COLR_MIN_SHIFT 0 +#define XAVBUF_DITHER_CFG_MIN_COLR_MIN_WIDTH 12 +#define XAVBUF_DITHER_CFG_MIN_COLR_MIN_MASK 0X00000FFF + +/** + * * Register: XAVBUF_PATTERN_GEN_SELECT + * */ +#define XAVBUF_PATTERN_GEN_SELECT 0X0000B100 + +#define XAVBUF_PATTERN_GEN_SELECT_OFFSET_EQ_SHIFT 8 +#define XAVBUF_PATTERN_GEN_SELECT_OFFSET_EQ_WIDTH 24 +#define XAVBUF_PATTERN_GEN_SELECT_OFFSET_EQ_MASK 0XFFFFFF00 + +#define XAVBUF_PATTERN_GEN_SELECT_AUD_RATE_SEL_SHIFT 0 +#define XAVBUF_PATTERN_GEN_SELECT_AUD_RATE_SEL_WIDTH 2 +#define XAVBUF_PATTERN_GEN_SELECT_AUD_RATE_SEL_MASK 0X00000003 + +/** + * * Register: XAVBUF_AUD_PATTERN_SELECT1 + * */ +#define XAVBUF_AUD_PATTERN_SELECT1 0X0000B104 + +#define XAVBUF_AUD_PATTERN_SELECT1_PATTERN_SHIFT 0 +#define XAVBUF_AUD_PATTERN_SELECT1_PATTERN_WIDTH 2 +#define XAVBUF_AUD_PATTERN_SELECT1_PATTERN_MASK 0X00000003 + +/** + * * Register: XAVBUF_AUD_PATTERN_SELECT2 + * */ +#define XAVBUF_AUD_PATTERN_SELECT2 0X0000B108 + +#define XAVBUF_AUD_PATTERN_SELECT2_PATTERN_SHIFT 0 +#define XAVBUF_AUD_PATTERN_SELECT2_PATTERN_WIDTH 2 +#define XAVBUF_AUD_PATTERN_SELECT2_PATTERN_MASK 0X00000003 + +/** + * * Register: XAVBUF_BUF_AUD_VID_CLK_SOURCE + * */ +#define XAVBUF_BUF_AUD_VID_CLK_SOURCE 0X0000B120 + +#define XAVBUF_BUF_AUD_VID_CLK_SOURCE_VID_TIMING_SRC_SHIFT 2 +#define XAVBUF_BUF_AUD_VID_CLK_SOURCE_VID_TIMING_SRC_WIDTH 1 +#define XAVBUF_BUF_AUD_VID_CLK_SOURCE_VID_TIMING_SRC_MASK 0X00000004 + +#define XAVBUF_BUF_AUD_VID_CLK_SOURCE_AUD_CLK_SRC_SHIFT 1 +#define XAVBUF_BUF_AUD_VID_CLK_SOURCE_AUD_CLK_SRC_WIDTH 1 +#define XAVBUF_BUF_AUD_VID_CLK_SOURCE_AUD_CLK_SRC_MASK 0X00000002 + +#define XAVBUF_BUF_AUD_VID_CLK_SOURCE_VID_CLK_SRC_SHIFT 0 +#define XAVBUF_BUF_AUD_VID_CLK_SOURCE_VID_CLK_SRC_WIDTH 1 +#define XAVBUF_BUF_AUD_VID_CLK_SOURCE_VID_CLK_SRC_MASK 0X00000001 + +/** + * * Register: XAVBUF_BUF_SRST_REG + * */ +#define XAVBUF_BUF_SRST_REG 0X0000B124 + +#define XAVBUF_BUF_SRST_REG_VID_RST_SHIFT 1 +#define XAVBUF_BUF_SRST_REG_VID_RST_WIDTH 1 +#define XAVBUF_BUF_SRST_REG_VID_RST_MASK 0X00000002 + +/** + * * Register: XAVBUF_BUF_AUD_RDY_INTERVAL + * */ +#define XAVBUF_BUF_AUD_RDY_INTERVAL 0X0000B128 + +#define XAVBUF_BUF_AUD_RDY_INTERVAL_CH1_INT_SHIFT 16 +#define XAVBUF_BUF_AUD_RDY_INTERVAL_CH1_INT_WIDTH 16 +#define XAVBUF_BUF_AUD_RDY_INTERVAL_CH1_INT_MASK 0XFFFF0000 + +#define XAVBUF_BUF_AUD_RDY_INTERVAL_CH0_INT_SHIFT 0 +#define XAVBUF_BUF_AUD_RDY_INTERVAL_CH0_INT_WIDTH 16 +#define XAVBUF_BUF_AUD_RDY_INTERVAL_CH0_INT_MASK 0X0000FFFF + +/** + * * Register: XAVBUF_BUF_AUD_CH_CFG + * */ +#define XAVBUF_BUF_AUD_CH_CFG 0X0000B12C + +#define XAVBUF_BUF_AUD_CH_CFG_AUD_CH_ID_SHIFT 0 +#define XAVBUF_BUF_AUD_CH_CFG_AUD_CH_ID_WIDTH 2 +#define XAVBUF_BUF_AUD_CH_CFG_AUD_CH_ID_MASK 0X00000003 + +/** + * * Register: XAVBUF_BUF_GRAPHICS_COMP0_SCALE_FACTOR + * */ +#define XAVBUF_BUF_GRAPHICS_COMP0_SCALE_FACTOR 0X0000B200 + +#define XAVBUF_BUF_GRAPHICS_COMP0_SCALE_FACTOR_GRAPHICS_SCALE_FACTOR0_SHIFT 0 +#define XAVBUF_BUF_GRAPHICS_COMP0_SCALE_FACTOR_GRAPHICS_SCALE_FACTOR0_WIDTH 17 +#define XAVBUF_BUF_GRAPHICS_COMP0_SCALE_FACTOR_GRAPHICS_SCALE_FACTOR0_MASK 0X0001FFFF + +/** + * * Register: XAVBUF_BUF_GRAPHICS_COMP1_SCALE_FACTOR + * */ +#define XAVBUF_BUF_GRAPHICS_COMP1_SCALE_FACTOR 0X0000B204 + +#define XAVBUF_BUF_GRAPHICS_COMP1_SCALE_FACTOR_GRAPHICS_SCALE_FACTOR1_SHIFT 0 +#define XAVBUF_BUF_GRAPHICS_COMP1_SCALE_FACTOR_GRAPHICS_SCALE_FACTOR1_WIDTH 17 +#define XAVBUF_BUF_GRAPHICS_COMP1_SCALE_FACTOR_GRAPHICS_SCALE_FACTOR1_MASK 0X0001FFFF + +/** + * * Register: XAVBUF_BUF_GRAPHICS_COMP2_SCALE_FACTOR + * */ +#define XAVBUF_BUF_GRAPHICS_COMP2_SCALE_FACTOR 0X0000B208 + +#define XAVBUF_BUF_GRAPHICS_COMP2_SCALE_FACTOR_GRAPHICS_SCALE_FACTOR2_SHIFT 0 +#define XAVBUF_BUF_GRAPHICS_COMP2_SCALE_FACTOR_GRAPHICS_SCALE_FACTOR2_WIDTH 17 +#define XAVBUF_BUF_GRAPHICS_COMP2_SCALE_FACTOR_GRAPHICS_SCALE_FACTOR2_MASK 0X0001FFFF + +/** + * * Register: XAVBUF_BUF_VID_COMP0_SCALE_FACTOR + * */ +#define XAVBUF_BUF_VID_COMP0_SCALE_FACTOR 0X0000B20C + +#define XAVBUF_BUF_VID_COMP0_SCALE_FACTOR_VID_SCA_FACT0_SHIFT 0 +#define XAVBUF_BUF_VID_COMP0_SCALE_FACTOR_VID_SCA_FACT0_WIDTH 17 +#define XAVBUF_BUF_VID_COMP0_SCALE_FACTOR_VID_SCA_FACT0_MASK 0X0001FFFF + +/** + * * Register: XAVBUF_BUF_VID_COMP1_SCALE_FACTOR + * */ +#define XAVBUF_BUF_VID_COMP1_SCALE_FACTOR 0X0000B210 + +#define XAVBUF_BUF_VID_COMP1_SCALE_FACTOR_VID_SCA_FACT1_SHIFT 0 +#define XAVBUF_BUF_VID_COMP1_SCALE_FACTOR_VID_SCA_FACT1_WIDTH 17 +#define XAVBUF_BUF_VID_COMP1_SCALE_FACTOR_VID_SCA_FACT1_MASK 0X0001FFFF + +/** + * * Register: XAVBUF_BUF_VID_COMP2_SCALE_FACTOR + * */ +#define XAVBUF_BUF_VID_COMP2_SCALE_FACTOR 0X0000B214 + +#define XAVBUF_BUF_VID_COMP2_SCALE_FACTOR_VID_SCA_FACT2_SHIFT 0 +#define XAVBUF_BUF_VID_COMP2_SCALE_FACTOR_VID_SCA_FACT2_WIDTH 17 +#define XAVBUF_BUF_VID_COMP2_SCALE_FACTOR_VID_SCA_FACT2_MASK 0X0001FFFF + +/** + * * Register: XAVBUF_BUF_LIVE_VID_COMP0_SF + * */ +#define XAVBUF_BUF_LIVE_VID_COMP0_SF 0X0000B218 + +#define XAVBUF_BUF_LIVE_VID_COMP0_SF_LIV_VID_SCA_FACT0_SHIFT 0 +#define XAVBUF_BUF_LIVE_VID_COMP0_SF_LIV_VID_SCA_FACT0_WIDTH 17 +#define XAVBUF_BUF_LIVE_VID_COMP0_SF_LIV_VID_SCA_FACT0_MASK 0X0001FFFF + +/** + * * Register: XAVBUF_BUF_LIVE_VID_COMP1_SF + * */ +#define XAVBUF_BUF_LIVE_VID_COMP1_SF 0X0000B21C + +#define XAVBUF_BUF_LIVE_VID_COMP1_SF_LIV_VID_SCA_FACT1_SHIFT 0 +#define XAVBUF_BUF_LIVE_VID_COMP1_SF_LIV_VID_SCA_FACT1_WIDTH 17 +#define XAVBUF_BUF_LIVE_VID_COMP1_SF_LIV_VID_SCA_FACT1_MASK 0X0001FFFF + +/** + * * Register: XAVBUF_BUF_LIVE_VID_COMP2_SF + * */ +#define XAVBUF_BUF_LIVE_VID_COMP2_SF 0X0000B220 + +#define XAVBUF_BUF_LIVE_VID_COMP2_SF_LIV_VID_SCA_FACT2_SHIFT 0 +#define XAVBUF_BUF_LIVE_VID_COMP2_SF_LIV_VID_SCA_FACT2_WIDTH 17 +#define XAVBUF_BUF_LIVE_VID_COMP2_SF_LIV_VID_SCA_FACT2_MASK 0X0001FFFF + +/** + * * Register: XAVBUF_BUF_LIVE_VID_CFG + * */ +#define XAVBUF_BUF_LIVE_VID_CFG 0X0000B224 + +#define XAVBUF_BUF_LIVE_VID_CFG_CB_FIRST_SHIFT 8 +#define XAVBUF_BUF_LIVE_VID_CFG_CB_FIRST_WIDTH 1 +#define XAVBUF_BUF_LIVE_VID_CFG_CB_FIRST_MASK 0X00000100 + +#define XAVBUF_BUF_LIVE_VID_CFG_FORMAT_SHIFT 4 +#define XAVBUF_BUF_LIVE_VID_CFG_FORMAT_WIDTH 2 +#define XAVBUF_BUF_LIVE_VID_CFG_FORMAT_MASK 0X00000030 + +#define XAVBUF_BUF_LIVE_VID_CFG_BPC_SHIFT 0 +#define XAVBUF_BUF_LIVE_VID_CFG_BPC_WIDTH 3 +#define XAVBUF_BUF_LIVE_VID_CFG_BPC_MASK 0X00000007 + +/** + * * Register: XAVBUF_BUF_LIVE_GFX_COMP0_SF + * */ +#define XAVBUF_BUF_LIVE_GFX_COMP0_SF 0X0000B228 + +#define XAVBUF_BUF_LIVE_GFX_COMP0_SF_LIV_VID_SCA_FACT0_SHIFT 0 +#define XAVBUF_BUF_LIVE_GFX_COMP0_SF_LIV_VID_SCA_FACT0_WIDTH 17 +#define XAVBUF_BUF_LIVE_GFX_COMP0_SF_LIV_VID_SCA_FACT0_MASK 0X0001FFFF + +/** + * * Register: XAVBUF_BUF_LIVE_GFX_COMP1_SF + * */ +#define XAVBUF_BUF_LIVE_GFX_COMP1_SF 0X0000B22C + +#define XAVBUF_BUF_LIVE_GFX_COMP1_SF_LIV_VID_SCA_FACT1_SHIFT 0 +#define XAVBUF_BUF_LIVE_GFX_COMP1_SF_LIV_VID_SCA_FACT1_WIDTH 17 +#define XAVBUF_BUF_LIVE_GFX_COMP1_SF_LIV_VID_SCA_FACT1_MASK 0X0001FFFF + +/** + * * Register: XAVBUF_BUF_LIVE_GFX_COMP2_SF + * */ +#define XAVBUF_BUF_LIVE_GFX_COMP2_SF 0X0000B230 + +#define XAVBUF_BUF_LIVE_GFX_COMP2_SF_LIV_VID_SCA_FACT2_SHIFT 0 +#define XAVBUF_BUF_LIVE_GFX_COMP2_SF_LIV_VID_SCA_FACT2_WIDTH 17 +#define XAVBUF_BUF_LIVE_GFX_COMP2_SF_LIV_VID_SCA_FACT2_MASK 0X0001FFFF + +/** + * * Register: XAVBUF_BUF_LIVE_GFX_CFG + * */ +#define XAVBUF_BUF_LIVE_GFX_CFG 0X0000B234 + +#define XAVBUF_BUF_LIVE_GFX_CFG_CB_FIRST_SHIFT 8 +#define XAVBUF_BUF_LIVE_GFX_CFG_CB_FIRST_WIDTH 1 +#define XAVBUF_BUF_LIVE_GFX_CFG_CB_FIRST_MASK 0X00000100 + +#define XAVBUF_BUF_LIVE_GFX_CFG_FORMAT_SHIFT 4 +#define XAVBUF_BUF_LIVE_GFX_CFG_FORMAT_WIDTH 2 +#define XAVBUF_BUF_LIVE_GFX_CFG_FORMAT_MASK 0X00000030 + +#define XAVBUF_BUF_LIVE_GFX_CFG_BPC_SHIFT 0 +#define XAVBUF_BUF_LIVE_GFX_CFG_BPC_WIDTH 3 +#define XAVBUF_BUF_LIVE_GFX_CFG_BPC_MASK 0X00000007 + +/** + * * Register: XAVBUF_AUD_MIXER_VOLUME_CONTROL + * */ +#define XAVBUF_AUD_MIXER_VOLUME_CONTROL 0X0000C000 + +#define XAVBUF_AUD_MIXER_VOLUME_CONTROL_VOL_CTRL_CH1_SHIFT 16 +#define XAVBUF_AUD_MIXER_VOLUME_CONTROL_VOL_CTRL_CH1_WIDTH 16 +#define XAVBUF_AUD_MIXER_VOLUME_CONTROL_VOL_CTRL_CH1_MASK 0XFFFF0000 + +#define XAVBUF_AUD_MIXER_VOLUME_CONTROL_VOL_CTRL_CH0_SHIFT 0 +#define XAVBUF_AUD_MIXER_VOLUME_CONTROL_VOL_CTRL_CH0_WIDTH 16 +#define XAVBUF_AUD_MIXER_VOLUME_CONTROL_VOL_CTRL_CH0_MASK 0X0000FFFF + +/** + * * Register: XAVBUF_AUD_MIXER_META_DATA + * */ +#define XAVBUF_AUD_MIXER_META_DATA 0X0000C004 + +#define XAVBUF_AUD_MIXER_META_DATA_AUD_META_DATA_SEL_SHIFT 0 +#define XAVBUF_AUD_MIXER_META_DATA_AUD_META_DATA_SEL_WIDTH 1 +#define XAVBUF_AUD_MIXER_META_DATA_AUD_META_DATA_SEL_MASK 0X00000001 + +/** + * * Register: XAVBUF_AUD_CH_STATUS_REG0 + * */ +#define XAVBUF_AUD_CH_STATUS_REG0 0X0000C008 + +#define XAVBUF_AUD_CH_STATUS_REG0_STATUS0_SHIFT 0 +#define XAVBUF_AUD_CH_STATUS_REG0_STATUS0_WIDTH 32 +#define XAVBUF_AUD_CH_STATUS_REG0_STATUS0_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_STATUS_REG1 + * */ +#define XAVBUF_AUD_CH_STATUS_REG1 0X0000C00C + +#define XAVBUF_AUD_CH_STATUS_REG1_STATUS1_SHIFT 0 +#define XAVBUF_AUD_CH_STATUS_REG1_STATUS1_WIDTH 32 +#define XAVBUF_AUD_CH_STATUS_REG1_STATUS1_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_STATUS_REG2 + * */ +#define XAVBUF_AUD_CH_STATUS_REG2 0X0000C010 + +#define XAVBUF_AUD_CH_STATUS_REG2_STATUS2_SHIFT 0 +#define XAVBUF_AUD_CH_STATUS_REG2_STATUS2_WIDTH 32 +#define XAVBUF_AUD_CH_STATUS_REG2_STATUS2_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_STATUS_REG3 + * */ +#define XAVBUF_AUD_CH_STATUS_REG3 0X0000C014 + +#define XAVBUF_AUD_CH_STATUS_REG3_STATUS3_SHIFT 0 +#define XAVBUF_AUD_CH_STATUS_REG3_STATUS3_WIDTH 32 +#define XAVBUF_AUD_CH_STATUS_REG3_STATUS3_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_STATUS_REG4 + * */ +#define XAVBUF_AUD_CH_STATUS_REG4 0X0000C018 + +#define XAVBUF_AUD_CH_STATUS_REG4_STATUS4_SHIFT 0 +#define XAVBUF_AUD_CH_STATUS_REG4_STATUS4_WIDTH 32 +#define XAVBUF_AUD_CH_STATUS_REG4_STATUS4_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_STATUS_REG5 + * */ +#define XAVBUF_AUD_CH_STATUS_REG5 0X0000C01C + +#define XAVBUF_AUD_CH_STATUS_REG5_STATUS5_SHIFT 0 +#define XAVBUF_AUD_CH_STATUS_REG5_STATUS5_WIDTH 32 +#define XAVBUF_AUD_CH_STATUS_REG5_STATUS5_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_A_DATA_REG0 + * */ +#define XAVBUF_AUD_CH_A_DATA_REG0 0X0000C020 + +#define XAVBUF_AUD_CH_A_DATA_REG0_USER_DATA0_SHIFT 0 +#define XAVBUF_AUD_CH_A_DATA_REG0_USER_DATA0_WIDTH 32 +#define XAVBUF_AUD_CH_A_DATA_REG0_USER_DATA0_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_A_DATA_REG1 + * */ +#define XAVBUF_AUD_CH_A_DATA_REG1 0X0000C024 + +#define XAVBUF_AUD_CH_A_DATA_REG1_USER_DATA1_SHIFT 0 +#define XAVBUF_AUD_CH_A_DATA_REG1_USER_DATA1_WIDTH 32 +#define XAVBUF_AUD_CH_A_DATA_REG1_USER_DATA1_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_A_DATA_REG2 + * */ +#define XAVBUF_AUD_CH_A_DATA_REG2 0X0000C028 + +#define XAVBUF_AUD_CH_A_DATA_REG2_USER_DATA2_SHIFT 0 +#define XAVBUF_AUD_CH_A_DATA_REG2_USER_DATA2_WIDTH 32 +#define XAVBUF_AUD_CH_A_DATA_REG2_USER_DATA2_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_A_DATA_REG3 + * */ +#define XAVBUF_AUD_CH_A_DATA_REG3 0X0000C02C + +#define XAVBUF_AUD_CH_A_DATA_REG3_USER_DATA3_SHIFT 0 +#define XAVBUF_AUD_CH_A_DATA_REG3_USER_DATA3_WIDTH 32 +#define XAVBUF_AUD_CH_A_DATA_REG3_USER_DATA3_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_A_DATA_REG4 + * */ +#define XAVBUF_AUD_CH_A_DATA_REG4 0X0000C030 + +#define XAVBUF_AUD_CH_A_DATA_REG4_USER_DATA4_SHIFT 0 +#define XAVBUF_AUD_CH_A_DATA_REG4_USER_DATA4_WIDTH 32 +#define XAVBUF_AUD_CH_A_DATA_REG4_USER_DATA4_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_A_DATA_REG5 + * */ +#define XAVBUF_AUD_CH_A_DATA_REG5 0X0000C034 + +#define XAVBUF_AUD_CH_A_DATA_REG5_USER_DATA5_SHIFT 0 +#define XAVBUF_AUD_CH_A_DATA_REG5_USER_DATA5_WIDTH 32 +#define XAVBUF_AUD_CH_A_DATA_REG5_USER_DATA5_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_B_DATA_REG0 + * */ +#define XAVBUF_AUD_CH_B_DATA_REG0 0X0000C038 + +#define XAVBUF_AUD_CH_B_DATA_REG0_USER_DATA0_SHIFT 0 +#define XAVBUF_AUD_CH_B_DATA_REG0_USER_DATA0_WIDTH 32 +#define XAVBUF_AUD_CH_B_DATA_REG0_USER_DATA0_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_B_DATA_REG1 + * */ +#define XAVBUF_AUD_CH_B_DATA_REG1 0X0000C03C + +#define XAVBUF_AUD_CH_B_DATA_REG1_USER_DATA1_SHIFT 0 +#define XAVBUF_AUD_CH_B_DATA_REG1_USER_DATA1_WIDTH 32 +#define XAVBUF_AUD_CH_B_DATA_REG1_USER_DATA1_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_B_DATA_REG2 + * */ +#define XAVBUF_AUD_CH_B_DATA_REG2 0X0000C040 + +#define XAVBUF_AUD_CH_B_DATA_REG2_USER_DATA2_SHIFT 0 +#define XAVBUF_AUD_CH_B_DATA_REG2_USER_DATA2_WIDTH 32 +#define XAVBUF_AUD_CH_B_DATA_REG2_USER_DATA2_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_B_DATA_REG3 + * */ +#define XAVBUF_AUD_CH_B_DATA_REG3 0X0000C044 + +#define XAVBUF_AUD_CH_B_DATA_REG3_USER_DATA3_SHIFT 0 +#define XAVBUF_AUD_CH_B_DATA_REG3_USER_DATA3_WIDTH 32 +#define XAVBUF_AUD_CH_B_DATA_REG3_USER_DATA3_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_B_DATA_REG4 + * */ +#define XAVBUF_AUD_CH_B_DATA_REG4 0X0000C048 + +#define XAVBUF_AUD_CH_B_DATA_REG4_USER_DATA4_SHIFT 0 +#define XAVBUF_AUD_CH_B_DATA_REG4_USER_DATA4_WIDTH 32 +#define XAVBUF_AUD_CH_B_DATA_REG4_USER_DATA4_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_B_DATA_REG5 + * */ +#define XAVBUF_AUD_CH_B_DATA_REG5 0X0000C04C + +#define XAVBUF_AUD_CH_B_DATA_REG5_USER_DATA5_SHIFT 0 +#define XAVBUF_AUD_CH_B_DATA_REG5_USER_DATA5_WIDTH 32 +#define XAVBUF_AUD_CH_B_DATA_REG5_USER_DATA5_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_SOFT_RST + * */ +#define XAVBUF_AUD_SOFT_RST 0X0000CC00 + +#define XAVBUF_AUD_SOFT_RST_EXTRA_BS_CONTROL_SHIFT 2 +#define XAVBUF_AUD_SOFT_RST_EXTRA_BS_CONTROL_WIDTH 1 +#define XAVBUF_AUD_SOFT_RST_EXTRA_BS_CONTROL_MASK 0X00000004 + +#define XAVBUF_AUD_SOFT_RST_LINE_RST_DISABLE_SHIFT 1 +#define XAVBUF_AUD_SOFT_RST_LINE_RST_DISABLE_WIDTH 1 +#define XAVBUF_AUD_SOFT_RST_LINE_RST_DISABLE_MASK 0X00000002 + +#define XAVBUF_AUD_SOFT_RST_AUD_SRST_SHIFT 0 +#define XAVBUF_AUD_SOFT_RST_AUD_SRST_WIDTH 1 +#define XAVBUF_AUD_SOFT_RST_AUD_SRST_MASK 0X00000001 + +/** + * * Register: XAVBUF_PATGEN_CRC_R + * */ +#define XAVBUF_PATGEN_CRC_R 0X0000CC10 + +#define XAVBUF_PATGEN_CRC_R_CRC_R_SHIFT 0 +#define XAVBUF_PATGEN_CRC_R_CRC_R_WIDTH 16 +#define XAVBUF_PATGEN_CRC_R_CRC_R_MASK 0X0000FFFF + +/** + * * Register: XAVBUF_PATGEN_CRC_G + * */ +#define XAVBUF_PATGEN_CRC_G 0X0000CC14 + +#define XAVBUF_PATGEN_CRC_G_CRC_G_SHIFT 0 +#define XAVBUF_PATGEN_CRC_G_CRC_G_WIDTH 16 +#define XAVBUF_PATGEN_CRC_G_CRC_G_MASK 0X0000FFFF + +/** + * * Register: XAVBUF_PATGEN_CRC_B + * */ +#define XAVBUF_PATGEN_CRC_B 0X0000CC18 + +#define XAVBUF_PATGEN_CRC_B_CRC_B_SHIFT 0 +#define XAVBUF_PATGEN_CRC_B_CRC_B_WIDTH 16 +#define XAVBUF_PATGEN_CRC_B_CRC_B_MASK 0X0000FFFF + +#define XAVBUF_NUM_SUPPORTED 52 + +#define XAVBUF_BUF_4BIT_SF 0x11111 +#define XAVBUF_BUF_5BIT_SF 0x10842 +#define XAVBUF_BUF_6BIT_SF 0x10410 +#define XAVBUF_BUF_8BIT_SF 0x10101 +#define XAVBUF_BUF_10BIT_SF 0x10040 +#define XAVBUF_BUF_12BIT_SF 0x10000 + +#define XAVBUF_BUF_6BPC 0x000 +#define XAVBUF_BUF_8BPC 0x001 +#define XAVBUF_BUF_10BPC 0x010 +#define XAVBUF_BUF_12BPC 0x011 + +#define XAVBUF_CHBUF_V_BURST_LEN 0xF +#define XAVBUF_CHBUF_A_BURST_LEN 0x3 + +#define XAVBUF_PL_CLK 0x0 +#define XAVBUF_PS_CLK 0x1 + +#define XAVBUF_NUM_SUPPORTED_NLVID 25 +#define XAVBUF_NUM_SUPPORTED_NLGFX 14 +#define XAVBUF_NUM_SUPPORTED_LIVE 14 +#define XAVBUF_NUM_OUTPUT_FORMATS 14 + +/** + * Address mapping for PLL (CRF and CRL) + */ + +/* Base Address for CLOCK in FPD. */ +#define XAVBUF_CLK_FPD_BASEADDR 0XFD1A0000 + +/* Base Address for CLOCK in LPD. */ +#define XAVBUF_CLK_LPD_BASEADDR 0XFF5E0000 + +/** + * The following constants define values to manipulate + * the bits of the VPLL control register. + */ +#define XAVBUF_PLL_CTRL 0X00000020 + +#define XAVBUF_PLL_CTRL_POST_SRC_SHIFT 24 +#define XAVBUF_PLL_CTRL_POST_SRC_WIDTH 3 +#define XAVBUF_PLL_CTRL_POST_SRC_MASK 0X07000000 + +#define XAVBUF_PLL_CTRL_PRE_SRC_SHIFT 20 +#define XAVBUF_VPLL_CTRL_PRE_SRC_WIDTH 3 +#define XAVBUF_VPLL_CTRL_PRE_SRC_MASK 0X00700000 + +#define XAVBUF_PLL_CTRL_CLKOUTDIV_SHIFT 17 +#define XAVBUF_PLL_CTRL_CLKOUTDIV_WIDTH 1 +#define XAVBUF_PLL_CTRL_CLKOUTDIV_MASK 0X00020000 + +#define XAVBUF_PLL_CTRL_DIV2_SHIFT 16 +#define XAVBUF_PLL_CTRL_DIV2_WIDTH 1 +#define XAVBUF_PLL_CTRL_DIV2_MASK 0X00010000 + +#define XAVBUF_PLL_CTRL_FBDIV_SHIFT 8 +#define XAVBUF_PLL_CTRL_FBDIV_WIDTH 7 +#define XAVBUF_PLL_CTRL_FBDIV_MASK 0X00007F00 + +#define XAVBUF_PLL_CTRL_BYPASS_SHIFT 3 +#define XAVBUF_PLL_CTRL_BYPASS_WIDTH 1 +#define XAVBUF_PLL_CTRL_BYPASS_MASK 0X00000008 + +#define XAVBUF_PLL_CTRL_RESET_SHIFT 0 +#define XAVBUF_PLL_CTRL_RESET_WIDTH 1 +#define XAVBUF_PLL_CTRL_RESET_MASK 0X00000001 + +/** + * The following constants define values to manipulate + * the bits of the PLL config register. + */ +#define XAVBUF_PLL_CFG 0X00000024 + +#define XAVBUF_PLL_CFG_LOCK_DLY_SHIFT 25 +#define XAVBUF_PLL_CFG_LOCK_DLY_WIDTH 7 +#define XAVBUF_PLL_CFG_LOCK_DLY_MASK 0XFE000000 + +#define XAVBUF_PLL_CFG_LOCK_CNT_SHIFT 13 +#define XAVBUF_PLL_CFG_LOCK_CNT_WIDTH 10 +#define XAVBUF_PLL_CFG_LOCK_CNT_MASK 0X007FE000 + +#define XAVBUF_PLL_CFG_LFHF_SHIFT 10 +#define XAVBUF_PLL_CFG_LFHF_WIDTH 2 +#define XAVBUF_PLL_CFG_LFHF_MASK 0X00000C00 + +#define XAVBUF_PLL_CFG_CP_SHIFT 5 +#define XAVBUF_PLL_CFG_CP_WIDTH 4 +#define XAVBUF_PLL_CFG_CP_MASK 0X000001E0 + +#define XAVBUF_PLL_CFG_RES_SHIFT 0 +#define XAVBUF_PLL_CFG_RES_WIDTH 4 +#define XAVBUF_PLL_CFG_RES_MASK 0X0000000F + +/** + * The following constants define values to manipulate + * the bits of the VPLL fractional config register. + */ +#define XAVBUF_PLL_FRAC_CFG 0X00000028 + +#define XAVBUF_PLL_FRAC_CFG_ENABLED_SHIFT 31 +#define XAVBUF_PLL_FRAC_CFG_ENABLED_WIDTH 1 +#define XAVBUF_PLL_FRAC_CFG_ENABLED_MASK 0X80000000 + +#define XAVBUF_PLL_FRAC_CFG_SEED_SHIFT 22 +#define XAVBUF_PLL_FRAC_CFG_SEED_WIDTH 3 +#define XAVBUF_PLL_FRAC_CFG_SEED_MASK 0X01C00000 + +#define XAVBUF_PLL_FRAC_CFG_ALGRTHM_SHIFT 19 +#define XAVBUF_PLL_FRAC_CFG_ALGRTHM_WIDTH 1 +#define XAVBUF_PLL_FRAC_CFG_ALGRTHM_MASK 0X00080000 + +#define XAVBUF_PLL_FRAC_CFG_ORDER_SHIFT 18 +#define XAVBUF_PLL_FRAC_CFG_ORDER_WIDTH 1 +#define XAVBUF_PLL_FRAC_CFG_ORDER_MASK 0X00040000 + +#define XAVBUF_PLL_FRAC_CFG_DATA_SHIFT 0 +#define XAVBUF_PLL_FRAC_CFG_DATA_WIDTH 16 +#define XAVBUF_PLL_FRAC_CFG_DATA_MASK 0X0000FFFF + +/** + * The following constants define values to manipulate + * the bits of the PLL STATUS register. + */ +#define XAVBUF_PLL_STATUS 0X00000044 + +#define XAVBUF_PLL_STATUS_VPLL_STABLE_SHIFT 5 +#define XAVBUF_PLL_STATUS_VPLL_STABLE_WIDTH 1 +#define XAVBUF_PLL_STATUS_VPLL_STABLE_MASK 0X00000020 + +#define XAVBUF_PLL_STATUS_DPLL_STABLE_SHIFT 4 +#define XAVBUF_PLL_STATUS_DPLL_STABLE_WIDTH 1 +#define XAVBUF_PLL_STATUS_DPLL_STABLE_MASK 0X00000010 + +#define XAVBUF_PLL_STATUS_APLL_STABLE_SHIFT 3 +#define XAVBUF_PLL_STATUS_APLL_STABLE_WIDTH 1 +#define XAVBUF_PLL_STATUS_APLL_STABLE_MASK 0X00000008 + +#define XAVBUF_PLL_STATUS_VPLL_LOCK_SHIFT 2 +#define XAVBUF_PLL_STATUS_VPLL_LOCK_WIDTH 1 +#define XAVBUF_PLL_STATUS_VPLL_LOCK_MASK 0X00000004 + +#define XAVBUF_PLL_STATUS_DPLL_LOCK_SHIFT 1 +#define XAVBUF_PLL_STATUS_DPLL_LOCK_WIDTH 1 +#define XAVBUF_PLL_STATUS_DPLL_LOCK_MASK 0X00000002 + +#define XAVBUF_PLL_STATUS_APLL_LOCK_SHIFT 0 +#define XAVBUF_PLL_STATUS_APLL_LOCK_WIDTH 1 +#define XAVBUF_PLL_STATUS_APLL_LOCK_MASK 0X00000001 + +/** + * The following constants define values to manipulate + * the bits of the VIDEO reference control register. + */ +#define XAVBUF_VIDEO_REF_CTRL 0X00000070 + +#define XAVBUF_VIDEO_REF_CTRL_CLKACT_SHIFT 24 +#define XAVBUF_VIDEO_REF_CTRL_CLKACT_WIDTH 1 +#define XAVBUF_VIDEO_REF_CTRL_CLKACT_MASK 0X01000000 + +#define XAVBUF_VIDEO_REF_CTRL_DIVISOR1_SHIFT 16 +#define XAVBUF_VIDEO_REF_CTRL_DIVISOR1_WIDTH 6 +#define XAVBUF_VIDEO_REF_CTRL_DIVISOR1_MASK 0X003F0000 + +#define XAVBUF_VIDEO_REF_CTRL_DIVISOR0_SHIFT 8 +#define XAVBUF_VIDEO_REF_CTRL_DIVISOR0_WIDTH 6 +#define XAVBUF_VIDEO_REF_CTRL_DIVISOR0_MASK 0X00003F00 + +#define XAVBUF_VIDEO_REF_CTRL_SRCSEL_SHIFT 0 +#define XAVBUF_VIDEO_REF_CTRL_SRCSEL_WIDTH 3 +#define XAVBUF_VIDEO_REF_CTRL_SRCSEL_MASK 0X00000007 + +/** + * The following constants define values to manipulate + * the bits of the AUDIO reference control register. + */ +#define XAVBUF_AUDIO_REF_CTRL 0X00000074 + +#define XAVBUF_AUDIO_REF_CTRL_CLKACT_SHIFT 24 +#define XAVBUF_AUDIO_REF_CTRL_CLKACT_WIDTH 1 +#define XAVBUF_AUDIO_REF_CTRL_CLKACT_MASK 0X01000000 + +#define XAVBUF_AUDIO_REF_CTRL_DIVISOR1_SHIFT 16 +#define XAVBUF_AUDIO_REF_CTRL_DIVISOR1_WIDTH 6 +#define XAVBUF_AUDIO_REF_CTRL_DIVISOR1_MASK 0X003F0000 + +#define XAVBUF_AUDIO_REF_CTRL_DIVISOR0_SHIFT 8 +#define XAVBUF_AUDIO_REF_CTRL_DIVISOR0_WIDTH 6 +#define XAVBUF_AUDIO_REF_CTRL_DIVISOR0_MASK 0X00003F00 + +#define XAVBUF_AUDIO_REF_CTRL_SRCSEL_SHIFT 0 +#define XAVBUF_AUDIO_REF_CTRL_SRCSEL_WIDTH 3 +#define XAVBUF_AUDIO_REF_CTRL_SRCSEL_MASK 0X00000007 + +/** + * The following constants define values to manipulate + * the bits of the Domain Switch register. + * For eg. FPD to LPD. + */ +#define XAVBUF_DOMAIN_SWITCH_CTRL 0X00000044 + +#define XAVBUF_DOMAIN_SWITCH_DIVISOR0_SHIFT 8 +#define XAVBUF_DOMAIN_SWITCH_DIVISOR0_WIDTH 6 +#define XAVBUF_DOMAIN_SWITCH_DIVISOR0_MASK 0X00003F00 + +/** + * The following constants define values to Reference + * clock. + */ +#define XAVBUF_Pss_Ref_Clk 0 +#define XAVBUF_Video_Clk 4 +#define XAVBUF_Pss_alt_Ref_Clk 5 +#define XAVBUF_Aux_Ref_clk 6 +#define XAVBUF_Gt_Crx_Ref_Clk 7 + +/** + * The following constants define values to manipulate + * the bits of any register. + */ +#define XAVBUF_ENABLE_BIT 1 +#define XAVBUF_DISABLE_BIT 0 + +/** + * The following constants define values available + * PLL source to Audio and Video. + */ +#define XAVBUF_VPLL_SRC_SEL 0 +#define XAVBUF_DPLL_SRC_SEL 2 +#define XAVBUF_RPLL_TO_FPD_SRC_SEL 3 + +/******************* Macros (Inline Functions) Definitions ********************/ + +/** @name Register access macro definitions. + * @{ + */ +#define XAVBuf_In32 Xil_In32 +#define XAVBuf_Out32 Xil_Out32 +/* @} */ + +/******************************************************************************/ +/** + * This is a low-level function that reads from the specified register. + * + * @param BaseAddress is the base address of the device. + * @param RegOffset is the register offset to be read from. + * + * @return The 32-bit value of the specified register. + * + * @note C-style signature: + * u32 XAVBuf_ReadReg(u32 BaseAddress, u32 RegOffset) + * +*******************************************************************************/ +#define XAVBuf_ReadReg(BaseAddress, RegOffset) \ + XAVBuf_In32((BaseAddress) + (RegOffset)) + +/******************************************************************************/ +/** + * This is a low-level function that writes to the specified register. + * + * @param BaseAddress is the base address of the device. + * @param RegOffset is the register offset to write to. + * @param Data is the 32-bit data to write to the specified register. + * + * @return None. + * + * @note C-style signature: + * void XAVBuf_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) + * +*******************************************************************************/ +#define XAVBuf_WriteReg(BaseAddress, RegOffset, Data) \ + XAVBuf_Out32((BaseAddress) + (RegOffset), (Data)) + + +#ifdef __cplusplus +} +#endif + + +#endif //XAVBUF_H_
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/xavbuf_videoformats.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/xavbuf_videoformats.c new file mode 100644 index 0000000..4651cd8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/xavbuf_videoformats.c
@@ -0,0 +1,227 @@ +/******************************************************************************* + * + * Copyright (C) 2017 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xavbuf_videoformats.c + * @addtogroup xavbuf_v2_1 + * @{ + * + * Contains attributes of the video formats mapped to the hardware + * + * @note None. + * + * <pre> + * MODIFICATION HISTORY: + * + * Ver Who Date Changes + * ----- ---- -------- ----------------------------------------------- + * 1.0 aad 03/10/17 Initial release. + * 2.0 aad 02/22/18 Fixed scaling factors and bits per pixel + * </pre> + * +*******************************************************************************/ + +/******************************* Include Files ********************************/ + +#include "xavbuf.h" + + +/**************************** Variable Definitions ****************************/ +#ifdef __cplusplus +extern "C" +#endif + +const XAVBuf_VideoAttribute XAVBuf_SupportedFormats[XAVBUF_NUM_SUPPORTED] = +{ + /* Non - Live Video Formats */ + { CbY0CrY1, 0, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + TRUE, FALSE, FALSE, 16}, + { CrY0CbY1, 1, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + TRUE, FALSE, FALSE, 16}, + { Y0CrY1Cb, 2, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + TRUE, FALSE, FALSE, 16}, + { Y0CbY1Cr, 3, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + TRUE, FALSE, FALSE, 16}, + { YV16, 4, Planar, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + TRUE, FALSE, FALSE, 16}, + { YV24, 5, Planar, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, FALSE, FALSE, 24}, + { YV16Ci, 6, SemiPlanar, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + TRUE, FALSE, FALSE, 16}, + { MONOCHROME, 7, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + TRUE, FALSE, FALSE, 8}, + { YV16Ci2, 8, SemiPlanar, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + TRUE, FALSE, TRUE, 16}, + { YUV444, 9, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, FALSE, FALSE, 24}, + { RGB888, 10, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, TRUE, FALSE, 24}, + { RGBA8880, 11, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, TRUE, FALSE, 32}, + { RGB888_10BPC, 12, Interleaved, + {XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF}, + FALSE, TRUE, FALSE, 30}, + { YUV444_10BPC, 13, Interleaved, + {XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF}, + FALSE, FALSE, FALSE, 30}, + { YV16Ci2_10BPC, 14, SemiPlanar, + {XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF}, + TRUE, FALSE, TRUE, 20}, + { YV16Ci_10BPC, 15, SemiPlanar, + {XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF}, + TRUE, FALSE, FALSE, 20}, + { YV16_10BPC, 16, Planar, + {XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF}, + TRUE, FALSE, FALSE, 20}, + { YV24_10BPC, 17, Planar, + {XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF}, + FALSE, FALSE, FALSE, 30}, + { MONOCHROME_10BPC, 18, Interleaved, + {XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF}, + TRUE, FALSE, FALSE, 10}, + { YV16_420, 19, Planar, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + TRUE, FALSE, FALSE, 16}, + { YV16Ci_420, 20, SemiPlanar, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + TRUE, FALSE, FALSE, 16}, + { YV16Ci2_420, 21, SemiPlanar, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + TRUE, FALSE, TRUE, 16}, + { YV16_420_10BPC, 22, Planar, + {XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF}, + TRUE, FALSE, FALSE, 20}, + { YV16Ci_420_10BPC, 23, SemiPlanar, + {XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF}, + TRUE, FALSE, FALSE, 20}, + { YV16Ci2_420_10BPC, 24, SemiPlanar, + {XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF}, + TRUE, FALSE, TRUE, 20}, + + /* Non-Live Graphics formats */ + { RGBA8888, 0, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, TRUE, FALSE, 32}, + { ABGR8888, 1, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, TRUE, FALSE, 32}, + { RGB888_GFX, 2, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, TRUE, FALSE, 24}, + { BGR888, 3, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, TRUE, FALSE, 24}, + { RGBA5551, 4, Interleaved, + {XAVBUF_BUF_5BIT_SF, XAVBUF_BUF_5BIT_SF, XAVBUF_BUF_5BIT_SF}, + FALSE, TRUE, FALSE, 16}, + { RGBA4444, 5, Interleaved, + {XAVBUF_BUF_4BIT_SF, XAVBUF_BUF_4BIT_SF, XAVBUF_BUF_4BIT_SF}, + FALSE, TRUE, FALSE, 16}, + { RGB565, 6, Interleaved, + {XAVBUF_BUF_5BIT_SF, XAVBUF_BUF_6BIT_SF, XAVBUF_BUF_5BIT_SF}, + FALSE, TRUE, FALSE, 16}, + { BPP8, 7, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, TRUE, FALSE, 8}, + { BPP4, 8, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, TRUE, FALSE, 4}, + { BPP2, 9, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, TRUE, FALSE, 2}, + { BPP1, 10, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, TRUE, FALSE, 1}, + { YUV422, 11, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, FALSE, FALSE, 24}, + + /* Video Formats for Live Video/Graphics input and output sources */ + { RGB_6BPC, 0, Interleaved, + {XAVBUF_BUF_6BIT_SF, XAVBUF_BUF_6BIT_SF, XAVBUF_BUF_6BIT_SF}, + FALSE, TRUE, FALSE, 18}, + { RGB_8BPC, 0, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, TRUE, FALSE, 24}, + { RGB_10BPC, 0, Interleaved, + {XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF}, + FALSE, TRUE, FALSE, 30}, + { RGB_12BPC, 0, Interleaved, + {XAVBUF_BUF_12BIT_SF, XAVBUF_BUF_12BIT_SF, XAVBUF_BUF_12BIT_SF}, + FALSE, TRUE, FALSE, 36}, + { YCbCr444_6BPC, 1, Interleaved, + {XAVBUF_BUF_6BIT_SF, XAVBUF_BUF_6BIT_SF, XAVBUF_BUF_6BIT_SF}, + FALSE, FALSE, FALSE, 18}, + { YCbCr444_8BPC, 1, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, FALSE, FALSE, 24}, + { YCbCr444_10BPC, 1, Interleaved, + {XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF}, + FALSE, FALSE, FALSE, 30}, + { YCbCr444_12BPC, 1, Interleaved, + {XAVBUF_BUF_12BIT_SF, XAVBUF_BUF_12BIT_SF, XAVBUF_BUF_12BIT_SF}, + FALSE, FALSE, FALSE, 36}, + { YCbCr422_8BPC, 2, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + TRUE, FALSE, FALSE, 24}, + { YCbCr422_10BPC, 2, Interleaved, + {XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF}, + TRUE, FALSE, FALSE, 30}, + { YCbCr422_12BPC, 2, Interleaved, + {XAVBUF_BUF_12BIT_SF, XAVBUF_BUF_12BIT_SF, XAVBUF_BUF_12BIT_SF}, + TRUE, FALSE, FALSE, 36}, + { YOnly_8BPC, 3, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + TRUE, FALSE, FALSE, 24}, + { YOnly_10BPC, 3, Interleaved, + {XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF}, + TRUE, FALSE, FALSE, 30}, + { YOnly_12BPC, 3, Interleaved, + {XAVBUF_BUF_12BIT_SF, XAVBUF_BUF_12BIT_SF, XAVBUF_BUF_12BIT_SF}, + TRUE, FALSE, FALSE, 36}, + +}; + +/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/Makefile deleted file mode 100644 index 926b20c..0000000 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/Makefile +++ /dev/null
@@ -1,27 +0,0 @@ -COMPILER= -ARCHIVER= -CP=cp -COMPILER_FLAGS= -EXTRA_COMPILER_FLAGS= -LIB=libxil.a - -RELEASEDIR=../../../lib -INCLUDEDIR=../../../include -INCLUDES=-I./. -I${INCLUDEDIR} - -INCLUDEFILES=*.h -LIBSOURCES=*.c -OUTS = *.o - - -libs: - echo "Compiling axipmon" - $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) - $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} - make clean - -include: - ${CP} ${INCLUDEFILES} ${INCLUDEDIR} - -clean: - rm -rf ${OUTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/Makefile new file mode 100644 index 0000000..8c40126 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/Makefile
@@ -0,0 +1,40 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +CC_FLAGS = $(COMPILER_FLAGS) +ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +OUTS = *.o + +LIBSOURCES:=*.c +INCLUDEFILES:=*.h + +OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) + +libs: banner xaxipmon_libs clean + +%.o: %.c + ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< + +banner: + echo "Compiling axipmon" + +xaxipmon_libs: ${OBJECTS} + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} + +.PHONY: include +include: xaxipmon_includes + +xaxipmon_includes: + ${CP} ${INCLUDEFILES} ${INCLUDEDIR} + +clean: + rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/xaxipmon.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/xaxipmon.c index fbb8678..fc5d99f 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/xaxipmon.c
@@ -33,7 +33,7 @@ /** * * @file xaxipmon.c -* @addtogroup axipmon_v6_3 +* @addtogroup axipmon_v6_6 * @{ * * This file contains the driver API functions that can be used to access
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/xaxipmon.h similarity index 98% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/xaxipmon.h index f8d4d64..ea347e0 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/xaxipmon.h
@@ -33,7 +33,7 @@ /** * * @file xaxipmon.h -* @addtogroup axipmon_v6_3 +* @addtogroup axipmon_v6_6 * @{ * @details * @@ -253,6 +253,14 @@ * 6.3 kvn 07/02/15 Modified code according to MISRA-C:2012 guidelines. * 6.4 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425. * Changed the prototype of XAxiPmon_CfgInitialize API. +* 6.5 ms 01/23/17 Modified xil_printf statement in main function for all +* examples to ensure that "Successfully ran" and "Failed" +* strings are available in all examples. This is a fix +* for CR-965028. +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* 6.6 ms 04/18/17 Modified tcl file to add suffix U for all macro +* definitions of axipmon in xparameters.h * </pre> * *****************************************************************************/
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/xaxipmon_g.c similarity index 96% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_g.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/xaxipmon_g.c index 2bd473d..b54becb 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_g.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/xaxipmon_g.c
@@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,7 +44,7 @@ * The configuration table for devices */ -XAxiPmon_Config XAxiPmon_ConfigTable[] = +XAxiPmon_Config XAxiPmon_ConfigTable[XPAR_XAXIPMON_NUM_INSTANCES] = { { XPAR_PSU_APM_0_DEVICE_ID,
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/xaxipmon_hw.h similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_hw.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/xaxipmon_hw.h index 68ed57a..b5d20f5 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_hw.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/xaxipmon_hw.h
@@ -33,7 +33,7 @@ /** * * @file xaxipmon_hw.h -* @addtogroup axipmon_v6_3 +* @addtogroup axipmon_v6_6 * @{ * * This header file contains identifiers and basic driver functions (or
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/xaxipmon_selftest.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_selftest.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/xaxipmon_selftest.c index df2a9da..7a66791 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_selftest.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/xaxipmon_selftest.c
@@ -33,7 +33,7 @@ /** * * @file xaxipmon_selftest.c -* @addtogroup axipmon_v6_3 +* @addtogroup axipmon_v6_6 * @{ * * This file contains a diagnostic self test function for the XAxiPmon driver.
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/xaxipmon_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_sinit.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/xaxipmon_sinit.c index 737d80b..2494aea 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_sinit.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/xaxipmon_sinit.c
@@ -33,7 +33,7 @@ /** * * @file xaxipmon_sinit.c -* @addtogroup axipmon_v6_3 +* @addtogroup axipmon_v6_6 * @{ * * This file contains the implementation of the XAxiPmon driver's static
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps.c index 243b3a8..f852de4 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps.c
@@ -33,7 +33,7 @@ /** * * @file xcanps.c -* @addtogroup canps_v3_0 +* @addtogroup canps_v3_2 * @{ * * Functions in this file are the minimum required functions for the XCanPs
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps.h index b180e37..9feb45e 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps.h
@@ -33,7 +33,7 @@ /** * * @file xcanps.h -* @addtogroup canps_v3_0 +* @addtogroup canps_v3_2 * @{ * @details * @@ -204,6 +204,8 @@ * Data mismatch while sending data less than 8 bytes. * 3.1 nsk 12/21/15 Updated XCanPs_IntrHandler in xcanps_intr.c to handle * error interrupts correctly. CR#925615 +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. * </pre> * ******************************************************************************/
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_g.c index 4063a44..0ed8cd1 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_g.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_g.c
@@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,7 +44,7 @@ * The configuration table for devices */ -XCanPs_Config XCanPs_ConfigTable[] = +XCanPs_Config XCanPs_ConfigTable[XPAR_XCANPS_NUM_INSTANCES] = { { XPAR_PSU_CAN_1_DEVICE_ID,
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_hw.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_hw.c index bbb9612..7ca2f81 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_hw.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_hw.c
@@ -33,7 +33,7 @@ /** * * @file xcanps_hw.c -* @addtogroup canps_v3_0 +* @addtogroup canps_v3_2 * @{ * * This file contains the implementation of the canps interface reset sequence
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_hw.h index 9fe681a..30ec68a 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_hw.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_hw.h
@@ -33,7 +33,7 @@ /** * * @file xcanps_hw.h -* @addtogroup canps_v3_0 +* @addtogroup canps_v3_2 * @{ * * This header file contains the identifiers and basic driver functions (or
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_intr.c index f6721ca..715b35e 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_intr.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_intr.c
@@ -33,7 +33,7 @@ /** * * @file xcanps_intr.c -* @addtogroup canps_v3_0 +* @addtogroup canps_v3_2 * @{ * * This file contains functions related to CAN interrupt handling.
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_selftest.c index 48a6f40..26c9fcb 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_selftest.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_selftest.c
@@ -33,7 +33,7 @@ /** * * @file xcanps_selftest.c -* @addtogroup canps_v3_0 +* @addtogroup canps_v3_2 * @{ * * This file contains a diagnostic self-test function for the XCanPs driver.
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_sinit.c index 230c429..5321669 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_sinit.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_sinit.c
@@ -33,7 +33,7 @@ /** * * @file xcanps_sinit.c -* @addtogroup canps_v3_0 +* @addtogroup canps_v3_2 * @{ * * This file contains the implementation of the XCanPs driver's static
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_3/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_4/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_3/src/Makefile rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_4/src/Makefile
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_3/src/xcoresightpsdcc.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.c similarity index 98% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_3/src/xcoresightpsdcc.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.c index 4bad570..fca26ca 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_3/src/xcoresightpsdcc.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.c
@@ -33,7 +33,7 @@ /** * * @file xcoresightpsdcc.c -* @addtogroup coresightps_dcc_v1_1 +* @addtogroup coresightps_dcc_v1_4 * @{ * * Functions in this file are the minimum required functions for the @@ -132,7 +132,7 @@ ******************************************************************************/ u8 XCoresightPs_DccRecvByte(u32 BaseAddress) { - u8 Data; + u8 Data = 0U; (void) BaseAddress; while (!(XCoresightPs_DccGetStatus() & XCORESIGHTPS_DCC_STATUS_RX)) @@ -169,7 +169,7 @@ ******************************************************************************/ static INLINE u32 XCoresightPs_DccGetStatus(void) { - u32 Status; + u32 Status = 0U; #ifdef __aarch64__ asm volatile ("mrs %0, mdccsr_el0" : "=r" (Status));
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_3/src/xcoresightpsdcc.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.h similarity index 98% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_3/src/xcoresightpsdcc.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.h index a732b23..67959e3 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_3/src/xcoresightpsdcc.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.h
@@ -33,7 +33,7 @@ /** * * @file xcoresightpsdcc.h -* @addtogroup coresightps_dcc_v1_1 +* @addtogroup coresightps_dcc_v1_4 * @{ * @details *
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/cpu_cortexr5_v1_1/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/cpu_cortexr5_v1_4/src/Makefile similarity index 78% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/cpu_cortexr5_v1_1/src/Makefile rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/cpu_cortexr5_v1_4/src/Makefile index 648f83a..7478263 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/cpu_cortexr5_v1_1/src/Makefile +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/cpu_cortexr5_v1_4/src/Makefile
@@ -10,7 +10,7 @@ INCLUDES=-I${INCLUDEDIR} OUTS = *.o - +OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) LIBSOURCES=*.c INCLUDEFILES=*.h @@ -20,3 +20,6 @@ .PHONY: include include: ${CP} $(INCLUDEFILES) $(INCLUDEDIR) + +clean: + rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/cpu_cortexr5_v1_1/src/xcpu_cortexr5.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/cpu_cortexr5_v1_4/src/xcpu_cortexr5.h similarity index 85% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/cpu_cortexr5_v1_1/src/xcpu_cortexr5.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/cpu_cortexr5_v1_4/src/xcpu_cortexr5.h index 7b21dcd..108dc7e 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/cpu_cortexr5_v1_1/src/xcpu_cortexr5.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/cpu_cortexr5_v1_4/src/xcpu_cortexr5.h
@@ -33,11 +33,16 @@ /** * * @file xcpu_cortexr5.h -* @addtogroup cpu_cortexr5_v1_1 +* @addtogroup cpu_cortexr5_v1_4 * @{ * @details * * dummy file +* MODIFICATION HISTORY: * +* Ver Who Date Changes +* ----- ---- -------- --------------------------------------------------------- +* 1.4 ms 04/18/17 Modified tcl file to add suffix U for XPAR_CPU_ID +* parameter of cpu_cortexr5 in xparameters.h ******************************************************************************/ /** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/Makefile rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/Makefile
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/xcsudma.c similarity index 89% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/xcsudma.c index 4ed4dd6..9aa4bee 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/xcsudma.c
@@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2014-2018 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -34,7 +34,7 @@ /** * * @file xcsudma.c -* @addtogroup csudma_v1_0 +* @addtogroup csudma_v1_2 * @{ * * This file contains the implementation of the interface functions for CSU_DMA @@ -191,6 +191,80 @@ /*****************************************************************************/ /** * +* This function sets the starting address and amount(size) of the data to be +* transfered from/to the memory through the AXI interface. +* This function is useful for pmu processor when it wishes to do +* a 64-bit DMA transfer. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* @param AddrLow is a 32 bit variable which holds the starting lower address of +* data which needs to write into the memory(DST) (or read from +* the memory(SRC)). +* @param AddrHigh is a 32 bit variable which holds the higher address of data +* which needs to write into the memory(DST) (or read from +* the memroy(SRC)). +* @param Size is a 32 bit variable which represents the number of 4 byte +* words needs to be transfered from starting address. +* @param EnDataLast is to trigger an end of message. It will enable or +* disable data_inp_last signal to stream interface when current +* command is completed. It is applicable only to source channel +* and neglected for destination channel. +* - 1 - Asserts data_inp_last signal. +* - 0 - data_inp_last will not be asserted. +* +* @return None. +* +* @note Data_inp_last signal is asserted simultaneously with the +* data_inp_valid signal associated with the final 32-bit word +* transfer +* This API won't do flush/invalidation for the DMA buffer. +* It is recommened to call this API only through PMU processor. +* +******************************************************************************/ +void XCsuDma_64BitTransfer(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + u32 AddrLow, u32 AddrHigh, u32 Size, u8 EnDataLast) +{ + /* Verify arguments */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) || + (Channel == (XCSUDMA_DST_CHANNEL))); + Xil_AssertVoid(Size <= (u32)(XCSUDMA_SIZE_MAX)); + Xil_AssertVoid(InstancePtr->IsReady == (u32)(XIL_COMPONENT_IS_READY)); + + + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_ADDR_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), + (AddrLow & XCSUDMA_ADDR_MASK)); + + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_ADDR_MSB_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), + (AddrHigh & XCSUDMA_MSB_ADDR_MASK)); + + if (EnDataLast == (u8)(XCSUDMA_LAST_WORD_MASK)) { + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_SIZE_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), + ((Size << (u32)(XCSUDMA_SIZE_SHIFT)) | + (u32)(XCSUDMA_LAST_WORD_MASK))); + } + else { + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_SIZE_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), + (Size << (u32)(XCSUDMA_SIZE_SHIFT))); + } +} + +/*****************************************************************************/ +/*****************************************************************************/ +/** +* * This function returns the current address location of the memory, from where * it has to read the data(SRC) or the location where it has to write the data * (DST) based on the channel selection.
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/xcsudma.h similarity index 95% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/xcsudma.h index 03a32c1..fc675a1 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/xcsudma.h
@@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2014-2018 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -82,7 +82,7 @@ * to build and link only those parts of the driver that are necessary. * * @file xcsudma.h -* @addtogroup csudma_v1_0 +* @addtogroup csudma_v1_2 * @{ * @details * @@ -99,6 +99,13 @@ * 1.0 vnsld 22/10/14 First release * 1.1 adk 10/05/16 Fixed CR#951040 race condition in the recv path when * source and destination points to the same buffer. +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* ms 04/10/17 Modified filename tag in xcsudma_selftest_example.c to +* include the file in doxygen examples. +* 1.2 adk 11/22/17 Added peripheral test app support for CSUDMA driver. +* adk 09/03/18 Added new API XCsuDma_64BitTransfer() useful for 64-bit +* dma transfers through PMU processor(CR#996201). * </pre> * ******************************************************************************/ @@ -373,6 +380,8 @@ u32 EffectiveAddr); void XCsuDma_Transfer(XCsuDma *InstancePtr, XCsuDma_Channel Channel, UINTPTR Addr, u32 Size, u8 EnDataLast); +void XCsuDma_64BitTransfer(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + u32 AddrLow, u32 AddrHigh, u32 Size, u8 EnDataLast); void XCsuDma_LoopBackTransfer(XCsuDma *InstancePtr, u64 SrcAddr, u64 DstAddr, u32 Size); u64 XCsuDma_GetAddr(XCsuDma *InstancePtr, XCsuDma_Channel Channel);
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/xcsudma_g.c similarity index 93% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_g.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/xcsudma_g.c index 09e7f73..1c2317e 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_g.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/xcsudma_g.c
@@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,7 +44,7 @@ * The configuration table for devices */ -XCsuDma_Config XCsuDma_ConfigTable[] = +XCsuDma_Config XCsuDma_ConfigTable[XPAR_XCSUDMA_NUM_INSTANCES] = { { XPAR_PSU_CSUDMA_DEVICE_ID,
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/xcsudma_hw.h similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_hw.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/xcsudma_hw.h index 6b2c2cd..031c134 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_hw.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/xcsudma_hw.h
@@ -33,7 +33,7 @@ /** * * @file xcsudma_hw.h -* @addtogroup csudma_v1_0 +* @addtogroup csudma_v1_2 * @{ * * This header file contains identifiers and register-level driver functions (or
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/xcsudma_intr.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_intr.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/xcsudma_intr.c index 9f37e45..b45d6cf 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_intr.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/xcsudma_intr.c
@@ -34,7 +34,7 @@ /** * * @file xcsudma_intr.c -* @addtogroup csudma_v1_0 +* @addtogroup csudma_v1_2 * @{ * * This file contains interrupt related functions of Xilinx CSU_DMA core.
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/xcsudma_selftest.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_selftest.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/xcsudma_selftest.c index f61910f..00f35e1 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_selftest.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/xcsudma_selftest.c
@@ -34,7 +34,7 @@ /** * * @file xcsudma_selftest.c -* @addtogroup csudma_v1_0 +* @addtogroup csudma_v1_2 * @{ * * This file contains a diagnostic self-test function for the CSU_DMA driver.
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/xcsudma_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_sinit.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/xcsudma_sinit.c index 10e5c14..be962e2 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_sinit.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/xcsudma_sinit.c
@@ -34,7 +34,7 @@ /** * * @file xcsudma_sinit.c -* @addtogroup csudma_v1_0 +* @addtogroup csudma_v1_2 * @{ * * This file contains static initialization methods for Xilinx CSU_DMA core.
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ddrcpsu_v1_1/src/xddrcpsu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ddrcpsu_v1_1/src/xddrcpsu.h index 2640a94..412f335 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ddrcpsu_v1_1/src/xddrcpsu.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ddrcpsu_v1_1/src/xddrcpsu.h
@@ -18,15 +18,14 @@ * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Except as contained in this notice, the name of the Xilinx shall not be used * in advertising or otherwise to promote the sale, use or other dealings in - * in advertising or otherwise to promote the sale, use or other dealings in * this Software without prior written authorization from Xilinx. * *******************************************************************************/ @@ -34,7 +33,7 @@ /** * * @file xddcrpsu.h - * @addtogroup ddrcpsu_v1_0 + * @addtogroup ddrcpsu_v1_1 * @{ * @details *
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/dpdma_v1_0/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/dpdma_v1_0/src/Makefile new file mode 100644 index 0000000..f5944f9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/dpdma_v1_0/src/Makefile
@@ -0,0 +1,40 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +CC_FLAGS = $(COMPILER_FLAGS) +ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +OUTS = *.o + +LIBSOURCES:=*.c +INCLUDEFILES:=*.h + +OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) + +libs: banner dpdma_libs clean + +%.o: %.c + ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< + +banner: + echo "Compiling dpdma" + +dpdma_libs: ${OBJECTS} + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} + +.PHONY: include +include: dpdma_includes + +dpdma_includes: + ${CP} ${INCLUDEFILES} ${INCLUDEDIR} + +clean: + rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/dpdma_v1_0/src/xdpdma.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/dpdma_v1_0/src/xdpdma.c new file mode 100644 index 0000000..92eaad2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/dpdma_v1_0/src/xdpdma.c
@@ -0,0 +1,966 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* + +*******************************************************************************/ +/*****************************************************************************/ +/** + * + * @file xdpdma.c + * + * This file contains the implementation of the interface functions of the + * XDpDma driver. Refer to xdpdma.h for detailed information. + * + * @note None. + * + * <pre> + * MODIFICATION HISTORY: + * + * Ver Who Date Changes + * ---- ----- -------- ---------------------------------------------------- + * 1.0 aad 04/12/16 Initial release. + * + *****************************************************************************/ + +/***************************** Include Files **********************************/ +#include "xdpdma.h" +#include "xavbuf.h" + +/************************** Constant Definitions ******************************/ +#define XDPDMA_CH_OFFSET 0x100 +#define XDPDMA_WAIT_TIMEOUT 10000 + +#define XDPDMA_AUDIO_ALIGNMENT 128 + +#define XDPDMA_VIDEO_CHANNEL0 0 +#define XDPDMA_VIDEO_CHANNEL1 1 +#define XDPDMA_VIDEO_CHANNEL2 2 +#define XDPDMA_GRAPHICS_CHANNEL 3 +#define XDPDMA_AUDIO_CHANNEL0 4 +#define XDPDMA_AUDIO_CHANNEL1 5 + +#define XDPDMA_DESC_PREAMBLE 0xA5 +#define XDPDMA_DESC_IGNR_DONE 0x400 +#define XDPDMA_DESC_UPDATE 0x200 +#define XDPDMA_DESC_COMP_INTR 0x100 +#define XDPDMA_DESC_LAST_FRAME 0x200000 +#define XDPDMA_DESC_DONE_SHIFT 31 +#define XDPDMA_QOS_MIN 4 +#define XDPDMA_QOS_MAX 11 + +/*************************************************************************/ +/** + * + * This function returns the number of outstanding transactions on a given + * channel. + * + * @param InstancePtr is a pointer to the driver instance. + * @param ChannelNum is the channel number on which the operation is + * being carried out. + * + * @return Number of pending transactions. + * + * @note None. + * + * **************************************************************************/ +static int XDpDma_GetPendingTransaction(XDpDma *InstancePtr, u32 ChannelNum) +{ + u32 RegVal; + RegVal = XDpDma_ReadReg(InstancePtr->Config.BaseAddr, + XDPDMA_CH0_STATUS + 0x100 * ChannelNum); + return (RegVal & XDPDMA_CH_STATUS_OTRAN_CNT_MASK); +} + +/*************************************************************************/ +/** + * + * This function waits until the outstanding transactions are completed. + * + * @param InstancePtr is a pointer to the driver instance. + * @param ChannelNum is the channel number on which the operation is + * being carried out. + * + * @return XST_SUCCESS when all the pending transactions are complete + * before timeout. + * XST_FAILURE if timeout occurs before pending transactions are + * completed. + * + * @note None. + * + * **************************************************************************/ +static int XDpDma_WaitPendingTransaction(XDpDma *InstancePtr, u8 ChannelNum) +{ + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(ChannelNum <= XDPDMA_AUDIO_CHANNEL1); + + u32 Timeout = 0; + u32 Count; + do { + Count = XDpDma_GetPendingTransaction(InstancePtr, ChannelNum); + Timeout++; + } while((Timeout != XDPDMA_WAIT_TIMEOUT) && Count); + + if(Timeout == XDPDMA_WAIT_TIMEOUT) { + return XST_FAILURE; + } + + return XST_SUCCESS; +} + +/*************************************************************************/ +/** + * + * This function controls the hardware channels of the DPDMA. + * + * + * @param InstancePtr is a pointer to the driver instance. + * @param ChannelNum is the physical channel number of the DPDMA. + * @param ChannelState is an enum of type XDpDma_ChannelState. + * + * @return XST_SUCCESS when the mentioned channel is enabled successfully. + * XST_FAILURE when the mentioned channel fails to be enabled. + * + * @note None. + * + * **************************************************************************/ +static int XDpDma_ConfigChannelState(XDpDma *InstancePtr, u8 ChannelNum, + XDpDma_ChannelState Enable) +{ + u32 Mask = 0; + u32 RegVal = 0; + u32 Status = 0; + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(ChannelNum <= XDPDMA_AUDIO_CHANNEL1); + + Mask = XDPDMA_CH_CNTL_EN_MASK | XDPDMA_CH_CNTL_PAUSE_MASK; + switch(Enable) { + case XDPDMA_ENABLE: + RegVal = XDPDMA_CH_CNTL_EN_MASK; + break; + case XDPDMA_DISABLE: + XDpDma_ConfigChannelState(InstancePtr, ChannelNum, + XDPDMA_PAUSE); + Status = XDpDma_WaitPendingTransaction(InstancePtr, + ChannelNum); + if(Status == XST_FAILURE) { + return XST_FAILURE; + } + + RegVal = XDPDMA_DISABLE; + Mask = XDPDMA_CH_CNTL_EN_MASK; + break; + case XDPDMA_IDLE: + Status = XDpDma_ConfigChannelState(InstancePtr, + ChannelNum, + XDPDMA_DISABLE); + if(Status == XST_FAILURE) { + return XST_FAILURE; + } + + RegVal = 0; + break; + case XDPDMA_PAUSE: + RegVal = XDPDMA_PAUSE; + break; + } + XDpDma_ReadModifyWrite(InstancePtr->Config.BaseAddr, + XDPDMA_CH0_CNTL + XDPDMA_CH_OFFSET * ChannelNum, + RegVal, Mask); + return XST_SUCCESS; +} + +/*************************************************************************/ +/** + * + * This function updates the descriptor that is not currently active on a + * Video/Graphics channel. + * + * @param InstancePtr is a pointer to the driver instance. + * @param Channel is a pointer to the channel on which the operation is + * to be carried out. + * + * @return Descriptor for next operation. + * + * @note None. + * + * **************************************************************************/ +static XDpDma_Descriptor *XDpDma_UpdateVideoDescriptor(XDpDma_Channel *Channel) +{ + if(Channel->Current == NULL) { + Channel->Current = &Channel->Descriptor0; + } + else if(Channel->Current == &Channel->Descriptor0) { + Channel->Current = &Channel->Descriptor1; + } + else if(Channel->Current == &Channel->Descriptor1) { + Channel->Current = &Channel->Descriptor0; + } + return Channel->Current; +} + +/*************************************************************************/ +/** + * This function programs the address of the descriptor about to be active + * + * @param InstancePtr is a pointer to the DPDMA instance. + * @param Channel is an enum of the channel for which the descriptor + * address is to be set. + * + * @return Descriptor for next operation. + * + * @note None. + * + * **************************************************************************/ +static void XDpDma_SetDescriptorAddress(XDpDma *InstancePtr, u8 ChannelNum) +{ + u32 AddrOffset; + u32 AddrEOffset; + Xil_AssertVoid(ChannelNum <= XDPDMA_AUDIO_CHANNEL1); + AddrOffset = XDPDMA_CH0_DSCR_STRT_ADDR + + (XDPDMA_CH_OFFSET * ChannelNum); + AddrEOffset = XDPDMA_CH0_DSCR_STRT_ADDRE + + (XDPDMA_CH_OFFSET * ChannelNum); + + XDpDma_Descriptor *Descriptor = NULL; + switch(ChannelNum) { + case XDPDMA_VIDEO_CHANNEL0: + Descriptor = InstancePtr->Video.Channel[ChannelNum].Current; + break; + case XDPDMA_VIDEO_CHANNEL1: + Descriptor = InstancePtr->Video.Channel[ChannelNum].Current; + break; + case XDPDMA_VIDEO_CHANNEL2: + Descriptor = InstancePtr->Video.Channel[ChannelNum].Current; + break; + case XDPDMA_GRAPHICS_CHANNEL: + Descriptor = InstancePtr->Gfx.Channel.Current; + break; + case XDPDMA_AUDIO_CHANNEL0: + Descriptor = InstancePtr->Audio[0].Current; + break; + case XDPDMA_AUDIO_CHANNEL1: + Descriptor = InstancePtr->Audio[1].Current; + break; + } + + XDpDma_WriteReg(InstancePtr->Config.BaseAddr, AddrEOffset, + (INTPTR) Descriptor >> 32); + XDpDma_WriteReg(InstancePtr->Config.BaseAddr, AddrOffset, + (INTPTR) Descriptor); +} + +/*************************************************************************/ +/** + * + * This functions sets the Audio Descriptor for Data Transfer. + * + * @param CurrDesc is a pointer to the descriptor to be initialized + * @param DataSize is the payload size of the buffer to be transferred + * @param BuffAddr is the payload address + * + * @return None. + * + * @note None. + * + * **************************************************************************/ +static void XDpDma_SetupAudioDescriptor(XDpDma_Descriptor *CurrDesc, + u64 DataSize, u64 BuffAddr, + XDpDma_Descriptor *NextDesc) +{ + Xil_AssertVoid(CurrDesc != NULL); + Xil_AssertVoid(DataSize != 0); + Xil_AssertVoid(BuffAddr != 0); + + if(NextDesc == NULL) { + CurrDesc->Control = XDPDMA_DESC_PREAMBLE | + XDPDMA_DESC_UPDATE | XDPDMA_DESC_IGNR_DONE | + XDPDMA_DESC_COMP_INTR; + + } + else { + CurrDesc->Control = XDPDMA_DESC_PREAMBLE | + XDPDMA_DESC_UPDATE | XDPDMA_DESC_IGNR_DONE; + } + CurrDesc->DSCR_ID = 0; + CurrDesc->XFER_SIZE = DataSize; + CurrDesc->LINE_SIZE_STRIDE = 0; + CurrDesc->LSB_Timestamp = 0; + CurrDesc->MSB_Timestamp = 0; + CurrDesc->ADDR_EXT = ((BuffAddr >> XDPDMA_DESCRIPTOR_SRC_ADDR_WIDTH) << + XDPDMA_DESCRIPTOR_ADDR_EXT_SRC_ADDR_EXT_SHIFT) | + ((INTPTR) NextDesc >> + XDPDMA_DESCRIPTOR_NEXT_DESR_WIDTH); + CurrDesc->NEXT_DESR = (INTPTR) NextDesc; + CurrDesc->SRC_ADDR = BuffAddr; +} + +/*************************************************************************/ +/** + * + * This functions retrieves the configuration for this DPDMA driver and + * fills in the InstancePtr->Config structure. + * + * @param InstancePtr is a pointer to the driver instance. + * @param ConfigPtr is a pointer to the configuration structure that will + * be used to copy the settings from. + * + * @return None. + * + * @note None. + * + * **************************************************************************/ +void XDpDma_CfgInitialize(XDpDma *InstancePtr, XDpDma_Config *CfgPtr) +{ + InstancePtr->Config.DeviceId = CfgPtr->DeviceId; + InstancePtr->Config.BaseAddr = CfgPtr->BaseAddr; + + InstancePtr->Video.Channel[XDPDMA_VIDEO_CHANNEL0].Current = NULL; + InstancePtr->Video.Channel[XDPDMA_VIDEO_CHANNEL1].Current = NULL; + InstancePtr->Video.Channel[XDPDMA_VIDEO_CHANNEL2].Current = NULL; + InstancePtr->Video.TriggerStatus = XDPDMA_TRIGGER_DONE; + InstancePtr->Video.VideoInfo = NULL; + InstancePtr->Video.FrameBuffer[XDPDMA_VIDEO_CHANNEL0] = NULL; + InstancePtr->Video.FrameBuffer[XDPDMA_VIDEO_CHANNEL1] = NULL; + InstancePtr->Video.FrameBuffer[XDPDMA_VIDEO_CHANNEL2] = NULL; + + InstancePtr->Gfx.Channel.Current = NULL; + InstancePtr->Gfx.TriggerStatus = XDPDMA_TRIGGER_DONE; + InstancePtr->Gfx.VideoInfo = NULL; + InstancePtr->Gfx.FrameBuffer = NULL; +} + +/*************************************************************************/ +/** + * + * This functions controls the states in which a channel should go into. + * + * @param InstancePtr is a pointer to the driver instance. + * @param ChannelType is an enum of XDpDma_ChannelType. + * @param ChannelState is an enum of type XDpDma_ChannelState. + * + * @return XST_SUCCESS when the mentioned channel is enabled successfully. + * XST_FAILURE when the mentioned channel fails to be enabled. + * + * @note None. + * + * **************************************************************************/ +int XDpDma_SetChannelState(XDpDma *InstancePtr, XDpDma_ChannelType Channel, + XDpDma_ChannelState ChannelState) +{ + u32 Index = 0; + u32 NumPlanes = 0; + u32 Status = 0; + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + + switch(Channel) { + case VideoChan: + if(InstancePtr->Video.VideoInfo == NULL) { + return XST_FAILURE; + } + else { + NumPlanes = InstancePtr->Video.VideoInfo->Mode; + for(Index = 0; Index <= NumPlanes; Index++) { + Status = XDpDma_ConfigChannelState(InstancePtr, + Index, + ChannelState); + if(Status == XST_FAILURE) { + return XST_FAILURE; + } + } + } + break; + case GraphicsChan: + if(InstancePtr->Gfx.VideoInfo == NULL) { + return XST_FAILURE; + } + else { + return XDpDma_ConfigChannelState(InstancePtr, + XDPDMA_GRAPHICS_CHANNEL, + ChannelState); + } + break; + case AudioChan0: + return XDpDma_ConfigChannelState(InstancePtr, + XDPDMA_AUDIO_CHANNEL0, + ChannelState); + break; + case AudioChan1: + return XDpDma_ConfigChannelState(InstancePtr, + XDPDMA_AUDIO_CHANNEL1, + ChannelState); + break; + default: + return XST_FAILURE; + break; + } + + return XST_SUCCESS; +} + +/*************************************************************************/ +/** + * + * This function allocates DPDMA Video Channels depending on the number of + * planes in the video + * + * @param InstancePtr is a pointer to the driver instance. + * @params Format is the video format to be used for the DPDMA transfer + * + * @return XST_SUCCESS, When the format is valid Video Format. + * XST_FAILURE, When the format is not valid Video Format + * + * @note None. + * + * **************************************************************************/ +int XDpDma_SetVideoFormat(XDpDma *InstancePtr, XAVBuf_VideoFormat Format) +{ + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + + InstancePtr->Video.VideoInfo = XAVBuf_GetNLiveVideoAttribute(Format); + if(InstancePtr->Video.VideoInfo == NULL) { + return XST_FAILURE; + } + + return XST_SUCCESS; +} + +/*************************************************************************/ +/** + * + * This function allocates DPDMA Graphics Channels. + * + * @param InstancePtr is a pointer to the driver instance. + * @params Format is the video format to be used for the DPDMA transfer + * + * @return XST_SUCCESS, When the format is a valid Graphics Format. + * XST_FAILURE, When the format is not valid Graphics Format. + * + * @note None. + * + * **************************************************************************/ +int XDpDma_SetGraphicsFormat(XDpDma *InstancePtr, XAVBuf_VideoFormat Format) +{ + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + + InstancePtr->Gfx.VideoInfo = XAVBuf_GetNLGraphicsAttribute(Format); + if(InstancePtr->Gfx.VideoInfo == NULL) { + return XST_FAILURE; + } + + return XST_SUCCESS; +} + +/*************************************************************************/ +/** + * + * This function starts the operation on the a given channel + * + * @param InstancePtr is a pointer to the driver instance. + * @param QOS is the Quality of Service value to be selected. + * + * @return None. + * + * @note . + * + * **************************************************************************/ +void XDpDma_SetQOS(XDpDma *InstancePtr, u8 QOS) +{ + u8 Index; + u32 RegVal = 0; + + Xil_AssertVoid(QOS >= XDPDMA_QOS_MIN && QOS <= XDPDMA_QOS_MAX); + + RegVal = ((QOS << XDPDMA_CH_CNTL_QOS_DATA_RD_SHIFT) | + (QOS << XDPDMA_CH_CNTL_QOS_DSCR_RD_SHIFT) | + (QOS << XDPDMA_CH_CNTL_QOS_DSCR_WR_SHIFT)); + + u32 Mask = XDPDMA_CH_CNTL_QOS_DATA_RD_MASK | + XDPDMA_CH_CNTL_QOS_DSCR_RD_MASK | + XDPDMA_CH_CNTL_QOS_DSCR_WR_MASK; + + for(Index = 0; Index <= XDPDMA_AUDIO_CHANNEL1; Index++) { + XDpDma_ReadModifyWrite(InstancePtr->Config.BaseAddr, + XDPDMA_CH0_CNTL + (XDPDMA_CH_OFFSET * Index), + RegVal, Mask); + } + +} + +/*************************************************************************/ +/** + * + * This function Triggers DPDMA to start the transaction. + * + * @param InstancePtr is a pointer to the XDpDma instance. + * @param Channel is the XDpDma_ChannelType on which the transaction + * is to be triggered. + * + * @return XST_SUCCESS The channel has successfully been Triggered. + * XST_FAILURE When the triggering Video and Graphics channel + * without setting the Video Formats. + * + * @note None. + * + * **************************************************************************/ +int XDpDma_Trigger(XDpDma *InstancePtr, XDpDma_ChannelType Channel) +{ + u32 Trigger = 0; + u8 Index = 0; + u8 NumPlanes = 0; + switch(Channel) { + case VideoChan: + if(InstancePtr->Video.VideoInfo == NULL) { + return XST_FAILURE; + } + else { + NumPlanes = InstancePtr->Video.VideoInfo->Mode; + for(Index = 0; Index <= NumPlanes; Index++) { + Trigger |= XDPDMA_GBL_TRG_CH0_MASK << Index; + InstancePtr->Video.TriggerStatus = + XDPDMA_TRIGGER_DONE; + } + } + break; + case GraphicsChan: + if(InstancePtr->Gfx.VideoInfo == NULL) { + return XST_FAILURE; + } + Trigger = XDPDMA_GBL_TRG_CH3_MASK; + InstancePtr->Gfx.TriggerStatus = XDPDMA_TRIGGER_DONE; + break; + case AudioChan0: + Trigger = XDPDMA_GBL_TRG_CH4_MASK; + InstancePtr->Audio[0].TriggerStatus = XDPDMA_TRIGGER_DONE; + break; + case AudioChan1: + Trigger = XDPDMA_GBL_TRG_CH5_MASK; + InstancePtr->Audio[1].TriggerStatus = XDPDMA_TRIGGER_DONE; + break; + } + XDpDma_WriteReg(InstancePtr->Config.BaseAddr, XDPDMA_GBL, Trigger); + + return XST_SUCCESS; + +} + +/*************************************************************************/ +/** + * + * This function Retriggers DPDMA to fetch data from new descriptor. + * + * @param InstancePtr is a pointer to the XDpDma instance. + * @param Channel is the XDpDma_ChannelType on which the transaction + * is to be retriggered. + * + * @return XST_SUCCESS The channel has successfully been Triggered. + * XST_FAILURE When the triggering Video and Graphics channel + * without setting the Video Formats. + * + * @note None. + * + * **************************************************************************/ +int XDpDma_ReTrigger(XDpDma *InstancePtr, XDpDma_ChannelType Channel) +{ + u32 Trigger = 0; + u8 NumPlanes; + u8 Index; + switch(Channel) { + case VideoChan: + if(InstancePtr->Video.VideoInfo == NULL) { + return XST_FAILURE; + } + else { + NumPlanes = InstancePtr->Video.VideoInfo->Mode; + for(Index = 0; Index <= NumPlanes; Index++) { + Trigger |= XDPDMA_GBL_RTRG_CH0_MASK << Index; + InstancePtr->Video.TriggerStatus = + XDPDMA_RETRIGGER_DONE; + } + } + break; + case GraphicsChan: + if(InstancePtr->Gfx.VideoInfo == NULL) { + return XST_FAILURE; + } + Trigger = XDPDMA_GBL_RTRG_CH3_MASK; + InstancePtr->Gfx.TriggerStatus = XDPDMA_RETRIGGER_DONE; + break; + case AudioChan0: + Trigger = XDPDMA_GBL_RTRG_CH4_MASK; + InstancePtr->Audio[0].TriggerStatus = XDPDMA_RETRIGGER_DONE; + break; + case AudioChan1: + Trigger = XDPDMA_GBL_RTRG_CH5_MASK; + InstancePtr->Audio[1].TriggerStatus = XDPDMA_RETRIGGER_DONE; + break; + } + XDpDma_WriteReg(InstancePtr->Config.BaseAddr, XDPDMA_GBL, Trigger); + + return XST_SUCCESS; +} + +/*************************************************************************/ +/** + * + * This function intializes Video Descriptor for Video and Graphics channel + * + * @param Channel is a pointer to the current Descriptor of Video or + * Graphics Channel. + * @param FrameBuffer is a pointer to the Frame Buffer structure + * + * @return None. + * + * @note None. + * + * **************************************************************************/ +void XDpDma_InitVideoDescriptor(XDpDma_Descriptor *CurrDesc, + XDpDma_FrameBuffer *FrameBuffer) +{ + Xil_AssertVoid(CurrDesc != NULL); + Xil_AssertVoid(FrameBuffer != NULL); + Xil_AssertVoid((FrameBuffer->Stride) % XDPDMA_DESCRIPTOR_ALIGN == 0); + CurrDesc->Control = XDPDMA_DESC_PREAMBLE | XDPDMA_DESC_IGNR_DONE | + XDPDMA_DESC_LAST_FRAME; + CurrDesc->DSCR_ID = 0; + CurrDesc->XFER_SIZE = FrameBuffer->Size; + CurrDesc->LINE_SIZE_STRIDE = ((FrameBuffer->Stride >> 4) << + XDPDMA_DESCRIPTOR_LINE_SIZE_STRIDE_SHIFT) | + (FrameBuffer->LineSize); + CurrDesc->ADDR_EXT = (((FrameBuffer->Address >> + XDPDMA_DESCRIPTOR_SRC_ADDR_WIDTH) << + XDPDMA_DESCRIPTOR_ADDR_EXT_SRC_ADDR_EXT_SHIFT) | + ((INTPTR) CurrDesc >> + XDPDMA_DESCRIPTOR_NEXT_DESR_WIDTH)); + CurrDesc->NEXT_DESR = (INTPTR) CurrDesc; + CurrDesc->SRC_ADDR = FrameBuffer->Address; +} + +/*************************************************************************/ +/** + * + * This function intializes Descriptors for transactions on Audio Channel + * + * @param Channel is a pointer to the XDpDma_AudioChannel instance + * + * @param AudioBuffer is a pointer to the Audio Buffer structure + * + * @return None. + * + * @note None. + * + * **************************************************************************/ +void XDpDma_InitAudioDescriptor(XDpDma_AudioChannel *Channel, + XDpDma_AudioBuffer *AudioBuffer) +{ + u32 Size; + u64 Address; + Xil_AssertVoid(Channel != NULL); + Xil_AssertVoid(AudioBuffer != NULL); + Xil_AssertVoid((AudioBuffer->Size) % XDPDMA_AUDIO_ALIGNMENT == 0); + Xil_AssertVoid((AudioBuffer->Address) % XDPDMA_AUDIO_ALIGNMENT == 0); + + Size = AudioBuffer->Size / 4; + Address = AudioBuffer->Address; + if(Channel->Current == &Channel->Descriptor4) { + XDpDma_SetupAudioDescriptor(&Channel->Descriptor4, Size, + Address, + &Channel->Descriptor5); + XDpDma_SetupAudioDescriptor(&Channel->Descriptor5, Size, + Address + Size, + &Channel->Descriptor6); + XDpDma_SetupAudioDescriptor(&Channel->Descriptor6, Size, + Address + (Size * 2), + &Channel->Descriptor7); + XDpDma_SetupAudioDescriptor(&Channel->Descriptor7, Size, + Address + (Size * 3), NULL); + } + + else if(Channel->Current == &Channel->Descriptor0) { + XDpDma_SetupAudioDescriptor(&Channel->Descriptor0, Size, + Address, + &Channel->Descriptor1); + XDpDma_SetupAudioDescriptor(&Channel->Descriptor1, Size, + Address + Size, + &Channel->Descriptor2); + XDpDma_SetupAudioDescriptor(&Channel->Descriptor2, Size, + Address + (Size * 2), + &Channel->Descriptor3); + XDpDma_SetupAudioDescriptor(&Channel->Descriptor3, Size, + Address + (Size * 3), NULL); + + } +} + +/*************************************************************************/ +/** + * + * This function sets the next Frame Buffers to be displayed on the Video + * Channel. + * + * @param InstancePtr is pointer to the instance of DPDMA. + * @param Plane0 is a pointer to the Frame Buffer structure. + * @param Plane1 is a pointer to the Frame Buffer structure. + * @param Plane2 is a pointer to the Frame Buffer structure. + * + * @return None. + * + * @note For interleaved mode use Plane0. + * For semi-planar mode use Plane0 and Plane1. + * For planar mode use Plane0, Plane1 and Plane2 + * + * **************************************************************************/ +void XDpDma_DisplayVideoFrameBuffer(XDpDma *InstancePtr, + XDpDma_FrameBuffer *Plane0, + XDpDma_FrameBuffer *Plane1, + XDpDma_FrameBuffer *Plane2) +{ + u8 NumPlanes; + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->Video.VideoInfo != NULL); + + NumPlanes = InstancePtr->Video.VideoInfo->Mode; + + switch(NumPlanes) { + case XDPDMA_VIDEO_CHANNEL2: + Xil_AssertVoid(Plane2 != NULL); + InstancePtr->Video.FrameBuffer[XDPDMA_VIDEO_CHANNEL2] = + Plane2; + case XDPDMA_VIDEO_CHANNEL1: + Xil_AssertVoid(Plane1 != NULL); + InstancePtr->Video.FrameBuffer[XDPDMA_VIDEO_CHANNEL1] = + Plane1; + case XDPDMA_VIDEO_CHANNEL0: + Xil_AssertVoid(Plane0 != NULL); + InstancePtr->Video.FrameBuffer[XDPDMA_VIDEO_CHANNEL0] = + Plane0; + break; + } + + if(InstancePtr->Video.Channel[XDPDMA_VIDEO_CHANNEL0].Current == NULL) { + InstancePtr->Video.TriggerStatus = XDPDMA_TRIGGER_EN; + } + else { + InstancePtr->Video.TriggerStatus = XDPDMA_RETRIGGER_EN; + } +} + +/*************************************************************************/ +/** + * + * This function sets the next Frame Buffers to be displayed on the Graphics + * Channel. + * + * @param InstancePtr is pointer to the instance of DPDMA. + * @param Plane is a pointer to the Frame Buffer structure. + * + * @return None. + * + * @note None. + * + **************************************************************************/ +void XDpDma_DisplayGfxFrameBuffer(XDpDma *InstancePtr, + XDpDma_FrameBuffer *Plane) +{ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(Plane != NULL); + + InstancePtr->Gfx.FrameBuffer = Plane; + + if(InstancePtr->Gfx.Channel.Current == NULL) { + InstancePtr->Gfx.TriggerStatus = XDPDMA_TRIGGER_EN; + } + else { + InstancePtr->Gfx.TriggerStatus = XDPDMA_RETRIGGER_EN; + } +} +/*************************************************************************/ +/** + * + * This function sets the next Audio Buffer to be played on Audio Channel 0 + * + * @param InstancePtr is pointer to the instance of DPDMA. + * @param Buffer is a pointer to the attributes of the Audio information + * to be played. + * @param ChannelNum selects between Audio Channel 0 and Audio Channel 1 + * + * @return XST_SUCCESS when the play audio request is successful. + * XST_FAILURE when the play audio request fails, user has to + * retry to play the audio. + * + * @note The user has to schedule new audio buffer before half the audio + * information is consumed by DPDMA to have a seamless playback. + * + **************************************************************************/ +int XDpDma_PlayAudio(XDpDma *InstancePtr, XDpDma_AudioBuffer *Buffer, + u8 ChannelNum) +{ + XDpDma_AudioChannel *Channel; + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(Buffer != NULL); + Xil_AssertNonvoid(Buffer->Size >= 512); + Xil_AssertNonvoid(Buffer->Size % 128 == 0); + Xil_AssertNonvoid(Buffer->Address % 128 == 0); + + Channel = &InstancePtr->Audio[ChannelNum]; + Channel->Buffer = Buffer; + + if(Channel->Current == NULL) { + Channel->TriggerStatus = XDPDMA_TRIGGER_EN; + Channel->Current = &Channel->Descriptor0; + Channel->Used = 0; + } + +else if(Channel->Current == &Channel->Descriptor0) { + /* Check if descriptor chain can be updated */ + if(Channel->Descriptor1.MSB_Timestamp >> + XDPDMA_DESC_DONE_SHIFT) { + Channel->Current = NULL; + return XST_FAILURE; + } + else if(Channel->Descriptor7.MSB_Timestamp >> + XDPDMA_DESC_DONE_SHIFT || !(Channel->Used)) { + Channel->Descriptor3.Control = XDPDMA_DESC_PREAMBLE | + XDPDMA_DESC_UPDATE | XDPDMA_DESC_IGNR_DONE; + Channel->Descriptor3.NEXT_DESR = + (INTPTR) &Channel->Descriptor4; + Channel->Descriptor3.ADDR_EXT &= + ~XDPDMA_DESCRIPTOR_ADDR_EXT_DSC_NXT_MASK; + Channel->Descriptor3.ADDR_EXT |= + (INTPTR) &Channel->Descriptor4 >> 32; + Channel->Current = &Channel->Descriptor4; + Channel->Used = 1; + XDpDma_InitAudioDescriptor(Channel, Buffer); + } + else { + return XST_FAILURE; + } + } + + else if(Channel->Current == &Channel->Descriptor4) { + /* Check if descriptor chain can be updated */ + if(Channel->Descriptor5.MSB_Timestamp >> + XDPDMA_DESC_DONE_SHIFT) { + Channel->Current = NULL; + return XST_FAILURE; + } + else if(Channel->Descriptor3.MSB_Timestamp >> + XDPDMA_DESC_DONE_SHIFT) { + Channel->Descriptor7.Control = XDPDMA_DESC_PREAMBLE | + XDPDMA_DESC_UPDATE | XDPDMA_DESC_IGNR_DONE; + Channel->Descriptor7.NEXT_DESR = + (INTPTR) &Channel->Descriptor0; + Channel->Descriptor7.ADDR_EXT &= + ~XDPDMA_DESCRIPTOR_ADDR_EXT_DSC_NXT_MASK; + Channel->Descriptor7.ADDR_EXT |= + (INTPTR) &Channel->Descriptor0 >> 32; + Channel->Current = &Channel->Descriptor0; + XDpDma_InitAudioDescriptor(Channel, Buffer); + } + else { + return XST_FAILURE; + } + } + + return XST_SUCCESS; + +} +/*************************************************************************/ +/** + * + * This function sets the channel with the latest framebuffer and the + * available descriptor for transfer on the next Vsync. + * + * @param InstancePtr is pointer to the instance of DPDMA. + * @param Channel indicates which channels are being setup for transfer. + * + * @return None. + * + * @note None. + * + **************************************************************************/ +void XDpDma_SetupChannel(XDpDma *InstancePtr, XDpDma_ChannelType Channel) +{ + XDpDma_Channel *Chan; + XDpDma_AudioChannel *AudChan; + XDpDma_FrameBuffer *FB; + XDpDma_AudioBuffer *AudioBuffer; + u8 Index, NumPlanes; + Xil_AssertVoid(InstancePtr != NULL); + + switch(Channel) { + case VideoChan: + Xil_AssertVoid(InstancePtr->Video.VideoInfo != NULL); + Xil_AssertVoid(InstancePtr->Video.FrameBuffer != NULL); + NumPlanes = InstancePtr->Video.VideoInfo->Mode; + for(Index = 0; Index <= NumPlanes; Index++) { + Chan = &InstancePtr->Video.Channel[Index]; + FB = InstancePtr->Video.FrameBuffer[Index]; + XDpDma_UpdateVideoDescriptor(Chan); + XDpDma_InitVideoDescriptor(Chan->Current, FB); + XDpDma_SetDescriptorAddress(InstancePtr, + Index); + } + break; + + case GraphicsChan: + Xil_AssertVoid(InstancePtr->Gfx.VideoInfo != NULL); + Xil_AssertVoid(InstancePtr->Gfx.FrameBuffer != NULL); + Chan = &InstancePtr->Gfx.Channel; + FB = InstancePtr->Gfx.FrameBuffer; + XDpDma_UpdateVideoDescriptor(Chan); + XDpDma_InitVideoDescriptor(Chan->Current, FB); + XDpDma_SetDescriptorAddress(InstancePtr, + XDPDMA_GRAPHICS_CHANNEL); + break; + + case AudioChan0: + Xil_AssertVoid(InstancePtr->Audio[0].Buffer != NULL); + AudChan = &InstancePtr->Audio[0]; + AudioBuffer = InstancePtr->Audio[0].Buffer; + XDpDma_InitAudioDescriptor(AudChan, AudioBuffer); + XDpDma_SetDescriptorAddress(InstancePtr, + XDPDMA_AUDIO_CHANNEL0); + break; + case AudioChan1: + Xil_AssertVoid(InstancePtr->Audio[1].Buffer != NULL); + AudChan = &InstancePtr->Audio[1]; + AudioBuffer = InstancePtr->Audio[1].Buffer; + XDpDma_InitAudioDescriptor(AudChan, AudioBuffer); + XDpDma_SetDescriptorAddress(InstancePtr, + XDPDMA_AUDIO_CHANNEL1); + break; + } +}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/dpdma_v1_0/src/xdpdma.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/dpdma_v1_0/src/xdpdma.h new file mode 100644 index 0000000..95315b0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/dpdma_v1_0/src/xdpdma.h
@@ -0,0 +1,283 @@ +/****************************************************************************** + * + * Copyright (C) 2017 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * + ******************************************************************************/ + +/*****************************************************************************/ +/** + * + * @file xdpdma.h + * + * This file defines the functions implemented by the DPDMA driver present + * in the Zynq Ultrascale MP. + * + * @note None. + * + * <pre> + * MODIFICATION HISTORY: + * + * Ver Who Date Changes + * ---- ----- -------- ---------------------------------------------------- + * 1.0 aad 04/12/16 Initial release. + * + *****************************************************************************/ + + +#ifndef XDPDMA_H_ +/* Prevent circular inclusions by using protection macros. */ +#define XDPDMA_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files **********************************/ + +#include "xdpdma_hw.h" +#include "xvidc.h" +#include "xil_io.h" +#include "xil_assert.h" +#include "xstatus.h" +#include "xavbuf.h" +/************************** Constant Definitions ******************************/ + +/* Alignment for DPDMA Descriptor and Payload */ +#define XDPDMA_DESCRIPTOR_ALIGN 256 +/* DPDMA preamble field */ +#define XDPDMA_DESCRIPTOR_PREAMBLE 0xA5 +/**************************** Type Definitions ********************************/ + +/** + * This typedef describes the DPDMA descriptor structure and its internals + * which will be used when fetching data from a nonlive path + */ +typedef struct { + u32 Control; /**< [7:0] Descriptor Preamble + [8] Enable completion Interrupt + [9] Enable descriptor update + [10] Ignore Done + [11] AXI burst type + [15:12] AXACHE + [17:16] AXPROT + [18] Descriptor mode + [19] Last Descriptor + [20] Enable CRC + [21] Last descriptor frame + [31:22] Reserved */ + u32 DSCR_ID; /**< [15:0] Descriptor ID + [31:16] Reserved */ + u32 XFER_SIZE; /**< Size of transfer in bytes */ + u32 LINE_SIZE_STRIDE; /**< [17:0] Horizontal Resolution + [31:18] Stride */ + u32 LSB_Timestamp; /**< LSB of the Timestamp */ + u32 MSB_Timestamp; /**< MSB of the Timestamp */ + u32 ADDR_EXT; /**< [15:0] Next descriptor + extenstion + [31:16] SRC address extemsion */ + u32 NEXT_DESR; /**< Address of next descriptor */ + u32 SRC_ADDR; /**< Source Address */ + u32 ADDR_EXT_23; /**< [15:0] Address extension for SRC + Address2 + [31:16] Address extension for + SRC Address 3 */ + u32 ADDR_EXT_45; /**< [15:0] Address extension for SRC + Address4 + [31:16] Address extension for + SRC Address 5 */ + u32 SRC_ADDR2; /**< Source address of 2nd page */ + u32 SRC_ADDR3; /**< Source address of 3rd page */ + u32 SRC_ADDR4; /**< Source address of 4th page */ + u32 SRC_ADDR5; /**< Source address of 5th page */ + u32 CRC; /**< Reserved */ + +} XDpDma_Descriptor __attribute__ ((aligned(XDPDMA_DESCRIPTOR_ALIGN))); + +/** + * This typedef contains configuration information for the DPDMA. + */ +typedef struct { + u16 DeviceId; /**< Device ID */ + u32 BaseAddr; /**< Base Address */ +} XDpDma_Config; + +/** + * The following data structure enumerates the types of + * DPDMA channels + */ +typedef enum { + VideoChan, + GraphicsChan, + AudioChan0, + AudioChan1, +} XDpDma_ChannelType; + +/** + * This typedef lists the channel status. + */ +typedef enum { + XDPDMA_DISABLE, + XDPDMA_ENABLE, + XDPDMA_IDLE, + XDPDMA_PAUSE +} XDpDma_ChannelState; + +/** + * This typedef is the information needed to transfer video info. + */ +typedef struct { + u64 Address; + u32 Size; + u32 Stride; + u32 LineSize; +} XDpDma_FrameBuffer; +/** + * This typedef is the information needed to transfer audio info. + */ +typedef struct { + u64 Address; + u64 Size; +} XDpDma_AudioBuffer; + +/** + * This typedef defines the Video/Graphics Channel attributes. + */ +typedef struct { + XDpDma_Descriptor Descriptor0; + XDpDma_Descriptor Descriptor1; + XDpDma_Descriptor *Current; +} XDpDma_Channel; + +/** + * This typedef defines the Video Channel attributes. + */ +typedef struct { + XDpDma_Channel Channel[3]; + u8 TriggerStatus; + u8 AVBufEn; + XAVBuf_VideoAttribute *VideoInfo; + XDpDma_FrameBuffer *FrameBuffer[3]; +} XDpDma_VideoChannel; + +/** + * This typedef defines the Graphics Channel attributes. + */ +typedef struct { + XDpDma_Channel Channel; + u8 TriggerStatus; + u8 AVBufEn; + XAVBuf_VideoAttribute *VideoInfo; + XDpDma_FrameBuffer *FrameBuffer; +} XDpDma_GfxChannel; + +/** + * This typedef defines the Audio Channel attributes. + */ +typedef struct { + XDpDma_Descriptor Descriptor0, Descriptor1, Descriptor2; + XDpDma_Descriptor Descriptor3, Descriptor4, Descriptor5; + XDpDma_Descriptor Descriptor6, Descriptor7; + XDpDma_Descriptor *Current; + u8 TriggerStatus; + XDpDma_AudioBuffer *Buffer; + u8 Used; +} XDpDma_AudioChannel; +/*************************************************************************/ +/** + * This callback type represents the handler for a DPDMA VSync interrupt. + * + * @param InstancePtr is a pointer to the XDpDma instance. + * + * @note None. + * +**************************************************************************/ +typedef void (*XDpDma_VSyncInterruptHandler)(void *InstancePtr); + +/*************************************************************************/ +/** + * This callback type represents the handler for a DPDMA Done interrupt. + * + * @param InstancePtr is a pointer to the XDpDma instance. + * + * @note None. + * +**************************************************************************/ +typedef void (*XDpDma_DoneInterruptHandler)(void *InstancePtr); + +/** + * The XDpDma driver instance data representing the DPDMA operation. + */ +typedef struct { + XDpDma_Config Config; + XDpDma_VideoChannel Video; + XDpDma_GfxChannel Gfx; + XDpDma_AudioChannel Audio[2]; + XVidC_VideoTiming *Timing; + u8 QOS; + + XDpDma_VSyncInterruptHandler VSyncHandler; + void * VSyncInterruptHandler; + + XDpDma_DoneInterruptHandler DoneHandler; + void * DoneInterruptHandler; + +} XDpDma; + +void XDpDma_CfgInitialize(XDpDma *InstancePtr, XDpDma_Config *CfgPtr); +XDpDma_Config *XDpDma_LookupConfig(u16 DeviceId); +int XDpDma_SetChannelState(XDpDma *InstancePtr, XDpDma_ChannelType Channel, + XDpDma_ChannelState ChannelState); +void XDpDma_SetQOS(XDpDma *InstancePtr, u8 QOS); +void XDpDma_SetupChannel(XDpDma *InstancePtr, XDpDma_ChannelType Channel); +int XDpDma_SetVideoFormat(XDpDma *InstancePtr, XAVBuf_VideoFormat Format); +int XDpDma_SetGraphicsFormat(XDpDma *InstancePtr, XAVBuf_VideoFormat Format); +void XDpDma_SetVideoTiming(XDpDma *InstancePtr, XVidC_VideoTiming *Timing); +int XDpDma_Trigger(XDpDma *InstancePtr, XDpDma_ChannelType Channel); +int XDpDma_ReTrigger(XDpDma *InstancePtr, XDpDma_ChannelType Channel); +void XDpDma_InterruptEnable(XDpDma *InstancePtr, u32 Mask); +void XDpDma_InterruptHandler(XDpDma *InstancePtr); +void XDpDma_VSyncHandler(XDpDma *InstancePtr); +void XDpDma_DoneHandler(XDpDma *InstancePtr); +void XDpDma_InitVideoDescriptor(XDpDma_Descriptor *CurrDesc, + XDpDma_FrameBuffer *FrameBuffer); +void XDpDma_DisplayVideoFrameBuffer(XDpDma *InstancePtr, + XDpDma_FrameBuffer *Plane1, + XDpDma_FrameBuffer *Plane2, + XDpDma_FrameBuffer *Plane3); +void XDpDma_DisplayGfxFrameBuffer(XDpDma *InstancePtr, + XDpDma_FrameBuffer *Plane); +void XDpDma_InitAudioDescriptor(XDpDma_AudioChannel *Channel, + XDpDma_AudioBuffer *AudioBuffer); +int XDpDma_PlayAudio(XDpDma *InstancePtr, XDpDma_AudioBuffer *Buffer, + u8 ChannelNum); +#ifdef __cplusplus +} +#endif + +#endif /* _XDPDMA_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/dpdma_v1_0/src/xdpdma_g.c similarity index 89% copy from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_g.c copy to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/dpdma_v1_0/src/xdpdma_g.c index 5913cd8..5bedc6c 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_g.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/dpdma_v1_0/src/xdpdma_g.c
@@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -38,17 +38,17 @@ *******************************************************************/ #include "xparameters.h" -#include "xrtcpsu.h" +#include "xdpdma.h" /* * The configuration table for devices */ -XRtcPsu_Config XRtcPsu_ConfigTable[] = +XDpDma_Config XDpDma_ConfigTable[XPAR_XDPDMA_NUM_INSTANCES] = { { - XPAR_PSU_RTC_DEVICE_ID, - XPAR_PSU_RTC_BASEADDR + XPAR_PSU_DPDMA_DEVICE_ID, + XPAR_PSU_DPDMA_BASEADDR } };
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/dpdma_v1_0/src/xdpdma_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/dpdma_v1_0/src/xdpdma_hw.h new file mode 100644 index 0000000..14ebce2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/dpdma_v1_0/src/xdpdma_hw.h
@@ -0,0 +1,1811 @@ +/****************************************************************************** + * + * Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * + ******************************************************************************/ + +/*****************************************************************************/ +/** + * + * @file xdpdma_hw.h + * + * This header file contains identifiers and low-level driver functions (or + * macros) that can be used to access the device. High-level driver functions + * are defined in xdpdma.h + * + * @note None. + * + * <pre> + * MODIFICATION HISTORY: + * + * Ver Who Date Changes + * ---- ----- -------- ---------------------------------------------------- + * 1.0 aad 04/12/16 Initial release. + * + *****************************************************************************/ + + +#ifndef XDPDMAHW_H_ +/* Prevent circular inclusions by using protection macros. */ +#define XDPDMAHW_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files **********************************/ + +#include "xil_io.h" + +/************************** Constant Definitions ******************************/ + +/******************************************************************************/ +/** + * Address mapping for the DPDMA. + */ +/******************************************************************************/ +/** @name DPDMA registers + * @{ + */ + +#define XDPDMA_BASEADDR 0XFD4C0000 + +/** + * Register: XDPDMA_ERR_CTRL + */ +#define XDPDMA_ERR_CTRL 0X0000 + +#define XDPDMA_ERR_CTRL_APB_ERR_RES_SHIFT 0 +#define XDPDMA_ERR_CTRL_APB_ERR_RES_WIDTH 1 +#define XDPDMA_ERR_CTRL_APB_ERR_RES_MASK 0X1 + +/** + * Register: XDPDMA_ISR + */ +#define XDPDMA_ISR 0X0004 + +#define XDPDMA_ISR_VSYNC_INT_SHIFT 27 +#define XDPDMA_ISR_VSYNC_INT_WIDTH 1 +#define XDPDMA_ISR_VSYNC_INT_MASK 0X08000000 + +#define XDPDMA_ISR_AXI_RD_4K_CROSS_SHIFT 26 +#define XDPDMA_ISR_AXI_RD_4K_CROSS_WIDTH 1 +#define XDPDMA_ISR_AXI_RD_4K_CROSS_MASK 0X04000000 + +#define XDPDMA_ISR_WR_DATA_FIFO_FULL_SHIFT 25 +#define XDPDMA_ISR_WR_DATA_FIFO_FULL_WIDTH 1 +#define XDPDMA_ISR_WR_DATA_FIFO_FULL_MASK 0X02000000 + +#define XDPDMA_ISR_WR_CMD_FIFO_FULL_SHIFT 24 +#define XDPDMA_ISR_WR_CMD_FIFO_FULL_WIDTH 1 +#define XDPDMA_ISR_WR_CMD_FIFO_FULL_MASK 0X01000000 + +#define XDPDMA_ISR_DSCR_ERR5_SHIFT 23 +#define XDPDMA_ISR_DSCR_ERR5_WIDTH 1 +#define XDPDMA_ISR_DSCR_ERR5_MASK 0X800000 + +#define XDPDMA_ISR_DSCR_ERR4_SHIFT 22 +#define XDPDMA_ISR_DSCR_ERR4_WIDTH 1 +#define XDPDMA_ISR_DSCR_ERR4_MASK 0X400000 + +#define XDPDMA_ISR_DSCR_ERR3_SHIFT 21 +#define XDPDMA_ISR_DSCR_ERR3_WIDTH 1 +#define XDPDMA_ISR_DSCR_ERR3_MASK 0X200000 + +#define XDPDMA_ISR_DSCR_ERR2_SHIFT 20 +#define XDPDMA_ISR_DSCR_ERR2_WIDTH 1 +#define XDPDMA_ISR_DSCR_ERR2_MASK 0X100000 + +#define XDPDMA_ISR_DSCR_ERR1_SHIFT 19 +#define XDPDMA_ISR_DSCR_ERR1_WIDTH 1 +#define XDPDMA_ISR_DSCR_ERR1_MASK 0X80000 + +#define XDPDMA_ISR_DSCR_ERR0_SHIFT 18 +#define XDPDMA_ISR_DSCR_ERR0_WIDTH 1 +#define XDPDMA_ISR_DSCR_ERR0_MASK 0X40000 + +#define XDPDMA_ISR_DATA_AXI_ERR5_SHIFT 17 +#define XDPDMA_ISR_DATA_AXI_ERR5_WIDTH 1 +#define XDPDMA_ISR_DATA_AXI_ERR5_MASK 0X20000 + +#define XDPDMA_ISR_DATA_AXI_ERR4_SHIFT 16 +#define XDPDMA_ISR_DATA_AXI_ERR4_WIDTH 1 +#define XDPDMA_ISR_DATA_AXI_ERR4_MASK 0X10000 + +#define XDPDMA_ISR_DATA_AXI_ERR3_SHIFT 15 +#define XDPDMA_ISR_DATA_AXI_ERR3_WIDTH 1 +#define XDPDMA_ISR_DATA_AXI_ERR3_MASK 0X8000 + +#define XDPDMA_ISR_DATA_AXI_ERR2_SHIFT 14 +#define XDPDMA_ISR_DATA_AXI_ERR2_WIDTH 1 +#define XDPDMA_ISR_DATA_AXI_ERR2_MASK 0X4000 + +#define XDPDMA_ISR_DATA_AXI_ERR1_SHIFT 13 +#define XDPDMA_ISR_DATA_AXI_ERR1_WIDTH 1 +#define XDPDMA_ISR_DATA_AXI_ERR1_MASK 0X2000 + +#define XDPDMA_ISR_DATA_AXI_ERR0_SHIFT 12 +#define XDPDMA_ISR_DATA_AXI_ERR0_WIDTH 1 +#define XDPDMA_ISR_DATA_AXI_ERR0_MASK 0X1000 + +#define XDPDMA_ISR_NO_OSTAND_TRAN5_SHIFT 11 +#define XDPDMA_ISR_NO_OSTAND_TRAN5_WIDTH 1 +#define XDPDMA_ISR_NO_OSTAND_TRAN5_MASK 0X0800 + +#define XDPDMA_ISR_NO_OSTAND_TRAN4_SHIFT 10 +#define XDPDMA_ISR_NO_OSTAND_TRAN4_WIDTH 1 +#define XDPDMA_ISR_NO_OSTAND_TRAN4_MASK 0X0400 + +#define XDPDMA_ISR_NO_OSTAND_TRAN3_SHIFT 9 +#define XDPDMA_ISR_NO_OSTAND_TRAN3_WIDTH 1 +#define XDPDMA_ISR_NO_OSTAND_TRAN3_MASK 0X0200 + +#define XDPDMA_ISR_NO_OSTAND_TRAN2_SHIFT 8 +#define XDPDMA_ISR_NO_OSTAND_TRAN2_WIDTH 1 +#define XDPDMA_ISR_NO_OSTAND_TRAN2_MASK 0X0100 + +#define XDPDMA_ISR_NO_OSTAND_TRAN1_SHIFT 7 +#define XDPDMA_ISR_NO_OSTAND_TRAN1_WIDTH 1 +#define XDPDMA_ISR_NO_OSTAND_TRAN1_MASK 0X80 + +#define XDPDMA_ISR_NO_OSTAND_TRAN0_SHIFT 6 +#define XDPDMA_ISR_NO_OSTAND_TRAN0_WIDTH 1 +#define XDPDMA_ISR_NO_OSTAND_TRAN0_MASK 0X40 + +#define XDPDMA_ISR_DSCR_DONE5_SHIFT 5 +#define XDPDMA_ISR_DSCR_DONE5_WIDTH 1 +#define XDPDMA_ISR_DSCR_DONE5_MASK 0X20 + +#define XDPDMA_ISR_DSCR_DONE4_SHIFT 4 +#define XDPDMA_ISR_DSCR_DONE4_WIDTH 1 +#define XDPDMA_ISR_DSCR_DONE4_MASK 0X10 + +#define XDPDMA_ISR_DSCR_DONE3_SHIFT 3 +#define XDPDMA_ISR_DSCR_DONE3_WIDTH 1 +#define XDPDMA_ISR_DSCR_DONE3_MASK 0X8 + +#define XDPDMA_ISR_DSCR_DONE2_SHIFT 2 +#define XDPDMA_ISR_DSCR_DONE2_WIDTH 1 +#define XDPDMA_ISR_DSCR_DONE2_MASK 0X4 + +#define XDPDMA_ISR_DSCR_DONE1_SHIFT 1 +#define XDPDMA_ISR_DSCR_DONE1_WIDTH 1 +#define XDPDMA_ISR_DSCR_DONE1_MASK 0X2 + +#define XDPDMA_ISR_DSCR_DONE0_SHIFT 0 +#define XDPDMA_ISR_DSCR_DONE0_WIDTH 1 +#define XDPDMA_ISR_DSCR_DONE0_MASK 0X1 + +/** + * Register: XDPDMA_IMR + */ +#define XDPDMA_IMR 0X0008 + +#define XDPDMA_IMR_VSYNC_INT_SHIFT 27 +#define XDPDMA_IMR_VSYNC_INT_WIDTH 1 +#define XDPDMA_IMR_VSYNC_INT_MASK 0X08000000 + +#define XDPDMA_IMR_AXI_RD_4K_CROSS_SHIFT 26 +#define XDPDMA_IMR_AXI_RD_4K_CROSS_WIDTH 1 +#define XDPDMA_IMR_AXI_RD_4K_CROSS_MASK 0X04000000 + +#define XDPDMA_IMR_WR_DATA_FIFO_FULL_SHIFT 25 +#define XDPDMA_IMR_WR_DATA_FIFO_FULL_WIDTH 1 +#define XDPDMA_IMR_WR_DATA_FIFO_FULL_MASK 0X02000000 + +#define XDPDMA_IMR_WR_CMD_FIFO_FULL_SHIFT 24 +#define XDPDMA_IMR_WR_CMD_FIFO_FULL_WIDTH 1 +#define XDPDMA_IMR_WR_CMD_FIFO_FULL_MASK 0X01000000 + +#define XDPDMA_IMR_DSCR_ERR5_SHIFT 23 +#define XDPDMA_IMR_DSCR_ERR5_WIDTH 1 +#define XDPDMA_IMR_DSCR_ERR5_MASK 0X800000 + +#define XDPDMA_IMR_DSCR_ERR4_SHIFT 22 +#define XDPDMA_IMR_DSCR_ERR4_WIDTH 1 +#define XDPDMA_IMR_DSCR_ERR4_MASK 0X400000 + +#define XDPDMA_IMR_DSCR_ERR3_SHIFT 21 +#define XDPDMA_IMR_DSCR_ERR3_WIDTH 1 +#define XDPDMA_IMR_DSCR_ERR3_MASK 0X200000 + +#define XDPDMA_IMR_DSCR_ERR2_SHIFT 20 +#define XDPDMA_IMR_DSCR_ERR2_WIDTH 1 +#define XDPDMA_IMR_DSCR_ERR2_MASK 0X100000 + +#define XDPDMA_IMR_DSCR_ERR1_SHIFT 19 +#define XDPDMA_IMR_DSCR_ERR1_WIDTH 1 +#define XDPDMA_IMR_DSCR_ERR1_MASK 0X80000 + +#define XDPDMA_IMR_DSCR_ERR0_SHIFT 18 +#define XDPDMA_IMR_DSCR_ERR0_WIDTH 1 +#define XDPDMA_IMR_DSCR_ERR0_MASK 0X40000 + +#define XDPDMA_IMR_DATA_AXI_ERR5_SHIFT 17 +#define XDPDMA_IMR_DATA_AXI_ERR5_WIDTH 1 +#define XDPDMA_IMR_DATA_AXI_ERR5_MASK 0X20000 + +#define XDPDMA_IMR_DATA_AXI_ERR4_SHIFT 16 +#define XDPDMA_IMR_DATA_AXI_ERR4_WIDTH 1 +#define XDPDMA_IMR_DATA_AXI_ERR4_MASK 0X10000 + +#define XDPDMA_IMR_DATA_AXI_ERR3_SHIFT 15 +#define XDPDMA_IMR_DATA_AXI_ERR3_WIDTH 1 +#define XDPDMA_IMR_DATA_AXI_ERR3_MASK 0X8000 + +#define XDPDMA_IMR_DATA_AXI_ERR2_SHIFT 14 +#define XDPDMA_IMR_DATA_AXI_ERR2_WIDTH 1 +#define XDPDMA_IMR_DATA_AXI_ERR2_MASK 0X4000 + +#define XDPDMA_IMR_DATA_AXI_ERR1_SHIFT 13 +#define XDPDMA_IMR_DATA_AXI_ERR1_WIDTH 1 +#define XDPDMA_IMR_DATA_AXI_ERR1_MASK 0X2000 + +#define XDPDMA_IMR_DATA_AXI_ERR0_SHIFT 12 +#define XDPDMA_IMR_DATA_AXI_ERR0_WIDTH 1 +#define XDPDMA_IMR_DATA_AXI_ERR0_MASK 0X1000 + +#define XDPDMA_IMR_NO_OSTAND_TRAN5_SHIFT 11 +#define XDPDMA_IMR_NO_OSTAND_TRAN5_WIDTH 1 +#define XDPDMA_IMR_NO_OSTAND_TRAN5_MASK 0X0800 + +#define XDPDMA_IMR_NO_OSTAND_TRAN4_SHIFT 10 +#define XDPDMA_IMR_NO_OSTAND_TRAN4_WIDTH 1 +#define XDPDMA_IMR_NO_OSTAND_TRAN4_MASK 0X0400 + +#define XDPDMA_IMR_NO_OSTAND_TRAN3_SHIFT 9 +#define XDPDMA_IMR_NO_OSTAND_TRAN3_WIDTH 1 +#define XDPDMA_IMR_NO_OSTAND_TRAN3_MASK 0X0200 + +#define XDPDMA_IMR_NO_OSTAND_TRAN2_SHIFT 8 +#define XDPDMA_IMR_NO_OSTAND_TRAN2_WIDTH 1 +#define XDPDMA_IMR_NO_OSTAND_TRAN2_MASK 0X0100 + +#define XDPDMA_IMR_NO_OSTAND_TRAN1_SHIFT 7 +#define XDPDMA_IMR_NO_OSTAND_TRAN1_WIDTH 1 +#define XDPDMA_IMR_NO_OSTAND_TRAN1_MASK 0X80 + +#define XDPDMA_IMR_NO_OSTAND_TRAN0_SHIFT 6 +#define XDPDMA_IMR_NO_OSTAND_TRAN0_WIDTH 1 +#define XDPDMA_IMR_NO_OSTAND_TRAN0_MASK 0X40 + +#define XDPDMA_IMR_DSCR_DONE5_SHIFT 5 +#define XDPDMA_IMR_DSCR_DONE5_WIDTH 1 +#define XDPDMA_IMR_DSCR_DONE5_MASK 0X20 + +#define XDPDMA_IMR_DSCR_DONE4_SHIFT 4 +#define XDPDMA_IMR_DSCR_DONE4_WIDTH 1 +#define XDPDMA_IMR_DSCR_DONE4_MASK 0X10 + +#define XDPDMA_IMR_DSCR_DONE3_SHIFT 3 +#define XDPDMA_IMR_DSCR_DONE3_WIDTH 1 +#define XDPDMA_IMR_DSCR_DONE3_MASK 0X8 + +#define XDPDMA_IMR_DSCR_DONE2_SHIFT 2 +#define XDPDMA_IMR_DSCR_DONE2_WIDTH 1 +#define XDPDMA_IMR_DSCR_DONE2_MASK 0X4 + +#define XDPDMA_IMR_DSCR_DONE1_SHIFT 1 +#define XDPDMA_IMR_DSCR_DONE1_WIDTH 1 +#define XDPDMA_IMR_DSCR_DONE1_MASK 0X2 + +#define XDPDMA_IMR_DSCR_DONE0_SHIFT 0 +#define XDPDMA_IMR_DSCR_DONE0_WIDTH 1 +#define XDPDMA_IMR_DSCR_DONE0_MASK 0X1 + +/** + * Register: XDPDMA_IEN + */ +#define XDPDMA_IEN 0X000C + +#define XDPDMA_IEN_VSYNC_INT_SHIFT 27 +#define XDPDMA_IEN_VSYNC_INT_WIDTH 1 +#define XDPDMA_IEN_VSYNC_INT_MASK 0X08000000 + +#define XDPDMA_IEN_AXI_RD_4K_CROSS_SHIFT 26 +#define XDPDMA_IEN_AXI_RD_4K_CROSS_WIDTH 1 +#define XDPDMA_IEN_AXI_RD_4K_CROSS_MASK 0X04000000 + +#define XDPDMA_IEN_WR_DATA_FIFO_FULL_SHIFT 25 +#define XDPDMA_IEN_WR_DATA_FIFO_FULL_WIDTH 1 +#define XDPDMA_IEN_WR_DATA_FIFO_FULL_MASK 0X02000000 + +#define XDPDMA_IEN_WR_CMD_FIFO_FULL_SHIFT 24 +#define XDPDMA_IEN_WR_CMD_FIFO_FULL_WIDTH 1 +#define XDPDMA_IEN_WR_CMD_FIFO_FULL_MASK 0X01000000 + +#define XDPDMA_IEN_DSCR_ERR5_SHIFT 23 +#define XDPDMA_IEN_DSCR_ERR5_WIDTH 1 +#define XDPDMA_IEN_DSCR_ERR5_MASK 0X800000 + +#define XDPDMA_IEN_DSCR_ERR4_SHIFT 22 +#define XDPDMA_IEN_DSCR_ERR4_WIDTH 1 +#define XDPDMA_IEN_DSCR_ERR4_MASK 0X400000 + +#define XDPDMA_IEN_DSCR_ERR3_SHIFT 21 +#define XDPDMA_IEN_DSCR_ERR3_WIDTH 1 +#define XDPDMA_IEN_DSCR_ERR3_MASK 0X200000 + +#define XDPDMA_IEN_DSCR_ERR2_SHIFT 20 +#define XDPDMA_IEN_DSCR_ERR2_WIDTH 1 +#define XDPDMA_IEN_DSCR_ERR2_MASK 0X100000 + +#define XDPDMA_IEN_DSCR_ERR1_SHIFT 19 +#define XDPDMA_IEN_DSCR_ERR1_WIDTH 1 +#define XDPDMA_IEN_DSCR_ERR1_MASK 0X80000 + +#define XDPDMA_IEN_DSCR_ERR0_SHIFT 18 +#define XDPDMA_IEN_DSCR_ERR0_WIDTH 1 +#define XDPDMA_IEN_DSCR_ERR0_MASK 0X40000 + +#define XDPDMA_IEN_DATA_AXI_ERR5_SHIFT 17 +#define XDPDMA_IEN_DATA_AXI_ERR5_WIDTH 1 +#define XDPDMA_IEN_DATA_AXI_ERR5_MASK 0X20000 + +#define XDPDMA_IEN_DATA_AXI_ERR4_SHIFT 16 +#define XDPDMA_IEN_DATA_AXI_ERR4_WIDTH 1 +#define XDPDMA_IEN_DATA_AXI_ERR4_MASK 0X10000 + +#define XDPDMA_IEN_DATA_AXI_ERR3_SHIFT 15 +#define XDPDMA_IEN_DATA_AXI_ERR3_WIDTH 1 +#define XDPDMA_IEN_DATA_AXI_ERR3_MASK 0X8000 + +#define XDPDMA_IEN_DATA_AXI_ERR2_SHIFT 14 +#define XDPDMA_IEN_DATA_AXI_ERR2_WIDTH 1 +#define XDPDMA_IEN_DATA_AXI_ERR2_MASK 0X4000 + +#define XDPDMA_IEN_DATA_AXI_ERR1_SHIFT 13 +#define XDPDMA_IEN_DATA_AXI_ERR1_WIDTH 1 +#define XDPDMA_IEN_DATA_AXI_ERR1_MASK 0X2000 + +#define XDPDMA_IEN_DATA_AXI_ERR0_SHIFT 12 +#define XDPDMA_IEN_DATA_AXI_ERR0_WIDTH 1 +#define XDPDMA_IEN_DATA_AXI_ERR0_MASK 0X1000 + +#define XDPDMA_IEN_NO_OSTAND_TRAN5_SHIFT 11 +#define XDPDMA_IEN_NO_OSTAND_TRAN5_WIDTH 1 +#define XDPDMA_IEN_NO_OSTAND_TRAN5_MASK 0X0800 + +#define XDPDMA_IEN_NO_OSTAND_TRAN4_SHIFT 10 +#define XDPDMA_IEN_NO_OSTAND_TRAN4_WIDTH 1 +#define XDPDMA_IEN_NO_OSTAND_TRAN4_MASK 0X0400 + +#define XDPDMA_IEN_NO_OSTAND_TRAN3_SHIFT 9 +#define XDPDMA_IEN_NO_OSTAND_TRAN3_WIDTH 1 +#define XDPDMA_IEN_NO_OSTAND_TRAN3_MASK 0X0200 + +#define XDPDMA_IEN_NO_OSTAND_TRAN2_SHIFT 8 +#define XDPDMA_IEN_NO_OSTAND_TRAN2_WIDTH 1 +#define XDPDMA_IEN_NO_OSTAND_TRAN2_MASK 0X0100 + +#define XDPDMA_IEN_NO_OSTAND_TRAN1_SHIFT 7 +#define XDPDMA_IEN_NO_OSTAND_TRAN1_WIDTH 1 +#define XDPDMA_IEN_NO_OSTAND_TRAN1_MASK 0X80 + +#define XDPDMA_IEN_NO_OSTAND_TRAN0_SHIFT 6 +#define XDPDMA_IEN_NO_OSTAND_TRAN0_WIDTH 1 +#define XDPDMA_IEN_NO_OSTAND_TRAN0_MASK 0X40 + +#define XDPDMA_IEN_DSCR_DONE5_SHIFT 5 +#define XDPDMA_IEN_DSCR_DONE5_WIDTH 1 +#define XDPDMA_IEN_DSCR_DONE5_MASK 0X20 + +#define XDPDMA_IEN_DSCR_DONE4_SHIFT 4 +#define XDPDMA_IEN_DSCR_DONE4_WIDTH 1 +#define XDPDMA_IEN_DSCR_DONE4_MASK 0X10 + +#define XDPDMA_IEN_DSCR_DONE3_SHIFT 3 +#define XDPDMA_IEN_DSCR_DONE3_WIDTH 1 +#define XDPDMA_IEN_DSCR_DONE3_MASK 0X8 + +#define XDPDMA_IEN_DSCR_DONE2_SHIFT 2 +#define XDPDMA_IEN_DSCR_DONE2_WIDTH 1 +#define XDPDMA_IEN_DSCR_DONE2_MASK 0X4 + +#define XDPDMA_IEN_DSCR_DONE1_SHIFT 1 +#define XDPDMA_IEN_DSCR_DONE1_WIDTH 1 +#define XDPDMA_IEN_DSCR_DONE1_MASK 0X2 + +#define XDPDMA_IEN_DSCR_DONE0_SHIFT 0 +#define XDPDMA_IEN_DSCR_DONE0_WIDTH 1 +#define XDPDMA_IEN_DSCR_DONE0_MASK 0X1 + +/** + * Register: XDPDMA_IDS + */ +#define XDPDMA_IDS 0X0010 + +#define XDPDMA_IDS_VSYNC_INT_SHIFT 27 +#define XDPDMA_IDS_VSYNC_INT_WIDTH 1 +#define XDPDMA_IDS_VSYNC_INT_MASK 0X08000000 + +#define XDPDMA_IDS_AXI_RD_4K_CROSS_SHIFT 26 +#define XDPDMA_IDS_AXI_RD_4K_CROSS_WIDTH 1 +#define XDPDMA_IDS_AXI_RD_4K_CROSS_MASK 0X04000000 + +#define XDPDMA_IDS_WR_DATA_FIFO_FULL_SHIFT 25 +#define XDPDMA_IDS_WR_DATA_FIFO_FULL_WIDTH 1 +#define XDPDMA_IDS_WR_DATA_FIFO_FULL_MASK 0X02000000 + +#define XDPDMA_IDS_WR_CMD_FIFO_FULL_SHIFT 24 +#define XDPDMA_IDS_WR_CMD_FIFO_FULL_WIDTH 1 +#define XDPDMA_IDS_WR_CMD_FIFO_FULL_MASK 0X01000000 + +#define XDPDMA_IDS_DSCR_ERR5_SHIFT 23 +#define XDPDMA_IDS_DSCR_ERR5_WIDTH 1 +#define XDPDMA_IDS_DSCR_ERR5_MASK 0X800000 + +#define XDPDMA_IDS_DSCR_ERR4_SHIFT 22 +#define XDPDMA_IDS_DSCR_ERR4_WIDTH 1 +#define XDPDMA_IDS_DSCR_ERR4_MASK 0X400000 + +#define XDPDMA_IDS_DSCR_ERR3_SHIFT 21 +#define XDPDMA_IDS_DSCR_ERR3_WIDTH 1 +#define XDPDMA_IDS_DSCR_ERR3_MASK 0X200000 + +#define XDPDMA_IDS_DSCR_ERR2_SHIFT 20 +#define XDPDMA_IDS_DSCR_ERR2_WIDTH 1 +#define XDPDMA_IDS_DSCR_ERR2_MASK 0X100000 + +#define XDPDMA_IDS_DSCR_ERR1_SHIFT 19 +#define XDPDMA_IDS_DSCR_ERR1_WIDTH 1 +#define XDPDMA_IDS_DSCR_ERR1_MASK 0X80000 + +#define XDPDMA_IDS_DSCR_ERR0_SHIFT 18 +#define XDPDMA_IDS_DSCR_ERR0_WIDTH 1 +#define XDPDMA_IDS_DSCR_ERR0_MASK 0X40000 + +#define XDPDMA_IDS_DATA_AXI_ERR5_SHIFT 17 +#define XDPDMA_IDS_DATA_AXI_ERR5_WIDTH 1 +#define XDPDMA_IDS_DATA_AXI_ERR5_MASK 0X20000 + +#define XDPDMA_IDS_DATA_AXI_ERR4_SHIFT 16 +#define XDPDMA_IDS_DATA_AXI_ERR4_WIDTH 1 +#define XDPDMA_IDS_DATA_AXI_ERR4_MASK 0X10000 + +#define XDPDMA_IDS_DATA_AXI_ERR3_SHIFT 15 +#define XDPDMA_IDS_DATA_AXI_ERR3_WIDTH 1 +#define XDPDMA_IDS_DATA_AXI_ERR3_MASK 0X8000 + +#define XDPDMA_IDS_DATA_AXI_ERR2_SHIFT 14 +#define XDPDMA_IDS_DATA_AXI_ERR2_WIDTH 1 +#define XDPDMA_IDS_DATA_AXI_ERR2_MASK 0X4000 + +#define XDPDMA_IDS_DATA_AXI_ERR1_SHIFT 13 +#define XDPDMA_IDS_DATA_AXI_ERR1_WIDTH 1 +#define XDPDMA_IDS_DATA_AXI_ERR1_MASK 0X2000 + +#define XDPDMA_IDS_DATA_AXI_ERR0_SHIFT 12 +#define XDPDMA_IDS_DATA_AXI_ERR0_WIDTH 1 +#define XDPDMA_IDS_DATA_AXI_ERR0_MASK 0X1000 + +#define XDPDMA_IDS_NO_OSTAND_TRAN5_SHIFT 11 +#define XDPDMA_IDS_NO_OSTAND_TRAN5_WIDTH 1 +#define XDPDMA_IDS_NO_OSTAND_TRAN5_MASK 0X0800 + +#define XDPDMA_IDS_NO_OSTAND_TRAN4_SHIFT 10 +#define XDPDMA_IDS_NO_OSTAND_TRAN4_WIDTH 1 +#define XDPDMA_IDS_NO_OSTAND_TRAN4_MASK 0X0400 + +#define XDPDMA_IDS_NO_OSTAND_TRAN3_SHIFT 9 +#define XDPDMA_IDS_NO_OSTAND_TRAN3_WIDTH 1 +#define XDPDMA_IDS_NO_OSTAND_TRAN3_MASK 0X0200 + +#define XDPDMA_IDS_NO_OSTAND_TRAN2_SHIFT 8 +#define XDPDMA_IDS_NO_OSTAND_TRAN2_WIDTH 1 +#define XDPDMA_IDS_NO_OSTAND_TRAN2_MASK 0X0100 + +#define XDPDMA_IDS_NO_OSTAND_TRAN1_SHIFT 7 +#define XDPDMA_IDS_NO_OSTAND_TRAN1_WIDTH 1 +#define XDPDMA_IDS_NO_OSTAND_TRAN1_MASK 0X80 + +#define XDPDMA_IDS_NO_OSTAND_TRAN0_SHIFT 6 +#define XDPDMA_IDS_NO_OSTAND_TRAN0_WIDTH 1 +#define XDPDMA_IDS_NO_OSTAND_TRAN0_MASK 0X40 + +#define XDPDMA_IDS_DSCR_DONE5_SHIFT 5 +#define XDPDMA_IDS_DSCR_DONE5_WIDTH 1 +#define XDPDMA_IDS_DSCR_DONE5_MASK 0X20 + +#define XDPDMA_IDS_DSCR_DONE4_SHIFT 4 +#define XDPDMA_IDS_DSCR_DONE4_WIDTH 1 +#define XDPDMA_IDS_DSCR_DONE4_MASK 0X10 + +#define XDPDMA_IDS_DSCR_DONE3_SHIFT 3 +#define XDPDMA_IDS_DSCR_DONE3_WIDTH 1 +#define XDPDMA_IDS_DSCR_DONE3_MASK 0X8 + +#define XDPDMA_IDS_DSCR_DONE2_SHIFT 2 +#define XDPDMA_IDS_DSCR_DONE2_WIDTH 1 +#define XDPDMA_IDS_DSCR_DONE2_MASK 0X4 + +#define XDPDMA_IDS_DSCR_DONE1_SHIFT 1 +#define XDPDMA_IDS_DSCR_DONE1_WIDTH 1 +#define XDPDMA_IDS_DSCR_DONE1_MASK 0X2 + +#define XDPDMA_IDS_DSCR_DONE0_SHIFT 0 +#define XDPDMA_IDS_DSCR_DONE0_WIDTH 1 +#define XDPDMA_IDS_DSCR_DONE0_MASK 0X1 + +/** + * Register: XDPDMA_EISR + */ +#define XDPDMA_EISR 0X0014 + +#define XDPDMA_EISR_RD_CMD_FIFO_FULL_SHIFT 31 +#define XDPDMA_EISR_RD_CMD_FIFO_FULL_WIDTH 1 +#define XDPDMA_EISR_RD_CMD_FIFO_FULL_MASK 0X80000000 + +#define XDPDMA_EISR_DSCR_DONE_ERR5_SHIFT 30 +#define XDPDMA_EISR_DSCR_DONE_ERR5_WIDTH 1 +#define XDPDMA_EISR_DSCR_DONE_ERR5_MASK 0X40000000 + +#define XDPDMA_EISR_DSCR_DONE_ERR4_SHIFT 29 +#define XDPDMA_EISR_DSCR_DONE_ERR4_WIDTH 1 +#define XDPDMA_EISR_DSCR_DONE_ERR4_MASK 0X20000000 + +#define XDPDMA_EISR_DSCR_DONE_ERR3_SHIFT 28 +#define XDPDMA_EISR_DSCR_DONE_ERR3_WIDTH 1 +#define XDPDMA_EISR_DSCR_DONE_ERR3_MASK 0X10000000 + +#define XDPDMA_EISR_DSCR_DONE_ERR2_SHIFT 27 +#define XDPDMA_EISR_DSCR_DONE_ERR2_WIDTH 1 +#define XDPDMA_EISR_DSCR_DONE_ERR2_MASK 0X08000000 + +#define XDPDMA_EISR_DSCR_DONE_ERR1_SHIFT 26 +#define XDPDMA_EISR_DSCR_DONE_ERR1_WIDTH 1 +#define XDPDMA_EISR_DSCR_DONE_ERR1_MASK 0X04000000 + +#define XDPDMA_EISR_DSCR_DONE_ERR0_SHIFT 25 +#define XDPDMA_EISR_DSCR_DONE_ERR0_WIDTH 1 +#define XDPDMA_EISR_DSCR_DONE_ERR0_MASK 0X02000000 + +#define XDPDMA_EISR_DSCR_WR_AXI_ERR5_SHIFT 24 +#define XDPDMA_EISR_DSCR_WR_AXI_ERR5_WIDTH 1 +#define XDPDMA_EISR_DSCR_WR_AXI_ERR5_MASK 0X01000000 + +#define XDPDMA_EISR_DSCR_WR_AXI_ERR4_SHIFT 23 +#define XDPDMA_EISR_DSCR_WR_AXI_ERR4_WIDTH 1 +#define XDPDMA_EISR_DSCR_WR_AXI_ERR4_MASK 0X800000 + +#define XDPDMA_EISR_DSCR_WR_AXI_ERR3_SHIFT 22 +#define XDPDMA_EISR_DSCR_WR_AXI_ERR3_WIDTH 1 +#define XDPDMA_EISR_DSCR_WR_AXI_ERR3_MASK 0X400000 + +#define XDPDMA_EISR_DSCR_WR_AXI_ERR2_SHIFT 21 +#define XDPDMA_EISR_DSCR_WR_AXI_ERR2_WIDTH 1 +#define XDPDMA_EISR_DSCR_WR_AXI_ERR2_MASK 0X200000 + +#define XDPDMA_EISR_DSCR_WR_AXI_ERR1_SHIFT 20 +#define XDPDMA_EISR_DSCR_WR_AXI_ERR1_WIDTH 1 +#define XDPDMA_EISR_DSCR_WR_AXI_ERR1_MASK 0X100000 + +#define XDPDMA_EISR_DSCR_WR_AXI_ERR0_SHIFT 19 +#define XDPDMA_EISR_DSCR_WR_AXI_ERR0_WIDTH 1 +#define XDPDMA_EISR_DSCR_WR_AXI_ERR0_MASK 0X80000 + +#define XDPDMA_EISR_DSCR_CRC_ERR5_SHIFT 18 +#define XDPDMA_EISR_DSCR_CRC_ERR5_WIDTH 1 +#define XDPDMA_EISR_DSCR_CRC_ERR5_MASK 0X40000 + +#define XDPDMA_EISR_DSCR_CRC_ERR4_SHIFT 17 +#define XDPDMA_EISR_DSCR_CRC_ERR4_WIDTH 1 +#define XDPDMA_EISR_DSCR_CRC_ERR4_MASK 0X20000 + +#define XDPDMA_EISR_DSCR_CRC_ERR3_SHIFT 16 +#define XDPDMA_EISR_DSCR_CRC_ERR3_WIDTH 1 +#define XDPDMA_EISR_DSCR_CRC_ERR3_MASK 0X10000 + +#define XDPDMA_EISR_DSCR_CRC_ERR2_SHIFT 15 +#define XDPDMA_EISR_DSCR_CRC_ERR2_WIDTH 1 +#define XDPDMA_EISR_DSCR_CRC_ERR2_MASK 0X8000 + +#define XDPDMA_EISR_DSCR_CRC_ERR1_SHIFT 14 +#define XDPDMA_EISR_DSCR_CRC_ERR1_WIDTH 1 +#define XDPDMA_EISR_DSCR_CRC_ERR1_MASK 0X4000 + +#define XDPDMA_EISR_DSCR_CRC_ERR0_SHIFT 13 +#define XDPDMA_EISR_DSCR_CRC_ERR0_WIDTH 1 +#define XDPDMA_EISR_DSCR_CRC_ERR0_MASK 0X2000 + +#define XDPDMA_EISR_DSCR_PRE_ERR5_SHIFT 12 +#define XDPDMA_EISR_DSCR_PRE_ERR5_WIDTH 1 +#define XDPDMA_EISR_DSCR_PRE_ERR5_MASK 0X1000 + +#define XDPDMA_EISR_DSCR_PRE_ERR4_SHIFT 11 +#define XDPDMA_EISR_DSCR_PRE_ERR4_WIDTH 1 +#define XDPDMA_EISR_DSCR_PRE_ERR4_MASK 0X0800 + +#define XDPDMA_EISR_DSCR_PRE_ERR3_SHIFT 10 +#define XDPDMA_EISR_DSCR_PRE_ERR3_WIDTH 1 +#define XDPDMA_EISR_DSCR_PRE_ERR3_MASK 0X0400 + +#define XDPDMA_EISR_DSCR_PRE_ERR2_SHIFT 9 +#define XDPDMA_EISR_DSCR_PRE_ERR2_WIDTH 1 +#define XDPDMA_EISR_DSCR_PRE_ERR2_MASK 0X0200 + +#define XDPDMA_EISR_DSCR_PRE_ERR1_SHIFT 8 +#define XDPDMA_EISR_DSCR_PRE_ERR1_WIDTH 1 +#define XDPDMA_EISR_DSCR_PRE_ERR1_MASK 0X0100 + +#define XDPDMA_EISR_DSCR_PRE_ERR0_SHIFT 7 +#define XDPDMA_EISR_DSCR_PRE_ERR0_WIDTH 1 +#define XDPDMA_EISR_DSCR_PRE_ERR0_MASK 0X80 + +#define XDPDMA_EISR_DSCR_RD_AXI_ERR5_SHIFT 6 +#define XDPDMA_EISR_DSCR_RD_AXI_ERR5_WIDTH 1 +#define XDPDMA_EISR_DSCR_RD_AXI_ERR5_MASK 0X40 + +#define XDPDMA_EISR_DSCR_RD_AXI_ERR4_SHIFT 5 +#define XDPDMA_EISR_DSCR_RD_AXI_ERR4_WIDTH 1 +#define XDPDMA_EISR_DSCR_RD_AXI_ERR4_MASK 0X20 + +#define XDPDMA_EISR_DSCR_RD_AXI_ERR3_SHIFT 4 +#define XDPDMA_EISR_DSCR_RD_AXI_ERR3_WIDTH 1 +#define XDPDMA_EISR_DSCR_RD_AXI_ERR3_MASK 0X10 + +#define XDPDMA_EISR_DSCR_RD_AXI_ERR2_SHIFT 3 +#define XDPDMA_EISR_DSCR_RD_AXI_ERR2_WIDTH 1 +#define XDPDMA_EISR_DSCR_RD_AXI_ERR2_MASK 0X8 + +#define XDPDMA_EISR_DSCR_RD_AXI_ERR1_SHIFT 2 +#define XDPDMA_EISR_DSCR_RD_AXI_ERR1_WIDTH 1 +#define XDPDMA_EISR_DSCR_RD_AXI_ERR1_MASK 0X4 + +#define XDPDMA_EISR_DSCR_RD_AXI_ERR0_SHIFT 1 +#define XDPDMA_EISR_DSCR_RD_AXI_ERR0_WIDTH 1 +#define XDPDMA_EISR_DSCR_RD_AXI_ERR0_MASK 0X2 + +#define XDPDMA_EISR_INV_APB_SHIFT 0 +#define XDPDMA_EISR_INV_APB_WIDTH 1 +#define XDPDMA_EISR_INV_APB_MASK 0X1 + +/** + * Register: XDPDMA_EIMR + */ +#define XDPDMA_EIMR 0X0018 + +#define XDPDMA_EIMR_RD_CMD_FIFO_FULL_SHIFT 31 +#define XDPDMA_EIMR_RD_CMD_FIFO_FULL_WIDTH 1 +#define XDPDMA_EIMR_RD_CMD_FIFO_FULL_MASK 0X80000000 + +#define XDPDMA_EIMR_DSCR_DONE_ERR5_SHIFT 30 +#define XDPDMA_EIMR_DSCR_DONE_ERR5_WIDTH 1 +#define XDPDMA_EIMR_DSCR_DONE_ERR5_MASK 0X40000000 + +#define XDPDMA_EIMR_DSCR_DONE_ERR4_SHIFT 29 +#define XDPDMA_EIMR_DSCR_DONE_ERR4_WIDTH 1 +#define XDPDMA_EIMR_DSCR_DONE_ERR4_MASK 0X20000000 + +#define XDPDMA_EIMR_DSCR_DONE_ERR3_SHIFT 28 +#define XDPDMA_EIMR_DSCR_DONE_ERR3_WIDTH 1 +#define XDPDMA_EIMR_DSCR_DONE_ERR3_MASK 0X10000000 + +#define XDPDMA_EIMR_DSCR_DONE_ERR2_SHIFT 27 +#define XDPDMA_EIMR_DSCR_DONE_ERR2_WIDTH 1 +#define XDPDMA_EIMR_DSCR_DONE_ERR2_MASK 0X08000000 + +#define XDPDMA_EIMR_DSCR_DONE_ERR1_SHIFT 26 +#define XDPDMA_EIMR_DSCR_DONE_ERR1_WIDTH 1 +#define XDPDMA_EIMR_DSCR_DONE_ERR1_MASK 0X04000000 + +#define XDPDMA_EIMR_DSCR_DONE_ERR0_SHIFT 25 +#define XDPDMA_EIMR_DSCR_DONE_ERR0_WIDTH 1 +#define XDPDMA_EIMR_DSCR_DONE_ERR0_MASK 0X02000000 + +#define XDPDMA_EIMR_DSCR_WR_AXI_ERR5_SHIFT 24 +#define XDPDMA_EIMR_DSCR_WR_AXI_ERR5_WIDTH 1 +#define XDPDMA_EIMR_DSCR_WR_AXI_ERR5_MASK 0X01000000 + +#define XDPDMA_EIMR_DSCR_WR_AXI_ERR4_SHIFT 23 +#define XDPDMA_EIMR_DSCR_WR_AXI_ERR4_WIDTH 1 +#define XDPDMA_EIMR_DSCR_WR_AXI_ERR4_MASK 0X800000 + +#define XDPDMA_EIMR_DSCR_WR_AXI_ERR3_SHIFT 22 +#define XDPDMA_EIMR_DSCR_WR_AXI_ERR3_WIDTH 1 +#define XDPDMA_EIMR_DSCR_WR_AXI_ERR3_MASK 0X400000 + +#define XDPDMA_EIMR_DSCR_WR_AXI_ERR2_SHIFT 21 +#define XDPDMA_EIMR_DSCR_WR_AXI_ERR2_WIDTH 1 +#define XDPDMA_EIMR_DSCR_WR_AXI_ERR2_MASK 0X200000 + +#define XDPDMA_EIMR_DSCR_WR_AXI_ERR1_SHIFT 20 +#define XDPDMA_EIMR_DSCR_WR_AXI_ERR1_WIDTH 1 +#define XDPDMA_EIMR_DSCR_WR_AXI_ERR1_MASK 0X100000 + +#define XDPDMA_EIMR_DSCR_WR_AXI_ERR0_SHIFT 19 +#define XDPDMA_EIMR_DSCR_WR_AXI_ERR0_WIDTH 1 +#define XDPDMA_EIMR_DSCR_WR_AXI_ERR0_MASK 0X80000 + +#define XDPDMA_EIMR_DSCR_CRC_ERR5_SHIFT 18 +#define XDPDMA_EIMR_DSCR_CRC_ERR5_WIDTH 1 +#define XDPDMA_EIMR_DSCR_CRC_ERR5_MASK 0X40000 + +#define XDPDMA_EIMR_DSCR_CRC_ERR4_SHIFT 17 +#define XDPDMA_EIMR_DSCR_CRC_ERR4_WIDTH 1 +#define XDPDMA_EIMR_DSCR_CRC_ERR4_MASK 0X20000 + +#define XDPDMA_EIMR_DSCR_CRC_ERR3_SHIFT 16 +#define XDPDMA_EIMR_DSCR_CRC_ERR3_WIDTH 1 +#define XDPDMA_EIMR_DSCR_CRC_ERR3_MASK 0X10000 + +#define XDPDMA_EIMR_DSCR_CRC_ERR2_SHIFT 15 +#define XDPDMA_EIMR_DSCR_CRC_ERR2_WIDTH 1 +#define XDPDMA_EIMR_DSCR_CRC_ERR2_MASK 0X8000 + +#define XDPDMA_EIMR_DSCR_CRC_ERR1_SHIFT 14 +#define XDPDMA_EIMR_DSCR_CRC_ERR1_WIDTH 1 +#define XDPDMA_EIMR_DSCR_CRC_ERR1_MASK 0X4000 + +#define XDPDMA_EIMR_DSCR_CRC_ERR0_SHIFT 13 +#define XDPDMA_EIMR_DSCR_CRC_ERR0_WIDTH 1 +#define XDPDMA_EIMR_DSCR_CRC_ERR0_MASK 0X2000 + +#define XDPDMA_EIMR_DSCR_PRE_ERR5_SHIFT 12 +#define XDPDMA_EIMR_DSCR_PRE_ERR5_WIDTH 1 +#define XDPDMA_EIMR_DSCR_PRE_ERR5_MASK 0X1000 + +#define XDPDMA_EIMR_DSCR_PRE_ERR4_SHIFT 11 +#define XDPDMA_EIMR_DSCR_PRE_ERR4_WIDTH 1 +#define XDPDMA_EIMR_DSCR_PRE_ERR4_MASK 0X0800 + +#define XDPDMA_EIMR_DSCR_PRE_ERR3_SHIFT 10 +#define XDPDMA_EIMR_DSCR_PRE_ERR3_WIDTH 1 +#define XDPDMA_EIMR_DSCR_PRE_ERR3_MASK 0X0400 + +#define XDPDMA_EIMR_DSCR_PRE_ERR2_SHIFT 9 +#define XDPDMA_EIMR_DSCR_PRE_ERR2_WIDTH 1 +#define XDPDMA_EIMR_DSCR_PRE_ERR2_MASK 0X0200 + +#define XDPDMA_EIMR_DSCR_PRE_ERR1_SHIFT 8 +#define XDPDMA_EIMR_DSCR_PRE_ERR1_WIDTH 1 +#define XDPDMA_EIMR_DSCR_PRE_ERR1_MASK 0X0100 + +#define XDPDMA_EIMR_DSCR_PRE_ERR0_SHIFT 7 +#define XDPDMA_EIMR_DSCR_PRE_ERR0_WIDTH 1 +#define XDPDMA_EIMR_DSCR_PRE_ERR0_MASK 0X80 + +#define XDPDMA_EIMR_DSCR_RD_AXI_ERR5_SHIFT 6 +#define XDPDMA_EIMR_DSCR_RD_AXI_ERR5_WIDTH 1 +#define XDPDMA_EIMR_DSCR_RD_AXI_ERR5_MASK 0X40 + +#define XDPDMA_EIMR_DSCR_RD_AXI_ERR4_SHIFT 5 +#define XDPDMA_EIMR_DSCR_RD_AXI_ERR4_WIDTH 1 +#define XDPDMA_EIMR_DSCR_RD_AXI_ERR4_MASK 0X20 + +#define XDPDMA_EIMR_DSCR_RD_AXI_ERR3_SHIFT 4 +#define XDPDMA_EIMR_DSCR_RD_AXI_ERR3_WIDTH 1 +#define XDPDMA_EIMR_DSCR_RD_AXI_ERR3_MASK 0X10 + +#define XDPDMA_EIMR_DSCR_RD_AXI_ERR2_SHIFT 3 +#define XDPDMA_EIMR_DSCR_RD_AXI_ERR2_WIDTH 1 +#define XDPDMA_EIMR_DSCR_RD_AXI_ERR2_MASK 0X8 + +#define XDPDMA_EIMR_DSCR_RD_AXI_ERR1_SHIFT 2 +#define XDPDMA_EIMR_DSCR_RD_AXI_ERR1_WIDTH 1 +#define XDPDMA_EIMR_DSCR_RD_AXI_ERR1_MASK 0X4 + +#define XDPDMA_EIMR_DSCR_RD_AXI_ERR0_SHIFT 1 +#define XDPDMA_EIMR_DSCR_RD_AXI_ERR0_WIDTH 1 +#define XDPDMA_EIMR_DSCR_RD_AXI_ERR0_MASK 0X2 + +#define XDPDMA_EIMR_INV_APB_SHIFT 0 +#define XDPDMA_EIMR_INV_APB_WIDTH 1 +#define XDPDMA_EIMR_INV_APB_MASK 0X1 + +/** + * Register: XDPDMA_EIEN + */ +#define XDPDMA_EIEN 0X001C + +#define XDPDMA_EIEN_RD_CMD_FIFO_FULL_SHIFT 31 +#define XDPDMA_EIEN_RD_CMD_FIFO_FULL_WIDTH 1 +#define XDPDMA_EIEN_RD_CMD_FIFO_FULL_MASK 0X80000000 + +#define XDPDMA_EIEN_DSCR_DONE_ERR5_SHIFT 30 +#define XDPDMA_EIEN_DSCR_DONE_ERR5_WIDTH 1 +#define XDPDMA_EIEN_DSCR_DONE_ERR5_MASK 0X40000000 + +#define XDPDMA_EIEN_DSCR_DONE_ERR4_SHIFT 29 +#define XDPDMA_EIEN_DSCR_DONE_ERR4_WIDTH 1 +#define XDPDMA_EIEN_DSCR_DONE_ERR4_MASK 0X20000000 + +#define XDPDMA_EIEN_DSCR_DONE_ERR3_SHIFT 28 +#define XDPDMA_EIEN_DSCR_DONE_ERR3_WIDTH 1 +#define XDPDMA_EIEN_DSCR_DONE_ERR3_MASK 0X10000000 + +#define XDPDMA_EIEN_DSCR_DONE_ERR2_SHIFT 27 +#define XDPDMA_EIEN_DSCR_DONE_ERR2_WIDTH 1 +#define XDPDMA_EIEN_DSCR_DONE_ERR2_MASK 0X08000000 + +#define XDPDMA_EIEN_DSCR_DONE_ERR1_SHIFT 26 +#define XDPDMA_EIEN_DSCR_DONE_ERR1_WIDTH 1 +#define XDPDMA_EIEN_DSCR_DONE_ERR1_MASK 0X04000000 + +#define XDPDMA_EIEN_DSCR_DONE_ERR0_SHIFT 25 +#define XDPDMA_EIEN_DSCR_DONE_ERR0_WIDTH 1 +#define XDPDMA_EIEN_DSCR_DONE_ERR0_MASK 0X02000000 + +#define XDPDMA_EIEN_DSCR_WR_AXI_ERR5_SHIFT 24 +#define XDPDMA_EIEN_DSCR_WR_AXI_ERR5_WIDTH 1 +#define XDPDMA_EIEN_DSCR_WR_AXI_ERR5_MASK 0X01000000 + +#define XDPDMA_EIEN_DSCR_WR_AXI_ERR4_SHIFT 23 +#define XDPDMA_EIEN_DSCR_WR_AXI_ERR4_WIDTH 1 +#define XDPDMA_EIEN_DSCR_WR_AXI_ERR4_MASK 0X800000 + +#define XDPDMA_EIEN_DSCR_WR_AXI_ERR3_SHIFT 22 +#define XDPDMA_EIEN_DSCR_WR_AXI_ERR3_WIDTH 1 +#define XDPDMA_EIEN_DSCR_WR_AXI_ERR3_MASK 0X400000 + +#define XDPDMA_EIEN_DSCR_WR_AXI_ERR2_SHIFT 21 +#define XDPDMA_EIEN_DSCR_WR_AXI_ERR2_WIDTH 1 +#define XDPDMA_EIEN_DSCR_WR_AXI_ERR2_MASK 0X200000 + +#define XDPDMA_EIEN_DSCR_WR_AXI_ERR1_SHIFT 20 +#define XDPDMA_EIEN_DSCR_WR_AXI_ERR1_WIDTH 1 +#define XDPDMA_EIEN_DSCR_WR_AXI_ERR1_MASK 0X100000 + +#define XDPDMA_EIEN_DSCR_WR_AXI_ERR0_SHIFT 19 +#define XDPDMA_EIEN_DSCR_WR_AXI_ERR0_WIDTH 1 +#define XDPDMA_EIEN_DSCR_WR_AXI_ERR0_MASK 0X80000 + +#define XDPDMA_EIEN_DSCR_CRC_ERR5_SHIFT 18 +#define XDPDMA_EIEN_DSCR_CRC_ERR5_WIDTH 1 +#define XDPDMA_EIEN_DSCR_CRC_ERR5_MASK 0X40000 + +#define XDPDMA_EIEN_DSCR_CRC_ERR4_SHIFT 17 +#define XDPDMA_EIEN_DSCR_CRC_ERR4_WIDTH 1 +#define XDPDMA_EIEN_DSCR_CRC_ERR4_MASK 0X20000 + +#define XDPDMA_EIEN_DSCR_CRC_ERR3_SHIFT 16 +#define XDPDMA_EIEN_DSCR_CRC_ERR3_WIDTH 1 +#define XDPDMA_EIEN_DSCR_CRC_ERR3_MASK 0X10000 + +#define XDPDMA_EIEN_DSCR_CRC_ERR2_SHIFT 15 +#define XDPDMA_EIEN_DSCR_CRC_ERR2_WIDTH 1 +#define XDPDMA_EIEN_DSCR_CRC_ERR2_MASK 0X8000 + +#define XDPDMA_EIEN_DSCR_CRC_ERR1_SHIFT 14 +#define XDPDMA_EIEN_DSCR_CRC_ERR1_WIDTH 1 +#define XDPDMA_EIEN_DSCR_CRC_ERR1_MASK 0X4000 + +#define XDPDMA_EIEN_DSCR_CRC_ERR0_SHIFT 13 +#define XDPDMA_EIEN_DSCR_CRC_ERR0_WIDTH 1 +#define XDPDMA_EIEN_DSCR_CRC_ERR0_MASK 0X2000 + +#define XDPDMA_EIEN_DSCR_PRE_ERR5_SHIFT 12 +#define XDPDMA_EIEN_DSCR_PRE_ERR5_WIDTH 1 +#define XDPDMA_EIEN_DSCR_PRE_ERR5_MASK 0X1000 + +#define XDPDMA_EIEN_DSCR_PRE_ERR4_SHIFT 11 +#define XDPDMA_EIEN_DSCR_PRE_ERR4_WIDTH 1 +#define XDPDMA_EIEN_DSCR_PRE_ERR4_MASK 0X0800 + +#define XDPDMA_EIEN_DSCR_PRE_ERR3_SHIFT 10 +#define XDPDMA_EIEN_DSCR_PRE_ERR3_WIDTH 1 +#define XDPDMA_EIEN_DSCR_PRE_ERR3_MASK 0X0400 + +#define XDPDMA_EIEN_DSCR_PRE_ERR2_SHIFT 9 +#define XDPDMA_EIEN_DSCR_PRE_ERR2_WIDTH 1 +#define XDPDMA_EIEN_DSCR_PRE_ERR2_MASK 0X0200 + +#define XDPDMA_EIEN_DSCR_PRE_ERR1_SHIFT 8 +#define XDPDMA_EIEN_DSCR_PRE_ERR1_WIDTH 1 +#define XDPDMA_EIEN_DSCR_PRE_ERR1_MASK 0X0100 + +#define XDPDMA_EIEN_DSCR_PRE_ERR0_SHIFT 7 +#define XDPDMA_EIEN_DSCR_PRE_ERR0_WIDTH 1 +#define XDPDMA_EIEN_DSCR_PRE_ERR0_MASK 0X80 + +#define XDPDMA_EIEN_DSCR_RD_AXI_ERR5_SHIFT 6 +#define XDPDMA_EIEN_DSCR_RD_AXI_ERR5_WIDTH 1 +#define XDPDMA_EIEN_DSCR_RD_AXI_ERR5_MASK 0X40 + +#define XDPDMA_EIEN_DSCR_RD_AXI_ERR4_SHIFT 5 +#define XDPDMA_EIEN_DSCR_RD_AXI_ERR4_WIDTH 1 +#define XDPDMA_EIEN_DSCR_RD_AXI_ERR4_MASK 0X20 + +#define XDPDMA_EIEN_DSCR_RD_AXI_ERR3_SHIFT 4 +#define XDPDMA_EIEN_DSCR_RD_AXI_ERR3_WIDTH 1 +#define XDPDMA_EIEN_DSCR_RD_AXI_ERR3_MASK 0X10 + +#define XDPDMA_EIEN_DSCR_RD_AXI_ERR2_SHIFT 3 +#define XDPDMA_EIEN_DSCR_RD_AXI_ERR2_WIDTH 1 +#define XDPDMA_EIEN_DSCR_RD_AXI_ERR2_MASK 0X8 + +#define XDPDMA_EIEN_DSCR_RD_AXI_ERR1_SHIFT 2 +#define XDPDMA_EIEN_DSCR_RD_AXI_ERR1_WIDTH 1 +#define XDPDMA_EIEN_DSCR_RD_AXI_ERR1_MASK 0X4 + +#define XDPDMA_EIEN_DSCR_RD_AXI_ERR0_SHIFT 1 +#define XDPDMA_EIEN_DSCR_RD_AXI_ERR0_WIDTH 1 +#define XDPDMA_EIEN_DSCR_RD_AXI_ERR0_MASK 0X2 + +#define XDPDMA_EIEN_INV_APB_SHIFT 0 +#define XDPDMA_EIEN_INV_APB_WIDTH 1 +#define XDPDMA_EIEN_INV_APB_MASK 0X1 + +/** + * Register: XDPDMA_EIDS + */ +#define XDPDMA_EIDS 0X0020 + +#define XDPDMA_EIDS_RD_CMD_FIFO_FULL_SHIFT 31 +#define XDPDMA_EIDS_RD_CMD_FIFO_FULL_WIDTH 1 +#define XDPDMA_EIDS_RD_CMD_FIFO_FULL_MASK 0X80000000 + +#define XDPDMA_EIDS_DSCR_DONE_ERR5_SHIFT 30 +#define XDPDMA_EIDS_DSCR_DONE_ERR5_WIDTH 1 +#define XDPDMA_EIDS_DSCR_DONE_ERR5_MASK 0X40000000 + +#define XDPDMA_EIDS_DSCR_DONE_ERR4_SHIFT 29 +#define XDPDMA_EIDS_DSCR_DONE_ERR4_WIDTH 1 +#define XDPDMA_EIDS_DSCR_DONE_ERR4_MASK 0X20000000 + +#define XDPDMA_EIDS_DSCR_DONE_ERR3_SHIFT 28 +#define XDPDMA_EIDS_DSCR_DONE_ERR3_WIDTH 1 +#define XDPDMA_EIDS_DSCR_DONE_ERR3_MASK 0X10000000 + +#define XDPDMA_EIDS_DSCR_DONE_ERR2_SHIFT 27 +#define XDPDMA_EIDS_DSCR_DONE_ERR2_WIDTH 1 +#define XDPDMA_EIDS_DSCR_DONE_ERR2_MASK 0X08000000 + +#define XDPDMA_EIDS_DSCR_DONE_ERR1_SHIFT 26 +#define XDPDMA_EIDS_DSCR_DONE_ERR1_WIDTH 1 +#define XDPDMA_EIDS_DSCR_DONE_ERR1_MASK 0X04000000 + +#define XDPDMA_EIDS_DSCR_DONE_ERR0_SHIFT 25 +#define XDPDMA_EIDS_DSCR_DONE_ERR0_WIDTH 1 +#define XDPDMA_EIDS_DSCR_DONE_ERR0_MASK 0X02000000 + +#define XDPDMA_EIDS_DSCR_WR_AXI_ERR5_SHIFT 24 +#define XDPDMA_EIDS_DSCR_WR_AXI_ERR5_WIDTH 1 +#define XDPDMA_EIDS_DSCR_WR_AXI_ERR5_MASK 0X01000000 + +#define XDPDMA_EIDS_DSCR_WR_AXI_ERR4_SHIFT 23 +#define XDPDMA_EIDS_DSCR_WR_AXI_ERR4_WIDTH 1 +#define XDPDMA_EIDS_DSCR_WR_AXI_ERR4_MASK 0X800000 + +#define XDPDMA_EIDS_DSCR_WR_AXI_ERR3_SHIFT 22 +#define XDPDMA_EIDS_DSCR_WR_AXI_ERR3_WIDTH 1 +#define XDPDMA_EIDS_DSCR_WR_AXI_ERR3_MASK 0X400000 + +#define XDPDMA_EIDS_DSCR_WR_AXI_ERR2_SHIFT 21 +#define XDPDMA_EIDS_DSCR_WR_AXI_ERR2_WIDTH 1 +#define XDPDMA_EIDS_DSCR_WR_AXI_ERR2_MASK 0X200000 + +#define XDPDMA_EIDS_DSCR_WR_AXI_ERR1_SHIFT 20 +#define XDPDMA_EIDS_DSCR_WR_AXI_ERR1_WIDTH 1 +#define XDPDMA_EIDS_DSCR_WR_AXI_ERR1_MASK 0X100000 + +#define XDPDMA_EIDS_DSCR_WR_AXI_ERR0_SHIFT 19 +#define XDPDMA_EIDS_DSCR_WR_AXI_ERR0_WIDTH 1 +#define XDPDMA_EIDS_DSCR_WR_AXI_ERR0_MASK 0X80000 + +#define XDPDMA_EIDS_DSCR_CRC_ERR5_SHIFT 18 +#define XDPDMA_EIDS_DSCR_CRC_ERR5_WIDTH 1 +#define XDPDMA_EIDS_DSCR_CRC_ERR5_MASK 0X40000 + +#define XDPDMA_EIDS_DSCR_CRC_ERR4_SHIFT 17 +#define XDPDMA_EIDS_DSCR_CRC_ERR4_WIDTH 1 +#define XDPDMA_EIDS_DSCR_CRC_ERR4_MASK 0X20000 + +#define XDPDMA_EIDS_DSCR_CRC_ERR3_SHIFT 16 +#define XDPDMA_EIDS_DSCR_CRC_ERR3_WIDTH 1 +#define XDPDMA_EIDS_DSCR_CRC_ERR3_MASK 0X10000 + +#define XDPDMA_EIDS_DSCR_CRC_ERR2_SHIFT 15 +#define XDPDMA_EIDS_DSCR_CRC_ERR2_WIDTH 1 +#define XDPDMA_EIDS_DSCR_CRC_ERR2_MASK 0X8000 + +#define XDPDMA_EIDS_DSCR_CRC_ERR1_SHIFT 14 +#define XDPDMA_EIDS_DSCR_CRC_ERR1_WIDTH 1 +#define XDPDMA_EIDS_DSCR_CRC_ERR1_MASK 0X4000 + +#define XDPDMA_EIDS_DSCR_CRC_ERR0_SHIFT 13 +#define XDPDMA_EIDS_DSCR_CRC_ERR0_WIDTH 1 +#define XDPDMA_EIDS_DSCR_CRC_ERR0_MASK 0X2000 + +#define XDPDMA_EIDS_DSCR_PRE_ERR5_SHIFT 12 +#define XDPDMA_EIDS_DSCR_PRE_ERR5_WIDTH 1 +#define XDPDMA_EIDS_DSCR_PRE_ERR5_MASK 0X1000 + +#define XDPDMA_EIDS_DSCR_PRE_ERR4_SHIFT 11 +#define XDPDMA_EIDS_DSCR_PRE_ERR4_WIDTH 1 +#define XDPDMA_EIDS_DSCR_PRE_ERR4_MASK 0X0800 + +#define XDPDMA_EIDS_DSCR_PRE_ERR3_SHIFT 10 +#define XDPDMA_EIDS_DSCR_PRE_ERR3_WIDTH 1 +#define XDPDMA_EIDS_DSCR_PRE_ERR3_MASK 0X0400 + +#define XDPDMA_EIDS_DSCR_PRE_ERR2_SHIFT 9 +#define XDPDMA_EIDS_DSCR_PRE_ERR2_WIDTH 1 +#define XDPDMA_EIDS_DSCR_PRE_ERR2_MASK 0X0200 + +#define XDPDMA_EIDS_DSCR_PRE_ERR1_SHIFT 8 +#define XDPDMA_EIDS_DSCR_PRE_ERR1_WIDTH 1 +#define XDPDMA_EIDS_DSCR_PRE_ERR1_MASK 0X0100 + +#define XDPDMA_EIDS_DSCR_PRE_ERR0_SHIFT 7 +#define XDPDMA_EIDS_DSCR_PRE_ERR0_WIDTH 1 +#define XDPDMA_EIDS_DSCR_PRE_ERR0_MASK 0X80 + +#define XDPDMA_EIDS_DSCR_RD_AXI_ERR5_SHIFT 6 +#define XDPDMA_EIDS_DSCR_RD_AXI_ERR5_WIDTH 1 +#define XDPDMA_EIDS_DSCR_RD_AXI_ERR5_MASK 0X40 + +#define XDPDMA_EIDS_DSCR_RD_AXI_ERR4_SHIFT 5 +#define XDPDMA_EIDS_DSCR_RD_AXI_ERR4_WIDTH 1 +#define XDPDMA_EIDS_DSCR_RD_AXI_ERR4_MASK 0X20 + +#define XDPDMA_EIDS_DSCR_RD_AXI_ERR3_SHIFT 4 +#define XDPDMA_EIDS_DSCR_RD_AXI_ERR3_WIDTH 1 +#define XDPDMA_EIDS_DSCR_RD_AXI_ERR3_MASK 0X10 + +#define XDPDMA_EIDS_DSCR_RD_AXI_ERR2_SHIFT 3 +#define XDPDMA_EIDS_DSCR_RD_AXI_ERR2_WIDTH 1 +#define XDPDMA_EIDS_DSCR_RD_AXI_ERR2_MASK 0X8 + +#define XDPDMA_EIDS_DSCR_RD_AXI_ERR1_SHIFT 2 +#define XDPDMA_EIDS_DSCR_RD_AXI_ERR1_WIDTH 1 +#define XDPDMA_EIDS_DSCR_RD_AXI_ERR1_MASK 0X4 + +#define XDPDMA_EIDS_DSCR_RD_AXI_ERR0_SHIFT 1 +#define XDPDMA_EIDS_DSCR_RD_AXI_ERR0_WIDTH 1 +#define XDPDMA_EIDS_DSCR_RD_AXI_ERR0_MASK 0X2 + +#define XDPDMA_EIDS_INV_APB_SHIFT 0 +#define XDPDMA_EIDS_INV_APB_WIDTH 1 +#define XDPDMA_EIDS_INV_APB_MASK 0X1 + +/** + * Register: XDPDMA_CNTL + */ +#define XDPDMA_CNTL 0X0100 + +/** + * Register: XDPDMA_GBL + */ +#define XDPDMA_GBL 0X0104 + +#define XDPDMA_GBL_RTRG_CH5_SHIFT 11 +#define XDPDMA_GBL_RTRG_CH5_WIDTH 1 +#define XDPDMA_GBL_RTRG_CH5_MASK 0X0800 + +#define XDPDMA_GBL_RTRG_CH4_SHIFT 10 +#define XDPDMA_GBL_RTRG_CH4_WIDTH 1 +#define XDPDMA_GBL_RTRG_CH4_MASK 0X0400 + +#define XDPDMA_GBL_RTRG_CH3_SHIFT 9 +#define XDPDMA_GBL_RTRG_CH3_WIDTH 1 +#define XDPDMA_GBL_RTRG_CH3_MASK 0X0200 + +#define XDPDMA_GBL_RTRG_CH2_SHIFT 8 +#define XDPDMA_GBL_RTRG_CH2_WIDTH 1 +#define XDPDMA_GBL_RTRG_CH2_MASK 0X0100 + +#define XDPDMA_GBL_RTRG_CH1_SHIFT 7 +#define XDPDMA_GBL_RTRG_CH1_WIDTH 1 +#define XDPDMA_GBL_RTRG_CH1_MASK 0X80 + +#define XDPDMA_GBL_RTRG_CH0_SHIFT 6 +#define XDPDMA_GBL_RTRG_CH0_WIDTH 1 +#define XDPDMA_GBL_RTRG_CH0_MASK 0X40 + +#define XDPDMA_GBL_TRG_CH5_SHIFT 5 +#define XDPDMA_GBL_TRG_CH5_WIDTH 1 +#define XDPDMA_GBL_TRG_CH5_MASK 0X20 + +#define XDPDMA_GBL_TRG_CH4_SHIFT 4 +#define XDPDMA_GBL_TRG_CH4_WIDTH 1 +#define XDPDMA_GBL_TRG_CH4_MASK 0X10 + +#define XDPDMA_GBL_TRG_CH3_SHIFT 3 +#define XDPDMA_GBL_TRG_CH3_WIDTH 1 +#define XDPDMA_GBL_TRG_CH3_MASK 0X8 + +#define XDPDMA_GBL_TRG_CH2_SHIFT 2 +#define XDPDMA_GBL_TRG_CH2_WIDTH 1 +#define XDPDMA_GBL_TRG_CH2_MASK 0X4 + +#define XDPDMA_GBL_TRG_CH1_SHIFT 1 +#define XDPDMA_GBL_TRG_CH1_WIDTH 1 +#define XDPDMA_GBL_TRG_CH1_MASK 0X2 + +#define XDPDMA_GBL_TRG_CH0_SHIFT 0 +#define XDPDMA_GBL_TRG_CH0_WIDTH 1 +#define XDPDMA_GBL_TRG_CH0_MASK 0X1 + +/** + * Register: XDPDMA_CH0_DSCR_STRT_ADDRE + */ +#define XDPDMA_CH0_DSCR_STRT_ADDRE 0X0200 + +/** + * Register: XDPDMA_CH0_DSCR_STRT_ADDR + */ +#define XDPDMA_CH0_DSCR_STRT_ADDR 0X0204 + +/** + * Register: XDPDMA_CH0_DSCR_NEXT_ADDRE + */ +#define XDPDMA_CH0_DSCR_NEXT_ADDRE 0X0208 + +/** + * Register: XDPDMA_CH0_DSCR_NEXT_ADDR + */ +#define XDPDMA_CH0_DSCR_NEXT_ADDR 0X020C + +/** + * Register: XDPDMA_CH0_PYLD_CUR_ADDRE + */ +#define XDPDMA_CH0_PYLD_CUR_ADDRE 0X0210 + +/** + * Register: XDPDMA_CH0_PYLD_CUR_ADDR + */ +#define XDPDMA_CH0_PYLD_CUR_ADDR 0X0214 + +/** + * Register: XDPDMA_CH0_CNTL + */ +#define XDPDMA_CH0_CNTL 0X0218 + +#define XDPDMA_CNTL_QOS_VIDEO 0x11 + +/** + * Register: XDPDMA_CH0_STATUS + */ +#define XDPDMA_CH0_STATUS 0X021C + +/** + * Register: XDPDMA_CH0_VDO + */ +#define XDPDMA_CH0_VDO 0X0220 + +/** + * Register: XDPDMA_CH0_PYLD_SZ + */ +#define XDPDMA_CH0_PYLD_SZ 0X0224 + +/** + * Register: XDPDMA_CH0_DSCR_ID + */ +#define XDPDMA_CH0_DSCR_ID 0X0228 + +/** + * Register: XDPDMA_CH1_DSCR_STRT_ADDRE + */ +#define XDPDMA_CH1_DSCR_STRT_ADDRE 0X0300 + +/** + * Register: XDPDMA_CH1_DSCR_STRT_ADDR + */ +#define XDPDMA_CH1_DSCR_STRT_ADDR 0X0304 + +/** + * Register: XDPDMA_CH1_DSCR_NEXT_ADDRE + */ +#define XDPDMA_CH1_DSCR_NEXT_ADDRE 0X0308 + +/** + * Register: XDPDMA_CH1_DSCR_NEXT_ADDR + */ +#define XDPDMA_CH1_DSCR_NEXT_ADDR 0X030C + +/** + * Register: XDPDMA_CH1_PYLD_CUR_ADDRE + */ +#define XDPDMA_CH1_PYLD_CUR_ADDRE 0X0310 + +/** + * Register: XDPDMA_CH1_PYLD_CUR_ADDR + */ +#define XDPDMA_CH1_PYLD_CUR_ADDR 0X0314 + +/** + * Register: XDPDMA_CH1_CNTL + */ +#define XDPDMA_CH1_CNTL 0X0318 +/** + * Register: XDPDMA_CH1_STATUS + */ +#define XDPDMA_CH1_STATUS 0X031C + +/** + * Register: XDPDMA_CH1_VDO + */ +#define XDPDMA_CH1_VDO 0X0320 + +/** + * Register: XDPDMA_CH1_PYLD_SZ + */ +#define XDPDMA_CH1_PYLD_SZ 0X0324 + +/** + * Register: XDPDMA_CH1_DSCR_ID + */ +#define XDPDMA_CH1_DSCR_ID 0X0328 + +/** + * Register: XDPDMA_CH2_DSCR_STRT_ADDRE + */ +#define XDPDMA_CH2_DSCR_STRT_ADDRE 0X0400 + +/** + * Register: XDPDMA_CH2_DSCR_STRT_ADDR + */ +#define XDPDMA_CH2_DSCR_STRT_ADDR 0X0404 + +/** + * Register: XDPDMA_CH2_DSCR_NEXT_ADDRE + */ +#define XDPDMA_CH2_DSCR_NEXT_ADDRE 0X0408 + +/** + * Register: XDPDMA_CH2_DSCR_NEXT_ADDR + */ +#define XDPDMA_CH2_DSCR_NEXT_ADDR 0X040C + +/** + * Register: XDPDMA_CH2_PYLD_CUR_ADDRE + */ +#define XDPDMA_CH2_PYLD_CUR_ADDRE 0X0410 + +/** + * Register: XDPDMA_CH2_PYLD_CUR_ADDR + */ +#define XDPDMA_CH2_PYLD_CUR_ADDR 0X0414 + +/** + * Register: XDPDMA_CH2_CNTL + */ +#define XDPDMA_CH2_CNTL 0X0418 + +/** + * Register: XDPDMA_CH2_STATUS + */ +#define XDPDMA_CH2_STATUS 0X041C + +/** + * Register: XDPDMA_CH2_VDO + */ +#define XDPDMA_CH2_VDO 0X0420 + +/** + * Register: XDPDMA_CH2_PYLD_SZ + */ +#define XDPDMA_CH2_PYLD_SZ 0X0424 + +/** + * Register: XDPDMA_CH2_DSCR_ID + */ +#define XDPDMA_CH2_DSCR_ID 0X0428 + +/** + * Register: XDPDMA_CH3_DSCR_STRT_ADDRE + */ +#define XDPDMA_CH3_DSCR_STRT_ADDRE 0X0500 + +/** + * Register: XDPDMA_CH3_DSCR_STRT_ADDR + */ +#define XDPDMA_CH3_DSCR_STRT_ADDR 0X0504 + +/** + * Register: XDPDMA_CH3_DSCR_NEXT_ADDRE + */ +#define XDPDMA_CH3_DSCR_NEXT_ADDRE 0X0508 + +/** + * Register: XDPDMA_CH3_DSCR_NEXT_ADDR + */ +#define XDPDMA_CH3_DSCR_NEXT_ADDR 0X050C + +/** + * Register: XDPDMA_CH3_PYLD_CUR_ADDRE + */ +#define XDPDMA_CH3_PYLD_CUR_ADDRE 0X0510 + +/** + * Register: XDPDMA_CH3_PYLD_CUR_ADDR + */ +#define XDPDMA_CH3_PYLD_CUR_ADDR 0X0514 + +/** + * Register: XDPDMA_CH3_CNTL + */ +#define XDPDMA_CH3_CNTL 0X0518 +/** + * Register: XDPDMA_CH3_STATUS + */ +#define XDPDMA_CH3_STATUS 0X051C + +/** + * Register: XDPDMA_CH3_VDO + */ +#define XDPDMA_CH3_VDO 0X0520 + +/** + * Register: XDPDMA_CH3_PYLD_SZ + */ +#define XDPDMA_CH3_PYLD_SZ 0X0524 + +/** + * Register: XDPDMA_CH3_DSCR_ID + */ +#define XDPDMA_CH3_DSCR_ID 0X0528 + +/** + * Register: XDPDMA_CH4_DSCR_STRT_ADDRE + */ +#define XDPDMA_CH4_DSCR_STRT_ADDRE 0X0600 + +/** + * Register: XDPDMA_CH4_DSCR_STRT_ADDR + */ +#define XDPDMA_CH4_DSCR_STRT_ADDR 0X0604 +/** + * Register: XDPDMA_CH4_DSCR_NEXT_ADDRE + */ +#define XDPDMA_CH4_DSCR_NEXT_ADDRE 0X0608 + +/** + * Register: XDPDMA_CH4_DSCR_NEXT_ADDR + */ +#define XDPDMA_CH4_DSCR_NEXT_ADDR 0X060C + +/** + * Register: XDPDMA_CH4_PYLD_CUR_ADDRE + */ +#define XDPDMA_CH4_PYLD_CUR_ADDRE 0X0610 + +/** + * Register: XDPDMA_CH4_PYLD_CUR_ADDR + */ +#define XDPDMA_CH4_PYLD_CUR_ADDR 0X0614 + +/** + * Register: XDPDMA_CH4_CNTL + */ +#define XDPDMA_CH4_CNTL 0X0618 + +/** + * Register: XDPDMA_CH4_STATUS + */ +#define XDPDMA_CH4_STATUS 0X061C + +/** + * Register: XDPDMA_CH4_VDO + */ +#define XDPDMA_CH4_VDO 0X0620 + +/** + * Register: XDPDMA_CH4_PYLD_SZ + */ +#define XDPDMA_CH4_PYLD_SZ 0X0624 + +/** + * Register: XDPDMA_CH4_DSCR_ID + */ +#define XDPDMA_CH4_DSCR_ID 0X0628 + +/** + * Register: XDPDMA_CH5_DSCR_STRT_ADDRE + */ +#define XDPDMA_CH5_DSCR_STRT_ADDRE 0X0700 + +/** + * Register: XDPDMA_CH5_DSCR_STRT_ADDR + */ +#define XDPDMA_CH5_DSCR_STRT_ADDR 0X0704 + +/** + * Register: XDPDMA_CH5_DSCR_NEXT_ADDRE + */ +#define XDPDMA_CH5_DSCR_NEXT_ADDRE 0X0708 + +/** + * Register: XDPDMA_CH5_DSCR_NEXT_ADDR + */ +#define XDPDMA_CH5_DSCR_NEXT_ADDR 0X070C + +/** + * Register: XDPDMA_CH5_PYLD_CUR_ADDRE + */ +#define XDPDMA_CH5_PYLD_CUR_ADDRE 0X0710 + +/** + * Register: XDPDMA_CH5_PYLD_CUR_ADDR + */ +#define XDPDMA_CH5_PYLD_CUR_ADDR 0X0714 + +/** + * Register: XDPDMA_CH5_CNTL + */ +#define XDPDMA_CH5_CNTL 0X0718 + +/** + * Register: XDPDMA_CH5_STATUS + */ +#define XDPDMA_CH5_STATUS 0X071C + +/** + * Register: XDPDMA_CH5_VDO + */ +#define XDPDMA_CH5_VDO 0X0720 + +/** + * Register: XDPDMA_CH5_PYLD_SZ + */ +#define XDPDMA_CH5_PYLD_SZ 0X0724 + +/** + * Register: XDPDMA_CH5_DSCR_ID + */ +#define XDPDMA_CH5_DSCR_ID 0X0728 + + +#define XDPDMA_CH_DSCR_STRT_ADDRE_MSB_SHIFT 0 +#define XDPDMA_CH_DSCR_STRT_ADDRE_MSB_WIDTH 16 +#define XDPDMA_CH_DSCR_STRT_ADDRE_MSB_MASK 0XFFFF + + +#define XDPDMA_CH_DSCR_STRT_ADDR_LSB_SHIFT 0 +#define XDPDMA_CH_DSCR_STRT_ADDR_LSB_WIDTH 32 +#define XDPDMA_CH_DSCR_STRT_ADDR_LSB_MASK 0XFFFFFFFF + + +#define XDPDMA_CH_DSCR_NEXT_ADDRE_MSB_SHIFT 0 +#define XDPDMA_CH_DSCR_NEXT_ADDRE_MSB_WIDTH 16 +#define XDPDMA_CH_DSCR_NEXT_ADDRE_MSB_MASK 0XFFFF + + +#define XDPDMA_CH_DSCR_NEXT_ADDR_LSB_SHIFT 0 +#define XDPDMA_CH_DSCR_NEXT_ADDR_LSB_WIDTH 32 +#define XDPDMA_CH_DSCR_NEXT_ADDR_LSB_MASK 0XFFFFFFFF + + +#define XDPDMA_CH_PYLD_CUR_ADDRE_MSB_SHIFT 0 +#define XDPDMA_CH_PYLD_CUR_ADDRE_MSB_WIDTH 16 +#define XDPDMA_CH_PYLD_CUR_ADDRE_MSB_MASK 0XFFFF + +#define XDPDMA_CH_PYLD_CUR_ADDR_LSB_SHIFT 0 +#define XDPDMA_CH_PYLD_CUR_ADDR_LSB_WIDTH 32 +#define XDPDMA_CH_PYLD_CUR_ADDR_LSB_MASK 0XFFFFFFFF + +#define XDPDMA_CH_CNTL_DSCR_AXCACHE_SHIFT 16 +#define XDPDMA_CH_CNTL_DSCR_AXCACHE_WIDTH 4 +#define XDPDMA_CH_CNTL_DSCR_AXCACHE_MASK 0XF0000 + +#define XDPDMA_CH_CNTL_DSCR_AXPROT_SHIFT 14 +#define XDPDMA_CH_CNTL_DSCR_AXPROT_WIDTH 2 +#define XDPDMA_CH_CNTL_DSCR_AXPROT_MASK 0XC000 + +#define XDPDMA_CH_CNTL_QOS_DATA_RD_SHIFT 10 +#define XDPDMA_CH_CNTL_QOS_DATA_RD_WIDTH 4 +#define XDPDMA_CH_CNTL_QOS_DATA_RD_MASK 0X3C00 + +#define XDPDMA_CH_CNTL_QOS_DSCR_RD_SHIFT 6 +#define XDPDMA_CH_CNTL_QOS_DSCR_RD_WIDTH 4 +#define XDPDMA_CH_CNTL_QOS_DSCR_RD_MASK 0X03C0 + +#define XDPDMA_CH_CNTL_QOS_DSCR_WR_SHIFT 2 +#define XDPDMA_CH_CNTL_QOS_DSCR_WR_WIDTH 4 +#define XDPDMA_CH_CNTL_QOS_DSCR_WR_MASK 0X3C + +#define XDPDMA_CH_CNTL_PAUSE_SHIFT 1 +#define XDPDMA_CH_CNTL_PAUSE_WIDTH 1 +#define XDPDMA_CH_CNTL_PAUSE_MASK 0X2 + +#define XDPDMA_CH_CNTL_EN_SHIFT 0 +#define XDPDMA_CH_CNTL_EN_WIDTH 1 +#define XDPDMA_CH_CNTL_EN_MASK 0X1 + + +#define XDPDMA_CH_STATUS_OTRAN_CNT_SHIFT 21 +#define XDPDMA_CH_STATUS_OTRAN_CNT_WIDTH 4 +#define XDPDMA_CH_STATUS_OTRAN_CNT_MASK 0X01E00000 + +#define XDPDMA_CH_STATUS_PREAMBLE_SHIFT 13 +#define XDPDMA_CH_STATUS_PREAMBLE_WIDTH 8 +#define XDPDMA_CH_STATUS_PREAMBLE_MASK 0X1FE000 + +#define XDPDMA_CH_STATUS_EN_DSCR_INTR_SHIFT 12 +#define XDPDMA_CH_STATUS_EN_DSCR_INTR_WIDTH 1 +#define XDPDMA_CH_STATUS_EN_DSCR_INTR_MASK 0X1000 + +#define XDPDMA_CH_STATUS_EN_DSCR_UP_SHIFT 11 +#define XDPDMA_CH_STATUS_EN_DSCR_UP_WIDTH 1 +#define XDPDMA_CH_STATUS_EN_DSCR_UP_MASK 0X0800 + +#define XDPDMA_CH_STATUS_DSCR_DONE_SHIFT 10 +#define XDPDMA_CH_STATUS_DSCR_DONE_WIDTH 1 +#define XDPDMA_CH_STATUS_DSCR_DONE_MASK 0X0400 + +#define XDPDMA_CH_STATUS_IGNR_DONE_SHIFT 9 +#define XDPDMA_CH_STATUS_IGNR_DONE_WIDTH 1 +#define XDPDMA_CH_STATUS_IGNR_DONE_MASK 0X0200 + +#define XDPDMA_CH_STATUS_LDSCR_FRAME_SHIFT 8 +#define XDPDMA_CH_STATUS_LDSCR_FRAME_WIDTH 1 +#define XDPDMA_CH_STATUS_LDSCR_FRAME_MASK 0X0100 + +#define XDPDMA_CH_STATUS_LAST_DSCR_SHIFT 7 +#define XDPDMA_CH_STATUS_LAST_DSCR_WIDTH 1 +#define XDPDMA_CH_STATUS_LAST_DSCR_MASK 0X80 + +#define XDPDMA_CH_STATUS_EN_CRC_SHIFT 6 +#define XDPDMA_CH_STATUS_EN_CRC_WIDTH 1 +#define XDPDMA_CH_STATUS_EN_CRC_MASK 0X40 + +#define XDPDMA_CH_STATUS_MODE_SHIFT 5 +#define XDPDMA_CH_STATUS_MODE_WIDTH 1 +#define XDPDMA_CH_STATUS_MODE_MASK 0X20 + +#define XDPDMA_CH_STATUS_BURST_TYPE_SHIFT 4 +#define XDPDMA_CH_STATUS_BURST_TYPE_WIDTH 1 +#define XDPDMA_CH_STATUS_BURST_TYPE_MASK 0X10 + +#define XDPDMA_CH_STATUS_BURST_LEN_SHIFT 0 +#define XDPDMA_CH_STATUS_BURST_LEN_WIDTH 4 +#define XDPDMA_CH_STATUS_BURST_LEN_MASK 0XF + + +#define XDPDMA_CH_VDO_LINE_LENGTH_SHIFT 14 +#define XDPDMA_CH_VDO_LINE_LENGTH_WIDTH 18 +#define XDPDMA_CH_VDO_LINE_LENGTH_MASK 0XFFFFC000 + +#define XDPDMA_CH_VDO_STRIDE_SHIFT 0 +#define XDPDMA_CH_VDO_STRIDE_WIDTH 14 +#define XDPDMA_CH_VDO_STRIDE_MASK 0X3FFF + +#define XDPDMA_CH_PYLD_SZ_BYTE_SHIFT 0 +#define XDPDMA_CH_PYLD_SZ_BYTE_WIDTH 32 +#define XDPDMA_CH_PYLD_SZ_BYTE_MASK 0XFFFFFFFF + +#define XDPDMA_CH_DSCR_ID_VAL_SHIFT 0 +#define XDPDMA_CH_DSCR_ID_VAL_WIDTH 16 +#define XDPDMA_CH_DSCR_ID_VAL_MASK 0XFFFF + +/** + * Register: XDPDMA_ECO + */ +#define XDPDMA_ECO 0X0FFC + +#define XDPDMA_ECO_VAL_SHIFT 0 +#define XDPDMA_ECO_VAL_WIDTH 32 +#define XDPDMA_ECO_VAL_MASK 0XFFFFFFFF + +/** + * DPDMA descriptor + */ + +#define XDPDMA_DESCRIPTOR_CONTROL_PREAMBLE_SHIFT 0 +#define XDPDMA_DESCRIPTOR_CONTROL_PREAMBLE_WIDTH 8 +#define XDPDMA_DESCRIPTOR_CONTROL_PREAMBLE_MASK 0XFF + +#define XDPDMA_DESCRIPTOR_CONTROL_EN_COMP_INTR_SHIFT 8 +#define XDPDMA_DESCRIPTOR_CONTROL_EN_COMP_INTR_WIDTH 1 +#define XDPDMA_DESCRIPTOR_CONTROL_EN_COMP_INTR_MASK 0X0100 + +#define XDPDMA_DESCRIPTOR_CONTROL_EN_DESC_UPDATE_SHIFT 9 +#define XDPDMA_DESCRIPTOR_CONTROL_EN_DESC_UPDATE_WIDTH 1 +#define XDPDMA_DESCRIPTOR_CONTROL_EN_DESC_UPDATE_MASK 0X0200 + +#define XDPDMA_DESCRIPTOR_CONTROL_IGNORE_DONE_SHIFT 10 +#define XDPDMA_DESCRIPTOR_CONTROL_IGNORE_DONE_WIDTH 1 +#define XDPDMA_DESCRIPTOR_CONTROL_IGNORE_DONE_MASK 0X0400 + +#define XDPDMA_DESCRIPTOR_CONTROL_AXI_BURST_TYPE_SHIFT 11 +#define XDPDMA_DESCRIPTOR_CONTROL_AXI_BURST_TYPE_WIDTH 1 +#define XDPDMA_DESCRIPTOR_CONTROL_AXI_BURST_TYPE_MASK 0X0800 + +#define XDPDMA_DESCRIPTOR_CONTROL_AXACACHE_SHIFT 12 +#define XDPDMA_DESCRIPTOR_CONTROL_AXACACHE_WIDTH 4 +#define XDPDMA_DESCRIPTOR_CONTROL_AXACACHE_MASK 0XF000 + +#define XDPDMA_DESCRIPTOR_CONTROL_AXPROT_SHIFT 16 +#define XDPDMA_DESCRIPTOR_CONTROL_AXPROT_WIDTH 2 +#define XDPDMA_DESCRIPTOR_CONTROL_AXPROT_MASK 0X30000 + +#define XDPDMA_DESCRIPTOR_CONTROL_MODE_SHIFT 18 +#define XDPDMA_DESCRIPTOR_CONTROL_MODE_WIDTH 1 +#define XDPDMA_DESCRIPTOR_CONTROL_MODE_MASK 0X40000 + +#define XDPDMA_DESCRIPTOR_CONTROL_LAST_DESC_SHIFT 19 +#define XDPDMA_DESCRIPTOR_CONTROL_LAST_DESC_WIDTH 1 +#define XDPDMA_DESCRIPTOR_CONTROL_LAST_DESC_MASK 0X80000 + +#define XDPDMA_DESCRIPTOR_CONTROL_ENABLE_CRC_SHIFT 20 +#define XDPDMA_DESCRIPTOR_CONTROL_ENABLE_CRC_WIDTH 1 +#define XDPDMA_DESCRIPTOR_CONTROL_ENABLE_CRC_MASK 0x00100000 + +#define XDPDMA_DESCRIPTOR_CONTROL_LAST_DESC_FRAME_SHIFT 21 +#define XDPDMA_DESCRIPTOR_CONTROL_LAST_DESC_FRAME_WIDTH 1 +#define XDPDMA_DESCRIPTOR_CONTROL_LAST_DESC_FRAME_MASK 0X200000 + +#define XDPDMA_DESCRIPTOR_DSCR_ID_SHIFT 0 +#define XDPDMA_DESCRIPTOR_DSCR_ID_WIDTH 16 +#define XDPDMA_DESCRIPTOR_DSCR_ID_MASK 0XFFFF + +#define XDPDMA_DESCRIPTOR_XFER_SIZE_SHIFT 0 +#define XDPDMA_DESCRIPTOR_XFER_SIZE_WIDTH 32 +#define XDPDMA_DESCRIPTOR_XFER_SIZE_MASK 0x0000FFFF + +#define XDPDMA_DESCRIPTOR_LINE_SIZE_HZ_RES_SHIFT 0 +#define XDPDMA_DESCRIPTOR_LINE_SIZE_HZ_RES_WIDTH 18 +#define XDPDMA_DESCRIPTOR_LINE_SIZE_HZ_RES_MASK 0X3FFFF + +#define XDPDMA_DESCRIPTOR_LINE_SIZE_STRIDE_SHIFT 18 +#define XDPDMA_DESCRIPTOR_LINE_SIZE_STRIDE_WIDTH 14 +#define XDPDMA_DESCRIPTOR_LINE_SIZE_STRIDE_MASK 0XFFFC0000 + +#define XDPDMA_DESCRIPTOR_TS_LSB_SHIFT 0 +#define XDPDMA_DESCRIPTOR_TS_LSB_WIDTH 32 +#define XDPDMA_DESCRIPTOR_TS_LSB_MASK 0XFFFFFFFF + +#define XDPDMA_DESCRIPTOR_TS_MSB_SHIFT 0 +#define XDPDMA_DESCRIPTOR_TS_MSB_WIDTH 32 +#define XDPDMA_DESCRIPTOR_TS_MSB_MASK 0XFFFFFFFF + +#define XDPDMA_DESCRIPTOR_TS_MSB_TS_SHIFT 0 +#define XDPDMA_DESCRIPTOR_TS_MSB_TS_WIDTH 9 +#define XDPDMA_DESCRIPTOR_TS_MSB_TS_MASK 0X01FF + +#define XDPDMA_DESCRIPTOR_TS_MSB_STATUS_SHIFT 31 +#define XDPDMA_DESCRIPTOR_TS_MSB_STATUS_WIDTH 1 +#define XDPDMA_DESCRIPTOR_TS_MSB_STATUS_MASK 0X80000000 + +#define XDPDMA_DESCRIPTOR_ADDR_EXT_DSC_NXT_SHIFT 0 +#define XDPDMA_DESCRIPTOR_ADDR_EXT_DSC_NXT_WIDTH 16 +#define XDPDMA_DESCRIPTOR_ADDR_EXT_DSC_NXT_MASK 0XFFFF + +#define XDPDMA_DESCRIPTOR_ADDR_EXT_SRC_ADDR_EXT_SHIFT 16 +#define XDPDMA_DESCRIPTOR_ADDR_EXT_SRC_ADDR_EXT_WIDTH 16 +#define XDPDMA_DESCRIPTOR_ADDR_EXT_SRC_ADDR_EXT_MASK 0XFFFF0000 + +#define XDPDMA_DESCRIPTOR_ADDR_EXT23_2_SHIFT 0 +#define XDPDMA_DESCRIPTOR_ADDR_EXT23_2_WIDTH 16 +#define XDPDMA_DESCRIPTOR_ADDR_EXT23_2_MASK 0XFFFF + +#define XDPDMA_DESCRIPTOR_ADDR_EXT23_3_SHIFT 16 +#define XDPDMA_DESCRIPTOR_ADDR_EXT23_3_WIDTH 16 +#define XDPDMA_DESCRIPTOR_ADDR_EXT23_3_MASK 0xFFFF0000 + +#define XDPDMA_DESCRIPTOR_ADDR_EXT45_4_SHIFT 0 +#define XDPDMA_DESCRIPTOR_ADDR_EXT45_4_WIDTH 16 +#define XDPDMA_DESCRIPTOR_ADDR_EXT45_4_MASK 0XFFFF + +#define XDPDMA_DESCRIPTOR_ADDR_EXT45_5_SHIFT 16 +#define XDPDMA_DESCRIPTOR_ADDR_EXT45_5_WIDTH 16 +#define XDPDMA_DESCRIPTOR_ADDR_EXT45_5_MASK 0XFFFF0000 + +#define XDPDMA_DESCRIPTOR_NEXT_DESR_SHIFT 0 +#define XDPDMA_DESCRIPTOR_NEXT_DESR_WIDTH 32 +#define XDPDMA_DESCRIPTOR_NEXT_DESR_MASK 0XFFFFFFFF + +#define XDPDMA_DESCRIPTOR_SRC_ADDR_SHIFT 0 +#define XDPDMA_DESCRIPTOR_SRC_ADDR_WIDTH 32 +#define XDPDMA_DESCRIPTOR_SRC_ADDR_MASK 0XFFFFFFFF + +#define XDPDMA_DESCRIPTOR_SRC_ADDR2_SHIFT 0 +#define XDPDMA_DESCRIPTOR_SRC_ADDR2_WIDTH 32 +#define XDPDMA_DESCRIPTOR_SRC_ADDR2_MASK 0XFFFFFFFF + +#define XDPDMA_DESCRIPTOR_SRC_ADDR3_SHIFT 0 +#define XDPDMA_DESCRIPTOR_SRC_ADDR3_WIDTH 32 +#define XDPDMA_DESCRIPTOR_SRC_ADDR3_MASK 0XFFFFFFFF + +#define XDPDMA_DESCRIPTOR_SRC_ADDR4_SHIFT 0 +#define XDPDMA_DESCRIPTOR_SRC_ADDR4_WIDTH 32 +#define XDPDMA_DESCRIPTOR_SRC_ADDR4_MASK 0XFFFFFFFF + +#define XDPDMA_DESCRIPTOR_SRC_ADDR5_SHIFT 0 +#define XDPDMA_DESCRIPTOR_SRC_ADDR5_WIDTH 32 +#define XDPDMA_DESCRIPTOR_SRC_ADDR5_MASK 0XFFFFFFFF + +#define XDPDMA_TRIGGER_EN 1 +#define XDPDMA_RETRIGGER_EN 2 +#define XDPDMA_TRIGGER_DONE 0 +#define XDPDMA_RETRIGGER_DONE 0 +/* @} */ + +/******************* Macros (Inline Functions Definitions ********************/ + +/** @name Register access macro definitions. + * @{ + */ +#define XDpDma_In32 Xil_In32 +#define XDpDma_Out32 Xil_Out32 +/* @} */ + +/******************************************************************************/ +/** + * This is a low-level function that reads from the specified register. + * + * @param BaseAddress is the base address of the device. + * @param RegOffset is the register offset to be read from. + * + * @return The 32-bit value of the specified register. + * + * @note C-style signature: + * u32 XDpDma_ReadReg(u32 BaseAddress, u32 RegOffset + * +*******************************************************************************/ +#define XDpDma_ReadReg(BaseAddress, RegOffset) \ + XDpDma_In32((BaseAddress) + (RegOffset)) + +/******************************************************************************/ +/** + * This is a low-level function that writes to the specified register. + * + * @param BaseAddress is the base address of the device. + * @param RegOffset is the register offset to write to. + * @param Data is the 32-bit data to write to the specified register. + * + * @return None. + * + * @note C-style signature: + * void XDpDma_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) + * +*******************************************************************************/ +#define XDpDma_WriteReg(BaseAddress, RegOffset, Data) \ + XDpDma_Out32((BaseAddress) + (RegOffset), (Data)) + + +/******************************************************************************/ +/** + * This is a low-level function that writes to the specified register. + * + * @param BaseAddress is the base address of the device. + * @param RegOffset is the register offset to write to. + * @param Data is the 32-bit data to write to the specified register. + * @param Mask is the 32-bit field to which data is to be written + * + * @return None. + * + * @note C-style signature: + * void XDpDma_ReadModifyWrite(u32 BaseAddress, + * u32 RegOffset, u32 Data) + * +*******************************************************************************/ +#define XDpDma_ReadModifyWrite(BaseAddress, RegOffset, Data, Mask) \ + XDpDma_WriteReg((BaseAddress), (RegOffset), \ + ((XDpDma_ReadReg(BaseAddress, RegOffset) & \ + ~(Mask)) | Data)) + +#ifdef __cplusplus +} +#endif + + +#endif /* _XDPDMAHW_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/dpdma_v1_0/src/xdpdma_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/dpdma_v1_0/src/xdpdma_intr.c new file mode 100644 index 0000000..80b175d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/dpdma_v1_0/src/xdpdma_intr.c
@@ -0,0 +1,166 @@ +/******************************************************************************* + * + * Copyright (C) 2017 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xdppsu_intr.c + * + * This file contains functions related to XDpPsu interrupt handling. + * + * @note None. + * + * <pre> + * MODIFICATION HISTORY: + * + * Ver Who Date Changes + * ----- ---- -------- ----------------------------------------------- + * 1.0 aad 01/17/17 Initial release. + * </pre> + * +*******************************************************************************/ + +/******************************* Include Files ********************************/ +#include "xdpdma.h" + + +/*************************************************************************/ +/** + * + * This function enables the interrupts that are required. + * + * @param InstancePtr is pointer to the instance of DPDMA + * + * @return None. + * + * @note None. + * + * **************************************************************************/ +void XDpDma_InterruptEnable(XDpDma *InstancePtr, u32 Mask) +{ + XDpDma_WriteReg(InstancePtr->Config.BaseAddr, XDPDMA_IEN, Mask); +} + +/*************************************************************************/ +/** + * + * This function handles the interrupts generated by DPDMA + * + * @param InstancePtr is pointer to the instance of the DPDMA + * + * @return None. + * + * @note None. + * + * **************************************************************************/ +void XDpDma_InterruptHandler(XDpDma *InstancePtr) +{ + u32 RegVal; + RegVal = XDpDma_ReadReg(InstancePtr->Config.BaseAddr, + XDPDMA_ISR); + if(RegVal & XDPDMA_ISR_VSYNC_INT_MASK) { + XDpDma_VSyncHandler(InstancePtr); + } + + if(RegVal & XDPDMA_ISR_DSCR_DONE4_MASK) { + XDpDma_SetChannelState(InstancePtr, AudioChan0, XDPDMA_DISABLE); + InstancePtr->Audio[0].Current = NULL; + XDpDma_WriteReg(InstancePtr->Config.BaseAddr, XDPDMA_ISR, + XDPDMA_ISR_DSCR_DONE4_MASK); + } + + if(RegVal & XDPDMA_ISR_DSCR_DONE5_MASK) { + XDpDma_SetChannelState(InstancePtr, AudioChan1, XDPDMA_DISABLE); + InstancePtr->Audio[1].Current = NULL; + XDpDma_WriteReg(InstancePtr->Config.BaseAddr, XDPDMA_ISR, + XDPDMA_ISR_DSCR_DONE5_MASK); + } +} + +/*************************************************************************/ +/** + * + * This function handles frame new frames on VSync + * + * @param InstancePtr is pointer to the instance of the driver. + * + * @return None. + * + * @note None. + * + * **************************************************************************/ +void XDpDma_VSyncHandler(XDpDma *InstancePtr) +{ + Xil_AssertVoid(InstancePtr != NULL); + + /* Video Channel Trigger/Retrigger Handler */ + if(InstancePtr->Video.TriggerStatus == XDPDMA_TRIGGER_EN) { + XDpDma_SetupChannel(InstancePtr, VideoChan); + XDpDma_SetChannelState(InstancePtr, VideoChan, + XDPDMA_ENABLE); + XDpDma_Trigger(InstancePtr, VideoChan); + } + else if(InstancePtr->Video.TriggerStatus == XDPDMA_RETRIGGER_EN) { + XDpDma_SetupChannel(InstancePtr, VideoChan); + XDpDma_ReTrigger(InstancePtr, VideoChan); + } + + /* Graphics Channel Trigger/Retrigger Handler */ + if(InstancePtr->Gfx.TriggerStatus == XDPDMA_TRIGGER_EN) { + XDpDma_SetupChannel(InstancePtr, GraphicsChan); + XDpDma_SetChannelState(InstancePtr, GraphicsChan, + XDPDMA_ENABLE); + XDpDma_Trigger(InstancePtr, GraphicsChan); + } + else if(InstancePtr->Gfx.TriggerStatus == XDPDMA_RETRIGGER_EN) { + XDpDma_SetupChannel(InstancePtr, GraphicsChan); + XDpDma_ReTrigger(InstancePtr, GraphicsChan); + } + + /* Audio Channel 0 Trigger Handler */ + if(InstancePtr->Audio[0].TriggerStatus == XDPDMA_TRIGGER_EN) { + XDpDma_SetupChannel(InstancePtr, AudioChan0); + XDpDma_SetChannelState(InstancePtr, AudioChan0, + XDPDMA_ENABLE); + XDpDma_Trigger(InstancePtr, AudioChan0); + } + + /* Audio Channel 1 Trigger Handler */ + if(InstancePtr->Audio[1].TriggerStatus == XDPDMA_TRIGGER_EN) { + XDpDma_SetupChannel(InstancePtr, AudioChan1); + XDpDma_SetChannelState(InstancePtr, AudioChan1, + XDPDMA_ENABLE); + XDpDma_Trigger(InstancePtr, AudioChan1); + } + /* Clear VSync Interrupt */ + XDpDma_WriteReg(InstancePtr->Config.BaseAddr, XDPDMA_ISR, + XDPDMA_ISR_VSYNC_INT_MASK); +}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/dpdma_v1_0/src/xdpdma_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/dpdma_v1_0/src/xdpdma_sinit.c new file mode 100644 index 0000000..8f06268 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/dpdma_v1_0/src/xdpdma_sinit.c
@@ -0,0 +1,96 @@ +/******************************************************************************* + * + * Copyright (C) 2017 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xdpdma_sinit.c + * @addtogroup dpdma_v1_0 + * @{ + * + * This file contains static initialization methods for the XDpDma driver. + * + * @note None. + * + * <pre> + * MODIFICATION HISTORY: + * + * Ver Who Date Changes + * ----- ---- -------- ----------------------------------------------- + * 1.0 aad 01/20/15 Initial release. + * </pre> + * +*******************************************************************************/ + +/******************************* Include Files ********************************/ + +#include "xdpdma.h" +#include "xparameters.h" + +/*************************** Variable Declarations ****************************/ + +/** + * A table of configuration structures containing the configuration information + * for each DisplayPort TX core in the system. + */ +extern XDpDma_Config XDpDma_ConfigTable[XPAR_XDPDMA_NUM_INSTANCES]; + +/**************************** Function Definitions ****************************/ + +/******************************************************************************/ +/** + * This function looks for the device configuration based on the unique device + * ID. The table XDpDma_ConfigTable[] contains the configuration information for + * each device in the system. + * + * @param DeviceId is the unique device ID of the device being looked up. + * + * @return A pointer to the configuration table entry corresponding to the + * given device ID, or NULL if no match is found. + * + * @note None. + * +*******************************************************************************/ +XDpDma_Config *XDpDma_LookupConfig(u16 DeviceId) +{ + XDpDma_Config *CfgPtr; + u32 Index; + + for (Index = 0; Index < XPAR_XDPDMA_NUM_INSTANCES; Index++) { + if (XDpDma_ConfigTable[Index].DeviceId == DeviceId) { + CfgPtr = &XDpDma_ConfigTable[Index]; + break; + } + } + + return CfgPtr; +} +/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/Makefile rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/Makefile
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps.c similarity index 98% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps.c index 26df03c..c013c49 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps.c
@@ -33,7 +33,7 @@ /** * * @file xemacps.c -* @addtogroup emacps_v3_1 +* @addtogroup emacps_v3_7 * @{ * * The XEmacPs driver. Functions in this file are the minimum required functions @@ -52,6 +52,8 @@ * Disable extended mode. Perform all 64 bit changes under * check for arch64. * 3.1 hk 08/10/15 Update upper 32 bit tx and rx queue ptr registers +* 3.5 hk 08/14/17 Update cache coherency information of the interface in +* its config structure. * * </pre> ******************************************************************************/ @@ -107,6 +109,7 @@ /* Set device base address and ID */ InstancePtr->Config.DeviceId = CfgPtr->DeviceId; InstancePtr->Config.BaseAddress = EffectiveAddress; + InstancePtr->Config.IsCacheCoherent = CfgPtr->IsCacheCoherent; /* Set callbacks to an initial stub routine */ InstancePtr->SendHandler = ((XEmacPs_Handler)((void*)XEmacPs_StubHandler));
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps.h similarity index 96% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps.h index f12092b..6d4b15b 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps.h
@@ -33,7 +33,7 @@ /** * * @file xemacps.h -* @addtogroup emacps_v3_1 +* @addtogroup emacps_v3_7 * @{ * @details * @@ -316,6 +316,21 @@ * there is no error. CR# 869403 * 08/10/15 Update upper 32 bit tx and rx queue ptr registers. * 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC. + * 3.4 ms 01/23/17 Modified xil_printf statement in main function for all + * examples to ensure that "Successfully ran" and "Failed" + * strings are available in all examples. This is a fix + * for CR-965028. + * ms 03/17/17 Modified text file in examples folder for doxygen + * generation. + * ms 04/05/17 Added tabspace for return statements in functions of + * xemacps_ieee1588_example.c for proper documentation + * while generating doxygen. + * 3.5 hk 08/14/17 Update cache coherency information of the interface in + * its config structure. + * 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is + * changed to volatile. + * Add API XEmacPs_BdRingPtrReset() to reset pointers + * * </pre> * ****************************************************************************/ @@ -513,6 +528,8 @@ typedef struct { u16 DeviceId; /**< Unique ID of device */ UINTPTR BaseAddress;/**< Physical base address of IPIF registers */ + u8 IsCacheCoherent; /**< Applicable only to A53 in EL1 mode; + * describes whether Cache Coherent or not */ } XEmacPs_Config;
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_bd.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_bd.h similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_bd.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_bd.h index 52c5f7e..83f9a87 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_bd.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_bd.h
@@ -33,7 +33,7 @@ /** * * @file xemacps_bd.h -* @addtogroup emacps_v3_1 +* @addtogroup emacps_v3_7 * @{ * * This header provides operations to manage buffer descriptors in support
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_bdring.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_bdring.c similarity index 97% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_bdring.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_bdring.c index d837e1d..3536873 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_bdring.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_bdring.c
@@ -33,7 +33,7 @@ /** * * @file xemacps_bdring.c -* @addtogroup emacps_v3_1 +* @addtogroup emacps_v3_7 * @{ * * This file implements buffer descriptor ring related functions. @@ -57,6 +57,8 @@ * from uncached area. Fix for CR #663885. * 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture. * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. +* 3.6 rb 09/08/17 Add XEmacPs_BdRingPtrReset() API to reset BD ring +* pointers * * </pre> ******************************************************************************/ @@ -505,7 +507,7 @@ XEmacPs_Bd * BdSetPtr) { LONG Status; - (void *)BdSetPtr; + (void) BdSetPtr; Xil_AssertNonvoid(RingPtr != NULL); Xil_AssertNonvoid(BdSetPtr != NULL); @@ -1072,4 +1074,29 @@ *TempPtr = DataValueTx; } } + +/*****************************************************************************/ +/** + * Reset BD ring head and tail pointers. + * + * @param RingPtr is the instance to be worked on. + * @param VirtAddr is the virtual base address of the user memory region. + * + * @note + * Should be called after XEmacPs_Stop() + * + * @note + * C-style signature: + * void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc) + * + *****************************************************************************/ +void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc) +{ + RingPtr->FreeHead = virtaddrloc; + RingPtr->PreHead = virtaddrloc; + RingPtr->HwHead = virtaddrloc; + RingPtr->HwTail = virtaddrloc; + RingPtr->PostHead = virtaddrloc; +} + /** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_bdring.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_bdring.h similarity index 97% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_bdring.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_bdring.h index de78cf2..b89e898 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_bdring.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_bdring.h
@@ -33,7 +33,7 @@ /** * * @file xemacps_bdring.h -* @addtogroup emacps_v3_1 +* @addtogroup emacps_v3_7 * @{ * * The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs @@ -47,6 +47,8 @@ * 1.00a wsy 01/10/10 First release * 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture. * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. +* 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is +* changed to volatile. * * </pre> * @@ -81,7 +83,7 @@ XEmacPs_Bd *BdaRestart; /**< BDA to load when channel is started */ - u32 HwCnt; /**< Number of BDs in work group */ + volatile u32 HwCnt; /**< Number of BDs in work group */ u32 PreCnt; /**< Number of BDs in pre-work group */ u32 FreeCnt; /**< Number of allocatable BDs in the free group */ u32 PostCnt; /**< Number of BDs in post-work group */ @@ -228,6 +230,7 @@ XEmacPs_Bd ** BdSetPtr); LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction); +void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc); #ifdef __cplusplus }
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_control.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_control.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_control.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_control.c index f52451a..8217a45 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_control.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_control.c
@@ -33,7 +33,7 @@ /** * * @file xemacps_control.c -* @addtogroup emacps_v3_1 +* @addtogroup emacps_v3_7 * @{ * * Functions in this file implement general purpose command and control related
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_g.c similarity index 89% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_g.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_g.c index db734b9..e58610f 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_g.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_g.c
@@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,11 +44,12 @@ * The configuration table for devices */ -XEmacPs_Config XEmacPs_ConfigTable[] = +XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES] = { { XPAR_PSU_ETHERNET_3_DEVICE_ID, - XPAR_PSU_ETHERNET_3_BASEADDR + XPAR_PSU_ETHERNET_3_BASEADDR, + XPAR_PSU_ETHERNET_3_IS_CACHE_COHERENT } };
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_hw.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_hw.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_hw.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_hw.c index daba383..00e79a5 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_hw.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_hw.c
@@ -33,7 +33,7 @@ /** * * @file xemacps_hw.c -* @addtogroup emacps_v3_1 +* @addtogroup emacps_v3_7 * @{ * * This file contains the implementation of the ethernet interface reset sequence
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_hw.h similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_hw.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_hw.h index 953cc62..e535470 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_hw.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_hw.h
@@ -33,7 +33,7 @@ /** * * @file xemacps_hw.h -* @addtogroup emacps_v3_1 +* @addtogroup emacps_v3_7 * @{ * * This header file contains identifiers and low-level driver functions (or
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_intr.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_intr.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_intr.c index 59636c4..9c355a1 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_intr.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_intr.c
@@ -33,7 +33,7 @@ /** * * @file xemacps_intr.c -* @addtogroup emacps_v3_1 +* @addtogroup emacps_v3_7 * @{ * * Functions in this file implement general purpose interrupt processing related
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_sinit.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_sinit.c index 1bc5b3b..e2d2078 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_sinit.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_sinit.c
@@ -33,7 +33,7 @@ /** * * @file xemacps_sinit.c -* @addtogroup emacps_v3_1 +* @addtogroup emacps_v3_7 * @{ * * This file contains lookup method by device ID when success, it returns
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/Makefile rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/Makefile
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops.c index 90eedb8..7b6fe2e 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops.c
@@ -33,7 +33,7 @@ /** * * @file xgpiops.c -* @addtogroup gpiops_v3_1 +* @addtogroup gpiops_v3_3 * @{ * * The XGpioPs driver. Functions in this file are the minimum required functions
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops.h similarity index 94% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops.h index 1026155..fda562d 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops.h
@@ -1,3 +1,4 @@ + /****************************************************************************** * * Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. @@ -33,7 +34,7 @@ /** * * @file xgpiops.h -* @addtogroup gpiops_v3_1 +* @addtogroup gpiops_v3_3 * @{ * @details * @@ -97,7 +98,15 @@ * passed to APIs. CR# 822636 * 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. * 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980. -* +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* ms 04/05/17 Added tabspace for return statements in functions of +* gpiops examples for proper documentation while +* generating doxygen. +* 3.3 ms 04/17/17 Added notes about gpio input and output pin description +* for zcu102 and zc702 boards in polled and interrupt +* example, configured Interrupt pin to input pin for +* proper functioning of interrupt example. * </pre> * ******************************************************************************/
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops_g.c similarity index 93% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_g.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops_g.c index 38a5b93..a518a70 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_g.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops_g.c
@@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,7 +44,7 @@ * The configuration table for devices */ -XGpioPs_Config XGpioPs_ConfigTable[] = +XGpioPs_Config XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES] = { { XPAR_PSU_GPIO_0_DEVICE_ID,
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_hw.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops_hw.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_hw.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops_hw.c index d7a5e00..8961c42 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_hw.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops_hw.c
@@ -33,7 +33,7 @@ /** * * @file xgpiops_hw.c -* @addtogroup gpiops_v3_1 +* @addtogroup gpiops_v3_3 * @{ * * This file contains low level GPIO functions.
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops_hw.h similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_hw.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops_hw.h index 81e8d6a..ff01906 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_hw.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops_hw.h
@@ -33,7 +33,7 @@ /** * * @file xgpiops_hw.h -* @addtogroup gpiops_v3_1 +* @addtogroup gpiops_v3_3 * @{ * * This header file contains the identifiers and basic driver functions (or
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops_intr.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_intr.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops_intr.c index c07381b..a8b0a56 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_intr.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops_intr.c
@@ -33,7 +33,7 @@ /** * * @file xgpiops_intr.c -* @addtogroup gpiops_v3_1 +* @addtogroup gpiops_v3_3 * @{ * * This file contains functions related to GPIO interrupt handling. @@ -722,7 +722,7 @@ ******************************************************************************/ void StubHandler(void *CallBackRef, u32 Bank, u32 Status) { - (void*) CallBackRef; + (void) CallBackRef; (void) Bank; (void) Status;
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops_selftest.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_selftest.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops_selftest.c index da1973a..378524c 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_selftest.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops_selftest.c
@@ -33,7 +33,7 @@ /** * * @file xgpiops_selftest.c -* @addtogroup gpiops_v3_1 +* @addtogroup gpiops_v3_3 * @{ * * This file contains a diagnostic self-test function for the XGpioPs driver.
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_sinit.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops_sinit.c index 2ca0083..4cc0c39 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_sinit.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops_sinit.c
@@ -33,7 +33,7 @@ /** * * @file xgpiops_sinit.c -* @addtogroup gpiops_v3_1 +* @addtogroup gpiops_v3_3 * @{ * * This file contains the implementation of the XGpioPs driver's static
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/Makefile rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/Makefile
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps.c index 1c68191..4f2b592 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps.c
@@ -33,7 +33,7 @@ /** * * @file xiicps.c -* @addtogroup iicps_v3_0 +* @addtogroup iicps_v3_5 * @{ * * Contains implementation of required functions for the XIicPs driver.
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps.h similarity index 98% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps.h index b261934..cc837a1 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps.h
@@ -33,7 +33,7 @@ /** * * @file xiicps.h -* @addtogroup iicps_v3_0 +* @addtogroup iicps_v3_5 * @{ * @details * @@ -184,6 +184,8 @@ * 02/18/15 Implemented larger data transfer using repeated start * in Zynq UltraScale MP. * 3.3 kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance. +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. * * </pre> *
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_g.c similarity index 93% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_g.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_g.c index f449e0e..1a469d0 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_g.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_g.c
@@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,7 +44,7 @@ * The configuration table for devices */ -XIicPs_Config XIicPs_ConfigTable[] = +XIicPs_Config XIicPs_ConfigTable[XPAR_XIICPS_NUM_INSTANCES] = { { XPAR_PSU_I2C_0_DEVICE_ID,
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_hw.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_hw.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_hw.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_hw.c index a1dba8e..2d85e14 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_hw.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_hw.c
@@ -33,7 +33,7 @@ /** * * @file xiicps_hw.c -* @addtogroup iicps_v3_0 +* @addtogroup iicps_v3_5 * @{ * * Contains implementation of required functions for providing the reset sequence
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_hw.h similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_hw.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_hw.h index 3b00cf8..d1eee82 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_hw.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_hw.h
@@ -33,7 +33,7 @@ /** * * @file xiicps_hw.h -* @addtogroup iicps_v3_0 +* @addtogroup iicps_v3_5 * @{ * * This header file contains the hardware definition for an IIC device.
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_intr.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_intr.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_intr.c index 5231049..7f38591 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_intr.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_intr.c
@@ -33,7 +33,7 @@ /** * * @file xiicps_intr.c -* @addtogroup iicps_v3_0 +* @addtogroup iicps_v3_5 * @{ * * Contains functions of the XIicPs driver for interrupt-driven transfers.
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_master.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_master.c similarity index 98% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_master.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_master.c index 7824d86..faa8528 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_master.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_master.c
@@ -33,7 +33,7 @@ /** * * @file xiicps_master.c -* @addtogroup iicps_v3_0 +* @addtogroup iicps_v3_5 * @{ * * Handles master mode transfers. @@ -63,7 +63,8 @@ * 02/18/15 Implemented larger data transfer using repeated start * in Zynq UltraScale MP. * 3.3 kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance. -* +* 3.6 ask 09/03/18 In XIicPs_MasterRecvPolled, set transfer size register +* before slave address. Fix for CR996440. * </pre> * ******************************************************************************/ @@ -424,7 +425,6 @@ IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET); XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg); - XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr); /* * Set up the transfer size register so the slave knows how much @@ -440,6 +440,9 @@ ByteCountVar); } + + XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr); + /* * Intrs keeps all the error-related interrupts. */ @@ -633,6 +636,11 @@ & (~XIICPS_CR_SLVMON_MASK)); /* + * wait for slv monitor control bit to be clear + */ + while (XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET) + & XIICPS_CR_SLVMON_MASK); + /* * Clear interrupt flag for slave monitor interrupt. */ XIicPs_DisableInterrupts(BaseAddr, XIICPS_IXR_SLV_RDY_MASK);
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_options.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_options.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_options.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_options.c index 1ebd786..c9237db 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_options.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_options.c
@@ -33,7 +33,7 @@ /** * * @file xiicps_options.c -* @addtogroup iicps_v3_0 +* @addtogroup iicps_v3_5 * @{ * * Contains functions for the configuration of the XIccPs driver.
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_selftest.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_selftest.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_selftest.c index dd57a1a..31e02b5 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_selftest.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_selftest.c
@@ -33,7 +33,7 @@ /** * * @file xiicps_selftest.c -* @addtogroup iicps_v3_0 +* @addtogroup iicps_v3_5 * @{ * * This component contains the implementation of selftest functions for the
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_sinit.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_sinit.c index 7d7dada..d8fbc4c 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_sinit.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_sinit.c
@@ -33,7 +33,7 @@ /** * * @file xiicps_sinit.c -* @addtogroup iicps_v3_0 +* @addtogroup iicps_v3_5 * @{ * * The implementation of the XIicPs component's static initialization
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_slave.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_slave.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_slave.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_slave.c index fef640b..adc40a4 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_slave.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_slave.c
@@ -32,7 +32,7 @@ /*****************************************************************************/ /** * @file xiicps_slave.c -* @addtogroup iicps_v3_0 +* @addtogroup iicps_v3_5 * @{ * * Handles slave transfers
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_3/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/Makefile rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_3/src/Makefile
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_3/src/xipipsu.c similarity index 87% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_3/src/xipipsu.c index 7c9d98a..06d9ced 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_3/src/xipipsu.c
@@ -33,7 +33,7 @@ /** * * @file xipipsu.c -* @addtogroup ipipsu_v1_0 +* @addtogroup ipipsu_v2_3 * @{ * * This file contains the implementation of the interface functions for XIpiPsu @@ -48,6 +48,7 @@ * 2.0 mjr 01/22/16 Fixed response buffer address * calculation. CR# 932582. * 2.1 kvn 05/05/16 Modified code for MISRA-C:2012 Compliance +* 2.2 kvn 02/17/17 Add support for updating ConfigTable at run time * </pre> * *****************************************************************************/ @@ -56,6 +57,9 @@ #include "xipipsu.h" #include "xipipsu_hw.h" +/************************** Variable Definitions *****************************/ +extern XIpiPsu_Config XIpiPsu_ConfigTable[XPAR_XIPIPSU_NUM_INSTANCES]; + /****************************************************************************/ /** * Initialize the Instance pointer based on a given Config Pointer @@ -350,4 +354,39 @@ return Status; } + +/*****************************************************************************/ +/** +* +* Set up the device configuration based on the unique device ID. A table +* contains the configuration info for each device in the system. +* +* @param DeviceId contains the ID of the device to set up the +* configuration for. +* +* @return A pointer to the device configuration for the specified +* device ID. See xipipsu.h for the definition of +* XIpiPsu_Config. +* +* @note This is for safety use case where in this function has to +* be called before CfgInitialize. So that driver will be +* initialized with the provided configuration. For non-safe +* use cases, this is not needed. +* +******************************************************************************/ +void XIpiPsu_SetConfigTable(u32 DeviceId, XIpiPsu_Config *ConfigTblPtr) +{ + u32 Index; + + Xil_AssertVoid(ConfigTblPtr != NULL); + + for (Index = 0U; Index < XPAR_XIPIPSU_NUM_INSTANCES; Index++) { + if (XIpiPsu_ConfigTable[Index].DeviceId == DeviceId) { + XIpiPsu_ConfigTable[Index].BaseAddress = ConfigTblPtr->BaseAddress; + XIpiPsu_ConfigTable[Index].BitMask = ConfigTblPtr->BitMask; + XIpiPsu_ConfigTable[Index].BufferIndex = ConfigTblPtr->BufferIndex; + XIpiPsu_ConfigTable[Index].IntId = ConfigTblPtr->IntId; + } + } +} /** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_3/src/xipipsu.h similarity index 92% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_3/src/xipipsu.h index 0253b9a..83701f4 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_3/src/xipipsu.h
@@ -32,7 +32,7 @@ /*****************************************************************************/ /** * @file xipipsu.h -* @addtogroup ipipsu_v1_0 +* @addtogroup ipipsu_v2_3 * @{ * @details * @@ -76,7 +76,23 @@ * @note XIpiPsu_Reset can be used at startup to clear the status and * disable all sources * - */ + * <pre> + * MODIFICATION HISTORY: + * + * Ver Who Date Changes + * ---- --- -------- -------------------------------------------------- + * 2.2 ms 01/23/17 Modified xil_printf statement in main function for all + * examples to ensure that "Successfully ran" and "Failed" + * strings are available in all examples. This is a fix + * for CR-965028. + * kvn 02/17/17 Add support for updating ConfigTable at run time + * ms 03/17/17 Added readme.txt file in examples folder for doxygen + * generation. + * 2.3 ms 04/11/17 Modified tcl file to add suffix U for all macro + * definitions of ipipsu in xparameters.h + * </pre> + * + *****************************************************************************/ /*****************************************************************************/ #ifndef XIPIPSU_H_ #define XIPIPSU_H_ @@ -276,6 +292,7 @@ XStatus XIpiPsu_WriteMessage(XIpiPsu *InstancePtr, u32 DestCpuMask, u32 *MsgPtr, u32 MsgLength, u8 BufferType); +void XIpiPsu_SetConfigTable(u32 DeviceId, XIpiPsu_Config *ConfigTblPtr); #endif /* XIPIPSU_H_ */ /** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_3/src/xipipsu_g.c similarity index 86% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu_g.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_3/src/xipipsu_g.c index d40c925..f71017c 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu_g.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_3/src/xipipsu_g.c
@@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,7 +44,7 @@ * The configuration table for devices */ -XIpiPsu_Config XIpiPsu_ConfigTable[] = +XIpiPsu_Config XIpiPsu_ConfigTable[XPAR_XIPIPSU_NUM_INSTANCES] = { { @@ -83,22 +83,6 @@ { XPAR_PSU_IPI_6_BIT_MASK, XPAR_PSU_IPI_6_BUFFER_INDEX - }, - { - XPAR_PSU_IPI_7_BIT_MASK, - XPAR_PSU_IPI_7_BUFFER_INDEX - }, - { - XPAR_PSU_IPI_8_BIT_MASK, - XPAR_PSU_IPI_8_BUFFER_INDEX - }, - { - XPAR_PSU_IPI_9_BIT_MASK, - XPAR_PSU_IPI_9_BUFFER_INDEX - }, - { - XPAR_PSU_IPI_10_BIT_MASK, - XPAR_PSU_IPI_10_BUFFER_INDEX } } }
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_3/src/xipipsu_hw.h similarity index 95% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu_hw.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_3/src/xipipsu_hw.h index b4c02b6..5a32021 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu_hw.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_3/src/xipipsu_hw.h
@@ -32,7 +32,7 @@ /** * * @file xipipsu_hw.h -* @addtogroup ipipsu_v1_0 +* @addtogroup ipipsu_v2_3 * @{ * * This file contains macro definitions for low level HW related params @@ -62,8 +62,8 @@ #define XIPIPSU_BUFFER_OFFSET_TARGET (32U * 2U) #define XIPIPSU_BUFFER_OFFSET_RESPONSE (32U) -/* Max Number of IPI slots on the device */ -#define XIPIPSU_MAX_TARGETS 11 +/* Number of IPI slots enabled on the device */ +#define XIPIPSU_MAX_TARGETS XPAR_XIPIPSU_NUM_TARGETS /* Register Offsets for each member of IPI Register Set */ #define XIPIPSU_TRIG_OFFSET 0x00U
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_3/src/xipipsu_sinit.c similarity index 98% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu_sinit.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_3/src/xipipsu_sinit.c index ae09004..6f52a63 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu_sinit.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_3/src/xipipsu_sinit.c
@@ -32,7 +32,7 @@ /** * * @file xipipsu_sinit.c -* @addtogroup ipipsu_v1_0 +* @addtogroup ipipsu_v2_3 * @{ * * The implementation of the XIpiPsu component's static initialization
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_7/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/Makefile rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_7/src/Makefile
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_7/src/xqspipsu.c similarity index 96% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_7/src/xqspipsu.c index 93fa53f..60eee53 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_7/src/xqspipsu.c
@@ -33,7 +33,7 @@ /** * * @file xqspipsu.c -* @addtogroup qspipsu_v1_0 +* @addtogroup qspipsu_v1_7 * @{ * * This file implements the functions required to use the QSPIPSU hardware to @@ -60,6 +60,10 @@ * 1.3 nsk 09/16/16 Update PollData and PollTimeout support for dual * parallel configurations, modified XQspiPsu_PollData() * and XQspiPsu_Create_PollConfigData() +* 1,5 nsk 08/14/17 Added CCI support +* 1.7 tjs 01/16/18 Removed the check for DMA MSB to be written. (CR#992560) +* 1.7 tjs 01/17/18 Added a support to toggle WP pin of the flash. +* 1.7 tjs 03/14/18 Added support in EL1 NS mode (CR#974882) * * </pre> * @@ -150,6 +154,7 @@ InstancePtr->StatusHandler = StubStatusHandler; InstancePtr->Config.BusWidth = ConfigPtr->BusWidth; InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz; + InstancePtr->Config.IsCacheCoherent = ConfigPtr->IsCacheCoherent; /* Other instance variable initializations */ InstancePtr->SendBufferPtr = NULL; InstancePtr->RecvBufferPtr = NULL; @@ -928,7 +933,7 @@ static void StubStatusHandler(void *CallBackRef, u32 StatusEvent, u32 ByteCount) { - (void *) CallBackRef; + (void) CallBackRef; (void) StatusEvent; (void) ByteCount; @@ -1136,13 +1141,13 @@ XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET, (u32)AddrTemp); - AddrTemp = AddrTemp >> 32; - if ((AddrTemp & 0xFFFU) != FALSE) { - XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, - XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET, - (u32)AddrTemp & - XQSPIPSU_QSPIDMA_DST_ADDR_MSB_MASK); - } +#ifdef __aarch64__ + AddrTemp = (u64)((INTPTR)(Msg->RxBfrPtr) >> 32); + XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, + XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET, + (u32)AddrTemp & + XQSPIPSU_QSPIDMA_DST_ADDR_MSB_MASK); +#endif Remainder = InstancePtr->RxBytes % 4; DmaRxBytes = InstancePtr->RxBytes; @@ -1151,8 +1156,10 @@ DmaRxBytes = InstancePtr->RxBytes - Remainder; Msg->ByteCount = (u32)DmaRxBytes; } - - Xil_DCacheInvalidateRange((INTPTR)InstancePtr->RecvBufferPtr, Msg->ByteCount); + if (InstancePtr->Config.IsCacheCoherent == 0) { + Xil_DCacheInvalidateRange((INTPTR)InstancePtr->RecvBufferPtr, + Msg->ByteCount); + } /* Write no. of words to DMA DST SIZE */ XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, @@ -1511,4 +1518,37 @@ & XQSPIPSU_POLL_CFG_DATA_VALUE_MASK); return ConfigData; } + +/*****************************************************************************/ +/** +* @brief +* This API enables/ disables Write Protect pin on the flash parts. +* +* @param QspiPtr is a pointer to the QSPIPSU driver component to use. +* +* @return None +* +* @note By default WP pin as per the QSPI controller is driven High +* which means no write protection. Calling this function once +* will enable the protection. +* +******************************************************************************/ +void XQspiPsu_WriteProtectToggle(XQspiPsu *QspiPsuPtr, u32 Toggle) +{ + /* For Single and Stacked flash configuration with x1 or x2 mode*/ + if (QspiPsuPtr->Config.ConnectionMode == XQSPIPSU_CONNECTION_MODE_SINGLE) { + /* Enable */ + XQspiPsu_Enable(QspiPsuPtr); + + /* Select slave */ + XQspiPsu_GenFifoEntryCSAssert(QspiPsuPtr); + + XQspiPsu_WriteReg(QspiPsuPtr->Config.BaseAddress, XQSPIPSU_GPIO_OFFSET, + Toggle); + + } else if (QspiPsuPtr->Config.ConnectionMode == XQSPIPSU_CONNECTION_MODE_PARALLEL || + QspiPsuPtr->Config.ConnectionMode == XQSPIPSU_CONNECTION_MODE_STACKED) { + xil_printf("Dual Parallel/Stacked configuration is not supported by this API\r\n"); + } +} /** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_7/src/xqspipsu.h similarity index 85% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_7/src/xqspipsu.h index 9480194..b73b722 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_7/src/xqspipsu.h
@@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2018 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ /** * * @file xqspipsu.h -* @addtogroup qspipsu_v1_0 +* @addtogroup qspipsu_v1_7 * @{ * @details * @@ -112,7 +112,33 @@ * configuration. Updated XQspiPsu_PollData() and * XQspiPsu_Create_PollConfigData() functions in xqspipsu.c * and also modified the polldata example -* +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* ms 04/05/17 Modified Comment lines in functions of qspipsu +* examples to recognize it as documentation block +* and modified filename tag to include them in +* doxygen examples. +* 1.4 tjs 05/26/17 Added support for accessing upper DDR (0x800000000) +* while booting images from QSPI +* 1.5 tjs 08/08/17 Added index.html file for importing examples from system.mss +* 1.5 nsk 08/14/17 Added CCI support +* 1.5 tjs 09/14/17 Modified the checks for 4 byte addressing and commands. +* 1.6 tjs 10/16/17 Flow for accessing flash is made similar to u-boot and linux +* For CR-984966 +* 1.6 tjs 11/02/17 Resolved the compilation errors for ICCARM. CR-988625 +* 1.7 tjs 11/16/17 Removed the unsupported 4 Byte write and sector erase +* commands. +* 1.7 tjs 12/01/17 Added support for MT25QL02G Flash from Micron. CR-990642 +* 1.7 tjs 12/19/17 Added support for S25FL064L from Spansion. CR-990724 +* 1.7 tjs 01/11/18 Added support for MX66L1G45G flash from Macronix CR-992367 +* 1.7 tjs 01/16/18 Removed the check for DMA MSB to be written. (CR#992560) +* 1.7 tjs 01/17/18 Added support to toggle the WP pin of flash. (PR#2448) +* Added XQspiPsu_SetWP() in xqspipsu_options.c +* Added XQspiPsu_WriteProtectToggle() in xqspipsu.c and +* also added write protect example. +* 1.7 tjs 03/14/18 Added support in EL1 NS mode (CR#974882) +* 1.7 tjs 26/03/18 In dual parallel mode enable both CS when issuing Write +* enable command. CR-998478 * </pre> * ******************************************************************************/ @@ -175,6 +201,7 @@ u32 InputClockHz; /**< Input clock frequency */ u8 ConnectionMode; /**< Single, Stacked and Parallel mode */ u8 BusWidth; /**< Bus width available on board */ + u8 IsCacheCoherent; /**< Describes whether Cache Coherent or not */ } XQspiPsu_Config; /** @@ -259,6 +286,9 @@ #define XQSPIPSU_MSG_FLAG_TX 0x4U #define XQSPIPSU_MSG_FLAG_POLL 0x8U +/* GQSPI configuration to toggle WP of flash*/ +#define XQSPIPSU_SET_WP 1 + #define XQspiPsu_Select(InstancePtr, Mask) XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + XQSPIPSU_SEL_OFFSET, Mask) #define XQspiPsu_Enable(InstancePtr) XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + XQSPIPSU_EN_OFFSET, XQSPIPSU_EN_MASK) @@ -267,6 +297,7 @@ #define XQspiPsu_GetLqspiConfigReg(InstancePtr) XQspiPsu_In32((XQSPIPS_BASEADDR) + XQSPIPSU_LQSPI_CR_OFFSET) + /************************** Function Prototypes ******************************/ /* Initialization and reset */ @@ -292,6 +323,8 @@ s32 XQspiPsu_ClearOptions(XQspiPsu *InstancePtr, u32 Options); u32 XQspiPsu_GetOptions(XQspiPsu *InstancePtr); s32 XQspiPsu_SetReadMode(XQspiPsu *InstancePtr, u32 Mode); +void XQspiPsu_SetWP(XQspiPsu *InstancePtr, u8 Value); +void XQspiPsu_WriteProtectToggle(XQspiPsu *InstancePtr, u32 Toggle); #ifdef __cplusplus }
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_7/src/xqspipsu_g.c similarity index 90% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_g.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_7/src/xqspipsu_g.c index 969fa96..a6df4f5 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_g.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_7/src/xqspipsu_g.c
@@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,14 +44,15 @@ * The configuration table for devices */ -XQspiPsu_Config XQspiPsu_ConfigTable[] = +XQspiPsu_Config XQspiPsu_ConfigTable[XPAR_XQSPIPSU_NUM_INSTANCES] = { { XPAR_PSU_QSPI_0_DEVICE_ID, XPAR_PSU_QSPI_0_BASEADDR, XPAR_PSU_QSPI_0_QSPI_CLK_FREQ_HZ, XPAR_PSU_QSPI_0_QSPI_MODE, - XPAR_PSU_QSPI_0_QSPI_BUS_WIDTH + XPAR_PSU_QSPI_0_QSPI_BUS_WIDTH, + XPAR_PSU_QSPI_0_IS_CACHE_COHERENT } };
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_7/src/xqspipsu_hw.h similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_hw.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_7/src/xqspipsu_hw.h index 40314d6..a7e8563 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_hw.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_7/src/xqspipsu_hw.h
@@ -33,7 +33,7 @@ /** * * @file xqspipsu_hw.h -* @addtogroup qspipsu_v1_0 +* @addtogroup qspipsu_v1_7 * @{ * * This file contains low level access funcitons using the base address @@ -49,6 +49,7 @@ * sk 04/24/15 Modified the code according to MISRAC-2012. * 1.2 nsk 07/01/16 Added LQSPI supported Masks * rk 07/15/16 Added support for TapDelays at different frequencies. +* 1.7 tjs 03/14/18 Added support in EL1 NS mode. * * </pre> * @@ -147,6 +148,7 @@ or quad I/O */ #define XQSPIPS_LQSPI_CR_INST_MASK 0x000000FF /**< Read instr code */ #define XQSPIPS_LQSPI_CR_RST_STATE 0x80000003 /**< Default LQSPI CR value */ +#define XQSPIPS_LQSPI_CR_4_BYTE_STATE 0x88000013 /**< Default 4 Byte LQSPI CR value */ #define XQSPIPS_LQSPI_CFG_RST_STATE 0x800238C1 /**< Default LQSPI CFG value */ /** * Register: XQSPIPSU_ISR @@ -828,6 +830,7 @@ #define IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT 0X02 #define IOU_TAPDLY_BYPASS_LQSPI_RX_WIDTH 0X01 #define IOU_TAPDLY_BYPASS_LQSPI_RX_MASK 0x00000004 +#define IOU_TAPDLY_RESET_STATE 0x7 /***************** Macros (Inline Functions) Definitions *********************/
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_options.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_7/src/xqspipsu_options.c similarity index 92% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_options.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_7/src/xqspipsu_options.c index 2c77a08..e943e52 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_options.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_7/src/xqspipsu_options.c
@@ -33,7 +33,7 @@ /** * * @file xqspipsu_options.c -* @addtogroup qspipsu_v1_0 +* @addtogroup qspipsu_v1_7 * @{ * * This file implements funcitons to configure the QSPIPSU component, @@ -51,6 +51,8 @@ * 1.2 nsk 07/01/16 Modified XQspiPsu_SetOptions() to support * LQSPI options and updated OptionsTable * rk 07/15/16 Added support for TapDelays at different frequencies. +* 1.7 tjs 01/17/18 Added support to toggle the WP pin of flash. (PR#2448) +* 1.7 tjs 03/14/18 Added support in EL1 NS mode. (CR#974882) * * </pre> * @@ -59,6 +61,9 @@ /***************************** Include Files *********************************/ #include "xqspipsu.h" +#if defined (__aarch64__) +#include "xil_smc.h" +#endif /************************** Constant Definitions *****************************/ @@ -179,7 +184,7 @@ ConfigReg = XQspiPsu_ReadReg(XQSPIPS_BASEADDR,XQSPIPSU_LQSPI_CR_OFFSET); if (QspiPsuOptions & XQSPIPSU_LQSPI_MODE_OPTION) { - XQspiPsu_WriteReg(XQSPIPS_BASEADDR,XQSPIPSU_LQSPI_CR_OFFSET,XQSPIPS_LQSPI_CR_RST_STATE); + XQspiPsu_WriteReg(XQSPIPS_BASEADDR,XQSPIPSU_LQSPI_CR_OFFSET,XQSPIPS_LQSPI_CR_4_BYTE_STATE); XQspiPsu_WriteReg(XQSPIPS_BASEADDR,XQSPIPSU_CFG_OFFSET,XQSPIPS_LQSPI_CFG_RST_STATE); /* Enable the QSPI controller */ XQspiPsu_WriteReg(XQSPIPS_BASEADDR,XQSPIPSU_EN_OFFSET,XQSPIPSU_EN_MASK); @@ -344,8 +349,15 @@ if (InstancePtr->IsBusy == TRUE) { Status = XST_DEVICE_BUSY; } else { +#if EL1_NONSECURE && defined (__aarch64__) + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + IOU_TAPDLY_BYPASS_OFFSET) | + ((u64)(0x4) << 32), + (u64)TapdelayBypass, 0, 0, 0, 0, 0); +#else XQspiPsu_WriteReg(XPS_SYS_CTRL_BASEADDR,IOU_TAPDLY_BYPASS_OFFSET, TapdelayBypass); +#endif XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_LPBK_DLY_ADJ_OFFSET,LPBKDelay); XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, @@ -380,8 +392,12 @@ Divider = (1 << (Prescaler+1)); FreqDiv = (InstancePtr->Config.InputClockHz)/Divider; +#if EL1_NONSECURE && defined (__aarch64__) + Tapdelay = IOU_TAPDLY_RESET_STATE; +#else Tapdelay = XQspiPsu_ReadReg(XPS_SYS_CTRL_BASEADDR, - IOU_TAPDLY_BYPASS_OFFSET); + IOU_TAPDLY_BYPASS_OFFSET); +#endif Tapdelay = Tapdelay & (~IOU_TAPDLY_BYPASS_LQSPI_RX_MASK); @@ -618,4 +634,33 @@ #endif return Status; } + +/*****************************************************************************/ +/** +* +* This function sets the Write Protect and Hold options for the QSPIPSU device +* driver.The device must be idle rather than busy transferring data before +* setting Write Protect and Hold options. +* +* @param InstancePtr is a pointer to the XQspiPsu instance. +* @param Value of the WP_HOLD bit in configuration register +* +* @return None +* +* @note +* This function is not thread-safe. This function can only be used with single +* flash configuration and x1/x2 data mode. This function cannot be used with +* x4 data mode and dual parallel and stacked flash configuration. +* +******************************************************************************/ +void XQspiPsu_SetWP(XQspiPsu *InstancePtr, u8 Value) +{ + u32 ConfigReg; + + ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress, + XQSPIPSU_CFG_OFFSET); + ConfigReg |= Value << XQSPIPSU_CFG_WP_HOLD_SHIFT; + XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET, + ConfigReg); +} /** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_7/src/xqspipsu_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_sinit.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_7/src/xqspipsu_sinit.c index 63aaed0..3869167 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_sinit.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_7/src/xqspipsu_sinit.c
@@ -33,7 +33,7 @@ /** * * @file xqspipsu_sinit.c -* @addtogroup qspipsu_v1_0 +* @addtogroup qspipsu_v1_7 * @{ * * The implementation of the XQspiPsu component's static initialization
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/resetps_v1_0/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/resetps_v1_0/src/Makefile new file mode 100644 index 0000000..67ab3d8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/resetps_v1_0/src/Makefile
@@ -0,0 +1,40 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +CC_FLAGS = $(COMPILER_FLAGS) +ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +OUTS = *.o + +LIBSOURCES:=*.c +INCLUDEFILES:=*.h + +OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) + +libs: banner resetps_libs clean + +%.o: %.c + ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< + +banner: + echo "Compiling resetps" + +resetps_libs: ${OBJECTS} + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} + +.PHONY: include +include: resetps_includes + +resetps_includes: + ${CP} ${INCLUDEFILES} ${INCLUDEDIR} + +clean: + rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/resetps_v1_0/src/xresetps.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/resetps_v1_0/src/xresetps.c new file mode 100644 index 0000000..626ec54 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/resetps_v1_0/src/xresetps.c
@@ -0,0 +1,1030 @@ +/****************************************************************************** +* +* Copyright (C) 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xresetps.c +* @addtogroup xresetps_v1_0 +* @{ +* +* Contains the implementation of interface functions of the XResetPs driver. +* See xresetps.h for a description of the driver. +* +* <pre> +* MODIFICATION HISTORY: +* Ver Who Date Changes +* ----- ------ -------- --------------------------------------------- +* 1.00 cjp 09/05/17 First release +* </pre> +* +******************************************************************************/ + +/***************************** Include Files *********************************/ +#include "xresetps.h" +#include "xresetps_hw.h" +#include "xil_types.h" + +/************************** Constant Definitions *****************************/ +#define XRESETPS_RSTID_BASE (1000) +#define XRESETPS_REGADDR_INVALID (0xFFFFFFFFU) +#define XRESETPS_BM_INVALID (0xFFFFFFFFU) + +/**************************** Type Definitions *******************************/ +typedef struct { + const u32 SlcrregAddr; + const u32 SlcrregBitmask; + const u32 PwrStateBitmask; + const XResetPs_PulseTypes PulseType; + const u8 SupportedActions; +} XResetPs_Lookup; + +/************************** Variable Definitions *****************************/ +#if !EL1_NONSECURE +const static XResetPs_Lookup ResetMap[] = { + /* + * {Control Register, Control Bitmask, + * Power State Bitask, Pulse Type, + * Supported Actions}, + */ + {XRESETPS_CRF_APB_RST_FPD_TOP, PCIE_CFG_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, PCIE_BRIDGE_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, PCIE_CTRL_RESET_MASK, + PCIE_CTRL_PSCHK_MASK, XRESETPS_PT_DLY_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, DP_RESET_MASK, + DP_PSCHK_MASK, XRESETPS_PT_DLY_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, SWDT_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, AFI_FM5_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, AFI_FM4_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, AFI_FM3_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, AFI_FM2_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, AFI_FM1_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, AFI_FM0_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, GDMA_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, GPU_PP1_RESET_MASK, + GPU_PP1_PSCHK_MASK, XRESETPS_PT_DLY_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, GPU_PP0_RESET_MASK, + GPU_PP0_PSCHK_MASK, XRESETPS_PT_DLY_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, GPU_RESET_MASK, + GPU_PSCHK_MASK, XRESETPS_PT_DLY_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, GT_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, SATA_RESET_MASK, + SATA_PSCHK_MASK, XRESETPS_PT_DLY_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_APU, ACPU3_PWRON_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_APU, ACPU2_PWRON_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_APU, ACPU1_PWRON_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_APU, ACPU0_PWRON_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_APU, APU_L2_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_APU, ACPU3_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_APU, ACPU2_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_APU, ACPU1_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_APU, ACPU0_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_DDR_SS, DDR_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_DDR_SS, DDR_APM_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RESET_CTRL, SOFT_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU0, GEM0_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU0, GEM1_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU0, GEM2_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU0, GEM3_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, QSPI_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, UART0_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, UART1_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, SPI0_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, SPI1_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, SDIO0_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, SDIO1_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, CAN0_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, CAN1_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, I2C0_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, I2C1_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, TTC0_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, TTC1_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, TTC2_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, TTC3_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, SWDT_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, NAND_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, ADMA_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, GPIO_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, IOU_CC_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, TIMESTAMP_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, RPU_R50_RESET_MASK, + R50_PSCHK_MASK, XRESETPS_PT_DLY_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, RPU_R51_RESET_MASK, + R51_PSCHK_MASK, XRESETPS_PT_DLY_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, RPU_AMBA_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, OCM_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, RPU_PGE_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, USB0_CORERESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, USB1_CORERESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, USB0_HIBERRESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, USB1_HIBERRESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, USB0_APB_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, USB1_APB_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, IPI_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, APM_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, RTC_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, SYSMON_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, AFI_FM6_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, LPD_SWDT_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, FPD_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_DBG, RPU_DBG1_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_DBG, RPU_DBG0_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_DBG, DBG_LPD_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_DBG, DBG_FPD_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_APLL_CTRL, APLL_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_DPLL_CTRL, DPLL_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_VPLL_CTRL, VPLL_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_IOPLL_CTRL, IOPLL_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RPLL_CTRL, RPLL_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL0_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL1_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL2_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL3_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL4_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL5_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL6_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL7_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL8_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL9_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL10_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL11_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL12_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL13_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL14_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL15_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL16_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL17_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL18_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL19_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL20_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL21_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL22_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL23_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL24_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL25_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL26_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL27_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL28_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL29_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL30_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL31_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_GLB_RST_CTRL, RPU_LS_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_GLB_RST_CTRL, PS_ONLY_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_NOSUP)}, + /* All fields invalidated for PL since not supported */ + {XRESETPS_REGADDR_INVALID, XRESETPS_BM_INVALID, + XRESETPS_BM_INVALID, XRESETPS_PT_INVALID, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, +}; +#endif + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* Initialize a specific reset controller instance/driver. This function +* must be called before other functions of the driver are called. +* +* @param InstancePtr is a pointer to the XResetPs instance. +* @param ConfigPtr is the config structure. +* @param EffectiveAddress is the base address for the device. It could be +* a virtual address if address translation is supported in the +* system, otherwise it is the physical address. +* +* @return +* - XST_SUCCESS if initialization was successful. +* +* @note None. +* +******************************************************************************/ +XStatus XResetPs_CfgInitialize(XResetPs *InstancePtr, + XResetPs_Config *ConfigPtr, u32 EffectiveAddress) +{ + /* Arguments validation */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(ConfigPtr != NULL); + + /* Copying instance */ + InstancePtr->Config.DeviceId = ConfigPtr->DeviceId; + InstancePtr->Config.BaseAddress = EffectiveAddress; + + return XST_SUCCESS; +} + +#if !EL1_NONSECURE +/****************************************************************************/ +/** +* +* Pulse Reset RPU. +* +* @param None. +* +* @return +* - XST_SUCCESS if successful else error code. +* +* @note The pulse reset sequence is referred from ug1085(v1.3) +* chapter-38. Few changes to the sequence are adpoted from PMUFW. +* +******************************************************************************/ +static XStatus XResetPs_PulseResetRpuLs(void) +{ + u32 TimeOut; + u32 RegValue; + + /* Block Cortex-R5 master interface */ + RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL); + RegValue &= (~RPU_MASTER_ISO_MASK); + RegValue |= RPU_MASTER_ISO_MASK; + XResetPs_WriteReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL, RegValue); + + /* Wait for acknowledgment from AIB until timeout */ + TimeOut = XRESETPS_AIB_PSPL_DELAY; + RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_ACK_CTRL); + while ((TimeOut > 0U) && + ((RegValue & RPU_MASTER_ISO_MASK) != RPU_MASTER_ISO_MASK)) { + RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_ACK_CTRL); + TimeOut--; + } + + if (TimeOut == 0U) { + /* + * @NOTE: + * AIB ack Timed Out. + * As per ug1085(v1.3), nothing is to be done on timeout, hence + * continuing with reset sequence. + */ + } + + /* Block Cortex-R5 slave interface */ + RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL); + RegValue &= (~RPU_SLAVE_ISO_MASK); + RegValue |= RPU_SLAVE_ISO_MASK; + XResetPs_WriteReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL, RegValue); + + /* Wait for acknowledgment from AIB until timeout */ + TimeOut = XRESETPS_AIB_PSPL_DELAY; + RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_ACK_CTRL); + while ((TimeOut > 0U) && + ((RegValue & RPU_SLAVE_ISO_MASK) != RPU_SLAVE_ISO_MASK)) { + RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_ACK_CTRL); + TimeOut--; + } + + if (TimeOut == 0U) { + /* + * @NOTE: + * AIB ack Timed Out. + * As per ug1085(v1.3), nothing is to be done on timeout, hence + * continuing with reset sequence. + */ + } + + /* Unblock Cortex-R5 master interface */ + RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL); + RegValue &= (~RPU_MASTER_ISO_MASK); + XResetPs_WriteReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL, RegValue); + + /* Initiate Cortex-R5 LockStep reset */ + RegValue = XResetPs_ReadReg(XRESETPS_PMU_GLB_RST_CTRL); + RegValue |= RPU_LS_RESET_MASK; + XResetPs_WriteReg(XRESETPS_PMU_GLB_RST_CTRL, RegValue); + + /* Wait */ + TimeOut = XRESETPS_RST_PROP_DELAY; + while (TimeOut > 0U) { + TimeOut--; + } + + /* Release Cortex-R5 from Reset */ + RegValue = XResetPs_ReadReg(XRESETPS_PMU_GLB_RST_CTRL); + RegValue &= (~RPU_LS_RESET_MASK); + XResetPs_WriteReg(XRESETPS_PMU_GLB_RST_CTRL, RegValue); + + /* Wait */ + TimeOut = XRESETPS_RST_PROP_DELAY; + while (TimeOut > 0U) { + TimeOut--; + } + + /* Unblock Cortex-R5 slave interface */ + RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL); + RegValue &= (~RPU_SLAVE_ISO_MASK); + XResetPs_WriteReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL, RegValue); + + return XST_SUCCESS; +} + +/****************************************************************************/ +/** +* +* Pulse Reset PS only. +* +* @param None. +* +* @return +* - XST_SUCCESS if successful else error code. +* +* @note The pulse reset sequence is referred from ug1085(v1.3) +* chapter-38. Few changes to the sequence are adpoted from PMUFW. +* +******************************************************************************/ +static XStatus XResetPs_PulseResetPsOnly(void) +{ + + u32 RegValue; + u32 TimeOut; + u8 ReconfirmAckCnt; + + /* TODO: Set PMU Error to indicate to PL */ + + /* Block FPD to PL and LPD to PL interfaces with AIB (in PS) */ + XResetPs_WriteReg(XRESETPS_PMU_GLB_AIB_CTRL, AIB_ISO_CTRL_MASK); + + /* + * @NOTE: Updated referring PMUFW + * There is a possibility of glitch in AIB ack signal to PMU, hence ack + * needs reconfirmation. + */ + /* Wait for AIB ack or Timeout */ + ReconfirmAckCnt = XRESETPS_AIB_PSPL_RECONFIRM_CNT; + do { + TimeOut = XRESETPS_AIB_PSPL_DELAY; + RegValue = XResetPs_ReadReg(XRESETPS_PMU_GLB_AIB_STATUS); + while ((TimeOut > 0U) && + ((RegValue & AIB_ISO_STATUS_MASK) != AIB_ISO_STATUS_MASK)) { + RegValue = + XResetPs_ReadReg(XRESETPS_PMU_GLB_AIB_STATUS); + TimeOut--; + } + + if (TimeOut == 0U) { + /* + * @NOTE: + * AIB ack Timed Out. + * As per ug1085(v1.3), nothing is to be done on + * timeout, hence continuing with reset sequence. + */ + ReconfirmAckCnt = 0U; + } else { + ReconfirmAckCnt--; + } + } + while (ReconfirmAckCnt > 0U); + + /* + * @NOTE: Updated referring PMUFW. + * Check if we are running Silicon version 1.0. If so, + * bypass the RPLL before initiating the reset. This is + * due to a bug in 1.0 Silicon wherein the PS hangs on a + * reset if the RPLL is in use. + */ + RegValue = XResetPs_ReadReg(XRESETPS_CSU_VERSION_REG); + if (XRESETPS_PLATFORM_PS_VER1 == (RegValue & PS_VERSION_MASK)) { + RegValue = XResetPs_ReadReg(XRESETPS_CRL_APB_RPLL_CTRL); + RegValue |= RPLL_BYPASS_MASK; + XResetPs_WriteReg(XRESETPS_CRL_APB_RPLL_CTRL, RegValue); + } + + /* Block the propagation of the PROG signal to the PL */ + RegValue = XResetPs_ReadReg(XRESETPS_PMU_GLB_PS_CTRL); + RegValue &= (~PROG_ENABLE_MASK); + XResetPs_WriteReg(XRESETPS_PMU_GLB_PS_CTRL, RegValue); + + RegValue = XResetPs_ReadReg(XRESETPS_PMU_GLB_PS_CTRL); + RegValue |= PROG_GATE_MASK; + XResetPs_WriteReg(XRESETPS_PMU_GLB_PS_CTRL, RegValue); + + /* Initiate PS-only reset */ + RegValue = XResetPs_ReadReg(XRESETPS_PMU_GLB_RST_CTRL); + RegValue |= PS_ONLY_RESET_MASK; + XResetPs_WriteReg(XRESETPS_PMU_GLB_RST_CTRL, RegValue); + + return XST_SUCCESS; +} + +/****************************************************************************/ +/** +* +* Pulse Reset FPD. +* +* @param None. +* +* @return +* - XST_SUCCESS if successful else error code. +* +* @note The pulse reset sequence is referred from ug1085(v1.3) +* chapter-38. Few changes to the sequence are adpoted from PMUFW. +* +******************************************************************************/ +static XStatus XResetPs_PulseResetFpd(void) +{ + u32 TimeOut; + u32 RegValue; + + /* Enable FPD to LPD isolations */ + RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL); + RegValue &= (~FPD_TO_LPD_ISO_MASK); + RegValue |= FPD_TO_LPD_ISO_MASK; + XResetPs_WriteReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL, RegValue); + + RegValue = XResetPs_ReadReg(XRESETPS_LPD_SLCR_APBISO_REQ_CTRL); + RegValue |= GPU_ISO_MASK; + XResetPs_WriteReg(XRESETPS_LPD_SLCR_APBISO_REQ_CTRL, RegValue); + + /* Enable LPD to FPD isolations */ + RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL); + RegValue &= (~LPD_TO_FPD_ISO_MASK); + RegValue |= LPD_TO_FPD_ISO_MASK; + XResetPs_WriteReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL, RegValue); + + /* + * Here we need to check for AIB ack, since nothing is done incase + * ack is not received, we are just waiting for specified timeout + * and continuing + */ + TimeOut = XRESETPS_AIB_ISO_DELAY; + while (TimeOut > 0U) { + TimeOut--; + } + + /* Initiate FPD reset */ + RegValue = XResetPs_ReadReg(XRESETPS_PMU_GLB_RST_CTRL); + RegValue |= FPD_APU_RESET_MASK; + XResetPs_WriteReg(XRESETPS_PMU_GLB_RST_CTRL, RegValue); + + /* Wait till reset propagates */ + TimeOut = XRESETPS_RST_PROP_DELAY; + while (TimeOut > 0U) { + TimeOut--; + } + + /* Disable FPD to LPD isolations */ + RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL); + RegValue &= (~FPD_TO_LPD_ISO_MASK); + XResetPs_WriteReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL, RegValue); + + RegValue = XResetPs_ReadReg(XRESETPS_LPD_SLCR_APBISO_REQ_CTRL); + RegValue &= (~GPU_ISO_MASK); + XResetPs_WriteReg(XRESETPS_LPD_SLCR_APBISO_REQ_CTRL, RegValue); + + /* Release from Reset and wait till it propagates */ + RegValue = XResetPs_ReadReg(XRESETPS_PMU_GLB_RST_CTRL); + RegValue &= (~FPD_APU_RESET_MASK); + XResetPs_WriteReg(XRESETPS_PMU_GLB_RST_CTRL, RegValue); + + /* Wait till reset propagates */ + TimeOut = XRESETPS_RST_PROP_DELAY; + while (TimeOut > 0U) { + TimeOut--; + } + + /* Disable LPD to FPD isolations */ + RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL); + RegValue &= (~LPD_TO_FPD_ISO_MASK); + XResetPs_WriteReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL, RegValue); + + return XST_SUCCESS; +} +#endif + +/****************************************************************************/ +/** +* +* Assert reset for specific peripheral based on reset ID. +* +* @param InstancePtr is a pointer to the XResetPs instance. +* @param ResetID is the ID of the peripheral. +* +* @return +* - XST_SUCCESS if reset assertion was successful. +* - Error Code otherwise. +* +* @note None. +* +******************************************************************************/ +XStatus XResetPs_ResetAssert(XResetPs *InstancePtr, + const XResetPs_RstId ResetID) +{ + /* Arguments validation */ + Xil_AssertNonvoid(InstancePtr != NULL); + if ((ResetID > XRESETPS_RSTID_END) || + (ResetID < XRESETPS_RSTID_START)) { + return XST_INVALID_PARAM; + } + +#if EL1_NONSECURE + /* Assert reset via PMUFW */ + u64 SmcArgs; + XSmc_OutVar out; + + SmcArgs = (u64)XRESETPS_RSTACT_ASSERT << 32; + SmcArgs |= ((u64)(ResetID + XRESETPS_RSTID_BASE)); + + out = Xil_Smc(PM_ASSERT_SMC_FID, SmcArgs, 0, 0, 0, 0, 0, 0); + + return ((u32)out.Arg0); +#else + u32 RegAddr; + u32 RegBitmask; + u32 RegValue; + + /* Ignoring Nodes that doesnot support assert */ + if (!XRESETPS_CHK_ASSERT_SUPPORT(ResetMap[ResetID].SupportedActions)) { + return XST_NO_FEATURE; + } + + RegAddr = ResetMap[ResetID].SlcrregAddr; + RegBitmask = ResetMap[ResetID].SlcrregBitmask; + + /* Enable bit to assert reset */ + RegValue = XResetPs_ReadReg(RegAddr); + RegValue |= RegBitmask; + XResetPs_WriteReg(RegAddr, RegValue); + + return XST_SUCCESS; +#endif +} + +/****************************************************************************/ +/** +* +* Deassert reset for specific peripheral based on reset ID. +* +* @param InstancePtr is a pointer to the XResetPs instance. +* @param ResetID is the ID of the peripheral. +* +* @return +* - XST_SUCCESS if reset deassertion was successful. +* - Error Code otherwise. +* +* @note None. +* +******************************************************************************/ +XStatus XResetPs_ResetDeassert(XResetPs *InstancePtr, + const XResetPs_RstId ResetID) +{ + /* Arguments validation */ + Xil_AssertNonvoid(InstancePtr != NULL); + if ((ResetID > XRESETPS_RSTID_END) || + (ResetID < XRESETPS_RSTID_START)) { + return XST_INVALID_PARAM; + } + +#if EL1_NONSECURE + /* Deassert reset via PMUFW */ + u64 SmcArgs; + XSmc_OutVar out; + + SmcArgs = (u64)XRESETPS_RSTACT_RELEASE << 32; + SmcArgs |= ((u64)(ResetID + XRESETPS_RSTID_BASE)); + + out = Xil_Smc(PM_ASSERT_SMC_FID, SmcArgs, 0, 0, 0, 0, 0, 0); + + return ((u32)out.Arg0); +#else + u32 RegAddr; + u32 RegBitmask; + u32 RegValue; + + /* Ignoring Nodes that does not support deassert */ + if (!XRESETPS_CHK_ASSERT_SUPPORT(ResetMap[ResetID].SupportedActions)) { + return XST_NO_FEATURE; + } + + RegAddr = ResetMap[ResetID].SlcrregAddr; + RegBitmask = ResetMap[ResetID].SlcrregBitmask; + + /* Disable bit to deassert reset */ + RegValue = XResetPs_ReadReg(RegAddr); + RegValue &= (~RegBitmask); + XResetPs_WriteReg(RegAddr, RegValue); + + return XST_SUCCESS; +#endif +} + +/****************************************************************************/ +/** +* +* Pulse reset for specific peripheral based on reset ID. +* +* @param InstancePtr is a pointer to the XResetPs instance. +* @param ResetID is the ID of the peripheral. +* +* @return +* - XST_SUCCESS if pulse reset was successful. +* - Error Code otherwise. +* +* @note None. +* +******************************************************************************/ +XStatus XResetPs_ResetPulse(XResetPs *InstancePtr, const XResetPs_RstId ResetID) +{ + /* Arguments validation */ + Xil_AssertNonvoid(InstancePtr != NULL); + if ((ResetID > XRESETPS_RSTID_END) || + (ResetID < XRESETPS_RSTID_START)) { + return XST_INVALID_PARAM; + } + +#if EL1_NONSECURE + /* Pulse reset via PMUFW */ + u64 SmcArgs; + XSmc_OutVar out; + + SmcArgs = (u64)XRESETPS_RSTACT_PULSE << 32; + SmcArgs |= ((u64)(ResetID + XRESETPS_RSTID_BASE)); + + out = Xil_Smc(PM_ASSERT_SMC_FID, SmcArgs, 0, 0, 0, 0, 0, 0); + + return ((u32)out.Arg0); +#else + u32 RegAddr; + u32 RegBitmask; + u32 RegValue; + u32 TimeOut; + + /* Ignoring Nodes that donot support pulse reset */ + if (!XRESETPS_CHK_PULSE_SUPPORT(ResetMap[ResetID].SupportedActions)) { + return XST_NO_FEATURE; + } + + /* Handling specific pulse resets */ + switch (ResetID) { + case XRESETPS_RSTID_FPD: + return XResetPs_PulseResetFpd(); + case XRESETPS_RSTID_RPU_LS: + return XResetPs_PulseResetRpuLs(); + case XRESETPS_RSTID_PS_ONLY: + return XResetPs_PulseResetPsOnly(); + default: + break; + } + + RegAddr = ResetMap[ResetID].SlcrregAddr; + RegBitmask = ResetMap[ResetID].SlcrregBitmask; + + /* Power state mask validation */ + if ((ResetMap[ResetID].PulseType == XRESETPS_PT_DLY_PSCHK) && + (ResetMap[ResetID].PwrStateBitmask != XRESETPS_BM_INVALID)) { + RegValue = XResetPs_ReadReg(XRESETPS_PMU_GLB_PWR_STATUS); + if (ResetMap[ResetID].PwrStateBitmask != + (RegValue && ResetMap[ResetID].PwrStateBitmask )) { + return XST_REGISTER_ERROR; + } + } + + /* Enable bit to assert reset */ + RegValue = XResetPs_ReadReg(RegAddr); + RegValue |= RegBitmask; + XResetPs_WriteReg(RegAddr, RegValue); + + /* Wait for assert propogation */ + if (ResetMap[ResetID].PulseType != XRESETPS_PT_NO_DLY_NO_PSCHK) { + TimeOut = XRESETPS_PULSE_PROP_DELAY; + while (TimeOut > 0U) { + TimeOut--; + } + } + + /* Disable bit to deassert reset */ + RegValue = XResetPs_ReadReg(RegAddr); + RegValue &= (~RegBitmask); + XResetPs_WriteReg(RegAddr, RegValue); + + /* Wait for release propogation */ + if (ResetMap[ResetID].PulseType != XRESETPS_PT_NO_DLY_NO_PSCHK) { + TimeOut = XRESETPS_PULSE_PROP_DELAY; + while (TimeOut > 0U) { + TimeOut--; + } + } + + return XST_SUCCESS; +#endif +} + +/****************************************************************************/ +/** +* +* Get reset status for specific peripheral based on reset ID. +* +* @param InstancePtr is a pointer to the XResetPs instance. +* @param ResetID is the ID of the peripheral. +* @param Status is the status of reset for ResetID. +* 1 if asserted and 0 if released +* +* @return +* - XST_SUCCESS if status fetched successful. +* - Error Code otherwise. +* +* @note None. +* +******************************************************************************/ +XStatus XResetPs_ResetStatus(XResetPs *InstancePtr, + const XResetPs_RstId ResetID, XResetPs_RstStatus *Status) +{ + /* Arguments validation */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(Status != NULL); + if ((ResetID > XRESETPS_RSTID_END) || + (ResetID < XRESETPS_RSTID_START)) { + return XST_INVALID_PARAM; + } + +#if EL1_NONSECURE + /* Get reset status via PMUFW */ + XSmc_OutVar out; + + out = Xil_Smc(PM_GETSTATUS_SMC_FID, + ((u64)(ResetID + XRESETPS_RSTID_BASE)), 0, 0, 0, 0, 0, 0); + *Status = ((u32)(out.Arg0 >> 32)); + + return ((u32)out.Arg0); +#else + u32 RegAddr; + u32 RegBitmask; + u32 RegValue; + + /* Ignoring Nodes that donot support reset status */ + if (!XRESETPS_CHK_STATUS_SUPPORT(ResetMap[ResetID].SupportedActions)) { + return XST_NO_FEATURE; + } + + /* + * @NOTE: + * This will always move to else part as GPO3 are ignored because + * XRESETPS_PMU_LCL_READ_CTRL is not accessible. + */ + /* GPO3PL have status address different from control address */ + if ((ResetID >= XRESETPS_RSTID_GPO3PL0) && + (ResetID <= XRESETPS_RSTID_GPO3PL31)) { + RegAddr = XRESETPS_PMU_LCL_READ_CTRL; + } else { + RegAddr = ResetMap[ResetID].SlcrregAddr; + } + + RegBitmask = ResetMap[ResetID].SlcrregBitmask; + + RegValue = XResetPs_ReadReg(RegAddr); + if ((RegValue & RegBitmask) == RegBitmask) { + *Status = XRESETPS_RESETASSERTED; + } else { + *Status = XRESETPS_RESETRELEASED; + } + + return XST_SUCCESS; +#endif +} + +/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/resetps_v1_0/src/xresetps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/resetps_v1_0/src/xresetps.h new file mode 100644 index 0000000..f6a632b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/resetps_v1_0/src/xresetps.h
@@ -0,0 +1,382 @@ +/****************************************************************************** +* +* Copyright (C) 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xresetps.h +* @addtogroup xresetps_v1_0 +* @{ +* @details +* +* The Xilinx Reset Controller driver supports the following features: +* - Assert reset for specific peripheral. +* - Deassert reset for specific peripheral. +* - Pulse reset for specific peripheral. +* - Get reset status for specific peripheral. +* +* This driver is intended to be RTOS and processor independent. It works with +* physical addresses only. Any needs for dynamic memory management, threads +* or thread mutual exclusion, virtual memory, or cache control must be +* satisfied by the layer above this driver. +* +* <pre> +* MODIFICATION HISTORY: +* Ver Who Date Changes +* ----- ------ -------- ----------------------------------------------- +* 1.00 cjp 09/05/17 First release +* </pre> +* +******************************************************************************/ +#ifndef XRESETPS_H /* prevent circular inclusions */ +#define XRESETPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" +#include "xresetps_hw.h" + +#if defined (__aarch64__) +#include "xil_smc.h" +#endif + +/************************** Constant Definitions *****************************/ +/* + * Constants for supported/Not supported reset actions + */ +#define XRESETPS_SUP 1 +#define XRESETPS_NOSUP 0 + +/**************************** Type Definitions *******************************/ +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddress; /**< Base address of the device */ +} XResetPs_Config; + +/** + * The XResetPs driver instance data. The user is required to allocate a + * variable of this type for every reset controller device in the system. + * A pointer to a variable of this type is then passed to the driver API + * functions. + */ +typedef struct { + XResetPs_Config Config; /**< Hardware Configuration */ +} XResetPs; + +/** + * This typedef defines type of pulse reset to be executed for peripherals. + * 3 type of pulse reset are possible: + * 1. Pulse with no delay and no power state validation + * 2. Pulse with delay but no power state validation + * 3. Pulse with delay and power state validation + */ +typedef enum { + XRESETPS_PT_NO_DLY_NO_PSCHK, /**< No delay, no power state check */ + XRESETPS_PT_DLY_NO_PSCHK, /**< Delay, no power state check */ + XRESETPS_PT_DLY_PSCHK, /**< Delay, power state check */ + XRESETPS_PT_INVALID, /**< Invalid pulse type */ +} XResetPs_PulseTypes; + +/** + * This typedef defines reset actions on the peripherals. + */ +typedef enum { + XRESETPS_RSTACT_RELEASE, + XRESETPS_RSTACT_ASSERT, + XRESETPS_RSTACT_PULSE, +} XresetPs_ResetAction; + +/** + * This typedef defines resetIDs of peripherals maps to PMUFW resetIDs. This + * resetIDs are not offseted by 1000 and are relative. + */ +typedef enum { + XRESETPS_RSTID_START, + XRESETPS_RSTID_PCIE_CFG = XRESETPS_RSTID_START, + XRESETPS_RSTID_PCIE_BRIDGE, + XRESETPS_RSTID_PCIE_CTRL, + XRESETPS_RSTID_DP, + XRESETPS_RSTID_SWDT_CRF, + XRESETPS_RSTID_AFI_FM5, + XRESETPS_RSTID_AFI_FM4, + XRESETPS_RSTID_AFI_FM3, + XRESETPS_RSTID_AFI_FM2, + XRESETPS_RSTID_AFI_FM1, + XRESETPS_RSTID_AFI_FM0, + XRESETPS_RSTID_GDMA, + XRESETPS_RSTID_GPU_PP1, + XRESETPS_RSTID_GPU_PP0, + XRESETPS_RSTID_GPU, + XRESETPS_RSTID_GT, + XRESETPS_RSTID_SATA, + XRESETPS_RSTID_ACPU3_PWRON, + XRESETPS_RSTID_ACPU2_PWRON, + XRESETPS_RSTID_ACPU1_PWRON, + XRESETPS_RSTID_ACPU0_PWRON, + XRESETPS_RSTID_APU_L2, + XRESETPS_RSTID_ACPU3, + XRESETPS_RSTID_ACPU2, + XRESETPS_RSTID_ACPU1, + XRESETPS_RSTID_ACPU0, + XRESETPS_RSTID_DDR, + XRESETPS_RSTID_APM_FPD, + XRESETPS_RSTID_SOFT, + XRESETPS_RSTID_GEM0, + XRESETPS_RSTID_GEM1, + XRESETPS_RSTID_GEM2, + XRESETPS_RSTID_GEM3, + XRESETPS_RSTID_QSPI, + XRESETPS_RSTID_UART0, + XRESETPS_RSTID_UART1, + XRESETPS_RSTID_SPI0, + XRESETPS_RSTID_SPI1, + XRESETPS_RSTID_SDIO0, + XRESETPS_RSTID_SDIO1, + XRESETPS_RSTID_CAN0, + XRESETPS_RSTID_CAN1, + XRESETPS_RSTID_I2C0, + XRESETPS_RSTID_I2C1, + XRESETPS_RSTID_TTC0, + XRESETPS_RSTID_TTC1, + XRESETPS_RSTID_TTC2, + XRESETPS_RSTID_TTC3, + XRESETPS_RSTID_SWDT_CRL, + XRESETPS_RSTID_NAND, + XRESETPS_RSTID_ADMA, + XRESETPS_RSTID_GPIO, + XRESETPS_RSTID_IOU_CC, + XRESETPS_RSTID_TIMESTAMP, + XRESETPS_RSTID_RPU_R50, + XRESETPS_RSTID_RPU_R51, + XRESETPS_RSTID_RPU_AMBA, + XRESETPS_RSTID_OCM, + XRESETPS_RSTID_RPU_PGE, + XRESETPS_RSTID_USB0_CORERESET, + XRESETPS_RSTID_USB1_CORERESET, + XRESETPS_RSTID_USB0_HIBERRESET, + XRESETPS_RSTID_USB1_HIBERRESET, + XRESETPS_RSTID_USB0_APB, + XRESETPS_RSTID_USB1_APB, + XRESETPS_RSTID_IPI, + XRESETPS_RSTID_APM_LPD, + XRESETPS_RSTID_RTC, + XRESETPS_RSTID_SYSMON, + XRESETPS_RSTID_AFI_FM6, + XRESETPS_RSTID_LPD_SWDT, + XRESETPS_RSTID_FPD, + XRESETPS_RSTID_RPU_DBG1, + XRESETPS_RSTID_RPU_DBG0, + XRESETPS_RSTID_DBG_LPD, + XRESETPS_RSTID_DBG_FPD, + XRESETPS_RSTID_APLL, + XRESETPS_RSTID_DPLL, + XRESETPS_RSTID_VPLL, + XRESETPS_RSTID_IOPLL, + XRESETPS_RSTID_RPLL, + XRESETPS_RSTID_GPO3PL0, + XRESETPS_RSTID_GPO3PL1, + XRESETPS_RSTID_GPO3PL2, + XRESETPS_RSTID_GPO3PL3, + XRESETPS_RSTID_GPO3PL4, + XRESETPS_RSTID_GPO3PL5, + XRESETPS_RSTID_GPO3PL6, + XRESETPS_RSTID_GPO3PL7, + XRESETPS_RSTID_GPO3PL8, + XRESETPS_RSTID_GPO3PL9, + XRESETPS_RSTID_GPO3PL10, + XRESETPS_RSTID_GPO3PL11, + XRESETPS_RSTID_GPO3PL12, + XRESETPS_RSTID_GPO3PL13, + XRESETPS_RSTID_GPO3PL14, + XRESETPS_RSTID_GPO3PL15, + XRESETPS_RSTID_GPO3PL16, + XRESETPS_RSTID_GPO3PL17, + XRESETPS_RSTID_GPO3PL18, + XRESETPS_RSTID_GPO3PL19, + XRESETPS_RSTID_GPO3PL20, + XRESETPS_RSTID_GPO3PL21, + XRESETPS_RSTID_GPO3PL22, + XRESETPS_RSTID_GPO3PL23, + XRESETPS_RSTID_GPO3PL24, + XRESETPS_RSTID_GPO3PL25, + XRESETPS_RSTID_GPO3PL26, + XRESETPS_RSTID_GPO3PL27, + XRESETPS_RSTID_GPO3PL28, + XRESETPS_RSTID_GPO3PL29, + XRESETPS_RSTID_GPO3PL30, + XRESETPS_RSTID_GPO3PL31, + XRESETPS_RSTID_RPU_LS, + XRESETPS_RSTID_PS_ONLY, + XRESETPS_RSTID_PL, + XRESETPS_RSTID_END = XRESETPS_RSTID_PL, +} XResetPs_RstId; + +/** + * This typedef defines possible values for reset status of peripherals. + */ +typedef enum { + XRESETPS_RESETRELEASED, + XRESETPS_RESETASSERTED +} XResetPs_RstStatus; + +/***************** Macros (Inline Functions) Definitions *********************/ +/****************************************************************************/ +/** +* +* Set supported reset action. +* +* @param StatusSupport indicates if reset status check is supported +* @param PulseSupport indicates if pulse reset action is supported +* @param AssertSupport indicates if reset assert/deassert is supported +* +* @return Supported reset actions +* +* @note Here bit fields are used decide supported actions as defined +* below: +* BIT 1 - Assert/Deassert +* BIT 2 - Pulse +* BIT 3 - Reset status +* Bit set indicates corresponding action is supported and +* vice versa. +******************************************************************************/ +#define XRESETPS_SUPPORTED_ACT(ResetSupport, PulseSupport, AssertSupport) \ + ((ResetSupport << 2) | (PulseSupport << 1) | AssertSupport) + +/****************************************************************************/ +/** +* +* Check if assert/dessert reset is supported. +* +* @param Actions is supported reset actions +* +* @return 1 - Supported +* 0 - Not Supported +* +* @note None. +* +******************************************************************************/ +#define XRESETPS_CHK_ASSERT_SUPPORT(Actions) ((Actions & 0x1)) + +/****************************************************************************/ +/** +* +* Check if pulse reset is supported. +* +* @param Actions is supported reset actions +* +* @return 1 - Supported +* 0 - Not Supported +* +* @note None. +* +******************************************************************************/ +#define XRESETPS_CHK_PULSE_SUPPORT(Actions) ((Actions & 0x2) >> 1) + +/****************************************************************************/ +/** +* +* Check if Status check is supported. +* +* @param Actions is supported reset actions +* +* @return 1 - Supported +* 0 - Not Supported +* +* @note None. +* +******************************************************************************/ +#define XRESETPS_CHK_STATUS_SUPPORT(Actions) ((Actions & 0x4) >> 2) + +/****************************************************************************/ +/** +* +* Read the given register. +* +* @param RegAddress is the address of the register to read +* +* @return The 32-bit value of the register +* +* @note None. +* +******************************************************************************/ +#define XResetPs_ReadReg(RegAddress) \ + Xil_In32((u32)RegAddress) + +/****************************************************************************/ +/** +* +* Write the given register. +* +* @param RegAddress is the address of the register to write +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note None. +* +******************************************************************************/ +#define XResetPs_WriteReg(RegAddress, Data) \ + Xil_Out32((u32)RegAddress, (u32)Data) + +/************************** Function Prototypes ******************************/ + +/* + * Lookup configuration in xresetps_sinit.c. + */ +XResetPs_Config *XResetPs_LookupConfig(u16 DeviceId); + +/* + * Interface functions in xresetps.c + */ +XStatus XResetPs_CfgInitialize(XResetPs *InstancePtr, + XResetPs_Config *ConfigPtr, u32 EffectiveAddress); +XStatus XResetPs_ResetAssert(XResetPs *InstancePtr, + const XResetPs_RstId ResetID); +XStatus XResetPs_ResetDeassert(XResetPs *InstancePtr, + const XResetPs_RstId ResetID); +XStatus XResetPs_ResetPulse(XResetPs *InstancePtr, + const XResetPs_RstId ResetID); +XStatus XResetPs_ResetStatus(XResetPs *InstancePtr, + const XResetPs_RstId ResetID, XResetPs_RstStatus *Status); + +#ifdef __cplusplus +} +#endif +#endif /* end of protection macro */ +/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/resetps_v1_0/src/xresetps_g.c similarity index 89% copy from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_g.c copy to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/resetps_v1_0/src/xresetps_g.c index 5913cd8..529215d 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_g.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/resetps_v1_0/src/xresetps_g.c
@@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -38,18 +38,16 @@ *******************************************************************/ #include "xparameters.h" -#include "xrtcpsu.h" +#include "xresetps.h" /* * The configuration table for devices */ -XRtcPsu_Config XRtcPsu_ConfigTable[] = +XResetPs_Config XResetPs_ConfigTable[XPAR_XRESETPS_NUM_INSTANCES] = { { - XPAR_PSU_RTC_DEVICE_ID, - XPAR_PSU_RTC_BASEADDR + XPAR_XRESETPS_DEVICE_ID, + XPAR_XRESETPS_BASEADDR, } }; - -
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/resetps_v1_0/src/xresetps_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/resetps_v1_0/src/xresetps_hw.h new file mode 100644 index 0000000..a97162d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/resetps_v1_0/src/xresetps_hw.h
@@ -0,0 +1,327 @@ +/****************************************************************************** +* +* Copyright (C) 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xresetps_hw.h +* @addtogroup xresetps_v1_0 +* @{ +* +* This file contains the hardware interface to the System Reset controller. +* +* <pre> +* MODIFICATION HISTORY: +* Ver Who Date Changes +* ----- ------ -------- --------------------------------------------- +* 1.00 cjp 09/05/17 First release +* </pre> +* +******************************************************************************/ +#ifndef XRESETPS_HW_H /* prevent circular inclusions */ +#define XRESETPS_HW_H /* by using protection macros */ + +/***************************** Include Files *********************************/ +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ +/* Register address defines */ +/* CRF_APB defines */ +#define XRESETPS_CRF_APB_BASE (0XFD1A0000U) +/* RST_FPD_TOP Address and mask definations */ +#define XRESETPS_CRF_APB_RST_FPD_TOP \ + ((XRESETPS_CRF_APB_BASE) + ((u32)0X00000100U)) +#define PCIE_CFG_RESET_MASK ((u32)0X00080000U) +#define PCIE_BRIDGE_RESET_MASK ((u32)0X00040000U) +#define PCIE_CTRL_RESET_MASK ((u32)0X00020000U) +#define DP_RESET_MASK ((u32)0X00010000U) +#define SWDT_RESET_MASK ((u32)0X00008000U) +#define AFI_FM5_RESET_MASK ((u32)0X00001000U) +#define AFI_FM4_RESET_MASK ((u32)0X00000800U) +#define AFI_FM3_RESET_MASK ((u32)0X00000400U) +#define AFI_FM2_RESET_MASK ((u32)0X00000200U) +#define AFI_FM1_RESET_MASK ((u32)0X00000100U) +#define AFI_FM0_RESET_MASK ((u32)0X00000080U) +#define GDMA_RESET_MASK ((u32)0X00000040U) +#define GPU_PP1_RESET_MASK ((u32)0X00000020U) +#define GPU_PP0_RESET_MASK ((u32)0X00000010U) +#define GPU_RESET_MASK ((u32)0X00000008U) +#define GT_RESET_MASK ((u32)0X00000004U) +#define SATA_RESET_MASK ((u32)0X00000002U) +/* RST_FPD_APU Address and mask definations */ +#define XRESETPS_CRF_APB_RST_FPD_APU \ + ((XRESETPS_CRF_APB_BASE) + ((u32)0X00000104U)) +#define ACPU3_PWRON_RESET_MASK ((u32)0X00002000U) +#define ACPU2_PWRON_RESET_MASK ((u32)0X00001000U) +#define ACPU1_PWRON_RESET_MASK ((u32)0X00000800U) +#define ACPU0_PWRON_RESET_MASK ((u32)0X00000400U) +#define APU_L2_RESET_MASK ((u32)0X00000100U) +#define ACPU3_RESET_MASK ((u32)0X00000008U) +#define ACPU2_RESET_MASK ((u32)0X00000004U) +#define ACPU1_RESET_MASK ((u32)0X00000002U) +#define ACPU0_RESET_MASK ((u32)0X00000001U) +/* RST_DDR_SS Address and mask definations */ +#define XRESETPS_CRF_APB_RST_DDR_SS \ + ((XRESETPS_CRF_APB_BASE) + ((u32)0X00000108U)) +#define DDR_RESET_MASK ((u32)0X00000008U) +#define DDR_APM_RESET_MASK ((u32)0X00000004U) +/* APLL_CTRL Address and mask definations */ +#define XRESETPS_CRF_APB_APLL_CTRL \ + ((XRESETPS_CRF_APB_BASE) + ((u32)0X00000020U)) +#define APLL_RESET_MASK ((u32)0X00000001U) +/* DPLL_CTRL Address and mask definations */ +#define XRESETPS_CRF_APB_DPLL_CTRL \ + ((XRESETPS_CRF_APB_BASE) + ((u32)0X0000002CU)) +#define DPLL_RESET_MASK ((u32)0X00000001U) +/* VPLL_CTRL Address and mask definations */ +#define XRESETPS_CRF_APB_VPLL_CTRL \ + ((XRESETPS_CRF_APB_BASE) + ((u32)0X00000038U)) +#define VPLL_RESET_MASK ((u32)0X00000001U) + +/* CRL_APB defines */ +#define XRESETPS_CRL_APB_BASE (0XFF5E0000U) +/* RESET_CTRL Address and mask definations */ +#define XRESETPS_CRL_APB_RESET_CTRL \ + ((XRESETPS_CRL_APB_BASE) + ((u32)0X00000218U)) +#define SOFT_RESET_MASK ((u32)0X00000010U) +/* RST_LPD_IOU0 Address and mask definations */ +#define XRESETPS_CRL_APB_RST_LPD_IOU0 \ + ((XRESETPS_CRL_APB_BASE) + ((u32)0X00000230U)) +#define GEM0_RESET_MASK ((u32)0X00000001U) +#define GEM1_RESET_MASK ((u32)0X00000002U) +#define GEM2_RESET_MASK ((u32)0X00000004U) +#define GEM3_RESET_MASK ((u32)0X00000008U) +/* RST_LPD_IOU2 Address and mask definations */ +#define XRESETPS_CRL_APB_RST_LPD_IOU2 \ + ((XRESETPS_CRL_APB_BASE) + ((u32)0X00000238U)) +#define QSPI_RESET_MASK ((u32)0X00000001U) +#define UART0_RESET_MASK ((u32)0X00000002U) +#define UART1_RESET_MASK ((u32)0X00000004U) +#define SPI0_RESET_MASK ((u32)0X00000008U) +#define SPI1_RESET_MASK ((u32)0X00000010U) +#define SDIO0_RESET_MASK ((u32)0X00000020U) +#define SDIO1_RESET_MASK ((u32)0X00000040U) +#define CAN0_RESET_MASK ((u32)0X00000080U) +#define CAN1_RESET_MASK ((u32)0X00000100U) +#define I2C0_RESET_MASK ((u32)0X00000200U) +#define I2C1_RESET_MASK ((u32)0X00000400U) +#define TTC0_RESET_MASK ((u32)0X00000800U) +#define TTC1_RESET_MASK ((u32)0X00001000U) +#define TTC2_RESET_MASK ((u32)0X00002000U) +#define TTC3_RESET_MASK ((u32)0X00004000U) +#define SWDT_RESET_MASK ((u32)0X00008000U) +#define NAND_RESET_MASK ((u32)0X00010000U) +#define ADMA_RESET_MASK ((u32)0X00020000U) +#define GPIO_RESET_MASK ((u32)0X00040000U) +#define IOU_CC_RESET_MASK ((u32)0X00080000U) +#define TIMESTAMP_RESET_MASK ((u32)0X00100000U) +/* RST_LPD_TOP Address and mask definations */ +#define XRESETPS_CRL_APB_RST_LPD_TOP \ + ((XRESETPS_CRL_APB_BASE) + ((u32)0X0000023CU)) +#define RPU_R50_RESET_MASK ((u32)0X00000001U) +#define RPU_R51_RESET_MASK ((u32)0X00000002U) +#define RPU_AMBA_RESET_MASK ((u32)0X00000004U) +#define OCM_RESET_MASK ((u32)0X00000008U) +#define RPU_PGE_RESET_MASK ((u32)0X00000010U) +#define USB0_CORERESET_MASK ((u32)0X00000040U) +#define USB1_CORERESET_MASK ((u32)0X00000080U) +#define USB0_HIBERRESET_MASK ((u32)0X00000100U) +#define USB1_HIBERRESET_MASK ((u32)0X00000200U) +#define USB0_APB_RESET_MASK ((u32)0X00000400U) +#define USB1_APB_RESET_MASK ((u32)0X00000800U) +#define IPI_RESET_MASK ((u32)0X00004000U) +#define APM_RESET_MASK ((u32)0X00008000U) +#define RTC_RESET_MASK ((u32)0X00010000U) +#define SYSMON_RESET_MASK ((u32)0X00020000U) +#define AFI_FM6_RESET_MASK ((u32)0X00080000U) +#define LPD_SWDT_RESET_MASK ((u32)0X00100000U) +#define FPD_RESET_MASK ((u32)0X00800000U) +/* RST_LPD_DBG Address and mask definations */ +#define XRESETPS_CRL_APB_RST_LPD_DBG \ + ((XRESETPS_CRL_APB_BASE) + ((u32)0X00000240U)) +#define RPU_DBG1_RESET_MASK ((u32)0X00000020U) +#define RPU_DBG0_RESET_MASK ((u32)0X00000010U) +#define DBG_LPD_RESET_MASK ((u32)0X00000002U) +#define DBG_FPD_RESET_MASK ((u32)0X00000001U) +/* IOPLL_CTRL Address and mask definations */ +#define XRESETPS_CRL_APB_IOPLL_CTRL \ + ((XRESETPS_CRL_APB_BASE) + ((u32)0X00000020U)) +#define IOPLL_RESET_MASK ((u32)0X00000001U) +/* RPLL_CTRL Address and mask definations */ +#define XRESETPS_CRL_APB_RPLL_CTRL \ + ((XRESETPS_CRL_APB_BASE) + ((u32)0X00000030U)) +#define RPLL_RESET_MASK ((u32)0X00000001U) +#define RPLL_BYPASS_MASK ((u32)0X00000008U) + +/* PMU_IOM defines */ +#define XRESETPS_PMU_IOM_BASE (0XFFD40000U) +/* PMU_IOM_GPO3 Address and mask definations */ +#define XRESETPS_PMU_IOM_GPO3_CTRL \ + ((XRESETPS_PMU_IOM_BASE) + ((u32)0X0000001CU)) +#define GPO3_PL0_RESET_MASK ((u32)0X00000001U) +#define GPO3_PL1_RESET_MASK ((u32)0X00000002U) +#define GPO3_PL2_RESET_MASK ((u32)0X00000004U) +#define GPO3_PL3_RESET_MASK ((u32)0X00000008U) +#define GPO3_PL4_RESET_MASK ((u32)0X00000010U) +#define GPO3_PL5_RESET_MASK ((u32)0X00000020U) +#define GPO3_PL6_RESET_MASK ((u32)0X00000040U) +#define GPO3_PL7_RESET_MASK ((u32)0X00000080U) +#define GPO3_PL8_RESET_MASK ((u32)0X00000100U) +#define GPO3_PL9_RESET_MASK ((u32)0X00000200U) +#define GPO3_PL10_RESET_MASK ((u32)0X00000400U) +#define GPO3_PL11_RESET_MASK ((u32)0X00000800U) +#define GPO3_PL12_RESET_MASK ((u32)0X00001000U) +#define GPO3_PL13_RESET_MASK ((u32)0X00002000U) +#define GPO3_PL14_RESET_MASK ((u32)0X00004000U) +#define GPO3_PL15_RESET_MASK ((u32)0X00008000U) +#define GPO3_PL16_RESET_MASK ((u32)0X00010000U) +#define GPO3_PL17_RESET_MASK ((u32)0X00020000U) +#define GPO3_PL18_RESET_MASK ((u32)0X00040000U) +#define GPO3_PL19_RESET_MASK ((u32)0X00080000U) +#define GPO3_PL20_RESET_MASK ((u32)0X00100000U) +#define GPO3_PL21_RESET_MASK ((u32)0X00200000U) +#define GPO3_PL22_RESET_MASK ((u32)0X00400000U) +#define GPO3_PL23_RESET_MASK ((u32)0X00800000U) +#define GPO3_PL24_RESET_MASK ((u32)0X01000000U) +#define GPO3_PL25_RESET_MASK ((u32)0X02000000U) +#define GPO3_PL26_RESET_MASK ((u32)0X04000000U) +#define GPO3_PL27_RESET_MASK ((u32)0X08000000U) +#define GPO3_PL28_RESET_MASK ((u32)0X10000000U) +#define GPO3_PL29_RESET_MASK ((u32)0X20000000U) +#define GPO3_PL30_RESET_MASK ((u32)0X40000000U) +#define GPO3_PL31_RESET_MASK ((u32)0X80000000U) + +/* PMU_LCL defines */ +#define XRESETPS_PMU_LCL_BASE (0XFFD60000U) +/* GPO Read control address */ +#define XRESETPS_PMU_LCL_READ_CTRL \ + ((XRESETPS_PMU_LCL_BASE) + ((u32)0X0000021CU)) + +/* PMU_GLB defines */ +#define XRESETPS_PMU_GLB_BASE (0XFFD80000U) +/* PMU_GLB_RST Address and mask definations */ +#define XRESETPS_PMU_GLB_RST_CTRL ((XRESETPS_PMU_GLB_BASE) + ((u32)0X00000608U)) +#define RPU_LS_RESET_MASK ((u32)0X00000100U) +#define FPD_APU_RESET_MASK ((u32)0X00000200U) +#define PS_ONLY_RESET_MASK ((u32)0X00000400U) +/* PMU_GLB_PS Address and mask definations */ +#define XRESETPS_PMU_GLB_PS_CTRL ((XRESETPS_PMU_GLB_BASE) + ((u32)0X00000004U)) +#define PROG_ENABLE_MASK ((u32)0X00000002U) +#define PROG_GATE_MASK ((u32)0X00000001U) +/* PMU_GLB_AIB Address and mask definations */ +#define XRESETPS_PMU_GLB_AIB_CTRL ((XRESETPS_PMU_GLB_BASE) + ((u32)0X00000600U)) +#define LPD_AFI_FM_ISO_MASK ((u32)0X00000001U) +#define LPD_AFI_FS_ISO_MASK ((u32)0X00000002U) +#define FPD_AFI_FM_ISO_MASK ((u32)0X00000004U) +#define FPD_AFI_FS_ISO_MASK ((u32)0X00000008U) +#define AIB_ISO_CTRL_MASK (LPD_AFI_FM_ISO_MASK | LPD_AFI_FS_ISO_MASK | \ + FPD_AFI_FM_ISO_MASK | FPD_AFI_FS_ISO_MASK) +/* PMU_GLB_AIB status Address and mask definations */ +#define XRESETPS_PMU_GLB_AIB_STATUS \ + ((XRESETPS_PMU_GLB_BASE) + ((u32)0X00000604U)) +#define AIB_ISO_STATUS_MASK (AIB_ISO_CTRL_MASK) +/* PMU_GLB_PWR status Address and mask definations */ +#define XRESETPS_PMU_GLB_PWR_STATUS \ + ((XRESETPS_PMU_GLB_BASE) + ((u32)0X00000100U)) +#define FPD_PSCHK_MASK ((u32)0x00400000U) +#define PCIE_CTRL_PSCHK_MASK (FPD_PSCHK_MASK) +#define DP_PSCHK_MASK (FPD_PSCHK_MASK) +#define SATA_PSCHK_MASK (FPD_PSCHK_MASK) +#define R50_PSCHK_MASK ((u32)0x00000400U) +#define R51_PSCHK_MASK ((u32)0x00000800U) +#define GPU_PP0_PSCHK_MASK (((u32)0x00000010U) | (FPD_PSCHK_MASK)) +#define GPU_PP1_PSCHK_MASK (((u32)0x00000020U) | (FPD_PSCHK_MASK)) +#define GPU_PSCHK_MASK ((GPU_PP0_PSCHK_MASK) | \ + (GPU_PP1_PSCHK_MASK) | (FPD_PSCHK_MASK)) + +/* LPD_SLCR defines */ +#define XRESETPS_LPD_SCR_BASE (0XFF410000U) +/* LPD_SCR_AXIISO_REQ and LPD_SCR_AXIISO_ACK Address and mask definations */ +#define XRESETPS_LPD_SCR_AXIISO_REQ_CTRL \ + ((XRESETPS_LPD_SCR_BASE) + ((u32)0X00003030U)) +#define XRESETPS_LPD_SCR_AXIISO_ACK_CTRL \ + ((XRESETPS_LPD_SCR_BASE) + ((u32)0X00003040U)) +#define RPU0_MASTER_ISO_MASK ((u32)0X00010000U) +#define RPU1_MASTER_ISO_MASK ((u32)0X00020000U) +#define RPU_MASTER_ISO_MASK (RPU0_MASTER_ISO_MASK | RPU1_MASTER_ISO_MASK) +#define RPU0_SLAVE_ISO_MASK ((u32)0X00040000U) +#define RPU1_SLAVE_ISO_MASK ((u32)0X00080000U) +#define RPU_SLAVE_ISO_MASK (RPU0_SLAVE_ISO_MASK | RPU1_SLAVE_ISO_MASK) +#define FPD_OCM_ISO_MASK ((u32)0X00000008U) +#define FPD_LPDIBS_ISO_MASK ((u32)0X00000004U) +#define AFIFS1_ISO_MASK ((u32)0X00000002U) +#define AFIFS0_ISO_MASK ((u32)0X00000001U) +#define FPD_TO_LPD_ISO_MASK (FPD_LPDIBS_ISO_MASK | FPD_OCM_ISO_MASK | \ + AFIFS0_ISO_MASK | AFIFS1_ISO_MASK) +#define LPD_DDR_ISO_MASK ((u32)0X08000000U) +#define FPD_MAIN_ISO_MASK ((u32)0X01000000U) +#define LPD_TO_FPD_ISO_MASK (LPD_DDR_ISO_MASK | FPD_MAIN_ISO_MASK) +/* LPD_SLCR_APBISO_REQ Address and mask definations */ +#define XRESETPS_LPD_SLCR_APBISO_REQ_CTRL \ + ((XRESETPS_LPD_SCR_BASE) + ((u32)0X00003048U)) +#define GPU_ISO_MASK ((u32)0X00000001U) + +/* CSU defines */ +#define XRESETPS_CSU_BASE (0xFFCA0000U) +#define XRESETPS_CSU_VERSION_REG ((XRESETPS_CSU_BASE) + ((u32)0x00000044U)) +#define XRESETPS_PLATFORM_PS_VER1 ((u32)0x00000000U) +#define PS_VERSION_MASK ((u32)0x0000000FU) + +/* Timeout delay defines */ +#define XRESETPS_RST_PROP_DELAY (0xFU) +#define XRESETPS_AIB_ISO_DELAY (0xFU) +#define XRESETPS_AIB_PSPL_DELAY (0xFU) +#define XRESETPS_PULSE_PROP_DELAY (0xFU) + +/* AIB ack reconfirmation count */ +#define XRESETPS_AIB_PSPL_RECONFIRM_CNT \ + (0x2U) + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + + +/************************** Variable Definitions *****************************/ + +#ifdef __cplusplus +} +#endif +#endif /* end of protection macro */ +/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/resetps_v1_0/src/xresetps_sinit.c similarity index 71% copy from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_sinit.c copy to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/resetps_v1_0/src/xresetps_sinit.c index 1bc5b3b..eebdc9d 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_sinit.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/resetps_v1_0/src/xresetps_sinit.c
@@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -32,66 +32,63 @@ /*****************************************************************************/ /** * -* @file xemacps_sinit.c -* @addtogroup emacps_v3_1 +* @file xresetps_sinit.c +* @addtogroup xresetps_v1_0 * @{ * -* This file contains lookup method by device ID when success, it returns -* pointer to config table to be used to initialize the device. +* This file contains method for static initialization (compile-time) of the +* driver. * * <pre> * MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ------------------------------------------------------- -* 1.00a wsy 01/10/10 New -* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. +* Ver Who Date Changes +* ----- ------ -------- ---------------------------------------------- +* 1.00 cjp 09/05/17 First release * </pre> * ******************************************************************************/ /***************************** Include Files *********************************/ -#include "xemacps.h" +#include "xresetps.h" #include "xparameters.h" /************************** Constant Definitions *****************************/ - /**************************** Type Definitions *******************************/ -/*************************** Variable Definitions *****************************/ -extern XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES]; /***************** Macros (Inline Functions) Definitions *********************/ +/*************************** Variable Definitions ****************************/ +extern XResetPs_Config XResetPs_ConfigTable[XPAR_XRESETPS_NUM_INSTANCES]; /************************** Function Prototypes ******************************/ /*****************************************************************************/ /** -* Lookup the device configuration based on the unique device ID. The table +* Lookup the device configuration based on the unique device ID. The table * contains the configuration info for each device in the system. * -* @param DeviceId is the unique device ID of the device being looked up. +* @param DeviceId is the unique device ID of the device being looked up. * -* @return -* A pointer to the configuration table entry corresponding to the given -* device ID, or NULL if no match is found. +* @return A pointer to the configuration table entry corresponding to the +* given device ID, or NULL if no match is found. +* +* @note None. * ******************************************************************************/ -XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId) +XResetPs_Config *XResetPs_LookupConfig(u16 DeviceId) { - XEmacPs_Config *CfgPtr = NULL; - u32 i; + XResetPs_Config *CfgPtr = NULL; + u32 Index; - for (i = 0U; i < (u32)XPAR_XEMACPS_NUM_INSTANCES; i++) { - if (XEmacPs_ConfigTable[i].DeviceId == DeviceId) { - CfgPtr = &XEmacPs_ConfigTable[i]; + for (Index = 0U; Index < (u32)XPAR_XRESETPS_NUM_INSTANCES; Index++) { + if (XResetPs_ConfigTable[Index].DeviceId == DeviceId) { + CfgPtr = &XResetPs_ConfigTable[Index]; break; } } - - return (XEmacPs_Config *)(CfgPtr); + return (XResetPs_Config *)CfgPtr; } /** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/Makefile rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/Makefile
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/xrtcpsu.c similarity index 96% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/xrtcpsu.c index c91f612..c09d1e7 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/xrtcpsu.c
@@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2015 - 2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -18,8 +18,8 @@ * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. @@ -33,7 +33,7 @@ /** * * @file xrtcpsu.c -* @addtogroup rtcpsu_v1_0 +* @addtogroup rtcpsu_v1_5 * @{ * * Functions in this file are the minimum required functions for the XRtcPsu @@ -53,6 +53,8 @@ * 1.2 02/15/16 Corrected Calibration mask and Fractional * mask in CalculateCalibration API. * 1.3 vak 04/25/16 Corrected the RTC read and write time logic(cr#948833). +* 1.5 ms 08/27/17 Fixed compilation warnings. +* ms 08/29/17 Updated code as per source code style. * </pre> * ******************************************************************************/ @@ -166,7 +168,7 @@ *****************************************************************************/ static void XRtcPsu_StubHandler(void *CallBackRef, u32 Event) { - (void *) CallBackRef; + (void) CallBackRef; (void) Event; /* Assert occurs always since this is a stub and should never be called */ Xil_AssertVoidAlways(); @@ -218,7 +220,9 @@ *****************************************************************************/ u32 XRtcPsu_GetCurrentTime(XRtcPsu *InstancePtr) { - u32 Status, IntMask, CurrTime; + u32 Status; + u32 IntMask; + u32 CurrTime; IntMask = XRtcPsu_ReadReg(InstancePtr->RtcConfig.BaseAddr + XRTC_INT_MSK_OFFSET); @@ -294,9 +298,9 @@ * format and saves it in the DT structure variable. It also reports the weekday. * * @param Seconds is the time value that has to be shown in DateTime -* format. +* format. * @param dt is the DateTime format variable that stores the translated -* time. +* time. * * @return None. * @@ -305,7 +309,10 @@ *****************************************************************************/ void XRtcPsu_SecToDateTime(u32 Seconds, XRtcPsu_DT *dt) { - u32 CurrentTime, TempDays, Leap, DaysPerMonth; + u32 CurrentTime; + u32 TempDays; + u32 DaysPerMonth; + u32 Leap = 0U; CurrentTime = Seconds; dt->Sec = CurrentTime % 60U; @@ -364,7 +371,8 @@ *****************************************************************************/ u32 XRtcPsu_DateTimeToSec(XRtcPsu_DT *dt) { - u32 i, Days; + u32 i; + u32 Days; u32 Seconds; Xil_AssertNonvoid(dt != NULL); @@ -414,8 +422,14 @@ void XRtcPsu_CalculateCalibration(XRtcPsu *InstancePtr,u32 TimeReal, u32 CrystalOscFreq) { - u32 ReadTime, SetTime; - u32 Cprev,Fprev,Cnew,Fnew,Xf,Calibration; + u32 ReadTime; + u32 SetTime; + u32 Cprev; + u32 Fprev; + u32 Cnew; + u32 Fnew; + u32 Calibration; + float Xf; Xil_AssertVoid(TimeReal != 0U); Xil_AssertVoid(CrystalOscFreq != 0U);
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/xrtcpsu.h similarity index 94% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/xrtcpsu.h index 164ddf6..8320470 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/xrtcpsu.h
@@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2015 - 2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -18,8 +18,8 @@ * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. @@ -32,7 +32,7 @@ /*****************************************************************************/ /** * @file xrtcpsu.h -* @addtogroup rtcpsu_v1_0 +* @addtogroup rtcpsu_v1_5 * @{ * @details * @@ -101,6 +101,14 @@ * 1.1 kvn 09/25/15 Modify control register to enable battery * switching when vcc_psaux is not available. * 1.3 vak 04/25/16 Corrected the RTC read and write time logic(cr#948833). +* 1.4 MNK 01/27/17 Corrected calibration and frequency macros based on +* rtc input oscillator frequency ( 32.768Khz). +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* ms 04/10/17 Modified filename tag in examples to include them in +* doxygen examples. +* 1.5 ms 08/27/17 Fixed compilation warnings in xrtcpsu.c file. +* ms 08/29/17 Updated the code as per source code style. * </pre> * ******************************************************************************/ @@ -203,8 +211,8 @@ /***************** Macros (Inline Functions) Definitions *********************/ -#define XRTC_CALIBRATION_VALUE 0x00198231U -#define XRTC_TYPICAL_OSC_FREQ 33330U +#define XRTC_CALIBRATION_VALUE 0x8000U +#define XRTC_TYPICAL_OSC_FREQ 32768U /****************************************************************************/ /**
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_g.c similarity index 93% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_g.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_g.c index 5913cd8..ef49025 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_g.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_g.c
@@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,7 +44,7 @@ * The configuration table for devices */ -XRtcPsu_Config XRtcPsu_ConfigTable[] = +XRtcPsu_Config XRtcPsu_ConfigTable[XPAR_XRTCPSU_NUM_INSTANCES] = { { XPAR_PSU_RTC_DEVICE_ID,
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_hw.h similarity index 98% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_hw.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_hw.h index 532ef7e..b535359 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_hw.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_hw.h
@@ -18,8 +18,8 @@ * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. @@ -33,7 +33,7 @@ /** * * @file xrtcpsu_hw.h -* @addtogroup rtcpsu_v1_0 +* @addtogroup rtcpsu_v1_5 * @{ * * This header file contains the identifiers and basic driver functions (or
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_intr.c similarity index 98% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_intr.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_intr.c index 89d3cd9..1f5f831 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_intr.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_intr.c
@@ -18,8 +18,8 @@ * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. @@ -33,7 +33,7 @@ /** * * @file xrtcpsu_intr.c -* @addtogroup rtcpsu_v1_0 +* @addtogroup rtcpsu_v1_5 * @{ * * This file contains functions related to RTC interrupt handling.
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_selftest.c similarity index 96% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_selftest.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_selftest.c index 67c562c..2678d81 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_selftest.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_selftest.c
@@ -18,8 +18,8 @@ * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. @@ -33,7 +33,7 @@ /** * * @file xrtcpsu_selftest.c -* @addtogroup rtcpsu_v1_0 +* @addtogroup rtcpsu_v1_5 * @{ * * This file contains the self-test functions for the XRtcPsu driver.
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_sinit.c similarity index 96% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_sinit.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_sinit.c index d3a8b7d..32ea4e5 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_sinit.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_sinit.c
@@ -18,8 +18,8 @@ * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. @@ -33,7 +33,7 @@ /** * * @file xrtcpsu_sinit.c -* @addtogroup rtcpsu_v1_0 +* @addtogroup rtcpsu_v1_5 * @{ * * This file contains the implementation of the XRtcPsu driver's static
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/Makefile rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/Makefile
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/xscugic.c similarity index 82% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/xscugic.c index bf7ac12..f6afc0e 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/xscugic.c
@@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ /** * * @file xscugic.c -* @addtogroup scugic_v3_1 +* @addtogroup scugic_v3_8 * @{ * * Contains required functions for the XScuGic driver for the Interrupt @@ -107,7 +107,17 @@ * and properly mask interrupt target processor value to modify * interrupt target processor register for a given interrupt ID * and cpu ID -* +* 3.6 pkp 20/01/17 Added new API XScuGic_Stop to Disable distributor and +* interrupts in case they are being used only by current cpu. +* It also removes current cpu from interrupt target registers +* for all interrupts. +* kvn 02/17/17 Add support for changing GIC CPU master at run time. +* kvn 02/28/17 Make the CpuId as static variable and Added new +* XScugiC_GetCpuId to access CpuId. +* 3.9 mus 02/21/18 Added new API's XScuGic_UnmapAllInterruptsFromCpu and +* XScuGic_InterruptUnmapFromCpu, These API's can be used +* by applications to unmap specific/all interrupts from +* target CPU. It fixes CR#992490. * * </pre> * @@ -127,6 +137,7 @@ /***************** Macros (Inline Functions) Definitions *********************/ /************************** Variable Definitions *****************************/ +static u32 CpuId = XPAR_CPU_ID; /**< CPU Core identifier */ /************************** Function Prototypes ******************************/ @@ -254,7 +265,7 @@ #endif RegValue = XScuGic_DistReadReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET); - if (!(RegValue & XSCUGIC_EN_INT_MASK)) { + if ((RegValue & XSCUGIC_EN_INT_MASK) == 0U) { Xil_AssertVoid(InstancePtr != NULL); DoDistributorInit(InstancePtr, CpuID); return; @@ -353,7 +364,7 @@ u32 EffectiveAddr) { u32 Int_Id; - u32 Cpu_Id = (u32)XPAR_CPU_ID + (u32)1; + u32 Cpu_Id = CpuId + (u32)1; (void) EffectiveAddr; Xil_AssertNonvoid(InstancePtr != NULL); @@ -392,7 +403,7 @@ InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = InstancePtr; } - + XScuGic_Stop(InstancePtr); DistributorInit(InstancePtr, Cpu_Id); CPUInitialize(InstancePtr); @@ -827,4 +838,183 @@ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), RegValue); } +/****************************************************************************/ +/** +* Unmaps specific SPI interrupt from the target CPU +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Cpu_Id is a CPU number from which the interrupt has to be +* unmapped +* @param Int_Id is the IRQ source number to modify +* +* @return None. +* +* @note None +* +*****************************************************************************/ +void XScuGic_InterruptUnmapFromCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id) +{ + u32 RegValue; + u8 BitPos; + + Xil_AssertVoid(InstancePtr != NULL); + + RegValue = XScuGic_DistReadReg(InstancePtr, + XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id)); + + /* + * Identify bit position corresponding to Int_Id and Cpu_Id, + * in interrupt target register and clear it + */ + BitPos = ((Int_Id % 4U) * 8U) + Cpu_Id; + RegValue &= (~ ( 1U << BitPos )); + XScuGic_DistWriteReg(InstancePtr, + XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), + RegValue); +} +/****************************************************************************/ +/** +* Unmaps all SPI interrupts from the target CPU +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Cpu_Id is a CPU number from which the interrupts has to be +* unmapped +* +* @return None. +* +* @note None +* +*****************************************************************************/ +void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Id) +{ + u32 Int_Id; + u32 Target_Cpu; + u32 LocalCpuID = (1U << Cpu_Id); + + Xil_AssertVoid(InstancePtr != NULL); + + LocalCpuID |= LocalCpuID << 8U; + LocalCpuID |= LocalCpuID << 16U; + + for (Int_Id = 32U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+4U) + { + + Target_Cpu = XScuGic_DistReadReg(InstancePtr, + XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id)); + /* Remove LocalCpuID from interrupt target register */ + Target_Cpu &= (~LocalCpuID); + XScuGic_DistWriteReg(InstancePtr, + XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), Target_Cpu); + + } +} +/****************************************************************************/ +/** +* It checks if the interrupt target register contains all interrupts to be +* targeted for current CPU. If they are programmed to be forwarded to current +* cpu, this API disable all interrupts and disable GIC distributor. +* This API also removes current CPU from interrupt target registers for all +* interrupt. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +* @return None. +* +* @note None +* +*****************************************************************************/ +void XScuGic_Stop(XScuGic *InstancePtr) +{ + u32 Int_Id; + u32 RegValue; + u32 Target_Cpu; + u32 DistDisable = 1; /* To track if distributor need to be disabled or not */ + u32 LocalCpuID = ((u32)0x1 << CpuId); + + Xil_AssertVoid(InstancePtr != NULL); + + /* If distributor is already disabled, no need to do anything */ + RegValue = XScuGic_DistReadReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET); + if ((RegValue & XSCUGIC_EN_INT_MASK) == 0U) { + return; + } + + LocalCpuID |= LocalCpuID << 8U; + LocalCpuID |= LocalCpuID << 16U; + + /* + * Check if the interrupt are targeted to current cpu only or not. + * Also remove current cpu from interrupt target register for all + * interrupts. + */ + for (Int_Id = 32U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+4U) { + + Target_Cpu = XScuGic_DistReadReg(InstancePtr, + XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id)); + if ((Target_Cpu != LocalCpuID) && (Target_Cpu!= 0)) { + /* + * If any other CPU is also programmed to target register, GIC + * distributor can not be disabled. + */ + DistDisable = 0; + } + + /* Remove current CPU from interrupt target register */ + Target_Cpu &= (~LocalCpuID); + XScuGic_DistWriteReg(InstancePtr, + XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), Target_Cpu); + + } + + /* + * If GIC distributor is safe to be disabled, disable all the interrupt + * and then disable distributor. + */ + if ( DistDisable == 1) { + for (Int_Id = 0U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+32U) { + /* + * Disable all the interrupts + */ + XScuGic_DistWriteReg(InstancePtr, + XSCUGIC_EN_DIS_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET, + Int_Id), + 0xFFFFFFFFU); + } + XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET, 0U); + } +} + +/****************************************************************************/ +/** +* This updates the CpuId global variable. +* +* @param CpuCoreId is the CPU core number. +* +* @return None. +* +* @note None +* +*****************************************************************************/ +void XScuGic_SetCpuID(u32 CpuCoreId) +{ + Xil_AssertVoid(CpuCoreId <= 1U); + + CpuId = CpuCoreId; +} + +/****************************************************************************/ +/** +* This function returns the CpuId variable. +* +* @param None. +* +* @return The CPU core number. +* +* @note None. +* +*****************************************************************************/ +u32 XScuGic_GetCpuID(void) +{ + return CpuId; +} /** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/xscugic.h similarity index 87% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/xscugic.h index 1f02a73..e22ee5b 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/xscugic.h
@@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ /** * * @file xscugic.h -* @addtogroup scugic_v3_1 +* @addtogroup scugic_v3_8 * @{ * @details * @@ -157,6 +157,28 @@ * the distributor is enabled or not and if not, it does the * standard Distributor initialization. * This fixes the CR#952962. +* 3.6 ms 01/23/17 Modified xil_printf statement in main function for all +* examples to ensure that "Successfully ran" and "Failed" +* strings are available in all examples. This is a fix +* for CR-965028. +* kvn 02/17/17 Add support for changing GIC CPU master at run time. +* kvn 02/28/17 Make the CpuId as static variable and Added new +* XScugiC_GetCpuId to access CpuId. +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* 3.7 ms 04/11/17 Modified tcl file to add suffix U for all macro +* definitions of scugic in xparameters.h +* 3.8 mus 07/05/17 Updated scugic.tcl to add support for intrrupts connected +* through util_reduced_vector IP(OR gate) +* mus 07/05/17 Updated xdefine_zynq_canonical_xpars proc to initialize +* the HandlerTable in XScuGic_ConfigTable to 0, it removes +* the compilation warning in xscugic_g.c. Fix for CR#978736. +* mus 07/25/17 Updated xdefine_gic_params proc to export correct canonical +* definitions for pl to ps interrupts.Fix for CR#980534 +* 3.9 mus 02/21/18 Added new API's XScuGic_UnmapAllInterruptsFromCpu and +* XScuGic_InterruptUnmapFromCpu, These API's can be used +* by applications to unmap specific/all interrupts from +* target CPU. * * </pre> * @@ -322,6 +344,11 @@ void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id, u8 Priority, u8 Trigger); void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id); +void XScuGic_InterruptUnmapFromCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id); +void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Id); +void XScuGic_Stop(XScuGic *InstancePtr); +void XScuGic_SetCpuID(u32 CpuCoreId); +u32 XScuGic_GetCpuID(void); /* * Initialization functions in xscugic_sinit.c */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/xscugic_g.c similarity index 89% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_g.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/xscugic_g.c index 4bb186e..8bb1755 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_g.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/xscugic_g.c
@@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,12 +44,13 @@ * The configuration table for devices */ -XScuGic_Config XScuGic_ConfigTable[] = +XScuGic_Config XScuGic_ConfigTable[XPAR_XSCUGIC_NUM_INSTANCES] = { { XPAR_PSU_RCPU_GIC_DEVICE_ID, XPAR_PSU_RCPU_GIC_BASEADDR, - XPAR_PSU_RCPU_GIC_DIST_BASEADDR + XPAR_PSU_RCPU_GIC_DIST_BASEADDR, + {{0}} /**< Initialize the HandlerTable to 0 */ } };
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_hw.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/xscugic_hw.c similarity index 87% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_hw.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/xscugic_hw.c index 6267797..6604e3a 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_hw.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/xscugic_hw.c
@@ -33,7 +33,7 @@ /** * * @file xscugic_hw.c -* @addtogroup scugic_v3_1 +* @addtogroup scugic_v3_8 * @{ * * This file contains low-level driver functions that can be used to access the @@ -62,6 +62,13 @@ * XScuGic_SetPriTrigTypeByDistAddr and * XScuGic_GetPriTrigTypeByDistAddr here from xscugic.c * 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. +* 3.6 kvn 02/17/17 Add support for changing GIC CPU master at run time. +* kvn 02/28/17 Make the CpuId as static variable and Added new +* XScugiC_GetCpuId to access CpuId. +* 3.9 mus 02/21/18 Added new API's XScuGic_InterruptUnmapFromCpuByDistAddr +* and XScuGic_UnmapAllInterruptsFromCpuByDistAddr, These +* API's can be used by applications to unmap specific/all +* interrupts from target CPU. It fixes CR#992490. * * </pre> * @@ -90,6 +97,7 @@ /************************** Variable Definitions *****************************/ extern XScuGic_Config XScuGic_ConfigTable[XPAR_XSCUGIC_NUM_INSTANCES]; +extern u32 CpuId; /*****************************************************************************/ /** @@ -274,7 +282,7 @@ s32 XScuGic_DeviceInitialize(u32 DeviceId) { XScuGic_Config *Config; - u32 Cpu_Id = (u32)XPAR_CPU_ID + (u32)1; + u32 Cpu_Id = XScuGic_GetCpuID() + (u32)1; Config = &XScuGic_ConfigTable[(u32 )DeviceId]; @@ -567,4 +575,75 @@ *Trigger = (u8)(RegValue & XSCUGIC_INT_CFG_MASK); } + +/****************************************************************************/ +/** +* Unmaps specific SPI interrupt from the target CPU +* +* @param DistBaseAddress is the device base address +* @param Cpu_Id is a CPU number from which the interrupt has to be +* unmapped +* @param Int_Id is the IRQ source number to modify +* +* @return None. +* +* @note None +* +*****************************************************************************/ +void XScuGic_InterruptUnmapFromCpuByDistAddr(u32 DistBaseAddress, + u8 Cpu_Id, u32 Int_Id) +{ + u32 RegValue; + u8 BitPos; + + Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS); + + RegValue = XScuGic_ReadReg(DistBaseAddress, + XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id)); + + /* + * Identify bit position corresponding to Int_Id and Cpu_Id, + * in interrupt target register and clear it + */ + BitPos = ((Int_Id % 4U) * 8U) + Cpu_Id; + RegValue &= (~ ( 1U << BitPos )); + XScuGic_WriteReg(DistBaseAddress, + XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), RegValue); +} + +/****************************************************************************/ +/** +* Unmaps all SPI interrupts from the target CPU +* +* @param DistBaseAddress is the device base address +* @param Cpu_Id is a CPU number from which the interrupts has to be +* unmapped +* +* @return None. +* +* @note None +* +*****************************************************************************/ +void XScuGic_UnmapAllInterruptsFromCpuByDistAddr(u32 DistBaseAddress, + u8 Cpu_Id) +{ + u32 Int_Id; + u32 Target_Cpu; + u32 LocalCpuID = (1U << Cpu_Id); + + LocalCpuID |= LocalCpuID << 8U; + LocalCpuID |= LocalCpuID << 16U; + + for (Int_Id = 32U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+4U) + { + + Target_Cpu = XScuGic_ReadReg(DistBaseAddress, + XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id)); + /* Remove LocalCpuID from interrupt target register */ + Target_Cpu &= (~LocalCpuID); + XScuGic_WriteReg(DistBaseAddress, + XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), Target_Cpu); + + } +} /** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/xscugic_hw.h similarity index 97% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_hw.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/xscugic_hw.h index 5eaa633..08e65f4 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_hw.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/xscugic_hw.h
@@ -33,7 +33,7 @@ /** * * @file xscugic_hw.h -* @addtogroup scugic_v3_1 +* @addtogroup scugic_v3_8 * @{ * * This header file contains identifiers and HW access functions (or @@ -72,6 +72,10 @@ * 3.0 kvn 02/13/14 Modified code for MISRA-C:2012 compliance. * 3.2 pkp 11/09/15 Corrected the interrupt processsor target mask value * for CPU interface 2 i.e. XSCUGIC_SPI_CPU2_MASK +* 3.9 mus 02/21/18 Added new API's XScuGic_InterruptUnmapFromCpuByDistAddr +* and XScuGic_UnmapAllInterruptsFromCpuByDistAddr, These +* API's can be used by applications to unmap specific/all +* interrupts from target CPU. It fixes CR#992490. * </pre> * ******************************************************************************/ @@ -633,6 +637,10 @@ u8 Priority, u8 Trigger); void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id, u8 *Priority, u8 *Trigger); +void XScuGic_InterruptUnmapFromCpuByDistAddr(u32 DistBaseAddress, + u8 Cpu_Id, u32 Int_Id); +void XScuGic_UnmapAllInterruptsFromCpuByDistAddr(u32 DistBaseAddress, + u8 Cpu_Id); /************************** Variable Definitions *****************************/ #ifdef __cplusplus }
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/xscugic_intr.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_intr.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/xscugic_intr.c index d05a51c..d82a60b 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_intr.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/xscugic_intr.c
@@ -33,7 +33,7 @@ /** * * @file xscugic_intr.c -* @addtogroup scugic_v3_1 +* @addtogroup scugic_v3_8 * @{ * * This file contains the interrupt processing for the driver for the Xilinx
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/xscugic_selftest.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_selftest.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/xscugic_selftest.c index 47620d6..7b1028f 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_selftest.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/xscugic_selftest.c
@@ -33,7 +33,7 @@ /** * * @file xscugic_selftest.c -* @addtogroup scugic_v3_1 +* @addtogroup scugic_v3_8 * @{ * * Contains diagnostic self-test functions for the XScuGic driver.
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/xscugic_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_sinit.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/xscugic_sinit.c index d30390a..842f318 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_sinit.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/xscugic_sinit.c
@@ -33,7 +33,7 @@ /** * * @file xscugic_sinit.c -* @addtogroup scugic_v3_1 +* @addtogroup scugic_v3_8 * @{ * * Contains static init functions for the XScuGic driver for the Interrupt
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_4/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/Makefile rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_4/src/Makefile
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_4/src/xsdps.c similarity index 81% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_4/src/xsdps.c index ac3f946..65f1b22 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_4/src/xsdps.c
@@ -33,7 +33,7 @@ /** * * @file xsdps.c -* @addtogroup sdps_v2_5 +* @addtogroup sdps_v3_4 * @{ * * Contains the interface functions of the XSdPs driver. @@ -74,6 +74,22 @@ * sk 10/13/16 Reduced the delay during power cycle to 1ms as per spec * sk 10/19/16 Used emmc_hwreset pin to reset eMMC. * sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled. +* 3.2 sk 11/30/16 Modified the voltage switching sequence as per spec. +* sk 02/01/17 Added HSD and DDR mode support for eMMC. +* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397 +* sk 03/20/17 Add support for EL1 non-secure mode. +* 3.3 mn 05/17/17 Add support for 64bit DMA addressing +* mn 07/17/17 Add support for running SD at 200MHz +* mn 07/26/17 Fixed compilation warnings +* mn 08/07/17 Modify driver to support 64-bit DMA in arm64 only +* mn 08/17/17 Added CCI support for A53 and disabled data cache +* operations when it is enabled. +* mn 08/22/17 Updated for Word Access System support +* mn 09/06/17 Resolved compilation errors with IAR toolchain +* mn 09/26/17 Added UHS_MODE_ENABLE macro to enable UHS mode +* 3.4 mn 10/17/17 Use different commands for single and multi block +* transfers +* mn 03/02/18 Move UHS macro check to SD card initialization routine * </pre> * ******************************************************************************/ @@ -90,21 +106,23 @@ #define XSDPS_CMD1_HIGH_VOL 0x00FF8000U #define XSDPS_CMD1_DUAL_VOL 0x00FF8010U #define HIGH_SPEED_SUPPORT 0x2U +#define UHS_SDR50_SUPPORT 0x4U #define WIDTH_4_BIT_SUPPORT 0x4U #define SD_CLK_25_MHZ 25000000U #define SD_CLK_19_MHZ 19000000U #define SD_CLK_26_MHZ 26000000U #define EXT_CSD_DEVICE_TYPE_BYTE 196U -#define EXT_CSD_SEC_COUNT 212U +#define EXT_CSD_SEC_COUNT_BYTE1 212U +#define EXT_CSD_SEC_COUNT_BYTE2 213U +#define EXT_CSD_SEC_COUNT_BYTE3 214U +#define EXT_CSD_SEC_COUNT_BYTE4 215U #define EXT_CSD_DEVICE_TYPE_HIGH_SPEED 0x2U #define EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED 0x4U #define EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED 0x8U #define EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 0x10U #define EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200 0x20U #define CSD_SPEC_VER_3 0x3U - -/* Note: Remove this once fixed */ -#define UHS_BROKEN +#define SCR_SPEC_VER_3 0x80U /**************************** Type Definitions *******************************/ @@ -116,10 +134,9 @@ void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff); extern s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode); static s32 XSdPs_IdentifyCard(XSdPs *InstancePtr); -#ifndef UHS_BROKEN static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr); -#endif +u16 TransferMode; /*****************************************************************************/ /** * @@ -172,6 +189,7 @@ InstancePtr->Config.BusWidth = ConfigPtr->BusWidth; InstancePtr->Config.BankNumber = ConfigPtr->BankNumber; InstancePtr->Config.HasEMIO = ConfigPtr->HasEMIO; + InstancePtr->Config.IsCacheCoherent = ConfigPtr->IsCacheCoherent; InstancePtr->SectorCount = 0; InstancePtr->Mode = XSDPS_DEFAULT_SPEED_MODE; InstancePtr->Config_TapDelay = NULL; @@ -250,10 +268,18 @@ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_POWER_CTRL_OFFSET, PowerLevel | XSDPS_PC_BUS_PWR_MASK); + +#ifdef __aarch64__ /* Enable ADMA2 in 64bit mode. */ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET, + XSDPS_HC_DMA_ADMA2_64_MASK); +#else + /* Enable ADMA2 in 32bit mode. */ + XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, + XSDPS_HOST_CTRL1_OFFSET, XSDPS_HC_DMA_ADMA2_32_MASK); +#endif /* Enable all interrupt status except card interrupt initially */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, @@ -274,10 +300,8 @@ * Transfer mode register - default value * DMA enabled, block count enabled, data direction card to host(read) */ - XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_XFER_MODE_OFFSET, - XSDPS_TM_DMA_EN_MASK | XSDPS_TM_BLK_CNT_EN_MASK | - XSDPS_TM_DAT_DIR_SEL_MASK); + TransferMode = XSDPS_TM_DMA_EN_MASK | XSDPS_TM_BLK_CNT_EN_MASK | + XSDPS_TM_DAT_DIR_SEL_MASK; /* Set block size to 512 by default */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, @@ -328,6 +352,10 @@ Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); +#ifndef UHS_MODE_ENABLE + InstancePtr->Config.BusWidth = XSDPS_WIDTH_4; +#endif + if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) || ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK) != XSDPS_CAPS_EMB_SLOT)) { @@ -395,9 +423,17 @@ goto RETURN_PATH; } - Arg = XSDPS_ACMD41_HCS | XSDPS_ACMD41_3V3 | (0x1FFU << 15U); - if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) { - Arg |= XSDPS_OCR_S18; + Arg = XSDPS_ACMD41_HCS | XSDPS_ACMD41_3V3 | (0x1FFU << 15U); + /* + * There is no support to switch to 1.8V and use UHS mode on + * 1.0 silicon + */ + if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) && +#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU) + (XGetPSVersion_Info() > XPS_VERSION_1) && +#endif + (InstancePtr->Config.BusWidth == XSDPS_WIDTH_8)) { + Arg |= XSDPS_OCR_S18; } /* 0x40300000 - Host High Capacity support & 3.3V window */ @@ -419,18 +455,14 @@ InstancePtr->HCS = 1U; } - /* There is no support to switch to 1.8V and use UHS mode on 1.0 silicon */ -#ifndef UHS_BROKEN - if ((RespOCR & XSDPS_OCR_S18) != 0U) { + if ((RespOCR & XSDPS_OCR_S18) != 0U) { InstancePtr->Switch1v8 = 1U; Status = XSdPs_Switch_Voltage(InstancePtr); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } - } -#endif /* CMD2 for Card ID */ Status = XSdPs_CmdTransfer(InstancePtr, CMD2, 0U, 0U); @@ -528,12 +560,13 @@ { #ifdef __ICCARM__ #pragma data_alignment = 32 -static u8 ExtCsd[512]; + static u8 ExtCsd[512]; + u8 SCR[8] = { 0U }; #pragma data_alignment = 4 #else -static u8 ExtCsd[512] __attribute__ ((aligned(32))); + static u8 ExtCsd[512] __attribute__ ((aligned(32))); + u8 SCR[8] __attribute__ ((aligned(32))) = { 0U }; #endif - u8 SCR[8] = { 0U }; u8 ReadBuff[64] = { 0U }; s32 Status; u32 Arg; @@ -641,9 +674,68 @@ goto RETURN_PATH; } -#if defined (ARMR5) || defined (__aarch64__) - if ((InstancePtr->Switch1v8 != 0U) && - (InstancePtr->BusWidth == XSDPS_4_BIT_WIDTH)) { + if (((SCR[2] & SCR_SPEC_VER_3) != 0U) && + (ReadBuff[13] >= UHS_SDR50_SUPPORT) && + (InstancePtr->Config.BusWidth == XSDPS_WIDTH_8) && +#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU) + (XGetPSVersion_Info() > XPS_VERSION_1) && +#endif + (InstancePtr->Switch1v8 == 0U)) { + u16 CtrlReg, ClockReg; + + /* Stop the clock */ + CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + CtrlReg &= ~(XSDPS_CC_SD_CLK_EN_MASK | XSDPS_CC_INT_CLK_EN_MASK); + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET, + CtrlReg); + + /* Enabling 1.8V in controller */ + CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_HOST_CTRL2_OFFSET); + CtrlReg |= XSDPS_HC2_1V8_EN_MASK; + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET, + CtrlReg); + + /* Wait minimum 5mSec */ + (void)usleep(5000U); + + /* Check for 1.8V signal enable bit is cleared by Host */ + CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_HOST_CTRL2_OFFSET); + if ((CtrlReg & XSDPS_HC2_1V8_EN_MASK) == 0U) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + /* Wait for internal clock to stabilize */ + ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET, + ClockReg | XSDPS_CC_INT_CLK_EN_MASK); + ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + while((ClockReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) { + ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + } + + /* Enable SD clock */ + ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET, + ClockReg | XSDPS_CC_SD_CLK_EN_MASK); + + /* Wait for 1mSec */ + (void)usleep(1000U); + + InstancePtr->Switch1v8 = 1U; + } + +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) + if (InstancePtr->Switch1v8 != 0U) { /* Identify the UHS mode supported by card */ XSdPs_Identify_UhsMode(InstancePtr, ReadBuff); @@ -663,9 +755,10 @@ */ if (SCR[0] != 0U) { /* Check for high speed support */ - if ((ReadBuff[13] & HIGH_SPEED_SUPPORT) != 0U) { + if (((ReadBuff[13] & HIGH_SPEED_SUPPORT) != 0U) && + (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) { InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE; -#if defined (ARMR5) || defined (__aarch64__) +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) InstancePtr->Config_TapDelay = XSdPs_hsd_sdr25_tapdelay; #endif Status = XSdPs_Change_BusSpeed(InstancePtr); @@ -675,7 +768,7 @@ } } } -#if defined (ARMR5) || defined (__aarch64__) +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) } #endif @@ -695,10 +788,14 @@ goto RETURN_PATH; } - InstancePtr->SectorCount = *(u32 *)&ExtCsd[EXT_CSD_SEC_COUNT]; + InstancePtr->SectorCount = ((u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE4]) << 24; + InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE3] << 16; + InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE2] << 8; + InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE1]; - if ((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] & - EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) { + if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] & + EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) && + (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) { InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE; Status = XSdPs_Change_BusSpeed(InstancePtr); if (Status != XST_SUCCESS) { @@ -732,15 +829,39 @@ goto RETURN_PATH; } - InstancePtr->SectorCount = *(u32 *)&ExtCsd[EXT_CSD_SEC_COUNT]; + InstancePtr->SectorCount = ((u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE4]) << 24; + InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE3] << 16; + InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE2] << 8; + InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE1]; - if ((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] & + /* Check for card supported speed */ + if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] & (EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 | - EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200)) != 0U) { + EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200)) != 0U) && + (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) { InstancePtr->Mode = XSDPS_HS200_MODE; -#if defined (ARMR5) || defined (__aarch64__) +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) InstancePtr->Config_TapDelay = XSdPs_sdr104_hs200_tapdelay; #endif + } else if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] & + (EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED | + EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED)) != 0U) && + (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) { + InstancePtr->Mode = XSDPS_DDR52_MODE; +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) + InstancePtr->Config_TapDelay = XSdPs_ddr50_tapdelay; +#endif + } else if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] & + EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) && + (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) { + InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE; +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) + InstancePtr->Config_TapDelay = XSdPs_hsd_sdr25_tapdelay; +#endif + } else + InstancePtr->Mode = XSDPS_DEFAULT_SPEED_MODE; + + if (InstancePtr->Mode != XSDPS_DEFAULT_SPEED_MODE) { Status = XSdPs_Change_BusSpeed(InstancePtr); if (Status != XST_SUCCESS) { Status = XST_FAILURE; @@ -753,9 +874,27 @@ goto RETURN_PATH; } - if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HS200) { - Status = XST_FAILURE; - goto RETURN_PATH; + if (InstancePtr->Mode == XSDPS_HS200_MODE) { + if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HS200) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } + + if ((InstancePtr->Mode == XSDPS_HIGH_SPEED_MODE) || + InstancePtr->Mode == XSDPS_DDR52_MODE) { + if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HIGH) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + if (InstancePtr->Mode == XSDPS_DDR52_MODE) { + Status = XSdPs_Change_BusWidth(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } } } @@ -769,11 +908,13 @@ } } } - - Status = XSdPs_SetBlkSize(InstancePtr, XSDPS_BLK_SIZE_512_MASK); - if (Status != XST_SUCCESS) { - Status = XST_FAILURE; - goto RETURN_PATH; + if ((InstancePtr->Mode != XSDPS_DDR52_MODE) || + (InstancePtr->CardType == XSDPS_CARD_SD)) { + Status = XSdPs_SetBlkSize(InstancePtr, XSDPS_BLK_SIZE_512_MASK); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } } RETURN_PATH: @@ -839,7 +980,6 @@ return Status; } -#ifndef UHS_BROKEN /*****************************************************************************/ /** * @@ -853,7 +993,7 @@ { s32 Status; u16 CtrlReg; - u32 ReadReg; + u32 ReadReg, ClockReg; /* Send switch voltage command */ Status = XSdPs_CmdTransfer(InstancePtr, CMD11, 0U, 0U); @@ -877,9 +1017,6 @@ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET, CtrlReg); - /* Wait minimum 5mSec */ - (void)usleep(5000U); - /* Enabling 1.8V in controller */ CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET); @@ -887,13 +1024,40 @@ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET, CtrlReg); - /* Start clock */ - Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_400_KHZ); - if (Status != XST_SUCCESS) { + /* Wait minimum 5mSec */ + (void)usleep(5000U); + + /* Check for 1.8V signal enable bit is cleared by Host */ + CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_HOST_CTRL2_OFFSET); + if ((CtrlReg & XSDPS_HC2_1V8_EN_MASK) == 0U) { Status = XST_FAILURE; goto RETURN_PATH; } + /* Wait for internal clock to stabilize */ + ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET, + ClockReg | XSDPS_CC_INT_CLK_EN_MASK); + ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + while((ClockReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) { + ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + } + + /* Enable SD clock */ + ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET, + ClockReg | XSDPS_CC_SD_CLK_EN_MASK); + + /* Wait for 1mSec */ + (void)usleep(1000U); + /* Wait for CMD and DATA line to go high */ ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_PRES_STATE_OFFSET); @@ -906,7 +1070,6 @@ RETURN_PATH: return Status; } -#endif /*****************************************************************************/ /** @@ -986,8 +1149,8 @@ } } - XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CMD_OFFSET, - (u16)CommandReg); + XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET, + (CommandReg << 16) | TransferMode); /* Polling for response for now */ do { @@ -1178,20 +1341,32 @@ } XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff); + if (InstancePtr->Config.IsCacheCoherent == 0) { + Xil_DCacheInvalidateRange((INTPTR)Buff, + BlkCnt * XSDPS_BLK_SIZE_512_MASK); + } - XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_XFER_MODE_OFFSET, - XSDPS_TM_AUTO_CMD12_EN_MASK | + if (BlkCnt == 1U) { + TransferMode = XSDPS_TM_BLK_CNT_EN_MASK | + XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK; + + /* Send single block read command */ + Status = XSdPs_CmdTransfer(InstancePtr, CMD17, Arg, BlkCnt); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } else { + TransferMode = XSDPS_TM_AUTO_CMD12_EN_MASK | XSDPS_TM_BLK_CNT_EN_MASK | XSDPS_TM_DAT_DIR_SEL_MASK | - XSDPS_TM_DMA_EN_MASK | XSDPS_TM_MUL_SIN_BLK_SEL_MASK); + XSDPS_TM_DMA_EN_MASK | XSDPS_TM_MUL_SIN_BLK_SEL_MASK; - Xil_DCacheInvalidateRange((INTPTR)Buff, BlkCnt * XSDPS_BLK_SIZE_512_MASK); - - /* Send block read command */ - Status = XSdPs_CmdTransfer(InstancePtr, CMD18, Arg, BlkCnt); - if (Status != XST_SUCCESS) { - Status = XST_FAILURE; - goto RETURN_PATH; + /* Send multiple blocks read command */ + Status = XSdPs_CmdTransfer(InstancePtr, CMD18, Arg, BlkCnt); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } } /* Check for transfer complete */ @@ -1269,19 +1444,31 @@ } XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff); - Xil_DCacheFlushRange((INTPTR)Buff, BlkCnt * XSDPS_BLK_SIZE_512_MASK); + if (InstancePtr->Config.IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)Buff, + BlkCnt * XSDPS_BLK_SIZE_512_MASK); + } - XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_XFER_MODE_OFFSET, - XSDPS_TM_AUTO_CMD12_EN_MASK | + if (BlkCnt == 1U) { + TransferMode = XSDPS_TM_BLK_CNT_EN_MASK | XSDPS_TM_DMA_EN_MASK; + + /* Send single block write command */ + Status = XSdPs_CmdTransfer(InstancePtr, CMD24, Arg, BlkCnt); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } else { + TransferMode = XSDPS_TM_AUTO_CMD12_EN_MASK | XSDPS_TM_BLK_CNT_EN_MASK | - XSDPS_TM_MUL_SIN_BLK_SEL_MASK | XSDPS_TM_DMA_EN_MASK); + XSDPS_TM_MUL_SIN_BLK_SEL_MASK | XSDPS_TM_DMA_EN_MASK; - /* Send block write command */ - Status = XSdPs_CmdTransfer(InstancePtr, CMD25, Arg, BlkCnt); - if (Status != XST_SUCCESS) { - Status = XST_FAILURE; - goto RETURN_PATH; + /* Send multiple blocks write command */ + Status = XSdPs_CmdTransfer(InstancePtr, CMD25, Arg, BlkCnt); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } } /* @@ -1383,8 +1570,13 @@ } for (DescNum = 0U; DescNum < (TotalDescLines-1); DescNum++) { +#ifdef __aarch64__ + InstancePtr->Adma2_DescrTbl[DescNum].Address = + (u64)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH)); +#else InstancePtr->Adma2_DescrTbl[DescNum].Address = (u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH)); +#endif InstancePtr->Adma2_DescrTbl[DescNum].Attribute = XSDPS_DESC_TRAN | XSDPS_DESC_VALID; /* This will write '0' to length field which indicates 65536 */ @@ -1392,8 +1584,13 @@ (u16)XSDPS_DESC_MAX_LENGTH; } +#ifdef __aarch64__ + InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Address = + (u64)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH)); +#else InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Address = (u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH)); +#endif InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Attribute = XSDPS_DESC_TRAN | XSDPS_DESC_END | XSDPS_DESC_VALID; @@ -1401,13 +1598,18 @@ InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Length = (u16)((BlkCnt*BlkSize) - (DescNum*XSDPS_DESC_MAX_LENGTH)); +#ifdef __aarch64__ + XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_EXT_OFFSET, + (u32)(((u64)&(InstancePtr->Adma2_DescrTbl[0]))>>32)); +#endif XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET, (u32)(UINTPTR)&(InstancePtr->Adma2_DescrTbl[0])); - Xil_DCacheFlushRange((INTPTR)&(InstancePtr->Adma2_DescrTbl[0]), + if (InstancePtr->Config.IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)&(InstancePtr->Adma2_DescrTbl[0]), sizeof(XSdPs_Adma2Descriptor) * 32U); - + } } /*****************************************************************************/
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_4/src/xsdps.h similarity index 90% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_4/src/xsdps.h index 46fe545..3f9ffd2 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_4/src/xsdps.h
@@ -33,7 +33,7 @@ /** * * @file xsdps.h -* @addtogroup sdps_v2_5 +* @addtogroup sdps_v3_4 * @{ * @details * @@ -139,6 +139,16 @@ * sk 10/19/16 Used emmc_hwreset pin to reset eMMC. * sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled. * sk 11/16/16 Issue DLL reset at 31 iteration to load new zero value. +* 3.2 sk 11/30/16 Modified the voltage switching sequence as per spec. +* sk 02/01/17 Added HSD and DDR mode support for eMMC. +* sk 02/01/17 Consider bus width parameter from design for switching +* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397 +* sk 03/20/17 Add support for EL1 non-secure mode. +* 3.3 mn 05/17/17 Add support for 64bit DMA addressing +* mn 08/07/17 Modify driver to support 64-bit DMA in arm64 only +* mn 08/17/17 Enabled CCI support for A53 by adding cache coherency +* information. +* mn 09/06/17 Resolved compilation errors with IAR toolchain * * </pre> * @@ -156,6 +166,7 @@ #include "xil_cache.h" #include "xstatus.h" #include "xsdps_hw.h" +#include "xplatform_info.h" #include <string.h> /************************** Constant Definitions *****************************/ @@ -179,14 +190,25 @@ u32 BusWidth; /**< Bus Width */ u32 BankNumber; /**< MIO Bank selection for SD */ u32 HasEMIO; /**< If SD is connected to EMIO */ + u8 IsCacheCoherent; /**< If SD is Cache Coherent or not */ } XSdPs_Config; /* ADMA2 descriptor table */ typedef struct { u16 Attribute; /**< Attributes of descriptor */ u16 Length; /**< Length of current dma transfer */ +#ifdef __aarch64__ + u64 Address; /**< Address of current dma transfer */ +#else u32 Address; /**< Address of current dma transfer */ +#endif +#ifdef __ICCARM__ +#pragma data_alignment = 32 } XSdPs_Adma2Descriptor; +#pragma data_alignment = 4 +#else +} __attribute__((__packed__))XSdPs_Adma2Descriptor; +#endif /** * The XSdPs driver instance data. The user is required to allocate a @@ -243,8 +265,9 @@ s32 XSdPs_CardInitialize(XSdPs *InstancePtr); s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff); s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg); -#if defined (ARMR5) || defined (__aarch64__) +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff); +void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType); void XSdPs_hsd_sdr25_tapdelay(u32 Bank, u32 DeviceId, u32 CardType); void XSdPs_sdr104_hs200_tapdelay(u32 Bank, u32 DeviceId, u32 CardType); #endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_4/src/xsdps_g.c similarity index 91% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps_g.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_4/src/xsdps_g.c index 72981b5..de9be71 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps_g.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_4/src/xsdps_g.c
@@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,7 +44,7 @@ * The configuration table for devices */ -XSdPs_Config XSdPs_ConfigTable[] = +XSdPs_Config XSdPs_ConfigTable[XPAR_XSDPS_NUM_INSTANCES] = { { XPAR_PSU_SD_1_DEVICE_ID, @@ -54,7 +54,8 @@ XPAR_PSU_SD_1_HAS_WP, XPAR_PSU_SD_1_BUS_WIDTH, XPAR_PSU_SD_1_MIO_BANK, - XPAR_PSU_SD_1_HAS_EMIO + XPAR_PSU_SD_1_HAS_EMIO, + XPAR_PSU_SD_1_IS_CACHE_COHERENT } };
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_4/src/xsdps_hw.h similarity index 95% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps_hw.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_4/src/xsdps_hw.h index 2c5d712..8d190ef 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps_hw.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_4/src/xsdps_hw.h
@@ -33,7 +33,7 @@ /** * * @file xsdps_hw.h -* @addtogroup sdps_v2_5 +* @addtogroup sdps_v3_4 * @{ * * This header file contains the identifiers and basic HW access driver @@ -56,6 +56,11 @@ * sk 07/16/16 Added Tap delays accordingly to different SD/eMMC * operating modes. * 3.1 sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled. +* 3.2 sk 03/20/17 Add support for EL1 non-secure mode. +* 3.3 mn 08/22/17 Updated for Word Access System support +* mn 09/06/17 Added support for ARMCC toolchain +* 3.4 mn 01/22/18 Separated out SDR104 and HS200 clock defines +* * </pre> * ******************************************************************************/ @@ -953,6 +958,7 @@ #define XSDPS_HIGH_SPEED_MODE 0x5U #define XSDPS_DEFAULT_SPEED_MODE 0x6U #define XSDPS_HS200_MODE 0x7U +#define XSDPS_DDR52_MODE 0x4U #define XSDPS_SWITCH_CMD_BLKCNT 1U #define XSDPS_SWITCH_CMD_BLKSIZE 64U #define XSDPS_SWITCH_CMD_HS_GET 0x00FFFFF0U @@ -993,7 +999,16 @@ #define XSDPS_SD_SDR50_MAX_CLK 100000000U #define XSDPS_SD_DDR50_MAX_CLK 50000000U #define XSDPS_SD_SDR104_MAX_CLK 208000000U +/* + * XSDPS_SD_INPUT_MAX_CLK is set to 175000000 in order to keep it smaller + * than the clock value coming from the core. This value is kept to safely + * switch to SDR104 mode if the SD card supports it. + */ +#define XSDPS_SD_INPUT_MAX_CLK 175000000U + #define XSDPS_MMC_HS200_MAX_CLK 200000000U +#define XSDPS_MMC_HSD_MAX_CLK 52000000U +#define XSDPS_MMC_DDR_MAX_CLK 52000000U #define XSDPS_CARD_STATE_IDLE 0U #define XSDPS_CARD_STATE_RDY 1U @@ -1010,7 +1025,15 @@ #define XSDPS_SLOT_REM 0U #define XSDPS_SLOT_EMB 1U -#if defined (ARMR5) || defined (__aarch64__) +#define XSDPS_WIDTH_8 8U +#define XSDPS_WIDTH_4 4U + + +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) +#define SD0_ITAPDLY_SEL_MASK 0x000000FFU +#define SD0_OTAPDLY_SEL_MASK 0x0000003FU +#define SD1_ITAPDLY_SEL_MASK 0x00FF0000U +#define SD1_OTAPDLY_SEL_MASK 0x003F0000U #define SD_DLL_CTRL 0x00000358U #define SD_ITAPDLY 0x00000314U #define SD_OTAPDLY 0x00000318U @@ -1151,8 +1174,18 @@ * u16 XSdPs_ReadReg(u32 BaseAddress. int RegOffset) * ******************************************************************************/ -#define XSdPs_ReadReg16(BaseAddress, RegOffset) \ - XSdPs_In16((BaseAddress) + (RegOffset)) +static INLINE u16 XSdPs_ReadReg16(u32 BaseAddress, u8 RegOffset) +{ +#if defined (__MICROBLAZE__) + u32 Reg; + BaseAddress += RegOffset & 0xFC; + Reg = XSdPs_In32(BaseAddress); + Reg >>= ((RegOffset & 0x3)*8); + return (u16)Reg; +#else + return XSdPs_In16((BaseAddress) + (RegOffset)); +#endif +} /***************************************************************************/ /** @@ -1170,8 +1203,20 @@ * u16 RegisterValue) * ******************************************************************************/ -#define XSdPs_WriteReg16(BaseAddress, RegOffset, RegisterValue) \ - XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue)) + +static INLINE void XSdPs_WriteReg16(u32 BaseAddress, u8 RegOffset, u16 RegisterValue) +{ +#if defined (__MICROBLAZE__) + u32 Reg; + BaseAddress += RegOffset & 0xFC; + Reg = XSdPs_In32(BaseAddress); + Reg &= ~(0xFFFF<<((RegOffset & 0x3)*8)); + Reg |= RegisterValue <<((RegOffset & 0x3)*8); + XSdPs_Out32(BaseAddress, Reg); +#else + XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue)); +#endif +} /****************************************************************************/ /** @@ -1187,9 +1232,18 @@ * u8 XSdPs_ReadReg(u32 BaseAddress. int RegOffset) * ******************************************************************************/ -#define XSdPs_ReadReg8(BaseAddress, RegOffset) \ - XSdPs_In8((BaseAddress) + (RegOffset)) - +static INLINE u8 XSdPs_ReadReg8(u32 BaseAddress, u8 RegOffset) +{ +#if defined (__MICROBLAZE__) + u32 Reg; + BaseAddress += RegOffset & 0xFC; + Reg = XSdPs_In32(BaseAddress); + Reg >>= ((RegOffset & 0x3)*8); + return (u8)Reg; +#else + return XSdPs_In8((BaseAddress) + (RegOffset)); +#endif +} /***************************************************************************/ /** * Write to a register. @@ -1206,9 +1260,19 @@ * u8 RegisterValue) * ******************************************************************************/ -#define XSdPs_WriteReg8(BaseAddress, RegOffset, RegisterValue) \ - XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue)) - +static INLINE void XSdPs_WriteReg8(u32 BaseAddress, u8 RegOffset, u8 RegisterValue) +{ +#if defined (__MICROBLAZE__) + u32 Reg; + BaseAddress += RegOffset & 0xFC; + Reg = XSdPs_In32(BaseAddress); + Reg &= ~(0xFF<<((RegOffset & 0x3)*8)); + Reg |= RegisterValue <<((RegOffset & 0x3)*8); + XSdPs_Out32(BaseAddress, Reg); +#else + XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue)); +#endif +} /***************************************************************************/ /** * Macro to get present status register
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps_options.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_4/src/xsdps_options.c similarity index 77% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps_options.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_4/src/xsdps_options.c index 7dbc772..bcd7c68 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps_options.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_4/src/xsdps_options.c
@@ -33,7 +33,7 @@ /** * * @file xsdps_options.c -* @addtogroup sdps_v2_5 +* @addtogroup sdps_v3_4 * @{ * * Contains API's for changing the various options in host and card. @@ -63,6 +63,18 @@ * 3.1 mi 09/07/16 Removed compilation warnings with extra compiler flags. * sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled. * sk 11/16/16 Issue DLL reset at 31 iteration to load new zero value. +* 3.2 sk 02/01/17 Added HSD and DDR mode support for eMMC. +* sk 02/01/17 Consider bus width parameter from design for switching +* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397 +* vns 03/13/17 Fixed MISRAC mandatory violation +* sk 03/20/17 Add support for EL1 non-secure mode. +* 3.3 mn 07/25/17 Removed SD0_OTAPDLYENA and SD1_OTAPDLYENA bits +* mn 08/07/17 Properly set OTAPDLY value by clearing previous bit +* settings +* mn 08/17/17 Added CCI support for A53 and disabled data cache +* operations when it is enabled. +* mn 08/22/17 Updated for Word Access System support +* 3.4 mn 01/22/18 Separated out SDR104 and HS200 clock defines * * </pre> * @@ -71,7 +83,9 @@ /***************************** Include Files *********************************/ #include "xsdps.h" #include "sleep.h" - +#if defined (__aarch64__) +#include "xil_smc.h" +#endif /************************** Constant Definitions *****************************/ #define UHS_SDR12_SUPPORT 0x1U #define UHS_SDR25_SUPPORT 0x2U @@ -86,14 +100,14 @@ s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt); void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff); static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr); -#if defined (ARMR5) || defined (__aarch64__) +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode); static void XSdPs_sdr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType); -static void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType); void XSdPs_SetTapDelay(XSdPs *InstancePtr); static void XSdPs_DllReset(XSdPs *InstancePtr); #endif +extern u16 TransferMode; /*****************************************************************************/ /** * Update Block size for read/write operations. @@ -193,11 +207,11 @@ XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, SCR); - XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_XFER_MODE_OFFSET, - XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK); + TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK; - Xil_DCacheInvalidateRange((INTPTR)SCR, 8); + if (InstancePtr->Config.IsCacheCoherent == 0) { + Xil_DCacheInvalidateRange((INTPTR)SCR, 8); + } Status = XSdPs_CmdTransfer(InstancePtr, ACMD51, 0U, BlkCnt); if (Status != XST_SUCCESS) { @@ -261,6 +275,16 @@ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + /* + * check for bus width for 3.0 controller and return if + * bus width is <4 + */ + if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) && + (InstancePtr->Config.BusWidth < XSDPS_WIDTH_4)) { + Status = XST_SUCCESS; + goto RETURN_PATH; + } + if (InstancePtr->CardType == XSDPS_CARD_SD) { Status = XSdPs_CmdTransfer(InstancePtr, CMD55, InstancePtr->RelCardAddr, @@ -282,7 +306,8 @@ } else { if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) - && (InstancePtr->CardType == XSDPS_CHIP_EMMC)) { + && (InstancePtr->CardType == XSDPS_CHIP_EMMC) && + (InstancePtr->Config.BusWidth == XSDPS_WIDTH_8)) { /* in case of eMMC data width 8-bit */ InstancePtr->BusWidth = XSDPS_8_BIT_WIDTH; } else { @@ -290,9 +315,15 @@ } if (InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) { - Arg = XSDPS_MMC_8_BIT_BUS_ARG; + if (InstancePtr->Mode == XSDPS_DDR52_MODE) + Arg = XSDPS_MMC_DDR_8_BIT_BUS_ARG; + else + Arg = XSDPS_MMC_8_BIT_BUS_ARG; } else { - Arg = XSDPS_MMC_4_BIT_BUS_ARG; + if (InstancePtr->Mode == XSDPS_DDR52_MODE) + Arg = XSDPS_MMC_DDR_4_BIT_BUS_ARG; + else + Arg = XSDPS_MMC_4_BIT_BUS_ARG; } Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U); @@ -336,6 +367,15 @@ XSDPS_HOST_CTRL1_OFFSET, (u8)StatusReg); + if (InstancePtr->Mode == XSDPS_DDR52_MODE) { + StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_HOST_CTRL2_OFFSET); + StatusReg &= (u16)(~XSDPS_HC2_UHS_MODE_MASK); + StatusReg |= InstancePtr->Mode; + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_HOST_CTRL2_OFFSET, StatusReg); + } + Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); @@ -387,13 +427,13 @@ XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff); - XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_XFER_MODE_OFFSET, - XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK); + TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK; Arg = XSDPS_SWITCH_CMD_HS_GET; - Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 64); + if (InstancePtr->Config.IsCacheCoherent == 0) { + Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 64); + } Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U); if (Status != XST_SUCCESS) { @@ -454,7 +494,7 @@ u32 Arg; u16 BlkCnt; u16 BlkSize; - u8 ReadBuff[64]; + u8 ReadBuff[64] = {0U}; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); @@ -469,11 +509,11 @@ XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff); - Xil_DCacheFlushRange((INTPTR)ReadBuff, 64); + if (InstancePtr->Config.IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)ReadBuff, 64); + } - XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_XFER_MODE_OFFSET, - XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK); + TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK; Arg = XSDPS_SWITCH_CMD_HS_SET; @@ -553,7 +593,16 @@ goto RETURN_PATH; } } else { - Arg = XSDPS_MMC_HS200_ARG; + if (InstancePtr->Mode == XSDPS_HS200_MODE) { + Arg = XSDPS_MMC_HS200_ARG; + InstancePtr->BusSpeed = XSDPS_MMC_HS200_MAX_CLK; + } else if (InstancePtr->Mode == XSDPS_DDR52_MODE) { + Arg = XSDPS_MMC_HIGH_SPEED_ARG; + InstancePtr->BusSpeed = XSDPS_MMC_DDR_MAX_CLK; + } else { + Arg = XSDPS_MMC_HIGH_SPEED_ARG; + InstancePtr->BusSpeed = XSDPS_MMC_HSD_MAX_CLK; + } Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U); if (Status != XST_SUCCESS) { @@ -585,18 +634,18 @@ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK); - /* Change the clock frequency to 200 MHz */ - InstancePtr->BusSpeed = XSDPS_MMC_HS200_MAX_CLK; - Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } - Status = XSdPs_Execute_Tuning(InstancePtr); - if (Status != XST_SUCCESS) { - Status = XST_FAILURE; - goto RETURN_PATH; + + if (InstancePtr->Mode == XSDPS_HS200_MODE) { + Status = XSdPs_Execute_Tuning(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } } } @@ -654,7 +703,7 @@ XSDPS_CLK_CTRL_OFFSET, ClockReg); if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) { -#if defined (ARMR5) || defined (__aarch64__) +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) if ((InstancePtr->Mode != XSDPS_DEFAULT_SPEED_MODE) && (InstancePtr->Mode != XSDPS_UHS_SPEED_MODE_SDR12)) /* Program the Tap delays */ @@ -823,12 +872,11 @@ XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff); - Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 512U); + if (InstancePtr->Config.IsCacheCoherent == 0) { + Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 512U); + } - XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_XFER_MODE_OFFSET, - XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK); - + TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK; /* Send SEND_EXT_CSD command */ Status = XSdPs_CmdTransfer(InstancePtr, CMD8, Arg, 1U); @@ -927,7 +975,7 @@ } -#if defined (ARMR5) || defined (__aarch64__) +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) /*****************************************************************************/ /** * @@ -950,7 +998,7 @@ Xil_AssertVoid(InstancePtr != NULL); if (((ReadBuff[13] & UHS_SDR104_SUPPORT) != 0U) && - (InstancePtr->Config.InputClockHz >= XSDPS_MMC_HS200_MAX_CLK)) { + (InstancePtr->Config.InputClockHz >= XSDPS_SD_INPUT_MAX_CLK)) { InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR104; InstancePtr->Config_TapDelay = XSdPs_sdr104_hs200_tapdelay; } @@ -997,7 +1045,7 @@ u32 Arg; u16 BlkCnt; u16 BlkSize; - u8 ReadBuff[64]; + u8 ReadBuff[64] = {0U}; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); @@ -1013,10 +1061,11 @@ XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff); - Xil_DCacheFlushRange((INTPTR)ReadBuff, 64); + if (InstancePtr->Config.IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)ReadBuff, 64); + } - XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET, - XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK); + TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK; switch (Mode) { case 0U: @@ -1125,8 +1174,7 @@ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET, BlkSize); - XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET, - XSDPS_TM_DAT_DIR_SEL_MASK); + TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK; CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET); @@ -1141,7 +1189,7 @@ /* Wait for ~60 clock cycles to reset the tap values */ (void)usleep(1U); -#if defined (ARMR5) || defined (__aarch64__) +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) /* Issue DLL Reset to load new SDHC tuned tap values */ XSdPs_DllReset(InstancePtr); #endif @@ -1165,7 +1213,7 @@ } if (TuningCount == 31) { -#if defined (ARMR5) || defined (__aarch64__) +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) /* Issue DLL Reset to load new SDHC tuned tap values */ XSdPs_DllReset(InstancePtr); #endif @@ -1181,7 +1229,7 @@ /* Wait for ~12 clock cycles to synchronize the new tap values */ (void)usleep(1U); -#if defined (ARMR5) || defined (__aarch64__) +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) /* Issue DLL Reset to load new SDHC tuned tap values */ XSdPs_DllReset(InstancePtr); #endif @@ -1192,7 +1240,7 @@ } -#if defined (ARMR5) || defined (__aarch64__) +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) /*****************************************************************************/ /** * @@ -1213,25 +1261,48 @@ #ifdef XPAR_PSU_SD_0_DEVICE_ID if (DeviceId == 0U) { +#if EL1_NONSECURE && defined (__aarch64__) + (void)TapDelay; + if (Bank == 2) + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32), + (u64)SD0_OTAPDLYSEL_HS200_B2, 0, 0, 0, 0, 0); + else + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32), + (u64)SD0_OTAPDLYSEL_HS200_B0, 0, 0, 0, 0, 0); +#else /* Program the OTAPDLY */ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY); - TapDelay |= SD0_OTAPDLYENA; - XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); + TapDelay &= ~SD0_OTAPDLY_SEL_MASK; if (Bank == 2) TapDelay |= SD0_OTAPDLYSEL_HS200_B2; else TapDelay |= SD0_OTAPDLYSEL_HS200_B0; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); +#endif } else { #endif + (void) DeviceId; +#if EL1_NONSECURE && defined (__aarch64__) + (void)TapDelay; + if (Bank == 2) + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32), + (u64)SD1_OTAPDLYSEL_HS200_B2, 0, 0, 0, 0, 0); + else + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32), + (u64)SD1_OTAPDLYSEL_HS200_B0, 0, 0, 0, 0, 0); +#else TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY); - TapDelay |= SD1_OTAPDLYENA; - XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); + TapDelay &= ~SD1_OTAPDLY_SEL_MASK; if (Bank == 2) TapDelay |= SD1_OTAPDLYSEL_HS200_B2; else TapDelay |= SD1_OTAPDLYSEL_HS200_B0; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); +#endif #ifdef XPAR_PSU_SD_0_DEVICE_ID } #endif @@ -1258,19 +1329,32 @@ #ifdef XPAR_PSU_SD_0_DEVICE_ID if (DeviceId == 0U) { +#if EL1_NONSECURE && defined (__aarch64__) + (void)TapDelay; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_OTAPDLY) | + ((u64)SD0_OTAPDLY_SEL_MASK << 32), (u64)SD0_OTAPDLYSEL_SD50, + 0, 0, 0, 0, 0); +#else /* Program the OTAPDLY */ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY); - TapDelay |= SD0_OTAPDLYENA; - XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); + TapDelay &= ~SD0_OTAPDLY_SEL_MASK; TapDelay |= SD0_OTAPDLYSEL_SD50; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); +#endif } else { #endif + (void) DeviceId; +#if EL1_NONSECURE && defined (__aarch64__) + (void)TapDelay; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_OTAPDLY) | + ((u64)SD1_OTAPDLY_SEL_MASK << 32), (u64)SD1_OTAPDLYSEL_SD50, + 0, 0, 0, 0, 0); +#else TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY); - TapDelay |= SD1_OTAPDLYENA; - XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); + TapDelay &= ~SD1_OTAPDLY_SEL_MASK; TapDelay |= SD1_OTAPDLYSEL_SD50; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); +#endif #ifdef XPAR_PSU_SD_0_DEVICE_ID } #endif @@ -1296,6 +1380,33 @@ #ifdef XPAR_PSU_SD_0_DEVICE_ID if (DeviceId == 0U) { +#if EL1_NONSECURE && defined (__aarch64__) + (void)TapDelay; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD0_ITAPCHGWIN << 32), (u64)SD0_ITAPCHGWIN, + 0, 0, 0, 0, 0); + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD0_ITAPDLYENA << 32), (u64)SD0_ITAPDLYENA, + 0, 0, 0, 0, 0); + if (CardType== XSDPS_CARD_SD) + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_ITAPDLY) | ((u64)SD0_ITAPDLY_SEL_MASK << 32), + (u64)SD0_ITAPDLYSEL_SD_DDR50, 0, 0, 0, 0, 0); + else + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_ITAPDLY) | ((u64)SD0_ITAPDLY_SEL_MASK << 32), + (u64)SD0_ITAPDLYSEL_EMMC_DDR50, 0, 0, 0, 0, 0); + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD0_ITAPCHGWIN << 32), (u64)0x0, 0, 0, 0, 0, 0); + if (CardType == XSDPS_CARD_SD) + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32), + (u64)SD0_OTAPDLYSEL_SD_DDR50, 0, 0, 0, 0, 0); + else + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32), + (u64)SD0_OTAPDLYSEL_EMMC_DDR50, 0, 0, 0, 0, 0); +#else TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY); TapDelay |= SD0_ITAPCHGWIN; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay); @@ -1311,15 +1422,44 @@ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay); /* Program the OTAPDLY */ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY); - TapDelay |= SD0_OTAPDLYENA; - XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); + TapDelay &= ~SD0_OTAPDLY_SEL_MASK; if (CardType == XSDPS_CARD_SD) TapDelay |= SD0_OTAPDLYSEL_SD_DDR50; else TapDelay |= SD0_OTAPDLYSEL_EMMC_DDR50; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); +#endif } else { #endif + (void) DeviceId; +#if EL1_NONSECURE && defined (__aarch64__) + (void)TapDelay; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD1_ITAPCHGWIN << 32), (u64)SD1_ITAPCHGWIN, + 0, 0, 0, 0, 0); + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD1_ITAPDLYENA << 32), (u64)SD1_ITAPDLYENA, + 0, 0, 0, 0, 0); + if (CardType== XSDPS_CARD_SD) + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_ITAPDLY) | ((u64)SD1_ITAPDLY_SEL_MASK << 32), + (u64)SD1_ITAPDLYSEL_SD_DDR50, 0, 0, 0, 0, 0); + else + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_ITAPDLY) | ((u64)SD1_ITAPDLY_SEL_MASK << 32), + (u64)SD1_ITAPDLYSEL_EMMC_DDR50, 0, 0, 0, 0, 0); + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_ITAPDLY) | ((u64)SD1_ITAPCHGWIN << 32), + (u64)0x0, 0, 0, 0, 0, 0); + if (CardType == XSDPS_CARD_SD) + Xil_Smc(MMIO_WRITE_SMC_FID,(u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32), + (u64)SD1_OTAPDLYSEL_SD_DDR50, 0, 0, 0, 0, 0); + else + Xil_Smc(MMIO_WRITE_SMC_FID,(u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32), + (u64)SD1_OTAPDLYSEL_EMMC_DDR50, 0, 0, 0, 0, 0); +#else TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY); TapDelay |= SD1_ITAPCHGWIN; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay); @@ -1335,13 +1475,13 @@ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay); /* Program the OTAPDLY */ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY); - TapDelay |= SD1_OTAPDLYENA; - XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); + TapDelay &= ~SD1_OTAPDLY_SEL_MASK; if (CardType == XSDPS_CARD_SD) TapDelay |= SD1_OTAPDLYSEL_SD_DDR50; else TapDelay |= SD1_OTAPDLYSEL_EMMC_DDR50; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); +#endif #ifdef XPAR_PSU_SD_0_DEVICE_ID } #endif @@ -1367,6 +1507,28 @@ #ifdef XPAR_PSU_SD_0_DEVICE_ID if (DeviceId == 0U) { +#if EL1_NONSECURE && defined (__aarch64__) + (void)TapDelay; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD0_ITAPCHGWIN << 32), (u64)SD0_ITAPCHGWIN, + 0, 0, 0, 0, 0); + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD0_ITAPDLYENA << 32), (u64)SD0_ITAPDLYENA, + 0, 0, 0, 0, 0); + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD0_ITAPDLY_SEL_MASK << 32), (u64)SD0_ITAPDLYSEL_HSD, + 0, 0, 0, 0, 0); + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD0_ITAPCHGWIN << 32), (u64)0x0, 0, 0, 0, 0, 0); + if (CardType == XSDPS_CARD_SD) + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32), + (u64)SD0_OTAPDLYSEL_SD_HSD, 0, 0, 0, 0, 0); + else + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32), + (u64)SD0_OTAPDLYSEL_EMMC_HSD, 0, 0, 0, 0, 0); +#else TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY); TapDelay |= SD0_ITAPCHGWIN; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay); @@ -1379,15 +1541,38 @@ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay); /* Program the OTAPDLY */ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY); - TapDelay |= SD0_OTAPDLYENA; - XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); + TapDelay &= ~SD0_OTAPDLY_SEL_MASK; if (CardType == XSDPS_CARD_SD) TapDelay |= SD0_OTAPDLYSEL_SD_HSD; else TapDelay |= SD0_OTAPDLYSEL_EMMC_HSD; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); +#endif } else { #endif + (void) DeviceId; +#if EL1_NONSECURE && defined (__aarch64__) + (void)TapDelay; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD1_ITAPCHGWIN << 32), (u64)SD1_ITAPCHGWIN, + 0, 0, 0, 0, 0); + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD1_ITAPDLYENA << 32), (u64)SD1_ITAPDLYENA, + 0, 0, 0, 0, 0); + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD1_ITAPDLY_SEL_MASK << 32), (u64)SD1_ITAPDLYSEL_HSD, + 0, 0, 0, 0, 0); + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD1_ITAPCHGWIN << 32), (u64)0x0, 0, 0, 0, 0, 0); + if (CardType == XSDPS_CARD_SD) + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32), + (u64)SD1_OTAPDLYSEL_SD_HSD, 0, 0, 0, 0, 0); + else + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32), + (u64)SD1_OTAPDLYSEL_EMMC_HSD, 0, 0, 0, 0, 0); +#else TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY); TapDelay |= SD1_ITAPCHGWIN; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay); @@ -1400,13 +1585,13 @@ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay); /* Program the OTAPDLY */ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY); - TapDelay |= SD1_OTAPDLYENA; - XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); + TapDelay &= ~SD1_OTAPDLY_SEL_MASK; if (CardType == XSDPS_CARD_SD) TapDelay |= SD1_OTAPDLYSEL_SD_HSD; else TapDelay |= SD1_OTAPDLYSEL_EMMC_HSD; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); +#endif #ifdef XPAR_PSU_SD_0_DEVICE_ID } #endif @@ -1434,20 +1619,48 @@ CardType = InstancePtr->CardType ; #ifdef XPAR_PSU_SD_0_DEVICE_ID if (DeviceId == 0U) { +#if EL1_NONSECURE && defined (__aarch64__) + (void)DllCtrl; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_DLL_CTRL) | ((u64)SD0_DLL_RST << 32), + (u64)SD0_DLL_RST, 0, 0, 0, 0, 0); +#else DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL); DllCtrl |= SD0_DLL_RST; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl); +#endif InstancePtr->Config_TapDelay(BankNum, DeviceId, CardType); +#if EL1_NONSECURE && defined (__aarch64__) + (void)DllCtrl; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_DLL_CTRL) | ((u64)SD0_DLL_RST << 32), + (u64)0x0, 0, 0, 0, 0, 0); +#else DllCtrl &= ~SD0_DLL_RST; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl); +#endif } else { #endif +#if EL1_NONSECURE && defined (__aarch64__) + (void)DllCtrl; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_DLL_CTRL) | ((u64)SD1_DLL_RST << 32), + (u64)SD1_DLL_RST, 0, 0, 0, 0, 0); +#else DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL); DllCtrl |= SD1_DLL_RST; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl); +#endif InstancePtr->Config_TapDelay(BankNum, DeviceId, CardType); +#if EL1_NONSECURE && defined (__aarch64__) + (void)DllCtrl; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_DLL_CTRL) | ((u64)SD1_DLL_RST << 32), + (u64)0x0, 0, 0, 0, 0, 0); +#else DllCtrl &= ~SD1_DLL_RST; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl); +#endif #ifdef XPAR_PSU_SD_0_DEVICE_ID } #endif @@ -1480,11 +1693,26 @@ /* Issue DLL Reset to load zero tap values */ DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL); if (InstancePtr->Config.DeviceId == 0U) { +#if EL1_NONSECURE && defined (__aarch64__) + (void)DllCtrl; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_DLL_CTRL) | ((u64)SD0_DLL_RST << 32), + (u64)SD0_DLL_RST, 0, 0, 0, 0, 0); +#else DllCtrl |= SD0_DLL_RST; + XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl); +#endif } else { +#if EL1_NONSECURE && defined (__aarch64__) + (void)DllCtrl; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_DLL_CTRL) | ((u64)SD1_DLL_RST << 32), + (u64)SD1_DLL_RST, 0, 0, 0, 0, 0); +#else DllCtrl |= SD1_DLL_RST; + XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl); +#endif } - XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl); /* Wait for 2 micro seconds */ (void)usleep(2U); @@ -1492,11 +1720,26 @@ /* Release the DLL out of reset */ DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL); if (InstancePtr->Config.DeviceId == 0U) { +#if EL1_NONSECURE && defined (__aarch64__) + (void)DllCtrl; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_DLL_CTRL) | ((u64)SD0_DLL_RST << 32), + (u64)0x0, 0, 0, 0, 0, 0); +#else DllCtrl &= ~SD0_DLL_RST; + XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl); +#endif } else { +#if EL1_NONSECURE && defined (__aarch64__) + (void)DllCtrl; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_DLL_CTRL) | ((u64)SD1_DLL_RST << 32), + (u64)0x0, 0, 0, 0, 0, 0); +#else DllCtrl &= ~SD1_DLL_RST; + XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl); +#endif } - XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl); /* Wait for internal clock to stabilize */ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_4/src/xsdps_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps_sinit.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_4/src/xsdps_sinit.c index e0936b3..b49a006 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps_sinit.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_4/src/xsdps_sinit.c
@@ -33,7 +33,7 @@ /** * * @file xsdps_sinit.c -* @addtogroup sdps_v2_5 +* @addtogroup sdps_v3_4 * @{ * * The implementation of the XSdPs component's static initialization
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/sleep.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/sleep.h deleted file mode 100644 index 27add66..0000000 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/sleep.h +++ /dev/null
@@ -1,50 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. -* -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. -* -******************************************************************************/ - -#ifndef SLEEP_H -#define SLEEP_H - -#include "xil_types.h" -#include "xil_io.h" - -#ifdef __cplusplus -extern "C" { -#endif - -int usleep(unsigned long useconds); -unsigned sleep(unsigned int seconds); - -#ifdef __cplusplus -} -#endif - -#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_mpu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_mpu.c deleted file mode 100644 index 7c028c5..0000000 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_mpu.c +++ /dev/null
@@ -1,258 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. -* -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* @file xil_mpu.c -* -* This file provides APIs for enabling/disabling MPU and setting the memory -* attributes for sections, in the MPU translation table. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- --------------------------------------------------- -* 5.00 pkp 02/10/14 Initial version -* </pre> -* -* @note -* -* None. -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xil_cache.h" -#include "xpseudo_asm.h" -#include "xil_types.h" -#include "xil_mpu.h" -#include "xdebug.h" -/***************** Macros (Inline Functions) Definitions *********************/ - -/**************************** Type Definitions *******************************/ - -/************************** Constant Definitions *****************************/ - -/************************** Variable Definitions *****************************/ - -static const struct { - u64 size; - unsigned int encoding; -}region_size[] = { - { 0x20, REGION_32B }, - { 0x40, REGION_64B }, - { 0x80, REGION_128B }, - { 0x100, REGION_256B }, - { 0x200, REGION_512B }, - { 0x400, REGION_1K }, - { 0x800, REGION_2K }, - { 0x1000, REGION_4K }, - { 0x2000, REGION_8K }, - { 0x4000, REGION_16K }, - { 0x8000, REGION_32K }, - { 0x10000, REGION_64K }, - { 0x20000, REGION_128K }, - { 0x40000, REGION_256K }, - { 0x80000, REGION_512K }, - { 0x100000, REGION_1M }, - { 0x200000, REGION_2M }, - { 0x400000, REGION_4M }, - { 0x800000, REGION_8M }, - { 0x1000000, REGION_16M }, - { 0x2000000, REGION_32M }, - { 0x4000000, REGION_64M }, - { 0x8000000, REGION_128M }, - { 0x10000000, REGION_256M }, - { 0x20000000, REGION_512M }, - { 0x40000000, REGION_1G }, - { 0x80000000, REGION_2G }, - { 0x100000000, REGION_4G }, -}; - -/************************** Function Prototypes ******************************/ - -/***************************************************************************** -* -* Set the memory attributes for a section of memory with starting address addr -* of the region size 1MB having attributes attrib -* -* @param addr is the address for which attributes are to be set. -* @param attrib specifies the attributes for that memory region. -* @return None. -* -* -******************************************************************************/ -void Xil_SetTlbAttributes(INTPTR addr, u32 attrib) -{ - INTPTR Localaddr = addr; - Localaddr &= (~(0xFFFFFU)); - /* Setting the MPU region with given attribute with 1MB size */ - Xil_SetMPURegion(Localaddr, 0x100000, attrib); -} - -/***************************************************************************** -* -* Set the memory attributes for a section of memory with starting address addr -* of the region size size and having attributes attrib -* -* @param addr is the address for which attributes are to be set. -* @param size is the size of the region. -* @param attrib specifies the attributes for that memory region. -* @return None. -* -* -******************************************************************************/ -void Xil_SetMPURegion(INTPTR addr, u64 size, u32 attrib) -{ - u32 Regionsize = 0; - INTPTR Localaddr = addr; - u32 NextAvailableMemRegion; - unsigned int i; - - Xil_DCacheFlush(); - Xil_ICacheInvalidate(); - NextAvailableMemRegion = mfcp(XREG_CP15_MPU_MEMORY_REG_NUMBER); - NextAvailableMemRegion++; - if (NextAvailableMemRegion > 16) { - xdbg_printf(DEBUG, "No regions available\r\n"); - return; - } - mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,NextAvailableMemRegion); - isb(); - - /* Lookup the size. */ - for (i = 0; i < sizeof region_size / sizeof region_size[0]; i++) { - if (size <= region_size[i].size) { - Regionsize = region_size[i].encoding; - break; - } - } - - Localaddr &= ~(region_size[i].size - 1); - - Regionsize <<= 1; - Regionsize |= REGION_EN; - dsb(); - mtcp(XREG_CP15_MPU_REG_BASEADDR, Localaddr); /* Set base address of a region */ - mtcp(XREG_CP15_MPU_REG_ACCESS_CTRL, attrib); /* Set the control attribute */ - mtcp(XREG_CP15_MPU_REG_SIZE_EN, Regionsize); /* set the region size and enable it*/ - dsb(); - isb(); -} -/***************************************************************************** -* -* Enable MPU for Cortex R5 processor. This function invalidates I cache and -* flush the D Caches before enabling the MPU. -* -* -* @param None. -* @return None. -* -******************************************************************************/ -void Xil_EnableMPU(void) -{ - u32 CtrlReg, Reg; - s32 DCacheStatus=0, ICacheStatus=0; - /* enable caches only if they are disabled */ - CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); - if ((CtrlReg & XREG_CP15_CONTROL_C_BIT) != 0x00000000U) { - DCacheStatus=1; - } - if ((CtrlReg & XREG_CP15_CONTROL_I_BIT) != 0x00000000U) { - ICacheStatus=1; - } - - if(DCacheStatus != 0) { - Xil_DCacheDisable(); - } - if(ICacheStatus != 0){ - Xil_ICacheDisable(); - } - Reg = mfcp(XREG_CP15_SYS_CONTROL); - Reg |= 0x00000001U; - dsb(); - mtcp(XREG_CP15_SYS_CONTROL, Reg); - isb(); - /* enable caches only if they are disabled in routine*/ - if(DCacheStatus != 0) { - Xil_DCacheEnable(); - } - if(ICacheStatus != 0) { - Xil_ICacheEnable(); - } -} - -/***************************************************************************** -* -* Disable MPU for Cortex R5 processors. This function invalidates I cache and -* flush the D Caches before disabling the MPU. -* -* @param None. -* -* @return None. -* -******************************************************************************/ -void Xil_DisableMPU(void) -{ - u32 CtrlReg, Reg; - s32 DCacheStatus=0, ICacheStatus=0; - /* enable caches only if they are disabled */ - CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); - if ((CtrlReg & XREG_CP15_CONTROL_C_BIT) != 0x00000000U) { - DCacheStatus=1; - } - if ((CtrlReg & XREG_CP15_CONTROL_I_BIT) != 0x00000000U) { - ICacheStatus=1; - } - - if(DCacheStatus != 0) { - Xil_DCacheDisable(); - } - if(ICacheStatus != 0){ - Xil_ICacheDisable(); - } - - mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0); - Reg = mfcp(XREG_CP15_SYS_CONTROL); - Reg &= ~(0x00000001U); - dsb(); - mtcp(XREG_CP15_SYS_CONTROL, Reg); - isb(); - /* enable caches only if they are disabled in routine*/ - if(DCacheStatus != 0) { - Xil_DCacheEnable(); - } - if(ICacheStatus != 0) { - Xil_ICacheEnable(); - } -} \ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xstatus.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xstatus.h deleted file mode 100644 index 4873e85..0000000 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xstatus.h +++ /dev/null
@@ -1,432 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. -* -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xstatus.h -* -* This file contains Xilinx software status codes. Status codes have their -* own data type called int. These codes are used throughout the Xilinx -* device drivers. -* -******************************************************************************/ - -#ifndef XSTATUS_H /* prevent circular inclusions */ -#define XSTATUS_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_assert.h" - -/************************** Constant Definitions *****************************/ - -/*********************** Common statuses 0 - 500 *****************************/ - -#define XST_SUCCESS 0L -#define XST_FAILURE 1L -#define XST_DEVICE_NOT_FOUND 2L -#define XST_DEVICE_BLOCK_NOT_FOUND 3L -#define XST_INVALID_VERSION 4L -#define XST_DEVICE_IS_STARTED 5L -#define XST_DEVICE_IS_STOPPED 6L -#define XST_FIFO_ERROR 7L /* an error occurred during an - operation with a FIFO such as - an underrun or overrun, this - error requires the device to - be reset */ -#define XST_RESET_ERROR 8L /* an error occurred which requires - the device to be reset */ -#define XST_DMA_ERROR 9L /* a DMA error occurred, this error - typically requires the device - using the DMA to be reset */ -#define XST_NOT_POLLED 10L /* the device is not configured for - polled mode operation */ -#define XST_FIFO_NO_ROOM 11L /* a FIFO did not have room to put - the specified data into */ -#define XST_BUFFER_TOO_SMALL 12L /* the buffer is not large enough - to hold the expected data */ -#define XST_NO_DATA 13L /* there was no data available */ -#define XST_REGISTER_ERROR 14L /* a register did not contain the - expected value */ -#define XST_INVALID_PARAM 15L /* an invalid parameter was passed - into the function */ -#define XST_NOT_SGDMA 16L /* the device is not configured for - scatter-gather DMA operation */ -#define XST_LOOPBACK_ERROR 17L /* a loopback test failed */ -#define XST_NO_CALLBACK 18L /* a callback has not yet been - registered */ -#define XST_NO_FEATURE 19L /* device is not configured with - the requested feature */ -#define XST_NOT_INTERRUPT 20L /* device is not configured for - interrupt mode operation */ -#define XST_DEVICE_BUSY 21L /* device is busy */ -#define XST_ERROR_COUNT_MAX 22L /* the error counters of a device - have maxed out */ -#define XST_IS_STARTED 23L /* used when part of device is - already started i.e. - sub channel */ -#define XST_IS_STOPPED 24L /* used when part of device is - already stopped i.e. - sub channel */ -#define XST_DATA_LOST 26L /* driver defined error */ -#define XST_RECV_ERROR 27L /* generic receive error */ -#define XST_SEND_ERROR 28L /* generic transmit error */ -#define XST_NOT_ENABLED 29L /* a requested service is not - available because it has not - been enabled */ - -/***************** Utility Component statuses 401 - 500 *********************/ - -#define XST_MEMTEST_FAILED 401L /* memory test failed */ - - -/***************** Common Components statuses 501 - 1000 *********************/ - -/********************* Packet Fifo statuses 501 - 510 ************************/ - -#define XST_PFIFO_LACK_OF_DATA 501L /* not enough data in FIFO */ -#define XST_PFIFO_NO_ROOM 502L /* not enough room in FIFO */ -#define XST_PFIFO_BAD_REG_VALUE 503L /* self test, a register value - was invalid after reset */ -#define XST_PFIFO_ERROR 504L /* generic packet FIFO error */ -#define XST_PFIFO_DEADLOCK 505L /* packet FIFO is reporting - * empty and full simultaneously - */ - -/************************** DMA statuses 511 - 530 ***************************/ - -#define XST_DMA_TRANSFER_ERROR 511L /* self test, DMA transfer - failed */ -#define XST_DMA_RESET_REGISTER_ERROR 512L /* self test, a register value - was invalid after reset */ -#define XST_DMA_SG_LIST_EMPTY 513L /* scatter gather list contains - no buffer descriptors ready - to be processed */ -#define XST_DMA_SG_IS_STARTED 514L /* scatter gather not stopped */ -#define XST_DMA_SG_IS_STOPPED 515L /* scatter gather not running */ -#define XST_DMA_SG_LIST_FULL 517L /* all the buffer desciptors of - the scatter gather list are - being used */ -#define XST_DMA_SG_BD_LOCKED 518L /* the scatter gather buffer - descriptor which is to be - copied over in the scatter - list is locked */ -#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /* no buffer descriptors have been - put into the scatter gather - list to be commited */ -#define XST_DMA_SG_COUNT_EXCEEDED 521L /* the packet count threshold - specified was larger than the - total # of buffer descriptors - in the scatter gather list */ -#define XST_DMA_SG_LIST_EXISTS 522L /* the scatter gather list has - already been created */ -#define XST_DMA_SG_NO_LIST 523L /* no scatter gather list has - been created */ -#define XST_DMA_SG_BD_NOT_COMMITTED 524L /* the buffer descriptor which was - being started was not committed - to the list */ -#define XST_DMA_SG_NO_DATA 525L /* the buffer descriptor to start - has already been used by the - hardware so it can't be reused - */ -#define XST_DMA_SG_LIST_ERROR 526L /* general purpose list access - error */ -#define XST_DMA_BD_ERROR 527L /* general buffer descriptor - error */ - -/************************** IPIF statuses 531 - 550 ***************************/ - -#define XST_IPIF_REG_WIDTH_ERROR 531L /* an invalid register width - was passed into the function */ -#define XST_IPIF_RESET_REGISTER_ERROR 532L /* the value of a register at - reset was not valid */ -#define XST_IPIF_DEVICE_STATUS_ERROR 533L /* a write to the device interrupt - status register did not read - back correctly */ -#define XST_IPIF_DEVICE_ACK_ERROR 534L /* the device interrupt status - register did not reset when - acked */ -#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /* the device interrupt enable - register was not updated when - other registers changed */ -#define XST_IPIF_IP_STATUS_ERROR 536L /* a write to the IP interrupt - status register did not read - back correctly */ -#define XST_IPIF_IP_ACK_ERROR 537L /* the IP interrupt status register - did not reset when acked */ -#define XST_IPIF_IP_ENABLE_ERROR 538L /* IP interrupt enable register was - not updated correctly when other - registers changed */ -#define XST_IPIF_DEVICE_PENDING_ERROR 539L /* The device interrupt pending - register did not indicate the - expected value */ -#define XST_IPIF_DEVICE_ID_ERROR 540L /* The device interrupt ID register - did not indicate the expected - value */ -#define XST_IPIF_ERROR 541L /* generic ipif error */ - -/****************** Device specific statuses 1001 - 4095 *********************/ - -/********************* Ethernet statuses 1001 - 1050 *************************/ - -#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /* Memory space is not big enough - * to hold the minimum number of - * buffers or descriptors */ -#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /* Memory allocation failed */ -#define XST_EMAC_MII_READ_ERROR 1003L /* MII read error */ -#define XST_EMAC_MII_BUSY 1004L /* An MII operation is in progress */ -#define XST_EMAC_OUT_OF_BUFFERS 1005L /* Driver is out of buffers */ -#define XST_EMAC_PARSE_ERROR 1006L /* Invalid driver init string */ -#define XST_EMAC_COLLISION_ERROR 1007L /* Excess deferral or late - * collision on polled send */ - -/*********************** UART statuses 1051 - 1075 ***************************/ -#define XST_UART - -#define XST_UART_INIT_ERROR 1051L -#define XST_UART_START_ERROR 1052L -#define XST_UART_CONFIG_ERROR 1053L -#define XST_UART_TEST_FAIL 1054L -#define XST_UART_BAUD_ERROR 1055L -#define XST_UART_BAUD_RANGE 1056L - - -/************************ IIC statuses 1076 - 1100 ***************************/ - -#define XST_IIC_SELFTEST_FAILED 1076 /* self test failed */ -#define XST_IIC_BUS_BUSY 1077 /* bus found busy */ -#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /* mastersend attempted with */ - /* general call address */ -#define XST_IIC_STAND_REG_RESET_ERROR 1079 /* A non parameterizable reg */ - /* value after reset not valid */ -#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /* Tx fifo included in design */ - /* value after reset not valid */ -#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /* Rx fifo included in design */ - /* value after reset not valid */ -#define XST_IIC_TBA_REG_RESET_ERROR 1082 /* 10 bit addr incl in design */ - /* value after reset not valid */ -#define XST_IIC_CR_READBACK_ERROR 1083 /* Read of the control register */ - /* didn't return value written */ -#define XST_IIC_DTR_READBACK_ERROR 1084 /* Read of the data Tx reg */ - /* didn't return value written */ -#define XST_IIC_DRR_READBACK_ERROR 1085 /* Read of the data Receive reg */ - /* didn't return value written */ -#define XST_IIC_ADR_READBACK_ERROR 1086 /* Read of the data Tx reg */ - /* didn't return value written */ -#define XST_IIC_TBA_READBACK_ERROR 1087 /* Read of the 10 bit addr reg */ - /* didn't return written value */ -#define XST_IIC_NOT_SLAVE 1088 /* The device isn't a slave */ - -/*********************** ATMC statuses 1101 - 1125 ***************************/ - -#define XST_ATMC_ERROR_COUNT_MAX 1101L /* the error counters in the ATM - controller hit the max value - which requires the statistics - to be cleared */ - -/*********************** Flash statuses 1126 - 1150 **************************/ - -#define XST_FLASH_BUSY 1126L /* Flash is erasing or programming - */ -#define XST_FLASH_READY 1127L /* Flash is ready for commands */ -#define XST_FLASH_ERROR 1128L /* Flash had detected an internal - error. Use XFlash_DeviceControl - to retrieve device specific codes - */ -#define XST_FLASH_ERASE_SUSPENDED 1129L /* Flash is in suspended erase state - */ -#define XST_FLASH_WRITE_SUSPENDED 1130L /* Flash is in suspended write state - */ -#define XST_FLASH_PART_NOT_SUPPORTED 1131L /* Flash type not supported by - driver */ -#define XST_FLASH_NOT_SUPPORTED 1132L /* Operation not supported */ -#define XST_FLASH_TOO_MANY_REGIONS 1133L /* Too many erase regions */ -#define XST_FLASH_TIMEOUT_ERROR 1134L /* Programming or erase operation - aborted due to a timeout */ -#define XST_FLASH_ADDRESS_ERROR 1135L /* Accessed flash outside its - addressible range */ -#define XST_FLASH_ALIGNMENT_ERROR 1136L /* Write alignment error */ -#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /* Couldn't return immediately from - write/erase function with - XFL_NON_BLOCKING_WRITE/ERASE - option cleared */ -#define XST_FLASH_CFI_QUERY_ERROR 1138L /* Failed to query the device */ - -/*********************** SPI statuses 1151 - 1175 ****************************/ - -#define XST_SPI_MODE_FAULT 1151 /* master was selected as slave */ -#define XST_SPI_TRANSFER_DONE 1152 /* data transfer is complete */ -#define XST_SPI_TRANSMIT_UNDERRUN 1153 /* slave underruns transmit register */ -#define XST_SPI_RECEIVE_OVERRUN 1154 /* device overruns receive register */ -#define XST_SPI_NO_SLAVE 1155 /* no slave has been selected yet */ -#define XST_SPI_TOO_MANY_SLAVES 1156 /* more than one slave is being - * selected */ -#define XST_SPI_NOT_MASTER 1157 /* operation is valid only as master */ -#define XST_SPI_SLAVE_ONLY 1158 /* device is configured as slave-only - */ -#define XST_SPI_SLAVE_MODE_FAULT 1159 /* slave was selected while disabled */ -#define XST_SPI_SLAVE_MODE 1160 /* device has been addressed as slave */ -#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /* device received data in slave mode */ - -#define XST_SPI_COMMAND_ERROR 1162 /* unrecognised command - qspi only */ -#define XST_SPI_POLL_DONE 1163 /* controller completed polling the - device for status */ - -/********************** OPB Arbiter statuses 1176 - 1200 *********************/ - -#define XST_OPBARB_INVALID_PRIORITY 1176 /* the priority registers have either - * one master assigned to two or more - * priorities, or one master not - * assigned to any priority - */ -#define XST_OPBARB_NOT_SUSPENDED 1177 /* an attempt was made to modify the - * priority levels without first - * suspending the use of priority - * levels - */ -#define XST_OPBARB_PARK_NOT_ENABLED 1178 /* bus parking by id was enabled but - * bus parking was not enabled - */ -#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /* the arbiter must be in fixed - * priority mode to allow the - * priorities to be changed - */ - -/************************ Intc statuses 1201 - 1225 **************************/ - -#define XST_INTC_FAIL_SELFTEST 1201 /* self test failed */ -#define XST_INTC_CONNECT_ERROR 1202 /* interrupt already in use */ - -/********************** TmrCtr statuses 1226 - 1250 **************************/ - -#define XST_TMRCTR_TIMER_FAILED 1226 /* self test failed */ - -/********************** WdtTb statuses 1251 - 1275 ***************************/ - -#define XST_WDTTB_TIMER_FAILED 1251L - -/********************** PlbArb statuses 1276 - 1300 **************************/ - -#define XST_PLBARB_FAIL_SELFTEST 1276L - -/********************** Plb2Opb statuses 1301 - 1325 *************************/ - -#define XST_PLB2OPB_FAIL_SELFTEST 1301L - -/********************** Opb2Plb statuses 1326 - 1350 *************************/ - -#define XST_OPB2PLB_FAIL_SELFTEST 1326L - -/********************** SysAce statuses 1351 - 1360 **************************/ - -#define XST_SYSACE_NO_LOCK 1351L /* No MPU lock has been granted */ - -/********************** PCI Bridge statuses 1361 - 1375 **********************/ - -#define XST_PCI_INVALID_ADDRESS 1361L - -/********************** FlexRay constants 1400 - 1409 *************************/ - -#define XST_FR_TX_ERROR 1400 -#define XST_FR_TX_BUSY 1401 -#define XST_FR_BUF_LOCKED 1402 -#define XST_FR_NO_BUF 1403 - -/****************** USB constants 1410 - 1420 *******************************/ - -#define XST_USB_ALREADY_CONFIGURED 1410 -#define XST_USB_BUF_ALIGN_ERROR 1411 -#define XST_USB_NO_DESC_AVAILABLE 1412 -#define XST_USB_BUF_TOO_BIG 1413 -#define XST_USB_NO_BUF 1414 - -/****************** HWICAP constants 1421 - 1429 *****************************/ - -#define XST_HWICAP_WRITE_DONE 1421 - - -/****************** AXI VDMA constants 1430 - 1440 *****************************/ - -#define XST_VDMA_MISMATCH_ERROR 1430 - -/*********************** NAND Flash statuses 1441 - 1459 *********************/ - -#define XST_NAND_BUSY 1441L /* Flash is erasing or - * programming - */ -#define XST_NAND_READY 1442L /* Flash is ready for commands - */ -#define XST_NAND_ERROR 1443L /* Flash had detected an - * internal error. - */ -#define XST_NAND_PART_NOT_SUPPORTED 1444L /* Flash type not supported by - * driver - */ -#define XST_NAND_OPT_NOT_SUPPORTED 1445L /* Operation not supported - */ -#define XST_NAND_TIMEOUT_ERROR 1446L /* Programming or erase - * operation aborted due to a - * timeout - */ -#define XST_NAND_ADDRESS_ERROR 1447L /* Accessed flash outside its - * addressible range - */ -#define XST_NAND_ALIGNMENT_ERROR 1448L /* Write alignment error - */ -#define XST_NAND_PARAM_PAGE_ERROR 1449L /* Failed to read parameter - * page of the device - */ -#define XST_NAND_CACHE_ERROR 1450L /* Flash page buffer error - */ - -#define XST_NAND_WRITE_PROTECTED 1451L /* Flash is write protected - */ - -/**************************** Type Definitions *******************************/ - -typedef s32 XStatus; - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/Makefile similarity index 83% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/Makefile rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/Makefile index ca8621a..325e105 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/Makefile +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/Makefile
@@ -42,17 +42,19 @@ ECC_FLAGS = $(subst -pg, -DPROFILING, $(EXTRA_COMPILER_FLAGS)) ifeq ($(notdir $(CC)), armr5-none-eabi-gcc) -ECC_FLAGS += -nostartfiles\ - -mfloat-abi=soft\ - -mfpu=vfpv3-d16 +ECC_FLAGS += -nostartfiles endif +ECC_FLAGS_NO_FLTO1 = $(subst -flto,,$(ECC_FLAGS)) +ECC_FLAGS_NO_FLTO = $(subst -ffat-lto-objects,,$(ECC_FLAGS_NO_FLTO1)) + RELEASEDIR=../../../lib INCLUDEDIR=../../../include INCLUDES=-I./. -I${INCLUDEDIR} OUTS = *.o - +OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) +ASSEMBLY_OBJECTS = $(addsuffix .o, $(basename $(wildcard *.S))) INCLUDEFILES=*.h INCLUDEFILES+=includes_ps/*.h @@ -60,7 +62,8 @@ standalone_libs: $(LIBSOURCES) echo "Compiling standalone R5" - $(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $^ + $(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(filter-out _exit.c, $^) + $(CC) $(CC_FLAGS) $(ECC_FLAGS_NO_FLTO) $(INCLUDES) _exit.c $(AR) -r ${RELEASEDIR}/${LIB} ${OUTS} .PHONY: include @@ -70,5 +73,5 @@ ${CP} ${INCLUDEFILES} ${INCLUDEDIR} clean: - rm -rf ${OUTS} - $(MAKE) -C COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" clean + rm -rf ${OBJECTS} + rm -rf ${ASSEMBLY_OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/_exit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/_exit.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/_exit.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/_exit.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/_open.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/_open.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/_open.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/_open.c index 9b5a23a..a108b77 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/_open.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/_open.c
@@ -45,7 +45,7 @@ */ __attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode) { - (void *)buf; + (void)buf; (void)flags; (void)mode; errno = EIO;
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/_sbrk.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/_sbrk.c similarity index 95% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/_sbrk.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/_sbrk.c index 2a069ec..967bdfc 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/_sbrk.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/_sbrk.c
@@ -54,15 +54,10 @@ } prev_heap = heap; + if (((heap + incr) <= HeapEndPtr) && (prev_heap != NULL)) { heap += incr; - - if (heap > HeapEndPtr){ - Status = (caddr_t) -1; - } - else if (prev_heap != NULL) { Status = (caddr_t) ((void *)prev_heap); - } - else { + } else { Status = (caddr_t) -1; }
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/abort.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/abort.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/abort.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/abort.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/asm_vectors.S b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/asm_vectors.S similarity index 93% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/asm_vectors.S rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/asm_vectors.S index 2c6f117..efdf629 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/asm_vectors.S +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/asm_vectors.S
@@ -42,6 +42,7 @@ * ----- ------- -------- --------------------------------------------------- * 5.00 pkp 02/10/14 Initial version * 6.0 mus 27/07/16 Added UndefinedException handler +* 6.3 pkp 02/13/17 Added support for hard float * </pre> * * @note @@ -78,10 +79,25 @@ .text IRQHandler: /* IRQ vector handler */ stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code*/ +#ifndef __SOFTFP__ + + vpush {d0-d7} /* Store floating point registers */ + vmrs r1, FPSCR + push {r1} + vmrs r1, FPEXC + push {r1} +#endif bl IRQInterrupt /* IRQ vector */ +#ifndef __SOFTFP__ + + pop {r1} /* Restore floating point registers */ + vmsr FPEXC, r1 + pop {r1} + vmsr FPSCR, r1 + vpop {d0-d7} +#endif ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */ subs pc, lr, #4 /* adjust return */ - FIQHandler: /* FIQ vector handler */ stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */ FIQLoop:
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/boot.S b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/boot.S similarity index 85% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/boot.S rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/boot.S index 30b97cb..d9d2f1e 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/boot.S +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/boot.S
@@ -33,7 +33,26 @@ /** * @file boot.S * -* This file contains the initial startup code for the Cortex R5 processor +* @addtogroup r5_boot_code Cortex R5 Processor Boot Code +* @{ +* <h2> boot.S </h2> +* The boot code performs minimum configuration which is required for an +* application to run starting from processor's reset state. Below is a +* sequence illustrating what all configuration is performed before control +* reaches to main function. +* +* 1. Program vector table base for exception handling +* 2. Program stack pointer for various modes (IRQ, FIQ, supervisor, undefine, +* abort, system) +* 3. Disable instruction cache, data cache and MPU +* 4. Invalidate instruction and data cache +* 5. Configure MPU with short descriptor translation table format and program +* base address of translation table +* 6. Enable data cache, instruction cache and MPU +* 7. Enable Floating point unit +* 8. Transfer control to _start which clears BSS sections and jumping to main +* application +* * * <pre> * MODIFICATION HISTORY: @@ -52,12 +71,12 @@ * to avoid intervention for lock-step mode * 5.05 pkp 04/11/16 Enable the comparators for non-JTAG boot mode for * lock-step to avoid putting debug logic to reset +* 6.02 pkp 02/13/17 Added support for hard float +* 6.6 mus 02/23/17 Enable/Disable the debug logic in non-JTAG boot mode(when +* processor is in lockstep configuration), based +* on the mld parameter "lockstep_mode_debug". * </pre> * -* @note -* -* None. -* ******************************************************************************/ #include "xparameters.h" @@ -202,8 +221,10 @@ vmov d14,r1,r1 vmov d15,r1,r1 -/* restore previous value for fpu access */ +#ifdef __SOFTFP__ +/* Disable the FPU if SOFTFP is defined*/ vmsr FPEXC,r3 +#endif /* Disable MPU and caches */ mrc p15, 0, r0, c1, c0, 0 /* Read CP15 Control Register*/ @@ -218,12 +239,12 @@ orr r0, r0, #(0x1 << 17) /* Enable RSDIS bit 17 to disable the return stack */ orr r0, r0, #(0x1 << 16) /* Clear BP bit 15 and set BP bit 16:*/ bic r0, r0, #(0x1 << 15) /* Branch always not taken and history table updates disabled*/ - bic r0, r0, #(0x1 << 27) /* Disable B1TCM ECC check */ - bic r0, r0, #(0x1 << 26) /* Disable B0TCM ECC check */ - bic r0, r0, #(0x1 << 25) /* Disable ATCM ECC check */ - orr r0, r0, #(0x1 << 5) /* Enable ECC with no forced write through with [5:3]=b'101*/ + orr r0, r0, #(0x1 << 27) /* Enable B1TCM ECC check */ + orr r0, r0, #(0x1 << 26) /* Enable B0TCM ECC check */ + orr r0, r0, #(0x1 << 25) /* Enable ATCM ECC check */ + bic r0, r0, #(0x1 << 5) /* Generate abort on parity errors, with [5:3]=b 000*/ bic r0, r0, #(0x1 << 4) - orr r0, r0, #(0x1 << 3) + bic r0, r0, #(0x1 << 3) mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR*/ dsb /* Complete all outstanding explicit memory operations*/ @@ -233,7 +254,7 @@ mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */ mcr p15, 0, r0, c15, c5, 0 /* Invalidate entire data cache*/ isb - +#if LOCKSTEP_MODE_DEBUG == 0 /* enable fault log for lock step */ ldr r0,=RPU_GLBL_CNTL ldr r1, [r0] @@ -260,6 +281,7 @@ str r2, [r0] nop nop +#endif init: bl Init_MPU /* Initialize MPU */ @@ -306,3 +328,6 @@ .end +/** +* @} End of "addtogroup r5_boot_code". +*/
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/bspconfig.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/bspconfig.h similarity index 89% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/bspconfig.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/bspconfig.h index 8671e3f..9427ad0 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/bspconfig.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/bspconfig.h
@@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -37,4 +37,9 @@ * *******************************************************************/ +#ifndef BSPCONFIG_H /* prevent circular inclusions */ +#define BSPCONFIG_H /* by using protection macros */ + #define MICROBLAZE_PVR_NONE + +#endif /*end of __BSPCONFIG_H_*/
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/changelog.txt b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/changelog.txt similarity index 71% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/changelog.txt rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/changelog.txt index f663af1..6414440 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/changelog.txt +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/changelog.txt
@@ -399,4 +399,141 @@ * ::hsi::utils::handle_stdin and ::hsi::utils::handle_stdout are taken as a base for * these APIs and modifications are done on top of it to handle stdout/stdin * parameters for design which doesnt have UART.It fixes CR#953681 + * 6.1 nsk 11/07/16 Added two new files xil_mem.c and xil_mem.h for xil_memcpy + * 6.2 pkp 12/14/16 Updated cortexa53/64bit/translation_table.S for upper ps DDR. The 0x800000000 - + * 0xFFFFFFFFF range is marked normal memory for the DDR size defined in hdf + * and rest of the memory in that 32GB region is marked as reserved to avoid + * any speculative access + * 6.2 pkp 12/23/16 Added support for floating point operation to Cortex-A53 64bit mode. It modified + * asm_vectors.S to implement lazy floating point context saving i.e. floating point + * access is enabled if there is any floating point operation, it is disabled by + * default. Also FPU is initally disabled for IRQ and none of the floating point + * registers are saved during normal context saving. If IRQ handler does not require + * floating point operation, the floating point registers are untouched and no need + * for saving/restoring. If IRQ handler uses any floating point operation, then floating + * point registers are saved and FPU is enabled for IRQ handler. Then floating point + * registers are restored back after servicing IRQ during normal context restoring. + * 6.2 mus 01/01/17 Updated makefiles of R5 and a53 64 bit/32 bit processors to fix error in clean + * target.It fixes the CR#966900 + * 6.2 pkp 01/22/17 Added support for EL1 non-secure execution and Hypervisor Baremetal for Cortex-A53 + * 64bit Mode. If Hypervisor_guest is selected as true in BSP settings, BSP will be built + * for EL1 Non-secure, else BSP will be built for EL3. By default hypervisor_guest is + * as false i.e. default bsp is EL3. + * 6.2 pkp 01/24/17 Updated cortexa53/64bit/boot.S to clear FPUStatus variable to make sure that it + * contains initial status of FPU i.e. disabled. In case of a warm restart execution + * when bss sections are not cleared, it may contain previously updated value which + * does not hold true once processor resumes. This fixes CR#966826. + * 6.2 asa 01/31/17 The existing Xil_DCacheDisable API first flushes the + * D caches and then disables it. The problem with that is, + * potentially there will be a small window after the cache + * flush operation and before the we disable D caches where + * we might have valid data in cache lines. In such a + * scenario disabling the D cache can lead to unknown behavior. + * The ideal solution to this is to use assembly code for + * the complete API and avoid any memory accesses. But with + * that we will end up having a huge amount on assembly code + * which is not maintainable. Changes are done to use a mix + * of assembly and C code. All local variables are put in + * registers. Also function calls are avoided in the API to + * avoid using stack memory. + * 6.2 mus 02/13/17 A53 CPU cache system can pre-fetch catch lines.So there are + * scenarios when an invalidated cache line can get pre fetched to cache. + * If that happens, the coherency between cache and memory is lost + * resulting in lost data. To avoid this kind of issue either + * user has to use dsb() or disable pre-fetching for L1 cache + * or else reduce maximum number of outstanding data prefetches allowed. + * Using dsb() while comparing data costing more performance compared to + * disabling pre-fetching/reducing maximum number of outstanding data + * prefetches for L1 Cache.The new api Xil_ConfigureL1Prefetch is added + * to disable pre-fetching/configure maximum number of outstanding data + * prefetches allowed in L1 cache system.This fixes CR#967864. + * 6.2 pkp 02/16/17 Added xil_smc.c file to provide a C wrapper for smc calling which can be + * used by cortex-A53 64bit EL1 Non-secure application. + * 6.2 kvn 03/03/17 Added support thumb mode + * 6.2 mus 03/13/17 Fixed MISRA C mandatory standard violations in ARM cortexr5 and cortexa53 BSP. + * It fixes CR#970543 + * 6.2 asa 03/16/17 Fix for CR#970859. For Mcroblaze BSP, when we enable intrusive + * profiling we see a crash. That is because the the tcl uses invalid + * HSI command. This change fixes it. + * 6.2 mus 03/22/17 Updated standalone tcl to generate xparameter XPAR_FPD_IS_CACHE_COHERENT, if + * any FPD peripheral is configured to use CCI.It fixes CR#972638 + * 6.3 mus 03/20/17 Updated cortex-r5 BSP, to add hard floating point support. + * 6.3 mus 04/17/17 Updated Cortex-a53 32 bit BSP boot code to fix bug in + * the HW coherency enablement. It fixes the CR#973287 + * 6.3 mus 04/20/17 Updated Cortex-A53 64 bit BSP boot code, to remove redundant write to the + * L2CTLR_EL1 register. It fixes the CR#974698 + * 6.4 mus 06/08/17 Updated arm/common/xil_exception.c to fix warnings in C level exception handlers + * of ARM 32 bit processor's. + * 6.4 mus 06/14/17 Updated cortexa53/64bit/gcc/asm_vectors.S to fix bug in IRQInterruptHandler code + * snippet, which checks for the FPEN bit of CPACR_EL1 register. + * 6.4 ms 05/23/17 Added PSU_PMU macro in xplatform_info.c, xparameters.h to support + * XGetPSVersion_Info function for PMUFW. + * ms 06/13/17 Added PSU_PMU macro in xplatform_info.c to support XGetPlatform_Info + * function for PMUFW. + * 6.4 mus 07/05/17 Updated Xil_In32BE function in xil_io.h to fix bug.It fixes CR#979740. + * 6.4 mus 07/25/17 Updated a53 32 bit boot code and vectors to support hard floating point + * operations.Now,VFP is being enabled in FPEXC register, through boot code + * and FPU registers are being saved/restored when irq/fiq vector is invoked. + * 6.4 adk 08/01/17 Updated standalone tcl to generate xparameter XPAR_PL_IS_CACHE_COHERENT, + * if h/w design configured with HPC port. + * 6.4 mus 08/10/17 Updated a53 64 bit translation table to mark memory as a outer shareable for + * EL1 NS execution. This change has been done to support CCI enabled IP's. + * 6.4 mus 08/11/17 Updated a53 64 bit boot code to implement ARM erratum 855873.This fixes + * CR#982209. + * 6.4 asa 08/16/17 Made several changes in the R5 MPU handling logic. Added new APIs to + * make RPU MPU handling user-friendly. This also fixes the CR-981028. + * 6.4 mus 08/17/17 Updated XGet_Zynq_UltraMp_Platform_info and XGetPSVersion_Info APIs to read + * version register through SMC call, over EL1 NS mode. This change has been done to + * support these APIs over EL1 NS mode. + * 6.5 mus 10/20/17 Updated standalone.tcl to fix bug in mb_can_handle_exceptions_in_delay_slots proc, + * it fixes CR#987464. + * 6.6 mus 12/07/17 Updated cortexa9/xil_errata.h and cortexa9/xil_cache.c to remove Errata 753970. + * It fixes CR#989132. + * srm 10/18/17 Updated all the sleep routines in a9,a53,R5,microblaze. Now the sleep routines + * will use the timer specified by the user to provide delay. A9 and A53 can use + * Global timer or TTC. R5 can use TTC or the machine cycles. Microblaze can use + * machine cycles or Axi timer. Updated standalone.tcl and standalone.mld files + * to support the sleep configuration Added new API's for the Axi timer in + * microblaze and TTC in ARM. Added two new files, xil_sleeptimer.c and + * xil_sleeptimer.h in ARM for the common sleep routines and 1 new file, + * xil_sleepcommon.c in Standalone-common for sleep/usleep API's. + * 6.6 hk 12/15/17 Export platform macros to bspconfig.h based on the processor. + * 6.6 asa 1/16/18 Ensure C stack information for A9 are flushed out from L1 D cache + * or L2 cache only when the respective caches are enabled. This fixes CR-922023. + * 6.6 mus 01/19/18 Updated asm_vectors.S and boot.S in Cortexa53 64 bit BSP, to add isb + * after writing to cpacr_el1/cptr_el3 registers. It would ensure + * disabling/enabling of floating-point unit, before any subsequent + * instruction. + * 6.6 mus 01/30/18 Updated hypervisor enabled Cortexa53 64 bit BSP, to add xen PV console + * support. Now, xil_printf would use PV console instead of UART in case of + * hypervisor enabled BSP. + * 6.6 mus 02/02/18 Updated get_connected_if proc in standalone tcl to detect the HPC port + * configured with smart interconnect.It fixes CR#990318. + * 6.6 srm 02/10/18 Updated csu_wdt interrupt to the correct value. Fixes CR#992229 + * 6.6 asa 02/12/18 Fix for heap handling for ARM platforms. CR#993932. + * 6.6 mus 02/19/18 Updated standalone.tcl to fix bug in handle_profile_opbtimer proc, + * CR#995014. + * 6.6 mus 02/23/18 Presently Cortex R5 BSP boot code is disabling the debug logic in +* non-JTAG boot mode, when processor is in lockstep configuration. +* This behavior is restricting application debugging in non-JTAG boot +* mode. To get rid of this restriction, added new mld parameter +* "lockstep_mode_debug", to enable/disable debug logic from BSP +* settings. Now, debug logic can be enabled through BSP settings, +* by modifying value of parameter "lockstep_mode_debug" as "true". +* It fixes CR#993896. + * 6.6.mus 02/27/18 Updated Xil_DCacheInvalidateRange and +* Xil_ICacheInvalidateRange APIs in Cortexa53 64 bit BSP, to fix bug +* in handling upper DDR addresses.It fixes CR#995581. +* 6.6 mus 03/12/18 Updated makefile of Cortexa53 32bit BSP to add includes_ps directory +* in the list of include paths. This change allows applications/BSP +* files to include .h files in include_ps directory. +* 6.6 mus 03/16/18 By default CPUACTLR_EL1 is accessible only from EL3, it +* results into abort if accessed from EL1 non secure privilege +* level. Updated Xil_ConfigureL1Prefetch function in Cortexa53 64 bit BSP +* to avoid CPUACTLR_EL1 access from privile levels other than EL3. +* 6.6 mus 03/16/18 Updated hypervisor enabled BSP to use PV console, based on the +* XEN_USE_PV_CONSOLE flag. By deafault hypervisor enabled BSP would +* use UART console, PV console can be enabled by appending + "-DXEN_USE_PV_CONSOLE" to the BSP extra compiler flags. + * *****************************************************************************************/
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/close.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/close.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/close.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/close.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/config.make b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/config.make similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/config.make rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/config.make
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/cpu_init.S b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/cpu_init.S similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/cpu_init.S rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/cpu_init.S
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/errno.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/errno.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/errno.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/errno.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/fcntl.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/fcntl.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/fcntl.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/fcntl.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/fstat.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/fstat.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/fstat.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/fstat.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/getpid.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/getpid.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/getpid.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/getpid.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/inbyte.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/inbyte.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/inbyte.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/inbyte.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu0_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu0_cfg.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu0_cfg.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu0_cfg.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu1_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu1_cfg.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu1_cfg.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu1_cfg.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu2_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu2_cfg.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu2_cfg.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu2_cfg.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu3_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu3_cfg.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu3_cfg.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu3_cfg.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu4_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu4_cfg.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu4_cfg.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu4_cfg.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu5_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu5_cfg.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu5_cfg.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu5_cfg.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_slcr.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xfpd_slcr.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_slcr.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xfpd_slcr.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_slcr_secure.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xfpd_slcr_secure.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_slcr_secure.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xfpd_slcr_secure.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_xmpu_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xfpd_xmpu_cfg.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_xmpu_cfg.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xfpd_xmpu_cfg.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_xmpu_sink.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xfpd_xmpu_sink.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_xmpu_sink.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xfpd_xmpu_sink.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xiou_secure_slcr.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xiou_secure_slcr.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xiou_secure_slcr.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xiou_secure_slcr.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xiou_slcr.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xiou_slcr.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xiou_slcr.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xiou_slcr.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_slcr.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xlpd_slcr.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_slcr.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xlpd_slcr.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_slcr_secure.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xlpd_slcr_secure.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_slcr_secure.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xlpd_slcr_secure.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_xppu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xlpd_xppu.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_xppu.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xlpd_xppu.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_xppu_sink.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xlpd_xppu_sink.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_xppu_sink.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xlpd_xppu_sink.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xocm_xmpu_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xocm_xmpu_cfg.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xocm_xmpu_cfg.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xocm_xmpu_cfg.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/isatty.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/isatty.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/isatty.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/isatty.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/kill.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/kill.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/kill.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/kill.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/lseek.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/lseek.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/lseek.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/lseek.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/mpu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/mpu.c similarity index 93% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/mpu.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/mpu.c index 55cdd49..6d7054e 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/mpu.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/mpu.c
@@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved. +* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -44,6 +44,7 @@ * 5.04 pkp 12/18/15 Updated MPU initialization as per the proper address map * 6.00 pkp 06/27/16 moving the Init_MPU code to .boot section since it is a * part of processor boot process +* 6.2 mus 01/27/17 Updated to support IAR compiler * </pre> * * @note @@ -102,10 +103,16 @@ }; /************************** Function Prototypes ******************************/ +#if defined (__GNUC__) void Init_MPU(void) __attribute__((__section__(".boot"))); static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib) __attribute__((__section__(".boot"))); static void Xil_DisableMPURegions(void) __attribute__((__section__(".boot"))); - +#elif defined (__ICCARM__) +#pragma default_function_attributes = @ ".boot" +void Init_MPU(void); +static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib); +static void Xil_DisableMPURegions(void); +#endif /***************************************************************************** * * Initialize MPU for a given address map and Enabled the background Region in @@ -122,7 +129,7 @@ void Init_MPU(void) { u32 Addr; - u32 RegSize; + u32 RegSize = 0U; u32 Attrib; u32 RegNum = 0, i; u64 size; @@ -270,11 +277,15 @@ ******************************************************************************/ static void Xil_DisableMPURegions(void) { - u32 Temp; - u32 Index; + u32 Temp = 0U; + u32 Index = 0U; for (Index = 0; Index <= 15; Index++) { mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,Index); +#if defined (__GNUC__) Temp = mfcp(XREG_CP15_MPU_REG_SIZE_EN); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_MPU_REG_SIZE_EN,Temp); +#endif Temp &= (~REGION_EN); dsb(); mtcp(XREG_CP15_MPU_REG_SIZE_EN,Temp); @@ -283,3 +294,7 @@ } } + +#if defined (__ICCARM__) +#pragma default_function_attributes = +#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/open.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/open.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/open.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/open.c index 4b51839..85e9ce4 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/open.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/open.c
@@ -44,7 +44,7 @@ */ __attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode) { - (void *)buf; + (void)buf; (void)flags; (void)mode; errno = EIO;
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/outbyte.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/outbyte.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/outbyte.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/outbyte.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/print.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/print.c similarity index 90% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/print.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/print.c index 74d70ee..da7e768 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/print.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/print.c
@@ -21,6 +21,9 @@ void print(const char8 *ptr) { +#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE + XPVXenConsole_Write(ptr); +#else #ifdef STDOUT_BASEADDRESS while (*ptr != (char8)0) { outbyte (*ptr); @@ -29,4 +32,5 @@ #else (void)ptr; #endif +#endif }
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/putnum.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/putnum.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/putnum.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/putnum.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/read.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/read.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/read.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/read.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/sbrk.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/sbrk.c similarity index 94% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/sbrk.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/sbrk.c index 64d5156..87a753d 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/sbrk.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/sbrk.c
@@ -51,12 +51,8 @@ static char8 *heap_ptr = HeapBase; base = heap_ptr; - if(heap_ptr != NULL) { + if((heap_ptr != NULL) && (heap_ptr + nbytes <= (char8 *)&HeapLimit + 1)) { heap_ptr += nbytes; - } - -/* if (heap_ptr <= ((char8 *)&_heap_end + 1)) */ - if (heap_ptr <= ((char8 *)&HeapLimit + 1)) { return base; } else { errno = ENOMEM;
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/sleep.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/sleep.c similarity index 61% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/sleep.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/sleep.c index 74c7ec2..d5e56c5 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/sleep.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/sleep.c
@@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved. +* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,8 +33,9 @@ * * @file sleep.c * -* This function provides a second delay using the Global Timer register in -* the ARM Cortex R5 MP core. +* This function supports user configurable sleep implementation. +* This provides delay in seconds by using the Timer specified by +* the user in the ARM Cortex R5 MP core. * * <pre> * MODIFICATION HISTORY: @@ -50,6 +51,9 @@ * 5.04 pkp 03/11/16 Compare the counter value to previously read value * to detect the overflow for TTC3 * 6.0 asa 08/15/16 Updated the sleep signature. Fix for CR#956899. +* 6.6 srm 10/18/17 Updated sleep routines to support user configurable +* implementation. Now sleep routines will use TTC +* instance specified by user. * </pre> * ******************************************************************************/ @@ -59,6 +63,10 @@ #include "xtime_l.h" #include "xparameters.h" +#if defined (SLEEP_TIMER_BASEADDR) +#include "xil_sleeptimer.h" +#endif + /*****************************************************************************/ /* * @@ -68,59 +76,45 @@ * * @return 0 always * -* @note The sleep API is implemented using TTC3 counter 0 timer if present. -* When TTC3 is absent, sleep is implemented using assembly -* instructions which is tested with instruction and data caches -* enabled and it gives proper delay. It may give more delay than -* exepcted when caches are disabled. If interrupt comes when sleep -* using assembly instruction is being executed, the delay may be -* greater than what is expected since once the interrupt is served -* count resumes from where it was interrupted unlike the case of TTC3 -* where counter keeps running while interrupt is being served. +* @note By default, sleep is implemented using TTC3. Although user is +* given an option to select other instances of TTC. When the user +* selects other instances of TTC, sleep is implemented by that +* specific TTC instance. If the user didn't select any other instance +* of TTC specifically and when TTC3 is absent, sleep is implemented +* using assembly instructions which is tested with instruction and +* data caches enabled and it gives proper delay. It may give more +* delay than exepcted when caches are disabled. If interrupt comes +* when sleep using assembly instruction is being executed, the delay +* may be greater than what is expected since once the interrupt is +* served count resumes from where it was interrupted unlike the case +* of TTC3 where counter keeps running while interrupt is being served. * ****************************************************************************/ -unsigned sleep(unsigned int seconds) +unsigned sleep_R5(unsigned int seconds) { -#ifdef SLEEP_TIMER_BASEADDR - u64 tEnd; - u64 tCur; - u32 TimeHighVal; - XTime TimeLowVal1; - XTime TimeLowVal2; - - TimeHighVal = 0; - - XTime_GetTime(&TimeLowVal1); - tEnd = (u64)TimeLowVal1 + (((u64) seconds) * COUNTS_PER_SECOND); - - do - { - - XTime_GetTime(&TimeLowVal2); - if (TimeLowVal2 < TimeLowVal1) { - TimeHighVal++; - } - - TimeLowVal1 = TimeLowVal2; - tCur = (((u64) TimeHighVal) << 32U) | (u64)TimeLowVal2; - - } while (tCur < tEnd); - - return 0; +#if defined (SLEEP_TIMER_BASEADDR) + Xil_SleepTTCCommon(seconds, COUNTS_PER_SECOND); #else +#if defined (__GNUC__) __asm__ __volatile__ ( - " push {r0,r1} \n\t" - " mov r0, %[sec] \n\t" - " 1: \n\t" - " mov r1, %[iter] \n\t" - " 2: \n\t" - " subs r1, r1, #0x1 \n\t" - " bne 2b \n\t" - " subs r0,r0,#0x1 \n\t" - " bne 1b \n\t" - " pop {r0,r1} \n\t" - :: [iter] "r" (ITERS_PER_SEC), [sec] "r" (seconds) - ); +#elif defined (__ICCARM__) + __asm volatile ( #endif + "push {r0,r1,r3} \n" + "mov r0, %[sec] \n" + "mov r1, %[iter] \n" + "1: \n" + "mov r3, r1\n" + "2: \n" + "subs r3, r3, #0x1 \n" + "bne 2b \n" + "subs r0, r0, #0x1 \n" + "bne 1b \n" + "pop {r0,r1,r3} \n" + ::[iter] "r" (ITERS_PER_SEC), [sec] "r" (seconds) + ); +#endif + +return 0; }
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/sleep.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/sleep.h new file mode 100644 index 0000000..f53b2d8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/sleep.h
@@ -0,0 +1,119 @@ +/****************************************************************************** +* +* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/*****************************************************************************/ +/** +* @file sleep.h +* +* This header file contains ARM Cortex A53,A9,R5,Microblaze specific sleep +* related APIs. +* +* <pre> +* MODIFICATION HISTORY : +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 6.6 srm 11/02/17 Added processor specific sleep rountines +* function prototypes. +* +* </pre> +* +******************************************************************************/ + +#ifndef SLEEP_H +#define SLEEP_H + +#include "xil_types.h" +#include "xil_io.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/*****************************************************************************/ +/** +* +* This macro polls an address periodically until a condition is met or till the +* timeout occurs. +* The minimum timeout for calling this macro is 100us. If the timeout is less +* than 100us, it still waits for 100us. Also the unit for the timeout is 100us. +* If the timeout is not a multiple of 100us, it waits for a timeout of +* the next usec value which is a multiple of 100us. +* +* @param IO_func - accessor function to read the register contents. +* Depends on the register width. +* @param ADDR - Address to be polled +* @param VALUE - variable to read the value +* @param COND - Condition to checked (usually involves VALUE) +* @param TIMEOUT_US - timeout in micro seconds +* +* @return 0 - when the condition is met +* -1 - when the condition is not met till the timeout period +* +* @note none +* +*****************************************************************************/ +#define Xil_poll_timeout(IO_func, ADDR, VALUE, COND, TIMEOUT_US) \ + ( { \ + u64 timeout = TIMEOUT_US/100; \ + if(TIMEOUT_US%100!=0) \ + timeout++; \ + for(;;) { \ + VALUE = IO_func(ADDR); \ + if(COND) \ + break; \ + else { \ + usleep(100); \ + timeout--; \ + if(timeout==0) \ + break; \ + } \ + } \ + (timeout>0) ? 0 : -1; \ + } ) + +void usleep(unsigned long useconds); +void sleep(unsigned int seconds); +int usleep_R5(unsigned long useconds); +unsigned sleep_R5(unsigned int seconds); +int usleep_MB(unsigned long useconds); +unsigned sleep_MB(unsigned int seconds); +int usleep_A53(unsigned long useconds); +unsigned sleep_A53(unsigned int seconds); +int usleep_A9(unsigned long useconds); +unsigned sleep_A9(unsigned int seconds); + +#ifdef __cplusplus +} +#endif + +#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/uart.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/uart.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/uart.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/uart.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/unlink.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/unlink.c similarity index 98% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/unlink.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/unlink.c index 84e44a4..d0cc680 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/unlink.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/unlink.c
@@ -44,7 +44,7 @@ */ __attribute__((weak)) sint32 unlink(char8 *path) { - (void *)path; + (void) path; errno = EIO; return (-1); }
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/usleep.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/usleep.c similarity index 62% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/usleep.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/usleep.c index ff01dfd..a245f4f 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/usleep.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/usleep.c
@@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved. +* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -34,7 +34,8 @@ * * @file usleep.c * -* This function provides a microsecond delay using the Global Timer register in +* This function supports user configurable sleep implementation. +* This provides a microsecond delay using the timer specified by the user in * the ARM Cortex R5 MP core. * * <pre> @@ -51,6 +52,10 @@ * 5.04 pkp 03/11/16 Compare the counter value to previously read value * to detect the overflow for TTC3 * 6.0 asa 08/15/16 Updated the usleep signature. Fix for CR#956899. +* 6.6 srm 10/18/17 Updated sleep routines to support user configurable +* implementation. Now sleep routines will use TTC +* instance specified by user. +* * </pre> * ******************************************************************************/ @@ -63,6 +68,10 @@ #include "xpseudo_asm.h" #include "xreg_cortexr5.h" +#if defined (SLEEP_TIMER_BASEADDR) +#include "xil_sleeptimer.h" +#endif + /*****************************************************************************/ /** * @@ -72,57 +81,45 @@ * * @return 0 always * -* @note The usleep API is implemented using TTC3 counter 0 timer if present -* When TTC3 is absent, usleep is implemented using assembly -* instructions which is tested with instruction and data caches -* enabled and it gives proper delay. It may give more delay than -* exepcted when caches are disabled. If interrupt comes when usleep -* using assembly instruction is being executed, the delay may be -* greater than what is expected since once the interrupt is served -* count resumes from where it was interrupted unlike the case of TTC3 -* where counter keeps running while interrupt is being served. +* @note By default, usleep is implemented using TTC3. Although user is +* given an option to select other instances of TTC. When the user +* selects other instances of TTC, usleep is implemented by that +* specific TTC instance. If the user didn't select any other instance +* of TTC specifically and when TTC3 is absent, usleep is implemented +* using assembly instructions which is tested with instruction and +* data caches enabled and it gives proper delay. It may give more +* delay than exepcted when caches are disabled. If interrupt comes +* when usleep using assembly instruction is being executed, the delay +* may be greater than what is expected since once the interrupt is +* served count resumes from where it was interrupted unlike the case +* of TTC3 where counter keeps running while interrupt is being served. * ****************************************************************************/ -int usleep(unsigned long useconds) +int usleep_R5(unsigned long useconds) { - -#ifdef SLEEP_TIMER_BASEADDR - u64 tEnd; - u64 tCur; - u32 TimeHighVal; - XTime TimeLowVal1; - XTime TimeLowVal2; - - TimeHighVal = 0; - - XTime_GetTime(&TimeLowVal1); - tEnd = (u64)TimeLowVal1 + (((u64) useconds) * COUNTS_PER_USECOND); - - do - { - XTime_GetTime(&TimeLowVal2); - if (TimeLowVal2 < TimeLowVal1) { - TimeHighVal++; - } - TimeLowVal1 = TimeLowVal2; - tCur = (((u64) TimeHighVal) << 32U) | (u64)TimeLowVal2; - } while (tCur < tEnd); - - return 0; +#if defined (SLEEP_TIMER_BASEADDR) + Xil_SleepTTCCommon(useconds, COUNTS_PER_USECOND); #else +#if defined (__GNUC__) __asm__ __volatile__ ( - " push {r0,r1} \n\t" - " mov r0, %[usec] \n\t" - " 1: \n\t" - " mov r1, %[iter] \n\t" - " 2: \n\t" - " subs r1, r1, #0x1 \n\t" - " bne 2b \n\t" - " subs r0,r0,#0x1 \n\t" - " bne 1b \n\t" - " pop {r0,r1} \n\t" - :: [iter] "r" (ITERS_PER_USEC), [usec] "r" (useconds) - ); +#elif defined (__ICCARM__) + __asm volatile ( #endif + "push {r0,r1,r3} \n" + "mov r0, %[usec] \n" + "mov r1, %[iter] \n" + "1: \n" + "mov r3, r1 \n" + "2: \n" + "subs r3, r3, #0x1\n" + "bne 2b \n" + "subs r0, r0, #0x1 \n" + "bne 1b \n" + "pop {r0,r1,r3} \n" + ::[iter] "r" (ITERS_PER_USEC), [usec] "r" (useconds) + ); +#endif + +return 0; }
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/vectors.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/vectors.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/vectors.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/vectors.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/vectors.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/vectors.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/vectors.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/vectors.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/write.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/write.c similarity index 92% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/write.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/write.c index aaa879e..9389f61 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/write.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/write.c
@@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -82,6 +82,14 @@ __attribute__((weak)) sint32 _write (sint32 fd, char8* buf, sint32 nbytes) { +#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE + sint32 length; + + (void)fd; + (void)nbytes; + length = XPVXenConsole_Write(buf); + return length; +#else #ifdef STDOUT_BASEADDRESS s32 i; char8* LocalBuf = buf; @@ -108,5 +116,6 @@ (void)nbytes; return 0; #endif +#endif } #endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xbasic_types.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xbasic_types.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xbasic_types.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xbasic_types.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xdebug.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xdebug.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xdebug.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xdebug.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xenv.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xenv.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xenv.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xenv.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xenv_standalone.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xenv_standalone.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xenv_standalone.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xenv_standalone.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil-crt0.S b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil-crt0.S similarity index 86% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil-crt0.S rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil-crt0.S index 6715a6c..5c4fe74 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil-crt0.S +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil-crt0.S
@@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -42,6 +42,12 @@ * 5.04 pkp 12/18/15 Initialized global constructor for C++ applications * 5.04 pkp 02/19/16 Added timer configuration using XTime_StartTimer API when * TTC3 is present +* 6.4 asa 08/16/17 Added call to Xil_InitializeExistingMPURegConfig to +* initialize the MPU configuration table with the MPU +* configurations already set in Init_Mpu function. +* 6.6 srm 10/18/17 Updated the timer configuration with XTime_StartTTCTimer. +* Now the timer instance as specified by the user will be +* started. * </pre> * * @note @@ -123,11 +129,11 @@ /* set stack pointer */ ldr r13,.Lstack /* stack address */ - /* configure the timer if TTC3 is present */ + /* configure the timer if TTC is present */ #ifdef SLEEP_TIMER_BASEADDR - bl XTime_StartTimer + bl XTime_StartTTCTimer #endif - + bl Xil_InitializeExistingMPURegConfig /* Initialize MPU config */ /* run global constructors */ bl __libc_init_array
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_assert.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_assert.c similarity index 83% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_assert.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_assert.c index 3087fe8..59b3c1c 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_assert.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_assert.c
@@ -82,12 +82,13 @@ /*****************************************************************************/ /** * -* Implement assert. Currently, it calls a user-defined callback function -* if one has been set. Then, it potentially enters an infinite loop depending -* on the value of the Xil_AssertWait variable. +* @brief Implement assert. Currently, it calls a user-defined callback +* function if one has been set. Then, it potentially enters an +* infinite loop depending on the value of the Xil_AssertWait +* variable. * -* @param file is the name of the filename of the source -* @param line is the linenumber within File +* @param file: filename of the source +* @param line: linenumber within File * * @return None. * @@ -111,10 +112,10 @@ /*****************************************************************************/ /** * -* Set up a callback function to be invoked when an assert occurs. If there -* was already a callback installed, then it is replaced. +* @brief Set up a callback function to be invoked when an assert occurs. +* If a callback is already installed, then it will be replaced. * -* @param routine is the callback to be invoked when an assert is taken +* @param routine: callback to be invoked when an assert is taken * * @return None. * @@ -129,11 +130,11 @@ /*****************************************************************************/ /** * -* Null handler function. This follows the XInterruptHandler signature for -* interrupt handlers. It can be used to assign a null handler (a stub) to an -* interrupt controller vector table. +* @brief Null handler function. This follows the XInterruptHandler +* signature for interrupt handlers. It can be used to assign a null +* handler (a stub) to an interrupt controller vector table. * -* @param NullParameter is an arbitrary void pointer and not used. +* @param NullParameter: arbitrary void pointer and not used. * * @return None. * @@ -142,5 +143,5 @@ ******************************************************************************/ void XNullHandler(void *NullParameter) { - (void *) NullParameter; + (void) NullParameter; }
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_assert.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_assert.h similarity index 77% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_assert.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_assert.h index 1e3c17b..add4124 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_assert.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_assert.h
@@ -34,8 +34,15 @@ * * @file xil_assert.h * -* This file contains assert related functions. +* @addtogroup common_assert_apis Assert APIs and Macros * +* The xil_assert.h file contains assert related functions and macros. +* Assert APIs/Macros specifies that a application program satisfies certain +* conditions at particular points in its execution. These function can be +* used by application programs to ensure that, application code is satisfying +* certain conditions. +* +* @{ * <pre> * MODIFICATION HISTORY: * @@ -83,18 +90,17 @@ /*****************************************************************************/ /** -* This assert macro is to be used for functions that do not return anything -* (void). This in conjunction with the Xil_AssertWait boolean can be used to -* accomodate tests so that asserts which fail allow execution to continue. +* @brief This assert macro is to be used for void functions. This in +* conjunction with the Xil_AssertWait boolean can be used to +* accomodate tests so that asserts which fail allow execution to +* continue. * -* @param Expression is the expression to evaluate. If it evaluates to +* @param Expression: expression to be evaluated. If it evaluates to * false, the assert occurs. * * @return Returns void unless the Xil_AssertWait variable is true, in which * case no return is made and an infinite loop is entered. * -* @note None. -* ******************************************************************************/ #define Xil_AssertVoid(Expression) \ { \ @@ -109,17 +115,16 @@ /*****************************************************************************/ /** -* This assert macro is to be used for functions that do return a value. This in -* conjunction with the Xil_AssertWait boolean can be used to accomodate tests -* so that asserts which fail allow execution to continue. +* @brief This assert macro is to be used for functions that do return a +* value. This in conjunction with the Xil_AssertWait boolean can be +* used to accomodate tests so that asserts which fail allow execution +* to continue. * -* @param Expression is the expression to evaluate. If it evaluates to false, +* @param Expression: expression to be evaluated. If it evaluates to false, * the assert occurs. * * @return Returns 0 unless the Xil_AssertWait variable is true, in which -* case no return is made and an infinite loop is entered. -* -* @note None. +* case no return is made and an infinite loop is entered. * ******************************************************************************/ #define Xil_AssertNonvoid(Expression) \ @@ -135,14 +140,11 @@ /*****************************************************************************/ /** -* Always assert. This assert macro is to be used for functions that do not -* return anything (void). Use for instances where an assert should always -* occur. +* @brief Always assert. This assert macro is to be used for void functions. +* Use for instances where an assert should always occur. * -* @return Returns void unless the Xil_AssertWait variable is true, in which -* case no return is made and an infinite loop is entered. -* -* @note None. +* @return Returns void unless the Xil_AssertWait variable is true, in which +* case no return is made and an infinite loop is entered. * ******************************************************************************/ #define Xil_AssertVoidAlways() \ @@ -154,13 +156,12 @@ /*****************************************************************************/ /** -* Always assert. This assert macro is to be used for functions that do return -* a value. Use for instances where an assert should always occur. +* @brief Always assert. This assert macro is to be used for functions that +* do return a value. Use for instances where an assert should always +* occur. * * @return Returns void unless the Xil_AssertWait variable is true, in which -* case no return is made and an infinite loop is entered. -* -* @note None. +* case no return is made and an infinite loop is entered. * ******************************************************************************/ #define Xil_AssertNonvoidAlways() \ @@ -189,3 +190,6 @@ #endif #endif /* end of protection macro */ +/** +* @} End of "addtogroup common_assert_apis". +*/ \ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_cache.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_cache.c similarity index 74% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_cache.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_cache.c index 2ba080d..3cd51ab 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_cache.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_cache.c
@@ -42,6 +42,7 @@ * Ver Who Date Changes * ----- ---- -------- ----------------------------------------------- * 5.00 pkp 02/20/14 First release +* 6.2 mus 01/27/17 Updated to support IAR compiler * </pre> * ******************************************************************************/ @@ -60,16 +61,16 @@ #define IRQ_FIQ_MASK 0xC0 /* Mask IRQ and FIQ interrupts in cpsr */ - +#if defined (__GNUC__) extern s32 _stack_end; extern s32 __undef_stack; - +#endif /****************************************************************************/ /************************** Function Prototypes ******************************/ -/**************************************************************************** -* -* Enable the Data cache. +/****************************************************************************/ +/** +* @brief Enable the Data cache. * * @param None. * @@ -83,8 +84,11 @@ register u32 CtrlReg; /* enable caches only if they are disabled */ +#if defined (__GNUC__) CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); - +#elif defined (__ICCARM__) + mfcp(XREG_CP15_SYS_CONTROL,CtrlReg); +#endif if ((CtrlReg & XREG_CP15_CONTROL_C_BIT)==0x00000000U) { /* invalidate the Data cache */ Xil_DCacheInvalidate(); @@ -96,9 +100,9 @@ } } -/**************************************************************************** -* -* Disable the Data cache. +/****************************************************************************/ +/** +* @brief Disable the Data cache. * * @param None. * @@ -115,23 +119,25 @@ Xil_DCacheFlush(); /* disable the Data cache */ +#if defined (__GNUC__) CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_SYS_CONTROL,CtrlReg); +#endif CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT); mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); } -/**************************************************************************** -* -* Invalidate the entire Data cache. +/****************************************************************************/ +/** +* @brief Invalidate the entire Data cache. * * @param None. * * @return None. * -* @note None. -* ****************************************************************************/ void Xil_DCacheInvalidate(void) { @@ -141,14 +147,14 @@ currmask = mfcpsr(); mtcpsr(currmask | IRQ_FIQ_MASK); - +#if defined (__GNUC__) stack_end = (u32 )&_stack_end; stack_start = (u32 )&__undef_stack; stack_size = stack_start-stack_end; /* Flush stack memory to save return address */ Xil_DCacheFlushRange(stack_end, stack_size); - +#endif mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); /*invalidate all D cache*/ @@ -157,15 +163,16 @@ mtcpsr(currmask); } -/**************************************************************************** +/****************************************************************************/ +/** +* @brief Invalidate a Data cache line. If the byte specified by the +* address (adr) is cached by the data cache, the cacheline +* containing that byte is invalidated.If the cacheline is modified +* (dirty), the modified contents are lost and are NOT written +* to system memory before the line is invalidated. * -* Invalidate a Data cache line. If the byte specified by the address (adr) -* is cached by the Data cache, the cacheline containing that byte is -* invalidated. If the cacheline is modified (dirty), the modified contents -* are lost and are NOT written to system memory before the line is -* invalidated. * -* @param Address to be flushed. +* @param adr: 32bit address of the data to be flushed. * * @return None. * @@ -188,21 +195,20 @@ mtcpsr(currmask); } -/**************************************************************************** +/****************************************************************************/ +/** +* @brief Invalidate the Data cache for the given address range. +* If the bytes specified by the address (adr) are cached by the +* Data cache,the cacheline containing that byte is invalidated. +* If the cacheline is modified (dirty), the modified contents are +* lost and are NOT written to system memory before the line is +* invalidated. * -* Invalidate the Data cache for the given address range. -* If the bytes specified by the address (adr) are cached by the Data cache, -* the cacheline containing that byte is invalidated. If the cacheline -* is modified (dirty), the modified contents are lost and are NOT -* written to system memory before the line is invalidated. -* -* @param Start address of range to be invalidated. -* @param Length of range to be invalidated in bytes. +* @param adr: 32bit start address of the range to be invalidated. +* @param len: Length of range to be invalidated in bytes. * * @return None. * -* @note None. -* ****************************************************************************/ void Xil_DCacheInvalidateRange(INTPTR adr, u32 len) { @@ -245,16 +251,14 @@ mtcpsr(currmask); } -/**************************************************************************** -* -* Flush the entire Data cache. +/****************************************************************************/ +/** +* @brief Flush the entire Data cache. * * @param None. * * @return None. * -* @note None. -* ****************************************************************************/ void Xil_DCacheFlush(void) { @@ -269,8 +273,11 @@ /* Select cache level 0 and D cache in CSSR */ mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); +#if defined (__GNUC__) CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID); - +#elif defined (__ICCARM__) + mfcp(XREG_CP15_CACHE_SIZE_ID,CsidReg); +#endif /* Determine Cache Size */ CacheSize = (CsidReg >> 13U) & 0x000001FFU; @@ -310,15 +317,15 @@ mtcpsr(currmask); } -/**************************************************************************** +/****************************************************************************/ +/** +* @brief Flush a Data cache line. If the byte specified by the address (adr) +* is cached by the Data cache, the cacheline containing that byte is +* invalidated. If the cacheline is modified (dirty), the entire +* contents of the cacheline are written to system memory before the +* line is invalidated. * -* Flush a Data cache line. If the byte specified by the address (adr) -* is cached by the Data cache, the cacheline containing that byte is -* invalidated. If the cacheline is modified (dirty), the entire -* contents of the cacheline are written to system memory before the -* line is invalidated. -* -* @param Address to be flushed. +* @param adr: 32bit address of the data to be flushed. * * @return None. * @@ -341,20 +348,19 @@ mtcpsr(currmask); } -/**************************************************************************** -* Flush the Data cache for the given address range. -* If the bytes specified by the address (adr) are cached by the Data cache, -* the cacheline containing that byte is invalidated. If the cacheline -* is modified (dirty), the written to system memory first before the -* before the line is invalidated. +/****************************************************************************/ +/** +* @brief Flush the Data cache for the given address range. +* If the bytes specified by the address (adr) are cached by the +* Data cache, the cacheline containing those bytes is invalidated.If +* the cacheline is modified (dirty), the written to system memory +* before the lines are invalidated. * -* @param Start address of range to be flushed. -* @param Length of range to be flushed in bytes. +* @param adr: 32bit start address of the range to be flushed. +* @param len: Length of the range to be flushed in bytes * * @return None. * -* @note None. -* ****************************************************************************/ void Xil_DCacheFlushRange(INTPTR adr, u32 len) { @@ -383,15 +389,15 @@ dsb(); mtcpsr(currmask); } -/**************************************************************************** +/****************************************************************************/ +/** +* @brief Store a Data cache line. If the byte specified by the address +* (adr) is cached by the Data cache and the cacheline is modified +* (dirty), the entire contents of the cacheline are written to +* system memory.After the store completes, the cacheline is marked +* as unmodified (not dirty). * -* Store a Data cache line. If the byte specified by the address (adr) -* is cached by the Data cache and the cacheline is modified (dirty), -* the entire contents of the cacheline are written to system memory. -* After the store completes, the cacheline is marked as unmodified -* (not dirty). -* -* @param Address to be stored. +* @param adr: 32bit address of the data to be stored * * @return None. * @@ -415,25 +421,25 @@ mtcpsr(currmask); } -/**************************************************************************** -* -* Enable the instruction cache. +/****************************************************************************/ +/** +* @brief Enable the instruction cache. * * @param None. * * @return None. * -* @note None. -* ****************************************************************************/ void Xil_ICacheEnable(void) { register u32 CtrlReg; /* enable caches only if they are disabled */ - +#if defined (__GNUC__) CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); - +#elif defined (__ICCARM__) + mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); +#endif if ((CtrlReg & XREG_CP15_CONTROL_I_BIT)==0x00000000U) { /* invalidate the instruction cache */ mtcp(XREG_CP15_INVAL_IC_POU, 0); @@ -445,16 +451,14 @@ } } -/**************************************************************************** -* -* Disable the instruction cache. +/****************************************************************************/ +/** +* @brief Disable the instruction cache. * * @param None. * * @return None. * -* @note None. -* ****************************************************************************/ void Xil_ICacheDisable(void) { @@ -466,24 +470,25 @@ mtcp(XREG_CP15_INVAL_IC_POU, 0); /* disable the instruction cache */ - +#if defined (__GNUC__) CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_SYS_CONTROL,CtrlReg); +#endif CtrlReg &= ~(XREG_CP15_CONTROL_I_BIT); mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); } -/**************************************************************************** -* -* Invalidate the entire instruction cache. +/****************************************************************************/ +/** +* @brief Invalidate the entire instruction cache. * * @param None. * * @return None. * -* @note None. -* ****************************************************************************/ void Xil_ICacheInvalidate(void) { @@ -502,13 +507,13 @@ mtcpsr(currmask); } -/**************************************************************************** +/****************************************************************************/ +/** +* @brief Invalidate an instruction cache line.If the instruction specified +* by the address is cached by the instruction cache, the +* cacheline containing that instruction is invalidated. * -* Invalidate an instruction cache line. If the instruction specified by the -* parameter adr is cached by the instruction cache, the cacheline containing -* that instruction is invalidated. -* -* @param None. +* @param adr: 32bit address of the instruction to be invalidated. * * @return None. * @@ -530,21 +535,20 @@ mtcpsr(currmask); } -/**************************************************************************** +/****************************************************************************/ +/** +* @brief Invalidate the instruction cache for the given address range. +* If the bytes specified by the address (adr) are cached by the +* Data cache, the cacheline containing that byte is invalidated. +* If the cachelineis modified (dirty), the modified contents are +* lost and are NOT written to system memory before the line is +* invalidated. * -* Invalidate the instruction cache for the given address range. -* If the bytes specified by the address (adr) are cached by the Data cache, -* the cacheline containing that byte is invalidated. If the cacheline -* is modified (dirty), the modified contents are lost and are NOT -* written to system memory before the line is invalidated. -* -* @param Start address of range to be invalidated. -* @param Length of range to be invalidated in bytes. +* @param adr: 32bit start address of the range to be invalidated. +* @param len: Length of the range to be invalidated in bytes. * * @return None. * -* @note None. -* ****************************************************************************/ void Xil_ICacheInvalidateRange(INTPTR adr, u32 len) {
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_cache.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_cache.h similarity index 77% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_cache.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_cache.h index 581db3f..ad1d10a 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_cache.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_cache.h
@@ -34,14 +34,21 @@ * * @file xil_cache.h * -* Contains required functions for the ARM cache functionality +* @addtogroup r5_cache_apis Cortex R5 Processor Cache Functions * +* Cache functions provide access to cache related operations such as flush +* and invalidate for instruction and data caches. It gives option to perform +* the cache operations on a single cacheline, a range of memory and an entire +* cache. +* +* @{ * <pre> * MODIFICATION HISTORY: * * Ver Who Date Changes * ----- ---- -------- ----------------------------------------------- * 5.00 pkp 02/20/14 First release +* 6.2 mus 01/27/17 Updated to support IAR compiler * </pre> * ******************************************************************************/ @@ -54,6 +61,7 @@ extern "C" { #endif +#if defined (__GNUC__) #define asm_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \ XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param)) @@ -65,6 +73,19 @@ #define asm_inval_ic_line_mva_pou(param) __asm__ __volatile__("mcr " \ XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param)) +#elif defined (__ICCARM__) +#define asm_inval_dc_line_mva_poc(param) __asm volatile("mcr " \ + XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param)) + +#define asm_clean_inval_dc_line_sw(param) __asm volatile("mcr " \ + XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param)) + +#define asm_clean_inval_dc_line_mva_poc(param) __asm volatile("mcr " \ + XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param)) + +#define asm_inval_ic_line_mva_pou(param) __asm volatile("mcr " \ + XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param)) +#endif void Xil_DCacheEnable(void); void Xil_DCacheDisable(void); @@ -87,3 +108,6 @@ #endif #endif +/** +* @} End of "addtogroup r5_cache_apis". +*/ \ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_cache_vxworks.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_cache_vxworks.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_cache_vxworks.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_cache_vxworks.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_exception.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_exception.c similarity index 85% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_exception.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_exception.c index 66f722d..4a2f2cf 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_exception.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_exception.c
@@ -46,6 +46,8 @@ * 6.0 mus 27/07/16 Consolidated exceptions for a53,a9 and r5 * processors and added Xil_UndefinedExceptionHandler * for a53 32 bit and r5 as well. +* 6.4 mus 08/06/17 Updated debug prints to replace %x with the %lx, to +* fix the warnings. * </pre> * *****************************************************************************/ @@ -122,19 +124,19 @@ *****************************************************************************/ static void Xil_ExceptionNullHandler(void *Data) { - (void *)Data; + (void) Data; DieLoop: goto DieLoop; } /****************************************************************************/ /** -* The function is a common API used to initialize exception handlers across all -* processors supported. For ARM CortexA53,R5,A9, the exception handlers are being -* initialized statically and hence this function does not do anything. -* However, it is still present to avoid any compilation issues in case an -* application uses this API and also to take care of backward compatibility -* issues (in earlier versions of BSPs, this API was being used to initialize -* exception handlers). +* @brief The function is a common API used to initialize exception handlers +* across all supported arm processors. For ARM Cortex-A53, Cortex-R5, +* and Cortex-A9, the exception handlers are being initialized +* statically and this function does not do anything. +* However, it is still present to take care of backward compatibility +* issues (in earlier versions of BSPs, this API was being used to +* initialize exception handlers). * * @param None. * @@ -150,18 +152,15 @@ /*****************************************************************************/ /** -* -* Makes the connection between the Id of the exception source and the -* associated Handler that is to run when the exception is recognized. The -* argument provided in this call as the Data is used as the argument -* for the Handler when it is called. +* @brief Register a handler for a specific exception. This handler is being +* called when the processor encounters the specified exception. * * @param exception_id contains the ID of the exception source and should -* be in the range of 0 to XIL_EXCEPTION_ID_LAST. - See xil_exception_l.h for further information. +* be in the range of 0 to XIL_EXCEPTION_ID_LAST. +* See xil_exception.h for further information. * @param Handler to the Handler for that exception. * @param Data is a reference to Data that will be passed to the -* Handler when it gets called. +* Handler when it gets called. * * @return None. * @@ -179,13 +178,13 @@ /*****************************************************************************/ /** * -* Removes the Handler for a specific exception Id. The stub Handler is then -* registered for this exception Id. +* @brief Removes the Handler for a specific exception Id. The stub Handler +* is then registered for this exception Id. * * @param exception_id contains the ID of the exception source and should -* be in the range of 0 to XIL_EXCEPTION_ID_LAST. -* See xil_exception_l.h for further information. - +* be in the range of 0 to XIL_EXCEPTION_ID_LAST. +* See xil_exception.h for further information. +* * @return None. * * @note None. @@ -214,6 +213,7 @@ ****************************************************************************/ void Xil_SyncAbortHandler(void *CallBackRef){ + (void) CallBackRef; xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n"); while(1) { ; @@ -234,6 +234,7 @@ * ****************************************************************************/ void Xil_SErrorAbortHandler(void *CallBackRef){ + (void) CallBackRef; xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n"); while(1) { ; @@ -241,7 +242,7 @@ } #else /*****************************************************************************/ -/** +/* * * Default Data abort handler which prints data fault status register through * which information about data fault can be acquired @@ -255,6 +256,7 @@ ****************************************************************************/ void Xil_DataAbortHandler(void *CallBackRef){ + (void) CallBackRef; #ifdef DEBUG u32 FaultStatus; @@ -267,8 +269,8 @@ { volatile register u32 Reg __asm(XREG_CP15_DATA_FAULT_STATUS); FaultStatus = Reg; } #endif - xdbg_printf(XDBG_DEBUG_GENERAL, "Data abort with Data Fault Status Register %x\n",FaultStatus); - xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instrcution causing Data abort %x\n",DataAbortAddr); + xdbg_printf(XDBG_DEBUG_GENERAL, "Data abort with Data Fault Status Register %lx\n",FaultStatus); + xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instruction causing Data abort %lx\n",DataAbortAddr); #endif while(1) { ; @@ -276,7 +278,7 @@ } /*****************************************************************************/ -/** +/* * * Default Prefetch abort handler which prints prefetch fault status register through * which information about instruction prefetch fault can be acquired @@ -289,6 +291,7 @@ * ****************************************************************************/ void Xil_PrefetchAbortHandler(void *CallBackRef){ + (void) CallBackRef; #ifdef DEBUG u32 FaultStatus; @@ -301,15 +304,15 @@ { volatile register u32 Reg __asm(XREG_CP15_INST_FAULT_STATUS); FaultStatus = Reg; } #endif - xdbg_printf(XDBG_DEBUG_GENERAL, "Prefetch abort with Instruction Fault Status Register %x\n",FaultStatus); - xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instrcution causing Prefetch abort %x\n",PrefetchAbortAddr); + xdbg_printf(XDBG_DEBUG_GENERAL, "Prefetch abort with Instruction Fault Status Register %lx\n",FaultStatus); + xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instruction causing Prefetch abort %lx\n",PrefetchAbortAddr); #endif while(1) { ; } } /*****************************************************************************/ -/** +/* * * Default undefined exception handler which prints address of the undefined * instruction if debug prints are enabled @@ -322,8 +325,8 @@ * ****************************************************************************/ void Xil_UndefinedExceptionHandler(void *CallBackRef){ - - xdbg_printf(XDBG_DEBUG_GENERAL, "Address of the undefined instruction %x\n",UndefinedExceptionAddr); + (void) CallBackRef; + xdbg_printf(XDBG_DEBUG_GENERAL, "Address of the undefined instruction %lx\n",UndefinedExceptionAddr); while(1) { ; }
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_exception.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_exception.h similarity index 90% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_exception.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_exception.h index 434ef2a..ad48222 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_exception.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_exception.h
@@ -38,6 +38,12 @@ * For exception related functions that can be used across all Xilinx supported * processors, please use xil_exception.h. * +* @addtogroup arm_exception_apis ARM Processor Exception Handling +* @{ +* ARM processors specific exception related APIs for cortex A53,A9 and R5 can +* utilized for enabling/disabling IRQ, registering/removing handler for +* exceptions or initializing exception vector table with null handler. +* * <pre> * MODIFICATION HISTORY: * @@ -102,14 +108,14 @@ /****************************************************************************/ /** -* Enable Exceptions. +* @brief Enable Exceptions. * -* @param Mask for exceptions to be enabled. +* @param Mask: Value for enabling the exceptions. * * @return None. * * @note If bit is 0, exception is enabled. -* C-Style signature: void Xil_ExceptionEnableMask(Mask) +* C-Style signature: void Xil_ExceptionEnableMask(Mask) * ******************************************************************************/ #if defined (__GNUC__) || defined (__ICCARM__) @@ -124,7 +130,7 @@ #endif /****************************************************************************/ /** -* Enable the IRQ exception. +* @brief Enable the IRQ exception. * * @return None. * @@ -136,14 +142,14 @@ /****************************************************************************/ /** -* Disable Exceptions. +* @brief Disable Exceptions. * -* @param Mask for exceptions to be enabled. +* @param Mask: Value for disabling the exceptions. * * @return None. * * @note If bit is 1, exception is disabled. -* C-Style signature: Xil_ExceptionDisableMask(Mask) +* C-Style signature: Xil_ExceptionDisableMask(Mask) * ******************************************************************************/ #if defined (__GNUC__) || defined (__ICCARM__) @@ -171,7 +177,8 @@ #if !defined (__aarch64__) && !defined (ARMA53_32) /****************************************************************************/ /** -* Enable nested interrupts by clearing the I and F bits it CPSR +* @brief Enable nested interrupts by clearing the I and F bits in CPSR. This +* API is defined for cortex-a9 and cortex-r5. * * @return None. * @@ -197,7 +204,8 @@ /****************************************************************************/ /** -* Disable the nested interrupts by setting the I and F bits. +* @brief Disable the nested interrupts by setting the I and F bits. This API +* is defined for cortex-a9 and cortex-r5. * * @return None. * @@ -243,3 +251,6 @@ #endif /* __cplusplus */ #endif /* XIL_EXCEPTION_H */ +/** +* @} End of "addtogroup arm_exception_apis". +*/ \ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_hal.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_hal.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_hal.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_hal.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_io.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_io.c similarity index 89% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_io.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_io.c index 31de055..90bfc81 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_io.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_io.c
@@ -35,8 +35,7 @@ * @file xil_io.c * * Contains I/O functions for memory-mapped or non-memory-mapped I/O -* architectures. These functions encapsulate Cortex A53 architecture-specific -* I/O requirements. +* architectures. * * @note * @@ -60,13 +59,11 @@ /*****************************************************************************/ /** * -* Perform a 16-bit endian converion. +* @brief Perform a 16-bit endian converion. * -* @param Data contains the value to be converted. +* @param Data: 16 bit value to be converted * -* @return converted value. -* -* @note None. +* @return 16 bit Data with converted endianess * ******************************************************************************/ u16 Xil_EndianSwap16(u16 Data) @@ -77,13 +74,11 @@ /*****************************************************************************/ /** * -* Perform a 32-bit endian converion. +* @brief Perform a 32-bit endian converion. * -* @param Data contains the value to be converted. +* @param Data: 32 bit value to be converted * -* @return converted value. -* -* @note None. +* @return 32 bit data with converted endianess * ******************************************************************************/ u32 Xil_EndianSwap32(u32 Data)
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_io.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_io.h similarity index 74% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_io.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_io.h index 06d89dc..9c5aa43 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_io.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_io.h
@@ -34,11 +34,13 @@ * * @file xil_io.h * -* This file contains the interface for the general IO component, which -* encapsulates the Input/Output functions for processors that do not +* @addtogroup common_io_interfacing_apis Register IO interfacing APIs +* +* The xil_io.h file contains the interface for the general I/O component, which +* encapsulates the Input/Output functions for the processors that do not * require any special I/O handling. * -* +* @{ * <pre> * MODIFICATION HISTORY: * @@ -71,6 +73,9 @@ /************************** Function Prototypes ******************************/ u16 Xil_EndianSwap16(u16 Data); u32 Xil_EndianSwap32(u32 Data); +#ifdef ENABLE_SAFETY +extern u32 XStl_RegUpdate(u32 RegAddr, u32 RegVal); +#endif /***************** Macros (Inline Functions) Definitions *********************/ #if defined __GNUC__ @@ -99,15 +104,14 @@ /*****************************************************************************/ /** * -* Performs an input operation for an 8-bit memory location by reading from the -* specified address and returning the Value read from that address. +* @brief Performs an input operation for a memory location by reading +* from the specified address and returning the 8 bit Value read from +* that address. * -* @param Addr contains the address to perform the input operation -* at. +* @param Addr: contains the address to perform the input operation * -* @return The Value read from the specified input address. -* -* @note None. +* @return The 8 bit Value read from the specified input address. + * ******************************************************************************/ static INLINE u8 Xil_In8(UINTPTR Addr) @@ -118,15 +122,13 @@ /*****************************************************************************/ /** * -* Performs an input operation for a 16-bit memory location by reading from the -* specified address and returning the Value read from that address. +* @brief Performs an input operation for a memory location by reading from +* the specified address and returning the 16 bit Value read from that +* address. * -* @param Addr contains the address to perform the input operation -* at. +* @param Addr: contains the address to perform the input operation * -* @return The Value read from the specified input address. -* -* @note None. +* @return The 16 bit Value read from the specified input address. * ******************************************************************************/ static INLINE u16 Xil_In16(UINTPTR Addr) @@ -137,15 +139,13 @@ /*****************************************************************************/ /** * -* Performs an input operation for a 32-bit memory location by reading from the -* specified address and returning the Value read from that address. +* @brief Performs an input operation for a memory location by +* reading from the specified address and returning the 32 bit Value +* read from that address. * -* @param Addr contains the address to perform the input operation -* at. +* @param Addr: contains the address to perform the input operation * -* @return The Value read from the specified input address. -* -* @note None. +* @return The 32 bit Value read from the specified input address. * ******************************************************************************/ static INLINE u32 Xil_In32(UINTPTR Addr) @@ -156,16 +156,13 @@ /*****************************************************************************/ /** * -* Performs an input operation for a 64-bit memory location by reading the -* specified Value to the the specified address. +* @brief Performs an input operation for a memory location by reading the +* 64 bit Value read from that address. * -* @param OutAddress contains the address to perform the output operation -* at. -* @param Value contains the Value to be output at the specified address. * -* @return None. +* @param Addr: contains the address to perform the input operation * -* @note None. +* @return The 64 bit Value read from the specified input address. * ******************************************************************************/ static INLINE u64 Xil_In64(UINTPTR Addr) @@ -176,17 +173,15 @@ /*****************************************************************************/ /** * -* Performs an output operation for an 8-bit memory location by writing the -* specified Value to the the specified address. +* @brief Performs an output operation for an memory location by +* writing the 8 bit Value to the the specified address. * -* @param Addr contains the address to perform the output operation -* at. -* @param Value contains the Value to be output at the specified address. +* @param Addr: contains the address to perform the output operation +* @param Value: contains the 8 bit Value to be written at the specified +* address. * * @return None. * -* @note None. -* ******************************************************************************/ static INLINE void Xil_Out8(UINTPTR Addr, u8 Value) { @@ -197,17 +192,14 @@ /*****************************************************************************/ /** * -* Performs an output operation for a 16-bit memory location by writing the -* specified Value to the the specified address. +* @brief Performs an output operation for a memory location by writing the +* 16 bit Value to the the specified address. * * @param Addr contains the address to perform the output operation -* at. -* @param Value contains the Value to be output at the specified address. +* @param Value contains the Value to be written at the specified address. * * @return None. * -* @note None. -* ******************************************************************************/ static INLINE void Xil_Out16(UINTPTR Addr, u16 Value) { @@ -218,38 +210,37 @@ /*****************************************************************************/ /** * -* Performs an output operation for a 32-bit memory location by writing the -* specified Value to the the specified address. +* @brief Performs an output operation for a memory location by writing the +* 32 bit Value to the the specified address. * * @param Addr contains the address to perform the output operation -* at. -* @param Value contains the Value to be output at the specified address. +* @param Value contains the 32 bit Value to be written at the specified +* address. * * @return None. * -* @note None. -* ******************************************************************************/ static INLINE void Xil_Out32(UINTPTR Addr, u32 Value) { +#ifndef ENABLE_SAFETY volatile u32 *LocalAddr = (volatile u32 *)Addr; *LocalAddr = Value; +#else + XStl_RegUpdate(Addr, Value); +#endif } /*****************************************************************************/ /** * -* Performs an output operation for a 64-bit memory location by writing the -* specified Value to the the specified address. +* @brief Performs an output operation for a memory location by writing the +* 64 bit Value to the the specified address. * * @param Addr contains the address to perform the output operation -* at. -* @param Value contains the Value to be output at the specified address. +* @param Value contains 64 bit Value to be written at the specified address. * * @return None. * -* @note None. -* ******************************************************************************/ static INLINE void Xil_Out64(UINTPTR Addr, u64 Value) { @@ -312,7 +303,7 @@ static INLINE u32 Xil_In32BE(UINTPTR Addr) #endif { - u16 value = Xil_In32(Addr); + u32 value = Xil_In32(Addr); return Xil_EndianSwap32(value); } @@ -349,3 +340,6 @@ #endif #endif /* end of protection macro */ +/** +* @} End of "addtogroup common_io_interfacing_apis". +*/
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_macroback.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_macroback.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_macroback.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_macroback.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_mpu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_mem.c similarity index 61% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_mpu.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_mem.c index a55be91..0929a68 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_mpu.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_mem.c
@@ -1,6 +1,6 @@ -/****************************************************************************** -* -* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved. +/******************************************************************************/ +/** +* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -29,52 +29,55 @@ * this Software without prior written authorization from Xilinx. * ******************************************************************************/ -/*****************************************************************************/ +/****************************************************************************/ /** -* @file xil_mmu.h +* @file xil_mem.c * -* +* This file contains xil mem copy function to use in case of word aligned +* data copies. * * <pre> * MODIFICATION HISTORY: * -* Ver Who Date Changes -* ----- ---- -------- --------------------------------------------------- -* 5.00 pkp 02/10/14 Initial version +* Ver Who Date Changes +* ----- -------- -------- ----------------------------------------------- +* 6.1 nsk 11/07/16 First release. +* * </pre> * -* @note -* -* None. -* -******************************************************************************/ +*****************************************************************************/ -#ifndef XIL_MPU_H -#define XIL_MPU_H +/***************************** Include Files ********************************/ -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ #include "xil_types.h" -/***************************** Include Files *********************************/ -/***************** Macros (Inline Functions) Definitions *********************/ +/***************** Inline Functions Definitions ********************/ +/*****************************************************************************/ +/** +* @brief This function copies memory from once location to other. +* +* @param dst: pointer pointing to destination memory +* +* @param src: pointer pointing to source memory +* +* @param cnt: 32 bit length of bytes to be copied +* +*****************************************************************************/ +void Xil_MemCpy(void* dst, const void* src, u32 cnt) +{ + char *d = (char*)(void *)dst; + const char *s = src; -/**************************** Type Definitions *******************************/ - -/************************** Constant Definitions *****************************/ - -/************************** Variable Definitions *****************************/ - -/************************** Function Prototypes ******************************/ - -void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib); -void Xil_EnableMPU(void); -void Xil_DisableMPU(void); -void Xil_SetMPURegion(INTPTR addr, u64 size, u32 attrib); - -#ifdef __cplusplus + while (cnt >= sizeof (int)) { + *(int*)d = *(int*)s; + d += sizeof (int); + s += sizeof (int); + cnt -= sizeof (int); + } + while ((cnt) > 0U){ + *d = *s; + d += 1U; + s += 1U; + cnt -= 1U; + } } -#endif /* __cplusplus */ - -#endif /* XIL_MPU_H */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpseudo_asm.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_mem.h similarity index 70% copy from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpseudo_asm.h copy to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_mem.h index aff19d5..a2d5e66 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpseudo_asm.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_mem.h
@@ -1,6 +1,6 @@ -/****************************************************************************** -* -* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved. +/******************************************************************************/ +/** +* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -29,26 +29,31 @@ * this Software without prior written authorization from Xilinx. * ******************************************************************************/ -/*****************************************************************************/ +/****************************************************************************/ /** +* @file xil_mem.h * -* @file xpseudo_asm.h +* @addtogroup common_mem_operation_api Customized APIs for Memory Operations * -* This header file contains macros for using inline assembler code. +* The xil_mem.h file contains prototype for functions related +* to memory operations. These APIs are applicable for all processors supported +* by Xilinx. * +* @{ * <pre> * MODIFICATION HISTORY: * -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 5.00 pkp 02/10/14 Initial version +* Ver Who Date Changes +* ----- -------- -------- ----------------------------------------------- +* 6.1 nsk 11/07/16 First release. +* * </pre> * -******************************************************************************/ -#ifndef XPSEUDO_ASM_H /* prevent circular inclusions */ -#define XPSEUDO_ASM_H /* by using protection macros */ +*****************************************************************************/ -#include "xreg_cortexr5.h" -#include "xpseudo_asm_gcc.h" +/************************** Function Prototypes *****************************/ -#endif /* XPSEUDO_ASM_H */ +void Xil_MemCpy(void* dst, const void* src, u32 cnt); +/** +* @} End of "addtogroup common_mem_operation_api". +*/ \ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_mmu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_mmu.h similarity index 96% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_mmu.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_mmu.h index 8e43e82..28a7c78 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_mmu.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_mmu.h
@@ -18,8 +18,8 @@ * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE.
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_mpu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_mpu.c new file mode 100644 index 0000000..7dd048f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_mpu.c
@@ -0,0 +1,579 @@ +/****************************************************************************** +* +* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xil_mpu.c +* +* This file provides APIs for enabling/disabling MPU and setting the memory +* attributes for sections, in the MPU translation table. +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- --------------------------------------------------- +* 5.00 pkp 02/10/14 Initial version +* 6.2 mus 01/27/17 Updated to support IAR compiler +* 6.4 asa 08/16/17 Added many APIs for MPU access to make MPU usage +* user-friendly. The APIs added are: Xil_UpdateMPUConfig, +* Xil_GetMPUConfig, Xil_GetNumOfFreeRegions, +* Xil_GetNextMPURegion, Xil_DisableMPURegionByRegNum, +* Xil_GetMPUFreeRegMask, Xil_SetMPURegionByRegNum, and +* Xil_InitializeExistingMPURegConfig. +* Added a new array of structure of type XMpuConfig to +* represent the MPU configuration table. +* </pre> +* +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xil_cache.h" +#include "xpseudo_asm.h" +#include "xil_types.h" +#include "xil_mpu.h" +#include "xdebug.h" +#include "xstatus.h" +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +/************************** Variable Definitions *****************************/ + +static const struct { + u64 size; + unsigned int encoding; +}region_size[] = { + { 0x20, REGION_32B }, + { 0x40, REGION_64B }, + { 0x80, REGION_128B }, + { 0x100, REGION_256B }, + { 0x200, REGION_512B }, + { 0x400, REGION_1K }, + { 0x800, REGION_2K }, + { 0x1000, REGION_4K }, + { 0x2000, REGION_8K }, + { 0x4000, REGION_16K }, + { 0x8000, REGION_32K }, + { 0x10000, REGION_64K }, + { 0x20000, REGION_128K }, + { 0x40000, REGION_256K }, + { 0x80000, REGION_512K }, + { 0x100000, REGION_1M }, + { 0x200000, REGION_2M }, + { 0x400000, REGION_4M }, + { 0x800000, REGION_8M }, + { 0x1000000, REGION_16M }, + { 0x2000000, REGION_32M }, + { 0x4000000, REGION_64M }, + { 0x8000000, REGION_128M }, + { 0x10000000, REGION_256M }, + { 0x20000000, REGION_512M }, + { 0x40000000, REGION_1G }, + { 0x80000000, REGION_2G }, + { 0x100000000, REGION_4G }, +}; + +XMpu_Config Mpu_Config; + +/************************** Function Prototypes ******************************/ +void Xil_InitializeExistingMPURegConfig(void); +/*****************************************************************************/ +/** +* @brief This function sets the memory attributes for a section covering +* 1MB, of memory in the translation table. +* +* @param Addr: 32-bit address for which memory attributes need to be set. +* @param attrib: Attribute for the given memory region. +* @return None. +* +* +******************************************************************************/ +void Xil_SetTlbAttributes(INTPTR addr, u32 attrib) +{ + INTPTR Localaddr = addr; + Localaddr &= (~(0xFFFFFU)); + /* Setting the MPU region with given attribute with 1MB size */ + Xil_SetMPURegion(Localaddr, 0x100000, attrib); +} + +/*****************************************************************************/ +/** +* @brief Set the memory attributes for a section of memory in the +* translation table. +* +* @param Addr: 32-bit address for which memory attributes need to be set.. +* @param size: size is the size of the region. +* @param attrib: Attribute for the given memory region. +* @return None. +* +* +******************************************************************************/ +u32 Xil_SetMPURegion(INTPTR addr, u64 size, u32 attrib) +{ + u32 Regionsize = 0; + INTPTR Localaddr = addr; + u32 NextAvailableMemRegion; + unsigned int i; + + NextAvailableMemRegion = Xil_GetNextMPURegion(); + if (NextAvailableMemRegion == 0xFF) { + xdbg_printf(DEBUG, "No regions available\r\n"); + return XST_FAILURE; + } + + Xil_DCacheFlush(); + Xil_ICacheInvalidate(); + + mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,NextAvailableMemRegion); + isb(); + + /* Lookup the size. */ + for (i = 0; i < sizeof region_size / sizeof region_size[0]; i++) { + if (size <= region_size[i].size) { + Regionsize = region_size[i].encoding; + break; + } + } + + Localaddr &= ~(region_size[i].size - 1); + + Regionsize <<= 1; + Regionsize |= REGION_EN; + dsb(); + mtcp(XREG_CP15_MPU_REG_BASEADDR, Localaddr); /* Set base address of a region */ + mtcp(XREG_CP15_MPU_REG_ACCESS_CTRL, attrib); /* Set the control attribute */ + mtcp(XREG_CP15_MPU_REG_SIZE_EN, Regionsize); /* set the region size and enable it*/ + dsb(); + isb(); + Xil_UpdateMPUConfig(NextAvailableMemRegion, Localaddr, Regionsize, attrib); + return XST_SUCCESS; +} +/*****************************************************************************/ +/** +* @brief Enable MPU for Cortex R5 processor. This function invalidates I +* cache and flush the D Caches, and then enables the MPU. +* +* +* @param None. +* @return None. +* +******************************************************************************/ +void Xil_EnableMPU(void) +{ + u32 CtrlReg, Reg; + s32 DCacheStatus=0, ICacheStatus=0; + /* enable caches only if they are disabled */ +#if defined (__GNUC__) + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_SYS_CONTROL,CtrlReg); +#endif + if ((CtrlReg & XREG_CP15_CONTROL_C_BIT) != 0x00000000U) { + DCacheStatus=1; + } + if ((CtrlReg & XREG_CP15_CONTROL_I_BIT) != 0x00000000U) { + ICacheStatus=1; + } + + if(DCacheStatus != 0) { + Xil_DCacheDisable(); + } + if(ICacheStatus != 0){ + Xil_ICacheDisable(); + } +#if defined (__GNUC__) + Reg = mfcp(XREG_CP15_SYS_CONTROL); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_SYS_CONTROL,Reg); +#endif + Reg |= 0x00000001U; + dsb(); + mtcp(XREG_CP15_SYS_CONTROL, Reg); + isb(); + /* enable caches only if they are disabled in routine*/ + if(DCacheStatus != 0) { + Xil_DCacheEnable(); + } + if(ICacheStatus != 0) { + Xil_ICacheEnable(); + } +} + +/*****************************************************************************/ +/** +* @brief Disable MPU for Cortex R5 processors. This function invalidates I +* cache and flush the D Caches, and then disabes the MPU. +* +* @param None. +* +* @return None. +* +******************************************************************************/ +void Xil_DisableMPU(void) +{ + u32 CtrlReg, Reg; + s32 DCacheStatus=0, ICacheStatus=0; + /* enable caches only if they are disabled */ + +#if defined (__GNUC__) + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_SYS_CONTROL,CtrlReg); +#endif + if ((CtrlReg & XREG_CP15_CONTROL_C_BIT) != 0x00000000U) { + DCacheStatus=1; + } + if ((CtrlReg & XREG_CP15_CONTROL_I_BIT) != 0x00000000U) { + ICacheStatus=1; + } + + if(DCacheStatus != 0) { + Xil_DCacheDisable(); + } + if(ICacheStatus != 0){ + Xil_ICacheDisable(); + } + + mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0); +#if defined (__GNUC__) + Reg = mfcp(XREG_CP15_SYS_CONTROL); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_SYS_CONTROL,Reg); +#endif + Reg &= ~(0x00000001U); + dsb(); + mtcp(XREG_CP15_SYS_CONTROL, Reg); + isb(); + /* enable caches only if they are disabled in routine*/ + if(DCacheStatus != 0) { + Xil_DCacheEnable(); + } + if(ICacheStatus != 0) { + Xil_ICacheEnable(); + } +} + +/*****************************************************************************/ +/** +* @brief Update the MPU configuration for the requested region number in +* the global MPU configuration table. +* +* @param reg_num: The requested region number to be updated information for. +* @param address: 32 bit address for start of the region. +* @param size: Requested size of the region. +* @param attrib: Attribute for the corresponding region. +* @return XST_FAILURE: When the requested region number if 16 or more. +* XST_SUCCESS: When the MPU configuration table is updated. +* +* +******************************************************************************/ +u32 Xil_UpdateMPUConfig(u32 reg_num, INTPTR address, u32 size, u32 attrib) +{ + u32 ReturnVal = XST_SUCCESS; + u32 Tempsize = size; + u32 Index; + + if (reg_num >= MAX_POSSIBLE_MPU_REGS) { + xdbg_printf(DEBUG, "Invalid region number\r\n"); + ReturnVal = XST_FAILURE; + goto exit; + } + + if (size & REGION_EN) { + Mpu_Config[reg_num].RegionStatus = MPU_REG_ENABLED; + Mpu_Config[reg_num].BaseAddress = address; + Tempsize &= (~REGION_EN); + Tempsize >>= 1; + /* Lookup the size. */ + for (Index = 0; Index < + sizeof region_size / sizeof region_size[0]; Index++) { + if (Tempsize <= region_size[Index].encoding) { + Mpu_Config[reg_num].Size = region_size[Index].size; + break; + } + } + Mpu_Config[reg_num].Attribute = attrib; + } else { + Mpu_Config[reg_num].RegionStatus = 0U; + Mpu_Config[reg_num].BaseAddress = 0U; + Mpu_Config[reg_num].Size = 0U; + Mpu_Config[reg_num].Attribute = 0U; + } + +exit: + return ReturnVal; +} + +/*****************************************************************************/ +/** +* @brief The MPU configuration table is passed to the caller. +* +* @param mpuconfig: This is of type XMpu_Config which is an array of +* 16 entries of type structure representing the MPU config table +* @return none +* +* +******************************************************************************/ +void Xil_GetMPUConfig (XMpu_Config mpuconfig) { + u32 Index = 0U; + + while (Index < MAX_POSSIBLE_MPU_REGS) { + mpuconfig[Index].RegionStatus = Mpu_Config[Index].RegionStatus; + mpuconfig[Index].BaseAddress = Mpu_Config[Index].BaseAddress; + mpuconfig[Index].Attribute = Mpu_Config[Index].Attribute; + mpuconfig[Index].Size = Mpu_Config[Index].Size; + Index++; + } +} + +/*****************************************************************************/ +/** +* @brief Returns the total number of free MPU regions available. +* +* @param none +* @return Number of free regions available to users +* +* +******************************************************************************/ +u32 Xil_GetNumOfFreeRegions (void) { + u32 Index = 0U; + int NumofFreeRegs = 0U; + + while (Index < MAX_POSSIBLE_MPU_REGS) { + if (MPU_REG_DISABLED == Mpu_Config[Index].RegionStatus) { + NumofFreeRegs++; + } + Index++; + } + return NumofFreeRegs; +} + +/*****************************************************************************/ +/** +* @brief Returns the total number of free MPU regions available in the form +* of a mask. A bit of 1 in the returned 16 bit value represents the +* corresponding region number to be available. +* For example, if this function returns 0xC0000, this would mean, the +* regions 14 and 15 are available to users. +* +* @param none +* @return The free region mask as a 16 bit value +* +* +******************************************************************************/ +u16 Xil_GetMPUFreeRegMask (void) { + u32 Index = 0U; + u16 FreeRegMask = 0U; + + while (Index < MAX_POSSIBLE_MPU_REGS) { + if (MPU_REG_DISABLED == Mpu_Config[Index].RegionStatus) { + FreeRegMask |= (1U << Index); + } + Index++; + } + return FreeRegMask; +} + +/*****************************************************************************/ +/** +* @brief Disables the corresponding region number as passed by the user. +* +* @param reg_num: The region number to be disabled +* @return XST_SUCCESS: If the region could be disabled successfully +* XST_FAILURE: If the requested region number is 16 or more. +* +* +******************************************************************************/ +u32 Xil_DisableMPURegionByRegNum (u32 reg_num) { + u32 Temp = 0U; + u32 ReturnVal = XST_FAILURE; + + if (reg_num >= 16U) { + xdbg_printf(DEBUG, "Invalid region number\r\n"); + goto exit1; + } + Xil_DCacheFlush(); + Xil_ICacheInvalidate(); + + mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,reg_num); +#if defined (__GNUC__) + Temp = mfcp(XREG_CP15_MPU_REG_SIZE_EN); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_MPU_REG_SIZE_EN,Temp); +#endif + Temp &= (~REGION_EN); + dsb(); + mtcp(XREG_CP15_MPU_REG_SIZE_EN,Temp); + dsb(); + isb(); + Xil_UpdateMPUConfig(reg_num, 0U, 0U, 0U); + ReturnVal = XST_SUCCESS; + +exit1: + return ReturnVal; +} + +/*****************************************************************************/ +/** +* @brief Enables the corresponding region number as passed by the user. +* +* @param reg_num: The region number to be enabled +* @param address: 32 bit address for start of the region. +* @param size: Requested size of the region. +* @param attrib: Attribute for the corresponding region. +* @return XST_SUCCESS: If the region could be created successfully +* XST_FAILURE: If the requested region number is 16 or more. +* +* +******************************************************************************/ +u32 Xil_SetMPURegionByRegNum (u32 reg_num, INTPTR addr, u64 size, u32 attrib) +{ + u32 ReturnVal = XST_SUCCESS; + INTPTR Localaddr = addr; + u32 Regionsize = 0; + u32 Index; + + if (reg_num >= 16U) { + xdbg_printf(DEBUG, "Invalid region number\r\n"); + ReturnVal = XST_FAILURE; + goto exit2; + } + + if (Mpu_Config[reg_num].RegionStatus == MPU_REG_ENABLED) { + xdbg_printf(DEBUG, "Region already enabled\r\n"); + ReturnVal = XST_FAILURE; + goto exit2; + } + + Xil_DCacheFlush(); + Xil_ICacheInvalidate(); + mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,reg_num); + isb(); + + /* Lookup the size. */ + for (Index = 0; Index < + sizeof region_size / sizeof region_size[0]; Index++) { + if (size <= region_size[Index].size) { + Regionsize = region_size[Index].encoding; + break; + } + } + + Localaddr &= ~(region_size[Index].size - 1); + Regionsize <<= 1; + Regionsize |= REGION_EN; + dsb(); + mtcp(XREG_CP15_MPU_REG_BASEADDR, Localaddr); + mtcp(XREG_CP15_MPU_REG_ACCESS_CTRL, attrib); + mtcp(XREG_CP15_MPU_REG_SIZE_EN, Regionsize); + dsb(); + isb(); + Xil_UpdateMPUConfig(reg_num, Localaddr, Regionsize, attrib); +exit2: + return ReturnVal; + +} + +/*****************************************************************************/ +/** +* @brief Initializes the MPU configuration table that are setup in the +* R5 boot code in the Init_Mpu function called before C main. +* +* @param none +* @return none +* +* +******************************************************************************/ +void Xil_InitializeExistingMPURegConfig(void) +{ + u32 Index = 0U; + u32 Index1 = 0U; + u32 MPURegSize; + INTPTR MPURegBA; + u32 MPURegAttrib; + u32 Tempsize; + + while (Index < MAX_POSSIBLE_MPU_REGS) { + mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,Index); +#if defined (__GNUC__) + MPURegSize = mfcp(XREG_CP15_MPU_REG_SIZE_EN); + MPURegBA = mfcp(XREG_CP15_MPU_REG_BASEADDR); + MPURegAttrib = mfcp(XREG_CP15_MPU_REG_ACCESS_CTRL); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_MPU_REG_SIZE_EN,MPURegSize); + mfcp(XREG_CP15_MPU_REG_BASEADDR, MPURegBA); + mfcp(XREG_CP15_MPU_REG_ACCESS_CTRL, MPURegAttrib); +#endif + if (MPURegSize & REGION_EN) { + Mpu_Config[Index].RegionStatus = MPU_REG_ENABLED; + Mpu_Config[Index].BaseAddress = MPURegBA; + Mpu_Config[Index].Attribute = MPURegAttrib; + Tempsize = MPURegSize & (~REGION_EN); + Tempsize >>= 1; + for (Index1 = 0; Index1 < + (sizeof (region_size) / sizeof (region_size[0])); Index1++) { + if (Tempsize <= region_size[Index1].encoding) { + Mpu_Config[Index].Size = region_size[Index1].size; + break; + } + } + } + Index++; + } +} + +/*****************************************************************************/ +/** +* @brief Returns the next available free MPU region +* +* @param none +* @return The free MPU region available +* +* +******************************************************************************/ +u32 Xil_GetNextMPURegion(void) +{ + u32 Index = 0U; + u32 NextAvailableReg = 0xFF; + while (Index < MAX_POSSIBLE_MPU_REGS) { + if (Mpu_Config[Index].RegionStatus != MPU_REG_ENABLED) { + NextAvailableReg = Index; + break; + } + Index++; + } + return NextAvailableReg; +}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_mpu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_mpu.h new file mode 100644 index 0000000..95ffc66 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_mpu.h
@@ -0,0 +1,134 @@ +/****************************************************************************** +* +* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xil_mmu.h +* +* @addtogroup r5_mpu_apis Cortex R5 Processor MPU specific APIs +* +* MPU functions provides access to MPU operations such as enable MPU, disable +* MPU and set attribute for section of memory. +* Boot code invokes Init_MPU function to configure the MPU. A total of 10 MPU +* regions are allocated with another 6 being free for users. Overview of the +* memory attributes for different MPU regions is as given below, +* +*| | Memory Range | Attributes of MPURegion | +*|-----------------------|-------------------------|-----------------------------| +*| DDR | 0x00000000 - 0x7FFFFFFF | Normal write-back Cacheable | +*| PL | 0x80000000 - 0xBFFFFFFF | Strongly Ordered | +*| QSPI | 0xC0000000 - 0xDFFFFFFF | Device Memory | +*| PCIe | 0xE0000000 - 0xEFFFFFFF | Device Memory | +*| STM_CORESIGHT | 0xF8000000 - 0xF8FFFFFF | Device Memory | +*| RPU_R5_GIC | 0xF9000000 - 0xF90FFFFF | Device memory | +*| FPS | 0xFD000000 - 0xFDFFFFFF | Device Memory | +*| LPS | 0xFE000000 - 0xFFFFFFFF | Device Memory | +*| OCM | 0xFFFC0000 - 0xFFFFFFFF | Normal write-back Cacheable | +* +* +* @note +* For a system where DDR is less than 2GB, region after DDR and before PL is +* marked as undefined in translation table. Memory range 0xFE000000-0xFEFFFFFF is +* allocated for upper LPS slaves, where as memory region 0xFF000000-0xFFFFFFFF is +* allocated for lower LPS slaves. +* +* @{ +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- --------------------------------------------------- +* 5.00 pkp 02/10/14 Initial version +* 6.4 asa 08/16/17 Added many APIs for MPU access to make MPU usage +* user-friendly. The APIs added are: Xil_UpdateMPUConfig, +* Xil_GetMPUConfig, Xil_GetNumOfFreeRegions, +* Xil_GetNextMPURegion, Xil_DisableMPURegionByRegNum, +* Xil_GetMPUFreeRegMask, Xil_SetMPURegionByRegNum, and +* Xil_InitializeExistingMPURegConfig. +* Added a new array of structure of type XMpuConfig to +* represent the MPU configuration table. +* </pre> +* + +* +* +******************************************************************************/ + +#ifndef XIL_MPU_H +#define XIL_MPU_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ +#include "xil_types.h" +/***************************** Include Files *********************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ +#define MPU_REG_DISABLED 0U +#define MPU_REG_ENABLED 1U +#define MAX_POSSIBLE_MPU_REGS 16U +/**************************** Type Definitions *******************************/ +struct XMpuConfig{ + u32 RegionStatus; /* Enabled or disabled */ + INTPTR BaseAddress;/* MPU region base address */ + u64 Size; /* MPU region size address */ + u32 Attribute; /* MPU region size attribute */ +}; + +typedef struct XMpuConfig XMpu_Config[MAX_POSSIBLE_MPU_REGS]; + +extern XMpu_Config Mpu_Config; +/************************** Constant Definitions *****************************/ + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib); +void Xil_EnableMPU(void); +void Xil_DisableMPU(void); +u32 Xil_SetMPURegion(INTPTR addr, u64 size, u32 attrib); +u32 Xil_UpdateMPUConfig(u32 reg_num, INTPTR address, u32 size, u32 attrib); +void Xil_GetMPUConfig (XMpu_Config mpuconfig); +u32 Xil_GetNumOfFreeRegions (void); +u32 Xil_GetNextMPURegion(void); +u32 Xil_DisableMPURegionByRegNum (u32 reg_num); +u16 Xil_GetMPUFreeRegMask (void); +u32 Xil_SetMPURegionByRegNum (u32 reg_num, INTPTR addr, u64 size, u32 attrib); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XIL_MPU_H */ +/** +* @} End of "addtogroup r5_mpu_apis". +*/ \ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_printf.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_printf.c similarity index 98% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_printf.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_printf.c index 9dffed1..dc0897f 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_printf.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_printf.c
@@ -75,8 +75,8 @@ (par->num2)--; #ifdef STDOUT_BASEADDRESS outbyte(*LocalPtr); - LocalPtr += 1; #endif + LocalPtr += 1; } /* Pad on right if needed */ @@ -135,8 +135,8 @@ while (&outbuf[i] >= outbuf) { #ifdef STDOUT_BASEADDRESS outbyte( outbuf[i] ); - i--; #endif + i--; } padding( par->left_flag, par); } @@ -239,6 +239,11 @@ /* void esp_printf( const func_ptr f_ptr, const charptr ctrl1, ...) */ +#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE +void xil_printf( const char8 *ctrl1, ...){ + XPVXenConsole_Printf(ctrl1); +} +#else void xil_printf( const char8 *ctrl1, ...) { s32 Check; @@ -262,8 +267,8 @@ if (*ctrl != '%') { #ifdef STDOUT_BASEADDRESS outbyte(*ctrl); - ctrl += 1; #endif + ctrl += 1; continue; } @@ -434,5 +439,5 @@ } va_end( argp); } - +#endif /*---------------------------------------------------*/
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_printf.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_printf.h similarity index 91% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_printf.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_printf.h index 2be5c57..016ae3b 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_printf.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_printf.h
@@ -10,6 +10,10 @@ #include <stdarg.h> #include "xil_types.h" #include "xparameters.h" +#include "bspconfig.h" +#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE +#include "xen_console.h" +#endif /*----------------------------------------------------*/ /* Use the following parameter passing structure to */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_io.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_sleepcommon.c similarity index 64% copy from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_io.c copy to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_sleepcommon.c index 31de055..972a310 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_io.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_sleepcommon.c
@@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved. +* Copyright (C) 2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -32,76 +32,75 @@ /*****************************************************************************/ /** * -* @file xil_io.c +*@file xil_sleepcommon.c * -* Contains I/O functions for memory-mapped or non-memory-mapped I/O -* architectures. These functions encapsulate Cortex A53 architecture-specific -* I/O requirements. -* -* @note -* -* This file contains architecture-dependent code. +* This file contains the sleep API's * * <pre> * MODIFICATION HISTORY: * * Ver Who Date Changes * ----- -------- -------- ----------------------------------------------- -* 5.00 pkp 05/29/14 First release +* 6.6 srm 11/02/17 First release * </pre> ******************************************************************************/ /***************************** Include Files *********************************/ #include "xil_io.h" -#include "xil_types.h" -#include "xil_assert.h" +#include "sleep.h" + +/**************************** Constant Definitions *************************/ + /*****************************************************************************/ /** * -* Perform a 16-bit endian converion. +* This API gives delay in sec * -* @param Data contains the value to be converted. +* @param seconds - delay time in seconds * -* @return converted value. +* @return none * -* @note None. +* @note none * -******************************************************************************/ -u16 Xil_EndianSwap16(u16 Data) -{ - return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U)); -} +*****************************************************************************/ + void sleep(unsigned int seconds) + { +#if defined (ARMR5) + sleep_R5(seconds); +#elif defined (__aarch64__) || defined (ARMA53_32) + sleep_A53(seconds); +#elif defined (__MICROBLAZE__) + sleep_MB(seconds); +#else + sleep_A9(seconds); +#endif -/*****************************************************************************/ + } + +/****************************************************************************/ /** * -* Perform a 32-bit endian converion. +* This API gives delay in usec * -* @param Data contains the value to be converted. +* @param useconds - delay time in useconds * -* @return converted value. +* @return none * -* @note None. +* @note none * -******************************************************************************/ -u32 Xil_EndianSwap32(u32 Data) -{ - u16 LoWord; - u16 HiWord; +*****************************************************************************/ + void usleep(unsigned long useconds) + { +#if defined (ARMR5) + usleep_R5(useconds); +#elif defined (__aarch64__) || defined (ARMA53_32) + usleep_A53(useconds); +#elif defined (__MICROBLAZE__) + usleep_MB(useconds); +#else + usleep_A9(useconds); +#endif - /* get each of the half words from the 32 bit word */ - - LoWord = (u16) (Data & 0x0000FFFFU); - HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U); - - /* byte swap each of the 16 bit half words */ - - LoWord = (((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U)); - HiWord = (((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U)); - - /* swap the half words before returning the value */ - - return ((((u32)LoWord) << (u32)16U) | (u32)HiWord); -} + }
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_sleeptimer.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_sleeptimer.c new file mode 100644 index 0000000..4772606 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_sleeptimer.c
@@ -0,0 +1,161 @@ +/****************************************************************************** +* +* Copyright (C) 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_sleeptimer.c +* +* This file provides the common helper routines for the sleep API's +* +* <pre> +* MODIFICATION HISTORY : +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 6.6 srm 10/18/17 First Release. +* +* </pre> +*****************************************************************************/ + +/**************************** Include Files ********************************/ + +#include "xil_io.h" +#include "xil_sleeptimer.h" +#include "xtime_l.h" + +/**************************** Constant Definitions *************************/ + + +/* Function definitions are applicable only when TTC3 is present*/ +#if defined (SLEEP_TIMER_BASEADDR) +/****************************************************************************/ +/** +* +* This is a helper function used by sleep/usleep APIs to +* have delay in sec/usec +* +* @param delay - delay time in seconds/micro seconds +* +* @param frequency - Number of counts per second/micro second +* +* @return none +* +* @note none +* +*****************************************************************************/ +void Xil_SleepTTCCommon(u32 delay, u64 frequency) +{ + INTPTR tEnd = 0U; + INTPTR tCur = 0U; + XCntrVal TimeHighVal = 0U; + XCntrVal TimeLowVal1 = 0U; + XCntrVal TimeLowVal2 = 0U; + + TimeLowVal1 = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR + + XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET); + tEnd = (INTPTR)TimeLowVal1 + ((INTPTR)(delay) * frequency); + do + { + TimeLowVal2 = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR + + XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET); + if (TimeLowVal2 < TimeLowVal1) { + TimeHighVal++; + } + TimeLowVal1 = TimeLowVal2; + tCur = (((INTPTR) TimeHighVal) << XSLEEP_TIMER_REG_SHIFT) | + (INTPTR)TimeLowVal2; + }while (tCur < tEnd); +} + + +/*****************************************************************************/ +/** +* +* This API starts the Triple Timer Counter +* +* @param none +* +* @return none +* +* @note none +* +*****************************************************************************/ +void XTime_StartTTCTimer() +{ + u32 TimerPrescalar; + u32 TimerCntrl; + +#if (defined (__aarch64__) && EL3==1) || defined (ARMR5) || defined (ARMA53_32) + u32 LpdRst; + + LpdRst = XSleep_ReadCounterVal(RST_LPD_IOU2); + + /* check if the timer is reset */ + if (((LpdRst & (RST_LPD_IOU2_TTC_BASE_RESET_MASK << + XSLEEP_TTC_INSTANCE)) != 0 )) { + LpdRst = LpdRst & (~(RST_LPD_IOU2_TTC_BASE_RESET_MASK << + XSLEEP_TTC_INSTANCE)); + Xil_Out32(RST_LPD_IOU2, LpdRst); + } else { +#endif + TimerCntrl = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR + + XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET); + /* check if Timer is disabled */ + if ((TimerCntrl & XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK) == 0) { + TimerPrescalar = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR + + XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET); + /* check if Timer is configured with proper functionalty for sleep */ + if ((TimerPrescalar & XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK) == 0) + return; + } +#if (defined (__aarch64__) && EL3==1) || defined (ARMR5) || defined (ARMA53_32) + } +#endif + /* Disable the timer to configure */ + TimerCntrl = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR + + XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET); + TimerCntrl = TimerCntrl | XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK; + Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET, + TimerCntrl); + /* Disable the prescalar */ + TimerPrescalar = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR + + XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET); + TimerPrescalar = TimerPrescalar & (~XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK); + Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET, + TimerPrescalar); + /* Enable the Timer */ + TimerCntrl = TimerCntrl & (~XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK); + Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET, + TimerCntrl); +} +#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_sleeptimer.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_sleeptimer.h new file mode 100644 index 0000000..4bfac0a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_sleeptimer.h
@@ -0,0 +1,116 @@ +/****************************************************************************** +* +* Copyright (C) 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_sleeptimer.h +* +* This header file contains ARM Cortex A53,A9,R5 specific sleep related APIs. +* For sleep related functions that can be used across all Xilinx supported +* processors, please use xil_sleeptimer.h. +* +* +* <pre> +* MODIFICATION HISTORY : +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 6.6 srm 10/18/17 First Release. +* +* </pre> +*****************************************************************************/ + +#ifndef XIL_SLEEPTIMER_H /* prevent circular inclusions */ +#define XIL_SLEEPTIMER_H /* by using protection macros */ +/**************************** Include Files ********************************/ + +#include "xil_io.h" +#include "xparameters.h" +#include "bspconfig.h" + +/************************** Constant Definitions *****************************/ + +#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) +#define XSLEEP_TIMER_REG_SHIFT 32U +#define XSleep_ReadCounterVal Xil_In32 +#define XCntrVal u32 +#else +#define XSLEEP_TIMER_REG_SHIFT 16U +#define XSleep_ReadCounterVal Xil_In16 +#define XCntrVal u16 +#endif + +#if defined(ARMR5) || (defined (__aarch64__) && EL3==1) || defined (ARMA53_32) +#define RST_LPD_IOU2 0xFF5E0238U +#define RST_LPD_IOU2_TTC_BASE_RESET_MASK 0x00000800U +#endif + +#if defined (SLEEP_TIMER_BASEADDR) +/** @name Register Map +* +* Register offsets from the base address of the TTC device +* +* @{ +*/ + #define XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET 0x00000000U + /**< Clock Control Register */ + #define XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET 0x0000000CU + /**< Counter Control Register*/ + #define XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET 0x00000018U + /**< Current Counter Value */ +/* @} */ +/** @name Clock Control Register +* Clock Control Register definitions of TTC +* @{ +*/ + #define XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK 0x00000001U + /**< Prescale enable */ +/* @} */ +/** @name Counter Control Register +* Counter Control Register definitions of TTC +* @{ +*/ +#define XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK 0x00000001U + /**< Disable the counter */ +#define XSLEEP_TIMER_TTC_CNT_CNTRL_RST_MASK 0x00000010U + /**< Reset counter */ +/* @} */ + +/**************************** Type Definitions *******************************/ + +/************************** Function Prototypes ******************************/ + +void Xil_SleepTTCCommon(u32 delay, u64 frequency); +void XTime_StartTTCTimer(); + +#endif +#endif /* XIL_SLEEPTIMER_H */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testcache.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_testcache.c similarity index 83% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testcache.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_testcache.c index a2c4b0b..157ad08 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testcache.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_testcache.c
@@ -47,7 +47,6 @@ * </pre> * * @note -* * This file contain functions that all operate on HAL. * ******************************************************************************/ @@ -74,17 +73,21 @@ static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(32))); #endif + +/*****************************************************************************/ /** -* Perform DCache range related API test such as Xil_DCacheFlushRange and -* Xil_DCacheInvalidateRange. This test function writes a constant value -* to the Data array, flushes the range, writes a new value, then invalidates -* the corresponding range. +* +* @brief Perform DCache range related API test such as Xil_DCacheFlushRange +* and Xil_DCacheInvalidateRange. This test function writes a constant +* value to the Data array, flushes the range, writes a new value, then +* invalidates the corresponding range. +* @param None * * @return +* - -1 is returned for a failure +* - 0 is returned for a pass * -* - 0 is returned for a pass -* - -1 is returned for a failure -*/ +*****************************************************************************/ s32 Xil_TestDCacheRange(void) { s32 Index; @@ -204,16 +207,17 @@ } +/*****************************************************************************/ /** -* Perform DCache all related API test such as Xil_DCacheFlush and -* Xil_DCacheInvalidate. This test function writes a constant value -* to the Data array, flushes the DCache, writes a new value, then invalidates -* the DCache. +* @brief Perform DCache all related API test such as Xil_DCacheFlush and +* Xil_DCacheInvalidate. This test function writes a constant value +* to the Data array, flushes the DCache, writes a new value, +* then invalidates the DCache. * * @return -* - 0 is returned for a pass -* - -1 is returned for a failure -*/ +* - 0 is returned for a pass +* - -1 is returned for a failure +*****************************************************************************/ s32 Xil_TestDCacheAll(void) { s32 Index; @@ -328,15 +332,15 @@ return Status; } - +/*****************************************************************************/ /** -* Perform Xil_ICacheInvalidateRange() on a few function pointers. +* @brief Perform Xil_ICacheInvalidateRange() on a few function pointers. * * @return -* * - 0 is returned for a pass +* @note * The function will hang if it fails. -*/ +*****************************************************************************/ s32 Xil_TestICacheRange(void) { @@ -349,14 +353,15 @@ return 0; } +/*****************************************************************************/ /** -* Perform Xil_ICacheInvalidate(). +* @brief Perform Xil_ICacheInvalidate() on a few function pointers. * * @return -* -* - 0 is returned for a pass -* The function will hang if it fails. -*/ +* - 0 is returned for a pass +* @note +* The function will hang if it fails. +*****************************************************************************/ s32 Xil_TestICacheAll(void) { Xil_ICacheInvalidate();
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testcache.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_testcache.h similarity index 92% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testcache.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_testcache.h index b3c416c..c35e9a4 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testcache.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_testcache.h
@@ -34,11 +34,16 @@ * * @file xil_testcache.h * -* This file contains utility functions to test cache. +* @addtogroup common_test_utils +* <h2>Cache test </h2> +* The xil_testcache.h file contains utility functions to test cache. * +* @{ +* <pre> * Ver Who Date Changes * ----- ---- -------- ----------------------------------------------- * 1.00a hbm 07/29/09 First release +* </pre> * ******************************************************************************/ @@ -61,3 +66,6 @@ #endif #endif /* end of protection macro */ +/** +* @} End of "addtogroup common_test_utils". +*/ \ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testio.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_testio.c similarity index 70% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testio.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_testio.c index a68d765..e6a3680 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testio.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_testio.c
@@ -32,7 +32,7 @@ /*****************************************************************************/ /** * -* @file xil_testmemend.c +* @file xil_testio.c * * Contains the memory test utility functions. * @@ -95,18 +95,17 @@ /*****************************************************************************/ /** * -* Perform a destructive 8-bit wide register IO test where the register is -* accessed using Xil_Out8 and Xil_In8, and comparing the reading and writing -* values. +* @brief Perform a destructive 8-bit wide register IO test where the +* register is accessed using Xil_Out8 and Xil_In8, and comparing +* the written values by reading them back. * -* @param Addr is a pointer to the region of memory to be tested. -* @param Length is the Length of the block. -* @param Value is the constant used for writting the memory. +* @param Addr: a pointer to the region of memory to be tested. +* @param Length: Length of the block. +* @param Value: constant used for writting the memory. * * @return -* -* - -1 is returned for a failure -* - 0 is returned for a pass +* - -1 is returned for a failure +* - 0 is returned for a pass * *****************************************************************************/ @@ -133,24 +132,24 @@ /*****************************************************************************/ /** * -* Perform a destructive 16-bit wide register IO test. Each location is tested -* by sequentially writing a 16-bit wide register, reading the register, and -* comparing value. This function tests three kinds of register IO functions, -* normal register IO, little-endian register IO, and big-endian register IO. -* When testing little/big-endian IO, the function performs the following -* sequence, Xil_Out16LE/Xil_Out16BE, Xil_In16, Compare In-Out values, -* Xil_Out16, Xil_In16LE/Xil_In16BE, Compare In-Out values. Whether to swap the -* read-in value before comparing is controlled by the 5th argument. +* @brief Perform a destructive 16-bit wide register IO test. Each location +* is tested by sequentially writing a 16-bit wide register, reading +* the register, and comparing value. This function tests three kinds +* of register IO functions, normal register IO, little-endian register +* IO, and big-endian register IO. When testing little/big-endian IO, +* the function performs the following sequence, Xil_Out16LE/Xil_Out16BE, +* Xil_In16, Compare In-Out values, Xil_Out16, Xil_In16LE/Xil_In16BE, +* Compare In-Out values. Whether to swap the read-in value before +* comparing is controlled by the 5th argument. * -* @param Addr is a pointer to the region of memory to be tested. -* @param Length is the Length of the block. -* @param Value is the constant used for writting the memory. -* @param Kind is the test kind. Acceptable values are: -* XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE. -* @param Swap indicates whether to byte swap the read-in value. +* @param Addr: a pointer to the region of memory to be tested. +* @param Length: Length of the block. +* @param Value: constant used for writting the memory. +* @param Kind: Type of test. Acceptable values are: +* XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE. +* @param Swap: indicates whether to byte swap the read-in value. * * @return -* * - -1 is returned for a failure * - 0 is returned for a pass * @@ -219,26 +218,25 @@ /*****************************************************************************/ /** * -* Perform a destructive 32-bit wide register IO test. Each location is tested -* by sequentially writing a 32-bit wide regsiter, reading the register, and -* comparing value. This function tests three kinds of register IO functions, -* normal register IO, little-endian register IO, and big-endian register IO. -* When testing little/big-endian IO, the function perform the following -* sequence, Xil_Out32LE/Xil_Out32BE, Xil_In32, Compare, -* Xil_Out32, Xil_In32LE/Xil_In32BE, Compare. Whether to swap the read-in value -* before comparing is controlled by the 5th argument. -* -* @param Addr is a pointer to the region of memory to be tested. -* @param Length is the Length of the block. -* @param Value is the constant used for writting the memory. -* @param Kind is the test kind. Acceptable values are: -* XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE. -* @param Swap indicates whether to byte swap the read-in value. +* @brief Perform a destructive 32-bit wide register IO test. Each location +* is tested by sequentially writing a 32-bit wide regsiter, reading +* the register, and comparing value. This function tests three kinds +* of register IO functions, normal register IO, little-endian register IO, +* and big-endian register IO. When testing little/big-endian IO, +* the function perform the following sequence, Xil_Out32LE/ +* Xil_Out32BE, Xil_In32, Compare, Xil_Out32, Xil_In32LE/Xil_In32BE, Compare. +* Whether to swap the read-in value *before comparing is controlled +* by the 5th argument. +* @param Addr: a pointer to the region of memory to be tested. +* @param Length: Length of the block. +* @param Value: constant used for writting the memory. +* @param Kind: type of test. Acceptable values are: +* XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE. +* @param Swap: indicates whether to byte swap the read-in value. * * @return -* -* - -1 is returned for a failure -* - 0 is returned for a pass +* - -1 is returned for a failure +* - 0 is returned for a pass * *****************************************************************************/ s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap)
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testio.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_testio.h similarity index 93% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testio.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_testio.h index fba0c10..ad68ead 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testio.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_testio.h
@@ -32,19 +32,19 @@ /*****************************************************************************/ /** * -* @file xil_testmemend.h +* @file xil_testio.h * -* This file contains utility functions to teach endian related memory +* @addtogroup common_test_utils Test Utilities +* <h2>I/O test </h2> +* The xil_testio.h file contains utility functions to test endian related memory * IO functions. * -* <b>Memory test description</b> -* * A subset of the memory tests can be selected or all of the tests can be run * in order. If there is an error detected by a subtest, the test stops and the * failure code is returned. Further tests are not run even if all of the tests * are selected. * -* +* @{ * <pre> * MODIFICATION HISTORY: * @@ -89,3 +89,6 @@ #endif #endif /* end of protection macro */ +/** +* @} End of "addtogroup common_test_utils". +*/
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testmem.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_testmem.c similarity index 92% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testmem.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_testmem.c index 19a3b66..87426d1 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testmem.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_testmem.c
@@ -66,22 +66,20 @@ /*****************************************************************************/ /** * -* Perform a destructive 32-bit wide memory test. +* @brief Perform a destructive 32-bit wide memory test. * -* @param Addr is a pointer to the region of memory to be tested. -* @param Words is the length of the block. -* @param Pattern is the constant used for the constant pattern test, if 0, +* @param Addr: pointer to the region of memory to be tested. +* @param Words: length of the block. +* @param Pattern: constant used for the constant pattern test, if 0, * 0xDEADBEEF is used. -* @param Subtest is the test selected. See xil_testmem.h for possible -* values. +* @param Subtest: test type selected. See xil_testmem.h for possible +* values. * * @return -* -* - 0 is returned for a pass -* - -1 is returned for a failure +* - 0 is returned for a pass +* - 1 is returned for a failure * * @note -* * Used for spaces where the address range of the region is smaller than * the data width. If the memory range is greater than 2 ** Width, * the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will @@ -315,22 +313,21 @@ /*****************************************************************************/ /** * -* Perform a destructive 16-bit wide memory test. +* @brief Perform a destructive 16-bit wide memory test. * -* @param Addr is a pointer to the region of memory to be tested. -* @param Words is the length of the block. -* @param Pattern is the constant used for the constant Pattern test, if 0, +* @param Addr: pointer to the region of memory to be tested. +* @param Words: length of the block. +* @param Pattern: constant used for the constant Pattern test, if 0, * 0xDEADBEEF is used. -* @param Subtest is the test selected. See xil_testmem.h for possible -* values. +* @param Subtest: type of test selected. See xil_testmem.h for possible +* values. * * @return * -* - -1 is returned for a failure -* - 0 is returned for a pass +* - -1 is returned for a failure +* - 0 is returned for a pass * * @note -* * Used for spaces where the address range of the region is smaller than * the data width. If the memory range is greater than 2 ** Width, * the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will @@ -549,22 +546,20 @@ /*****************************************************************************/ /** * -* Perform a destructive 8-bit wide memory test. +* @brief Perform a destructive 8-bit wide memory test. * -* @param Addr is a pointer to the region of memory to be tested. -* @param Words is the length of the block. -* @param Pattern is the constant used for the constant pattern test, if 0, +* @param Addr: pointer to the region of memory to be tested. +* @param Words: length of the block. +* @param Pattern: constant used for the constant pattern test, if 0, * 0xDEADBEEF is used. -* @param Subtest is the test selected. See xil_testmem.h for possible -* values. +* @param Subtest: type of test selected. See xil_testmem.h for possible +* values. * * @return -* -* - -1 is returned for a failure -* - 0 is returned for a pass +* - -1 is returned for a failure +* - 0 is returned for a pass * * @note -* * Used for spaces where the address range of the region is smaller than * the data width. If the memory range is greater than 2 ** Width, * the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will @@ -777,18 +772,14 @@ /*****************************************************************************/ /** * -* Rotates the provided value to the left one bit position +* @brief Rotates the provided value to the left one bit position * * @param Input is value to be rotated to the left * @param Width is the number of bits in the input data * * @return +* The resulting unsigned long value of the rotate left * -* The resulting unsigned long value of the rotate left -* -* @note -* -* None. * *****************************************************************************/ static u32 RotateLeft(u32 Input, u8 Width) @@ -831,18 +822,13 @@ /*****************************************************************************/ /** * -* Rotates the provided value to the right one bit position +* @brief Rotates the provided value to the right one bit position * -* @param Input is value to be rotated to the right -* @param Width is the number of bits in the input data +* @param Input: value to be rotated to the right +* @param Width: number of bits in the input data * * @return -* -* The resulting u32 value of the rotate right -* -* @note -* -* None. +* The resulting u32 value of the rotate right * *****************************************************************************/ static u32 RotateRight(u32 Input, u8 Width)
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testmem.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_testmem.h similarity index 79% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testmem.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_testmem.h index 4cbfd87..c204728 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testmem.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_testmem.h
@@ -33,64 +33,57 @@ /** * * @file xil_testmem.h +* @addtogroup common_test_utils * -* This file contains utility functions to test memory. +* <h2>Memory test</h2> * -* <b>Memory test description</b> -* +* The xil_testmem.h file contains utility functions to test memory. * A subset of the memory tests can be selected or all of the tests can be run * in order. If there is an error detected by a subtest, the test stops and the * failure code is returned. Further tests are not run even if all of the tests * are selected. +* Following list describes the supported memory tests: * -* Subtest descriptions: -* <pre> -* XIL_TESTMEM_ALLMEMTESTS: -* Runs all of the following tests +* - XIL_TESTMEM_ALLMEMTESTS: This test runs all of the subtests. * -* XIL_TESTMEM_INCREMENT: -* Incrementing Value Test. -* This test starts at 'XIL_TESTMEM_INIT_VALUE' and uses the -* incrementing value as the test value for memory. +* - XIL_TESTMEM_INCREMENT: This test +* starts at 'XIL_TESTMEM_INIT_VALUE' and uses the incrementing value as the +* test value for memory. * -* XIL_TESTMEM_WALKONES: -* Walking Ones Test. -* This test uses a walking '1' as the test value for memory. -* location 1 = 0x00000001 -* location 2 = 0x00000002 -* ... +* - XIL_TESTMEM_WALKONES: Also known as the Walking ones test. This test +* uses a walking '1' as the test value for memory. +* @code +* location 1 = 0x00000001 +* location 2 = 0x00000002 +* ... +* @endcode * -* XIL_TESTMEM_WALKZEROS: -* Walking Zero's Test. -* This test uses the inverse value of the walking ones test -* as the test value for memory. +* - XIL_TESTMEM_WALKZEROS: Also known as the Walking zero's test. +* This test uses the inverse value of the walking ones test +* as the test value for memory. +* @code * location 1 = 0xFFFFFFFE * location 2 = 0xFFFFFFFD * ... +*@endcode * -* XIL_TESTMEM_INVERSEADDR: -* Inverse Address Test. -* This test uses the inverse of the address of the location under test -* as the test value for memory. +* - XIL_TESTMEM_INVERSEADDR: Also known as the inverse address test. +* This test uses the inverse of the address of the location under test +* as the test value for memory. * -* XIL_TESTMEM_FIXEDPATTERN: -* Fixed Pattern Test. -* This test uses the provided patters as the test value for memory. -* If zero is provided as the pattern the test uses '0xDEADBEEF". -* </pre> +* - XIL_TESTMEM_FIXEDPATTERN: Also known as the fixed pattern test. +* This test uses the provided patters as the test value for memory. +* If zero is provided as the pattern the test uses '0xDEADBEEF". * -* <i>WARNING</i> -* +* @warning * The tests are <b>DESTRUCTIVE</b>. Run before any initialized memory spaces * have been set up. -* * The address provided to the memory tests is not checked for * validity except for the NULL case. It is possible to provide a code-space * pointer for this test to start with and ultimately destroy executable code * causing random failures. * * @note -* * Used for spaces where the address range of the region is smaller than * the data width. If the memory range is greater than 2 ** width, * the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will @@ -160,3 +153,6 @@ #endif #endif /* end of protection macro */ +/** +* @} End of "addtogroup common_test_utils". +*/
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_types.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_types.h similarity index 76% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_types.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_types.h index e8b78b7..8143aff 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_types.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_types.h
@@ -34,9 +34,11 @@ * * @file xil_types.h * -* This file contains basic types for Xilinx software IP. - +* @addtogroup common_types Basic Data types for Xilinx® Software IP * +* The xil_types.h file contains basic types for Xilinx software IP. These data types +* are applicable for all processors supported by Xilinx. +* @{ * <pre> * MODIFICATION HISTORY: * @@ -71,22 +73,28 @@ #define NULL 0U #endif -#define XIL_COMPONENT_IS_READY 0x11111111U /**< component has been initialized */ -#define XIL_COMPONENT_IS_STARTED 0x22222222U /**< component has been started */ +#define XIL_COMPONENT_IS_READY 0x11111111U /**< In device drivers, This macro will be + assigend to "IsReady" member of driver + instance to indicate that driver + instance is initialized and ready to use. */ +#define XIL_COMPONENT_IS_STARTED 0x22222222U /**< In device drivers, This macro will be assigend to + "IsStarted" member of driver instance + to indicate that driver instance is + started and it can be enabled. */ -/** @name New types +/* @name New types * New simple types. * @{ */ #ifndef __KERNEL__ #ifndef XBASIC_TYPES_H -/** +/* * guarded against xbasic_types.h. */ typedef uint8_t u8; typedef uint16_t u16; typedef uint32_t u32; - +/** @}*/ #define __XUINT64__ typedef struct { @@ -97,36 +105,32 @@ /*****************************************************************************/ /** -* Return the most significant half of the 64 bit data type. +* @brief Return the most significant half of the 64 bit data type. * * @param x is the 64 bit word. * * @return The upper 32 bits of the 64 bit word. * -* @note None. -* ******************************************************************************/ #define XUINT64_MSW(x) ((x).Upper) /*****************************************************************************/ /** -* Return the least significant half of the 64 bit data type. +* @brief Return the least significant half of the 64 bit data type. * * @param x is the 64 bit word. * * @return The lower 32 bits of the 64 bit word. * -* @note None. -* ******************************************************************************/ #define XUINT64_LSW(x) ((x).Lower) #endif /* XBASIC_TYPES_H */ -/** +/* * xbasic_types.h does not typedef s* or u64 */ - +/** @{ */ typedef char char8; typedef int8_t s8; typedef int16_t s16; @@ -138,7 +142,7 @@ typedef intptr_t INTPTR; typedef uintptr_t UINTPTR; typedef ptrdiff_t PTRDIFF; - +/** @}*/ #if !defined(LONG) || !defined(ULONG) typedef long LONG; typedef unsigned long ULONG; @@ -151,7 +155,7 @@ #include <linux/types.h> #endif - +/** @{ */ /** * This data type defines an interrupt handler for a device. * The argument points to the instance of the component @@ -165,22 +169,24 @@ typedef void (*XExceptionHandler) (void *InstancePtr); /** - * UPPER_32_BITS - return bits 32-63 of a number - * @n: the number we're accessing + * @brief Returns 32-63 bits of a number. + * @param n : Number being accessed. + * @return Bits 32-63 of number. * - * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress - * the "right shift count >= width of type" warning when that quantity is - * 32-bits. + * @note A basic shift-right of a 64- or 32-bit quantity. + * Use this to suppress the "right shift count >= width of type" + * warning when that quantity is 32-bits. */ #define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16)) /** - * LOWER_32_BITS - return bits 0-31 of a number - * @n: the number we're accessing + * @brief Returns 0-31 bits of a number + * @param n : Number being accessed. + * @return Bits 0-31 of number */ #define LOWER_32_BITS(n) ((u32)(n)) -/*@}*/ + /************************** Constant Definitions *****************************/ @@ -198,3 +204,6 @@ #endif #endif /* end of protection macro */ +/** +* @} End of "addtogroup common_types". +*/
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xparameters_ps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xparameters_ps.h similarity index 88% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xparameters_ps.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xparameters_ps.h index 2f527c9..260c4d5 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xparameters_ps.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xparameters_ps.h
@@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,9 +33,14 @@ /** * @file xparameters_ps.h * -* This file contains the address definitions for the hard peripherals -* attached to the ARM Cortex R5 core. +* @addtogroup r5_peripheral_definitions Cortex R5 peripheral definitions * +* The xparameters_ps.h file contains the canonical definitions and constant +* declarations for peripherals within hardblock, attached to the ARM Cortex R5 +* core. These definitions can be used by drivers or applications to access the +* peripherals. +* +* @{ * <pre> * MODIFICATION HISTORY: * @@ -45,10 +50,6 @@ * 6.0 mus 08/18/16 Defined ARMR5 flag * </pre> * -* @note -* -* None. -* ******************************************************************************/ #ifndef XPARAMETERS_PS_H_ @@ -62,6 +63,8 @@ extern "C" { #endif +/***************************** Include Files *********************************/ + /************************** Constant Definitions *****************************/ /* @@ -94,8 +97,9 @@ #define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID #define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID #define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID -#define XPAR_XWDTPS_0_INTR XPS_LPD_SWDT_INT_ID -#define XPAR_XWDTPS_1_INTR XPS_FPD_SWDT_INT_ID +#define XPAR_XWDTPS_0_INTR XPS_CSU_WDT_INT_ID +#define XPAR_XWDTPS_1_INTR XPS_LPD_SWDT_INT_ID +#define XPAR_XWDTPS_2_INTR XPS_FPD_SWDT_INT_ID #define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID #define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID #define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID @@ -119,6 +123,15 @@ #define XPAR_XADMAPS_6_INTR XPS_ADMA_CH6_INT_ID #define XPAR_XADMAPS_7_INTR XPS_ADMA_CH7_INT_ID #define XPAR_XCSUDMA_INTR XPS_CSU_DMA_INT_ID +#define XPAR_PSU_ADMA_0_INTR XPS_ADMA_CH0_INT_ID +#define XPAR_PSU_ADMA_1_INTR XPS_ADMA_CH1_INT_ID +#define XPAR_PSU_ADMA_2_INTR XPS_ADMA_CH2_INT_ID +#define XPAR_PSU_ADMA_3_INTR XPS_ADMA_CH3_INT_ID +#define XPAR_PSU_ADMA_4_INTR XPS_ADMA_CH4_INT_ID +#define XPAR_PSU_ADMA_5_INTR XPS_ADMA_CH5_INT_ID +#define XPAR_PSU_ADMA_6_INTR XPS_ADMA_CH6_INT_ID +#define XPAR_PSU_ADMA_7_INTR XPS_ADMA_CH7_INT_ID +#define XPAR_PSU_CSUDMA_INTR XPS_CSU_DMA_INT_ID #define XPAR_XMPU_LPD_INTR XPS_XMPU_LPD_INT_ID #define XPAR_XZDMAPS_0_INTR XPS_ZDMA_CH0_INT_ID #define XPAR_XZDMAPS_1_INTR XPS_ZDMA_CH1_INT_ID @@ -128,6 +141,14 @@ #define XPAR_XZDMAPS_5_INTR XPS_ZDMA_CH5_INT_ID #define XPAR_XZDMAPS_6_INTR XPS_ZDMA_CH6_INT_ID #define XPAR_XZDMAPS_7_INTR XPS_ZDMA_CH7_INT_ID +#define XPAR_PSU_GDMA_0_INTR XPS_ZDMA_CH0_INT_ID +#define XPAR_PSU_GDMA_1_INTR XPS_ZDMA_CH1_INT_ID +#define XPAR_PSU_GDMA_2_INTR XPS_ZDMA_CH2_INT_ID +#define XPAR_PSU_GDMA_3_INTR XPS_ZDMA_CH3_INT_ID +#define XPAR_PSU_GDMA_4_INTR XPS_ZDMA_CH4_INT_ID +#define XPAR_PSU_GDMA_5_INTR XPS_ZDMA_CH5_INT_ID +#define XPAR_PSU_GDMA_6_INTR XPS_ZDMA_CH6_INT_ID +#define XPAR_PSU_GDMA_7_INTR XPS_ZDMA_CH7_INT_ID #define XPAR_XMPU_FPD_INTR XPS_XMPU_FPD_INT_ID #define XPAR_XCCI_FPD_INTR XPS_FPD_CCI_INT_ID #define XPAR_XSMMU_FPD_INTR XPS_FPD_SMMU_INT_ID @@ -194,6 +215,7 @@ #define XPS_RTC_ALARM_INT_ID (26U + 32U) #define XPS_RTC_SEC_INT_ID (27U + 32U) #define XPS_LPD_SWDT_INT_ID (52U + 32U) +#define XPS_CSU_WDT_INT_ID (53U + 32U) #define XPS_FPD_SWDT_INT_ID (113U + 32U) #define XPS_TTC0_0_INT_ID (36U + 32U) #define XPS_TTC0_1_INT_ID (37U + 32U) @@ -282,6 +304,7 @@ #define XPAR_PSU_TTC_9_INTR XPS_TTC3_0_INT_ID #define XPAR_PSU_TTC_10_INTR XPS_TTC3_1_INT_ID #define XPAR_PSU_TTC_11_INTR XPS_TTC3_2_INT_ID +#define XPAR_PSU_AMS_INTR XPS_AMS_INT_ID #define XPAR_XADCPS_NUM_INSTANCES 1U #define XPAR_XADCPS_0_DEVICE_ID 0U @@ -318,3 +341,6 @@ #endif #endif /* protection macro */ +/** +* @} End of "addtogroup r5_peripheral_definitions". +*/ \ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xplatform_info.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xplatform_info.c similarity index 73% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xplatform_info.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xplatform_info.c index 9d4560a..2c08e5f 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xplatform_info.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xplatform_info.c
@@ -45,6 +45,13 @@ * 5.04 pkp 01/12/16 Added platform information support for Cortex-A53 32bit * mode * 6.00 mus 17/08/16 Removed unused variable from XGetPlatform_Info +* 6.4 ms 05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info +* function for PMUFW. +* ms 06/13/17 Added PSU_PMU macro to provide support of +* XGetPlatform_Info function for PMUFW. +* mus 08/17/17 Add EL1 NS mode support for +* XGet_Zynq_UltraMp_Platform_info and XGetPSVersion_Info +* APIs. * </pre> * ******************************************************************************/ @@ -54,7 +61,10 @@ #include "xil_types.h" #include "xil_io.h" #include "xplatform_info.h" - +#if defined (__aarch64__) +#include "bspconfig.h" +#include "xil_smc.h" +#endif /************************** Constant Definitions *****************************/ /**************************** Type Definitions *******************************/ @@ -69,19 +79,17 @@ /*****************************************************************************/ /** * -* This API is used to provide information about platform +* @brief This API is used to provide information about platform * * @param None. * * @return The information about platform defined in xplatform_info.h * -* @note None. -* ******************************************************************************/ u32 XGetPlatform_Info() { -#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) +#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU) return XPLAT_ZYNQ_ULTRA_MP; #elif (__microblaze__) return XPLAT_MICROBLAZE; @@ -93,43 +101,61 @@ /*****************************************************************************/ /** * -* This API is used to provide information about zynq ultrascale MP platform +* @brief This API is used to provide information about zynq ultrascale MP platform * * @param None. * * @return The information about zynq ultrascale MP platform defined in * xplatform_info.h * -* @note None. -* ******************************************************************************/ #if defined (ARMR5) || (__aarch64__) || (ARMA53_32) u32 XGet_Zynq_UltraMp_Platform_info() { +#if EL1_NONSECURE + XSmc_OutVar reg; + /* + * This SMC call will return, + * idcode - upper 32 bits of reg.Arg0 + * version - lower 32 bits of reg.Arg1 + */ + reg = Xil_Smc(GET_CHIPID_SMC_FID,0,0, 0, 0, 0, 0, 0); + return (u32)((reg.Arg1 >> XPLAT_INFO_SHIFT) & XPLAT_INFO_MASK); +#else u32 reg; reg = ((Xil_In32(XPAR_CSU_BASEADDR + XPAR_CSU_VER_OFFSET) >> 12U )& XPLAT_INFO_MASK); return reg; +#endif } #endif /*****************************************************************************/ /** * -* This API is used to provide information about PS Silicon version +* @brief This API is used to provide information about PS Silicon version * * @param None. * * @return The information about PS Silicon version. * -* @note None. -* ******************************************************************************/ -#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) +#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU) u32 XGetPSVersion_Info() { +#if EL1_NONSECURE + /* + * This SMC call will return, + * idcode - upper 32 bits of reg.Arg0 + * version - lower 32 bits of reg.Arg1 + */ + XSmc_OutVar reg; + reg = Xil_Smc(GET_CHIPID_SMC_FID,0,0, 0, 0, 0, 0, 0); + return (u32)(reg.Arg1 & XPS_VERSION_INFO_MASK); +#else u32 reg; reg = (Xil_In32(XPAR_CSU_BASEADDR + XPAR_CSU_VER_OFFSET) & XPS_VERSION_INFO_MASK); return reg; +#endif } #endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xplatform_info.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xplatform_info.h similarity index 80% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xplatform_info.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xplatform_info.h index 7028a83..0582222 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xplatform_info.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xplatform_info.h
@@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -34,7 +34,21 @@ * * @file xplatform_info.h * -* This file contains definitions for various platforms available +* @addtogroup common_platform_info APIs to Get Platform Information +* +* The xplatform_info.h file contains definitions for various available Xilinx® +* platforms. Also, it contains prototype of APIs, which can be used to get the +* platform information. +* +* @{ +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- --------- ------------------------------------------------------- +* 6.4 ms 05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info +* function for PMUFW. +* </pre> * ******************************************************************************/ @@ -65,6 +79,7 @@ #define XPS_VERSION_2 0x1 #define XPLAT_INFO_MASK (0xF) +#define XPLAT_INFO_SHIFT (0xC) #define XPS_VERSION_INFO_MASK (0xF) /**************************** Type Definitions *******************************/ @@ -74,7 +89,7 @@ u32 XGetPlatform_Info(); -#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) +#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU) u32 XGetPSVersion_Info(); #endif @@ -89,3 +104,6 @@ #endif #endif /* end of protection macro */ +/** +* @} End of "addtogroup common_platform_info". +*/
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpm_counter.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xpm_counter.c similarity index 87% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpm_counter.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xpm_counter.c index 0851408..e5b231e 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpm_counter.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xpm_counter.c
@@ -44,6 +44,7 @@ * Ver Who Date Changes * ----- ---- -------- ----------------------------------------------- * 5.00 pkp 02/10/14 Initial version +* 6.2 mus 01/27/17 Updated to support IAR compiler * </pre> * ******************************************************************************/ @@ -75,14 +76,12 @@ /****************************************************************************/ /** * -* This function disables the Cortex R5 event counters. +* @brief This function disables the Cortex R5 event counters. * * @param None. * * @return None. * -* @note None. -* *****************************************************************************/ void Xpm_DisableEventCounters(void) { @@ -93,14 +92,12 @@ /****************************************************************************/ /** * -* This function enables the Cortex R5 event counters. +* @brief This function enables the Cortex R5 event counters. * * @param None. * * @return None. * -* @note None. -* *****************************************************************************/ void Xpm_EnableEventCounters(void) { @@ -111,14 +108,12 @@ /****************************************************************************/ /** * -* This function resets the Cortex R5 event counters. +* @brief This function resets the Cortex R5 event counters. * * @param None. * * @return None. * -* @note None. -* *****************************************************************************/ void Xpm_ResetEventCounters(void) { @@ -126,6 +121,8 @@ #ifdef __GNUC__ Reg = mfcp(XREG_CP15_PERF_MONITOR_CTRL); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_PERF_MONITOR_CTRL, Reg); #else { register u32 C15Reg __asm(XREG_CP15_PERF_MONITOR_CTRL); Reg = C15Reg; } @@ -137,17 +134,16 @@ /****************************************************************************/ /** * -* This function configures the Cortex R5 event counters controller, with the -* event codes, in a configuration selected by the user and enables the counters. +* @brief This function configures the Cortex R5 event counters controller, +* with the event codes, in a configuration selected by the user and +* enables the counters. * -* @param PmcrCfg is configuration value based on which the event counters -* are configured. -* Use XPM_CNTRCFG* values defined in xpm_counter.h. +* @param PmcrCfg: Configuration value based on which the event counters +* are configured.XPM_CNTRCFG* values defined in xpm_counter.h can +* be utilized for setting configuration * * @return None. * -* @note None. -* *****************************************************************************/ void Xpm_SetEvents(s32 PmcrCfg) { @@ -262,16 +258,15 @@ /****************************************************************************/ /** * -* This function disables the event counters and returns the counter values. +* @brief This function disables the event counters and returns the counter +* values. * -* @param PmCtrValue is a pointer to an array of type u32 PmCtrValue[6]. -* It is an output parameter which is used to return the PM -* counter values. +* @param PmCtrValue: Pointer to an array of type u32 PmCtrValue[6]. +* It is an output parameter which is used to return the PM +* counter values. * * @return None. * -* @note None. -* *****************************************************************************/ void Xpm_GetEventCounters(u32 *PmCtrValue) { @@ -284,6 +279,8 @@ mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter); #ifdef __GNUC__ PmCtrValue[Counter] = mfcp(XREG_CP15_PERF_MONITOR_COUNT); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_PERF_MONITOR_COUNT, PmCtrValue[Counter]); #else { register u32 Cp15Reg __asm(XREG_CP15_PERF_MONITOR_COUNT); PmCtrValue[Counter] = Cp15Reg; }
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpm_counter.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xpm_counter.h similarity index 96% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpm_counter.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xpm_counter.h index 5679d4b..b24f4ae 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpm_counter.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xpm_counter.h
@@ -34,21 +34,20 @@ * * @file xpm_counter.h * -* This header file contains APIs for configuring and controlling the Cortex-R5 -* Performance Monitor Events. -* Cortex-R5 Performance Monitor has 6 event counters which can be used to -* count a variety of events described in Coretx-R5 TRM. This file defines -* configurations, where value configures the event counters to count a -* set of events. +* @addtogroup r5_event_counter_apis Cortex R5 Event Counters Functions * -* Xpm_SetEvents can be used to set the event counters to count a set of events -* and Xpm_GetEventCounters can be used to read the counter values. +* Cortex R5 event counter functions can be utilized to configure and control +* the Cortex-R5 performance monitor events. +* Cortex-R5 Performance Monitor has 6 event counters which can be used to +* count a variety of events described in Coretx-R5 TRM. The xpm_counter.h file +* defines configurations XPM_CNTRCFGx which can be used to program the event +* counters to count a set of events. * * @note -* -* This file doesn't handle the Cortex-R5 cycle counter, as the cycle counter is +* It doesn't handle the Cortex-R5 cycle counter, as the cycle counter is * being used for time keeping. * +* @{ * <pre> * MODIFICATION HISTORY: * @@ -569,3 +568,6 @@ #endif #endif +/** +* @} End of "addtogroup r5_event_counter_apis". +*/ \ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpseudo_asm.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xpseudo_asm.h similarity index 71% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpseudo_asm.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xpseudo_asm.h index aff19d5..4d587af 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpseudo_asm.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xpseudo_asm.h
@@ -34,14 +34,28 @@ * * @file xpseudo_asm.h * -* This header file contains macros for using inline assembler code. +* @addtogroup r5_specific Cortex R5 Processor Specific Include Files * +* The xpseudo_asm.h includes xreg_cortexr5.h and xpseudo_asm_gcc.h. +* +* The xreg_cortexr5.h file contains definitions for inline assembler code. +* It provides inline definitions for Cortex R5 GPRs, SPRs,co-processor +* registers and Debug register +* +* The xpseudo_asm_gcc.h contains the definitions for the most often used +* inline assembler instructions, available as macros. These can be very +* useful for tasks such as setting or getting special purpose registers, +* synchronization,or cache manipulation. These inline assembler instructions +* can be used from drivers and user applications written in C. +* +* @{ * <pre> * MODIFICATION HISTORY: * * Ver Who Date Changes * ----- ---- -------- ----------------------------------------------- * 5.00 pkp 02/10/14 Initial version +* 6.2 mus 01/27/17 Updated to support IAR compiler * </pre> * ******************************************************************************/ @@ -49,6 +63,12 @@ #define XPSEUDO_ASM_H /* by using protection macros */ #include "xreg_cortexr5.h" +#if defined (__GNUC__) #include "xpseudo_asm_gcc.h" - +#elif defined (__ICCARM__) +#include "xpseudo_asm_iccarm.h" +#endif #endif /* XPSEUDO_ASM_H */ +/** +* @} End of "addtogroup r5_specific". +*/ \ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpseudo_asm_gcc.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xpseudo_asm_gcc.h similarity index 97% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpseudo_asm_gcc.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xpseudo_asm_gcc.h index b475c90..1b67263 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpseudo_asm_gcc.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xpseudo_asm_gcc.h
@@ -71,7 +71,7 @@ #if defined (__aarch64__) /* pseudo assembler instructions */ -#define mfcpsr() ({u32 rval; \ +#define mfcpsr() ({u32 rval = 0U; \ asm volatile("mrs %0, DAIF" : "=r" (rval));\ rval;\ }) @@ -123,7 +123,7 @@ #else /* pseudo assembler instructions */ -#define mfcpsr() ({u32 rval; \ +#define mfcpsr() ({u32 rval = 0U; \ __asm__ __volatile__(\ "mrs %0, cpsr\n"\ : "=r" (rval)\ @@ -215,7 +215,7 @@ #define mtcptlbi(reg) __asm__ __volatile__("tlbi " #reg) #define mtcpat(reg,val) __asm__ __volatile__("at " #reg ",%0" : : "r" (val)) /* CP15 operations */ -#define mfcp(reg) ({u64 rval;\ +#define mfcp(reg) ({u64 rval = 0U;\ __asm__ __volatile__("mrs %0, " #reg : "=r" (rval));\ rval;\ }) @@ -229,7 +229,7 @@ : : "r" (v)\ ); -#define mfcp(rn) ({u32 rval; \ +#define mfcp(rn) ({u32 rval = 0U; \ __asm__ __volatile__(\ "mrc " rn "\n"\ : "=r" (rval)\
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xreg_cortexr5.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xreg_cortexr5.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xreg_cortexr5.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xreg_cortexr5.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xstatus.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xstatus.h new file mode 100644 index 0000000..9937475 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xstatus.h
@@ -0,0 +1,535 @@ +/****************************************************************************** +* +* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xstatus.h +* +* @addtogroup common_status_codes Xilinx® software status codes +* +* The xstatus.h file contains the Xilinx® software status codes.These codes are +* used throughout the Xilinx device drivers. +* +* @{ +******************************************************************************/ + +#ifndef XSTATUS_H /* prevent circular inclusions */ +#define XSTATUS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" + +/************************** Constant Definitions *****************************/ + +/*********************** Common statuses 0 - 500 *****************************/ +/** +@name Common Status Codes for All Device Drivers +@{ +*/ +#define XST_SUCCESS 0L +#define XST_FAILURE 1L +#define XST_DEVICE_NOT_FOUND 2L +#define XST_DEVICE_BLOCK_NOT_FOUND 3L +#define XST_INVALID_VERSION 4L +#define XST_DEVICE_IS_STARTED 5L +#define XST_DEVICE_IS_STOPPED 6L +#define XST_FIFO_ERROR 7L /*!< An error occurred during an + operation with a FIFO such as + an underrun or overrun, this + error requires the device to + be reset */ +#define XST_RESET_ERROR 8L /*!< An error occurred which requires + the device to be reset */ +#define XST_DMA_ERROR 9L /*!< A DMA error occurred, this error + typically requires the device + using the DMA to be reset */ +#define XST_NOT_POLLED 10L /*!< The device is not configured for + polled mode operation */ +#define XST_FIFO_NO_ROOM 11L /*!< A FIFO did not have room to put + the specified data into */ +#define XST_BUFFER_TOO_SMALL 12L /*!< The buffer is not large enough + to hold the expected data */ +#define XST_NO_DATA 13L /*!< There was no data available */ +#define XST_REGISTER_ERROR 14L /*!< A register did not contain the + expected value */ +#define XST_INVALID_PARAM 15L /*!< An invalid parameter was passed + into the function */ +#define XST_NOT_SGDMA 16L /*!< The device is not configured for + scatter-gather DMA operation */ +#define XST_LOOPBACK_ERROR 17L /*!< A loopback test failed */ +#define XST_NO_CALLBACK 18L /*!< A callback has not yet been + registered */ +#define XST_NO_FEATURE 19L /*!< Device is not configured with + the requested feature */ +#define XST_NOT_INTERRUPT 20L /*!< Device is not configured for + interrupt mode operation */ +#define XST_DEVICE_BUSY 21L /*!< Device is busy */ +#define XST_ERROR_COUNT_MAX 22L /*!< The error counters of a device + have maxed out */ +#define XST_IS_STARTED 23L /*!< Used when part of device is + already started i.e. + sub channel */ +#define XST_IS_STOPPED 24L /*!< Used when part of device is + already stopped i.e. + sub channel */ +#define XST_DATA_LOST 26L /*!< Driver defined error */ +#define XST_RECV_ERROR 27L /*!< Generic receive error */ +#define XST_SEND_ERROR 28L /*!< Generic transmit error */ +#define XST_NOT_ENABLED 29L /*!< A requested service is not + available because it has not + been enabled */ +/** @} */ +/***************** Utility Component statuses 401 - 500 *********************/ +/** +@name Utility Component Status Codes 401 - 500 +@{ +*/ +#define XST_MEMTEST_FAILED 401L /*!< Memory test failed */ + +/** @} */ +/***************** Common Components statuses 501 - 1000 *********************/ +/** +@name Packet Fifo Status Codes 501 - 510 +@{ +*/ +/********************* Packet Fifo statuses 501 - 510 ************************/ + +#define XST_PFIFO_LACK_OF_DATA 501L /*!< Not enough data in FIFO */ +#define XST_PFIFO_NO_ROOM 502L /*!< Not enough room in FIFO */ +#define XST_PFIFO_BAD_REG_VALUE 503L /*!< Self test, a register value + was invalid after reset */ +#define XST_PFIFO_ERROR 504L /*!< Generic packet FIFO error */ +#define XST_PFIFO_DEADLOCK 505L /*!< Packet FIFO is reporting + * empty and full simultaneously + */ +/** @} */ +/** +@name DMA Status Codes 511 - 530 +@{ +*/ +/************************** DMA statuses 511 - 530 ***************************/ + +#define XST_DMA_TRANSFER_ERROR 511L /*!< Self test, DMA transfer + failed */ +#define XST_DMA_RESET_REGISTER_ERROR 512L /*!< Self test, a register value + was invalid after reset */ +#define XST_DMA_SG_LIST_EMPTY 513L /*!< Scatter gather list contains + no buffer descriptors ready + to be processed */ +#define XST_DMA_SG_IS_STARTED 514L /*!< Scatter gather not stopped */ +#define XST_DMA_SG_IS_STOPPED 515L /*!< Scatter gather not running */ +#define XST_DMA_SG_LIST_FULL 517L /*!< All the buffer desciptors of + the scatter gather list are + being used */ +#define XST_DMA_SG_BD_LOCKED 518L /*!< The scatter gather buffer + descriptor which is to be + copied over in the scatter + list is locked */ +#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /*!< No buffer descriptors have been + put into the scatter gather + list to be commited */ +#define XST_DMA_SG_COUNT_EXCEEDED 521L /*!< The packet count threshold + specified was larger than the + total # of buffer descriptors + in the scatter gather list */ +#define XST_DMA_SG_LIST_EXISTS 522L /*!< The scatter gather list has + already been created */ +#define XST_DMA_SG_NO_LIST 523L /*!< No scatter gather list has + been created */ +#define XST_DMA_SG_BD_NOT_COMMITTED 524L /*!< The buffer descriptor which was + being started was not committed + to the list */ +#define XST_DMA_SG_NO_DATA 525L /*!< The buffer descriptor to start + has already been used by the + hardware so it can't be reused + */ +#define XST_DMA_SG_LIST_ERROR 526L /*!< General purpose list access + error */ +#define XST_DMA_BD_ERROR 527L /*!< General buffer descriptor + error */ +/** @} */ +/** +@name IPIF Status Codes Codes 531 - 550 +@{ +*/ +/************************** IPIF statuses 531 - 550 ***************************/ + +#define XST_IPIF_REG_WIDTH_ERROR 531L /*!< An invalid register width + was passed into the function */ +#define XST_IPIF_RESET_REGISTER_ERROR 532L /*!< The value of a register at + reset was not valid */ +#define XST_IPIF_DEVICE_STATUS_ERROR 533L /*!< A write to the device interrupt + status register did not read + back correctly */ +#define XST_IPIF_DEVICE_ACK_ERROR 534L /*!< The device interrupt status + register did not reset when + acked */ +#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /*!< The device interrupt enable + register was not updated when + other registers changed */ +#define XST_IPIF_IP_STATUS_ERROR 536L /*!< A write to the IP interrupt + status register did not read + back correctly */ +#define XST_IPIF_IP_ACK_ERROR 537L /*!< The IP interrupt status register + did not reset when acked */ +#define XST_IPIF_IP_ENABLE_ERROR 538L /*!< IP interrupt enable register was + not updated correctly when other + registers changed */ +#define XST_IPIF_DEVICE_PENDING_ERROR 539L /*!< The device interrupt pending + register did not indicate the + expected value */ +#define XST_IPIF_DEVICE_ID_ERROR 540L /*!< The device interrupt ID register + did not indicate the expected + value */ +#define XST_IPIF_ERROR 541L /*!< Generic ipif error */ +/** @} */ + +/****************** Device specific statuses 1001 - 4095 *********************/ +/** +@name Ethernet Status Codes 1001 - 1050 +@{ +*/ +/********************* Ethernet statuses 1001 - 1050 *************************/ + +#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /*!< Memory space is not big enough + * to hold the minimum number of + * buffers or descriptors */ +#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /*!< Memory allocation failed */ +#define XST_EMAC_MII_READ_ERROR 1003L /*!< MII read error */ +#define XST_EMAC_MII_BUSY 1004L /*!< An MII operation is in progress */ +#define XST_EMAC_OUT_OF_BUFFERS 1005L /*!< Driver is out of buffers */ +#define XST_EMAC_PARSE_ERROR 1006L /*!< Invalid driver init string */ +#define XST_EMAC_COLLISION_ERROR 1007L /*!< Excess deferral or late + * collision on polled send */ +/** @} */ +/** +@name UART Status Codes 1051 - 1075 +@{ +*/ +/*********************** UART statuses 1051 - 1075 ***************************/ +#define XST_UART + +#define XST_UART_INIT_ERROR 1051L +#define XST_UART_START_ERROR 1052L +#define XST_UART_CONFIG_ERROR 1053L +#define XST_UART_TEST_FAIL 1054L +#define XST_UART_BAUD_ERROR 1055L +#define XST_UART_BAUD_RANGE 1056L + +/** @} */ +/** +@name IIC Status Codes 1076 - 1100 +@{ +*/ +/************************ IIC statuses 1076 - 1100 ***************************/ + +#define XST_IIC_SELFTEST_FAILED 1076 /*!< self test failed */ +#define XST_IIC_BUS_BUSY 1077 /*!< bus found busy */ +#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /*!< mastersend attempted with */ + /* general call address */ +#define XST_IIC_STAND_REG_RESET_ERROR 1079 /*!< A non parameterizable reg */ + /* value after reset not valid */ +#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /*!< Tx fifo included in design */ + /* value after reset not valid */ +#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /*!< Rx fifo included in design */ + /* value after reset not valid */ +#define XST_IIC_TBA_REG_RESET_ERROR 1082 /*!< 10 bit addr incl in design */ + /* value after reset not valid */ +#define XST_IIC_CR_READBACK_ERROR 1083 /*!< Read of the control register */ + /* didn't return value written */ +#define XST_IIC_DTR_READBACK_ERROR 1084 /*!< Read of the data Tx reg */ + /* didn't return value written */ +#define XST_IIC_DRR_READBACK_ERROR 1085 /*!< Read of the data Receive reg */ + /* didn't return value written */ +#define XST_IIC_ADR_READBACK_ERROR 1086 /*!< Read of the data Tx reg */ + /* didn't return value written */ +#define XST_IIC_TBA_READBACK_ERROR 1087 /*!< Read of the 10 bit addr reg */ + /* didn't return written value */ +#define XST_IIC_NOT_SLAVE 1088 /*!< The device isn't a slave */ +/** @} */ +/** +@name ATMC Status Codes 1101 - 1125 +@{ +*/ +/*********************** ATMC statuses 1101 - 1125 ***************************/ + +#define XST_ATMC_ERROR_COUNT_MAX 1101L /*!< the error counters in the ATM + controller hit the max value + which requires the statistics + to be cleared */ +/** @} */ +/** +@name Flash Status Codes 1126 - 1150 +@{ +*/ +/*********************** Flash statuses 1126 - 1150 **************************/ + +#define XST_FLASH_BUSY 1126L /*!< Flash is erasing or programming + */ +#define XST_FLASH_READY 1127L /*!< Flash is ready for commands */ +#define XST_FLASH_ERROR 1128L /*!< Flash had detected an internal + error. Use XFlash_DeviceControl + to retrieve device specific codes + */ +#define XST_FLASH_ERASE_SUSPENDED 1129L /*!< Flash is in suspended erase state + */ +#define XST_FLASH_WRITE_SUSPENDED 1130L /*!< Flash is in suspended write state + */ +#define XST_FLASH_PART_NOT_SUPPORTED 1131L /*!< Flash type not supported by + driver */ +#define XST_FLASH_NOT_SUPPORTED 1132L /*!< Operation not supported */ +#define XST_FLASH_TOO_MANY_REGIONS 1133L /*!< Too many erase regions */ +#define XST_FLASH_TIMEOUT_ERROR 1134L /*!< Programming or erase operation + aborted due to a timeout */ +#define XST_FLASH_ADDRESS_ERROR 1135L /*!< Accessed flash outside its + addressible range */ +#define XST_FLASH_ALIGNMENT_ERROR 1136L /*!< Write alignment error */ +#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /*!< Couldn't return immediately from + write/erase function with + XFL_NON_BLOCKING_WRITE/ERASE + option cleared */ +#define XST_FLASH_CFI_QUERY_ERROR 1138L /*!< Failed to query the device */ +/** @} */ +/** +@name SPI Status Codes 1151 - 1175 +@{ +*/ +/*********************** SPI statuses 1151 - 1175 ****************************/ + +#define XST_SPI_MODE_FAULT 1151 /*!< master was selected as slave */ +#define XST_SPI_TRANSFER_DONE 1152 /*!< data transfer is complete */ +#define XST_SPI_TRANSMIT_UNDERRUN 1153 /*!< slave underruns transmit register */ +#define XST_SPI_RECEIVE_OVERRUN 1154 /*!< device overruns receive register */ +#define XST_SPI_NO_SLAVE 1155 /*!< no slave has been selected yet */ +#define XST_SPI_TOO_MANY_SLAVES 1156 /*!< more than one slave is being + * selected */ +#define XST_SPI_NOT_MASTER 1157 /*!< operation is valid only as master */ +#define XST_SPI_SLAVE_ONLY 1158 /*!< device is configured as slave-only + */ +#define XST_SPI_SLAVE_MODE_FAULT 1159 /*!< slave was selected while disabled */ +#define XST_SPI_SLAVE_MODE 1160 /*!< device has been addressed as slave */ +#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /*!< device received data in slave mode */ + +#define XST_SPI_COMMAND_ERROR 1162 /*!< unrecognised command - qspi only */ +#define XST_SPI_POLL_DONE 1163 /*!< controller completed polling the + device for status */ +/** @} */ +/** +@name OPB Arbiter Status Codes 1176 - 1200 +@{ +*/ +/********************** OPB Arbiter statuses 1176 - 1200 *********************/ + +#define XST_OPBARB_INVALID_PRIORITY 1176 /*!< the priority registers have either + * one master assigned to two or more + * priorities, or one master not + * assigned to any priority + */ +#define XST_OPBARB_NOT_SUSPENDED 1177 /*!< an attempt was made to modify the + * priority levels without first + * suspending the use of priority + * levels + */ +#define XST_OPBARB_PARK_NOT_ENABLED 1178 /*!< bus parking by id was enabled but + * bus parking was not enabled + */ +#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /*!< the arbiter must be in fixed + * priority mode to allow the + * priorities to be changed + */ +/** @} */ +/** +@name INTC Status Codes 1201 - 1225 +@{ +*/ +/************************ Intc statuses 1201 - 1225 **************************/ + +#define XST_INTC_FAIL_SELFTEST 1201 /*!< self test failed */ +#define XST_INTC_CONNECT_ERROR 1202 /*!< interrupt already in use */ +/** @} */ +/** +@name TmrCtr Status Codes 1226 - 1250 +@{ +*/ +/********************** TmrCtr statuses 1226 - 1250 **************************/ + +#define XST_TMRCTR_TIMER_FAILED 1226 /*!< self test failed */ +/** @} */ +/** +@name WdtTb Status Codes 1251 - 1275 +@{ +*/ +/********************** WdtTb statuses 1251 - 1275 ***************************/ + +#define XST_WDTTB_TIMER_FAILED 1251L +/** @} */ +/** +@name PlbArb status Codes 1276 - 1300 +@{ +*/ +/********************** PlbArb statuses 1276 - 1300 **************************/ + +#define XST_PLBARB_FAIL_SELFTEST 1276L +/** @} */ +/** +@name Plb2Opb Status Codes 1301 - 1325 +@{ +*/ +/********************** Plb2Opb statuses 1301 - 1325 *************************/ + +#define XST_PLB2OPB_FAIL_SELFTEST 1301L +/** @} */ +/** +@name Opb2Plb Status 1326 - 1350 +@{ +*/ +/********************** Opb2Plb statuses 1326 - 1350 *************************/ + +#define XST_OPB2PLB_FAIL_SELFTEST 1326L +/** @} */ +/** +@name SysAce Status Codes 1351 - 1360 +@{ +*/ +/********************** SysAce statuses 1351 - 1360 **************************/ + +#define XST_SYSACE_NO_LOCK 1351L /*!< No MPU lock has been granted */ +/** @} */ +/** +@name PCI Bridge Status Codes 1361 - 1375 +@{ +*/ +/********************** PCI Bridge statuses 1361 - 1375 **********************/ + +#define XST_PCI_INVALID_ADDRESS 1361L +/** @} */ +/** +@name FlexRay Constants 1400 - 1409 +@{ +*/ +/********************** FlexRay constants 1400 - 1409 *************************/ + +#define XST_FR_TX_ERROR 1400 +#define XST_FR_TX_BUSY 1401 +#define XST_FR_BUF_LOCKED 1402 +#define XST_FR_NO_BUF 1403 +/** @} */ +/** +@name USB constants 1410 - 1420 +@{ +*/ +/****************** USB constants 1410 - 1420 *******************************/ + +#define XST_USB_ALREADY_CONFIGURED 1410 +#define XST_USB_BUF_ALIGN_ERROR 1411 +#define XST_USB_NO_DESC_AVAILABLE 1412 +#define XST_USB_BUF_TOO_BIG 1413 +#define XST_USB_NO_BUF 1414 +/** @} */ +/** +@name HWICAP constants 1421 - 1429 +@{ +*/ +/****************** HWICAP constants 1421 - 1429 *****************************/ + +#define XST_HWICAP_WRITE_DONE 1421 + +/** @} */ +/** +@name AXI VDMA constants 1430 - 1440 +@{ +*/ +/****************** AXI VDMA constants 1430 - 1440 *****************************/ + +#define XST_VDMA_MISMATCH_ERROR 1430 +/** @} */ +/** +@name NAND Flash Status Codes 1441 - 1459 +@{ +*/ +/*********************** NAND Flash statuses 1441 - 1459 *********************/ + +#define XST_NAND_BUSY 1441L /*!< Flash is erasing or + * programming + */ +#define XST_NAND_READY 1442L /*!< Flash is ready for commands + */ +#define XST_NAND_ERROR 1443L /*!< Flash had detected an + * internal error. + */ +#define XST_NAND_PART_NOT_SUPPORTED 1444L /*!< Flash type not supported by + * driver + */ +#define XST_NAND_OPT_NOT_SUPPORTED 1445L /*!< Operation not supported + */ +#define XST_NAND_TIMEOUT_ERROR 1446L /*!< Programming or erase + * operation aborted due to a + * timeout + */ +#define XST_NAND_ADDRESS_ERROR 1447L /*!< Accessed flash outside its + * addressible range + */ +#define XST_NAND_ALIGNMENT_ERROR 1448L /*!< Write alignment error + */ +#define XST_NAND_PARAM_PAGE_ERROR 1449L /*!< Failed to read parameter + * page of the device + */ +#define XST_NAND_CACHE_ERROR 1450L /*!< Flash page buffer error + */ + +#define XST_NAND_WRITE_PROTECTED 1451L /*!< Flash is write protected + */ +/** @} */ + +/**************************** Type Definitions *******************************/ + +typedef s32 XStatus; + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** +* @} End of "addtogroup common_status_codes". +*/
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xtime_l.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xtime_l.c similarity index 63% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xtime_l.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xtime_l.c index a9db4df..2eeb412 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xtime_l.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xtime_l.c
@@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved. +* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -54,6 +54,8 @@ * 5.04 pkp * 6.0 mus 08/11/16 Removed implementation of XTime_SetTime API, since * TTC counter value register is read only. +* 6.6 srm 10/18/17 Removed XTime_StartTimer API and made XTime_GetTime, +* XTime_SetTime applicable for all the instances of TTC * * </pre> * @@ -68,109 +70,59 @@ #include "xil_io.h" #include "xdebug.h" +#if defined SLEEP_TIMER_BASEADDR +#include "xil_sleeptimer.h" +#endif + /***************** Macros (Inline Functions) Definitions *********************/ /**************************** Type Definitions *******************************/ /************************** Constant Definitions *****************************/ -#define RST_LPD_IOU2 0xFF5E0238U -#define RST_LPD_IOU2_TTC3_RESET_MASK 0x00004000U + /************************** Variable Definitions *****************************/ /************************** Function Prototypes ******************************/ -/* Function definitions are applicable only when TTC3 is present*/ +/* Function definitions are applicable only when TTC is present*/ #ifdef SLEEP_TIMER_BASEADDR -/**************************************************************************** + +/****************************************************************************/ +/** +* @brief TTC Timer runs continuously and the time can not be set as +* desired. This API doesn't contain anything. It is defined to have +* uniformity across platforms. * -* Start the TTC timer. -* -* @param None. +* @param Xtime_Global: 32 bit value to be written to the timer counter +* register. * * @return None. * * @note In multiprocessor environment reference time will reset/lost for -* all processors, when this function called by any one processor. -* -****************************************************************************/ -void XTime_StartTimer(void) -{ - u32 LpdRst; - u32 TimerPrescalar; - u32 TimerCntrl; - - LpdRst = Xil_In32(RST_LPD_IOU2); - if ((LpdRst & RST_LPD_IOU2_TTC3_RESET_MASK) != 0 ) { - LpdRst = LpdRst & (~RST_LPD_IOU2_TTC3_RESET_MASK); - Xil_Out32(RST_LPD_IOU2, LpdRst); - - } else { - TimerCntrl = Xil_In32(SLEEP_TIMER_BASEADDR + - SLEEP_TIMER_CNTR_CNTRL_OFFSET); - /* check if Timer is disabled */ - if ((TimerCntrl & SLEEP_TIMER_COUNTER_CONTROL_DIS_MASK) == 0) { - TimerPrescalar = Xil_In32(SLEEP_TIMER_BASEADDR + - SLEEP_TIMER_CLK_CNTRL_OFFSET); - - /* check if Timer is configured with proper functionalty for sleep */ - if ((TimerPrescalar & SLEEP_TIMER_CLOCK_CONTROL_PS_EN_MASK) == 0) - return; - } - } - /* Disable the timer to configure */ - TimerCntrl = Xil_In32(SLEEP_TIMER_BASEADDR + - SLEEP_TIMER_CNTR_CNTRL_OFFSET); - TimerCntrl = TimerCntrl | SLEEP_TIMER_COUNTER_CONTROL_DIS_MASK; - Xil_Out32(SLEEP_TIMER_BASEADDR + SLEEP_TIMER_CNTR_CNTRL_OFFSET, - TimerCntrl); - - /* Disable the prescalar */ - TimerPrescalar = Xil_In32(SLEEP_TIMER_BASEADDR + - SLEEP_TIMER_CLK_CNTRL_OFFSET); - TimerPrescalar = TimerPrescalar & (~SLEEP_TIMER_CLOCK_CONTROL_PS_EN_MASK); - Xil_Out32(SLEEP_TIMER_BASEADDR + SLEEP_TIMER_CLK_CNTRL_OFFSET, - TimerPrescalar); - - /* Enable the Timer */ - TimerCntrl = SLEEP_TIMER_COUNTER_CONTROL_RST_MASK & - (~SLEEP_TIMER_COUNTER_CONTROL_DIS_MASK); - Xil_Out32(SLEEP_TIMER_BASEADDR + SLEEP_TIMER_CNTR_CNTRL_OFFSET, - TimerCntrl); - -} -/**************************************************************************** -* -* Set the time in the Timer Counter Register. -* -* @param Value to be written to the Timer Counter Register. -* -* @return None. -* -* @note In multiprocessor environment reference time will reset/lost for -* all processors, when this function called by any one processor. +* all processors, when this function called by any one processor. * ****************************************************************************/ void XTime_SetTime(XTime Xtime_Global) { + (void) Xtime_Global; /*Timer cannot be set to desired value, so the API is left unimplemented*/ xdbg_printf(XDBG_DEBUG_GENERAL, "XTime_SetTime:Timer cannot be set to desired value,so API is not implemented\n"); } -/**************************************************************************** +/****************************************************************************/ +/** +* @brief Get the time from the timer counter register. * -* Get the time from the Timer Counter Register. -* -* @param Pointer to the location to be updated with the time. +* @param Xtime_Global: Pointer to the 32 bit location to be updated with +* the time current value of timer counter register. * * @return None. * -* @note None. -* ****************************************************************************/ void XTime_GetTime(XTime *Xtime_Global) { *Xtime_Global = Xil_In32(SLEEP_TIMER_BASEADDR + - SLEEP_TIMER_CNTR_VAL_OFFSET); + XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET); } #endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xtime_l.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xtime_l.h similarity index 84% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xtime_l.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xtime_l.h index 36c416d..4974664 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xtime_l.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xtime_l.h
@@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,6 +33,11 @@ /** * @file xtime_l.h * +* @addtogroup r5_time_apis Cortex R5 Time Functions +* The xtime_l.h provides access to 32-bit TTC timer counter. These functions +* can be used by applications to track the time. +* +* @{ * <pre> * MODIFICATION HISTORY: * @@ -42,10 +47,10 @@ * 5.04 pkp 02/19/16 Added timer configuration register offset definitions * 5.04 pkp 03/11/16 Removed definitions for overflow interrupt register * and mask +* 6.6 srm 10/22/17 Added a warning message for the user configurable sleep +* implementation when default timer is selected by the user * </pre> * -* @note None. -* ******************************************************************************/ #ifndef XTIME_H /* prevent circular inclusions */ @@ -67,21 +72,16 @@ #define COUNTS_PER_SECOND SLEEP_TIMER_FREQUENCY #define COUNTS_PER_USECOND COUNTS_PER_SECOND/1000000 -/* Timer Register Offset*/ -#define SLEEP_TIMER_CLK_CNTRL_OFFSET 0x00000000U -#define SLEEP_TIMER_CNTR_CNTRL_OFFSET 0x0000000CU -#define SLEEP_TIMER_CNTR_VAL_OFFSET 0x00000018U - -/*Timer register values*/ -#define SLEEP_TIMER_COUNTER_CONTROL_DIS_MASK 0x00000001U -#define SLEEP_TIMER_CLOCK_CONTROL_PS_EN_MASK 0x00000001U -#define SLEEP_TIMER_COUNTER_CONTROL_RST_MASK 0x00000010U #else #define ITERS_PER_SEC (XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ / 4) #define ITERS_PER_USEC (XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ / 4000000) #define IRQ_FIQ_MASK 0xC0 /* Mask IRQ and FIQ interrupts in cpsr */ #endif +#if defined (XSLEEP_TIMER_IS_DEFAULT_TIMER) +#pragma message ("For the sleep routines, TTC3 is used if present else the assembly instructions are called") +#endif + /**************************** Type Definitions *******************************/ /* The following definitions are applicable only when TTC3 is present*/ @@ -97,3 +97,6 @@ #endif /* __cplusplus */ #endif /* XTIME_H */ +/** +* @} End of "@addtogroup r5_time_apis". +*/
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/Makefile rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/Makefile
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu.c similarity index 95% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu.c index b047a45..4c2545c 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu.c
@@ -18,8 +18,8 @@ * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. @@ -61,6 +61,9 @@ * XSysMonPsu_SetSeqAcqTime * and XSysMonPsu_GetSeqAcqTime to provide support for * set/get 64 bit value. +* 2.1 sk 03/03/16 Check for PL reset before doing PL Sysmon reset. +* 2.3 mn 12/13/17 Correct the AMS block channel numbers +* mn 03/08/18 Update Clock Divisor to the proper value * * </pre> * @@ -109,6 +112,7 @@ { u32 PsSysmonControlStatus; u32 PlSysmonControlStatus; + u32 IntrStatus; /* Assert the input arguments. */ Xil_AssertNonvoid(InstancePtr != NULL); @@ -117,11 +121,14 @@ /* Set the values read from the device config and the base address. */ InstancePtr->Config.DeviceId = ConfigPtr->DeviceId; InstancePtr->Config.BaseAddress = EffectiveAddr; - + InstancePtr->Config.InputClockMHz = ConfigPtr->InputClockMHz; /* Set all handlers to stub values, let user configure this data later. */ InstancePtr->Handler = XSysMonPsu_StubHandler; + XSysMonPsu_UpdateAdcClkDivisor(InstancePtr, XSYSMON_PS); + XSysMonPsu_UpdateAdcClkDivisor(InstancePtr, XSYSMON_PL); + /* Reset the device such that it is in a known state. */ XSysMonPsu_Reset(InstancePtr); @@ -147,6 +154,10 @@ /* Indicate the instance is now ready to use, initialized without error */ InstancePtr->IsReady = XIL_COMPONENT_IS_READY; + /* Clear any bits set in the Interrupt Status Register. */ + IntrStatus = XSysMonPsu_IntrGetStatus(InstancePtr); + XSysMonPsu_IntrClear(InstancePtr, IntrStatus); + return XST_SUCCESS; } @@ -166,7 +177,7 @@ *****************************************************************************/ static void XSysMonPsu_StubHandler(void *CallBackRef) { - (void *) CallBackRef; + (void) CallBackRef; /* Assert occurs always since this is a stub and should never be called */ Xil_AssertVoidAlways(); @@ -189,6 +200,7 @@ ******************************************************************************/ void XSysMonPsu_Reset(XSysMonPsu *InstancePtr) { + u8 IsPlReset; /* Assert the arguments. */ Xil_AssertVoid(InstancePtr != NULL); @@ -196,9 +208,14 @@ XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress + XPS_BA_OFFSET + XSYSMONPSU_VP_VN_OFFSET, XSYSMONPSU_VP_VN_MASK); - /* RESET the PL SYSMON */ - XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress + XPL_BA_OFFSET + - XSYSMONPSU_VP_VN_OFFSET, XSYSMONPSU_VP_VN_MASK); + /* Check for PL is under reset or not */ + IsPlReset = (XSysmonPsu_ReadReg(CSU_BASEADDR + PCAP_STATUS_OFFSET) & + PL_CFG_RESET_MASK) >> PL_CFG_RESET_SHIFT; + if (IsPlReset != 0U) { + /* RESET the PL SYSMON */ + XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress + XPL_BA_OFFSET + + XSYSMONPSU_VP_VN_OFFSET, XSYSMONPSU_VP_VN_MASK); + } } @@ -576,7 +593,9 @@ ((Channel >= XSM_CH_SUPPLY_CALIB) && (Channel <= XSM_CH_GAINERR_CALIB)) || ((Channel >= XSM_CH_SUPPLY4) && - (Channel <= XSM_CH_TEMP_REMTE))); + (Channel <= XSM_CH_TEMP_REMTE)) || + ((Channel >= XSM_CH_VCC_PSLL0) && + (Channel <= XSM_CH_RESERVE1))); Xil_AssertNonvoid((IncreaseAcqCycles == TRUE) || (IncreaseAcqCycles == FALSE)); Xil_AssertNonvoid((IsEventMode == TRUE) || (IsEventMode == FALSE)); @@ -1163,6 +1182,60 @@ return (u8) (Divisor >> XSYSMONPSU_CFG_REG2_CLK_DVDR_SHIFT); } +u8 XSysMonPsu_UpdateAdcClkDivisor(XSysMonPsu *InstancePtr, u32 SysmonBlk) +{ + u16 Divisor; + u32 EffectiveBaseAddress; + u32 RegValue; + u32 InputFreq = InstancePtr->Config.InputClockMHz; + + /* Assert the arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL)); + + /* Calculate the effective baseaddress based on the Sysmon instance. */ + EffectiveBaseAddress = + XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress, + SysmonBlk); + + /* Read the divisor value from the Configuration Register 2. */ + Divisor = (u16) XSysmonPsu_ReadReg(EffectiveBaseAddress + + XSYSMONPSU_CFG_REG2_OFFSET); + Divisor = Divisor >> XSYSMONPSU_CFG_REG2_CLK_DVDR_SHIFT; + + while (1) { + if (!Divisor) { + if ((SysmonBlk == XSYSMON_PS) && + (InputFreq/8 >= 1) && (InputFreq/8 <= 26)) { + break; + } else if ((SysmonBlk == XSYSMON_PL) && + (InputFreq/2 >= 1) && (InputFreq/2 <= 26)) { + break; + } + } else if ((InputFreq/Divisor >= 1) && + (InputFreq/Divisor <= 26)) { + break; + } else { + Divisor += 1; + } + } + + /* + * Read the Configuration Register 2 and the clear the clock divisor + * bits. + */ + RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress + + XSYSMONPSU_CFG_REG2_OFFSET); + RegValue &= ~(XSYSMONPSU_CFG_REG2_CLK_DVDR_MASK); + + /* Write the divisor value into the Configuration Register 2. */ + RegValue |= ((u32)Divisor << XSYSMONPSU_CFG_REG2_CLK_DVDR_SHIFT) & + XSYSMONPSU_CFG_REG2_CLK_DVDR_MASK; + XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_CFG_REG2_OFFSET, + RegValue); + + return (u8)Divisor; +} /****************************************************************************/ /** *
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu.h similarity index 86% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu.h index ba090c5..8fcaa19 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu.h
@@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2016 Xilinx, Inc. All rights reserved. +* Copyright (C) 2016-2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -18,8 +18,8 @@ * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. @@ -163,6 +163,21 @@ * set/get 64 bit value. * Added constants XSM_CFR_ALM_SUPPLY*(8-31)_MASKs to * provide support for enabling extra PS alarams. +* 2.1 sk 03/03/16 Check for PL reset before doing PL Sysmon reset. +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* ms 04/05/17 Modified Comment lines in functions of sysmonpsu +* examples to recognize it as documentation block +* for doxygen generation. +* 2.2 sk 04/14/17 Corrected temperature conversion formulas. +* 2.3 mn 12/11/17 Added missing closing bracket error when C++ is used +* mn 12/12/17 Added Conversion Support for voltages having Range of +* 1 Volt +* mn 12/13/17 Correct the AMS block channel numbers +* ms 12/15/17 Added peripheral test support. +* ms 01/04/18 Provided conditional checks for interrupt example +* in sysmonpsu_header.h +* mn 03/08/18 Update Clock Divisor to the proper value * * </pre> * @@ -211,22 +226,14 @@ #define XSM_CH_SUPPLY10 35U /**< SUPPLY10 PS_MGTRAVTT */ #define XSM_CH_VCCAMS 36U /**< VCCAMS */ #define XSM_CH_TEMP_REMTE 37U /**< Temperature Remote */ -#define XSM_CH_VCC_PSLL0 38U /**< VCC_PSLL0 */ -#define XSM_CH_VCC_PSLL1 39U /**< VCC_PSLL1 */ -#define XSM_CH_VCC_PSLL2 40U /**< VCC_PSLL2 */ -#define XSM_CH_VCC_PSLL3 41U /**< VCC_PSLL3 */ -#define XSM_CH_VCC_PSLL4 42U /**< VCC_PSLL4 */ -#define XSM_CH_VCC_PSBATT 43U /**< VCC_PSBATT */ -#define XSM_CH_VCCINT 44U /**< VCCINT */ -#define XSM_CH_VCCBRAM 45U /**< VCCBRAM */ -#define XSM_CH_VCCAUX 46U /**< VCCAUX */ -#define XSM_CH_VCC_PSDDRPLL 47U /**< VCC_PSDDRPLL */ -#define XSM_CH_DDRPHY_VREF 48U /**< DDRPHY_VREF */ -#define XSM_CH_DDRPHY_AT0 49U /**< DDRPHY_AT0 */ -#define XSM_CH_PSGT_AT0 50U /**< PSGT_AT0 */ -#define XSM_CH_PSGT_AT1 51U /**< PSGT_AT0 */ -#define XSM_CH_RESERVE0 52U /**< PSGT_AT0 */ -#define XSM_CH_RESERVE1 53U /**< PSGT_AT0 */ +#define XSM_CH_VCC_PSLL0 48U /**< VCC_PSLL0 */ +#define XSM_CH_VCC_PSLL3 51U /**< VCC_PSLL3 */ +#define XSM_CH_VCCINT 54U /**< VCCINT */ +#define XSM_CH_VCCBRAM 55U /**< VCCBRAM */ +#define XSM_CH_VCCAUX 56U /**< VCCAUX */ +#define XSM_CH_VCC_PSDDRPLL 57U /**< VCC_PSDDRPLL */ +#define XSM_CH_DDRPHY_VREF 58U /**< DDRPHY_VREF */ +#define XSM_CH_RESERVE1 63U /**< PSGT_AT0 */ /*@}*/ @@ -381,7 +388,8 @@ */ typedef struct { u16 DeviceId; /**< Unique ID of device */ - u32 BaseAddress; /**< Register base address */ + u32 BaseAddress; /**< Register base address */ + u16 InputClockMHz; /**< Input clock frequency */ } XSysMonPsu_Config; /** @@ -425,7 +433,7 @@ * *****************************************************************************/ #define XSysMonPsu_RawToTemperature_OnChip(AdcData) \ - ((((float)(AdcData)/65536.0f)/0.00199451786f ) - 273.6777f) + ((((float)(AdcData)/65536.0f)/0.00196342531f ) - 280.2309f) /****************************************************************************/ /** @@ -442,12 +450,30 @@ * *****************************************************************************/ #define XSysMonPsu_RawToTemperature_ExternalRef(AdcData) \ - ((((float)(AdcData)/65536.0f)/0.00198842814f ) - 273.8195f) + ((((float)(AdcData)/65536.0f)/0.00197008621f ) - 279.4266f) /****************************************************************************/ /** * -* This macro converts System Monitor Raw Data to Voltage(volts). +* This macro converts System Monitor Raw Data to Voltage(volts) for VpVn +* supply. +* +* @param AdcData is the System Monitor ADC Raw Data. +* +* @return The Voltage in volts. +* +* @note C-Style signature: +* float XSysMon_VpVnRawToVoltage(u32 AdcData) +* +*****************************************************************************/ +#define XSysMonPsu_VpVnRawToVoltage(AdcData) \ + ((((float)(AdcData))* (1.0f))/65536.0f) + +/****************************************************************************/ +/** +* +* This macro converts System Monitor Raw Data to Voltage(volts) other than +* VCCO_PSIO supply. * * @param AdcData is the System Monitor ADC Raw Data. * @@ -463,6 +489,23 @@ /****************************************************************************/ /** * +* This macro converts System Monitor Raw Data to Voltage(volts) for +* VCCO_PSIO supply. +* +* @param AdcData is the System Monitor ADC Raw Data. +* +* @return The Voltage in volts. +* +* @note C-Style signature: +* float XSysMon_RawToVoltage(u32 AdcData) +* +*****************************************************************************/ +#define XSysMonPsu_VccopsioRawToVoltage(AdcData) \ + ((((float)(AdcData))* (6.0f))/65536.0f) + +/****************************************************************************/ +/** +* * This macro converts Temperature in centigrades to System Monitor Raw Data * for On-Chip Sensors. * @@ -476,7 +519,7 @@ * *****************************************************************************/ #define XSysMonPsu_TemperatureToRaw_OnChip(Temperature) \ - ((s32)(((Temperature) + 273.6777f)*65536.0f*0.00199451786f)) + ((s32)(((Temperature) + 280.2309f)*65536.0f*0.00196342531f)) /****************************************************************************/ /** @@ -494,12 +537,13 @@ * *****************************************************************************/ #define XSysMonPsu_TemperatureToRaw_ExternalRef(Temperature) \ - ((s32)(((Temperature) + 273.8195f)*65536.0f*0.00198842814f)) + ((s32)(((Temperature) + 279.4266f)*65536.0f*0.00197008621f)) /****************************************************************************/ /** * -* This macro converts Voltage in Volts to System Monitor Raw Data. +* This macro converts Voltage in Volts to System Monitor Raw Data other than +* VCCO_PSIO supply * * @param Voltage is the Voltage in volts to be converted to * System Monitor/ADC Raw Data. @@ -516,6 +560,24 @@ /****************************************************************************/ /** * +* This macro converts Voltage in Volts to System Monitor Raw Data for +* VCCO_PSIO supply +* +* @param Voltage is the Voltage in volts to be converted to +* System Monitor/ADC Raw Data. +* +* @return The System Monitor ADC Raw Data. +* +* @note C-Style signature: +* int XSysMon_VoltageToRaw(float Voltage) +* +*****************************************************************************/ +#define XSysMonPsu_VccopsioVoltageToRaw(Voltage) \ + ((s32)((Voltage)*65536.0f/6.0f)) + +/****************************************************************************/ +/** +* * This static inline macro calculates the effective baseaddress based on the * Sysmon instance. For PS Sysmon, use additional offset XPS_BA_OFFSET and For * PL Sysmon, use additional offset XPL_BA_OFFSET. @@ -574,6 +636,7 @@ u32 XSysMonPsu_GetExtenalMux(XSysMonPsu *InstancePtr, u32 SysmonBlk); void XSysMonPsu_SetAdcClkDivisor(XSysMonPsu *InstancePtr, u8 Divisor, u32 SysmonBlk); u8 XSysMonPsu_GetAdcClkDivisor(XSysMonPsu *InstancePtr, u32 SysmonBlk); +u8 XSysMonPsu_UpdateAdcClkDivisor(XSysMonPsu *InstancePtr, u32 SysmonBlk); s32 XSysMonPsu_SetSeqChEnables(XSysMonPsu *InstancePtr, u64 ChEnableMask, u32 SysmonBlk); u64 XSysMonPsu_GetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk); @@ -607,4 +670,8 @@ XSysMonPsu_Config *XSysMonPsu_LookupConfig(u16 DeviceId); +#ifdef __cplusplus +} +#endif + #endif /* XSYSMONPSU_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_g.c similarity index 90% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_g.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_g.c index b692531..34bd80b 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_g.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_g.c
@@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,11 +44,12 @@ * The configuration table for devices */ -XSysMonPsu_Config XSysMonPsu_ConfigTable[] = +XSysMonPsu_Config XSysMonPsu_ConfigTable[XPAR_XSYSMONPSU_NUM_INSTANCES] = { { XPAR_PSU_AMS_DEVICE_ID, - XPAR_PSU_AMS_BASEADDR + XPAR_PSU_AMS_BASEADDR, + XPAR_PSU_AMS_REF_FREQMHZ } };
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_hw.h similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_hw.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_hw.h index 80266eb..2008277 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_hw.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_hw.h
@@ -18,8 +18,8 @@ * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. @@ -46,6 +46,7 @@ * 1.0 kvn 12/15/15 First release * 2.0 vns 08/14/16 Added CFG_REG3, SEQ_INPUT_MODE2, SEQ_ACQ2, * SEQ_CH2 and SEQ_AVG2 offsets and bit masks +* 2.1 sk 03/03/16 Check for PL reset before doing PL Sysmon reset. * * </pre> * @@ -2281,6 +2282,11 @@ #define XSYSMONPSU_MIN_TEMP_REMTE_WIDTH 16U #define XSYSMONPSU_MIN_TEMP_REMTE_MASK 0x0000ffffU +#define CSU_BASEADDR 0xFFCA0000U +#define PCAP_STATUS_OFFSET 0x00003010U +#define PL_CFG_RESET_MASK 0x00000040U +#define PL_CFG_RESET_SHIFT 6U + /***************** Macros (Inline Functions) Definitions *********************/ /****************************************************************************/
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_intr.c similarity index 98% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_intr.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_intr.c index b178c2e..12d9219 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_intr.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_intr.c
@@ -18,8 +18,8 @@ * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE.
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_selftest.c similarity index 97% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_selftest.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_selftest.c index 5b709be..9b68b88 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_selftest.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_selftest.c
@@ -18,8 +18,8 @@ * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE.
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_sinit.c similarity index 97% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_sinit.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_sinit.c index 34249a2..32e17ab 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_sinit.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_sinit.c
@@ -18,8 +18,8 @@ * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE.
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/Makefile rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/Makefile
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/xttcps.c similarity index 95% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/xttcps.c index 3942628..b2382f1 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/xttcps.c
@@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ /** * * @file xttcps.c -* @addtogroup ttcps_v3_0 +* @addtogroup ttcps_v3_5 * @{ * * This file contains the implementation of the XTtcPs driver. This driver @@ -52,7 +52,10 @@ * to stop the timer before configuring * 3.2 mus 10/28/16 Modified XTtcPs_CalcIntervalFromFreq to calculate * 32 bit interval count for zynq ultrascale+mpsoc -* +* 3.5 srm 10/06/17 Updated XTtcPs_GetMatchValue and XTtcPs_SetMatchValue +* APIs to use correct match register width for zynq +* (i.e. 16 bit) and zynq ultrascale+mpsoc (i.e. 32 bit). +* It fixes CR# 986617 * </pre> * ******************************************************************************/ @@ -196,7 +199,7 @@ * @note None * ****************************************************************************/ -void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, u16 Value) +void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, XMatchRegValue Value) { /* * Assert to validate input arguments. @@ -222,12 +225,12 @@ * @param MatchIndex is the index to the match register to be set. * Valid values are 0, 1, or 2. * -* @return None +* @return The match register value * * @note None * ****************************************************************************/ -u16 XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex) +XMatchRegValue XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex) { u32 MatchReg; @@ -241,7 +244,7 @@ MatchReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress, XTtcPs_Match_N_Offset(MatchIndex)); - return (u16) MatchReg; + return (XMatchRegValue) MatchReg; } /*****************************************************************************/
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/xttcps.h similarity index 93% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/xttcps.h index be266d9..b7b4e19 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/xttcps.h
@@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ /** * * @file xttcps.h -* @addtogroup ttcps_v3_0 +* @addtogroup ttcps_v3_5 * @{ * @details * @@ -93,6 +93,16 @@ * modified for MISRA-C:2012 compliance. * 3.2 mus 10/28/16 Modified XTtcPs_GetCounterValue and XTtcPs_SetInterval * macros to return 32 bit values for zynq ultrascale+mpsoc +* ms 01/23/17 Modified xil_printf statement in main function for all +* examples to ensure that "Successfully ran" and "Failed" +* strings are available in all examples. This is a fix +* for CR-965028. +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* 3.4 ms 04/18/17 Modified tcl file to add suffix U for all macros +* definitions of ttcps in xparameters.h +* 3.5 srm 10/06/17 Added new typedef XMatchRegValue for match register width +* * </pre> * ******************************************************************************/ @@ -110,12 +120,7 @@ #include "xstatus.h" /************************** Constant Definitions *****************************/ -/* - * Flag for a9 processor - */ - #if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32) - #define ARMA9 - #endif + /* * Maximum Value for interval counter @@ -165,12 +170,14 @@ } XTtcPs; /** - * This typedef contains interval count + * This typedef contains interval count and Match register value */ #if defined(ARMA9) typedef u16 XInterval; +typedef u16 XMatchRegValue; #else typedef u32 XInterval; +typedef u32 XMatchRegValue; #endif /***************** Macros (Inline Functions) Definitions *********************/ @@ -279,7 +286,7 @@ * @return None * * @note C-style signature: -* void XTtcPs_SetInterval(XTtcPs *InstancePtr, u16 Value) +* void XTtcPs_SetInterval(XTtcPs *InstancePtr, XInterval Value) * ****************************************************************************/ #define XTtcPs_SetInterval(InstancePtr, Value) \ @@ -432,8 +439,8 @@ s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr, XTtcPs_Config * ConfigPtr, u32 EffectiveAddr); -void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, u16 Value); -u16 XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex); +void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, XMatchRegValue Value); +XMatchRegValue XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex); void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue); u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr);
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/xttcps_g.c similarity index 97% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_g.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/xttcps_g.c index 28d3560..571cb36 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_g.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/xttcps_g.c
@@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/xttcps_hw.h similarity index 90% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_hw.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/xttcps_hw.h index af78bcd..b1fa545 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_hw.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/xttcps_hw.h
@@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ /** * * @file xttcps_hw.h -* @addtogroup ttcps_v3_0 +* @addtogroup ttcps_v3_5 * @{ * * This file defines the hardware interface to one of the three timer counters @@ -47,7 +47,10 @@ * ----- ------ -------- ------------------------------------------------- * 1.00a drg/jz 01/21/10 First release * 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. -* +* 3.5 srm 10/06/17 Updated XTTCPS_COUNT_VALUE_MASK, +* XTTCPS_INTERVAL_VAL_MASK, XTTCPS_MATCH_MASK macros to +* mask 16 bit values for zynq and 32 bit values for +* zynq ultrascale+mpsoc " * </pre> * ******************************************************************************/ @@ -66,6 +69,12 @@ #include "xil_io.h" /************************** Constant Definitions *****************************/ +/* + * Flag for a9 processor + */ + #if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32) + #define ARMA9 + #endif /** @name Register Map * @@ -114,7 +123,11 @@ * Current Counter Value Register definitions * @{ */ +#if defined(ARMA9) #define XTTCPS_COUNT_VALUE_MASK 0x0000FFFFU /**< 16-bit counter value */ +#else +#define XTTCPS_COUNT_VALUE_MASK 0xFFFFFFFFU /**< 32-bit counter value */ +#endif /* @} */ /** @name Interval Value Register @@ -122,7 +135,11 @@ * down to. * @{ */ +#if defined(ARMA9) #define XTTCPS_INTERVAL_VAL_MASK 0x0000FFFFU /**< 16-bit Interval value*/ +#else +#define XTTCPS_INTERVAL_VAL_MASK 0xFFFFFFFFU /**< 32-bit Interval value*/ +#endif /* @} */ /** @name Match Registers @@ -130,7 +147,11 @@ * registers. * @{ */ +#if defined(ARMA9) #define XTTCPS_MATCH_MASK 0x0000FFFFU /**< 16-bit Match value */ +#else +#define XTTCPS_MATCH_MASK 0xFFFFFFFFU /**< 32-bit Match value */ +#endif #define XTTCPS_NUM_MATCH_REG 3U /**< Num of Match reg */ /* @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_options.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/xttcps_options.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_options.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/xttcps_options.c index 532b235..01dd9ef 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_options.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/xttcps_options.c
@@ -33,7 +33,7 @@ /** * * @file xttcps_options.c -* @addtogroup ttcps_v3_0 +* @addtogroup ttcps_v3_5 * @{ * * This file contains functions to get or set option features for the device.
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/xttcps_selftest.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_selftest.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/xttcps_selftest.c index 4923df6..b1dd7d0 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_selftest.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/xttcps_selftest.c
@@ -33,7 +33,7 @@ /** * * @file xttcps_selftest.c -* @addtogroup ttcps_v3_0 +* @addtogroup ttcps_v3_5 * @{ * * This file contains the implementation of self test function for the
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/xttcps_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_sinit.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/xttcps_sinit.c index ef3c6ea..4684c8a 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_sinit.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/xttcps_sinit.c
@@ -33,7 +33,7 @@ /** * * @file xttcps_sinit.c -* @addtogroup ttcps_v3_0 +* @addtogroup ttcps_v3_5 * @{ * * The implementation of the XTtcPs driver's static initialization functionality.
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/Makefile rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/Makefile
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps.c similarity index 98% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps.c index a338d1f..c33ec54 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps.c
@@ -33,7 +33,7 @@ /** * * @file xuartps.c -* @addtogroup uartps_v3_1 +* @addtogroup uartps_v3_5 * @{ * * This file contains the implementation of the interface functions for XUartPs @@ -49,6 +49,7 @@ * baud rate. CR# 804281. * 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. * 3.1 kvn 04/10/15 Modified code for latest RTL changes. +* 3.5 NK 09/26/17 Fix the RX Buffer Overflow issue. * </pre> * *****************************************************************************/ @@ -463,7 +464,7 @@ * Loop until there is no more data in RX FIFO or the specified * number of bytes has been received */ - while((ReceivedCount <= InstancePtr->ReceiveBuffer.RemainingBytes)&& + while((ReceivedCount < InstancePtr->ReceiveBuffer.RemainingBytes)&& (((CsrRegister & XUARTPS_SR_RXEMPTY) == (u32)0))){ if (InstancePtr->is_rxbs_error) { @@ -635,7 +636,7 @@ static void XUartPs_StubHandler(void *CallBackRef, u32 Event, u32 ByteCount) { - (void *) CallBackRef; + (void) CallBackRef; (void) Event; (void) ByteCount; /* Assert occurs always since this is a stub and should never be called */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps.h similarity index 96% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps.h index d915917..33758c2 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps.h
@@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ /** * * @file xuartps.h -* @addtogroup uartps_v3_1 +* @addtogroup uartps_v3_5 * @{ * @details * @@ -162,6 +162,14 @@ * 3.1 adk 14/03/16 Include interrupt examples in the peripheral test when * uart is connected to a valid interrupt controller CR#946803. * 3.2 rk 07/20/16 Modified the logic for transmission break bit set +* 3.4 ms 01/23/17 Added xil_printf statement in main function for all +* examples to ensure that "Successfully ran" and "Failed" +* strings are available in all examples. This is a fix +* for CR-965028. +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* 3.6 ms 02/16/18 Updates the flow control mode offset value in modem +* control register. * * </pre> *
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps_g.c similarity index 93% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_g.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps_g.c index d4a8e5a..6abb20e 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_g.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps_g.c
@@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,7 +44,7 @@ * The configuration table for devices */ -XUartPs_Config XUartPs_ConfigTable[] = +XUartPs_Config XUartPs_ConfigTable[XPAR_XUARTPS_NUM_INSTANCES] = { { XPAR_PSU_UART_0_DEVICE_ID,
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_hw.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps_hw.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_hw.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps_hw.c index 299dd35..724c3cb 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_hw.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps_hw.c
@@ -33,7 +33,7 @@ /** * * @file xuartps_hw.c -* @addtogroup uartps_v3_1 +* @addtogroup uartps_v3_5 * @{ * *
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps_hw.h similarity index 98% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_hw.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps_hw.h index 9f5f0b7..9a2bc43 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_hw.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps_hw.h
@@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ /** * * @file xuartps_hw.h -* @addtogroup uartps_v3_1 +* @addtogroup uartps_v3_5 * @{ * * This header file contains the hardware interface of an XUartPs device. @@ -55,6 +55,8 @@ * constant definitions. * 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. * 3.1 kvn 04/10/15 Modified code for latest RTL changes. +* 3.6 ms 02/16/18 Updates flow control mode offset value in +* modem control register. * * </pre> * @@ -256,7 +258,7 @@ * * @{ */ -#define XUARTPS_MODEMCR_FCM 0x00000010U /**< Flow control mode */ +#define XUARTPS_MODEMCR_FCM 0x00000020U /**< Flow control mode */ #define XUARTPS_MODEMCR_RTS 0x00000002U /**< Request to send */ #define XUARTPS_MODEMCR_DTR 0x00000001U /**< Data terminal ready */ /* @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps_intr.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_intr.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps_intr.c index 3068ee7..dff02fd 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_intr.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps_intr.c
@@ -33,7 +33,7 @@ /** * * @file xuartps_intr.c -* @addtogroup uartps_v3_1 +* @addtogroup uartps_v3_5 * @{ * * This file contains the functions for interrupt handling
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_options.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps_options.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_options.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps_options.c index 9a699af..5d8d301 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_options.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps_options.c
@@ -33,7 +33,7 @@ /** * * @file xuartps_options.c -* @addtogroup uartps_v3_1 +* @addtogroup uartps_v3_5 * @{ * * The implementation of the options functions for the XUartPs driver.
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps_selftest.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_selftest.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps_selftest.c index a1a7dd3..de58201 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_selftest.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps_selftest.c
@@ -33,7 +33,7 @@ /** * * @file xuartps_selftest.c -* @addtogroup uartps_v3_1 +* @addtogroup uartps_v3_5 * @{ * * This file contains the self-test functions for the XUartPs driver.
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_sinit.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps_sinit.c index 8dc87da..22e2f7a 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_sinit.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps_sinit.c
@@ -33,7 +33,7 @@ /** * * @file xuartps_sinit.c -* @addtogroup uartps_v3_1 +* @addtogroup uartps_v3_5 * @{ * * The implementation of the XUartPs driver's static initialzation
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/Makefile rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/Makefile
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusb_wrapper.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusb_wrapper.c new file mode 100644 index 0000000..57f859d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusb_wrapper.c
@@ -0,0 +1,329 @@ +/****************************************************************************** + * + * Copyright (C) 2017 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * + ******************************************************************************/ +/*****************************************************************************/ +/** + * + * @file xusb_wrapper.c + * + * This file contains implementation of USBPSU Driver wrappers. + * + * <pre> + * MODIFICATION HISTORY: + * + * Ver Who Date Changes + * ----- ---- -------- ------------------------------------------------------- + * 1.0 BK 12/01/18 First release + * MYK 12/01/18 Added hibernation support for device mode + * vak 13/03/18 Moved the setup interrupt system calls from driver to + * example. + * + * </pre> + * + *****************************************************************************/ + +/***************************** Include Files *********************************/ +#include "xusb_wrapper.h" + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ +Usb_Config* LookupConfig(u16 DeviceId) +{ + return XUsbPsu_LookupConfig(DeviceId); +} + +void CacheInit(void) +{ + +} + +s32 CfgInitialize(struct Usb_DevData *InstancePtr, + Usb_Config *ConfigPtr, u32 BaseAddress) +{ + PrivateData.AppData = InstancePtr; + InstancePtr->PrivateData = (void *)&PrivateData; + + return XUsbPsu_CfgInitialize((struct XUsbPsu *)InstancePtr->PrivateData, + ConfigPtr, BaseAddress); +} + +void Set_Ch9Handler( + void *InstancePtr, + void (*func)(struct Usb_DevData *, SetupPacket *)) +{ + XUsbPsu_set_ch9handler((struct XUsbPsu *)InstancePtr, func); +} + +void Set_RstHandler(void *InstancePtr, void (*func)(struct Usb_DevData *)) +{ + XUsbPsu_set_rsthandler((struct XUsbPsu *)InstancePtr, func); +} + +void Set_Disconnect(void *InstancePtr, void (*func)(struct Usb_DevData *)) +{ + XUsbPsu_set_disconnect((struct XUsbPsu *)InstancePtr, func); +} + +void EpConfigure(void *UsbInstance, u8 EndpointNo, u8 dir, u32 Type) +{ + (void)UsbInstance; + (void)EndpointNo; + (void)dir; + (void)Type; +} + +s32 ConfigureDevice(void *UsbInstance, u8 *MemPtr, u32 memSize) +{ + (void)UsbInstance; + (void)MemPtr; + (void)memSize; + return XST_SUCCESS; +} + +void SetEpHandler(void *InstancePtr, u8 Epnum, + u8 Dir, void (*Handler)(void *, u32, u32)) +{ + XUsbPsu_SetEpHandler((struct XUsbPsu *)InstancePtr, Epnum, Dir, Handler); +} + +s32 Usb_Start(void *InstancePtr) +{ + return XUsbPsu_Start((struct XUsbPsu *)InstancePtr); +} + +void *Get_DrvData(void *InstancePtr) +{ + return XUsbPsu_get_drvdata((struct XUsbPsu *)InstancePtr); +} + +void Set_DrvData(void *InstancePtr, void *data) +{ + XUsbPsu_set_drvdata((struct XUsbPsu *)InstancePtr, data); +} + +s32 IsEpStalled(void *InstancePtr, u8 Epnum, u8 Dir) +{ + return XUsbPsu_IsEpStalled((struct XUsbPsu *)InstancePtr, Epnum, Dir); +} + +void EpClearStall(void *InstancePtr, u8 Epnum, u8 Dir) +{ + XUsbPsu_EpClearStall((struct XUsbPsu *)InstancePtr, Epnum, Dir); +} + +s32 EpBufferSend(void *InstancePtr, u8 UsbEp, + u8 *BufferPtr, u32 BufferLen) +{ + if (UsbEp == 0 && BufferLen == 0) + return XST_SUCCESS; + else + return XUsbPsu_EpBufferSend((struct XUsbPsu *)InstancePtr, + UsbEp, BufferPtr, BufferLen); + +} + +s32 EpBufferRecv(void *InstancePtr, u8 UsbEp, + u8 *BufferPtr, u32 Length) +{ + return XUsbPsu_EpBufferRecv((struct XUsbPsu *)InstancePtr, UsbEp, + BufferPtr, Length); +} + +void EpSetStall(void *InstancePtr, u8 Epnum, u8 Dir) +{ + XUsbPsu_EpSetStall((struct XUsbPsu *)InstancePtr, Epnum, Dir); +} + +void SetBits(void *InstancePtr, u32 TestSel) +{ + (void)InstancePtr; + (void)TestSel; +} + +s32 SetDeviceAddress(void *InstancePtr, u16 Addr) +{ + return XUsbPsu_SetDeviceAddress((struct XUsbPsu *)InstancePtr, Addr); +} + +s32 SetU1SleepTimeout(void *InstancePtr, u8 Sleep) +{ + return XUsbPsu_SetU1SleepTimeout((struct XUsbPsu *)InstancePtr, Sleep); +} + +s32 SetU2SleepTimeout(void *InstancePtr, u8 Sleep) +{ + return XUsbPsu_SetU2SleepTimeout((struct XUsbPsu *)InstancePtr, Sleep); +} + +s32 AcceptU1U2Sleep(void *InstancePtr) +{ + return XUsbPsu_AcceptU1U2Sleep((struct XUsbPsu *)InstancePtr); + +} + +s32 U1SleepEnable(void *InstancePtr) +{ + return XUsbPsu_U1SleepEnable((struct XUsbPsu *)InstancePtr); +} + +s32 U2SleepEnable(void *InstancePtr) +{ + return XUsbPsu_U2SleepEnable((struct XUsbPsu *)InstancePtr); +} + +s32 U1SleepDisable(void *InstancePtr) +{ + return XUsbPsu_U1SleepDisable((struct XUsbPsu *)InstancePtr); +} + +s32 U2SleepDisable(void *InstancePtr) +{ + return XUsbPsu_U2SleepDisable((struct XUsbPsu *)InstancePtr); +} + +s32 EpEnable(void *InstancePtr, u8 UsbEpNum, u8 Dir, u16 Maxsize, u8 Type) +{ + return XUsbPsu_EpEnable((struct XUsbPsu *)InstancePtr, UsbEpNum, Dir, + Maxsize, Type, FALSE); +} + +s32 EpDisable(void *InstancePtr, u8 UsbEpNum, u8 Dir) +{ + return XUsbPsu_EpDisable((struct XUsbPsu *)InstancePtr, UsbEpNum, Dir); +} + +void Usb_SetSpeed(void *InstancePtr, u32 Speed) +{ + XUsbPsu_SetSpeed((struct XUsbPsu *)InstancePtr, Speed); +} + +/****************************************************************************/ +/** +* Sets speed of the Core for connecting to Host +* +* @param InstancePtr is a pointer to the Usb_DevData instance. +* +* @return XST_SUCCESS else XST_FAILURE +* +* @note None. +* +*****************************************************************************/ +s32 IsSuperSpeed(struct Usb_DevData *InstancePtr) +{ + if (InstancePtr->Speed != XUSBPSU_SPEED_SUPER) { + return XST_FAILURE; + } + + return XST_SUCCESS; +} + +/****************************************************************************/ +/** +* Set the Config state +* +* @param InstancePtr is a private member of Usb_DevData instance. +* @param Flag is the config value. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void SetConfigDone(void *InstancePtr, u8 Flag) +{ + ((struct XUsbPsu *)InstancePtr)->IsConfigDone = Flag; +} + +/****************************************************************************/ +/** +* Get the Config state +* +* @param InstancePtr is a private member of Usb_DevData instance. +* +* @return Current configuration value +* +* @note None. +* +*****************************************************************************/ +u8 GetConfigDone(void *InstancePtr) +{ + return (((struct XUsbPsu *)InstancePtr)->IsConfigDone); +} + +void Ep0StallRestart(void *InstancePtr) +{ + XUsbPsu_Ep0StallRestart((struct XUsbPsu *)InstancePtr); +} + +/******************************************************************************/ +/** + * This function sets Endpoint Interval. + * + * @param InstancePtr is a private member of Usb_DevData instance. + * @param UsbEpnum is Endpoint Number. + * @param Dir is Endpoint Direction(In/Out). + * @param Interval is the data transfer service interval + * + * @return None. + * + * @note None. + * + ******************************************************************************/ +void SetEpInterval(void *InstancePtr, u8 UsbEpNum, u8 Dir, u32 Interval) +{ + u32 PhyEpNum; + struct XUsbPsu_Ep *Ept; + + PhyEpNum = PhysicalEp(UsbEpNum, Dir); + Ept = &((struct XUsbPsu *)InstancePtr)->eps[PhyEpNum]; + Ept->Interval = Interval; +} + +void StopTransfer(void *InstancePtr, u8 EpNum, u8 Dir) +{ + XUsbPsu_StopTransfer((struct XUsbPsu *)InstancePtr, EpNum, Dir, TRUE); +} + +s32 StreamOn(void *InstancePtr, u8 EpNum, u8 Dir, u8 *BufferPtr) +{ + (void)InstancePtr; + (void)EpNum; + (void)Dir; + (void)BufferPtr; + /* Streaming will start on TxferNotReady Event */ + return XST_SUCCESS; +} + +void StreamOff(void *InstancePtr, u8 EpNum, u8 Dir) +{ + StopTransfer((struct XUsbPsu *)InstancePtr, EpNum, Dir); +}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusb_wrapper.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusb_wrapper.h new file mode 100644 index 0000000..d21072b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusb_wrapper.h
@@ -0,0 +1,190 @@ +/****************************************************************************** + * + * Copyright (C) 2017 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * + ******************************************************************************/ +/*****************************************************************************/ +/** + * + * @file xusb_wrapper.h + * + * This file contains declarations for USBPSU Driver wrappers. + * + * <pre> + * MODIFICATION HISTORY: + * + * Ver Who Date Changes + * ----- ---- -------- ------------------------------------------------------- + * 1.0 BK 12/01/18 First release + * MYK 12/01/18 Added hibernation support for device mode + * vak 22/01/18 Added Microblaze support for usbpsu driver + * vak 13/03/18 Moved the setup interrupt system calls from driver to + * example. + * + * </pre> + * + *****************************************************************************/ + +#ifndef XUSB_WRAPPER_H /* Prevent circular inclusions */ +#define XUSB_WRAPPER_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ +#include "xusbpsu.h" + +/************************** Constant Definitions ****************************/ +#define USB_DEVICE_ID XPAR_XUSBPSU_0_DEVICE_ID + +#define USB_EP_DIR_IN XUSBPSU_EP_DIR_IN +#define USB_EP_DIR_OUT XUSBPSU_EP_DIR_OUT + +#define USB_DIR_OUT 0U /* to device */ +#define USB_DIR_IN 0x80U /* to host */ + +/** + * @name Endpoint Address + * @{ + */ +#define USB_EP1_IN 0x81 +#define USB_EP1_OUT 0x01 +#define USB_EP2_IN 0x82 +#define USB_EP2_OUT 0x02 +/* @} */ + +/** + * @name Endpoint Type + * @{ + */ +#define USB_EP_TYPE_CONTROL XUSBPSU_ENDPOINT_XFER_CONTROL +#define USB_EP_TYPE_ISOCHRONOUS XUSBPSU_ENDPOINT_XFER_ISOC +#define USB_EP_TYPE_BULK XUSBPSU_ENDPOINT_XFER_BULK +#define USB_EP_TYPE_INTERRUPT XUSBPSU_ENDPOINT_XFER_INT +/* @} */ + +#define USB_ENDPOINT_NUMBER_MASK 0x0f /* in bEndpointAddress */ +#define USB_ENDPOINT_DIR_MASK 0x80 + +/* + * Device States + */ +#define USB_STATE_ATTACHED XUSBPSU_STATE_ATTACHED +#define USB_STATE_POWERED XUSBPSU_STATE_POWERED +#define USB_STATE_DEFAULT XUSBPSU_STATE_DEFAULT +#define USB_STATE_ADDRESS XUSBPSU_STATE_ADDRESS +#define USB_STATE_CONFIGURED XUSBPSU_STATE_CONFIGURED +#define USB_STATE_SUSPENDED XUSBPSU_STATE_SUSPENDED + +#define XUSBPSU_REQ_REPLY_LEN 1024 /**< Max size of reply buffer. */ +#define USB_REQ_REPLY_LEN XUSBPSU_REQ_REPLY_LEN + +/* + * Device Speeds + */ +#define USB_SPEED_UNKNOWN XUSBPSU_SPEED_UNKNOWN +#define USB_SPEED_LOW XUSBPSU_SPEED_LOW +#define USB_SPEED_FULL XUSBPSU_SPEED_FULL +#define USB_SPEED_HIGH XUSBPSU_SPEED_HIGH +#define USB_SPEED_SUPER XUSBPSU_SPEED_SUPER + +/* Device Configuration Speed */ +#define USB_DCFG_SPEED_MASK XUSBPSU_DCFG_SPEED_MASK +#define USB_DCFG_SUPERSPEED XUSBPSU_DCFG_SUPERSPEED +#define USB_DCFG_HIGHSPEED XUSBPSU_DCFG_HIGHSPEED +#define USB_DCFG_FULLSPEED2 XUSBPSU_DCFG_FULLSPEED2 +#define USB_DCFG_LOWSPEED XUSBPSU_DCFG_LOWSPEED +#define USB_DCFG_FULLSPEED1 XUSBPSU_DCFG_FULLSPEED1 + +#define USB_TEST_J XUSBPSU_TEST_J +#define USB_TEST_K XUSBPSU_TEST_K +#define USB_TEST_SE0_NAK XUSBPSU_TEST_SE0_NAK +#define USB_TEST_PACKET XUSBPSU_TEST_PACKET +#define USB_TEST_FORCE_ENABLE XUSBPSU_TEST_FORCE_ENABLE + +/* TODO: If we enable this macro, reconnection is failed with 2017.3 */ +#define USB_LPM_MODE XUSBPSU_LPM_MODE + +/* + * return Physical EP number as dwc3 mapping + */ +#define PhysicalEp(epnum, direction) (((epnum) << 1 ) | (direction)) + +/**************************** Type Definitions ******************************/ + +/************************** Variable Definitions *****************************/ +struct XUsbPsu PrivateData; + +/***************** Macros (Inline Functions) Definitions *********************/ +Usb_Config* LookupConfig(u16 DeviceId); +void CacheInit(void); +s32 CfgInitialize(struct Usb_DevData *InstancePtr, + Usb_Config *ConfigPtr, u32 BaseAddress); +void Set_Ch9Handler(void *InstancePtr, + void (*func)(struct Usb_DevData *, SetupPacket *)); +void Set_RstHandler(void *InstancePtr, void (*func)(struct Usb_DevData *)); +void Set_Disconnect(void *InstancePtr, void (*func)(struct Usb_DevData *)); +void EpConfigure(void *UsbInstance, u8 EndpointNo, u8 dir, u32 Type); +s32 ConfigureDevice(void *UsbInstance, u8 *MemPtr, u32 memSize); +void SetEpHandler(void *InstancePtr, u8 Epnum, + u8 Dir, void (*Handler)(void *, u32, u32)); +s32 Usb_Start(void *InstancePtr); +void *Get_DrvData(void *InstancePtr); +void Set_DrvData(void *InstancePtr, void *data); +s32 IsEpStalled(void *InstancePtr, u8 Epnum, u8 Dir); +void EpClearStall(void *InstancePtr, u8 Epnum, u8 Dir); +s32 EpBufferSend(void *InstancePtr, u8 UsbEp, + u8 *BufferPtr, u32 BufferLen); +s32 EpBufferRecv(void *InstancePtr, u8 UsbEp, + u8 *BufferPtr, u32 Length); +void EpSetStall(void *InstancePtr, u8 Epnum, u8 Dir); +void SetBits(void *InstancePtr, u32 TestSel); +s32 SetDeviceAddress(void *InstancePtr, u16 Addr); +s32 SetU1SleepTimeout(void *InstancePtr, u8 Sleep); +s32 SetU2SleepTimeout(void *InstancePtr, u8 Sleep); +s32 AcceptU1U2Sleep(void *InstancePtr); +s32 U1SleepEnable(void *InstancePtr); +s32 U2SleepEnable(void *InstancePtr); +s32 U1SleepDisable(void *InstancePtr); +s32 U2SleepDisable(void *InstancePtr); +s32 EpEnable(void *InstancePtr, u8 UsbEpNum, u8 Dir, u16 Maxsize, u8 Type); +s32 EpDisable(void *InstancePtr, u8 UsbEpNum, u8 Dir); +void Usb_SetSpeed(void *InstancePtr, u32 Speed); +s32 IsSuperSpeed(struct Usb_DevData *InstancePtr); +void SetConfigDone(void *InstancePtr, u8 Flag); +u8 GetConfigDone(void *InstancePtr); +void Ep0StallRestart(void *InstancePtr); +void SetEpInterval(void *InstancePtr, u8 UsbEpNum, u8 Dir, u32 Interval); +void StopTransfer(void *InstancePtr, u8 EpNum, u8 Dir); +s32 StreamOn(void *InstancePtr, u8 EpNum, u8 Dir, u8 *BufferPtr); +void StreamOff(void *InstancePtr, u8 EpNum, u8 Dir); + +#endif /* End of protection macro. */ +/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu.c similarity index 95% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu.c index c39d11a..245fba2 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu.c
@@ -33,7 +33,7 @@ /** * * @file xusbpsu.c -* @addtogroup usbpsu_v1_0 +* @addtogroup usbpsu_v1_3 * @{ * * <pre> @@ -44,14 +44,16 @@ * ----- ----- -------- ----------------------------------------------------- * 1.0 sg 06/16/16 First release * 1.1 sg 10/24/16 Added new function XUsbPsu_IsSuperSpeed -* +* 1.4 bk 12/01/18 Modify USBPSU driver code to fit USB common example code +* for all USB IPs. +* myk 12/01/18 Added hibernation support for device mode * </pre> * *****************************************************************************/ /***************************** Include Files ********************************/ -#include "xusbpsu.h" +#include "xusb_wrapper.h" /************************** Constant Definitions *****************************/ @@ -226,19 +228,20 @@ ******************************************************************************/ void XUsbPsu_EventBuffersSetup(struct XUsbPsu *InstancePtr) { - struct XUsbPsu_EvtBuffer *Evt; + struct XUsbPsu_EvtBuffer *Evt; Xil_AssertVoid(InstancePtr != NULL); Evt = &InstancePtr->Evt; Evt->BuffAddr = (void *)InstancePtr->EventBuffer; + Evt->Offset = 0; XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTADRLO(0), - (UINTPTR)InstancePtr->EventBuffer); + (UINTPTR)InstancePtr->EventBuffer); XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTADRHI(0), - ((UINTPTR)(InstancePtr->EventBuffer) >> 16U) >> 16U); + ((UINTPTR)(InstancePtr->EventBuffer) >> 16U) >> 16U); XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTSIZ(0), - XUSBPSU_GEVNTSIZ_SIZE(sizeof(InstancePtr->EventBuffer))); + XUSBPSU_GEVNTSIZ_SIZE(sizeof(InstancePtr->EventBuffer))); XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTCOUNT(0), 0); } @@ -321,9 +324,9 @@ XUsbPsu_PhyReset(InstancePtr); RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GCTL); - RegVal &= ~XUSBPSU_GCTL_SCALEDOWN_MASK; - RegVal &= ~XUSBPSU_GCTL_DISSCRAMBLE; - RegVal |= XUSBPSU_GCTL_U2EXIT_LFPS; + RegVal &= ~XUSBPSU_GCTL_SCALEDOWN_MASK; + RegVal &= ~XUSBPSU_GCTL_DISSCRAMBLE; + RegVal |= XUSBPSU_GCTL_U2EXIT_LFPS; Hwparams1 = XUsbPsu_ReadHwParams(InstancePtr, 1U); @@ -333,7 +336,11 @@ break; case XUSBPSU_GHWPARAMS1_EN_PWROPT_HIB: - /* enable hibernation here */ + /* enable hibernation here */ +#ifdef XUSBPSU_HIBERNATION_ENABLE + RegVal |= XUSBPSU_GCTL_GBLHIBERNATIONEN; + InstancePtr->HasHibernation = 1; +#endif break; default: @@ -343,6 +350,11 @@ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GCTL, RegVal); +#ifdef XUSBPSU_HIBERNATION_ENABLE + if (InstancePtr->HasHibernation) + XUsbPsu_InitHibernation(InstancePtr); +#endif + return XST_SUCCESS; } @@ -441,7 +453,7 @@ s32 XUsbPsu_CfgInitialize(struct XUsbPsu *InstancePtr, XUsbPsu_Config *ConfigPtr, u32 BaseAddress) { - int Status; + s32 Status; u32 RegVal; @@ -471,10 +483,10 @@ XUsbPsu_SetMode(InstancePtr, XUSBPSU_GCTL_PRTCAP_DEVICE); - /* - * Setting to max speed to support SS and HS - */ - XUsbPsu_SetSpeed(InstancePtr, XUSBPSU_DCFG_SUPERSPEED); + /* + * Setting to max speed to support SS and HS + */ + XUsbPsu_SetSpeed(InstancePtr, XUSBPSU_DCFG_SUPERSPEED); (void)XUsbPsu_SetDeviceAddress(InstancePtr, 0U); @@ -694,7 +706,7 @@ Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(Addr <= 127U); - if (InstancePtr->State == XUSBPSU_STATE_CONFIGURED) { + if (InstancePtr->AppData->State == XUSBPSU_STATE_CONFIGURED) { return XST_FAILURE; } @@ -704,30 +716,10 @@ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCFG, RegVal); if (Addr) { - InstancePtr->State = XUSBPSU_STATE_ADDRESS; + InstancePtr->AppData->State = XUSBPSU_STATE_ADDRESS; } else { - InstancePtr->State = XUSBPSU_STATE_DEFAULT; - } - - return XST_SUCCESS; -} - -/****************************************************************************/ -/** -* Sets speed of the Core for connecting to Host -* -* @param InstancePtr is a pointer to the XUsbPsu instance. -* -* @return XST_SUCCESS else XST_FAILURE -* -* @note None. -* -*****************************************************************************/ -s32 XUsbPsu_IsSuperSpeed(struct XUsbPsu *InstancePtr) -{ - if (InstancePtr->Speed != XUSBPSU_SPEED_SUPER) { - return XST_FAILURE; + InstancePtr->AppData->State = XUSBPSU_STATE_DEFAULT; } return XST_SUCCESS;
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu.h similarity index 78% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu.h index a136648..2d1498a 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu.h
@@ -33,7 +33,7 @@ /** * * @file xusbpsu.h -* @addtogroup usbpsu_v1_0 +* @addtogroup usbpsu_v1_3 * @{ * @details * @@ -46,6 +46,22 @@ * 1.0 sg 06/06/16 First release * 1.1 sg 10/24/16 Update for backward compatability * Added XUsbPsu_IsSuperSpeed function in xusbpsu.c +* 1.2 mn 01/20/17 removed unnecessary declaration of +* XUsbPsu_SetConfiguration in xusbpsu.h +* 1.2 mn 01/30/17 Corrected InstancePtr->UnalignedTx with +* Ept->UnalignedTx in xusbpsu_controltransfers.c +* 1.2 mus 02/10/17 Updated data structures to fix compilation errors for IAR +* compiler +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* ms 04/10/17 Modified filename tag to include the file in doxygen +* examples. +* 1.4 bk 12/01/18 Modify USBPSU driver code to fit USB common example code +* for all USB IPs. +* myk 12/01/18 Added hibernation support for device mode +* vak 22/01/18 Added changes for supporting microblaze platform +* vak 13/03/18 Moved the setup interrupt system calls from driver to +* example. * * </pre> * @@ -58,17 +74,22 @@ #endif /***************************** Include Files ********************************/ + +/* Enable XUSBPSU_HIBERNATION_ENABLE to enable hibernation */ +//#define XUSBPSU_HIBERNATION_ENABLE 1 + #include "xparameters.h" #include "xil_types.h" #include "xil_assert.h" #include "xstatus.h" #include "xusbpsu_hw.h" #include "xil_io.h" + /* * The header sleep.h and API usleep() can only be used with an arm design. * MB_Sleep() is used for microblaze design. */ -#if defined (__arm__) || defined (__aarch64__) +#if defined (__arm__) || defined (__aarch64__) || (__ICCARM__) #include "sleep.h" #endif @@ -79,16 +100,19 @@ /************************** Constant Definitions ****************************/ +#define NO_OF_TRB_PER_EP 2 + +#ifdef PLATFORM_ZYNQMP #define ALIGNMENT_CACHELINE __attribute__ ((aligned(64))) +#else +#define ALIGNMENT_CACHELINE __attribute__ ((aligned(32))) +#endif #define XUSBPSU_PHY_TIMEOUT 5000U /* in micro seconds */ #define XUSBPSU_EP_DIR_IN 1U #define XUSBPSU_EP_DIR_OUT 0U -#define XUSBPSU_ENDPOINT_NUMBER_MASK 0x0f /* in bEndpointAddress */ -#define XUSBPSU_ENDPOINT_DIR_MASK 0x80 - #define XUSBPSU_ENDPOINT_XFERTYPE_MASK 0x03 /* in bmAttributes */ #define XUSBPSU_ENDPOINT_XFER_CONTROL 0U #define XUSBPSU_ENDPOINT_XFER_ISOC 1U @@ -254,15 +278,6 @@ /**************************** Type Definitions ******************************/ /** - * This typedef contains configuration information for the XUSBPSU - * device. - */ -typedef struct { - u16 DeviceId; /**< Unique ID of controller */ - u32 BaseAddress; /**< Core register base address */ -} XUsbPsu_Config; - -/** * Software Event buffer representation */ struct XUsbPsu_EvtBuffer { @@ -275,13 +290,20 @@ /** * Transfer Request Block - Hardware format */ +#if defined (__ICCARM__) +#pragma pack(push, 1) +#endif struct XUsbPsu_Trb { u32 BufferPtrLow; u32 BufferPtrHigh; u32 Size; u32 Ctrl; +#if defined (__ICCARM__) +}; +#pragma pack(pop) +#else } __attribute__((packed)); - +#endif /* * Endpoint Parameters @@ -295,13 +317,21 @@ /** * USB Standard Control Request */ +#if defined (__ICCARM__) +#pragma pack(push, 1) +#endif typedef struct { u8 bRequestType; u8 bRequest; u16 wValue; u16 wIndex; u16 wLength; +#if defined (__ICCARM__) +}SetupPacket; +#pragma pack(pop) +#else } __attribute__ ((packed)) SetupPacket; +#endif /** * Endpoint representation @@ -312,11 +342,22 @@ * when data is sent for IN Ep * and received for OUT Ep */ - struct XUsbPsu_Trb EpTrb ALIGNMENT_CACHELINE;/**< TRB used by endpoint */ +#if defined (__ICCARM__) + #pragma data_alignment = 64 + struct XUsbPsu_Trb EpTrb[NO_OF_TRB_PER_EP + 1]; /**< One extra Trb is for Link Trb */ + #pragma data_alignment = 4 +#else + struct XUsbPsu_Trb EpTrb[NO_OF_TRB_PER_EP + 1] ALIGNMENT_CACHELINE;/**< TRB used by endpoint */ +#endif u32 EpStatus; /**< Flags to represent Endpoint status */ + u32 EpSavedState; /**< Endpoint status saved at the time of hibernation */ u32 RequestedBytes; /**< RequestedBytes for transfer */ u32 BytesTxed; /**< Actual Bytes transferred */ + u32 Interval; /**< Data transfer service interval */ + u32 TrbEnqueue; + u32 TrbDequeue; u16 MaxSize; /**< Size of endpoint */ + u16 CurUf; /**< current microframe */ u8 *BufferPtr; /**< Buffer location */ u8 ResourceIndex; /**< Resource Index assigned to * Endpoint by core @@ -331,12 +372,38 @@ }; /** + * This typedef contains configuration information for the USB + * device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of controller */ + u32 BaseAddress; /**< Core register base address */ + u8 IsCacheCoherent; /**< Describes whether Cache Coherent or not */ +} XUsbPsu_Config; + +typedef XUsbPsu_Config Usb_Config; + +struct Usb_DevData { + u8 Speed; + u8 State; + + void *PrivateData; +}; + +/** * USB Device Controller representation */ struct XUsbPsu { +#if defined (__ICCARM__) + #pragma data_alignment = 64 + SetupPacket SetupData; + struct XUsbPsu_Trb Ep0_Trb; + #pragma data_alignment = 4 +#else SetupPacket SetupData ALIGNMENT_CACHELINE; /**< Setup Packet buffer */ struct XUsbPsu_Trb Ep0_Trb ALIGNMENT_CACHELINE; +#endif /**< TRB for control transfers */ XUsbPsu_Config *ConfigPtr; /**< Configuration info pointer */ struct XUsbPsu_Ep eps[XUSBPSU_ENDPOINTS_NUM]; /**< Endpoints */ @@ -345,32 +412,48 @@ u32 BaseAddress; /**< Core register base address */ u32 DevDescSize; u32 ConfigDescSize; - void (*Chapter9)(struct XUsbPsu *, SetupPacket *); - void (*ClassHandler)(struct XUsbPsu *, SetupPacket *); + struct Usb_DevData *AppData; + void (*Chapter9)(struct Usb_DevData *, SetupPacket *); + void (*ResetIntrHandler)(struct Usb_DevData *); + void (*DisconnectIntrHandler)(struct Usb_DevData *); void *DevDesc; void *ConfigDesc; +#if defined(__ICCARM__) + #pragma data_alignment = XUSBPSU_EVENT_BUFFERS_SIZE + u8 EventBuffer[XUSBPSU_EVENT_BUFFERS_SIZE]; + #pragma data_alignment = 4 +#else u8 EventBuffer[XUSBPSU_EVENT_BUFFERS_SIZE] __attribute__((aligned(XUSBPSU_EVENT_BUFFERS_SIZE))); +#endif u8 NumOutEps; u8 NumInEps; u8 ControlDir; u8 IsInTestMode; u8 TestMode; - u8 Speed; - u8 State; u8 Ep0State; u8 LinkState; u8 UnalignedTx; u8 IsConfigDone; u8 IsThreeStage; + u8 IsHibernated; /**< Hibernated state */ + u8 HasHibernation; /**< Has hibernation support */ + void *data_ptr; /* pointer for storing applications data */ }; +#if defined (__ICCARM__) +#pragma pack(push, 1) +#endif struct XUsbPsu_Event_Type { u32 Is_DevEvt:1; u32 Type:7; u32 Reserved8_31:24; +#if defined (__ICCARM__) +}; +#pragma pack(pop) +#else } __attribute__((packed)); - +#endif /** * struct XUsbPsu_event_depvt - Device Endpoint Events * @Is_EpEvt: indicates this is an endpoint event @@ -390,6 +473,9 @@ * @Parameters: Parameters of the current event. Refer to databook for * more information. */ +#if defined (__ICCARM__) +#pragma pack(push, 1) +#endif struct XUsbPsu_Event_Epevt { u32 Is_EpEvt:1; u32 Epnumber:5; @@ -397,8 +483,12 @@ u32 Reserved11_10:2; u32 Status:4; u32 Parameters:16; +#if defined (__ICCARM__) +}; +#pragma pack(pop) +#else } __attribute__((packed)); - +#endif /** * struct XUsbPsu_event_devt - Device Events * @Is_DevEvt: indicates this is a non-endpoint event @@ -421,6 +511,9 @@ * @Event_Info: Information about this event * @Reserved31_25: Reserved, not used */ +#if defined (__ICCARM__) +#pragma pack(push, 1) +#endif struct XUsbPsu_Event_Devt { u32 Is_DevEvt:1; u32 Device_Event:7; @@ -428,8 +521,12 @@ u32 Reserved15_12:4; u32 Event_Info:9; u32 Reserved31_25:7; +#if defined (__ICCARM__) +}; +#pragma pack(pop) +#else } __attribute__((packed)); - +#endif /** * struct XUsbPsu_event_gevt - Other Core Events * @one_bit: indicates this is a non-endpoint event (not used) @@ -437,13 +534,20 @@ * @phy_port_number: self-explanatory * @reserved31_12: Reserved, not used. */ +#if defined (__ICCARM__) +#pragma pack(push, 1) +#endif struct XUsbPsu_Event_Gevt { u32 Is_GlobalEvt:1; u32 Device_Event:7; u32 Phy_Port_Number:4; u32 Reserved31_12:20; +#if defined (__ICCARM__) +}; +#pragma pack(pop) +#else } __attribute__((packed)); - +#endif /** * union XUsbPsu_event - representation of Event Buffer contents * @raw: raw 32-bit event @@ -461,16 +565,22 @@ }; /***************** Macros (Inline Functions) Definitions *********************/ - +#if defined (__ICCARM__) +#define IS_ALIGNED(x, a) (((x) & ((u32)(a) - 1)) == 0U) +#else #define IS_ALIGNED(x, a) (((x) & ((typeof(x))(a) - 1)) == 0U) +#endif +#if defined (__ICCARM__) +#define roundup(x, y) (((((x) + (u32)(y - 1)) / (u32)y) * (u32)y)) + +#else #define roundup(x, y) ( \ -{ \ - const typeof(y) y__ = (y); \ - (((x) + (u32)(y__ - 1)) / (u32)y__) * (u32)y__; \ -} \ + (((x) + (u32)((const typeof(y))y - 1)) / \ + (u32)((const typeof(y))y)) * \ + (u32)((const typeof(y))y) \ ) - +#endif #define DECLARE_DEV_DESC(Instance, desc) \ (Instance).DevDesc = &(desc); \ (Instance).DevDescSize = sizeof((desc)) @@ -479,6 +589,32 @@ (Instance).ConfigDesc = &(desc); \ (Instance).ConfigDescSize = sizeof((desc)) +static inline void *XUsbPsu_get_drvdata(struct XUsbPsu *InstancePtr) { + return InstancePtr->data_ptr; +} + +static inline void XUsbPsu_set_drvdata(struct XUsbPsu *InstancePtr, void *data) { + InstancePtr->data_ptr = data; +} + +static inline void XUsbPsu_set_ch9handler( + struct XUsbPsu *InstancePtr, + void (*func)(struct Usb_DevData *, SetupPacket *)) { + InstancePtr->Chapter9 = func; +} + +static inline void XUsbPsu_set_rsthandler( + struct XUsbPsu *InstancePtr, + void (*func)(struct Usb_DevData *)) { + InstancePtr->ResetIntrHandler = func; +} + +static inline void XUsbPsu_set_disconnect( + struct XUsbPsu *InstancePtr, + void (*func)(struct Usb_DevData *)) { + InstancePtr->DisconnectIntrHandler = func; +} + /************************** Function Prototypes ******************************/ /* @@ -510,7 +646,6 @@ s32 Cmd, u32 Param); void XUsbPsu_SetSpeed(struct XUsbPsu *InstancePtr, u32 Speed); s32 XUsbPsu_SetDeviceAddress(struct XUsbPsu *InstancePtr, u16 Addr); -s32 XUsbPsu_IsSuperSpeed(struct XUsbPsu *InstancePtr); s32 XUsbPsu_SetU1SleepTimeout(struct XUsbPsu *InstancePtr, u8 Sleep); s32 XUsbPsu_SetU2SleepTimeout(struct XUsbPsu *InstancePtr, u8 Sleep); s32 XUsbPsu_AcceptU1U2Sleep(struct XUsbPsu *InstancePtr); @@ -525,23 +660,25 @@ struct XUsbPsu_EpParams *XUsbPsu_GetEpParams(struct XUsbPsu *InstancePtr); u32 XUsbPsu_EpGetTransferIndex(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir); -const char *XUsbPsu_EpCmdString(u8 Cmd); s32 XUsbPsu_SendEpCmd(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir, u32 Cmd, struct XUsbPsu_EpParams *Params); s32 XUsbPsu_StartEpConfig(struct XUsbPsu *InstancePtr, u32 UsbEpNum, u8 Dir); s32 XUsbPsu_SetEpConfig(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir, - u16 Size, u8 Type); + u16 Size, u8 Type, u8 Restore); s32 XUsbPsu_SetXferResource(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir); s32 XUsbPsu_EpEnable(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir, - u16 Maxsize, u8 Type); + u16 Maxsize, u8 Type, u8 Restore); s32 XUsbPsu_EpDisable(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir); s32 XUsbPsu_EnableControlEp(struct XUsbPsu *InstancePtr, u16 Size); void XUsbPsu_InitializeEps(struct XUsbPsu *InstancePtr); -void XUsbPsu_StopTransfer(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir); +void XUsbPsu_StopTransfer(struct XUsbPsu *InstancePtr, u8 UsbEpNum, + u8 Dir, u8 Force); +void XUsbPsu_SaveEndpointState(struct XUsbPsu *InstancePtr, + struct XUsbPsu_Ep *Ept); void XUsbPsu_ClearStalls(struct XUsbPsu *InstancePtr); s32 XUsbPsu_EpBufferSend(struct XUsbPsu *InstancePtr, u8 UsbEp, - u8 *BufferPtr, u32 BufferLen); + u8 *BufferPtr, u32 BufferLen); s32 XUsbPsu_EpBufferRecv(struct XUsbPsu *InstancePtr, u8 UsbEp, u8 *BufferPtr, u32 Length); void XUsbPsu_EpSetStall(struct XUsbPsu *InstancePtr, u8 Epnum, u8 Dir); @@ -551,14 +688,14 @@ s32 XUsbPsu_IsEpStalled(struct XUsbPsu *InstancePtr, u8 Epnum, u8 Dir); void XUsbPsu_EpXferComplete(struct XUsbPsu *InstancePtr, const struct XUsbPsu_Event_Epevt *Event); +void XUsbPsu_EpXferNotReady(struct XUsbPsu *InstancePtr, + const struct XUsbPsu_Event_Epevt *Event); /* * Functions in xusbpsu_controltransfers.c */ s32 XUsbPsu_RecvSetup(struct XUsbPsu *InstancePtr); void XUsbPsu_Ep0StallRestart(struct XUsbPsu *InstancePtr); -s32 XUsbPsu_SetConfiguration(struct XUsbPsu *InstancePtr, - SetupPacket *Ctrl); void XUsbPsu_Ep0DataDone(struct XUsbPsu *InstancePtr, const struct XUsbPsu_Event_Epevt *Event); void XUsbPsu_Ep0StatusDone(struct XUsbPsu *InstancePtr, @@ -595,6 +732,14 @@ void XUsbPsu_EventBufferHandler(struct XUsbPsu *InstancePtr); void XUsbPsu_IntrHandler(void *XUsbPsuInstancePtr); +#ifdef XUSBPSU_HIBERNATION_ENABLE +void XUsbPsu_InitHibernation(struct XUsbPsu *InstancePtr); +void Xusbpsu_HibernationIntr(struct XUsbPsu *InstancePtr); +void XUsbPsu_WakeUpIntrHandler(void *XUsbPsuInstancePtr); +void XUsbPsu_WakeupIntr(struct XUsbPsu *InstancePtr); +s32 XUsbPsu_SetupScratchpad(struct XUsbPsu *InstancePtr); +#endif + /* * Functions in xusbpsu_sinit.c */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_controltransfers.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_controltransfers.c similarity index 90% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_controltransfers.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_controltransfers.c index b3a93dc..19be417 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_controltransfers.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_controltransfers.c
@@ -42,19 +42,20 @@ * Ver Who Date Changes * ----- ---- -------- ------------------------------------------------------- * 1.0 sg 06/06/16 First release +* 1.3 vak 04/03/17 Added CCI support for USB +* 1.4 bk 12/01/18 Modify USBPSU driver code to fit USB common example code +* for all USB IPs. * * </pre> * *****************************************************************************/ /***************************** Include Files *********************************/ - -#include "xusbpsu.h" #include "xusbpsu_endpoint.h" -/************************** Constant Definitions *****************************/ +#include "sleep.h" +#include "xusb_wrapper.h" -#define USB_DIR_OUT 0U /* to device */ -#define USB_DIR_IN 0x80U /* to host */ +/************************** Constant Definitions *****************************/ /**************************** Type Definitions *******************************/ @@ -62,10 +63,8 @@ /************************** Function Prototypes ******************************/ - /************************** Variable Definitions *****************************/ - /****************************************************************************/ /** * Initiates DMA on Control Endpoint 0 to receive Setup packet. @@ -92,7 +91,7 @@ /* Setup packet always on EP0 */ Ept = &InstancePtr->eps[0]; if ((Ept->EpStatus & XUSBPSU_EP_BUSY) != 0U) { - return XST_FAILURE; + return (s32)XST_FAILURE; } TrbPtr = &InstancePtr->Ep0_Trb; @@ -107,7 +106,10 @@ | XUSBPSU_TRB_CTRL_IOC | XUSBPSU_TRB_CTRL_ISP_IMI); - Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); + Xil_DCacheFlushRange((UINTPTR)&InstancePtr->SetupData, sizeof(SetupPacket)); + } Params->Param0 = 0U; Params->Param1 = (UINTPTR)TrbPtr; @@ -117,7 +119,7 @@ Ret = XUsbPsu_SendEpCmd(InstancePtr, 0U, XUSBPSU_EP_DIR_OUT, XUSBPSU_DEPCMD_STARTTRANSFER, Params); if (Ret != XST_SUCCESS) { - return XST_FAILURE; + return (s32)XST_FAILURE; } Ept->EpStatus |= XUSBPSU_EP_BUSY; @@ -187,7 +189,8 @@ Ept = &InstancePtr->eps[Epnum]; TrbPtr = &InstancePtr->Ep0_Trb; - Xil_DCacheInvalidateRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) + Xil_DCacheInvalidateRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); Status = XUSBPSU_TRB_SIZE_TRBSTS(TrbPtr->Size); if (Status == XUSBPSU_TRBSTS_SETUP_PENDING) { @@ -201,21 +204,22 @@ } else { if (Dir == XUSBPSU_EP_DIR_IN) { Ept->BytesTxed = Ept->RequestedBytes - Length; - } else if (Dir == XUSBPSU_EP_DIR_OUT) { - if (Ept->UnalignedTx == 1U) { - Ept->BytesTxed = Ept->RequestedBytes; - Ept->UnalignedTx = 0U; + } else { + if ((Dir == XUSBPSU_EP_DIR_OUT) && (Ept->UnalignedTx == 1U)) { + Ept->BytesTxed = Ept->RequestedBytes; + Ept->UnalignedTx = 0U; } } } if (Dir == XUSBPSU_EP_DIR_OUT) { /* Invalidate Cache */ - Xil_DCacheInvalidateRange((INTPTR)Ept->BufferPtr, Ept->BytesTxed); + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) + Xil_DCacheInvalidateRange((INTPTR)Ept->BufferPtr, Ept->BytesTxed); } if (Ept->Handler != NULL) { - Ept->Handler(InstancePtr, Ept->RequestedBytes, Ept->BytesTxed); + Ept->Handler(InstancePtr->AppData, Ept->RequestedBytes, Ept->BytesTxed); } } @@ -251,7 +255,8 @@ return; } } - Xil_DCacheInvalidateRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) + Xil_DCacheInvalidateRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); (void)XUsbPsu_RecvSetup(InstancePtr); } @@ -286,8 +291,10 @@ switch (InstancePtr->Ep0State) { case XUSBPSU_EP0_SETUP_PHASE: - Xil_DCacheInvalidateRange((INTPTR)&InstancePtr->SetupData, + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) { + Xil_DCacheInvalidateRange((INTPTR)&InstancePtr->SetupData, sizeof(InstancePtr->SetupData)); + } Length = Ctrl->wLength; if (Length == 0U) { InstancePtr->IsThreeStage = 0U; @@ -300,7 +307,7 @@ Xil_AssertVoid(InstancePtr->Chapter9 != NULL); - InstancePtr->Chapter9(InstancePtr, + InstancePtr->Chapter9(InstancePtr->AppData, &InstancePtr->SetupData); break; @@ -347,7 +354,7 @@ Params = XUsbPsu_GetEpParams(InstancePtr); Xil_AssertNonvoid(Params != NULL); if ((Ept->EpStatus & XUSBPSU_EP_BUSY) != 0U) { - return XST_FAILURE; + return (s32)XST_FAILURE; } Type = (InstancePtr->IsThreeStage != 0U) ? XUSBPSU_TRBCTL_CONTROL_STATUS3 @@ -364,7 +371,9 @@ | XUSBPSU_TRB_CTRL_IOC | XUSBPSU_TRB_CTRL_ISP_IMI); - Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); + } Params->Param0 = 0U; Params->Param1 = (UINTPTR)TrbPtr; @@ -380,7 +389,7 @@ Ret = XUsbPsu_SendEpCmd(InstancePtr, 0U, Dir, XUSBPSU_DEPCMD_STARTTRANSFER, Params); if (Ret != XST_SUCCESS) { - return XST_FAILURE; + return (s32)XST_FAILURE; } Ept->EpStatus |= XUSBPSU_EP_BUSY; @@ -543,7 +552,7 @@ Xil_AssertNonvoid(Params != NULL); if ((Ept->EpStatus & XUSBPSU_EP_BUSY) != 0U) { - return XST_FAILURE; + return (s32)XST_FAILURE; } Ept->RequestedBytes = BufferLen; @@ -565,15 +574,17 @@ Params->Param0 = 0U; Params->Param1 = (UINTPTR)TrbPtr; - Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); - Xil_DCacheFlushRange((INTPTR)BufferPtr, BufferLen); + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); + Xil_DCacheFlushRange((INTPTR)BufferPtr, BufferLen); + } InstancePtr->Ep0State = XUSBPSU_EP0_DATA_PHASE; Ret = XUsbPsu_SendEpCmd(InstancePtr, 0U, XUSBPSU_EP_DIR_IN, XUSBPSU_DEPCMD_STARTTRANSFER, Params); if (Ret != XST_SUCCESS) { - return XST_FAILURE; + return (s32)XST_FAILURE; } Ept->EpStatus |= XUSBPSU_EP_BUSY; @@ -612,7 +623,7 @@ Xil_AssertNonvoid(Params != NULL); if ((Ept->EpStatus & XUSBPSU_EP_BUSY) != 0U) { - return XST_FAILURE; + return (s32)XST_FAILURE; } Ept->RequestedBytes = Length; @@ -627,7 +638,7 @@ */ if (!IS_ALIGNED(Length, Ept->MaxSize)) { Size = (u32)roundup(Length, Ept->MaxSize); - InstancePtr->UnalignedTx = 1U; + Ept->UnalignedTx = 1U; } TrbPtr = &InstancePtr->Ep0_Trb; @@ -642,8 +653,10 @@ | XUSBPSU_TRB_CTRL_IOC | XUSBPSU_TRB_CTRL_ISP_IMI); - Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); - Xil_DCacheInvalidateRange((INTPTR)BufferPtr, Length); + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); + Xil_DCacheInvalidateRange((INTPTR)BufferPtr, Length); + } Params->Param0 = 0U; Params->Param1 = (UINTPTR)TrbPtr; @@ -653,7 +666,7 @@ Ret = XUsbPsu_SendEpCmd(InstancePtr, 0U, XUSBPSU_EP_DIR_OUT, XUSBPSU_DEPCMD_STARTTRANSFER, Params); if (Ret != XST_SUCCESS) { - return XST_FAILURE; + return (s32)XST_FAILURE; } Ept->EpStatus |= XUSBPSU_EP_BUSY;
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_endpoint.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_endpoint.c similarity index 72% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_endpoint.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_endpoint.c index 41368e5..42e4108 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_endpoint.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_endpoint.c
@@ -33,7 +33,7 @@ /** * * @file xusbpsu_endpoint.c -* @addtogroup usbpsu_v1_0 +* @addtogroup usbpsu_v1_3 * @{ * * @@ -43,32 +43,27 @@ * Ver Who Date Changes * ----- ---- -------- ------------------------------------------------------- * 1.0 sg 06/06/16 First release -* +* 1.3 vak 04/03/17 Added CCI support for USB +* 1.4 bk 12/01/18 Modify USBPSU driver code to fit USB common example code +* for all USB IPs +* myk 12/01/18 Added hibernation support for device mode * </pre> * *****************************************************************************/ /***************************** Include Files *********************************/ - -#include "xusbpsu.h" #include "xusbpsu_endpoint.h" -/************************** Constant Definitions *****************************/ +/************************** Constant Definitions *****************************/ /**************************** Type Definitions *******************************/ -/* return Physical EP number as dwc3 mapping */ -#define PhysicalEp(epnum, direction) (((epnum) << 1 ) | (direction)) - /***************** Macros (Inline Functions) Definitions *********************/ - /************************** Function Prototypes ******************************/ - /************************** Variable Definitions *****************************/ - /****************************************************************************/ /** * Returns zeroed parameters to be used by Endpoint commands @@ -233,6 +228,8 @@ * @param Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT. * @param Size is size of Endpoint size. * @param Type is Endpoint type Control/Bulk/Interrupt/Isoc. +* @param Restore should be true if saved state should be restored; +* typically this would be false * * @return XST_SUCCESS else XST_FAILURE. * @@ -240,8 +237,9 @@ * *****************************************************************************/ s32 XUsbPsu_SetEpConfig(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir, - u16 Size, u8 Type) + u16 Size, u8 Type, u8 Restore) { + struct XUsbPsu_Ep *Ept; struct XUsbPsu_EpParams *Params; u8 PhyEpNum; @@ -255,6 +253,7 @@ Xil_AssertNonvoid(Params != NULL); PhyEpNum = PhysicalEp(UsbEpNum , Dir); + Ept = &InstancePtr->eps[PhyEpNum]; Params->Param0 = XUSBPSU_DEPCFG_EP_TYPE(Type) | XUSBPSU_DEPCFG_MAX_PACKET_SIZE(Size); @@ -262,11 +261,18 @@ /* * Set burst size to 1 as recommended */ - Params->Param0 |= XUSBPSU_DEPCFG_BURST_SIZE(1); + if (InstancePtr->AppData->Speed == XUSBPSU_SPEED_SUPER) { + Params->Param0 |= XUSBPSU_DEPCFG_BURST_SIZE(1); + } Params->Param1 = XUSBPSU_DEPCFG_XFER_COMPLETE_EN | XUSBPSU_DEPCFG_XFER_NOT_READY_EN; + if (Restore) { + Params->Param0 |= XUSBPSU_DEPCFG_ACTION_RESTORE; + Params->Param2 = Ept->EpSavedState; + } + /* * We are doing 1:1 mapping for endpoints, meaning * Physical Endpoints 2 maps to Logical Endpoint 2 and @@ -279,6 +285,11 @@ Params->Param0 |= XUSBPSU_DEPCFG_FIFO_NUMBER((u32)PhyEpNum >> 1); } + if (Ept->Type == XUSBPSU_ENDPOINT_XFER_ISOC) { + Params->Param1 |= XUSBPSU_DEPCFG_BINTERVAL_M1(Ept->Interval - 1); + Params->Param1 |= XUSBPSU_DEPCFG_XFER_IN_PROGRESS_EN; + } + return XUsbPsu_SendEpCmd(InstancePtr, UsbEpNum, Dir, XUSBPSU_DEPCMD_SETEPCONFIG, Params); } @@ -325,6 +336,8 @@ * @param Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT. * @param Maxsize is size of Endpoint size. * @param Type is Endpoint type Control/Bulk/Interrupt/Isoc. +* @param Restore should be true if saved state should be restored; +* typically this would be false * * @return XST_SUCCESS else XST_FAILURE. * @@ -332,9 +345,10 @@ * ****************************************************************************/ s32 XUsbPsu_EpEnable(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir, - u16 Maxsize, u8 Type) + u16 Maxsize, u8 Type, u8 Restore) { struct XUsbPsu_Ep *Ept; + struct XUsbPsu_Trb *TrbStHw, *TrbLink; u32 RegVal; s32 Ret = (s32)XST_FAILURE; u32 PhyEpNum; @@ -353,20 +367,28 @@ Ept->Type = Type; Ept->MaxSize = Maxsize; Ept->PhyEpNum = (u8)PhyEpNum; + Ept->CurUf = 0; + if (!InstancePtr->IsHibernated) { + Ept->TrbEnqueue = 0; + Ept->TrbDequeue = 0; + } - if ((Ept->EpStatus & XUSBPSU_EP_ENABLED) == 0U) { + if (((Ept->EpStatus & XUSBPSU_EP_ENABLED) == 0U) + || (InstancePtr->IsHibernated)) { Ret = XUsbPsu_StartEpConfig(InstancePtr, UsbEpNum, Dir); if (Ret != 0) { return Ret; } } - Ret = XUsbPsu_SetEpConfig(InstancePtr, UsbEpNum, Dir, Maxsize, Type); + Ret = XUsbPsu_SetEpConfig(InstancePtr, UsbEpNum, Dir, Maxsize, + Type, Restore); if (Ret != 0) { return Ret; } - if ((Ept->EpStatus & XUSBPSU_EP_ENABLED) == 0U) { + if (((Ept->EpStatus & XUSBPSU_EP_ENABLED) == 0U) + || (InstancePtr->IsHibernated)) { Ret = XUsbPsu_SetXferResource(InstancePtr, UsbEpNum, Dir); if (Ret != 0) { return Ret; @@ -377,6 +399,18 @@ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DALEPENA); RegVal |= XUSBPSU_DALEPENA_EP(Ept->PhyEpNum); XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DALEPENA, RegVal); + + /* Following code is only applicable for ISO XFER */ + TrbStHw = &Ept->EpTrb[0]; + + /* Link TRB. The HWO bit is never reset */ + TrbLink = &Ept->EpTrb[NO_OF_TRB_PER_EP]; + memset(TrbLink, 0x00, sizeof(struct XUsbPsu_Trb)); + + TrbLink->BufferPtrLow = (UINTPTR)TrbStHw; + TrbLink->BufferPtrHigh = ((UINTPTR)TrbStHw >> 16) >> 16; + TrbLink->Ctrl |= XUSBPSU_TRBCTL_LINK_TRB; + TrbLink->Ctrl |= XUSBPSU_TRB_CTRL_HWO; } return XST_SUCCESS; @@ -410,6 +444,10 @@ PhyEpNum = PhysicalEp(UsbEpNum , Dir); Ept = &InstancePtr->eps[PhyEpNum]; + /* make sure HW endpoint isn't stalled */ + if (Ept->EpStatus & XUSBPSU_EP_STALL) + XUsbPsu_EpClearStall(InstancePtr, Ept->UsbEpNum, Ept->Direction); + RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DALEPENA); RegVal &= ~XUSBPSU_DALEPENA_EP(PhyEpNum); XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DALEPENA, RegVal); @@ -417,6 +455,8 @@ Ept->Type = 0U; Ept->EpStatus = 0U; Ept->MaxSize = 0U; + Ept->TrbEnqueue = 0U; + Ept->TrbDequeue = 0U; return XST_SUCCESS; } @@ -441,13 +481,13 @@ Xil_AssertNonvoid((Size >= 64U) && (Size <= 512U)); RetVal = XUsbPsu_EpEnable(InstancePtr, 0U, XUSBPSU_EP_DIR_OUT, Size, - XUSBPSU_ENDPOINT_XFER_CONTROL); + XUSBPSU_ENDPOINT_XFER_CONTROL, FALSE); if (RetVal != 0) { return XST_FAILURE; } RetVal = XUsbPsu_EpEnable(InstancePtr, 0U, XUSBPSU_EP_DIR_IN, Size, - XUSBPSU_ENDPOINT_XFER_CONTROL); + XUSBPSU_ENDPOINT_XFER_CONTROL, FALSE); if (RetVal != 0) { return XST_FAILURE; } @@ -479,11 +519,13 @@ Epnum = (i << 1U) | XUSBPSU_EP_DIR_OUT; InstancePtr->eps[Epnum].PhyEpNum = Epnum; InstancePtr->eps[Epnum].Direction = XUSBPSU_EP_DIR_OUT; + InstancePtr->eps[Epnum].ResourceIndex = 0; } for (i = 0U; i < InstancePtr->NumInEps; i++) { Epnum = (i << 1U) | XUSBPSU_EP_DIR_IN; InstancePtr->eps[Epnum].PhyEpNum = Epnum; InstancePtr->eps[Epnum].Direction = XUSBPSU_EP_DIR_IN; + InstancePtr->eps[Epnum].ResourceIndex = 0; } } @@ -494,13 +536,15 @@ * @param InstancePtr is a pointer to the XUsbPsu instance. * @param UsbEpNum is USB endpoint number. * @param Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT. +* @Force Force flag to stop/pause transfer. * * @return None. * * @note None. * ****************************************************************************/ -void XUsbPsu_StopTransfer(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir) +void XUsbPsu_StopTransfer(struct XUsbPsu *InstancePtr, u8 UsbEpNum, + u8 Dir, u8 Force) { struct XUsbPsu_Ep *Ept; struct XUsbPsu_EpParams *Params; @@ -526,17 +570,39 @@ * - Wait 100us */ Cmd = XUSBPSU_DEPCMD_ENDTRANSFER; + Cmd |= Force ? XUSBPSU_DEPCMD_HIPRI_FORCERM : 0; Cmd |= XUSBPSU_DEPCMD_CMDIOC; Cmd |= XUSBPSU_DEPCMD_PARAM(Ept->ResourceIndex); - (void)XUsbPsu_SendEpCmd(InstancePtr, Ept->PhyEpNum, Ept->Direction, + (void)XUsbPsu_SendEpCmd(InstancePtr, Ept->UsbEpNum, Ept->Direction, Cmd, Params); - Ept->ResourceIndex = 0U; + if (Force) + Ept->ResourceIndex = 0U; Ept->EpStatus &= ~XUSBPSU_EP_BUSY; XUsbSleep(100U); } /****************************************************************************/ /** +* Query endpoint state and save it in EpSavedState +* +* @param InstancePtr is a pointer to the XUsbPsu instance. +* @param Ept is a pointer to the XUsbPsu pointer structure. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void XUsbPsu_SaveEndpointState(struct XUsbPsu *InstancePtr, struct XUsbPsu_Ep *Ept) +{ + struct XUsbPsu_EpParams *Params = XUsbPsu_GetEpParams(InstancePtr); + XUsbPsu_SendEpCmd(InstancePtr, Ept->UsbEpNum, Ept->Direction, + XUSBPSU_DEPCMD_GETEPSTATE, Params); + Ept->EpSavedState = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DEPCMDPAR2(Ept->PhyEpNum)); +} + +/****************************************************************************/ +/** * Clears Stall on all endpoints. * * @param InstancePtr is a pointer to the XUsbPsu instance. @@ -570,7 +636,7 @@ Ept->EpStatus &= ~XUSBPSU_EP_STALL; - (void)XUsbPsu_SendEpCmd(InstancePtr, Ept->PhyEpNum, + (void)XUsbPsu_SendEpCmd(InstancePtr, Ept->UsbEpNum, Ept->Direction, XUSBPSU_DEPCMD_CLEARSTALL, Params); } @@ -594,6 +660,7 @@ u8 *BufferPtr, u32 BufferLen) { u8 PhyEpNum; + u32 cmd; s32 RetVal; struct XUsbPsu_Trb *TrbPtr; struct XUsbPsu_Ep *Ept; @@ -619,35 +686,98 @@ Ept->BytesTxed = 0U; Ept->BufferPtr = BufferPtr; - TrbPtr = &Ept->EpTrb; + TrbPtr = &Ept->EpTrb[Ept->TrbEnqueue]; Xil_AssertNonvoid(TrbPtr != NULL); + Ept->TrbEnqueue++; + if (Ept->TrbEnqueue == NO_OF_TRB_PER_EP) + Ept->TrbEnqueue = 0; TrbPtr->BufferPtrLow = (UINTPTR)BufferPtr; TrbPtr->BufferPtrHigh = ((UINTPTR)BufferPtr >> 16) >> 16; TrbPtr->Size = BufferLen & XUSBPSU_TRB_SIZE_MASK; - TrbPtr->Ctrl = XUSBPSU_TRBCTL_NORMAL; + + switch (Ept->Type) { + case XUSBPSU_ENDPOINT_XFER_ISOC: + /* + * According to DWC3 datasheet, XUSBPSU_TRBCTL_ISOCHRONOUS and + * XUSBPSU_TRBCTL_CHN fields are only set when request has + * scattered list so these fields are not set over here. + */ + TrbPtr->Ctrl = (XUSBPSU_TRBCTL_ISOCHRONOUS_FIRST + | XUSBPSU_TRB_CTRL_CSP); + + break; + case XUSBPSU_ENDPOINT_XFER_INT: + case XUSBPSU_ENDPOINT_XFER_BULK: + TrbPtr->Ctrl = (XUSBPSU_TRBCTL_NORMAL + | XUSBPSU_TRB_CTRL_LST); + + break; + } TrbPtr->Ctrl |= (XUSBPSU_TRB_CTRL_HWO - | XUSBPSU_TRB_CTRL_LST - | XUSBPSU_TRB_CTRL_IOC - | XUSBPSU_TRB_CTRL_ISP_IMI); + | XUSBPSU_TRB_CTRL_IOC + | XUSBPSU_TRB_CTRL_ISP_IMI); - Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); - Xil_DCacheFlushRange((INTPTR)BufferPtr, BufferLen); + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); + Xil_DCacheFlushRange((INTPTR)BufferPtr, BufferLen); + } Params = XUsbPsu_GetEpParams(InstancePtr); Xil_AssertNonvoid(Params != NULL); Params->Param0 = 0U; Params->Param1 = (UINTPTR)TrbPtr; + if (Ept->EpStatus & XUSBPSU_EP_BUSY) { + cmd = XUSBPSU_DEPCMD_UPDATETRANSFER; + cmd |= XUSBPSU_DEPCMD_PARAM(Ept->ResourceIndex); + } else { + if (Ept->Type == XUSBPSU_ENDPOINT_XFER_ISOC) { + BufferPtr += BufferLen; + struct XUsbPsu_Trb *TrbTempNext; + TrbTempNext = &Ept->EpTrb[Ept->TrbEnqueue]; + Xil_AssertNonvoid(TrbTempNext != NULL); + + Ept->TrbEnqueue++; + if (Ept->TrbEnqueue == NO_OF_TRB_PER_EP) + Ept->TrbEnqueue = 0; + TrbTempNext->BufferPtrLow = (UINTPTR)BufferPtr; + TrbTempNext->BufferPtrHigh = ((UINTPTR)BufferPtr >> 16) >> 16; + TrbTempNext->Size = BufferLen & XUSBPSU_TRB_SIZE_MASK; + + TrbTempNext->Ctrl = (XUSBPSU_TRBCTL_ISOCHRONOUS_FIRST + | XUSBPSU_TRB_CTRL_CSP + | XUSBPSU_TRB_CTRL_HWO + | XUSBPSU_TRB_CTRL_IOC + | XUSBPSU_TRB_CTRL_ISP_IMI); + + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)TrbTempNext, + sizeof(struct XUsbPsu_Trb)); + Xil_DCacheFlushRange((INTPTR)BufferPtr, BufferLen); + } + + } + + cmd = XUSBPSU_DEPCMD_STARTTRANSFER; + cmd |= XUSBPSU_DEPCMD_PARAM(Ept->CurUf); + } + RetVal = XUsbPsu_SendEpCmd(InstancePtr, UsbEp, Ept->Direction, - XUSBPSU_DEPCMD_STARTTRANSFER, Params); + cmd, Params); if (RetVal != XST_SUCCESS) { return XST_FAILURE; } - Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr, - Ept->UsbEpNum, - Ept->Direction); + + if (!(Ept->EpStatus & XUSBPSU_EP_BUSY)) { + Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr, + Ept->UsbEpNum, + Ept->Direction); + + Ept->EpStatus |= XUSBPSU_EP_BUSY; + } + return XST_SUCCESS; } @@ -656,7 +786,7 @@ * Initiates DMA to receive data on Endpoint from Host. * * @param InstancePtr is a pointer to the XUsbPsu instance. -* @param EpNum is USB endpoint number. +* @param UsbEp is USB endpoint number. * @param BufferPtr is pointer to data. * @param Length is length of data to be received. * @@ -669,7 +799,8 @@ u8 *BufferPtr, u32 Length) { u8 PhyEpNum; - u32 Size; + u32 cmd; + u32 Size; s32 RetVal; struct XUsbPsu_Trb *TrbPtr; struct XUsbPsu_Ep *Ept; @@ -706,36 +837,100 @@ Ept->UnalignedTx = 1U; } - TrbPtr = &Ept->EpTrb; + TrbPtr = &Ept->EpTrb[Ept->TrbEnqueue]; Xil_AssertNonvoid(TrbPtr != NULL); + Ept->TrbEnqueue++; + if (Ept->TrbEnqueue == NO_OF_TRB_PER_EP) + Ept->TrbEnqueue = 0; + TrbPtr->BufferPtrLow = (UINTPTR)BufferPtr; TrbPtr->BufferPtrHigh = ((UINTPTR)BufferPtr >> 16) >> 16; TrbPtr->Size = Size; - TrbPtr->Ctrl = XUSBPSU_TRBCTL_NORMAL; + + switch (Ept->Type) { + case XUSBPSU_ENDPOINT_XFER_ISOC: + /* + * According to Linux driver, XUSBPSU_TRBCTL_ISOCHRONOUS and + * XUSBPSU_TRBCTL_CHN fields are only set when request has + * scattered list so these fields are not set over here. + */ + TrbPtr->Ctrl = (XUSBPSU_TRBCTL_ISOCHRONOUS_FIRST + | XUSBPSU_TRB_CTRL_CSP); + + break; + case XUSBPSU_ENDPOINT_XFER_INT: + case XUSBPSU_ENDPOINT_XFER_BULK: + TrbPtr->Ctrl = (XUSBPSU_TRBCTL_NORMAL + | XUSBPSU_TRB_CTRL_LST); + + break; + } TrbPtr->Ctrl |= (XUSBPSU_TRB_CTRL_HWO - | XUSBPSU_TRB_CTRL_LST - | XUSBPSU_TRB_CTRL_IOC - | XUSBPSU_TRB_CTRL_ISP_IMI); + | XUSBPSU_TRB_CTRL_IOC + | XUSBPSU_TRB_CTRL_ISP_IMI); - Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); - Xil_DCacheInvalidateRange((INTPTR)BufferPtr, Length); + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); + Xil_DCacheInvalidateRange((INTPTR)BufferPtr, Length); + } Params = XUsbPsu_GetEpParams(InstancePtr); Xil_AssertNonvoid(Params != NULL); Params->Param0 = 0U; Params->Param1 = (UINTPTR)TrbPtr; + if (Ept->EpStatus & XUSBPSU_EP_BUSY) { + cmd = XUSBPSU_DEPCMD_UPDATETRANSFER; + cmd |= XUSBPSU_DEPCMD_PARAM(Ept->ResourceIndex); + } else { + if (Ept->Type == XUSBPSU_ENDPOINT_XFER_ISOC) { + BufferPtr += Length; + struct XUsbPsu_Trb *TrbTempNext; + TrbTempNext = &Ept->EpTrb[Ept->TrbEnqueue]; + Xil_AssertNonvoid(TrbTempNext != NULL); + + Ept->TrbEnqueue++; + if (Ept->TrbEnqueue == NO_OF_TRB_PER_EP) + Ept->TrbEnqueue = 0; + TrbTempNext->BufferPtrLow = (UINTPTR)BufferPtr; + TrbTempNext->BufferPtrHigh = ((UINTPTR)BufferPtr >> 16) >> 16; + TrbTempNext->Size = Length & XUSBPSU_TRB_SIZE_MASK; + + TrbTempNext->Ctrl = (XUSBPSU_TRBCTL_ISOCHRONOUS_FIRST + | XUSBPSU_TRB_CTRL_CSP + | XUSBPSU_TRB_CTRL_HWO + | XUSBPSU_TRB_CTRL_IOC + | XUSBPSU_TRB_CTRL_ISP_IMI); + + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)TrbTempNext, + sizeof(struct XUsbPsu_Trb)); + Xil_DCacheFlushRange((INTPTR)BufferPtr, Length); + } + + } + + cmd = XUSBPSU_DEPCMD_STARTTRANSFER; + cmd |= XUSBPSU_DEPCMD_PARAM(Ept->CurUf); + } + RetVal = XUsbPsu_SendEpCmd(InstancePtr, UsbEp, Ept->Direction, - XUSBPSU_DEPCMD_STARTTRANSFER, Params); + cmd, Params); if (RetVal != XST_SUCCESS) { return XST_FAILURE; } - Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr, - Ept->UsbEpNum, - Ept->Direction); + + if (!(Ept->EpStatus & XUSBPSU_EP_BUSY)) { + Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr, + Ept->UsbEpNum, + Ept->Direction); + + Ept->EpStatus |= XUSBPSU_EP_BUSY; + } + return XST_SUCCESS; } @@ -744,7 +939,7 @@ * Stalls an Endpoint. * * @param InstancePtr is a pointer to the XUsbPsu instance. -* @param EpNum is USB endpoint number. +* @param Epnum is USB endpoint number. * @param Dir is direction. * * @return None. @@ -768,7 +963,7 @@ Params = XUsbPsu_GetEpParams(InstancePtr); Xil_AssertVoid(Params != NULL); - (void)XUsbPsu_SendEpCmd(InstancePtr, Ept->PhyEpNum, Ept->Direction, + (void)XUsbPsu_SendEpCmd(InstancePtr, Ept->UsbEpNum, Ept->Direction, XUSBPSU_DEPCMD_SETSTALL, Params); Ept->EpStatus |= XUSBPSU_EP_STALL; @@ -803,7 +998,7 @@ Params = XUsbPsu_GetEpParams(InstancePtr); Xil_AssertVoid(Params != NULL); - (void)XUsbPsu_SendEpCmd(InstancePtr, Ept->PhyEpNum, Ept->Direction, + (void)XUsbPsu_SendEpCmd(InstancePtr, Ept->UsbEpNum, Ept->Direction, XUSBPSU_DEPCMD_CLEARSTALL, Params); Ept->EpStatus &= ~XUSBPSU_EP_STALL; @@ -895,10 +1090,20 @@ Epnum = Event->Epnumber; Ept = &InstancePtr->eps[Epnum]; Dir = Ept->Direction; - TrbPtr = &Ept->EpTrb; + TrbPtr = &Ept->EpTrb[Ept->TrbDequeue]; Xil_AssertVoid(TrbPtr != NULL); - Xil_DCacheInvalidateRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); + Ept->TrbDequeue++; + if (Ept->TrbDequeue == NO_OF_TRB_PER_EP) + Ept->TrbDequeue = 0; + + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) + Xil_DCacheInvalidateRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); + + if (Event->Endpoint_Event == XUSBPSU_DEPEVT_XFERCOMPLETE) { + Ept->EpStatus &= ~(XUSBPSU_EP_BUSY); + Ept->ResourceIndex = 0; + } Length = TrbPtr->Size & XUSBPSU_TRB_SIZE_MASK; @@ -909,19 +1114,64 @@ Ept->BytesTxed = Ept->RequestedBytes - Length; } else if (Dir == XUSBPSU_EP_DIR_OUT) { if (Ept->UnalignedTx == 1U) { - Ept->BytesTxed = Ept->RequestedBytes; + Ept->BytesTxed = (u32)roundup(Ept->RequestedBytes, + Ept->MaxSize); + Ept->BytesTxed -= Length; Ept->UnalignedTx = 0U; + } else { + /* + * Get the actual number of bytes transmitted + * by host + */ + Ept->BytesTxed = Ept->RequestedBytes - Length; } } } if (Dir == XUSBPSU_EP_DIR_OUT) { /* Invalidate Cache */ - Xil_DCacheInvalidateRange((INTPTR)Ept->BufferPtr, Ept->BytesTxed); + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) + Xil_DCacheInvalidateRange((INTPTR)Ept->BufferPtr, Ept->BytesTxed); } if (Ept->Handler != NULL) { - Ept->Handler(InstancePtr, Ept->RequestedBytes, Ept->BytesTxed); + Ept->Handler(InstancePtr->AppData, Ept->RequestedBytes, Ept->BytesTxed); + } +} + +/****************************************************************************/ +/** +* For Isochronous transfer, get the microframe time and calls respective Endpoint +* handler. +* +* @param InstancePtr is a pointer to the XUsbPsu instance. +* @param Event is a pointer to the Endpoint event occurred in core. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XUsbPsu_EpXferNotReady(struct XUsbPsu *InstancePtr, + const struct XUsbPsu_Event_Epevt *Event) +{ + struct XUsbPsu_Ep *Ept; + u32 Epnum; + u32 CurUf, Mask; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(Event != NULL); + + Epnum = Event->Epnumber; + Ept = &InstancePtr->eps[Epnum]; + + if (Ept->Type == XUSBPSU_ENDPOINT_XFER_ISOC) { + Mask = ~(1 << (Ept->Interval - 1)); + CurUf = Event->Parameters & Mask; + Ept->CurUf = CurUf + (Ept->Interval * 4); + if (Ept->Handler != NULL) { + Ept->Handler(InstancePtr->AppData, 0, 0); + } } } /** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_endpoint.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_endpoint.h similarity index 97% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_endpoint.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_endpoint.h index 2998378..b80da48 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_endpoint.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_endpoint.h
@@ -33,7 +33,7 @@ /** * * @file xusbps_endpoint.h -* @addtogroup usbpsu_v1_0 +* @addtogroup usbpsu_v1_3 * @{ * * This is an internal file containing the definitions for endpoints. It is @@ -46,6 +46,9 @@ * Ver Who Date Changes * ----- ---- -------- -------------------------------------------------------- * 1.0 sg 06/06/16 First release + * 1.4 bk 12/01/18 Modify USBPSU driver code to fit USB common example code + * for all USB IPs. + * * </pre> * ******************************************************************************/ @@ -59,7 +62,7 @@ /***************************** Include Files *********************************/ #include "xil_cache.h" -#include "xusbpsu.h" +#include "xusb_wrapper.h" #include "xil_types.h" /**************************** Type Definitions *******************************/
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_g.c similarity index 88% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_g.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_g.c index 41a9b8c..4019d76 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_g.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_g.c
@@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,11 +44,12 @@ * The configuration table for devices */ -XUsbPsu_Config XUsbPsu_ConfigTable[] = +XUsbPsu_Config XUsbPsu_ConfigTable[XPAR_XUSBPSU_NUM_INSTANCES] = { { - XPAR_PSU_USB_0_DEVICE_ID, - XPAR_PSU_USB_0_BASEADDR + XPAR_PSU_USB_XHCI_0_DEVICE_ID, + XPAR_PSU_USB_XHCI_0_BASEADDR, + XPAR_PSU_USB_XHCI_0_IS_CACHE_COHERENT } };
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_hibernation.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_hibernation.c new file mode 100644 index 0000000..20f53c9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_hibernation.c
@@ -0,0 +1,688 @@ +/****************************************************************************** +* +* Copyright (C) 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xusbpsu_hibernation.c +* +* This patch adds hibernation support to usbpsu driver when dwc3 is operating +* as a gadget +* +* <pre> +* +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ----- -------- ----------------------------------------------------- +* 1.0 Mayank 12/01/18 First release +* +* </pre> +* +*****************************************************************************/ + +/***************************** Include Files ********************************/ + +#include "xusbpsu.h" +#include "xusbpsu_hw.h" +#include "xusbpsu_endpoint.h" + +/************************** Constant Definitions *****************************/ + +#define NUM_OF_NONSTICKY_REGS 27 + +#define XUSBPSU_HIBER_SCRATCHBUF_SIZE 4096U + +#define XUSBPSU_NON_STICKY_SAVE_RETRIES 500U +#define XUSBPSU_PWR_STATE_RETRIES 1500U +#define XUSBPSU_CTRL_RDY_RETRIES 5000U +#define XUSBPSU_TIMEOUT 1000U + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + + +/************************** Variable Definitions *****************************/ + +static u8 ScratchBuf[XUSBPSU_HIBER_SCRATCHBUF_SIZE]; + +/* Registers saved during hibernation and restored at wakeup */ +static u32 save_reg_addr[] = { + XUSBPSU_DCTL, + XUSBPSU_DCFG, + XUSBPSU_DEVTEN, + XUSBPSU_GSBUSCFG0, + XUSBPSU_GSBUSCFG1, + XUSBPSU_GCTL, + XUSBPSU_GTXTHRCFG, + XUSBPSU_GRXTHRCFG, + XUSBPSU_GTXFIFOSIZ(0), + XUSBPSU_GTXFIFOSIZ(1), + XUSBPSU_GTXFIFOSIZ(2), + XUSBPSU_GTXFIFOSIZ(3), + XUSBPSU_GTXFIFOSIZ(4), + XUSBPSU_GTXFIFOSIZ(5), + XUSBPSU_GTXFIFOSIZ(6), + XUSBPSU_GTXFIFOSIZ(7), + XUSBPSU_GTXFIFOSIZ(8), + XUSBPSU_GTXFIFOSIZ(9), + XUSBPSU_GTXFIFOSIZ(10), + XUSBPSU_GTXFIFOSIZ(11), + XUSBPSU_GTXFIFOSIZ(12), + XUSBPSU_GTXFIFOSIZ(13), + XUSBPSU_GTXFIFOSIZ(14), + XUSBPSU_GTXFIFOSIZ(15), + XUSBPSU_GRXFIFOSIZ(0), + XUSBPSU_GUSB3PIPECTL(0), + XUSBPSU_GUSB2PHYCFG(0), +}; +static u32 saved_regs[NUM_OF_NONSTICKY_REGS]; + +/*****************************************************************************/ +/** +* Save non sticky registers +* +* @param InstancePtr is a pointer to the XUsbPsu instance to be worked +* on. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +static void save_regs(struct XUsbPsu *InstancePtr) +{ + u32 i; + + for (i = 0; i < NUM_OF_NONSTICKY_REGS; i++) + saved_regs[i] = XUsbPsu_ReadReg(InstancePtr, save_reg_addr[i]); +} + +/*****************************************************************************/ +/** +* Restore non sticky registers +* +* @param InstancePtr is a pointer to the XUsbPsu instance to be worked +* on. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +static void restore_regs(struct XUsbPsu *InstancePtr) +{ + u32 i; + + for (i = 0; i < NUM_OF_NONSTICKY_REGS; i++) + XUsbPsu_WriteReg(InstancePtr, save_reg_addr[i], saved_regs[i]); +} + +/*****************************************************************************/ +/** +* Send generic command for gadget +* +* @param InstancePtr is a pointer to the XUsbPsu instance to be worked +* on. +* @param cmd is command to be sent +* @param param is parameter for the command, to be written in DGCMDPAR +* register +* +* @return +* - XST_SUCCESS on success +* - XST_FAILURE on timeout +* - XST_REGISTER_ERROR on status error +* +* @note None. +* +******************************************************************************/ +s32 XUsbPsu_SendGadgetGenericCmd(struct XUsbPsu *InstancePtr, u32 cmd, + u32 param) +{ + u32 RegVal, retry = 500; + XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DGCMDPAR, param); + XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DGCMD, cmd | XUSBPSU_DGCMD_CMDACT); + + do { + RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DGCMD); + if (!(RegVal & XUSBPSU_DGCMD_CMDACT)) { + if (XUSBPSU_DGCMD_STATUS(RegVal)) + return XST_REGISTER_ERROR; + return 0; + } + } while (--retry); + + return XST_FAILURE; +} + +/*****************************************************************************/ +/** +* Sets scratchpad buffers +* +* @param InstancePtr is a pointer to the XUsbPsu instance to be worked +* on. +* +* @return XST_SUCCESS on success or else error code +* +* @note None. +* +******************************************************************************/ +s32 XUsbPsu_SetupScratchpad(struct XUsbPsu *InstancePtr) +{ + s32 Ret; + Ret = XUsbPsu_SendGadgetGenericCmd(InstancePtr, + XUSBPSU_DGCMD_SET_SCRATCHPAD_ADDR_LO, (UINTPTR)ScratchBuf & 0xffffffff); + if (Ret) { + xil_printf("Failed to set scratchpad low addr: %d\n", Ret); + return Ret; + } + + Ret = XUsbPsu_SendGadgetGenericCmd(InstancePtr, + XUSBPSU_DGCMD_SET_SCRATCHPAD_ADDR_HI, ((UINTPTR)ScratchBuf >> 16) >> 16); + if (Ret) { + xil_printf("Failed to set scratchpad high addr: %d\n", Ret); + return Ret; + } + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* Initialize to handle hibernation event when it comes +* +* @param InstancePtr is a pointer to the XUsbPsu instance to be worked +* on. +* +* @return none +* +* @note None. +* +******************************************************************************/ +void XUsbPsu_InitHibernation(struct XUsbPsu *InstancePtr) +{ + u32 RegVal; + + InstancePtr->IsHibernated = 0; + + memset(ScratchBuf, 0, sizeof(ScratchBuf)); + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) + Xil_DCacheFlushRange((INTPTR)ScratchBuf, XUSBPSU_HIBER_SCRATCHBUF_SIZE); + + XUsbPsu_SetupScratchpad(InstancePtr); + + /* enable PHY suspend */ + RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GUSB2PHYCFG(0)); + RegVal |= XUSBPSU_GUSB2PHYCFG_SUSPHY; + XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GUSB2PHYCFG(0), RegVal); + + RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GUSB3PIPECTL(0)); + RegVal |= XUSBPSU_GUSB3PIPECTL_SUSPHY; + XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GUSB3PIPECTL(0), RegVal); +} + +/*****************************************************************************/ +/** +* Handle hibernation event +* +* @param InstancePtr is a pointer to the XUsbPsu instance to be worked +* on. +* +* @return none +* +* @note None. +* +******************************************************************************/ +void Xusbpsu_HibernationIntr(struct XUsbPsu *InstancePtr) +{ + u8 EpNum; + u32 RegVal; + s32 retries; + XusbPsuLinkState LinkState; + + /* sanity check */ + switch(XUsbPsu_GetLinkState(InstancePtr)) { + case XUSBPSU_LINK_STATE_SS_DIS: + case XUSBPSU_LINK_STATE_U3: + break; + default: + /* fake hiber interrupt */ + xil_printf("got fake interrupt\r\n"); + return; + }; + + if (InstancePtr->Ep0State == XUSBPSU_EP0_SETUP_PHASE) { + XUsbPsu_StopTransfer(InstancePtr, 0, XUSBPSU_EP_DIR_OUT, TRUE); + XUsbPsu_RecvSetup(InstancePtr); + } + + /* stop active transfers for all endpoints including control + * endpoints force rm bit should be 0 when we do this */ + for (EpNum = 0; EpNum < XUSBPSU_ENDPOINTS_NUM; EpNum++) { + struct XUsbPsu_Ep *Ept; + + Ept = &InstancePtr->eps[EpNum]; + if (!Ept) + continue; + + if (!(Ept->EpStatus & XUSBPSU_EP_ENABLED)) + continue; + + /* save srsource index for later use */ + XUsbPsu_StopTransfer(InstancePtr, Ept->UsbEpNum, + Ept->Direction, FALSE); + + XUsbPsu_SaveEndpointState(InstancePtr, Ept); + } + + /* + * ack events, don't process them; h/w decrements the count by the value + * written + */ + RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GEVNTCOUNT(0)); + XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTCOUNT(0), RegVal); + InstancePtr->Evt.Count = 0; + InstancePtr->Evt.Flags &= ~XUSBPSU_EVENT_PENDING; + + if (XUsbPsu_Stop(InstancePtr)) { + xil_printf("Failed to stop USB core\r\n"); + return; + } + + RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL); + + /* Check the link state and if it is disconnected, set + * KEEP_CONNECT to 0 + */ + LinkState = XUsbPsu_GetLinkState(InstancePtr); + if (LinkState == XUSBPSU_LINK_STATE_SS_DIS) { + RegVal &= ~XUSBPSU_DCTL_KEEP_CONNECT; + XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal); + + /* update LinkState to be used while wakeup */ + InstancePtr->LinkState = XUSBPSU_LINK_STATE_SS_DIS; + } + + save_regs(InstancePtr); + + /* ask core to save state */ + RegVal |= XUSBPSU_DCTL_CSS; + XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal); + + /* wait till core saves */ + if (XUsbPsu_Wait_Clear_Timeout(InstancePtr, XUSBPSU_DSTS, + XUSBPSU_DSTS_SSS, XUSBPSU_NON_STICKY_SAVE_RETRIES) == XST_FAILURE) { + xil_printf("Failed to save core state\r\n"); + return; + } + + /* Enable PME to wakeup from hibernation */ + XUsbPsu_WriteVendorReg(XIL_PME_ENABLE, XIL_PME_ENABLE_SIG_GEN); + + /* change power state to D3 */ + XUsbPsu_WriteVendorReg(XIL_REQ_PWR_STATE, XIL_REQ_PWR_STATE_D3); + + /* wait till current state is changed to D3 */ + retries = XUSBPSU_PWR_STATE_RETRIES; + do { + RegVal = XUsbPsu_ReadVendorReg(XIL_CUR_PWR_STATE); + if ((RegVal & XIL_CUR_PWR_STATE_BITMASK) == XIL_CUR_PWR_STATE_D3) + break; + + XUsbSleep(XUSBPSU_TIMEOUT); + } while (--retries); + + if (retries < 0) { + xil_printf("Failed to change power state to D3\r\n"); + return; + } + XUsbSleep(XUSBPSU_TIMEOUT); + + RegVal = XUsbPsu_ReadLpdReg(RST_LPD_TOP); + if (InstancePtr->ConfigPtr->DeviceId == XPAR_XUSBPSU_0_DEVICE_ID) + XUsbPsu_WriteLpdReg(RST_LPD_TOP, RegVal | USB0_CORE_RST); + + InstancePtr->IsHibernated = 1; + xil_printf("Hibernated!\r\n"); +} + +/*****************************************************************************/ +/** +* Restarts transfer for active endpoint +* +* @param InstancePtr is a pointer to the XUsbPsu instance to be worked +* on. +* @param EpNum is an endpoint number. +* +* @return XST_SUCCESS on success or else XST_FAILURE. +* +* @note None. +* +******************************************************************************/ +static s32 XUsbPsu_RestartEp(struct XUsbPsu *InstancePtr, u8 EpNum) +{ + struct XUsbPsu_EpParams *Params; + struct XUsbPsu_Trb *TrbPtr; + struct XUsbPsu_Ep *Ept; + u32 Cmd; + s32 Ret; + + Xil_AssertNonvoid(InstancePtr != NULL); + + Params = XUsbPsu_GetEpParams(InstancePtr); + Xil_AssertNonvoid(Params != NULL); + + Ept = &InstancePtr->eps[EpNum]; + + /* check if we need to restart transfer */ + if (!Ept->ResourceIndex && Ept->PhyEpNum) + return XST_SUCCESS; + + if (Ept->UsbEpNum) { + TrbPtr = &Ept->EpTrb[Ept->TrbDequeue]; + } else { + TrbPtr = &InstancePtr->Ep0_Trb; + } + + Xil_AssertNonvoid(TrbPtr != NULL); + + TrbPtr->Ctrl |= XUSBPSU_TRB_CTRL_HWO; + + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); + Xil_DCacheInvalidateRange((INTPTR)Ept->BufferPtr, Ept->RequestedBytes); + } + + Params->Param0 = 0U; + Params->Param1 = (UINTPTR)TrbPtr; + + Cmd = XUSBPSU_DEPCMD_STARTTRANSFER; + + Ret = XUsbPsu_SendEpCmd(InstancePtr, Ept->UsbEpNum, Ept->Direction, + Cmd, Params); + if (Ret) + return XST_FAILURE; + + Ept->EpStatus |= XUSBPSU_EP_BUSY; + Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr, + Ept->UsbEpNum, Ept->Direction); + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* Restarts EP0 endpoint +* +* @param InstancePtr is a pointer to the XUsbPsu instance to be worked +* on. +* +* @return XST_SUCCESS on success or else XST_FAILURE. +* +* @note None. +* +******************************************************************************/ +static s32 XUsbPsu_RestoreEp0(struct XUsbPsu *InstancePtr) +{ + struct XUsbPsu_Ep *Ept; + s32 Ret; + u8 EpNum; + + for (EpNum = 0; EpNum < 2; EpNum++) { + Ept = &InstancePtr->eps[EpNum]; + + if (!Ept) + continue; + + if (!(Ept->EpStatus & XUSBPSU_EP_ENABLED)) + continue; + + Ret = XUsbPsu_EpEnable(InstancePtr, Ept->UsbEpNum, + Ept->Direction, Ept->MaxSize, Ept->Type, TRUE); + if (Ret) { + xil_printf("Failed to enable EP %d on wakeup: %d\r\n", + EpNum, Ret); + return XST_FAILURE; + } + + if (Ept->EpStatus & XUSBPSU_EP_STALL) { + XUsbPsu_Ep0StallRestart(InstancePtr); + } else { + Ret = XUsbPsu_RestartEp(InstancePtr, Ept->PhyEpNum); + if (Ret) { + xil_printf("Failed to restart EP %d on wakeup: %d\r\n", + EpNum, Ret); + return XST_FAILURE; + } + } + } + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* Restarts non EP0 endpoints +* +* @param InstancePtr is a pointer to the XUsbPsu instance to be worked +* on. +* +* @return XST_SUCCESS on success or else XST_FAILURE. +* +* @note None. +* +******************************************************************************/ +static s32 XUsbPsu_RestoreEps(struct XUsbPsu *InstancePtr) +{ + struct XUsbPsu_Ep *Ept; + s32 Ret; + u8 EpNum; + + for (EpNum = 2; EpNum < XUSBPSU_ENDPOINTS_NUM; EpNum++) { + Ept = &InstancePtr->eps[EpNum]; + + if (!Ept) + continue; + + if (!(Ept->EpStatus & XUSBPSU_EP_ENABLED)) + continue; + + Ret = XUsbPsu_EpEnable(InstancePtr, Ept->UsbEpNum, + Ept->Direction, Ept->MaxSize, Ept->Type, TRUE); + if (Ret) { + xil_printf("Failed to enable EP %d on wakeup: %d\r\n", + EpNum, Ret); + return XST_FAILURE; + } + } + + for (EpNum = 2; EpNum < XUSBPSU_ENDPOINTS_NUM; EpNum++) { + Ept = &InstancePtr->eps[EpNum]; + + if (!Ept) + continue; + + if (!(Ept->EpStatus & XUSBPSU_EP_ENABLED)) + continue; + + if (Ept->EpStatus & XUSBPSU_EP_STALL) { + XUsbPsu_EpSetStall(InstancePtr, Ept->UsbEpNum, Ept->Direction); + } else { + Ret = XUsbPsu_RestartEp(InstancePtr, Ept->PhyEpNum); + if (Ret) { + xil_printf("Failed to restart EP %d on wakeup: %d\r\n", + EpNum, Ret); + return XST_FAILURE; + } + } + } + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* Handle wakeup event +* +* @param InstancePtr is a pointer to the XUsbPsu instance to be worked +* on. +* +* @return none +* +* @note None. +* +******************************************************************************/ +void XUsbPsu_WakeupIntr(struct XUsbPsu *InstancePtr) +{ + u32 RegVal, link_state; + s32 retries; + char enter_hiber; + + RegVal = XUsbPsu_ReadLpdReg(RST_LPD_TOP); + if (InstancePtr->ConfigPtr->DeviceId == XPAR_XUSBPSU_0_DEVICE_ID) + XUsbPsu_WriteLpdReg(RST_LPD_TOP, RegVal & ~USB0_CORE_RST); + + /* change power state to D0 */ + XUsbPsu_WriteVendorReg(XIL_REQ_PWR_STATE, XIL_REQ_PWR_STATE_D0); + + /* wait till current state is changed to D0 */ + retries = XUSBPSU_PWR_STATE_RETRIES; + do { + RegVal = XUsbPsu_ReadVendorReg(XIL_CUR_PWR_STATE); + if ((RegVal & XIL_CUR_PWR_STATE_BITMASK) == XIL_CUR_PWR_STATE_D0) + break; + + XUsbSleep(XUSBPSU_TIMEOUT); + } while (--retries); + + if (retries < 0) { + xil_printf("Failed to change power state to D0\r\n"); + return; + } + + /* ask core to restore non-sticky registers */ + XUsbPsu_SetupScratchpad(InstancePtr); + + RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL); + RegVal |= XUSBPSU_DCTL_CRS; + XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal); + + /* wait till non-sticky registers are restored */ + if (XUsbPsu_Wait_Clear_Timeout(InstancePtr, XUSBPSU_DSTS, + XUSBPSU_DSTS_RSS, XUSBPSU_NON_STICKY_SAVE_RETRIES) == XST_FAILURE) { + xil_printf("Failed to restore USB core\r\n"); + return; + } + + restore_regs(InstancePtr); + + /* setup event buffers */ + XUsbPsu_EventBuffersSetup(InstancePtr); + + /* nothing to do when in OTG host mode */ + if (XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GSTS) & XUSBPSU_GSTS_CUR_MODE) + return; + + if (XUsbPsu_RestoreEp0(InstancePtr)) { + xil_printf("Failed to restore EP0\r\n"); + return; + } + + /* start controller */ + if (XUsbPsu_Start(InstancePtr)) { + xil_printf("Failed to start core on wakeup\r\n"); + return; + } + + /* Wait until device controller is ready */ + if (XUsbPsu_Wait_Clear_Timeout(InstancePtr, XUSBPSU_DSTS, + XUSBPSU_DSTS_DCNRD, XUSBPSU_CTRL_RDY_RETRIES) == XST_FAILURE) { + xil_printf("Failed to ready device controller\r\n"); + return; + } + + /* + * there can be suprious wakeup events , so wait for some time and check + * the link state + */ + XUsbSleep(XUSBPSU_TIMEOUT * 10); + + link_state = XUsbPsu_GetLinkState(InstancePtr); + + switch(link_state) { + case XUSBPSU_LINK_STATE_RESET: + RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DSTS); + RegVal &= ~XUSBPSU_DCFG_DEVADDR_MASK; + XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DSTS, RegVal); + + if (XUsbPsu_SetLinkState(InstancePtr, XUSBPSU_LINK_STATE_RECOV)) { + xil_printf("Failed to put link in Recovery\r\n"); + return; + } + break; + case XUSBPSU_LINK_STATE_SS_DIS: + RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL); + RegVal &= ~XUSBPSU_DCTL_KEEP_CONNECT; + XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal); + + /* fall Through */ + case XUSBPSU_LINK_STATE_U3: + /* enter hibernation again */ + enter_hiber = 1; + break; + default: + if (XUsbPsu_SetLinkState(InstancePtr, XUSBPSU_LINK_STATE_RECOV)) { + xil_printf("Failed to put link in Recovery\r\n"); + return; + } + break; + }; + + if (XUsbPsu_RestoreEps(InstancePtr)) { + xil_printf("Failed to restore EPs\r\n"); + return; + } + + InstancePtr->IsHibernated = 0; + + if (enter_hiber) { + Xusbpsu_HibernationIntr(InstancePtr); + return; + } + + xil_printf("We are back from hibernation!\r\n"); +} +/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_hw.h similarity index 83% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_hw.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_hw.h index db612b0..344f919 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_hw.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_hw.h
@@ -33,7 +33,7 @@ /** * * @file xusbpsu_hw.h -* @addtogroup usbpsu_v1_0 +* @addtogroup usbpsu_v1_3 * @{ * * <pre> @@ -43,6 +43,7 @@ * Ver Who Date Changes * ----- ----- -------- ----------------------------------------------------- * 1.0 sg 06/06/16 First release +* 1.4 myk 12/01/18 Added support of hibernation * * </pre> * @@ -174,6 +175,7 @@ /* Global Status Register Device Interrupt Mask */ #define XUSBPSU_GSTS_DEVICE_IP_MASK 0x00000040 +#define XUSBPSU_GSTS_CUR_MODE (0x00000001U << 0) /* Global USB2 PHY Configuration Register */ #define XUSBPSU_GUSB2PHYCFG_PHYSOFTRST (0x00000001U << 31) @@ -308,8 +310,28 @@ #define XUSBPSU_PORTMSC_30_U1_TIMEOUT_MASK (0xffU << 0) #define XUSBPSU_PORTMSC_30_U1_TIMEOUT_SHIFT (0U) +/* Register for LPD block */ +#define RST_LPD_TOP 0x23C +#define USB0_CORE_RST (1 << 6) +#define USB1_CORE_RST (1 << 7) -/*@}*/ +/* Vendor registers for Xilinx */ +#define XIL_CUR_PWR_STATE 0x00 +#define XIL_PME_ENABLE 0x34 +#define XIL_REQ_PWR_STATE 0x3c +#define XIL_PWR_CONFIG_USB3 0x48 + +#define XIL_REQ_PWR_STATE_D0 0 +#define XIL_REQ_PWR_STATE_D3 3 +#define XIL_PME_ENABLE_SIG_GEN 1 +#define XIL_CUR_PWR_STATE_D0 0 +#define XIL_CUR_PWR_STATE_D3 3 +#define XIL_CUR_PWR_STATE_BITMASK 0x03 + +#define VENDOR_BASE_ADDRESS 0xFF9D0000 +#define LPD_BASE_ADDRESS 0xFF5E0000 + + /*@}*/ /**************************** Type Definitions *******************************/ @@ -353,6 +375,76 @@ #define XUsbPsu_WriteReg(InstancePtr, Offset, Data) \ Xil_Out32((InstancePtr)->ConfigPtr->BaseAddress + (u32)(Offset), (u32)(Data)) +/*****************************************************************************/ +/** +* +* Read a vendor register of the USBPS8 device. +* +* @param Offset is the offset of the register to read. +* +* @return The contents of the register. +* +* @note C-style Signature: +* u32 XUsbPsu_ReadVendorReg(struct XUsbPsu *InstancePtr, u32 Offset); +* +******************************************************************************/ +#define XUsbPsu_ReadVendorReg(Offset) \ + Xil_In32(VENDOR_BASE_ADDRESS + (u32)(Offset)) + +/*****************************************************************************/ +/** +* +* Write a Vendor register of the USBPS8 device. +* +* @param RegOffset is the offset of the register to write. +* @param Data is the value to write to the register. +* +* @return None. +* +* @note C-style Signature: +* void XUsbPsu_WriteVendorReg(struct XUsbPsu *InstancePtr, +* u32 Offset,u32 Data) +* +******************************************************************************/ +#define XUsbPsu_WriteVendorReg(Offset, Data) \ + Xil_Out32(VENDOR_BASE_ADDRESS + (u32)(Offset), (u32)(Data)) + +/*****************************************************************************/ +/** +* +* Read a LPD register of the USBPS8 device. +* +* @param InstancePtr is a pointer to the XUsbPsu instance. +* @param Offset is the offset of the register to read. +* +* @return The contents of the register. +* +* @note C-style Signature: +* u32 XUsbPsu_ReadLpdReg(struct XUsbPsu *InstancePtr, u32 Offset); +* +******************************************************************************/ +#define XUsbPsu_ReadLpdReg(Offset) \ + Xil_In32(LPD_BASE_ADDRESS + (u32)(Offset)) + +/*****************************************************************************/ +/** +* +* Write a LPD register of the USBPS8 device. +* +* @param InstancePtr is a pointer to the XUsbPsu instance. +* @param RegOffset is the offset of the register to write. +* @param Data is the value to write to the register. +* +* @return None. +* +* @note C-style Signature: +* void XUsbPsu_WriteLpdReg(struct XUsbPsu *InstancePtr, +* u32 Offset,u32 Data) +* +******************************************************************************/ +#define XUsbPsu_WriteLpdReg(Offset, Data) \ + Xil_Out32(LPD_BASE_ADDRESS + (u32)(Offset), (u32)(Data)) + /************************** Function Prototypes ******************************/ #ifdef __cplusplus
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_intr.c similarity index 70% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_intr.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_intr.c index 85baab0..6124783 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_intr.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_intr.c
@@ -33,7 +33,7 @@ /** * * @file xusbpsu_intr.c -* @addtogroup usbpsu_v1_0 +* @addtogroup usbpsu_v1_3 * @{ * * @@ -43,6 +43,13 @@ * Ver Who Date Changes * ----- ---- -------- ------------------------------------------------------- * 1.0 sg 06/06/16 First release +* 1.3 vak 04/03/17 Added CCI support for USB +* 1.4 bk 12/01/18 Modify USBPSU driver code to fit USB common example code +* for all USB IPs +* myk 12/01/18 Added hibernation support +* vak 22/01/18 Added changes for supporting microblaze platform +* vak 13/03/18 Moved the setup interrupt system calls from driver to +* example. * * </pre> * @@ -50,7 +57,7 @@ /***************************** Include Files ********************************/ -#include "xusbpsu.h" +#include "xusb_wrapper.h" /************************** Constant Definitions *****************************/ @@ -95,10 +102,12 @@ /* Handle other end point events */ switch (Event->Endpoint_Event) { case XUSBPSU_DEPEVT_XFERCOMPLETE: + case XUSBPSU_DEPEVT_XFERINPROGRESS: XUsbPsu_EpXferComplete(InstancePtr, Event); break; case XUSBPSU_DEPEVT_XFERNOTREADY: + XUsbPsu_EpXferNotReady(InstancePtr, Event); break; default: @@ -130,7 +139,87 @@ XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal); InstancePtr->IsConfigDone = 0U; - InstancePtr->Speed = XUSBPSU_SPEED_UNKNOWN; + InstancePtr->AppData->Speed = XUSBPSU_SPEED_UNKNOWN; + +#ifdef XUSBPSU_HIBERNATION_ENABLE + /* In USB 2.0, to avoid hibernation interrupt at the time of connection + * clear KEEP_CONNECT bit. + */ + if (InstancePtr->HasHibernation) { + RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL); + if (RegVal & XUSBPSU_DCTL_KEEP_CONNECT) { + RegVal &= ~XUSBPSU_DCTL_KEEP_CONNECT; + XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal); + } + } +#endif + + /* Call the handler if necessary */ + if (InstancePtr->DisconnectIntrHandler != NULL) { + InstancePtr->DisconnectIntrHandler(InstancePtr->AppData); + } +} + +/****************************************************************************/ +/** +* Stops any active transfer. +* +* @param InstancePtr is a pointer to the XUsbPsu instance. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +static void XUsbPsu_stop_active_transfers(struct XUsbPsu *InstancePtr) +{ + u32 Epnum; + + for (Epnum = 2; Epnum < XUSBPSU_ENDPOINTS_NUM; Epnum++) { + struct XUsbPsu_Ep *Ept; + + Ept = &InstancePtr->eps[Epnum]; + if (!Ept) + continue; + + if (!(Ept->EpStatus & XUSBPSU_EP_ENABLED)) + continue; + + XUsbPsu_StopTransfer(InstancePtr, Ept->UsbEpNum, + Ept->Direction, TRUE); + } +} + +/****************************************************************************/ +/** +* Clears stall on all stalled Eps. +* +* @param InstancePtr is a pointer to the XUsbPsu instance. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +static void XUsbPsu_clear_stall_all_ep(struct XUsbPsu *InstancePtr) +{ + u32 Epnum; + + for (Epnum = 1; Epnum < XUSBPSU_ENDPOINTS_NUM; Epnum++) { + struct XUsbPsu_Ep *Ept; + + Ept = &InstancePtr->eps[Epnum]; + if (!Ept) + continue; + + if (!(Ept->EpStatus & XUSBPSU_EP_ENABLED)) + continue; + + if (!(Ept->EpStatus & XUSBPSU_EP_STALL)) + continue; + + XUsbPsu_EpClearStall(InstancePtr, Ept->UsbEpNum, Ept->Direction); + } } /****************************************************************************/ @@ -149,13 +238,16 @@ u32 RegVal; u32 Index; - InstancePtr->State = XUSBPSU_STATE_DEFAULT; + InstancePtr->AppData->State = XUSBPSU_STATE_DEFAULT; RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL); RegVal &= ~XUSBPSU_DCTL_TSTCTRL_MASK; XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal); InstancePtr->TestMode = 0U; + XUsbPsu_stop_active_transfers(InstancePtr); + XUsbPsu_clear_stall_all_ep(InstancePtr); + for (Index = 0U; Index < (InstancePtr->NumInEps + InstancePtr->NumOutEps); Index++) { @@ -168,6 +260,11 @@ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCFG); RegVal &= ~(XUSBPSU_DCFG_DEVADDR_MASK); XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCFG, RegVal); + + /* Call the handler if necessary */ + if (InstancePtr->ResetIntrHandler != NULL) { + InstancePtr->ResetIntrHandler(InstancePtr->AppData); + } } /****************************************************************************/ @@ -189,7 +286,7 @@ RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DSTS); Speed = (u8)(RegVal & XUSBPSU_DSTS_CONNECTSPD); - InstancePtr->Speed = Speed; + InstancePtr->AppData->Speed = Speed; switch (Speed) { case XUSBPSU_DCFG_SUPERSPEED: @@ -197,7 +294,7 @@ xil_printf("Super Speed\r\n"); #endif Size = 512U; - InstancePtr->Speed = XUSBPSU_SPEED_SUPER; + InstancePtr->AppData->Speed = XUSBPSU_SPEED_SUPER; break; case XUSBPSU_DCFG_HIGHSPEED: @@ -205,7 +302,7 @@ xil_printf("High Speed\r\n"); #endif Size = 64U; - InstancePtr->Speed = XUSBPSU_SPEED_HIGH; + InstancePtr->AppData->Speed = XUSBPSU_SPEED_HIGH; break; case XUSBPSU_DCFG_FULLSPEED2: @@ -214,7 +311,7 @@ xil_printf("Full Speed\r\n"); #endif Size = 64U; - InstancePtr->Speed = XUSBPSU_SPEED_FULL; + InstancePtr->AppData->Speed = XUSBPSU_SPEED_FULL; break; case XUSBPSU_DCFG_LOWSPEED: @@ -222,15 +319,34 @@ xil_printf("Low Speed\r\n"); #endif Size = 64U; - InstancePtr->Speed = XUSBPSU_SPEED_LOW; + InstancePtr->AppData->Speed = XUSBPSU_SPEED_LOW; break; default : Size = 64U; break; } + if (InstancePtr->AppData->Speed == XUSBPSU_SPEED_SUPER) { + RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL); + RegVal &= ~XUSBPSU_DCTL_HIRD_THRES_MASK; + XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal); + } + (void)XUsbPsu_EnableControlEp(InstancePtr, Size); (void)XUsbPsu_RecvSetup(InstancePtr); + +#ifdef XUSBPSU_HIBERNATION_ENABLE + /* In USB 2.0, to avoid hibernation interrupt at the time of connection + * clear KEEP_CONNECT bit. + */ + if (InstancePtr->HasHibernation) { + RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL); + if (!(RegVal & XUSBPSU_DCTL_KEEP_CONNECT)) { + RegVal |= XUSBPSU_DCTL_KEEP_CONNECT; + XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal); + } + } +#endif } /****************************************************************************/ @@ -284,6 +400,10 @@ break; case XUSBPSU_DEVICE_EVENT_HIBER_REQ: +#ifdef XUSBPSU_HIBERNATION_ENABLE + if (InstancePtr->HasHibernation) + Xusbpsu_HibernationIntr(InstancePtr); +#endif break; case XUSBPSU_DEVICE_EVENT_LINK_STATUS_CHANGE: @@ -362,26 +482,39 @@ { struct XUsbPsu_EvtBuffer *Evt; union XUsbPsu_Event Event = {0}; + u32 RegVal; Evt = &InstancePtr->Evt; - Xil_DCacheInvalidateRange((INTPTR)Evt->BuffAddr, + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) { + Xil_DCacheInvalidateRange((INTPTR)Evt->BuffAddr, (u32)XUSBPSU_EVENT_BUFFERS_SIZE); + } while (Evt->Count > 0) { - Event.Raw = *(UINTPTR *)(Evt->BuffAddr + Evt->Offset); + Event.Raw = *(UINTPTR *)((UINTPTR)Evt->BuffAddr + Evt->Offset); /* - * Process the event received - */ - XUsbPsu_EventHandler(InstancePtr, &Event); + * Process the event received + */ + XUsbPsu_EventHandler(InstancePtr, &Event); + + /* don't process anymore events if core is hibernated */ + if (InstancePtr->IsHibernated) + return; Evt->Offset = (Evt->Offset + 4U) % XUSBPSU_EVENT_BUFFERS_SIZE; Evt->Count -= 4; XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTCOUNT(0), 4U); } + Evt->Count = 0; Evt->Flags &= ~XUSBPSU_EVENT_PENDING; + + /* Unmask event interrupt */ + RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GEVNTSIZ(0)); + RegVal &= ~XUSBPSU_GEVNTSIZ_INTMASK; + XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTSIZ(0), RegVal); } /****************************************************************************/ @@ -424,11 +557,24 @@ /* Processes events in an Event Buffer */ XUsbPsu_EventBufferHandler(InstancePtr); - - /* Unmask event interrupt */ - RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GEVNTSIZ(0)); - RegVal &= ~XUSBPSU_GEVNTSIZ_INTMASK; - XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTSIZ(0), RegVal); } +#ifdef XUSBPSU_HIBERNATION_ENABLE +/****************************************************************************/ +/** +* Wakeup Interrupt Handler. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XUsbPsu_WakeUpIntrHandler(void *XUsbPsuInstancePtr) +{ + struct XUsbPsu *InstancePtr = (struct XUsbPsu *)XUsbPsuInstancePtr; + + XUsbPsu_WakeupIntr(InstancePtr); +} +#endif + /** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_sinit.c similarity index 98% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_sinit.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_sinit.c index c172c5d..bee46bc 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_sinit.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_sinit.c
@@ -33,7 +33,7 @@ /** * * @file xusbpsu_sinit.h -* @addtogroup usbpsu_v1_0 +* @addtogroup usbpsu_v1_3 * @{ * *
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/Makefile new file mode 100644 index 0000000..9cb03a4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/Makefile
@@ -0,0 +1,40 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS=-ffunction-sections -fdata-sections +EXTRA_COMPILER_FLAGS=-Wall -Wextra +LIB=libxil.a + +CC_FLAGS = $(COMPILER_FLAGS) +ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +OUTS = *.o + +LIBSOURCES:=*.c +INCLUDEFILES:=*.h + +OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) + +libs: banner video_common_libs clean + +%.o: %.c + ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< + +banner: + echo "Compiling video_common" + +video_common_libs: ${OBJECTS} + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} + +.PHONY: include +include: video_common_includes + +video_common_includes: + ${CP} ${INCLUDEFILES} ${INCLUDEDIR} + +clean: + rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc.c new file mode 100644 index 0000000..ba4f789 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc.c
@@ -0,0 +1,1204 @@ +/******************************************************************************* + * + * Copyright (C) 2017 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xvidc.c + * @addtogroup video_common_v4_3 + * @{ + * + * Contains common utility functions that are typically used by video-related + * drivers and applications. + * + * @note None. + * + * <pre> + * MODIFICATION HISTORY: + * + * Ver Who Date Changes + * ----- ---- -------- ----------------------------------------------- + * 1.0 rc, 01/10/15 Initial release. + * als + * 2.2 als 02/01/16 Functions with pointer arguments that don't modify + * contents now const. + * Added ability to insert a custom video timing table. + * yh Added 3D support. + * 3.0 aad 05/13/16 Added API to search for RB video modes. + * 3.1 rco 07/26/16 Added extern definition for timing table array + * Added video-in-memory color formats + * Updated XVidC_RegisterCustomTimingModes API signature + * 4.1 rco 11/23/16 Added new memory formats + * Added new API to get video mode id that matches exactly + * with provided timing information + * Fix c++ warnings + * 4.2 jsr 07/22/17 Added new framerates and color formats to support SDI + * Reordered YCBCR422 colorforamt and removed other formats + * that are not needed for SDI which were added earlier. + * vyc 10/04/17 Added new streaming alpha formats and new memory formats + * 4.3 eb 26/01/18 Added API XVidC_GetVideoModeIdExtensive + * jsr 02/22/18 Added XVIDC_CSF_YCBCR_420 color space format + * vyc 04/04/18 Added BGR8 memory format + * </pre> + * +*******************************************************************************/ + +/******************************* Include Files ********************************/ + +#include "xil_assert.h" +#include "xstatus.h" +#include "xvidc.h" + +/*************************** Variable Declarations ****************************/ +extern const XVidC_VideoTimingMode XVidC_VideoTimingModes[XVIDC_VM_NUM_SUPPORTED]; + +const XVidC_VideoTimingMode *XVidC_CustomTimingModes = NULL; +int XVidC_NumCustomModes = 0; + +/**************************** Function Prototypes *****************************/ + +static const XVidC_VideoTimingMode *XVidC_GetCustomVideoModeData( + XVidC_VideoMode VmId); +static u8 XVidC_IsVtmRb(const char *VideoModeStr, u8 RbN); + +/*************************** Function Definitions *****************************/ + +/******************************************************************************/ +/** + * This function registers a user-defined custom video mode timing table with + * video_common. Functions which search the available video modes, or take VmId + * as an input, will operate on or check the custom video mode timing table in + * addition to the pre-defined video mode timing table (XVidC_VideoTimingModes). + * + * @param CustomTable is a pointer to the user-defined custom vide mode + * timing table to register. + * @param NumElems is the number of video modes supported by CustomTable. + * + * @return + * - XST_SUCCESS if the custom table was successfully registered. + * - XST_FAILURE if an existing custom table is already present. + * + * @note IDs in the custom table may not conflict with IDs reserved by + * the XVidC_VideoMode enum. + * +*******************************************************************************/ +u32 XVidC_RegisterCustomTimingModes(const XVidC_VideoTimingMode *CustomTable, + u16 NumElems) +{ + u16 Index; + + /* Verify arguments. */ + Xil_AssertNonvoid(CustomTable != NULL); + for (Index = 0; Index < NumElems; Index++) { + Xil_AssertNonvoid((CustomTable[Index].VmId > XVIDC_VM_CUSTOM)); + /* The IDs of each video mode in the custom table must not + * conflict with IDs reserved by video_common. */ + } + + /* Fail if a custom table is currently already registered. */ + if (XVidC_CustomTimingModes) { + return XST_FAILURE; + } + + XVidC_CustomTimingModes = CustomTable; + XVidC_NumCustomModes = NumElems; + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function unregisters the user-defined custom video mode timing table + * previously registered by XVidC_RegisterCustomTimingModes(). + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +void XVidC_UnregisterCustomTimingModes(void) +{ + XVidC_CustomTimingModes = NULL; + XVidC_NumCustomModes = 0; +} + +/******************************************************************************/ +/** + * This function calculates pixel clock based on the inputs. + * + * @param HTotal specifies horizontal total. + * @param VTotal specifies vertical total. + * @param FrameRate specifies rate at which frames are generated. + * + * @return Pixel clock in Hz. + * + * @note None. + * +*******************************************************************************/ +u32 XVidC_GetPixelClockHzByHVFr(u32 HTotal, u32 VTotal, u8 FrameRate) +{ + return (HTotal * VTotal * FrameRate); +} + +/******************************************************************************/ +/** + * This function calculates pixel clock from video mode. + * + * @param VmId specifies the resolution id. + * + * @return Pixel clock in Hz. + * + * @note None. + * +*******************************************************************************/ +u32 XVidC_GetPixelClockHzByVmId(XVidC_VideoMode VmId) +{ + u32 ClkHz; + const XVidC_VideoTimingMode *VmPtr; + + VmPtr = XVidC_GetVideoModeData(VmId); + if (!VmPtr) { + return 0; + } + + if (XVidC_IsInterlaced(VmId)) { + /* For interlaced mode, use both frame 0 and frame 1 vertical + * totals. */ + ClkHz = VmPtr->Timing.F0PVTotal + VmPtr->Timing.F1VTotal; + + /* Multiply the number of pixels by the frame rate of each + * individual frame (half of the total frame rate). */ + ClkHz *= VmPtr->FrameRate / 2; + } + else { + /* For progressive mode, use only frame 0 vertical total. */ + ClkHz = VmPtr->Timing.F0PVTotal; + + /* Multiply the number of pixels by the frame rate. */ + ClkHz *= VmPtr->FrameRate; + } + + /* Multiply the vertical total by the horizontal total for number of + * pixels. */ + ClkHz *= VmPtr->Timing.HTotal; + + return ClkHz; +} + +/******************************************************************************/ +/** + * This function checks if the input video mode is interlaced/progressive based + * on its ID from the video timings table. + * + * @param VmId specifies the resolution ID from the video timings table. + * + * @return Video format. + * - XVIDC_VF_PROGRESSIVE + * - XVIDC_VF_INTERLACED + * + * @note None. + * +*******************************************************************************/ +XVidC_VideoFormat XVidC_GetVideoFormat(XVidC_VideoMode VmId) +{ + const XVidC_VideoTimingMode *VmPtr; + + VmPtr = XVidC_GetVideoModeData(VmId); + if (!VmPtr) { + return XVIDC_VF_UNKNOWN; + } + + if (VmPtr->Timing.F1VTotal == 0) { + return (XVIDC_VF_PROGRESSIVE); + } + + return (XVIDC_VF_INTERLACED); +} + +/******************************************************************************/ +/** + * This function checks if the input video mode is interlaced based on its ID + * from the video timings table. + * + * @param VmId specifies the resolution ID from the video timings table. + * + * @return + * - 1 if the video timing with the supplied table ID is + * interlaced. + * - 0 if the video timing is progressive. + * + * @note None. + * +*******************************************************************************/ +u8 XVidC_IsInterlaced(XVidC_VideoMode VmId) +{ + if (XVidC_GetVideoFormat(VmId) == XVIDC_VF_INTERLACED) { + return 1; + } + + return 0; +} + +/******************************************************************************/ +/** + * This function returns the Video Mode ID that matches the detected input + * timing, frame rate and I/P flag + * + * @param Timing is the pointer to timing parameters to match + * @param FrameRate specifies refresh rate in HZ + * @param IsInterlaced is flag. + * - 0 = Progressive + * - 1 = Interlaced. + * + * @return Id of a supported video mode. + * + * @note This is an extension of XVidC_GetVideoModeId API to include + * blanking information in match process. No attempt is made to + * search for reduced blanking entries, if any. + * +*******************************************************************************/ +XVidC_VideoMode XVidC_GetVideoModeIdWBlanking(const XVidC_VideoTiming *Timing, + u32 FrameRate, u8 IsInterlaced) +{ + XVidC_VideoMode VmId; + XVidC_VideoTiming const *StdTiming = NULL; + + /* First search for ID with matching Width & Height */ + VmId = XVidC_GetVideoModeId(Timing->HActive, Timing->VActive, FrameRate, + IsInterlaced); + + if(VmId == XVIDC_VM_NOT_SUPPORTED) { + return(VmId); + } else { + + /* Get standard timing info from default timing table */ + StdTiming = XVidC_GetTimingInfo(VmId); + + /* Match against detected timing parameters */ + if((Timing->HActive == StdTiming->HActive) && + (Timing->VActive == StdTiming->VActive) && + (Timing->HTotal == StdTiming->HTotal) && + (Timing->F0PVTotal == StdTiming->F0PVTotal) && + (Timing->HFrontPorch == StdTiming->HFrontPorch) && + (Timing->HSyncWidth == StdTiming->HSyncWidth) && + (Timing->HBackPorch == StdTiming->HBackPorch) && + (Timing->F0PVFrontPorch == StdTiming->F0PVFrontPorch) && + (Timing->F0PVSyncWidth == StdTiming->F0PVSyncWidth) && + (Timing->F0PVBackPorch == StdTiming->F0PVBackPorch)) { + return(VmId); + } else { + return(XVIDC_VM_NOT_SUPPORTED); + } + } +} + +/******************************************************************************/ +/** + * This function returns the Video Mode ID that matches the detected input + * width, height, frame rate and I/P flag + * + * @param Width specifies the number pixels per scanline. + * @param Height specifies the number of scanline's. + * @param FrameRate specifies refresh rate in HZ + * @param IsInterlaced is flag. + * - 0 = Progressive + * - 1 = Interlaced. + * + * @return Id of a supported video mode. + * + * @note None. + * +*******************************************************************************/ +XVidC_VideoMode XVidC_GetVideoModeId(u32 Width, u32 Height, u32 FrameRate, + u8 IsInterlaced) +{ + u32 Low; + u32 High; + u32 Mid; + u32 HActive; + u32 VActive; + u32 Rate; + u32 ResFound = (FALSE); + XVidC_VideoMode Mode; + u16 Index; + + /* First, attempt a linear search on the custom video timing table. */ + if(XVidC_CustomTimingModes) { + for (Index = 0; Index < XVidC_NumCustomModes; Index++) { + HActive = XVidC_CustomTimingModes[Index].Timing.HActive; + VActive = XVidC_CustomTimingModes[Index].Timing.VActive; + Rate = XVidC_CustomTimingModes[Index].FrameRate; + if ((Width == HActive) && + (Height == VActive) && + (FrameRate == Rate)) { + return XVidC_CustomTimingModes[Index].VmId; + } + } + } + + if (IsInterlaced) { + Low = (XVIDC_VM_INTL_START); + High = (XVIDC_VM_INTL_END); + } + else { + Low = (XVIDC_VM_PROG_START); + High = (XVIDC_VM_PROG_END); + } + + HActive = VActive = Rate = 0; + + /* Binary search finds item in sorted array. + * And returns index (zero based) of item + * If item is not found returns flag remains + * FALSE. Search key is "width or HActive" + */ + while (Low <= High) { + Mid = (Low + High) / 2; + HActive = XVidC_VideoTimingModes[Mid].Timing.HActive; + if (Width == HActive) { + ResFound = (TRUE); + break; + } + else if (Width < HActive) { + if (Mid == 0) { + break; + } + else { + High = Mid - 1; + } + } + else { + Low = Mid + 1; + } + } + + /* HActive matched at middle */ + if (ResFound) { + /* Rewind to start index of mode with matching width */ + while ((Mid > 0) && + (XVidC_VideoTimingModes[Mid - 1].Timing.HActive == + Width)) { + --Mid; + } + + ResFound = (FALSE); + VActive = XVidC_VideoTimingModes[Mid].Timing.VActive; + Rate = XVidC_VideoTimingModes[Mid].FrameRate; + + /* Now do a linear search for matching VActive and Frame + * Rate + */ + while (HActive == Width) { + /* check current entry */ + if ((VActive == Height) && (Rate == FrameRate)) { + ResFound = (TRUE); + break; + } + /* Check next entry */ + else { + Mid = Mid + 1; + HActive = + XVidC_VideoTimingModes[Mid].Timing.HActive; + VActive = + XVidC_VideoTimingModes[Mid].Timing.VActive; + Rate = XVidC_VideoTimingModes[Mid].FrameRate; + } + } + Mode = + (ResFound) ? (XVidC_VideoMode)Mid : (XVIDC_VM_NOT_SUPPORTED); + } + else { + Mode = (XVIDC_VM_NOT_SUPPORTED); + } + + return (Mode); +} + +/******************************************************************************/ +/** + * This function returns the Video Mode ID that matches the detected input + * timing, frame rate and I/P flag + * + * @param Timing is the pointer to timing parameters to match + * @param FrameRate specifies refresh rate in HZ + * @param IsInterlaced is flag. + * - 0 = Progressive + * - 1 = Interlaced. + * @param IsExtensive is flag. + * - 0 = Basic matching of timing parameters + * - 1 = Extensive matching of timing parameters + * + * @return Id of a supported video mode. + * + * @note This function attempts to search for reduced blanking entries, if + * any. + * +*******************************************************************************/ +XVidC_VideoMode XVidC_GetVideoModeIdExtensive(XVidC_VideoTiming *Timing, + u32 FrameRate, + u8 IsInterlaced, + u8 IsExtensive) +{ + u32 Low; + u32 High; + u32 Mid; + u32 HActive; + u32 VActive; + u32 Rate; + u32 ResFound = (FALSE); + XVidC_VideoMode Mode; + u16 Index; + + /* First, attempt a linear search on the custom video timing table. */ + if(XVidC_CustomTimingModes) { + for (Index = 0; Index < XVidC_NumCustomModes; Index++) { + HActive = XVidC_CustomTimingModes[Index].Timing.HActive; + VActive = XVidC_CustomTimingModes[Index].Timing.VActive; + Rate = XVidC_CustomTimingModes[Index].FrameRate; + if ((HActive == Timing->HActive) && (VActive == Timing->VActive) && + (Rate == FrameRate) && (IsExtensive == 0 || ( + XVidC_CustomTimingModes[Index].Timing.HTotal == Timing->HTotal && + XVidC_CustomTimingModes[Index].Timing.F0PVTotal == + Timing->F0PVTotal && + XVidC_CustomTimingModes[Index].Timing.HFrontPorch == + Timing->HFrontPorch && + XVidC_CustomTimingModes[Index].Timing.F0PVFrontPorch == + Timing->F0PVFrontPorch && + XVidC_CustomTimingModes[Index].Timing.HSyncWidth == + Timing->HSyncWidth && + XVidC_CustomTimingModes[Index].Timing.F0PVSyncWidth == + Timing->F0PVSyncWidth && + XVidC_CustomTimingModes[Index].Timing.VSyncPolarity == + Timing->VSyncPolarity))) { + if (!IsInterlaced || IsExtensive == 0 || ( + XVidC_CustomTimingModes[Index].Timing.F1VTotal == + Timing->F1VTotal && + XVidC_CustomTimingModes[Index].Timing.F1VFrontPorch == + Timing->F1VFrontPorch && + XVidC_CustomTimingModes[Index].Timing.F1VSyncWidth == + Timing->F1VSyncWidth)) { + return XVidC_CustomTimingModes[Index].VmId; + } + } + } + } + + if (IsInterlaced) { + Low = (XVIDC_VM_INTL_START); + High = (XVIDC_VM_INTL_END); + } + else { + Low = (XVIDC_VM_PROG_START); + High = (XVIDC_VM_PROG_END); + } + + HActive = VActive = Rate = 0; + + /* Binary search finds item in sorted array. + * And returns index (zero based) of item + * If item is not found returns flag remains + * FALSE. Search key is "Timing->HActive or HActive" + */ + while (Low <= High) { + Mid = (Low + High) / 2; + HActive = XVidC_VideoTimingModes[Mid].Timing.HActive; + if (Timing->HActive == HActive) { + ResFound = (TRUE); + break; + } + else if (Timing->HActive < HActive) { + if (Mid == 0) { + break; + } + else { + High = Mid - 1; + } + } + else { + Low = Mid + 1; + } + } + + /* HActive matched at middle */ + if (ResFound) { + /* Rewind to start index of mode with matching Timing->HActive */ + while ((Mid > 0) && + (XVidC_VideoTimingModes[Mid - 1].Timing.HActive == + Timing->HActive)) { + --Mid; + } + + ResFound = (FALSE); + VActive = XVidC_VideoTimingModes[Mid].Timing.VActive; + Rate = XVidC_VideoTimingModes[Mid].FrameRate; + + /* Now do a linear search for matching VActive and Frame + * Rate + */ + while (HActive == Timing->HActive) { + /* check current entry */ + if ((VActive == Timing->VActive) && (Rate == FrameRate) && + (IsExtensive == 0 || + (XVidC_VideoTimingModes[Mid].Timing.HTotal == + Timing->HTotal && + XVidC_VideoTimingModes[Mid].Timing.F0PVTotal == + Timing->F0PVTotal && + XVidC_VideoTimingModes[Mid].Timing.HFrontPorch == + Timing->HFrontPorch && + XVidC_VideoTimingModes[Mid].Timing.F0PVFrontPorch == + Timing->F0PVFrontPorch && + XVidC_VideoTimingModes[Mid].Timing.HSyncWidth == + Timing->HSyncWidth && + XVidC_VideoTimingModes[Mid].Timing.F0PVSyncWidth == + Timing->F0PVSyncWidth && + XVidC_VideoTimingModes[Mid].Timing.VSyncPolarity == + Timing->VSyncPolarity))) { + if (!IsInterlaced || IsExtensive == 0 || ( + XVidC_VideoTimingModes[Mid].Timing.F1VTotal == + Timing->F1VTotal && + XVidC_VideoTimingModes[Mid].Timing.F1VFrontPorch == + Timing->F1VFrontPorch && + XVidC_VideoTimingModes[Mid].Timing.F1VSyncWidth == + Timing->F1VSyncWidth)) { + ResFound = (TRUE); + break; + } + } + /* Check next entry */ + else { + Mid = Mid + 1; + HActive = + XVidC_VideoTimingModes[Mid].Timing.HActive; + VActive = + XVidC_VideoTimingModes[Mid].Timing.VActive; + Rate = XVidC_VideoTimingModes[Mid].FrameRate; + } + } + Mode = + (ResFound) ? (XVidC_VideoMode)Mid : (XVIDC_VM_NOT_SUPPORTED); + } + else { + Mode = (XVIDC_VM_NOT_SUPPORTED); + } + + return (Mode); +} + +/******************************************************************************/ +/** + * This function returns the video mode ID that matches the detected input + * width, height, frame rate, interlaced or progressive, and reduced blanking. + * + * @param Width specifies the number pixels per scanline. + * @param Height specifies the number of scanline's. + * @param FrameRate specifies refresh rate in HZ + * @param IsInterlaced specifies interlaced or progressive mode: + * - 0 = Progressive + * - 1 = Interlaced. + * @param RbN specifies the type of reduced blanking: + * - 0 = No reduced blanking + * - 1 = RB + * - 2 = RB2 + * + * @return ID of a supported video mode. + * + * @note None. + * +*******************************************************************************/ +XVidC_VideoMode XVidC_GetVideoModeIdRb(u32 Width, u32 Height, + u32 FrameRate, u8 IsInterlaced, u8 RbN) +{ + XVidC_VideoMode VmId; + const XVidC_VideoTimingMode *VtmPtr; + u8 Found = 0; + + VmId = XVidC_GetVideoModeId(Width, Height, FrameRate, + IsInterlaced); + + VtmPtr = XVidC_GetVideoModeData(VmId); + if (!VtmPtr) { + return XVIDC_VM_NOT_SUPPORTED; + } + + while (!Found) { + VtmPtr = XVidC_GetVideoModeData(VmId); + if ((Height != VtmPtr->Timing.VActive) || + (Width != VtmPtr->Timing.HActive) || + (FrameRate != VtmPtr->FrameRate) || + (IsInterlaced && !XVidC_IsInterlaced(VmId))) { + VmId = XVIDC_VM_NOT_SUPPORTED; + break; + } + Found = XVidC_IsVtmRb(XVidC_GetVideoModeStr(VmId), RbN); + if (Found) { + break; + } + VmId = (XVidC_VideoMode)((int)VmId + 1); + } + + return VmId; +} + +/******************************************************************************/ +/** + * This function returns the pointer to video mode data at index provided. + * + * @param VmId specifies the resolution id. + * + * @return Pointer to XVidC_VideoTimingMode structure based on the given + * video mode. + * + * @note None. + * +*******************************************************************************/ +const XVidC_VideoTimingMode *XVidC_GetVideoModeData(XVidC_VideoMode VmId) +{ + if (VmId < XVIDC_VM_NUM_SUPPORTED) { + return &XVidC_VideoTimingModes[VmId]; + } + + return XVidC_GetCustomVideoModeData(VmId); +} + +/******************************************************************************/ +/** + * + * This function returns the resolution name for index specified. + * + * @param VmId specifies the resolution id. + * + * @return Pointer to a resolution name string. + * + * @note None. + * +*******************************************************************************/ +const char *XVidC_GetVideoModeStr(XVidC_VideoMode VmId) +{ + const XVidC_VideoTimingMode *VmPtr; + + if (VmId == XVIDC_VM_CUSTOM) { + return ("Custom video mode"); + } + + VmPtr = XVidC_GetVideoModeData(VmId); + if (!VmPtr) { + return ("Video mode not supported"); + } + + return VmPtr->Name; +} + +/******************************************************************************/ +/** + * This function returns the frame rate name for index specified. + * + * @param VmId specifies the resolution id. + * + * @return Pointer to a frame rate name string. + * + * @note None. + * +*******************************************************************************/ +const char *XVidC_GetFrameRateStr(XVidC_VideoMode VmId) +{ + const XVidC_VideoTimingMode *VmPtr; + + VmPtr = XVidC_GetVideoModeData(VmId); + if (!VmPtr) { + return ("Video mode not supported"); + } + + switch (VmPtr->FrameRate) { + case (XVIDC_FR_24HZ): return ("24Hz"); + case (XVIDC_FR_25HZ): return ("25Hz"); + case (XVIDC_FR_30HZ): return ("30Hz"); + case (XVIDC_FR_48HZ): return ("48Hz"); + case (XVIDC_FR_50HZ): return ("50Hz"); + case (XVIDC_FR_56HZ): return ("56Hz"); + case (XVIDC_FR_60HZ): return ("60Hz"); + case (XVIDC_FR_65HZ): return ("65Hz"); + case (XVIDC_FR_67HZ): return ("67Hz"); + case (XVIDC_FR_70HZ): return ("70Hz"); + case (XVIDC_FR_72HZ): return ("72Hz"); + case (XVIDC_FR_75HZ): return ("75Hz"); + case (XVIDC_FR_85HZ): return ("85Hz"); + case (XVIDC_FR_87HZ): return ("87Hz"); + case (XVIDC_FR_88HZ): return ("88Hz"); + case (XVIDC_FR_96HZ): return ("96Hz"); + case (XVIDC_FR_100HZ): return ("100Hz"); + case (XVIDC_FR_120HZ): return ("120Hz"); + + default: + return ("Frame rate not supported"); + } +} + +/******************************************************************************/ +/** + * This function returns a string representation of the enumerated type, + * XVidC_3DFormat. + * + * @param Format specifies the value to convert. + * + * @return Pointer to the converted string. + * + * @note None. + * +*******************************************************************************/ +const char *XVidC_Get3DFormatStr(XVidC_3DFormat Format) +{ + switch (Format) { + case XVIDC_3D_FRAME_PACKING: + return ("Frame Packing"); + + case XVIDC_3D_FIELD_ALTERNATIVE: + return ("Field Alternative"); + + case XVIDC_3D_LINE_ALTERNATIVE: + return ("Line Alternative"); + + case XVIDC_3D_SIDE_BY_SIDE_FULL: + return ("Side-by-Side(full)"); + + case XVIDC_3D_TOP_AND_BOTTOM_HALF: + return ("Top-and-Bottom(half)"); + + case XVIDC_3D_SIDE_BY_SIDE_HALF: + return ("Side-by-Side(half)"); + + default: + return ("Unknown"); + } +} + +/******************************************************************************/ +/** + * This function returns the color format name for index specified. + * + * @param ColorFormatId specifies the index of color format space. + * + * @return Pointer to a color space name string. + * + * @note None. + * +*******************************************************************************/ +const char *XVidC_GetColorFormatStr(XVidC_ColorFormat ColorFormatId) +{ + switch (ColorFormatId) { + case XVIDC_CSF_RGB: return ("RGB"); + case XVIDC_CSF_YCRCB_444: return ("YUV_444"); + case XVIDC_CSF_YCRCB_422: return ("YUV_422"); + case XVIDC_CSF_YCRCB_420: return ("YUV_420"); + case XVIDC_CSF_YONLY: return ("Y_ONLY"); + case XVIDC_CSF_RGBA: return ("RGBA"); + case XVIDC_CSF_YCRCBA_444: return ("YUVA_444"); + case XVIDC_CSF_MEM_RGBX8: return ("RGBX8"); + case XVIDC_CSF_MEM_YUVX8: return ("YUVX8"); + case XVIDC_CSF_MEM_YUYV8: return ("YUYV8"); + case XVIDC_CSF_MEM_RGBA8: return ("RGBA8"); + case XVIDC_CSF_MEM_YUVA8: return ("YUVA8"); + case XVIDC_CSF_MEM_RGBX10: return ("RGBX10"); + case XVIDC_CSF_MEM_YUVX10: return ("YUVX10"); + case XVIDC_CSF_MEM_RGB565: return ("RGB565"); + case XVIDC_CSF_MEM_Y_UV8: return ("Y_UV8"); + case XVIDC_CSF_MEM_Y_UV8_420: return ("Y_UV8_420"); + case XVIDC_CSF_MEM_RGB8: return ("RGB8"); + case XVIDC_CSF_MEM_YUV8: return ("YUV8"); + case XVIDC_CSF_MEM_Y_UV10: return ("Y_UV10"); + case XVIDC_CSF_MEM_Y_UV10_420: return ("Y_UV10_420"); + case XVIDC_CSF_MEM_Y8: return ("Y8"); + case XVIDC_CSF_MEM_Y10: return ("Y10"); + case XVIDC_CSF_MEM_BGRA8: return ("BGRA8"); + case XVIDC_CSF_MEM_BGRX8: return ("BGRX8"); + case XVIDC_CSF_MEM_UYVY8: return ("UYVY8"); + case XVIDC_CSF_MEM_BGR8: return ("BGR8"); + case XVIDC_CSF_YCBCR_422: return ("YCBCR_422"); + case XVIDC_CSF_YCBCR_420: return ("YCBCR_420"); + default: + return ("Color space format not supported"); + } +} + +/******************************************************************************/ +/** + * This function returns the frame rate for index specified. + * + * @param VmId specifies the resolution id. + * + * @return Frame rate in Hz. + * + * @note None. + * +*******************************************************************************/ +XVidC_FrameRate XVidC_GetFrameRate(XVidC_VideoMode VmId) +{ + const XVidC_VideoTimingMode *VmPtr; + + VmPtr = XVidC_GetVideoModeData(VmId); + if (!VmPtr) { + return XVIDC_FR_NUM_SUPPORTED; + } + + return VmPtr->FrameRate; +} + +/******************************************************************************/ +/** + * This function returns the timing parameters for specified resolution. + * + * @param VmId specifies the resolution id. + * + * @return Pointer to a XVidC_VideoTiming structure. + * + * @note None. + * +*******************************************************************************/ +const XVidC_VideoTiming *XVidC_GetTimingInfo(XVidC_VideoMode VmId) +{ + const XVidC_VideoTimingMode *VmPtr; + + VmPtr = XVidC_GetVideoModeData(VmId); + if (!VmPtr) { + return NULL; + } + + return &VmPtr->Timing; +} + +/******************************************************************************/ +/** + * This function sets the VideoStream structure for the specified video format. + * + * @param VidStrmPtr is a pointer to the XVidC_VideoStream structure to be + * set. + * @param VmId specifies the resolution ID. + * @param ColorFormat specifies the color format type. + * @param Bpc specifies the color depth/bits per color component. + * @param Ppc specifies the pixels per clock. + * + * @return + * - XST_SUCCESS if the timing for the supplied ID was found. + * - XST_FAILURE, otherwise. + * + * @note None. + * +*******************************************************************************/ +u32 XVidC_SetVideoStream(XVidC_VideoStream *VidStrmPtr, XVidC_VideoMode VmId, + XVidC_ColorFormat ColorFormat, XVidC_ColorDepth Bpc, + XVidC_PixelsPerClock Ppc) +{ + const XVidC_VideoTiming *TimingPtr; + + /* Verify arguments. */ + Xil_AssertNonvoid(VidStrmPtr != NULL); + Xil_AssertNonvoid(ColorFormat < XVIDC_CSF_NUM_SUPPORTED); + Xil_AssertNonvoid((Bpc == XVIDC_BPC_6) || + (Bpc == XVIDC_BPC_8) || + (Bpc == XVIDC_BPC_10) || + (Bpc == XVIDC_BPC_12) || + (Bpc == XVIDC_BPC_14) || + (Bpc == XVIDC_BPC_16) || + (Bpc == XVIDC_BPC_UNKNOWN)); + Xil_AssertNonvoid((Ppc == XVIDC_PPC_1) || + (Ppc == XVIDC_PPC_2) || + (Ppc == XVIDC_PPC_4)); + + /* Get the timing from the video timing table. */ + TimingPtr = XVidC_GetTimingInfo(VmId); + if (!TimingPtr) { + return XST_FAILURE; + } + VidStrmPtr->VmId = VmId; + VidStrmPtr->Timing = *TimingPtr; + VidStrmPtr->FrameRate = XVidC_GetFrameRate(VmId); + VidStrmPtr->IsInterlaced = XVidC_IsInterlaced(VmId); + VidStrmPtr->ColorFormatId = ColorFormat; + VidStrmPtr->ColorDepth = Bpc; + VidStrmPtr->PixPerClk = Ppc; + + /* Set stream to 2D. */ + VidStrmPtr->Is3D = FALSE; + VidStrmPtr->Info_3D.Format = XVIDC_3D_UNKNOWN; + VidStrmPtr->Info_3D.Sampling.Method = XVIDC_3D_SAMPLING_UNKNOWN; + VidStrmPtr->Info_3D.Sampling.Position = XVIDC_3D_SAMPPOS_UNKNOWN; + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function sets the VideoStream structure for the specified 3D video + * format. + * + * @param VidStrmPtr is a pointer to the XVidC_VideoStream structure to be + * set. + * @param VmId specifies the resolution ID. + * @param ColorFormat specifies the color format type. + * @param Bpc specifies the color depth/bits per color component. + * @param Ppc specifies the pixels per clock. + * @param Info3DPtr is a pointer to a XVidC_3DInfo structure. + * + * @return + * - XST_SUCCESS if the timing for the supplied ID was found. + * - XST_FAILURE, otherwise. + * + * @return + * - XST_SUCCESS + * - XST_FAILURE + * + * @note None. + * +*******************************************************************************/ +u32 XVidC_Set3DVideoStream(XVidC_VideoStream *VidStrmPtr, XVidC_VideoMode VmId, + XVidC_ColorFormat ColorFormat, XVidC_ColorDepth Bpc, + XVidC_PixelsPerClock Ppc, XVidC_3DInfo *Info3DPtr) +{ + u32 Status; + u16 Vblank0; + u16 Vblank1; + + /* Verify arguments */ + Xil_AssertNonvoid(Info3DPtr != NULL); + + /* Initialize with info for 2D frame. */ + Status = XVidC_SetVideoStream(VidStrmPtr, VmId, ColorFormat, Bpc, Ppc); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* Set stream to 3D. */ + VidStrmPtr->Is3D = TRUE; + VidStrmPtr->Info_3D = *Info3DPtr; + + /* Only 3D format supported is frame packing. */ + if (Info3DPtr->Format != XVIDC_3D_FRAME_PACKING) { + return XST_FAILURE; + } + + /* Update the timing based on the 3D format. */ + + /* An interlaced format is converted to a progressive frame: */ + /* 3D VActive = (2D VActive * 4) + (2D VBlank field0) + + (2D Vblank field1 * 2) */ + if (VidStrmPtr->IsInterlaced) { + Vblank0 = VidStrmPtr->Timing.F0PVTotal - + VidStrmPtr->Timing.VActive; + Vblank1 = VidStrmPtr->Timing.F1VTotal - + VidStrmPtr->Timing.VActive; + VidStrmPtr->Timing.VActive = (VidStrmPtr->Timing.VActive * 4) + + Vblank0 + (Vblank1 * 2); + + /* Set VTotal */ + VidStrmPtr->Timing.F0PVTotal *= 2; + VidStrmPtr->Timing.F0PVTotal += VidStrmPtr->Timing.F1VTotal * 2; + + /* Clear field 1 values. */ + VidStrmPtr->Timing.F1VFrontPorch = 0; + VidStrmPtr->Timing.F1VSyncWidth = 0; + VidStrmPtr->Timing.F1VBackPorch = 0; + VidStrmPtr->Timing.F1VTotal = 0; + + /* Set format to progressive */ + VidStrmPtr->IsInterlaced = FALSE; + } + /* Progressive */ + else { + /* 3D Vactive = (2D VActive * 2) + (2D VBlank) */ + Vblank0 = VidStrmPtr->Timing.F0PVTotal - + VidStrmPtr->Timing.VActive; + VidStrmPtr->Timing.VActive = (VidStrmPtr->Timing.VActive * 2) + + Vblank0; + + /* Set VTotal. */ + VidStrmPtr->Timing.F0PVTotal = VidStrmPtr->Timing.F0PVTotal * 2; + } + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function prints the stream information on STDIO/UART console. + * + * @param Stream is a pointer to video stream. + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +void XVidC_ReportStreamInfo(const XVidC_VideoStream *Stream) +{ + if (!XVidC_GetVideoModeData(Stream->VmId) && + (Stream->VmId != XVIDC_VM_CUSTOM)) { + xil_printf("\tThe stream ID (%d) is not supported.\r\n", + Stream->VmId); + return; + } + + xil_printf("\tColor Format: %s\r\n", + XVidC_GetColorFormatStr(Stream->ColorFormatId)); + xil_printf("\tColor Depth: %d\r\n", Stream->ColorDepth); + xil_printf("\tPixels Per Clock: %d\r\n", Stream->PixPerClk); + xil_printf("\tMode: %s\r\n", + Stream->IsInterlaced ? "Interlaced" : "Progressive"); + + if (Stream->Is3D) { + xil_printf("\t3D Format: %s\r\n", + XVidC_Get3DFormatStr(Stream->Info_3D.Format)); + } + + if (Stream->VmId == XVIDC_VM_CUSTOM) { + xil_printf("\tFrame Rate: %dHz\r\n", + Stream->FrameRate); + xil_printf("\tResolution: %dx%d [Custom Mode]\r\n", + Stream->Timing.HActive, Stream->Timing.VActive); + xil_printf("\tPixel Clock: %d\r\n", + XVidC_GetPixelClockHzByHVFr( + Stream->Timing.HTotal, + Stream->Timing.F0PVTotal, + Stream->FrameRate)); + } + else { + xil_printf("\tFrame Rate: %s\r\n", + XVidC_GetFrameRateStr(Stream->VmId)); + xil_printf("\tResolution: %s\r\n", + XVidC_GetVideoModeStr(Stream->VmId)); + xil_printf("\tPixel Clock: %d\r\n", + XVidC_GetPixelClockHzByVmId(Stream->VmId)); + } +} + +/******************************************************************************/ +/** + * This function prints timing information on STDIO/Uart console. + * + * @param Timing is a pointer to Video Timing structure of the stream. + * @param IsInterlaced is a TRUE/FALSE flag that denotes the timing + * parameter is for interlaced/progressive stream. + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +void XVidC_ReportTiming(const XVidC_VideoTiming *Timing, u8 IsInterlaced) +{ + xil_printf("\r\n\tHSYNC Timing: hav=%04d, hfp=%02d, hsw=%02d(hsp=%d), " + "hbp=%03d, htot=%04d \n\r", Timing->HActive, + Timing->HFrontPorch, Timing->HSyncWidth, + Timing->HSyncPolarity, + Timing->HBackPorch, Timing->HTotal); + + /* Interlaced */ + if (IsInterlaced) { + xil_printf("\tVSYNC Timing (Field 0): vav=%04d, vfp=%02d, " + "vsw=%02d(vsp=%d), vbp=%03d, vtot=%04d\n\r", + Timing->VActive, Timing->F0PVFrontPorch, + Timing->F0PVSyncWidth, Timing->VSyncPolarity, + Timing->F0PVBackPorch, Timing->F0PVTotal); + xil_printf("\tVSYNC Timing (Field 1): vav=%04d, vfp=%02d, " + "vsw=%02d(vsp=%d), vbp=%03d, vtot=%04d\n\r", + Timing->VActive, Timing->F1VFrontPorch, + Timing->F1VSyncWidth, Timing->VSyncPolarity, + Timing->F1VBackPorch, Timing->F1VTotal); + } + /* Progressive */ + else { + xil_printf("\tVSYNC Timing: vav=%04d, vfp=%02d, " + "vsw=%02d(vsp=%d), vbp=%03d, vtot=%04d\n\r", + Timing->VActive, Timing->F0PVFrontPorch, + Timing->F0PVSyncWidth, Timing->VSyncPolarity, + Timing->F0PVBackPorch, Timing->F0PVTotal); + } +} + +/******************************************************************************/ +/** + * This function returns the pointer to video mode data at the provided index + * of the custom video mode table. + * + * @param VmId specifies the resolution ID. + * + * @return Pointer to XVidC_VideoTimingMode structure based on the given + * video mode. + * + * @note None. + * +*******************************************************************************/ +static const XVidC_VideoTimingMode *XVidC_GetCustomVideoModeData( + XVidC_VideoMode VmId) +{ + u16 Index; + + for (Index = 0; Index < XVidC_NumCustomModes; Index++) { + if (VmId == (XVidC_CustomTimingModes[Index].VmId)) { + return &(XVidC_CustomTimingModes[Index]); + } + } + + /* ID not found within the custom video mode table. */ + return NULL; +} + +/******************************************************************************/ +/** + * This function returns whether or not the video timing mode is a reduced + * blanking mode or not. + * + * @param VideoModeStr specifies the resolution name string. + * @param RbN specifies the type of reduced blanking: + * - 0 = No Reduced Blanking + * - 1 = RB + * - 2 = RB2 + * + * @return If the reduced blanking type is compatible with the video mode: + * - 0 = Not supported + * - 1 = Video mode supports the RB type + * + * @note None. + * +*******************************************************************************/ +static u8 XVidC_IsVtmRb(const char *VideoModeStr, u8 RbN) +{ + while ((*VideoModeStr !='\0') && (*VideoModeStr != 'R')) { + VideoModeStr++; + } + + if (*(VideoModeStr + 2) == ')') { + return RbN == 1; + } + if (*(VideoModeStr + 2) == '2') { + return RbN == 2; + } + return 0; +} +/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc.h new file mode 100644 index 0000000..bcd3d0b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc.h
@@ -0,0 +1,621 @@ +/******************************************************************************* + * + * Copyright (C) 2017 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xvidc.h + * @addtogroup video_common_v4_3 + * @{ + * @details + * + * Contains common structures, definitions, macros, and utility functions that + * are typically used by video-related drivers and applications. + * + * @note None. + * + * <pre> + * MODIFICATION HISTORY: + * + * Ver Who Date Changes + * ----- ---- -------- ----------------------------------------------- + * 1.0 rc, 01/10/15 Initial release. + * als + * 2.0 als 08/14/15 Added new video timings. + * 2.2 als 02/01/16 Functions with pointer arguments that don't modify + * contents now const. + * Added ability to insert a custom video timing table: + * XVidC_RegisterCustomTimingModes + * XVidC_UnregisterCustomTimingMode + * yh Added 3D support. + * 3.0 aad 05/13/16 Added API to search for RB video modes. + * als 05/16/16 Added Y-only to color format enum. + * 3.1 rco 07/26/17 Moved timing table extern definition to xvidc.c + * Added video-in-memory color formats + * Updated XVidC_RegisterCustomTimingModes API signature + * 4.1 rco 11/23/17 Added new memory formats + * Added xil_printf include statement + * Added new API XVidC_GetVideoModeIdWBlanking + * Fix C++ warnings + * 4.2 jsr 07/22/17 Added new video modes, framerates, color formats for SDI + * New member AspectRatio is added to video stream structure + * Reordered XVidC_VideoMode enum variables and corrected the + * memory format enums + * aad 07/10/17 Add XVIDC_VM_3840x2160_60_P_RB video format + * vyc 10/04/17 Added new streaming alpha formats and new memory formats + * aad 09/05/17 Add XVIDC_VM_1366x768_60_P_RB resolution + * 4.3 eb 26/01/18 Added API XVidC_GetVideoModeIdExtensive + * jsr 02/22/18 Added XVIDC_CSF_YCBCR_420 color space format + * vyc 04/04/18 Added BGR8 memory format + * </pre> + * +*******************************************************************************/ + +#ifndef XVIDC_H_ /* Prevent circular inclusions by using protection macros. */ +#define XVIDC_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************* Include Files ********************************/ + +#include "xil_types.h" +#include "xil_printf.h" + +/************************** Constant Definitions ******************************/ + +/** + * This typedef enumerates the list of available standard display monitor + * timings as specified in the xvidc_timings_table.c file. The naming format is: + * + * XVIDC_VM_<RESOLUTION>_<REFRESH RATE (HZ)>_<P|I>(_RB) + * + * Where RB stands for reduced blanking. + */ +typedef enum { + /* Interlaced modes. */ + XVIDC_VM_720x480_60_I = 0, + XVIDC_VM_720x576_50_I, + XVIDC_VM_1440x480_60_I, + XVIDC_VM_1440x576_50_I, + XVIDC_VM_1920x1080_48_I, + XVIDC_VM_1920x1080_50_I, + XVIDC_VM_1920x1080_60_I, + XVIDC_VM_1920x1080_96_I, + XVIDC_VM_1920x1080_100_I, + XVIDC_VM_1920x1080_120_I, + XVIDC_VM_2048x1080_48_I, + XVIDC_VM_2048x1080_50_I, + XVIDC_VM_2048x1080_60_I, + XVIDC_VM_2048x1080_96_I, + XVIDC_VM_2048x1080_100_I, + XVIDC_VM_2048x1080_120_I, + + + /* Progressive modes. */ + XVIDC_VM_640x350_85_P, + XVIDC_VM_640x480_60_P, + XVIDC_VM_640x480_72_P, + XVIDC_VM_640x480_75_P, + XVIDC_VM_640x480_85_P, + XVIDC_VM_720x400_85_P, + XVIDC_VM_720x480_60_P, + XVIDC_VM_720x576_50_P, + XVIDC_VM_800x600_56_P, + XVIDC_VM_800x600_60_P, + XVIDC_VM_800x600_72_P, + XVIDC_VM_800x600_75_P, + XVIDC_VM_800x600_85_P, + XVIDC_VM_800x600_120_P_RB, + XVIDC_VM_848x480_60_P, + XVIDC_VM_1024x768_60_P, + XVIDC_VM_1024x768_70_P, + XVIDC_VM_1024x768_75_P, + XVIDC_VM_1024x768_85_P, + XVIDC_VM_1024x768_120_P_RB, + XVIDC_VM_1152x864_75_P, + XVIDC_VM_1280x720_24_P, + XVIDC_VM_1280x720_25_P, + XVIDC_VM_1280x720_30_P, + XVIDC_VM_1280x720_50_P, + XVIDC_VM_1280x720_60_P, + XVIDC_VM_1280x768_60_P, + XVIDC_VM_1280x768_60_P_RB, + XVIDC_VM_1280x768_75_P, + XVIDC_VM_1280x768_85_P, + XVIDC_VM_1280x768_120_P_RB, + XVIDC_VM_1280x800_60_P, + XVIDC_VM_1280x800_60_P_RB, + XVIDC_VM_1280x800_75_P, + XVIDC_VM_1280x800_85_P, + XVIDC_VM_1280x800_120_P_RB, + XVIDC_VM_1280x960_60_P, + XVIDC_VM_1280x960_85_P, + XVIDC_VM_1280x960_120_P_RB, + XVIDC_VM_1280x1024_60_P, + XVIDC_VM_1280x1024_75_P, + XVIDC_VM_1280x1024_85_P, + XVIDC_VM_1280x1024_120_P_RB, + XVIDC_VM_1360x768_60_P, + XVIDC_VM_1360x768_120_P_RB, + XVIDC_VM_1366x768_60_P, + XVIDC_VM_1366x768_60_P_RB, + XVIDC_VM_1400x1050_60_P, + XVIDC_VM_1400x1050_60_P_RB, + XVIDC_VM_1400x1050_75_P, + XVIDC_VM_1400x1050_85_P, + XVIDC_VM_1400x1050_120_P_RB, + XVIDC_VM_1440x240_60_P, + XVIDC_VM_1440x900_60_P, + XVIDC_VM_1440x900_60_P_RB, + XVIDC_VM_1440x900_75_P, + XVIDC_VM_1440x900_85_P, + XVIDC_VM_1440x900_120_P_RB, + XVIDC_VM_1600x1200_60_P, + XVIDC_VM_1600x1200_65_P, + XVIDC_VM_1600x1200_70_P, + XVIDC_VM_1600x1200_75_P, + XVIDC_VM_1600x1200_85_P, + XVIDC_VM_1600x1200_120_P_RB, + XVIDC_VM_1680x720_50_P, + XVIDC_VM_1680x720_60_P, + XVIDC_VM_1680x720_100_P, + XVIDC_VM_1680x720_120_P, + XVIDC_VM_1680x1050_50_P, + XVIDC_VM_1680x1050_60_P, + XVIDC_VM_1680x1050_60_P_RB, + XVIDC_VM_1680x1050_75_P, + XVIDC_VM_1680x1050_85_P, + XVIDC_VM_1680x1050_120_P_RB, + XVIDC_VM_1792x1344_60_P, + XVIDC_VM_1792x1344_75_P, + XVIDC_VM_1792x1344_120_P_RB, + XVIDC_VM_1856x1392_60_P, + XVIDC_VM_1856x1392_75_P, + XVIDC_VM_1856x1392_120_P_RB, + XVIDC_VM_1920x1080_24_P, + XVIDC_VM_1920x1080_25_P, + XVIDC_VM_1920x1080_30_P, + XVIDC_VM_1920x1080_48_P, + XVIDC_VM_1920x1080_50_P, + XVIDC_VM_1920x1080_60_P, + XVIDC_VM_1920x1080_100_P, + XVIDC_VM_1920x1080_120_P, + XVIDC_VM_1920x1200_60_P, + XVIDC_VM_1920x1200_60_P_RB, + XVIDC_VM_1920x1200_75_P, + XVIDC_VM_1920x1200_85_P, + XVIDC_VM_1920x1200_120_P_RB, + XVIDC_VM_1920x1440_60_P, + XVIDC_VM_1920x1440_75_P, + XVIDC_VM_1920x1440_120_P_RB, + XVIDC_VM_1920x2160_60_P, + XVIDC_VM_2048x1080_24_P, + XVIDC_VM_2048x1080_25_P, + XVIDC_VM_2048x1080_30_P, + XVIDC_VM_2048x1080_48_P, + XVIDC_VM_2048x1080_50_P, + XVIDC_VM_2048x1080_60_P, + XVIDC_VM_2048x1080_100_P, + XVIDC_VM_2048x1080_120_P, + XVIDC_VM_2560x1080_50_P, + XVIDC_VM_2560x1080_60_P, + XVIDC_VM_2560x1080_100_P, + XVIDC_VM_2560x1080_120_P, + XVIDC_VM_2560x1600_60_P, + XVIDC_VM_2560x1600_60_P_RB, + XVIDC_VM_2560x1600_75_P, + XVIDC_VM_2560x1600_85_P, + XVIDC_VM_2560x1600_120_P_RB, + XVIDC_VM_3840x2160_24_P, + XVIDC_VM_3840x2160_25_P, + XVIDC_VM_3840x2160_30_P, + XVIDC_VM_3840x2160_48_P, + XVIDC_VM_3840x2160_50_P, + XVIDC_VM_3840x2160_60_P, + XVIDC_VM_3840x2160_60_P_RB, + XVIDC_VM_4096x2160_24_P, + XVIDC_VM_4096x2160_25_P, + XVIDC_VM_4096x2160_30_P, + XVIDC_VM_4096x2160_48_P, + XVIDC_VM_4096x2160_50_P, + XVIDC_VM_4096x2160_60_P, + XVIDC_VM_4096x2160_60_P_RB, + + XVIDC_VM_NUM_SUPPORTED, + XVIDC_VM_USE_EDID_PREFERRED, + XVIDC_VM_NO_INPUT, + XVIDC_VM_NOT_SUPPORTED, + XVIDC_VM_CUSTOM, + + /* Marks beginning/end of interlaced/progressive modes in the table. */ + XVIDC_VM_INTL_START = XVIDC_VM_720x480_60_I, + XVIDC_VM_PROG_START = XVIDC_VM_640x350_85_P, + XVIDC_VM_INTL_END = (XVIDC_VM_PROG_START - 1), + XVIDC_VM_PROG_END = (XVIDC_VM_NUM_SUPPORTED - 1), + + /* Common naming. */ + XVIDC_VM_480_60_I = XVIDC_VM_720x480_60_I, + XVIDC_VM_576_50_I = XVIDC_VM_720x576_50_I, + XVIDC_VM_1080_50_I = XVIDC_VM_1920x1080_50_I, + XVIDC_VM_1080_60_I = XVIDC_VM_1920x1080_60_I, + XVIDC_VM_VGA_60_P = XVIDC_VM_640x480_60_P, + XVIDC_VM_480_60_P = XVIDC_VM_720x480_60_P, + XVIDC_VM_SVGA_60_P = XVIDC_VM_800x600_60_P, + XVIDC_VM_XGA_60_P = XVIDC_VM_1024x768_60_P, + XVIDC_VM_720_50_P = XVIDC_VM_1280x720_50_P, + XVIDC_VM_720_60_P = XVIDC_VM_1280x720_60_P, + XVIDC_VM_WXGA_60_P = XVIDC_VM_1366x768_60_P, + XVIDC_VM_UXGA_60_P = XVIDC_VM_1600x1200_60_P, + XVIDC_VM_WSXGA_60_P = XVIDC_VM_1680x1050_60_P, + XVIDC_VM_1080_24_P = XVIDC_VM_1920x1080_24_P, + XVIDC_VM_1080_25_P = XVIDC_VM_1920x1080_25_P, + XVIDC_VM_1080_30_P = XVIDC_VM_1920x1080_30_P, + XVIDC_VM_1080_50_P = XVIDC_VM_1920x1080_50_P, + XVIDC_VM_1080_60_P = XVIDC_VM_1920x1080_60_P, + XVIDC_VM_WUXGA_60_P = XVIDC_VM_1920x1200_60_P, + XVIDC_VM_UHD2_60_P = XVIDC_VM_1920x2160_60_P, + XVIDC_VM_UHD_24_P = XVIDC_VM_3840x2160_24_P, + XVIDC_VM_UHD_25_P = XVIDC_VM_3840x2160_25_P, + XVIDC_VM_UHD_30_P = XVIDC_VM_3840x2160_30_P, + XVIDC_VM_UHD_60_P = XVIDC_VM_3840x2160_60_P, + XVIDC_VM_4K2K_60_P = XVIDC_VM_4096x2160_60_P, + XVIDC_VM_4K2K_60_P_RB = XVIDC_VM_4096x2160_60_P_RB, +} XVidC_VideoMode; + +/** + * Progressive/interlaced video format. + */ +typedef enum { + XVIDC_VF_PROGRESSIVE = 0, + XVIDC_VF_INTERLACED, + XVIDC_VF_UNKNOWN +} XVidC_VideoFormat; + +/** + * Frame rate. + */ +typedef enum { + XVIDC_FR_24HZ = 24, + XVIDC_FR_25HZ = 25, + XVIDC_FR_30HZ = 30, + XVIDC_FR_48HZ = 48, + XVIDC_FR_50HZ = 50, + XVIDC_FR_56HZ = 56, + XVIDC_FR_60HZ = 60, + XVIDC_FR_65HZ = 65, + XVIDC_FR_67HZ = 67, + XVIDC_FR_70HZ = 70, + XVIDC_FR_72HZ = 72, + XVIDC_FR_75HZ = 75, + XVIDC_FR_85HZ = 85, + XVIDC_FR_87HZ = 87, + XVIDC_FR_88HZ = 88, + XVIDC_FR_96HZ = 96, + XVIDC_FR_100HZ = 100, + XVIDC_FR_120HZ = 120, + XVIDC_FR_NUM_SUPPORTED = 18, + XVIDC_FR_UNKNOWN +} XVidC_FrameRate; + +/** + * Color depth - bits per color component. + */ +typedef enum { + XVIDC_BPC_6 = 6, + XVIDC_BPC_8 = 8, + XVIDC_BPC_10 = 10, + XVIDC_BPC_12 = 12, + XVIDC_BPC_14 = 14, + XVIDC_BPC_16 = 16, + XVIDC_BPC_NUM_SUPPORTED = 6, + XVIDC_BPC_UNKNOWN +} XVidC_ColorDepth; + +/** + * Pixels per clock. + */ +typedef enum { + XVIDC_PPC_1 = 1, + XVIDC_PPC_2 = 2, + XVIDC_PPC_4 = 4, + XVIDC_PPC_8 = 8, + XVIDC_PPC_NUM_SUPPORTED = 4, +} XVidC_PixelsPerClock; + +/** + * Color space format. + */ +typedef enum { + /* Streaming video formats */ + XVIDC_CSF_RGB = 0, + XVIDC_CSF_YCRCB_444, + XVIDC_CSF_YCRCB_422, + XVIDC_CSF_YCRCB_420, + XVIDC_CSF_YONLY, + XVIDC_CSF_RGBA, + XVIDC_CSF_YCRCBA_444, + + /* 6 empty slots reserved for video formats for future + * extension + */ + + /* Video in memory formats */ + XVIDC_CSF_MEM_RGBX8 = 10, // [31:0] x:B:G:R 8:8:8:8 + XVIDC_CSF_MEM_YUVX8, // [31:0] x:V:U:Y 8:8:8:8 + XVIDC_CSF_MEM_YUYV8, // [31:0] V:Y:U:Y 8:8:8:8 + XVIDC_CSF_MEM_RGBA8, // [31:0] A:B:G:R 8:8:8:8 + XVIDC_CSF_MEM_YUVA8, // [31:0] A:V:U:Y 8:8:8:8 + XVIDC_CSF_MEM_RGBX10, // [31:0] x:B:G:R 2:10:10:10 + XVIDC_CSF_MEM_YUVX10, // [31:0] x:V:U:Y 2:10:10:10 + XVIDC_CSF_MEM_RGB565, // [15:0] B:G:R 5:6:5 + XVIDC_CSF_MEM_Y_UV8, // [15:0] Y:Y 8:8, [15:0] V:U 8:8 + XVIDC_CSF_MEM_Y_UV8_420, // [15:0] Y:Y 8:8, [15:0] V:U 8:8 + XVIDC_CSF_MEM_RGB8, // [23:0] B:G:R 8:8:8 + XVIDC_CSF_MEM_YUV8, // [24:0] V:U:Y 8:8:8 + XVIDC_CSF_MEM_Y_UV10, // [31:0] x:Y:Y:Y 2:10:10:10 [31:0] x:U:V:U 2:10:10:10 + XVIDC_CSF_MEM_Y_UV10_420, // [31:0] x:Y:Y:Y 2:10:10:10 [31:0] x:U:V:U 2:10:10:10 + XVIDC_CSF_MEM_Y8, // [31:0] Y:Y:Y:Y 8:8:8:8 + XVIDC_CSF_MEM_Y10, // [31:0] x:Y:Y:Y 2:10:10:10 + XVIDC_CSF_MEM_BGRA8, // [31:0] A:R:G:B 8:8:8:8 + XVIDC_CSF_MEM_BGRX8, // [31:0] X:R:G:B 8:8:8:8 + XVIDC_CSF_MEM_UYVY8, // [31:0] Y:V:Y:U 8:8:8:8 + XVIDC_CSF_MEM_BGR8, // [23:0] R:G:B 8:8:8 + XVIDC_CSF_MEM_END, // End of memory formats + + /* Streaming formats with components re-ordered */ + XVIDC_CSF_YCBCR_422 = 64, + XVIDC_CSF_YCBCR_420, + + + XVIDC_CSF_NUM_SUPPORTED, // includes the reserved slots + XVIDC_CSF_UNKNOWN, + XVIDC_CSF_STRM_START = XVIDC_CSF_RGB, + XVIDC_CSF_STRM_END = XVIDC_CSF_YONLY, + XVIDC_CSF_MEM_START = XVIDC_CSF_MEM_RGBX8, + XVIDC_CSF_NUM_STRM = (XVIDC_CSF_STRM_END - XVIDC_CSF_STRM_START + 1), + XVIDC_CSF_NUM_MEM = (XVIDC_CSF_MEM_END - XVIDC_CSF_MEM_START) +} XVidC_ColorFormat; + + +/** + * Image Aspect Ratio. + */ +typedef enum { + XVIDC_AR_4_3 = 0, + XVIDC_AR_16_9 = 1 +} XVidC_AspectRatio; + +/** + * Color space conversion standard. + */ +typedef enum { + XVIDC_BT_2020 = 0, + XVIDC_BT_709, + XVIDC_BT_601, + XVIDC_BT_NUM_SUPPORTED, + XVIDC_BT_UNKNOWN +} XVidC_ColorStd; + +/** + * Color conversion output range. + */ +typedef enum { + XVIDC_CR_16_235 = 0, + XVIDC_CR_16_240, + XVIDC_CR_0_255, + XVIDC_CR_NUM_SUPPORTED, + XVIDC_CR_UNKNOWN_RANGE +} XVidC_ColorRange; + +/** + * 3D formats. + */ +typedef enum { + XVIDC_3D_FRAME_PACKING = 0, /**< Frame packing. */ + XVIDC_3D_FIELD_ALTERNATIVE, /**< Field alternative. */ + XVIDC_3D_LINE_ALTERNATIVE, /**< Line alternative. */ + XVIDC_3D_SIDE_BY_SIDE_FULL, /**< Side-by-side (full). */ + XVIDC_3D_TOP_AND_BOTTOM_HALF, /**< Top-and-bottom (half). */ + XVIDC_3D_SIDE_BY_SIDE_HALF, /**< Side-by-side (half). */ + XVIDC_3D_UNKNOWN +} XVidC_3DFormat; + +/** + * 3D Sub-sampling methods. + */ +typedef enum { + XVIDC_3D_SAMPLING_HORIZONTAL = 0, /**< Horizontal sub-sampling. */ + XVIDC_3D_SAMPLING_QUINCUNX, /**< Quincunx matrix. */ + XVIDC_3D_SAMPLING_UNKNOWN +} XVidC_3DSamplingMethod; + +/** + * 3D Sub-sampling positions. + */ +typedef enum { + XVIDC_3D_SAMPPOS_OLOR = 0, /**< Odd/Left, Odd/Right. */ + XVIDC_3D_SAMPPOS_OLER, /**< Odd/Left, Even/Right. */ + XVIDC_3D_SAMPPOS_ELOR, /**< Even/Left, Odd/Right. */ + XVIDC_3D_SAMPPOS_ELER, /**< Even/Left, Even/Right. */ + XVIDC_3D_SAMPPOS_UNKNOWN +} XVidC_3DSamplingPosition; + +/****************************** Type Definitions ******************************/ + +/** + * Video timing structure. + */ +typedef struct { + u16 HActive; + u16 HFrontPorch; + u16 HSyncWidth; + u16 HBackPorch; + u16 HTotal; + u8 HSyncPolarity; + u16 VActive; + u16 F0PVFrontPorch; + u16 F0PVSyncWidth; + u16 F0PVBackPorch; + u16 F0PVTotal; + u16 F1VFrontPorch; + u16 F1VSyncWidth; + u16 F1VBackPorch; + u16 F1VTotal; + u8 VSyncPolarity; +} XVidC_VideoTiming; + +/** + * 3D Sampling info structure. + */ +typedef struct { + XVidC_3DSamplingMethod Method; + XVidC_3DSamplingPosition Position; +} XVidC_3DSamplingInfo; + +/** + * 3D info structure. + */ +typedef struct { + XVidC_3DFormat Format; + XVidC_3DSamplingInfo Sampling; +} XVidC_3DInfo; + +/** + * Video stream structure. + */ +typedef struct { + XVidC_ColorFormat ColorFormatId; + XVidC_ColorDepth ColorDepth; + XVidC_PixelsPerClock PixPerClk; + XVidC_FrameRate FrameRate; + XVidC_AspectRatio AspectRatio; + u8 IsInterlaced; + u8 Is3D; + XVidC_3DInfo Info_3D; + XVidC_VideoMode VmId; + XVidC_VideoTiming Timing; +} XVidC_VideoStream; + +/** + * Video window structure. + */ +typedef struct { + u32 StartX; + u32 StartY; + u32 Width; + u32 Height; +} XVidC_VideoWindow; + +/** + * Video timing mode from the video timing table. + */ +typedef struct { + XVidC_VideoMode VmId; + const char Name[21]; + XVidC_FrameRate FrameRate; + XVidC_VideoTiming Timing; +} XVidC_VideoTimingMode; + +/** + * Callback type which represents a custom timer wait handler. This is only + * used for Microblaze since it doesn't have a native sleep function. To avoid + * dependency on a hardware timer, the default wait functionality is implemented + * using loop iterations; this isn't too accurate. Therefore a custom timer + * handler is used, the user may implement their own wait implementation. + * + * @param TimerPtr is a pointer to the timer instance. + * @param Delay is the duration (msec/usec) to be passed to the timer + * function. + * +*******************************************************************************/ +typedef void (*XVidC_DelayHandler)(void *TimerPtr, u32 Delay); + +/**************************** Function Prototypes *****************************/ + +u32 XVidC_RegisterCustomTimingModes(const XVidC_VideoTimingMode *CustomTable, + u16 NumElems); +void XVidC_UnregisterCustomTimingModes(void); +u32 XVidC_GetPixelClockHzByHVFr(u32 HTotal, u32 VTotal, u8 FrameRate); +u32 XVidC_GetPixelClockHzByVmId(XVidC_VideoMode VmId); +XVidC_VideoFormat XVidC_GetVideoFormat(XVidC_VideoMode VmId); +u8 XVidC_IsInterlaced(XVidC_VideoMode VmId); +const XVidC_VideoTimingMode* XVidC_GetVideoModeData(XVidC_VideoMode VmId); +const char *XVidC_GetVideoModeStr(XVidC_VideoMode VmId); +const char *XVidC_GetFrameRateStr(XVidC_VideoMode VmId); +const char *XVidC_GetColorFormatStr(XVidC_ColorFormat ColorFormatId); +XVidC_FrameRate XVidC_GetFrameRate(XVidC_VideoMode VmId); +const XVidC_VideoTiming* XVidC_GetTimingInfo(XVidC_VideoMode VmId); +void XVidC_ReportStreamInfo(const XVidC_VideoStream *Stream); +void XVidC_ReportTiming(const XVidC_VideoTiming *Timing, u8 IsInterlaced); +const char *XVidC_Get3DFormatStr(XVidC_3DFormat Format); +u32 XVidC_SetVideoStream(XVidC_VideoStream *VidStrmPtr, XVidC_VideoMode VmId, + XVidC_ColorFormat ColorFormat, XVidC_ColorDepth Bpc, + XVidC_PixelsPerClock Ppc); +u32 XVidC_Set3DVideoStream(XVidC_VideoStream *VidStrmPtr, XVidC_VideoMode VmId, + XVidC_ColorFormat ColorFormat, XVidC_ColorDepth Bpc, + XVidC_PixelsPerClock Ppc, XVidC_3DInfo *Info3DPtr); +XVidC_VideoMode XVidC_GetVideoModeId(u32 Width, u32 Height, u32 FrameRate, + u8 IsInterlaced); +XVidC_VideoMode XVidC_GetVideoModeIdExtensive(XVidC_VideoTiming *Timing, + u32 FrameRate, + u8 IsInterlaced, + u8 IsExtensive); +XVidC_VideoMode XVidC_GetVideoModeIdRb(u32 Width, u32 Height, u32 FrameRate, + u8 IsInterlaced, u8 RbN); +XVidC_VideoMode XVidC_GetVideoModeIdWBlanking(const XVidC_VideoTiming *Timing, + u32 FrameRate, u8 IsInterlaced); + +/******************* Macros (Inline Functions) Definitions ********************/ + +/*****************************************************************************/ +/** + * This macro check if video stream is 3D or 2D. + * + * @param VidStreamPtr is a pointer to the XVidC_VideoStream structure. + * + * @return 3D(1)/2D(0) + * + * @note C-style signature: + * u8 XDp_IsStream3D(XVidC_VideoStream *VidStreamPtr) + * + *****************************************************************************/ +#define XVidC_IsStream3D(VidStreamPtr) ((VidStreamPtr)->Is3D) + +/*************************** Variable Declarations ****************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* XVIDC_H_ */ +/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc_cea861.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc_cea861.h new file mode 100644 index 0000000..9e50b9d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc_cea861.h
@@ -0,0 +1,399 @@ +/* vim: set et fde fdm=syntax ft=c.doxygen ts=4 sts=4 sw=4 : */ +/* + * Copyright © 2010-2011 Saleem Abdulrasool <compnerd@compnerd.org>. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef xvidc_cea861_h +#define xvidc_cea861_h + +#define XVIDC_EDID_VERBOSITY 0 + +#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof(arr[0])) + +#define XVIDC_CEA861_NO_DTDS_PRESENT (0x04) + +#define HDMI_VSDB_EXTENSION_FLAGS_OFFSET (0x06) +#define HDMI_VSDB_MAX_TMDS_OFFSET (0x07) +#define HDMI_VSDB_LATENCY_FIELDS_OFFSET (0x08) + +static const u8 HDMI_OUI[] = { 0x00, 0x0C, 0x03 }; +static const u8 HDMI_OUI_HF[] = { 0xC4, 0x5D, 0xD8 }; + +enum xvidc_cea861_data_block_type { + XVIDC_CEA861_DATA_BLOCK_TYPE_RESERVED0, + XVIDC_CEA861_DATA_BLOCK_TYPE_AUDIO, + XVIDC_CEA861_DATA_BLOCK_TYPE_VIDEO, + XVIDC_CEA861_DATA_BLOCK_TYPE_VENDOR_SPECIFIC, + XVIDC_CEA861_DATA_BLOCK_TYPE_SPEAKER_ALLOCATION, + XVIDC_CEA861_DATA_BLOCK_TYPE_VESA_DTC, + XVIDC_CEA861_DATA_BLOCK_TYPE_RESERVED6, + XVIDC_CEA861_DATA_BLOCK_TYPE_EXTENDED, +}; + +enum xvidc_cea861_extended_tag_type_data_block { + XVIDC_CEA861_EXT_TAG_TYPE_VIDEO_CAPABILITY, + XVIDC_CEA861_EXT_TAG_TYPE_VENDOR_SPECIFIC, + XVIDC_CEA861_EXT_TAG_TYPE_VESA_DISPLAY_DEVICE, + XVIDC_CEA861_EXT_TAG_TYPE_VESA_VIDEO_TIMING_BLOCK_EXT, + XVIDC_CEA861_EXT_TAG_TYPE_RESERVED_FOR_HDMI_VIDEO_DATA_BLOCK, + XVIDC_CEA861_EXT_TAG_TYPE_COLORIMETRY, + XVIDC_CEA861_EXT_TAG_TYPE_HDR_STATIC_METADATA, + XVIDC_CEA861_EXT_TAG_TYPE_HDR_DYNAMIC_METADATA, + XVIDC_CEA861_EXT_TAG_TYPE_RESERVED2, + XVIDC_CEA861_EXT_TAG_TYPE_RESERVED3, + XVIDC_CEA861_EXT_TAG_TYPE_RESERVED4, + XVIDC_CEA861_EXT_TAG_TYPE_RESERVED5, + XVIDC_CEA861_EXT_TAG_TYPE_RESERVED6, + XVIDC_CEA861_EXT_TAG_TYPE_VIDEO_FRMT_PREFERENCE, + XVIDC_CEA861_EXT_TAG_TYPE_YCBCR420_VIDEO, + XVIDC_CEA861_EXT_TAG_TYPE_YCBCR420_CAPABILITY_MAP, + XVIDC_CEA861_EXT_TAG_TYPE_CEA_MISC_AUDIO_FIELDS, + XVIDC_CEA861_EXT_TAG_TYPE_VENDOR_SPECIFC_AUDIO, + XVIDC_CEA861_EXT_TAG_TYPE_HDMI_AUDIO, + XVIDC_CEA861_EXT_TAG_TYPE_ROOM_CONFIGURATION, + XVIDC_CEA861_EXT_TAG_TYPE_SPEAKER_LOCATION, + XVIDC_CEA861_EXT_TAG_TYPE_INFOFRAME = 32, +/* Can be extend to 255, refer table 46 cea data block tag codes cea-861-f */ +}; + +enum xvidc_cea861_audio_format { + XVIDC_CEA861_AUDIO_FORMAT_RESERVED, + XVIDC_CEA861_AUDIO_FORMAT_LPCM, + XVIDC_CEA861_AUDIO_FORMAT_AC_3, + XVIDC_CEA861_AUDIO_FORMAT_MPEG_1, + XVIDC_CEA861_AUDIO_FORMAT_MP3, + XVIDC_CEA861_AUDIO_FORMAT_MPEG2, + XVIDC_CEA861_AUDIO_FORMAT_AAC_LC, + XVIDC_CEA861_AUDIO_FORMAT_DTS, + XVIDC_CEA861_AUDIO_FORMAT_ATRAC, + XVIDC_CEA861_AUDIO_FORMAT_DSD, + XVIDC_CEA861_AUDIO_FORMAT_E_AC_3, + XVIDC_CEA861_AUDIO_FORMAT_DTS_HD, + XVIDC_CEA861_AUDIO_FORMAT_MLP, + XVIDC_CEA861_AUDIO_FORMAT_DST, + XVIDC_CEA861_AUDIO_FORMAT_WMA_PRO, + XVIDC_CEA861_AUDIO_FORMAT_EXTENDED, +}; + +struct __attribute__ (( packed )) xvidc_cea861_timing_block { + /* CEA Extension Header */ + u8 tag; + u8 revision; + u8 dtd_offset; + + /* Global Declarations */ + unsigned native_dtds : 4; + unsigned yuv_422_supported : 1; + unsigned yuv_444_supported : 1; + unsigned basic_audio_supported : 1; + unsigned underscan_supported : 1; + + u8 data[123]; + + u8 checksum; +}; + +struct __attribute__ (( packed )) xvidc_cea861_data_block_header { + unsigned length : 5; + unsigned tag : 3; +}; + +struct __attribute__ (( packed )) xvidc_cea861_short_video_descriptor { + unsigned video_identification_code : 7; + unsigned native : 1; +}; +#if XVIDC_EDID_VERBOSITY > 1 +struct __attribute__ (( packed )) xvidc_cea861_video_data_block { + struct xvidc_cea861_data_block_header header; + struct xvidc_cea861_short_video_descriptor svd[]; +}; +#endif +struct __attribute__ (( packed )) xvidc_cea861_short_audio_descriptor { + unsigned channels : 3; /* = value + 1 */ + unsigned audio_format : 4; + unsigned : 1; + + unsigned sample_rate_32_kHz : 1; + unsigned sample_rate_44_1_kHz : 1; + unsigned sample_rate_48_kHz : 1; + unsigned sample_rate_88_2_kHz : 1; + unsigned sample_rate_96_kHz : 1; + unsigned sample_rate_176_4_kHz : 1; + unsigned sample_rate_192_kHz : 1; + unsigned : 1; + + union { + struct __attribute__ (( packed )) { + unsigned bitrate_16_bit : 1; + unsigned bitrate_20_bit : 1; + unsigned bitrate_24_bit : 1; + unsigned : 5; + } lpcm; + + u8 maximum_bit_rate; /* formats 2-8; = value * 8 kHz */ + + u8 format_dependent; /* formats 9-13; */ + + struct __attribute__ (( packed )) { + unsigned profile : 3; + unsigned : 5; + } wma_pro; + + struct __attribute__ (( packed )) { + unsigned : 3; + unsigned code : 5; + } extension; + } flags; +}; +#if XVIDC_EDID_VERBOSITY > 1 +struct __attribute__ (( packed )) xvidc_cea861_audio_data_block { + struct xvidc_cea861_data_block_header header; + struct xvidc_cea861_short_audio_descriptor sad[]; +}; +#endif +#if XVIDC_EDID_VERBOSITY > 1 +struct __attribute__ (( packed )) xvidc_cea861_speaker_allocation { + unsigned front_left_right : 1; + unsigned front_lfe : 1; /* low frequency effects */ + unsigned front_center : 1; + unsigned rear_left_right : 1; + unsigned rear_center : 1; + unsigned front_left_right_center : 1; + unsigned rear_left_right_center : 1; + unsigned front_left_right_wide : 1; + + unsigned front_left_right_high : 1; + unsigned top_center : 1; + unsigned front_center_high : 1; + unsigned : 5; + + unsigned : 8; +}; +#endif +#if XVIDC_EDID_VERBOSITY > 1 +struct __attribute__ (( packed )) xvidc_cea861_speaker_allocation_data_block { + struct xvidc_cea861_data_block_header header; + struct xvidc_cea861_speaker_allocation payload; +}; +#endif +struct __attribute__ (( packed )) xvidc_cea861_vendor_specific_data_block { + struct xvidc_cea861_data_block_header header; + u8 ieee_registration[3]; + u8 data[30]; +}; + +struct __attribute__ (( packed )) xvidc_cea861_extended_data_block { + struct xvidc_cea861_data_block_header header; + u8 xvidc_cea861_extended_tag_codes; + u8 data[30]; +}; + +#if XVIDC_EDID_VERBOSITY > 1 +static const struct xvidc_cea861_timing { + const u16 hactive; + const u16 vactive; + const enum { + INTERLACED, + PROGRESSIVE, + } mode; + const u16 htotal; + const u16 hblank; + const u16 vtotal; + const double vblank; + const double hfreq; + const double vfreq; + const double pixclk; +} xvidc_cea861_timings[] = { + [ 1] = { 640, 480, PROGRESSIVE, 800, 160, 525, 45.0, 31.469, 59.940, 25.175 }, + [ 2] = { 720, 480, PROGRESSIVE, 858, 138, 525, 45.0, 31.469, 59.940, 27.000 }, + [ 3] = { 720, 480, PROGRESSIVE, 858, 138, 525, 45.0, 31.469, 59.940, 27.000 }, + [ 4] = { 1280, 720, PROGRESSIVE, 1650, 370, 750, 30.0, 45.000, 60.000, 74.250 }, + [ 5] = { 1920,1080, INTERLACED, 2200, 280, 1125, 22.5, 33.750, 60.000, 72.250 }, + [ 6] = { 1440, 480, INTERLACED, 1716, 276, 525, 22.5, 15.734, 59.940, 27.000 }, + [ 7] = { 1440, 480, INTERLACED, 1716, 276, 525, 22.5, 15.734, 59.940, 27.000 }, + [ 8] = { 1440, 240, PROGRESSIVE, 1716, 276, 262, 22.0, 15.734, 60.054, 27.000 }, + [ 9] = { 1440, 240, PROGRESSIVE, 1716, 276, 262, 22.0, 15.734, 59.826, 27.000 }, + [ 10] = { 2880, 480, INTERLACED, 3432, 552, 525, 22.5, 15.734, 59.940, 54.000 }, + [ 11] = { 2880, 480, INTERLACED, 3432, 552, 525, 22.5, 15.734, 59.940, 54.000 }, + [ 12] = { 2880, 240, PROGRESSIVE, 3432, 552, 262, 22.0, 15.734, 60.054, 54.000 }, + [ 13] = { 2880, 240, PROGRESSIVE, 3432, 552, 262, 22.0, 15.734, 59.826, 54.000 }, + [ 14] = { 1440, 480, PROGRESSIVE, 1716, 276, 525, 45.0, 31.469, 59.940, 54.000 }, + [ 15] = { 1440, 480, PROGRESSIVE, 1716, 276, 525, 45.0, 31.469, 59.940, 54.000 }, + [ 16] = { 1920, 1080, PROGRESSIVE, 2200, 280, 1125, 45.0, 67.500, 60.000, 148.500 }, + [ 17] = { 720, 576, PROGRESSIVE, 864, 144, 625, 49.0, 31.250, 50.000, 27.000 }, + [ 18] = { 720, 576, PROGRESSIVE, 864, 144, 625, 49.0, 31.250, 50.000, 27.000 }, + [ 19] = { 1280, 720, PROGRESSIVE, 1980, 700, 750, 30.0, 37.500, 50.000, 74.250 }, + [ 20] = { 1920, 1080, INTERLACED, 2640, 720, 1125, 22.5, 28.125, 50.000, 74.250 }, + [ 21] = { 1440, 576, INTERLACED, 1728, 288, 625, 24.5, 15.625, 50.000, 27.000 }, + [ 22] = { 1440, 576, INTERLACED, 1728, 288, 625, 24.5, 15.625, 50.000, 27.000 }, + [ 23] = { 1440, 288, PROGRESSIVE, 1728, 288, 312, 24.0, 15.625, 50.080, 27.000 }, + [ 24] = { 1440, 288, PROGRESSIVE, 1728, 288, 313, 25.0, 15.625, 49.920, 27.000 }, + [ 25] = { 2880, 576, INTERLACED, 3456, 576, 625, 24.5, 15.625, 50.000, 54.000 }, + [ 26] = { 2880, 576, INTERLACED, 3456, 576, 625, 24.5, 15.625, 50.000, 54.000 }, + [ 27] = { 2880, 288, PROGRESSIVE, 3456, 576, 312, 24.0, 15.625, 50.080, 54.000 }, + [ 28] = { 2880, 288, PROGRESSIVE, 3456, 576, 313, 25.0, 15.625, 49.920, 54.000 }, + [ 29] = { 1440, 576, PROGRESSIVE, 1728, 288, 625, 49.0, 31.250, 50.000, 54.000 }, + [ 30] = { 1440, 576, PROGRESSIVE, 1728, 288, 625, 49.0, 31.250, 50.000, 54.000 }, + [ 31] = { 1920, 1080, PROGRESSIVE, 2640, 720, 1125, 45.0, 56.250, 50.000, 148.500 }, + [ 32] = { 1920, 1080, PROGRESSIVE, 2750, 830, 1125, 45.0, 27.000, 24.000, 74.250 }, + [ 33] = { 1920, 1080, PROGRESSIVE, 2640, 720, 1125, 45.0, 28.125, 25.000, 74.250 }, + [ 34] = { 1920, 1080, PROGRESSIVE, 2200, 280, 1125, 45.0, 33.750, 30.000, 74.250 }, + [ 35] = { 2880, 480, PROGRESSIVE, 3432, 552, 525, 45.0, 31.469, 59.940, 108.500 }, + [ 36] = { 2880, 480, PROGRESSIVE, 3432, 552, 525, 45.0, 31.469, 59.940, 108.500 }, + [ 37] = { 2880, 576, PROGRESSIVE, 3456, 576, 625, 49.0, 31.250, 50.000, 108.000 }, + [ 38] = { 2880, 576, PROGRESSIVE, 3456, 576, 625, 49.0, 31.250, 50.000, 108.000 }, + [ 39] = { 1920, 1080, INTERLACED, 2304, 384, 1250, 85.0, 31.250, 50.000, 72.000 }, + [ 40] = { 1920, 1080, INTERLACED, 2640, 720, 1125, 22.5, 56.250, 100.000, 148.500 }, + [ 41] = { 1280, 720, PROGRESSIVE, 1980, 700, 750, 30.0, 75.000, 100.000, 148.500 }, + [ 42] = { 720, 576, PROGRESSIVE, 864, 144, 625, 49.0, 62.500, 100.000, 54.000 }, + [ 43] = { 720, 576, PROGRESSIVE, 864, 144, 625, 49.0, 62.500, 100.000, 54.000 }, + [ 44] = { 1440, 576, INTERLACED, 1728, 288, 625, 24.5, 31.250, 100.000, 54.000 }, + [ 45] = { 1440, 576, INTERLACED, 1728, 288, 625, 24.5, 31.250, 100.000, 54.000 }, + [ 46] = { 1920, 1080, INTERLACED, 2200, 280, 1125, 22.5, 67.500, 120.000, 148.500 }, + [ 47] = { 1280, 720, PROGRESSIVE, 1650, 370, 750, 30.0, 90.000, 120.000, 148.500 }, + [ 48] = { 720, 480, PROGRESSIVE, 858, 138, 525, 45.0, 62.937, 119.880, 54.000 }, + [ 49] = { 720, 480, PROGRESSIVE, 858, 138, 525, 45.0, 62.937, 119.880, 54.000 }, + [ 50] = { 1440, 480, INTERLACED, 1716, 276, 525, 22.5, 31.469, 119.880, 54.000 }, + [ 51] = { 1440, 480, INTERLACED, 1716, 276, 525, 22.5, 31.469, 119.880, 54.000 }, + [ 52] = { 720, 576, PROGRESSIVE, 864, 144, 625, 49.0, 125.000, 200.000, 108.000 }, + [ 53] = { 720, 576, PROGRESSIVE, 864, 144, 625, 49.0, 125.000, 200.000, 108.000 }, + [ 54] = { 1440, 576, INTERLACED, 1728, 288, 625, 24.5, 62.500, 200.000, 108.000 }, + [ 55] = { 1440, 576, INTERLACED, 1728, 288, 625, 24.5, 62.500, 200.000, 108.000 }, + [ 56] = { 720, 480, PROGRESSIVE, 858, 138, 525, 45.0, 125.874, 239.760, 108.000 }, + [ 57] = { 720, 480, PROGRESSIVE, 858, 138, 525, 45.0, 125.874, 239.760, 108.000 }, + [ 58] = { 1440, 480, INTERLACED, 1716, 276, 525, 22.5, 62.937, 239.760, 108.000 }, + [ 59] = { 1440, 480, INTERLACED, 1716, 276, 525, 22.5, 62.937, 239.760, 108.000 }, + [60 ] = {1280, 720 , PROGRESSIVE, 3300, 2020, 750 , 30 , 18 , 24.0003, 59.4 }, + [61 ] = {1280, 720 , PROGRESSIVE, 3960, 2680, 750 , 30 , 18.75 , 25 , 74.25 }, + [62 ] = {1280, 720 , PROGRESSIVE, 3300, 2020, 750 , 30 , 22.5 , 30.0003, 74.25 }, + [63 ] = {1920, 1080, PROGRESSIVE, 2200, 280 , 1125, 45 , 135 , 120.003, 297 }, + [64 ] = {1920, 1080, PROGRESSIVE, 2640, 720 , 1125, 45 , 112.5 , 100 , 297 }, + [65 ] = {1280, 720 , PROGRESSIVE, 3300, 2020, 750 , 30 , 18 , 24.0003, 59.4 }, + [66 ] = {1280, 720 , PROGRESSIVE, 3960, 2680, 750 , 30 , 18.75 , 25 , 74.25 }, + [67 ] = {1280, 720 , PROGRESSIVE, 3300, 2020, 750 , 30 , 22.5 , 30.0003, 74.25 }, + [68 ] = {1280, 720 , PROGRESSIVE, 1980, 700 , 750 , 30 , 37.5 , 50 , 74.25 }, + [69 ] = {1280, 720 , PROGRESSIVE, 1650, 370 , 750 , 30 , 45 , 60.0003, 74.25 }, + [70 ] = {1280, 720 , PROGRESSIVE, 1980, 700 , 750 , 30 , 75 , 100 , 148.5 }, + [71 ] = {1280, 720 , PROGRESSIVE, 1650, 370 , 750 , 30 , 90 , 120.003, 148.5 }, + [72 ] = {1920, 1080, PROGRESSIVE, 2750, 830 , 1125, 45 , 27 , 24.0003, 74.25 }, + [73 ] = {1920, 1080, PROGRESSIVE, 2640, 720 , 1125, 45 , 28.125 , 25 , 74.25 }, + [74 ] = {1920, 1080, PROGRESSIVE, 2200, 280 , 1125, 45 , 33.75 , 30.0003, 74.25 }, + [75 ] = {1920, 1080, PROGRESSIVE, 2640, 720 , 1125, 45 , 56.25 , 50 , 148.5 }, + [76 ] = {1920, 1080, PROGRESSIVE, 2200, 280 , 1125, 45 , 67.5 , 60.0003, 148.5 }, + [77 ] = {1920, 1080, PROGRESSIVE, 2640, 720 , 1125, 45 , 112.5 , 100 , 297 }, + [78 ] = {1920, 1080, PROGRESSIVE, 2200, 280 , 1125, 45 , 135 , 120.003, 297 }, + [79 ] = {1680, 720 , PROGRESSIVE, 3300, 1620, 750 , 30 , 18 , 24.0003, 59.4 }, + [80 ] = {1680, 720 , PROGRESSIVE, 3168, 1488, 750 , 30 , 18.75 , 25 , 59.4 }, + [81 ] = {1680, 720 , PROGRESSIVE, 2640, 960 , 750 , 30 , 22.5 , 30.0003, 59.4 }, + [82 ] = {1680, 720 , PROGRESSIVE, 2200, 520 , 750 , 30 , 37.5 , 50 , 82.5 }, + [83 ] = {1680, 720 , PROGRESSIVE, 2200, 520 , 750 , 30 , 45 , 60.0003, 99 }, + [84 ] = {1680, 720 , PROGRESSIVE, 2000, 320 , 825 , 105 , 82.5 , 100 , 165 }, + [85 ] = {1680, 720 , PROGRESSIVE, 2000, 320 , 825 , 105 , 99 , 120.003, 198 }, + [86 ] = {2560, 1080, PROGRESSIVE, 3750, 1190, 1100, 20 , 26.4 , 24.0003, 99 }, + [87 ] = {2560, 1080, PROGRESSIVE, 3200, 640 , 1125, 45 , 28.125 , 25 , 90 }, + [88 ] = {2560, 1080, PROGRESSIVE, 3520, 960 , 1125, 45 , 33.75 , 30.0003, 118.8 }, + [89 ] = {2560, 1080, PROGRESSIVE, 3300, 740 , 1125, 45 , 56.25 , 50 , 185.625 }, + [90 ] = {2560, 1080, PROGRESSIVE, 3000, 440 , 1100, 20 , 66 , 60.0003, 198 }, + [91 ] = {2560, 1080, PROGRESSIVE, 2970, 410 , 1250, 170 , 125 , 100 , 371.25 }, + [92 ] = {2560, 1080, PROGRESSIVE, 3300, 740 , 1250, 170 , 150 , 120.003, 495 }, + [93 ] = {3840, 2160, PROGRESSIVE, 5500, 1660, 2250, 90 , 54 , 24.0003, 297 }, + [94 ] = {3840, 2160, PROGRESSIVE, 5280, 1440, 2250, 90 , 56.25 , 25 , 297 }, + [95 ] = {3840, 2160, PROGRESSIVE, 4400, 560 , 2250, 90 , 67.5 , 30.0003, 297 }, + [96 ] = {3840, 2160, PROGRESSIVE, 5280, 1440, 2250, 90 , 112.5 , 50 , 594 }, + [97 ] = {3840, 2160, PROGRESSIVE, 4400, 560 , 2250, 90 , 135 , 60.0003, 594 }, + [98 ] = {4096, 2160, PROGRESSIVE, 5500, 1404, 2250, 90 , 54 , 24.0003, 297 }, + [99 ] = {4096, 2160, PROGRESSIVE, 5280, 1184, 2250, 90 , 56.25 , 25 , 297 }, + [100] = {4096, 2160, PROGRESSIVE, 4400, 304 , 2250, 90 , 67.5 , 30.0003, 297 }, + [101] = {4096, 2160, PROGRESSIVE, 5280, 1184, 2250, 90 , 112.5 , 50 , 594 }, + [102] = {4096, 2160, PROGRESSIVE, 4400, 304 , 2250, 90 , 135 , 60.0003, 594 }, + [103] = {3840, 2160, PROGRESSIVE, 5500, 1660, 2250, 90 , 54 , 24.0003, 297 }, + [104] = {3840, 2160, PROGRESSIVE, 5280, 1440, 2250, 90 , 56.25 , 25 , 297 }, + [105] = {3840, 2160, PROGRESSIVE, 4400, 560 , 2250, 90 , 67.5 , 30.0003, 297 }, + [106] = {3840, 2160, PROGRESSIVE, 5280, 1440, 2250, 90 , 112.5 , 50 , 594 }, + [107] = {3840, 2160, PROGRESSIVE, 4400, 560 , 2250, 90 , 135 , 60.0003, 594 }, +}; +#endif + +struct __attribute__ (( packed )) xvidc_cea861_hdmi_vendor_specific_data_block { + struct xvidc_cea861_data_block_header header; + + u8 ieee_registration_id[3]; /* LSB */ + + unsigned port_configuration_b : 4; + unsigned port_configuration_a : 4; + unsigned port_configuration_d : 4; + unsigned port_configuration_c : 4; + + /* extension fields */ + unsigned dvi_dual_link : 1; + unsigned : 2; + unsigned yuv_444_supported : 1; + unsigned colour_depth_30_bit : 1; + unsigned colour_depth_36_bit : 1; + unsigned colour_depth_48_bit : 1; + unsigned audio_info_frame : 1; + + u8 max_tmds_clock; /* = value * 5 */ + + unsigned : 6; + unsigned interlaced_latency_fields : 1; + unsigned latency_fields : 1; + + u8 video_latency; /* = (value - 1) * 2 */ + u8 audio_latency; /* = (value - 1) * 2 */ + u8 interlaced_video_latency; + u8 interlaced_audio_latency; + + u8 reserved[]; +}; + +struct __attribute__ (( packed )) xvidc_cea861_hdmi_hf_vendor_specific_data_block { + struct xvidc_cea861_data_block_header header; + + u8 ieee_registration_id[3]; /* LSB */ + + u8 version; + u8 max_tmds_char_rate; + + unsigned osd_disparity_3d : 1; + unsigned dual_view_3d : 1; + unsigned independent_view_3d : 1; + unsigned lte_340mcsc_scramble : 1; + + unsigned : 2; + + unsigned rr_capable : 1; + unsigned scdc_present : 1; + unsigned dc_30bit_yuv420 : 1; + unsigned dc_36bit_yuv420 : 1; + unsigned dc_48bit_yuv420 : 1; + + u8 reserved[]; +}; + +#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc_edid.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc_edid.c new file mode 100644 index 0000000..585f7b8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc_edid.c
@@ -0,0 +1,707 @@ +/******************************************************************************* + * + * Copyright (C) 2017 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xvidc_edid.c + * @addtogroup video_common_v4_2 + * @{ + * + * Contains function definitions related to the Extended Display Identification + * Data (EDID) structure which is present in all monitors. All content in this + * file is agnostic of communication interface protocol. + * + * @note None. + * + * <pre> + * MODIFICATION HISTORY: + * + * Ver Who Date Changes + * ----- ---- -------- ----------------------------------------------- + * 1.0 als 11/09/14 Initial release. + * 2.2 als 02/01/16 Functions with pointer arguments that don't modify + * contents now const. + * 4.0 aad 10/26/16 Added API for colormetry which returns fixed point + * in Q0.10 format instead of float. + * </pre> + * +*******************************************************************************/ + +/******************************* Include Files ********************************/ + +#include "xvidc_edid.h" + +/**************************** Function Prototypes *****************************/ + +static u32 XVidC_EdidIsVideoTimingSupportedPreferredTiming(const u8 *EdidRaw, + const XVidC_VideoTimingMode *VtMode); +static u32 XVidC_EdidIsVideoTimingSupportedEstablishedTimings(const u8 *EdidRaw, + const XVidC_VideoTimingMode *VtMode); +static u32 XVidC_EdidIsVideoTimingSupportedStandardTimings(const u8 *EdidRaw, + const XVidC_VideoTimingMode *VtMode); +static int XVidC_CalculatePower(u8 Base, u8 Power); +static int XVidC_CalculateBinaryFraction_QFormat(u16 Val, u8 DecPtIndex); + +/**************************** Function Definitions ****************************/ + +/******************************************************************************/ +/** + * Get the manufacturer name as specified in the vendor and product ID field of + * the supplied base Extended Display Identification Data (EDID). + * + * @param EdidRaw is the supplied base EDID to retrieve the manufacturer + * name from. + * @param ManName is the string that will be modified to hold the + * retrieved manufacturer name. + * + * @return None. + * + * @note The ManName argument is modified with the manufacturer name. + * +*******************************************************************************/ +void XVidC_EdidGetManName(const u8 *EdidRaw, char ManName[4]) +{ + ManName[0] = 0x40 + ((EdidRaw[XVIDC_EDID_VPI_ID_MAN_NAME0] & + XVIDC_EDID_VPI_ID_MAN_NAME0_CHAR0_MASK) >> + XVIDC_EDID_VPI_ID_MAN_NAME0_CHAR0_SHIFT); + ManName[1] = 0x40 + (((EdidRaw[XVIDC_EDID_VPI_ID_MAN_NAME0] & + XVIDC_EDID_VPI_ID_MAN_NAME0_CHAR1_MASK) << + XVIDC_EDID_VPI_ID_MAN_NAME0_CHAR1_POS) | + (EdidRaw[XVIDC_EDID_VPI_ID_MAN_NAME1] >> + XVIDC_EDID_VPI_ID_MAN_NAME1_CHAR1_SHIFT)); + ManName[2] = 0x40 + (EdidRaw[XVIDC_EDID_VPI_ID_MAN_NAME1] & + XVIDC_EDID_VPI_ID_MAN_NAME1_CHAR2_MASK); + ManName[3] = '\0'; +} + +/******************************************************************************/ +/** + * Get the color bit depth (bits per primary color) as specified in the basic + * display parameters and features, video input definition field of the supplied + * base Extended Display Identification Data (EDID). + * + * @param EdidRaw is the supplied base EDID to retrieve color depth + * information from. + * + * @return The number of bits per primary color as specified by the + * supplied base EDID. + * + * @note None. + * +*******************************************************************************/ +XVidC_ColorDepth XVidC_EdidGetColorDepth(const u8 *EdidRaw) +{ + XVidC_ColorDepth Bpc; + + switch (((EdidRaw[XVIDC_EDID_BDISP_VID] & + XVIDC_EDID_BDISP_VID_DIG_BPC_MASK) >> + XVIDC_EDID_BDISP_VID_DIG_BPC_SHIFT)) { + case XVIDC_EDID_BDISP_VID_DIG_BPC_6: + Bpc = XVIDC_BPC_6; + break; + + case XVIDC_EDID_BDISP_VID_DIG_BPC_8: + Bpc = XVIDC_BPC_8; + break; + + case XVIDC_EDID_BDISP_VID_DIG_BPC_10: + Bpc = XVIDC_BPC_10; + break; + + case XVIDC_EDID_BDISP_VID_DIG_BPC_12: + Bpc = XVIDC_BPC_12; + break; + + case XVIDC_EDID_BDISP_VID_DIG_BPC_14: + Bpc = XVIDC_BPC_14; + break; + + case XVIDC_EDID_BDISP_VID_DIG_BPC_16: + Bpc = XVIDC_BPC_16; + break; + + default: + Bpc = XVIDC_BPC_UNKNOWN; + break; + } + + return Bpc; +} + +/******************************************************************************/ +/** + * Calculates the x chromaticity coordinate for red by converting a 10 bit + * binary fraction representation from the supplied base Extended Display + * Identification Data (EDID) to a integer in Q0.10 Format. To convert back + * to float divide the fixed point value by 2^10. + * + * @param EdidRaw is the supplied base EDID to retrieve chromaticity + * information from. + * + * @return The x chromatacity coordinate for red. + * + * @note All values will be accurate to +/-0.0005. + * +*******************************************************************************/ +int XVidC_EdidGetCcRedX(const u8 *EdidRaw) +{ + return XVidC_CalculateBinaryFraction_QFormat( + (EdidRaw[XVIDC_EDID_CC_REDX_HIGH] << + XVIDC_EDID_CC_HIGH_SHIFT) | (EdidRaw[XVIDC_EDID_CC_RG_LOW] >> + XVIDC_EDID_CC_RBX_LOW_SHIFT), 10); +} + +/******************************************************************************/ +/** + * Calculates the y chromaticity coordinate for red by converting a 10 bit + * binary fraction representation from the supplied base Extended Display + * Identification Data (EDID) to a integer in Q0.10 Format. To convert back + * to float divide the fixed point value by 2^10. + * + * @param EdidRaw is the supplied base EDID to retrieve chromaticity + * information from. + * + * @return The y chromatacity coordinate for red. + * + * @note All values will be accurate to +/-0.0005. + * +*******************************************************************************/ +int XVidC_EdidGetCcRedY(const u8 *EdidRaw) +{ + return XVidC_CalculateBinaryFraction_QFormat( + (EdidRaw[XVIDC_EDID_CC_REDY_HIGH] << + XVIDC_EDID_CC_HIGH_SHIFT) | ((EdidRaw[XVIDC_EDID_CC_RG_LOW] & + XVIDC_EDID_CC_RBY_LOW_MASK) >> + XVIDC_EDID_CC_RBY_LOW_SHIFT), 10); +} + +/******************************************************************************/ +/** + * Calculates the x chromaticity coordinate for green by converting a 10 bit + * binary fraction representation from the supplied base Extended Display + * Identification Data (EDID) to a integer in Q0.10 Format. To convert back + * to float divide the fixed point value by 2^10. + * + * @param EdidRaw is the supplied base EDID to retrieve chromaticity + * information from. + * + * @return The x chromatacity coordinate for green. + * + * @note All values will be accurate to +/-0.0005. + * +*******************************************************************************/ +int XVidC_EdidGetCcGreenX(const u8 *EdidRaw) +{ + return XVidC_CalculateBinaryFraction_QFormat( + (EdidRaw[XVIDC_EDID_CC_GREENX_HIGH] << + XVIDC_EDID_CC_HIGH_SHIFT) | ((EdidRaw[XVIDC_EDID_CC_RG_LOW] & + XVIDC_EDID_CC_GWX_LOW_MASK) >> + XVIDC_EDID_CC_GWX_LOW_SHIFT), 10); +} + +/******************************************************************************/ +/** + * Calculates the y chromaticity coordinate for green by converting a 10 bit + * binary fraction representation from the supplied base Extended Display + * Identification Data (EDID) to a integer in Q0.10 Format. To convert back + * to float divide the fixed point value by 2^10. + * + * @param EdidRaw is the supplied base EDID to retrieve chromaticity + * information from. + * + * @return The y chromatacity coordinate for green. + * + * @note All values will be accurate to +/-0.0005. + * +*******************************************************************************/ +int XVidC_EdidGetCcGreenY(const u8 *EdidRaw) +{ + return XVidC_CalculateBinaryFraction_QFormat( + (EdidRaw[XVIDC_EDID_CC_GREENY_HIGH] << + XVIDC_EDID_CC_HIGH_SHIFT) | (EdidRaw[XVIDC_EDID_CC_RG_LOW] & + XVIDC_EDID_CC_GWY_LOW_MASK), 10); +} + +/******************************************************************************/ +/** + * Calculates the x chromaticity coordinate for blue by converting a 10 bit + * binary fraction representation from the supplied base Extended Display + * Identification Data (EDID) to a integer in Q0.10 Format. To convert back + * to float divide the fixed point value by 2^10. + * + * @param EdidRaw is the supplied base EDID to retrieve chromaticity + * information from. + * + * @return The x chromatacity coordinate for blue. + * + * @note All values will be accurate to +/-0.0005. + * +*******************************************************************************/ +int XVidC_EdidGetCcBlueX(const u8 *EdidRaw) +{ + return XVidC_CalculateBinaryFraction_QFormat( + (EdidRaw[XVIDC_EDID_CC_BLUEX_HIGH] << + XVIDC_EDID_CC_HIGH_SHIFT) | (EdidRaw[XVIDC_EDID_CC_BW_LOW] >> + XVIDC_EDID_CC_RBX_LOW_SHIFT), 10); +} + +/******************************************************************************/ +/** + * Calculates the y chromaticity coordinate for blue by converting a 10 bit + * binary fraction representation from the supplied base Extended Display + * Identification Data (EDID) to a integer in Q0.10 Format. To convert back + * to float divide the fixed point value by 2^10. + * + * @param EdidRaw is the supplied base EDID to retrieve chromaticity + * information from. + * + * @return The y chromatacity coordinate for blue. + * + * @note All values will be accurate to +/-0.0005. + * +*******************************************************************************/ +int XVidC_EdidGetCcBlueY(const u8 *EdidRaw) +{ + return XVidC_CalculateBinaryFraction_QFormat( + (EdidRaw[XVIDC_EDID_CC_BLUEY_HIGH] << + XVIDC_EDID_CC_HIGH_SHIFT) | ((EdidRaw[XVIDC_EDID_CC_BW_LOW] & + XVIDC_EDID_CC_RBY_LOW_MASK) >> + XVIDC_EDID_CC_RBY_LOW_SHIFT), 10); +} + +/******************************************************************************/ +/** + * Calculates the x chromaticity coordinate for white by converting a 10 bit + * binary fraction representation from the supplied base Extended Display + * Identification Data (EDID) to a integer in Q0.10 Format. To convert back + * to float divide the fixed point value by 2^10. + * + * @param EdidRaw is the supplied base EDID to retrieve chromaticity + * information from. + * + * @return The x chromatacity coordinate for white. + * + * @note All values will be accurate to +/-0.0005. + * +*******************************************************************************/ +int XVidC_EdidGetCcWhiteX(const u8 *EdidRaw) +{ + return XVidC_CalculateBinaryFraction_QFormat( + (EdidRaw[XVIDC_EDID_CC_WHITEX_HIGH] << + XVIDC_EDID_CC_HIGH_SHIFT) | ((EdidRaw[XVIDC_EDID_CC_BW_LOW] & + XVIDC_EDID_CC_GWX_LOW_MASK) >> XVIDC_EDID_CC_GWX_LOW_SHIFT), 10); +} + +/******************************************************************************/ +/** + * Calculates the y chromaticity coordinate for white by converting a 10 bit + * binary fraction representation from the supplied base Extended Display + * Identification Data (EDID) to an integer in Q0.10 Format. To convert back + * to float divide the fixed point value by 2^10. + * + * @param EdidRaw is the supplied base EDID to retrieve chromaticity + * information from. + * + * @return The y chromatacity coordinate for white. + * + * @note All values will be accurate to +/-0.0005. + * +*******************************************************************************/ +int XVidC_EdidGetCcWhiteY(const u8 *EdidRaw) +{ + return XVidC_CalculateBinaryFraction_QFormat( + (EdidRaw[XVIDC_EDID_CC_WHITEY_HIGH] << + XVIDC_EDID_CC_HIGH_SHIFT) | (EdidRaw[XVIDC_EDID_CC_BW_LOW] & + XVIDC_EDID_CC_GWY_LOW_MASK), 10); +} + +/******************************************************************************/ +/** + * Retrieves the active vertical resolution from the standard timings field of + * the supplied base Extended Display Identification Data (EDID). + * + * @param EdidRaw is the supplied base EDID to check the timing against. + * @param StdTimingsNum specifies which one of the standard timings to + * retrieve from the standard timings field. + * + * @return The vertical active resolution of the specified standard timing + * from the supplied base EDID. + * + * @note StdTimingsNum is an index 1-8. + * +*******************************************************************************/ +u16 XVidC_EdidGetStdTimingsV(const u8 *EdidRaw, u8 StdTimingsNum) +{ + u16 V; + + switch (XVidC_EdidGetStdTimingsAr(EdidRaw, StdTimingsNum)) { + case XVIDC_EDID_STD_TIMINGS_AR_16_10: + V = (10 * XVidC_EdidGetStdTimingsH(EdidRaw, + StdTimingsNum)) / 16; + break; + + case XVIDC_EDID_STD_TIMINGS_AR_4_3: + V = (3 * XVidC_EdidGetStdTimingsH(EdidRaw, + StdTimingsNum)) / 4; + break; + + case XVIDC_EDID_STD_TIMINGS_AR_5_4: + V = (4 * XVidC_EdidGetStdTimingsH(EdidRaw, + StdTimingsNum)) / 5; + break; + + case XVIDC_EDID_STD_TIMINGS_AR_16_9: + V = (9 * XVidC_EdidGetStdTimingsH(EdidRaw, + StdTimingsNum)) / 16; + break; + default: + V = 0; + break; + } + + return V; +} + +/******************************************************************************/ +/** + * Checks whether or not a specified video timing mode is supported as specified + * in the supplied base Extended Display Identification Data (EDID). The + * preferred timing, established timings (I, II, II), and the standard timings + * fields are checked for support. + * + * @param EdidRaw is the supplied base EDID to check the timing against. + * @param VtMode is the video timing mode to check for support. + * + * @return + * - XST_SUCCESS if the video timing mode is supported as specified + * in the supplied base EDID. + * - XST_FAILURE otherwise. + * + * @note None. + * +*******************************************************************************/ +u32 XVidC_EdidIsVideoTimingSupported(const u8 *EdidRaw, + const XVidC_VideoTimingMode *VtMode) +{ + u32 Status; + + /* Check if the video mode is the preferred timing. */ + Status = XVidC_EdidIsVideoTimingSupportedPreferredTiming(EdidRaw, + VtMode); + if (Status == XST_SUCCESS) { + return Status; + } + + /* Check established timings I, II, and III. */ + Status = XVidC_EdidIsVideoTimingSupportedEstablishedTimings(EdidRaw, + VtMode); + if (Status == XST_SUCCESS) { + return Status; + } + + /* Check in standard timings support. */ + Status = XVidC_EdidIsVideoTimingSupportedStandardTimings(EdidRaw, + VtMode); + + return Status; +} + +/******************************************************************************/ +/** + * Checks whether or not a specified video timing mode is the preferred timing + * of the supplied base Extended Display Identification Data (EDID). + * + * @param EdidRaw is the supplied base EDID to check the timing against. + * @param VtMode is the video timing mode to check for support. + * + * @return + * - XST_SUCCESS if the video timing mode is the preferred timing + * as specified in the base EDID. + * - XST_FAILURE otherwise. + * + * @note None. + * +*******************************************************************************/ +static u32 XVidC_EdidIsVideoTimingSupportedPreferredTiming(const u8 *EdidRaw, + const XVidC_VideoTimingMode *VtMode) +{ + const u8 *Ptm; + + Ptm = &EdidRaw[XVIDC_EDID_PTM]; + + u32 HActive = (((Ptm[XVIDC_EDID_DTD_PTM_HRES_HBLANK_U4] & + XVIDC_EDID_DTD_PTM_XRES_XBLANK_U4_XRES_MASK) >> + XVIDC_EDID_DTD_PTM_XRES_XBLANK_U4_XRES_SHIFT) << 8) | + Ptm[XVIDC_EDID_DTD_PTM_HRES_LSB]; + + u32 VActive = (((Ptm[XVIDC_EDID_DTD_PTM_VRES_VBLANK_U4] & + XVIDC_EDID_DTD_PTM_XRES_XBLANK_U4_XRES_MASK) >> + XVIDC_EDID_DTD_PTM_XRES_XBLANK_U4_XRES_SHIFT) << 8) | + Ptm[XVIDC_EDID_DTD_PTM_VRES_LSB]; + + if (VtMode->Timing.F1VTotal != XVidC_EdidIsDtdPtmInterlaced(EdidRaw)) { + return (XST_FAILURE); + } + else if ((VtMode->Timing.HActive == HActive) && + (VtMode->Timing.VActive == VActive)) { + return (XST_SUCCESS); + } + + return XST_FAILURE; +} + +/******************************************************************************/ +/** + * Checks whether or not a specified video timing mode is supported in the + * established timings field of the supplied base Extended Display + * Identification Data (EDID). + * + * @param EdidRaw is the supplied base EDID to check the timing against. + * @param VtMode is the video timing mode to check for support. + * + * @return + * - XST_SUCCESS if the video timing mode is supported in the + * base EDID's established timings field. + * - XST_FAILURE otherwise. + * + * @note None. + * +*******************************************************************************/ +static u32 XVidC_EdidIsVideoTimingSupportedEstablishedTimings(const u8 *EdidRaw, + const XVidC_VideoTimingMode *VtMode) +{ + u32 Status = XST_FAILURE; + + /* Check established timings I, II, and III. */ + if ((VtMode->Timing.HActive == 800) && + (VtMode->Timing.VActive == 640) && + (VtMode->FrameRate == XVIDC_FR_56HZ) && + XVidC_EdidSuppEstTimings800x600_56(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 640) && + (VtMode->Timing.VActive == 480) && + (VtMode->FrameRate == XVIDC_FR_60HZ) && + XVidC_EdidSuppEstTimings640x480_60(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 800) && + (VtMode->Timing.VActive == 600) && + (VtMode->FrameRate == XVIDC_FR_60HZ) && + XVidC_EdidSuppEstTimings800x600_60(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 1024) && + (VtMode->Timing.VActive == 768) && + (VtMode->FrameRate == XVIDC_FR_60HZ) && + XVidC_EdidSuppEstTimings1024x768_60(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 640) && + (VtMode->Timing.VActive == 480) && + (VtMode->FrameRate == XVIDC_FR_67HZ) && + XVidC_EdidSuppEstTimings640x480_67(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 720) && + (VtMode->Timing.VActive == 400) && + (VtMode->FrameRate == XVIDC_FR_70HZ) && + XVidC_EdidSuppEstTimings720x400_70(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 1024) && + (VtMode->Timing.VActive == 768) && + (VtMode->FrameRate == XVIDC_FR_70HZ) && + XVidC_EdidSuppEstTimings1024x768_70(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 640) && + (VtMode->Timing.VActive == 480) && + (VtMode->FrameRate == XVIDC_FR_72HZ) && + XVidC_EdidSuppEstTimings640x480_72(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 800) && + (VtMode->Timing.VActive == 600) && + (VtMode->FrameRate == XVIDC_FR_72HZ) && + XVidC_EdidSuppEstTimings800x600_72(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 640) && + (VtMode->Timing.VActive == 480) && + (VtMode->FrameRate == XVIDC_FR_75HZ) && + XVidC_EdidSuppEstTimings640x480_75(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 800) && + (VtMode->Timing.VActive == 600) && + (VtMode->FrameRate == XVIDC_FR_75HZ) && + XVidC_EdidSuppEstTimings800x600_75(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 832) && + (VtMode->Timing.VActive == 624) && + (VtMode->FrameRate == XVIDC_FR_75HZ) && + XVidC_EdidSuppEstTimings832x624_75(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 1024) && + (VtMode->Timing.VActive == 768) && + (VtMode->FrameRate == XVIDC_FR_75HZ) && + XVidC_EdidSuppEstTimings1024x768_75(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 1152) && + (VtMode->Timing.VActive == 870) && + (VtMode->FrameRate == XVIDC_FR_75HZ) && + XVidC_EdidSuppEstTimings1152x870_75(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 1280) && + (VtMode->Timing.VActive == 1024) && + (VtMode->FrameRate == XVIDC_FR_75HZ) && + XVidC_EdidSuppEstTimings1280x1024_75(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 1024) && + (VtMode->Timing.VActive == 768) && + (VtMode->FrameRate == XVIDC_FR_87HZ) && + XVidC_EdidSuppEstTimings1024x768_87(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 720) && + (VtMode->Timing.VActive == 400) && + (VtMode->FrameRate == XVIDC_FR_88HZ) && + XVidC_EdidSuppEstTimings720x400_88(EdidRaw)) { + Status = XST_SUCCESS; + } + + return Status; +} + +/******************************************************************************/ +/** + * Checks whether or not a specified video timing mode is supported in the + * standard timings field of the supplied base Extended Display Identification + * Data (EDID). + * + * @param EdidRaw is the supplied base EDID to check the timing against. + * @param VtMode is the video timing mode to check for support. + * + * @return + * - XST_SUCCESS if the video timing mode is supported in the + * base EDID's standard timings fields. + * - XST_FAILURE otherwise. + * + * @note None. + * +*******************************************************************************/ +static u32 XVidC_EdidIsVideoTimingSupportedStandardTimings(const u8 *EdidRaw, + const XVidC_VideoTimingMode *VtMode) +{ + u8 Index; + + for (Index = 0; Index < 8; Index++) { + if ((VtMode->Timing.HActive == + XVidC_EdidGetStdTimingsH(EdidRaw, Index + 1)) && + (VtMode->Timing.VActive == + XVidC_EdidGetStdTimingsV(EdidRaw, Index + 1)) && + (VtMode->FrameRate == (u8)XVidC_EdidGetStdTimingsFrr( + EdidRaw, Index + 1))) { + return XST_SUCCESS; + } + } + + return XST_FAILURE; +} + +/******************************************************************************/ +/** + * Perform a power operation. + * + * @param Base is b in the power operation, b^n. + * @param Power is n in the power operation, b^n. + * + * @return Base^Power (Base to the power of Power). + * + * @note None. + * +*******************************************************************************/ +static int XVidC_CalculatePower(u8 Base, u8 Power) +{ + u8 Index; + u32 Res = 1; + + for (Index = 0; Index < Power; Index++) { + Res *= Base; + } + + return Res; +} + + +/******************************************************************************/ +/** + * Convert a fractional binary number into a fixed point Q0.DecPtIndex number + * Binary digits to the right of the decimal point represent 2^-1 to + * 2^-(DecPtIndex+1). Binary digits to the left of the decimal point represent + * 2^0, 2^1, etc. For a given Q format, using an unsigned integer container with + * n fractional bits: + * its range is [0, 2^-n] + * its resolution is 2^n + * + * @param Val is the binary representation of the fraction. + * @param DecPtIndex is the index of the decimal point in the binary + * number. The decimal point is between the binary digits at Val's + * indices (DecPtIndex -1) and (DecPtIndex). DecPtIndex will + * determine the Q format resolution. + * + * @return Fixed point representation of the fractional part of the binary + * number in Q format. + * + * @note None. + * +*******************************************************************************/ +static int XVidC_CalculateBinaryFraction_QFormat(u16 Val, u8 DecPtIndex) +{ + int Index; + u32 Res; + + for (Index = DecPtIndex - 1, Res = 0; Index >= 0; Index--) { + if (((Val >> Index) & 0x1) == 1) { + Res += XVidC_CalculatePower(2 , Index); + } + } + + return Res; +} +/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc_edid.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc_edid.h new file mode 100644 index 0000000..347b4f3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc_edid.h
@@ -0,0 +1,484 @@ +/******************************************************************************* + * + * Copyright (C) 2017 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xvidc_edid.h + * @addtogroup video_common_v4_2 + * @{ + * + * Contains macros, definitions, and function declarations related to the + * Extended Display Identification Data (EDID) structure which is present in all + * monitors. All content in this file is agnostic of communication interface + * protocol. + * + * @note None. + * + * <pre> + * MODIFICATION HISTORY: + * + * Ver Who Date Changes + * ----- ---- -------- ----------------------------------------------- + * 1.0 als 11/09/14 Initial release. + * 2.2 als 02/01/16 Functions with pointer arguments that don't modify + * contents now const. + * 4.0 aad 10/26/16 Functions which return fixed point values instead of + * float + * </pre> + * +*******************************************************************************/ + +#ifndef XVIDC_EDID_H_ +/* Prevent circular inclusions by using protection macros. */ +#define XVIDC_EDID_H_ + +#ifdef __cplusplus +extern "C" { +#endif +/******************************* Include Files ********************************/ + +#include "xstatus.h" +#include "xvidc.h" + +/************************** Constant Definitions ******************************/ + +/** @name Address mapping for the base EDID block. + * @{ + */ +#define XVIDC_EDID_HEADER 0x00 +/* Vendor and product identification. */ +#define XVIDC_EDID_VPI_ID_MAN_NAME0 0x08 +#define XVIDC_EDID_VPI_ID_MAN_NAME1 0x09 +#define XVIDC_EDID_VPI_ID_PROD_CODE_LSB 0x0A +#define XVIDC_EDID_VPI_ID_PROD_CODE_MSB 0x0B +#define XVIDC_EDID_VPI_ID_SN0 0x0C +#define XVIDC_EDID_VPI_ID_SN1 0x0D +#define XVIDC_EDID_VPI_ID_SN2 0x0E +#define XVIDC_EDID_VPI_ID_SN3 0x0F +#define XVIDC_EDID_VPI_WEEK_MAN 0x10 +#define XVIDC_EDID_VPI_YEAR 0x11 +/* EDID structure version and revision. */ +#define XVIDC_EDID_STRUCT_VER 0x12 +#define XVIDC_EDID_STRUCT_REV 0x13 +/* Basic display parameters and features. */ +#define XVIDC_EDID_BDISP_VID 0x14 +#define XVIDC_EDID_BDISP_H_SSAR 0x15 +#define XVIDC_EDID_BDISP_V_SSAR 0x16 +#define XVIDC_EDID_BDISP_GAMMA 0x17 +#define XVIDC_EDID_BDISP_FEATURE 0x18 +/* Color characteristics (display x,y chromaticity coordinates). */ +#define XVIDC_EDID_CC_RG_LOW 0x19 +#define XVIDC_EDID_CC_BW_LOW 0x1A +#define XVIDC_EDID_CC_REDX_HIGH 0x1B +#define XVIDC_EDID_CC_REDY_HIGH 0x1C +#define XVIDC_EDID_CC_GREENX_HIGH 0x1D +#define XVIDC_EDID_CC_GREENY_HIGH 0x1E +#define XVIDC_EDID_CC_BLUEX_HIGH 0x1F +#define XVIDC_EDID_CC_BLUEY_HIGH 0x20 +#define XVIDC_EDID_CC_WHITEX_HIGH 0x21 +#define XVIDC_EDID_CC_WHITEY_HIGH 0x22 +/* Established timings. */ +#define XVIDC_EDID_EST_TIMINGS_I 0x23 +#define XVIDC_EDID_EST_TIMINGS_II 0x24 +#define XVIDC_EDID_EST_TIMINGS_MAN 0x25 +/* Standard timings. */ +#define XVIDC_EDID_STD_TIMINGS_H(N) (0x26 + 2 * (N - 1)) +#define XVIDC_EDID_STD_TIMINGS_AR_FRR(N) (0x27 + 2 * (N - 1)) +/* 18 byte descriptors. */ +#define XVIDC_EDID_18BYTE_DESCRIPTOR(N) (0x36 + 18 * (N - 1)) +#define XVIDC_EDID_PTM (XVIDC_EDID_18BYTE_DESCRIPTOR(1)) +/* - Detailed timing descriptor (DTD) / Preferred timing mode (PTM). */ +#define XVIDC_EDID_DTD_PTM_PIXEL_CLK_KHZ_LSB 0x00 +#define XVIDC_EDID_DTD_PTM_PIXEL_CLK_KHZ_MSB 0x01 +#define XVIDC_EDID_DTD_PTM_HRES_LSB 0x02 +#define XVIDC_EDID_DTD_PTM_HBLANK_LSB 0x03 +#define XVIDC_EDID_DTD_PTM_HRES_HBLANK_U4 0x04 +#define XVIDC_EDID_DTD_PTM_VRES_LSB 0x05 +#define XVIDC_EDID_DTD_PTM_VBLANK_LSB 0x06 +#define XVIDC_EDID_DTD_PTM_VRES_VBLANK_U4 0x07 +#define XVIDC_EDID_DTD_PTM_HFPORCH_LSB 0x08 +#define XVIDC_EDID_DTD_PTM_HSPW_LSB 0x09 +#define XVIDC_EDID_DTD_PTM_VFPORCH_VSPW_L4 0x0A +#define XVIDC_EDID_DTD_PTM_XFPORCH_XSPW_U2 0x0B +#define XVIDC_EDID_DTD_PTM_HIMGSIZE_MM_LSB 0x0C +#define XVIDC_EDID_DTD_PTM_VIMGSIZE_MM_LSB 0x0D +#define XVIDC_EDID_DTD_PTM_XIMGSIZE_MM_U4 0x0E +#define XVIDC_EDID_DTD_PTM_HBORDER 0x0F +#define XVIDC_EDID_DTD_PTM_VBORDER 0x10 +#define XVIDC_EDID_DTD_PTM_SIGNAL 0x11 + +/* Extension block count. */ +#define XVIDC_EDID_EXT_BLK_COUNT 0x7E +/* Checksum. */ +#define XVIDC_EDID_CHECKSUM 0x7F +/* @} */ + +/******************************************************************************/ + +/** @name Extended Display Identification Data: Masks, shifts, and values. + * @{ + */ +#define XVIDC_EDID_VPI_ID_MAN_NAME0_CHAR0_SHIFT 2 +#define XVIDC_EDID_VPI_ID_MAN_NAME0_CHAR0_MASK (0x1F << 2) +#define XVIDC_EDID_VPI_ID_MAN_NAME0_CHAR1_MASK 0x03 +#define XVIDC_EDID_VPI_ID_MAN_NAME0_CHAR1_POS 3 +#define XVIDC_EDID_VPI_ID_MAN_NAME1_CHAR1_SHIFT 5 +#define XVIDC_EDID_VPI_ID_MAN_NAME1_CHAR2_MASK 0x1F + +/* Basic display parameters and features: Video input definition. */ +#define XVIDC_EDID_BDISP_VID_VSI_SHIFT 7 +#define XVIDC_EDID_BDISP_VID_VSI_MASK (0x01 << 7) +#define XVIDC_EDID_BDISP_VID_ANA_SLS_SHIFT 5 +#define XVIDC_EDID_BDISP_VID_ANA_SLS_MASK (0x03 << 5) +#define XVIDC_EDID_BDISP_VID_ANA_SLS_0700_0300_1000 0x0 +#define XVIDC_EDID_BDISP_VID_ANA_SLS_0714_0286_1000 0x1 +#define XVIDC_EDID_BDISP_VID_ANA_SLS_1000_0400_1400 0x2 +#define XVIDC_EDID_BDISP_VID_ANA_SLS_0700_0000_0700 0x3 +#define XVIDC_EDID_BDISP_VID_ANA_VID_SETUP_MASK (0x01 << 4) +#define XVIDC_EDID_BDISP_VID_ANA_SEP_SYNC_HV_MASK (0x01 << 3) +#define XVIDC_EDID_BDISP_VID_ANA_COMP_SYNC_H_MASK (0x01 << 2) +#define XVIDC_EDID_BDISP_VID_ANA_COMP_SYNC_G_MASK (0x01 << 1) +#define XVIDC_EDID_BDISP_VID_ANA_SERR_V_SYNC_MASK (0x01) +#define XVIDC_EDID_BDISP_VID_DIG_BPC_SHIFT 4 +#define XVIDC_EDID_BDISP_VID_DIG_BPC_MASK (0x7 << 4) +#define XVIDC_EDID_BDISP_VID_DIG_BPC_UNDEF 0x0 +#define XVIDC_EDID_BDISP_VID_DIG_BPC_6 0x1 +#define XVIDC_EDID_BDISP_VID_DIG_BPC_8 0x2 +#define XVIDC_EDID_BDISP_VID_DIG_BPC_10 0x3 +#define XVIDC_EDID_BDISP_VID_DIG_BPC_12 0x4 +#define XVIDC_EDID_BDISP_VID_DIG_BPC_14 0x5 +#define XVIDC_EDID_BDISP_VID_DIG_BPC_16 0x6 +#define XVIDC_EDID_BDISP_VID_DIG_VIS_MASK 0xF +#define XVIDC_EDID_BDISP_VID_DIG_VIS_UNDEF 0x0 +#define XVIDC_EDID_BDISP_VID_DIG_VIS_DVI 0x1 +#define XVIDC_EDID_BDISP_VID_DIG_VIS_HDMIA 0x2 +#define XVIDC_EDID_BDISP_VID_DIG_VIS_HDMIB 0x3 +#define XVIDC_EDID_BDISP_VID_DIG_VIS_MDDI 0x4 +#define XVIDC_EDID_BDISP_VID_DIG_VIS_DP 0x5 + +/* Basic display parameters and features: Feature support. */ +#define XVIDC_EDID_BDISP_FEATURE_PM_STANDBY_MASK (0x1 << 7) +#define XVIDC_EDID_BDISP_FEATURE_PM_SUSPEND_MASK (0x1 << 6) +#define XVIDC_EDID_BDISP_FEATURE_PM_OFF_VLP_MASK (0x1 << 5) +#define XVIDC_EDID_BDISP_FEATURE_ANA_COLORTYPE_SHIFT 3 +#define XVIDC_EDID_BDISP_FEATURE_ANA_COLORTYPE_MASK (0x3 << 3) +#define XVIDC_EDID_BDISP_FEATURE_ANA_COLORTYPE_MCG 0x0 +#define XVIDC_EDID_BDISP_FEATURE_ANA_COLORTYPE_RGB 0x1 +#define XVIDC_EDID_BDISP_FEATURE_ANA_COLORTYPE_NRGB 0x2 +#define XVIDC_EDID_BDISP_FEATURE_ANA_COLORTYPE_UNDEF 0x3 +#define XVIDC_EDID_BDISP_FEATURE_DIG_COLORENC_YCRCB444_MASK (0x1 << 3) +#define XVIDC_EDID_BDISP_FEATURE_DIG_COLORENC_YCRCB422_MASK (0x1 << 4) +#define XVIDC_EDID_BDISP_FEATURE_SRGB_DEF_MASK (0x1 << 2) +#define XVIDC_EDID_BDISP_FEATURE_PTM_INC_MASK (0x1 << 1) +#define XVIDC_EDID_BDISP_FEATURE_CONTFREQ_MASK (0x1) + +/* Color characteristics (display x,y chromaticity coordinates). */ +#define XVIDC_EDID_CC_HIGH_SHIFT 2 +#define XVIDC_EDID_CC_RBX_LOW_SHIFT 6 +#define XVIDC_EDID_CC_RBY_LOW_SHIFT 4 +#define XVIDC_EDID_CC_RBY_LOW_MASK (0x3 << 4) +#define XVIDC_EDID_CC_GWX_LOW_SHIFT 2 +#define XVIDC_EDID_CC_GWX_LOW_MASK (0x3 << 2) +#define XVIDC_EDID_CC_GWY_LOW_MASK (0x3) +#define XVIDC_EDID_CC_GREENY_HIGH 0x1E +#define XVIDC_EDID_CC_BLUEX_HIGH 0x1F +#define XVIDC_EDID_CC_BLUEY_HIGH 0x20 +#define XVIDC_EDID_CC_WHITEX_HIGH 0x21 +#define XVIDC_EDID_CC_WHITEY_HIGH 0x22 + +/* Established timings. */ +#define XVIDC_EDID_EST_TIMINGS_I_720x400_70_MASK (0x1 << 7) +#define XVIDC_EDID_EST_TIMINGS_I_720x400_88_MASK (0x1 << 6) +#define XVIDC_EDID_EST_TIMINGS_I_640x480_60_MASK (0x1 << 5) +#define XVIDC_EDID_EST_TIMINGS_I_640x480_67_MASK (0x1 << 4) +#define XVIDC_EDID_EST_TIMINGS_I_640x480_72_MASK (0x1 << 3) +#define XVIDC_EDID_EST_TIMINGS_I_640x480_75_MASK (0x1 << 2) +#define XVIDC_EDID_EST_TIMINGS_I_800x600_56_MASK (0x1 << 1) +#define XVIDC_EDID_EST_TIMINGS_I_800x600_60_MASK (0x1) +#define XVIDC_EDID_EST_TIMINGS_II_800x600_72_MASK (0x1 << 7) +#define XVIDC_EDID_EST_TIMINGS_II_800x600_75_MASK (0x1 << 6) +#define XVIDC_EDID_EST_TIMINGS_II_832x624_75_MASK (0x1 << 5) +#define XVIDC_EDID_EST_TIMINGS_II_1024x768_87_MASK (0x1 << 4) +#define XVIDC_EDID_EST_TIMINGS_II_1024x768_60_MASK (0x1 << 3) +#define XVIDC_EDID_EST_TIMINGS_II_1024x768_70_MASK (0x1 << 2) +#define XVIDC_EDID_EST_TIMINGS_II_1024x768_75_MASK (0x1 << 1) +#define XVIDC_EDID_EST_TIMINGS_II_1280x1024_75_MASK (0x1) +#define XVIDC_EDID_EST_TIMINGS_MAN_1152x870_75_MASK (0x1 << 7) +#define XVIDC_EDID_EST_TIMINGS_MAN_MASK (0x7F) + +/* Standard timings. */ +#define XVIDC_EDID_STD_TIMINGS_AR_SHIFT 6 +#define XVIDC_EDID_STD_TIMINGS_AR_16_10 0x0 +#define XVIDC_EDID_STD_TIMINGS_AR_4_3 0x1 +#define XVIDC_EDID_STD_TIMINGS_AR_5_4 0x2 +#define XVIDC_EDID_STD_TIMINGS_AR_16_9 0x3 +#define XVIDC_EDID_STD_TIMINGS_FRR_MASK (0x3F) + +/* Detailed timing descriptor (DTD) / Preferred timing mode (PTM). */ +#define XVIDC_EDID_DTD_PTM_XRES_XBLANK_U4_XBLANK_MASK 0x0F +#define XVIDC_EDID_DTD_PTM_XRES_XBLANK_U4_XRES_MASK 0xF0 +#define XVIDC_EDID_DTD_PTM_XRES_XBLANK_U4_XRES_SHIFT 4 +#define XVIDC_EDID_DTD_PTM_VFPORCH_VSPW_L4_VSPW_MASK 0x0F +#define XVIDC_EDID_DTD_PTM_VFPORCH_VSPW_L4_VFPORCH_MASK 0xF0 +#define XVIDC_EDID_DTD_PTM_VFPORCH_VSPW_L4_VFPORCH_SHIFT 4 +#define XVIDC_EDID_DTD_PTM_XFPORCH_XSPW_U2_HFPORCH_MASK 0xC0 +#define XVIDC_EDID_DTD_PTM_XFPORCH_XSPW_U2_HSPW_MASK 0x30 +#define XVIDC_EDID_DTD_PTM_XFPORCH_XSPW_U2_VFPORCH_MASK 0x0C +#define XVIDC_EDID_DTD_PTM_XFPORCH_XSPW_U2_VSPW_MASK 0x03 +#define XVIDC_EDID_DTD_PTM_XFPORCH_XSPW_U2_HFPORCH_SHIFT 6 +#define XVIDC_EDID_DTD_PTM_XFPORCH_XSPW_U2_HSPW_SHIFT 4 +#define XVIDC_EDID_DTD_PTM_XFPORCH_XSPW_U2_VFPORCH_SHIFT 2 +#define XVIDC_EDID_DTD_PTM_XIMGSIZE_MM_U4_VIMGSIZE_MM_MASK 0x0F +#define XVIDC_EDID_DTD_PTM_XIMGSIZE_MM_U4_HIMGSIZE_MM_MASK 0xF0 +#define XVIDC_EDID_DTD_PTM_XIMGSIZE_MM_U4_HIMGSIZE_MM_SHIFT 4 +#define XVIDC_EDID_DTD_PTM_SIGNAL_INTERLACED_MASK 0x80 +#define XVIDC_EDID_DTD_PTM_SIGNAL_INTERLACED_SHIFT 7 +#define XVIDC_EDID_DTD_PTM_SIGNAL_HPOLARITY_MASK 0x02 +#define XVIDC_EDID_DTD_PTM_SIGNAL_VPOLARITY_MASK 0x04 +#define XVIDC_EDID_DTD_PTM_SIGNAL_HPOLARITY_SHIFT 1 +#define XVIDC_EDID_DTD_PTM_SIGNAL_VPOLARITY_SHIFT 2 +/* @} */ + +/******************* Macros (Inline Functions) Definitions ********************/ + +#define XVidC_EdidIsHeaderValid(E) \ + !memcmp(E, "\x00\xFF\xFF\xFF\xFF\xFF\xFF\x00", 8) + +/* Vendor and product identification: ID manufacturer name. */ +/* void XVidC_EdidGetManName(const u8 *EdidRaw, char ManName[4]); */ + +/* Vendor and product identification: ID product code. */ +#define XVidC_EdidGetIdProdCode(E) \ + ((u16)((E[XVIDC_EDID_VPI_ID_PROD_CODE_MSB] << 8) | \ + E[XVIDC_EDID_VPI_ID_PROD_CODE_LSB])) + +/* Vendor and product identification: ID serial number. */ +#define XVidC_EdidGetIdSn(E) \ + ((u32)((E[XVIDC_EDID_VPI_ID_SN3] << 24) | \ + (E[XVIDC_EDID_VPI_ID_SN2] << 16) | (E[XVIDC_EDID_VPI_ID_SN1] << 8) | \ + E[XVIDC_EDID_VPI_ID_SN0])) + +/* Vendor and product identification: Week and year of manufacture or model + * year. */ +#define XVidC_EdidGetManWeek(E) (E[XVIDC_EDID_VPI_WEEK_MAN]) +#define XVidC_EdidGetModManYear(E) (E[XVIDC_EDID_VPI_YEAR] + 1990) +#define XVidC_EdidIsYearModel(E) (XVidC_EdidGetManWeek(E) == 0xFF) +#define XVidC_EdidIsYearMan(E) (XVidC_EdidGetManWeek(E) != 0xFF) + +/* EDID structure version and revision. */ +#define XVidC_EdidGetStructVer(E) (E[XVIDC_EDID_STRUCT_VER]) +#define XVidC_EdidGetStructRev(E) (E[XVIDC_EDID_STRUCT_REV]) + +/* Basic display parameters and features: Video input definition. */ +#define XVidC_EdidIsDigitalSig(E) \ + ((E[XVIDC_EDID_BDISP_VID] & XVIDC_EDID_BDISP_VID_VSI_MASK) != 0) +#define XVidC_EdidIsAnalogSig(E) \ + ((E[XVIDC_EDID_BDISP_VID] & XVIDC_EDID_BDISP_VID_VSI_MASK) == 0) +#define XVidC_EdidGetAnalogSigLvlStd(E) \ + ((E[XVIDC_EDID_BDISP_VID] & XVIDC_EDID_BDISP_VID_ANA_SLS_MASK) >> \ + XVIDC_EDID_BDISP_VID_ANA_SLS_SHIFT) +#define XVidC_EdidGetAnalogSigVidSetup(E) \ + ((E[XVIDC_EDID_BDISP_VID] & \ + XVIDC_EDID_BDISP_VID_ANA_VID_SETUP_MASK) != 0) +#define XVidC_EdidSuppAnalogSigSepSyncHv(E) \ + ((E[XVIDC_EDID_BDISP_VID] & \ + XVIDC_EDID_BDISP_VID_ANA_SEP_SYNC_HV_MASK) != 0) +#define XVidC_EdidSuppAnalogSigCompSyncH(E) \ + ((E[XVIDC_EDID_BDISP_VID] & \ + XVIDC_EDID_BDISP_VID_ANA_COMP_SYNC_H_MASK) != 0) +#define XVidC_EdidSuppAnalogSigCompSyncG(E) \ + ((E[XVIDC_EDID_BDISP_VID] & \ + XVIDC_EDID_BDISP_VID_ANA_COMP_SYNC_G_MASK) != 0) +#define XVidC_EdidSuppAnalogSigSerrVsync(E) \ + ((E[XVIDC_EDID_BDISP_VID] & \ + XVIDC_EDID_BDISP_VID_ANA_SERR_V_SYNC_MASK) != 0) +/* XVidC_ColorDepth XVidC_EdidGetColorDepth(const u8 *EdidRaw); */ +#define XVidC_EdidGetDigitalSigIfaceStd(E) \ + (E[XVIDC_EDID_BDISP_VID] & XVIDC_EDID_BDISP_VID_DIG_VIS_MASK) + +/* Basic display parameters and features: Horizontal and vertical screen size or + * aspect ratio. */ +#define XVidC_EdidIsSsArDefined(E) \ + ((E[XVIDC_EDID_BDISP_H_SSAR] | E[XVIDC_EDID_BDISP_V_SSAR]) != 0) +#define XVidC_EdidGetSsArH(E) E[XVIDC_EDID_BDISP_H_SSAR] +#define XVidC_EdidGetSsArV(E) E[XVIDC_EDID_BDISP_V_SSAR] +#define XVidC_EdidIsSsArSs(E) \ + ((XVidC_EdidGetSsArH(E) != 0) && (XVidC_EdidGetSsArV(E) != 0)) +#define XVidC_EdidIsSsArArL(E) \ + ((XVidC_EdidGetSsArH(E) != 0) && (XVidC_EdidGetSsArV(E) == 0)) +#define XVidC_EdidIsSsArArP(E) \ + ((XVidC_EdidGetSsArH(E) == 0) && (XVidC_EdidGetSsArV(E) != 0)) +#define XVidC_EdidGetSsArArL(E) \ + ((float)((XVidC_EdidGetSsArH(E) + 99.0) / 100.0)) +#define XVidC_EdidGetSsArArP(E) \ + ((float)(100.0 / (XVidC_EdidGetSsArV(E) + 99.0))) + +/* Basic display parameters and features: Gamma. */ +#define XVidC_EdidIsGammaInExt(E) (E[XVIDC_EDID_BDISP_GAMMA] == 0xFF) +#define XVidC_EdidGetGamma(E) \ + ((float)((E[XVIDC_EDID_BDISP_GAMMA] + 100.0) / 100.0)) + +/* Basic display parameters and features: Feature support. */ +#define XVidC_EdidSuppFeaturePmStandby(E) \ + ((E[XVIDC_EDID_BDISP_FEATURE] & \ + XVIDC_EDID_BDISP_FEATURE_PM_STANDBY_MASK) != 0) +#define XVidC_EdidSuppFeaturePmSuspend(E) \ + ((E[XVIDC_EDID_BDISP_FEATURE] & \ + XVIDC_EDID_BDISP_FEATURE_PM_SUSPEND_MASK) != 0) +#define XVidC_EdidSuppFeaturePmOffVlp(E) \ + ((E[XVIDC_EDID_BDISP_FEATURE] & \ + XVIDC_EDID_BDISP_FEATURE_PM_OFF_VLP_MASK) != 0) +#define XVidC_EdidGetFeatureAnaColorType(E) \ + ((E[XVIDC_EDID_BDISP_FEATURE] & \ + XVIDC_EDID_BDISP_FEATURE_ANA_COLORTYPE_MASK) >> \ + XVIDC_EDID_BDISP_FEATURE_ANA_COLORTYPE_SHIFT) +#define XVidC_EdidSuppFeatureDigColorEncYCrCb444(E) \ + ((E[XVIDC_EDID_BDISP_FEATURE] & \ + XVIDC_EDID_BDISP_FEATURE_DIG_COLORENC_YCRCB444_MASK) != 0) +#define XVidC_EdidSuppFeatureDigColorEncYCrCb422(E) \ + ((E[XVIDC_EDID_BDISP_FEATURE] & \ + XVIDC_EDID_BDISP_FEATURE_DIG_COLORENC_YCRCB422_MASK) != 0) +#define XVidC_EdidIsFeatureSrgbDef(E) \ + ((E[XVIDC_EDID_BDISP_FEATURE] & \ + XVIDC_EDID_BDISP_FEATURE_SRGB_DEF_MASK) != 0) +#define XVidC_EdidIsFeaturePtmInc(E) \ + ((E[XVIDC_EDID_BDISP_FEATURE] & \ + XVIDC_EDID_BDISP_FEATURE_PTM_INC_MASK) != 0) +#define XVidC_EdidIsFeatureContFreq(E) \ + ((E[XVIDC_EDID_BDISP_FEATURE] & \ + XVIDC_EDID_BDISP_FEATURE_CONTFREQ_MASK) != 0) + +/* Established timings. */ +#define XVidC_EdidSuppEstTimings720x400_70(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_I] & \ + XVIDC_EDID_EST_TIMINGS_I_720x400_70_MASK) != 0) +#define XVidC_EdidSuppEstTimings720x400_88(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_I] & \ + XVIDC_EDID_EST_TIMINGS_I_720x400_88_MASK) != 0) +#define XVidC_EdidSuppEstTimings640x480_60(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_I] & \ + XVIDC_EDID_EST_TIMINGS_I_640x480_60_MASK) != 0) +#define XVidC_EdidSuppEstTimings640x480_67(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_I] & \ + XVIDC_EDID_EST_TIMINGS_I_640x480_67_MASK) != 0) +#define XVidC_EdidSuppEstTimings640x480_72(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_I] & \ + XVIDC_EDID_EST_TIMINGS_I_640x480_72_MASK) != 0) +#define XVidC_EdidSuppEstTimings640x480_75(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_I] & \ + XVIDC_EDID_EST_TIMINGS_I_640x480_75_MASK) != 0) +#define XVidC_EdidSuppEstTimings800x600_56(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_I] & \ + XVIDC_EDID_EST_TIMINGS_I_800x600_56_MASK) != 0) +#define XVidC_EdidSuppEstTimings800x600_60(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_I] & \ + XVIDC_EDID_EST_TIMINGS_I_800x600_60_MASK) != 0) +#define XVidC_EdidSuppEstTimings800x600_72(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_II] & \ + XVIDC_EDID_EST_TIMINGS_II_800x600_72_MASK) != 0) +#define XVidC_EdidSuppEstTimings800x600_75(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_II] & \ + XVIDC_EDID_EST_TIMINGS_II_800x600_75_MASK) != 0) +#define XVidC_EdidSuppEstTimings832x624_75(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_II] & \ + XVIDC_EDID_EST_TIMINGS_II_832x624_75_MASK) != 0) +#define XVidC_EdidSuppEstTimings1024x768_87(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_II] & \ + XVIDC_EDID_EST_TIMINGS_II_1024x768_87_MASK) != 0) +#define XVidC_EdidSuppEstTimings1024x768_60(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_II] & \ + XVIDC_EDID_EST_TIMINGS_II_1024x768_60_MASK) != 0) +#define XVidC_EdidSuppEstTimings1024x768_70(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_II] & \ + XVIDC_EDID_EST_TIMINGS_II_1024x768_70_MASK) != 0) +#define XVidC_EdidSuppEstTimings1024x768_75(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_II] & \ + XVIDC_EDID_EST_TIMINGS_II_1024x768_75_MASK) != 0) +#define XVidC_EdidSuppEstTimings1280x1024_75(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_II] & \ + XVIDC_EDID_EST_TIMINGS_II_1280x1024_75_MASK) != 0) +#define XVidC_EdidSuppEstTimings1152x870_75(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_MAN] & \ + XVIDC_EDID_EST_TIMINGS_MAN_1152x870_75_MASK) != 0) +#define XVidC_EdidGetTimingsMan(E) \ + (E[XVIDC_EDID_EST_TIMINGS_MAN] & XVIDC_EDID_EST_TIMINGS_MAN_MASK) + +/* Standard timings. */ +#define XVidC_EdidGetStdTimingsH(E, N) \ + ((E[XVIDC_EDID_STD_TIMINGS_H(N)] + 31) * 8) +#define XVidC_EdidGetStdTimingsAr(E, N) \ + (E[XVIDC_EDID_STD_TIMINGS_AR_FRR(N)] >> XVIDC_EDID_STD_TIMINGS_AR_SHIFT) +#define XVidC_EdidGetStdTimingsFrr(E, N) \ + ((E[XVIDC_EDID_STD_TIMINGS_AR_FRR(N)] & \ + XVIDC_EDID_STD_TIMINGS_FRR_MASK) + 60) +/* u16 XVidC_EdidGetStdTimingsV(const u8 *EdidRaw, u8 StdTimingsNum); */ +#define XVidC_EdidIsDtdPtmInterlaced(E) \ + ((E[XVIDC_EDID_PTM + XVIDC_EDID_DTD_PTM_SIGNAL] & \ + XVIDC_EDID_DTD_PTM_SIGNAL_INTERLACED_MASK) >> \ + XVIDC_EDID_DTD_PTM_SIGNAL_INTERLACED_SHIFT) + +/* Extension block count. */ +#define XVidC_EdidGetExtBlkCount(E) (E[XVIDC_EDID_EXT_BLK_COUNT]) + +/* Checksum. */ +#define XVidC_EdidGetChecksum(E) (E[XVIDC_EDID_CHECKSUM]) + +/**************************** Function Prototypes *****************************/ + +/* Vendor and product identification: ID manufacturer name. */ +void XVidC_EdidGetManName(const u8 *EdidRaw, char ManName[4]); + +/* Basic display parameters and features: Video input definition. */ +XVidC_ColorDepth XVidC_EdidGetColorDepth(const u8 *EdidRaw); + +/* Color characteristics (display x,y chromaticity coordinates). */ +int XVidC_EdidGetCcRedX(const u8 *EdidRaw); +int XVidC_EdidGetCcRedY(const u8 *EdidRaw); +int XVidC_EdidGetCcGreenX(const u8 *EdidRaw); +int XVidC_EdidGetCcGreenY(const u8 *EdidRaw); +int XVidC_EdidGetCcBlueX(const u8 *EdidRaw); +int XVidC_EdidGetCcBlueY(const u8 *EdidRaw); +int XVidC_EdidGetCcWhiteX(const u8 *EdidRaw); +int XVidC_EdidGetCcWhiteY(const u8 *EdidRaw); + +/* Standard timings. */ +u16 XVidC_EdidGetStdTimingsV(const u8 *EdidRaw, u8 StdTimingsNum); + +/* Utility functions. */ +u32 XVidC_EdidIsVideoTimingSupported(const u8 *EdidRaw, + const XVidC_VideoTimingMode *VtMode); + +#ifdef __cplusplus +} +#endif +#endif /* XVIDC_EDID_H_ */ +/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc_edid_ext.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc_edid_ext.c new file mode 100644 index 0000000..c8ce9f1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc_edid_ext.c
@@ -0,0 +1,174 @@ +/****************************************************************************** +* +* Copyright (C) 2017 - 2018 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xhdmi_edid.h +* +* <b>Software Initalization & Configuration</b> +* +* <b>Interrupts </b> +* +* <b> Virtual Memory </b> +* +* This driver supports Virtual Memory. The RTOS is responsible for calculating +* the correct device base address in Virtual Memory space. +* +* <b> Threads </b> +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* <b> Asserts </b> +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* <b> Building the driver </b> +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- ---------- -------------------------------------------------- +* 1.0 mmo 24-01-2017 EDID Parser capability +* </pre> +* +******************************************************************************/ +#include "stdio.h" +#include "string.h" +#include "stdlib.h" +#include "stdbool.h" +#include "xil_types.h" +#include "xstatus.h" +#include "xil_exception.h" +#include "xvidc_edid_ext.h" + +static XV_VidC_PicAspectRatio xv_vidc_getPicAspectRatio(u16 hres, u16 vres); + +static XV_VidC_PicAspectRatio xv_vidc_getPicAspectRatio(u16 hres, u16 vres) { + XV_VidC_PicAspectRatio ar; +#define HAS_RATIO_OF(x, y) (hres == (vres*(x)/(y))&&!((vres*(x))%(y))) + if (HAS_RATIO_OF(16, 10)) { + ar.width = 16; + ar.height = 10; + return ar; + } + if (HAS_RATIO_OF(4, 3)) { + ar.width = 4; + ar.height = 3; + return ar; + } + if (HAS_RATIO_OF(5, 4)) { + ar.width = 5; + ar.height = 4; + return ar; + } + if (HAS_RATIO_OF(16, 9)) { + ar.width = 16; + ar.height = 9; + return ar; +#undef HAS_RATIO + } else { + ar.width = 0; + ar.height = 0; + return ar; + } +} + + +void XV_VidC_EdidCtrlParamInit (XV_VidC_EdidCntrlParam *EdidCtrlParam) { + + /* Verify arguments. */ + Xil_AssertVoid(EdidCtrlParam != NULL); + + (void)memset((void *)EdidCtrlParam, 0, + sizeof(XV_VidC_EdidCntrlParam)); + + EdidCtrlParam->IsHdmi = XVIDC_ISDVI; + EdidCtrlParam->IsYCbCr444Supp = XVIDC_NOT_SUPPORTED; + EdidCtrlParam->IsYCbCr420Supp = XVIDC_NOT_SUPPORTED; + EdidCtrlParam->IsYCbCr422Supp = XVIDC_NOT_SUPPORTED; + EdidCtrlParam->IsYCbCr444DeepColSupp = XVIDC_NOT_SUPPORTED; + EdidCtrlParam->Is30bppSupp = XVIDC_NOT_SUPPORTED; + EdidCtrlParam->Is36bppSupp = XVIDC_NOT_SUPPORTED; + EdidCtrlParam->Is48bppSupp = XVIDC_NOT_SUPPORTED; + EdidCtrlParam->IsYCbCr420dc30bppSupp = XVIDC_NOT_SUPPORTED; + EdidCtrlParam->IsYCbCr420dc36bppSupp = XVIDC_NOT_SUPPORTED; + EdidCtrlParam->IsYCbCr420dc48bppSupp = XVIDC_NOT_SUPPORTED; + EdidCtrlParam->IsSCDCReadRequestReady= XVIDC_NOT_SUPPORTED; + EdidCtrlParam->IsSCDCPresent = XVIDC_NOT_SUPPORTED; + EdidCtrlParam->MaxFrameRateSupp = 0; + EdidCtrlParam->MaxTmdsMhz = 0; +} + +XV_VidC_TimingParam +XV_VidC_timing + (const struct xvidc_edid_detailed_timing_descriptor * const dtb) +{ + XV_VidC_TimingParam timing; + + timing.hres = xvidc_edid_detailed_timing_horizontal_active(dtb); + timing.vres = xvidc_edid_detailed_timing_vertical_active(dtb); + timing.htotal = timing.hres + + xvidc_edid_detailed_timing_horizontal_blanking(dtb); + timing.vtotal = timing.vres + + xvidc_edid_detailed_timing_vertical_blanking(dtb); + timing.hfp = xvidc_edid_detailed_timing_horizontal_sync_offset(dtb); + timing.vfp = xvidc_edid_detailed_timing_vertical_sync_offset(dtb); + timing.hsync_width = + xvidc_edid_detailed_timing_horizontal_sync_pulse_width(dtb); + timing.vsync_width = + xvidc_edid_detailed_timing_vertical_sync_pulse_width(dtb); + timing.pixclk = xvidc_edid_detailed_timing_pixel_clock(dtb); + timing.vfreq = (timing.pixclk / (timing.vtotal * timing.htotal)); + timing.vidfrmt = (XVidC_VideoFormat) dtb->interlaced; + timing.aspect_ratio = + xv_vidc_getPicAspectRatio (timing.hres, timing.vres); + timing.hsync_polarity = dtb->signal_pulse_polarity; + timing.vsync_polarity = dtb->signal_serration_polarity; + + return timing; +} + +#if XVIDC_EDID_VERBOSITY > 1 +XV_VidC_DoubleRep Double2Int (double in_val) { + XV_VidC_DoubleRep DR; + + DR.Integer = in_val; + DR.Decimal = (in_val - DR.Integer) * 10000; + + return (DR); +} +#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc_edid_ext.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc_edid_ext.h new file mode 100644 index 0000000..d685723 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc_edid_ext.h
@@ -0,0 +1,626 @@ +/* vim: set et fde fdm=syntax ft=c.doxygen ts=4 sts=4 sw=4 : */ +/* + * Copyright © 2010-2011 Saleem Abdulrasool <compnerd@compnerd.org>. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef xvidc_edid_h +#define xvidc_edid_h + +#include "stdbool.h" +#include "xvidc.h" +#include "xil_assert.h" +#include "xvidc_cea861.h" + +#define XVIDC_EDID_BLOCK_SIZE (0x80) +#define XVIDC_EDID_MAX_EXTENSIONS (0xFE) + + +static const u8 XVIDC_EDID_EXT_HEADER[] = + { 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 }; +static const u8 XVIDC_EDID_STANDARD_TIMING_DESCRIPTOR_INVALID[] = + { 0x01, 0x01 }; + +enum xvidc_edid_extension_type { + XVIDC_EDID_EXTENSION_TIMING = 0x01, /* Timing Extension */ + XVIDC_EDID_EXTENSION_CEA = 0x02, /* Additional Timing Block + Data (CEA EDID Timing Extension)*/ + XVIDC_EDID_EXTENSION_VTB = 0x10, /* Video Timing Block + Extension (VTB-EXT)*/ + XVIDC_EDID_EXTENSION_XVIDC_EDID_2_0= 0x20, /* EDID 2.0 Extension */ + XVIDC_EDID_EXTENSION_DI = 0x40, /* Display Information + Extension (DI-EXT) */ + XVIDC_EDID_EXTENSION_LS = 0x50, /* Localised String + Extension (LS-EXT) */ + XVIDC_EDID_EXTENSION_MI = 0x60, /* Microdisplay Interface + Extension (MI-EXT) */ + XVIDC_EDID_EXTENSION_DTCDB_1 = 0xA7, /* Display Transfer + Characteristics Data Block (DTCDB) */ + XVIDC_EDID_EXTENSION_DTCDB_2 = 0xAF, + XVIDC_EDID_EXTENSION_DTCDB_3 = 0xBF, + XVIDC_EDID_EXTENSION_BLOCK_MAP = 0xF0, /* Block Map*/ + XVIDC_EDID_EXTENSION_DDDB = 0xFF, /* Display Device Data + Block (DDDB)*/ +}; + +enum xvidc_edid_display_type { + XVIDC_EDID_DISPLAY_TYPE_MONOCHROME, + XVIDC_EDID_DISPLAY_TYPE_RGB, + XVIDC_EDID_DISPLAY_TYPE_NON_RGB, + XVIDC_EDID_DISPLAY_TYPE_UNDEFINED, +}; + +enum xvidc_edid_aspect_ratio { + XVIDC_EDID_ASPECT_RATIO_16_10, + XVIDC_EDID_ASPECT_RATIO_4_3, + XVIDC_EDID_ASPECT_RATIO_5_4, + XVIDC_EDID_ASPECT_RATIO_16_9, +}; + +enum xvidc_edid_signal_sync { + XVIDC_EDID_SIGNAL_SYNC_ANALOG_COMPOSITE, + XVIDC_EDID_SIGNAL_SYNC_BIPOLAR_ANALOG_COMPOSITE, + XVIDC_EDID_SIGNAL_SYNC_DIGITAL_COMPOSITE, + XVIDC_EDID_SIGNAL_SYNC_DIGITAL_SEPARATE, +}; + +enum xvidc_edid_stereo_mode { + XVIDC_EDID_STEREO_MODE_NONE, + XVIDC_EDID_STEREO_MODE_RESERVED, + XVIDC_EDID_STEREO_MODE_FIELD_SEQUENTIAL_RIGHT, + XVIDC_EDID_STEREO_MODE_2_WAY_INTERLEAVED_RIGHT, + XVIDC_EDID_STEREO_MODE_FIELD_SEQUENTIAL_LEFT, + XVIDC_EDID_STEREO_MODE_2_WAY_INTERLEAVED_LEFT, + XVIDC_EDID_STEREO_MODE_4_WAY_INTERLEAVED, + XVIDC_EDID_STEREO_MODE_SIDE_BY_SIDE_INTERLEAVED, +}; + +enum xvidc_edid_monitor_descriptor_type { + XVIDC_EDID_MONTIOR_DESCRIPTOR_MANUFACTURER_DEFINED = 0x0F, + XVIDC_EDID_MONITOR_DESCRIPTOR_STANDARD_TIMING_IDENTIFIERS = 0xFA, + XVIDC_EDID_MONITOR_DESCRIPTOR_COLOR_POINT = 0xFB, + XVIDC_EDID_MONITOR_DESCRIPTOR_MONITOR_NAME = 0xFC, + XVIDC_EDID_MONITOR_DESCRIPTOR_MONITOR_RANGE_LIMITS = 0xFD, + XVIDC_EDID_MONITOR_DESCRIPTOR_ASCII_STRING = 0xFE, + XVIDC_EDID_MONITOR_DESCRIPTOR_MONITOR_SERIAL_NUMBER = 0xFF, +}; + +enum xvidc_edid_secondary_timing_support { + XVIDC_EDID_SECONDARY_TIMING_NOT_SUPPORTED, + XVIDC_EDID_SECONDARY_TIMING_GFT = 0x02, +}; + + +struct __attribute__ (( packed )) xvidc_edid_detailed_timing_descriptor { + u16 pixel_clock; /* = value * 10000 */ + + u8 horizontal_active_lo; + u8 horizontal_blanking_lo; + + unsigned horizontal_blanking_hi : 4; + unsigned horizontal_active_hi : 4; + + u8 vertical_active_lo; + u8 vertical_blanking_lo; + + unsigned vertical_blanking_hi : 4; + unsigned vertical_active_hi : 4; + + u8 horizontal_sync_offset_lo; + u8 horizontal_sync_pulse_width_lo; + + unsigned vertical_sync_pulse_width_lo : 4; + unsigned vertical_sync_offset_lo : 4; + + unsigned vertical_sync_pulse_width_hi : 2; + unsigned vertical_sync_offset_hi : 2; + unsigned horizontal_sync_pulse_width_hi : 2; + unsigned horizontal_sync_offset_hi : 2; + + u8 horizontal_image_size_lo; + u8 vertical_image_size_lo; + + unsigned vertical_image_size_hi : 4; + unsigned horizontal_image_size_hi : 4; + + u8 horizontal_border; + u8 vertical_border; + + unsigned stereo_mode_lo : 1; + unsigned signal_pulse_polarity : 1; /* pulse on sync, + composite/horizontal polarity */ + unsigned signal_serration_polarity : 1; /* serrate on sync, vertical + polarity */ + unsigned signal_sync : 2; + unsigned stereo_mode_hi : 2; + unsigned interlaced : 1; +}; + +static inline u32 +xvidc_edid_detailed_timing_pixel_clock + (const struct xvidc_edid_detailed_timing_descriptor * const dtb) +{ + return dtb->pixel_clock * 10000; +} + +static inline u16 +xvidc_edid_detailed_timing_horizontal_blanking + (const struct xvidc_edid_detailed_timing_descriptor * const dtb) +{ + return (dtb->horizontal_blanking_hi << 8) | dtb->horizontal_blanking_lo; +} + +static inline u16 +xvidc_edid_detailed_timing_horizontal_active + (const struct xvidc_edid_detailed_timing_descriptor * const dtb) +{ + return (dtb->horizontal_active_hi << 8) | dtb->horizontal_active_lo; +} + +static inline u16 +xvidc_edid_detailed_timing_vertical_blanking + (const struct xvidc_edid_detailed_timing_descriptor * const dtb) +{ + return (dtb->vertical_blanking_hi << 8) | dtb->vertical_blanking_lo; +} + +static inline u16 +xvidc_edid_detailed_timing_vertical_active + (const struct xvidc_edid_detailed_timing_descriptor * const dtb) +{ + return (dtb->vertical_active_hi << 8) | dtb->vertical_active_lo; +} + +static inline u8 +xvidc_edid_detailed_timing_vertical_sync_offset + (const struct xvidc_edid_detailed_timing_descriptor * const dtb) +{ + return (dtb->vertical_sync_offset_hi << 4) | dtb->vertical_sync_offset_lo; +} + +static inline u8 +xvidc_edid_detailed_timing_vertical_sync_pulse_width + (const struct xvidc_edid_detailed_timing_descriptor * const dtb) +{ + return (dtb->vertical_sync_pulse_width_hi << 4) | + dtb->vertical_sync_pulse_width_lo; +} + +static inline u8 +xvidc_edid_detailed_timing_horizontal_sync_offset + (const struct xvidc_edid_detailed_timing_descriptor * const dtb) +{ + return (dtb->horizontal_sync_offset_hi << 4) | + dtb->horizontal_sync_offset_lo; +} + +static inline u8 +xvidc_edid_detailed_timing_horizontal_sync_pulse_width + (const struct xvidc_edid_detailed_timing_descriptor * const dtb) +{ + return (dtb->horizontal_sync_pulse_width_hi << 4) | + dtb->horizontal_sync_pulse_width_lo; +} + +static inline u16 +xvidc_edid_detailed_timing_horizontal_image_size + (const struct xvidc_edid_detailed_timing_descriptor * const dtb) +{ + return + (dtb->horizontal_image_size_hi << 8) | dtb->horizontal_image_size_lo; +} + +static inline u16 +xvidc_edid_detailed_timing_vertical_image_size + (const struct xvidc_edid_detailed_timing_descriptor * const dtb) +{ + return (dtb->vertical_image_size_hi << 8) | dtb->vertical_image_size_lo; +} + +static inline u8 +xvidc_edid_detailed_timing_stereo_mode + (const struct xvidc_edid_detailed_timing_descriptor * const dtb) +{ + return (dtb->stereo_mode_hi << 2 | dtb->stereo_mode_lo); +} + + +struct __attribute__ (( packed )) xvidc_edid_monitor_descriptor { + u16 flag0; + u8 flag1; + u8 tag; + u8 flag2; + u8 data[13]; +}; + +typedef char xvidc_edid_monitor_descriptor_string + [sizeof(((struct xvidc_edid_monitor_descriptor *)0)->data) + 1]; + + +struct __attribute__ (( packed )) xvidc_edid_monitor_range_limits { + u8 minimum_vertical_rate; /* Hz */ + u8 maximum_vertical_rate; /* Hz */ + u8 minimum_horizontal_rate; /* kHz */ + u8 maximum_horizontal_rate; /* kHz */ + u8 maximum_supported_pixel_clock; /* = (value * 10) Mhz + (round to 10 MHz) */ + + /* secondary timing formula */ + u8 secondary_timing_support; + u8 reserved; + u8 secondary_curve_start_frequency; /* horizontal frequency / 2 kHz */ + u8 c; /* = (value >> 1) */ + u16 m; + u8 k; + u8 j; /* = (value >> 1) */ +}; + + +struct __attribute__ (( packed )) xvidc_edid_standard_timing_descriptor { + u8 horizontal_active_pixels; /* = (value + 31) * 8 */ + + unsigned refresh_rate : 6; /* = value + 60 */ + unsigned image_aspect_ratio : 2; +}; + +inline u32 +xvidc_edid_standard_timing_horizontal_active +(const struct xvidc_edid_standard_timing_descriptor * const desc) { + return ((desc->horizontal_active_pixels + 31) << 3); +} + +inline u32 +xvidc_edid_standard_timing_vertical_active +(const struct xvidc_edid_standard_timing_descriptor * const desc) { + const u32 hres = xvidc_edid_standard_timing_horizontal_active(desc); + + switch (desc->image_aspect_ratio) { + case XVIDC_EDID_ASPECT_RATIO_16_10: + return ((hres * 10) >> 4); + case XVIDC_EDID_ASPECT_RATIO_4_3: + return ((hres * 3) >> 2); + case XVIDC_EDID_ASPECT_RATIO_5_4: + return ((hres << 2) / 5); + case XVIDC_EDID_ASPECT_RATIO_16_9: + return ((hres * 9) >> 4); + } + + return hres; +} + +inline u32 +xvidc_edid_standard_timing_refresh_rate +(const struct xvidc_edid_standard_timing_descriptor * const desc) { + return (desc->refresh_rate + 60); +} + + +struct __attribute__ (( packed )) edid { + /* header information */ + u8 header[8]; + + /* vendor/product identification */ + u16 manufacturer; + union { + u16 product_u16; + u8 product[2]; + }; + union { + u32 serial_number_u32; + u8 serial_number[4]; + }; + u8 manufacture_week; + u8 manufacture_year; /* = value + 1990 */ + + /* EDID version */ + u8 version; + u8 revision; + + /* basic display parameters and features */ + union { + struct __attribute__ (( packed )) { + unsigned dfp_1x : 1; /* VESA DFP 1.x */ + unsigned : 6; + unsigned digital : 1; + } digital; + struct __attribute__ (( packed )) { + unsigned vsync_serration : 1; + unsigned green_video_sync : 1; + unsigned composite_sync : 1; + unsigned separate_sync : 1; + unsigned blank_to_black_setup : 1; + unsigned signal_level_standard : 2; + unsigned digital : 1; + } analog; + } video_input_definition; + + u8 maximum_horizontal_image_size; /* cm */ + u8 maximum_vertical_image_size; /* cm */ + + u8 display_transfer_characteristics; /* gamma = (value + 100) / 100 */ + + struct __attribute__ (( packed )) { + unsigned default_gtf : 1; /* generalised timing + formula */ + unsigned preferred_timing_mode : 1; + unsigned standard_default_color_space : 1; + unsigned display_type : 2; + unsigned active_off : 1; + unsigned suspend : 1; + unsigned standby : 1; + } feature_support; + + /* color characteristics block */ + unsigned green_y_low : 2; + unsigned green_x_low : 2; + unsigned red_y_low : 2; + unsigned red_x_low : 2; + + unsigned white_y_low : 2; + unsigned white_x_low : 2; + unsigned blue_y_low : 2; + unsigned blue_x_low : 2; + + u8 red_x; + u8 red_y; + u8 green_x; + u8 green_y; + u8 blue_x; + u8 blue_y; + u8 white_x; + u8 white_y; + + /* established timings */ + struct __attribute__ (( packed )) { + unsigned timing_800x600_60 : 1; + unsigned timing_800x600_56 : 1; + unsigned timing_640x480_75 : 1; + unsigned timing_640x480_72 : 1; + unsigned timing_640x480_67 : 1; + unsigned timing_640x480_60 : 1; + unsigned timing_720x400_88 : 1; + unsigned timing_720x400_70 : 1; + + unsigned timing_1280x1024_75 : 1; + unsigned timing_1024x768_75 : 1; + unsigned timing_1024x768_70 : 1; + unsigned timing_1024x768_60 : 1; + unsigned timing_1024x768_87 : 1; + unsigned timing_832x624_75 : 1; + unsigned timing_800x600_75 : 1; + unsigned timing_800x600_72 : 1; + } established_timings; + + struct __attribute__ (( packed )) { + unsigned reserved : 7; + unsigned timing_1152x870_75 : 1; + } manufacturer_timings; + + /* standard timing id */ + struct xvidc_edid_standard_timing_descriptor standard_timing_id[8]; + + /* detailed timing */ + union { + struct xvidc_edid_monitor_descriptor monitor; + struct xvidc_edid_detailed_timing_descriptor timing; + } detailed_timings[4]; + + u8 extensions; + u8 checksum; +}; + +static inline void +xvidc_edid_manufacturer(const struct edid * const edid, char manufacturer[4]) +{ + manufacturer[0] = '@' + ((edid->manufacturer & 0x007c) >> 2); + manufacturer[1] = '@' + ((((edid->manufacturer & 0x0003) >> 00) << 3) | (((edid->manufacturer & 0xe000) >> 13) << 0)); + manufacturer[2] = '@' + ((edid->manufacturer & 0x1f00) >> 8); + manufacturer[3] = '\0'; +} + +static inline double +xvidc_edid_gamma(const struct edid * const edid) +{ + return (edid->display_transfer_characteristics + 100) / 100.0; +} + +static inline bool +xvidc_edid_detailed_timing_is_monitor_descriptor(const struct edid * const edid, + const u8 timing) +{ + const struct xvidc_edid_monitor_descriptor * const mon = + &edid->detailed_timings[timing].monitor; + + Xil_AssertNonvoid(timing < ARRAY_SIZE(edid->detailed_timings)); + + return mon->flag0 == 0x0000 && mon->flag1 == 0x00 && mon->flag2 == 0x00; +} + + +struct __attribute__ (( packed )) xvidc_edid_color_characteristics_data { + struct { + u16 x; + u16 y; + } red, green, blue, white; +}; + +static inline struct xvidc_edid_color_characteristics_data +xvidc_edid_color_characteristics(const struct edid * const edid) +{ + const struct xvidc_edid_color_characteristics_data characteristics = { + .red = { + .x = (edid->red_x << 2) | edid->red_x_low, + .y = (edid->red_y << 2) | edid->red_y_low, + }, + .green = { + .x = (edid->green_x << 2) | edid->green_x_low, + .y = (edid->green_y << 2) | edid->green_y_low, + }, + .blue = { + .x = (edid->blue_x << 2) | edid->blue_x_low, + .y = (edid->blue_y << 2) | edid->blue_y_low, + }, + .white = { + .x = (edid->white_x << 2) | edid->white_x_low, + .y = (edid->white_y << 2) | edid->white_y_low, + }, + }; + + return characteristics; +} + + +struct __attribute__ (( packed )) xvidc_edid_block_map { + u8 tag; + u8 extension_tag[126]; + u8 checksum; +}; + + +struct __attribute__ (( packed )) xvidc_edid_extension { + u8 tag; + u8 revision; + u8 extension_data[125]; + u8 checksum; +}; + + +static inline bool +xvidc_edid_verify_checksum(const u8 * const block) +{ + u8 checksum = 0; + int i; + + for (i = 0; i < XVIDC_EDID_BLOCK_SIZE; i++) + checksum += block[i]; + + return (checksum == 0); +} + +static inline double +xvidc_edid_decode_fixed_point(u16 value) +{ + double result = 0.0; + + Xil_AssertNonvoid((~value & 0xfc00) == 0xfc00); + /* edid fraction is 10 bits */ + + for (u8 i = 0; value && (i < 10); i++, value >>= 1) + result = result + ((value & 0x1) * (1.0 / (1 << (10 - i)))); + + return result; +} + +typedef enum { + XVIDC_VERBOSE_DISABLE, + XVIDC_VERBOSE_ENABLE +} XV_VidC_Verbose; + +typedef enum { + XVIDC_ISDVI, + XVIDC_ISHDMI +} XV_VidC_IsHdmi; + +typedef enum { + XVIDC_NOT_SUPPORTED, + XVIDC_SUPPORTED +} XV_VidC_Supp; +#if XVIDC_EDID_VERBOSITY > 1 +typedef struct { + u32 Integer; + u32 Decimal; +} XV_VidC_DoubleRep; +#endif + +typedef struct { + u8 width; + u8 height; +} XV_VidC_PicAspectRatio; + +typedef struct { + u16 hres; + u16 vres; + u16 htotal; + u16 vtotal; + XVidC_VideoFormat vidfrmt; + u32 pixclk; + u16 hsync_width; + u16 vsync_width; + u16 hfp; + u16 vfp; + u8 vfreq; + XV_VidC_PicAspectRatio aspect_ratio; + unsigned hsync_polarity : 1; + unsigned vsync_polarity : 1; +} XV_VidC_TimingParam; + +typedef struct { + /*Checks whether Sink able to support HDMI*/ + XV_VidC_IsHdmi IsHdmi; + /*Color Space Support*/ + XV_VidC_Supp IsYCbCr444Supp; + XV_VidC_Supp IsYCbCr420Supp; + XV_VidC_Supp IsYCbCr422Supp; + /*YCbCr444/YCbCr422/RGB444 Deep Color Support*/ + XV_VidC_Supp IsYCbCr444DeepColSupp; + XV_VidC_Supp Is30bppSupp; + XV_VidC_Supp Is36bppSupp; + XV_VidC_Supp Is48bppSupp; + /*YCbCr420 Deep Color Support*/ + XV_VidC_Supp IsYCbCr420dc30bppSupp; + XV_VidC_Supp IsYCbCr420dc36bppSupp; + XV_VidC_Supp IsYCbCr420dc48bppSupp; + /*SCDC and SCDC ReadRequest Support*/ + XV_VidC_Supp IsSCDCReadRequestReady; + XV_VidC_Supp IsSCDCPresent; + /*Sink Capability Support*/ + u8 MaxFrameRateSupp; + u16 MaxTmdsMhz; + /*CEA 861 Supported VIC Support*/ + u8 SuppCeaVIC[32]; + /*VESA Sink Preffered Timing Support*/ + XV_VidC_TimingParam PreferedTiming[4]; +} XV_VidC_EdidCntrlParam; + + +XV_VidC_TimingParam +XV_VidC_timing + (const struct xvidc_edid_detailed_timing_descriptor * const dtb); +#if XVIDC_EDID_VERBOSITY > 1 +XV_VidC_DoubleRep Double2Int (double in_val); +#endif +void XV_VidC_EdidCtrlParamInit (XV_VidC_EdidCntrlParam *EdidCtrlParam); + +void +XV_VidC_parse_edid(const u8 * const data, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn); + +#ifdef __cplusplus +} +#endif +#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc_parse_edid.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc_parse_edid.c new file mode 100644 index 0000000..6b0edb6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc_parse_edid.c
@@ -0,0 +1,1332 @@ +/* vim: set et fde fdm=syntax ft=c.doxygen ts=4 sts=4 sw=4 : */ +/* + * Copyright © 2011 Saleem Abdulrasool <compnerd@compnerd.org>. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "string.h" +#include "stdlib.h" +#include "stddef.h" + +#include "xil_types.h" +#include "xstatus.h" +#include "xil_exception.h" + +#include "xvidc_edid_ext.h" + +#if XVIDC_EDID_VERBOSITY > 1 +#include "math.h" + +#define CM_2_MM(cm) ((cm) * 10) +#define CM_2_IN(cm) ((cm) * 0.3937) +#endif +#if XVIDC_EDID_VERBOSITY > 0 +#define HZ_2_MHZ(hz) ((hz) / 1000000) +#endif +#if XVIDC_EDID_VERBOSITY > 1 +static void +xvidc_disp_cea861_audio_data( + const struct xvidc_cea861_audio_data_block * const adb, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn); + +static void +xvidc_disp_cea861_speaker_allocation_data( + const struct xvidc_cea861_speaker_allocation_data_block * const sadb, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn); + +static void +xvidc_disp_cea861_video_data( + const struct xvidc_cea861_video_data_block * const vdb, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn); +#endif + +static void +xvidc_disp_cea861_extended_data( + const struct xvidc_cea861_extended_data_block * const edb, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn); + +static void +xvidc_disp_cea861_vendor_data( + const struct xvidc_cea861_vendor_specific_data_block * vsdb, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn); + +static void +xvidc_disp_cea861(const struct xvidc_edid_extension * const ext, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn); + +static void +xvidc_disp_edid1(const struct edid * const edid, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn); + +/*****************************************************************************/ +/** +* +* This function parse EDID on General Data & VESA Data +* +* @param data is a pointer to the EDID array. +* @param EdidCtrlParam is a pointer the EDID Control parameter +* @param VerboseEn is a pointer to the XV_HdmiTxSs core instance. +* +* @return None +* +* @note API Define below here are CEA861 routines +* +******************************************************************************/ +static void +xvidc_disp_edid1(const struct edid * const edid, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn) +{ + const struct xvidc_edid_monitor_range_limits *monitor_range_limits = NULL; + xvidc_edid_monitor_descriptor_string monitor_serial_number = {0}; + xvidc_edid_monitor_descriptor_string monitor_model_name = {0}; + bool has_ascii_string = false; + char manufacturer[4] = {0}; +#if XVIDC_EDID_VERBOSITY > 1 + XV_VidC_DoubleRep min_doubleval; + XV_VidC_DoubleRep max_doubleval; +#endif + + u8 i; +#if XVIDC_EDID_VERBOSITY > 0 + //add by mmo + XV_VidC_TimingParam timing_params; +#endif + +#if XVIDC_EDID_VERBOSITY > 1 + struct xvidc_edid_color_characteristics_data characteristics; + const u8 vlen = edid->maximum_vertical_image_size; + const u8 hlen = edid->maximum_horizontal_image_size; + + + static const char * const display_type[] = { + [XVIDC_EDID_DISPLAY_TYPE_MONOCHROME] = "Monochrome or greyscale", + [XVIDC_EDID_DISPLAY_TYPE_RGB] = "sRGB colour", + [XVIDC_EDID_DISPLAY_TYPE_NON_RGB] = "Non-sRGB colour", + [XVIDC_EDID_DISPLAY_TYPE_UNDEFINED] = "Undefined", + }; +#endif + xvidc_edid_manufacturer(edid, manufacturer); + + for (i = 0; i < ARRAY_SIZE(edid->detailed_timings); i++) { + const struct xvidc_edid_monitor_descriptor * const mon = + &edid->detailed_timings[i].monitor; + + if (!xvidc_edid_detailed_timing_is_monitor_descriptor(edid, i)) + continue; + + switch (mon->tag) { + case XVIDC_EDID_MONTIOR_DESCRIPTOR_MANUFACTURER_DEFINED: + /* This is arbitrary data, just silently ignore it. */ + break; + case XVIDC_EDID_MONITOR_DESCRIPTOR_ASCII_STRING: + has_ascii_string = true; + break; + case XVIDC_EDID_MONITOR_DESCRIPTOR_MONITOR_NAME: + strncpy(monitor_model_name, (char *) mon->data, + sizeof(monitor_model_name) - 1); + break; + case XVIDC_EDID_MONITOR_DESCRIPTOR_MONITOR_RANGE_LIMITS: + monitor_range_limits = + (struct xvidc_edid_monitor_range_limits *) &mon->data; + break; + case XVIDC_EDID_MONITOR_DESCRIPTOR_MONITOR_SERIAL_NUMBER: + strncpy(monitor_serial_number, (char *) mon->data, + sizeof(monitor_serial_number) - 1); + break; + default: + if (VerboseEn) { + xil_printf("unknown monitor descriptor type 0x%02x\n", + mon->tag); + } + break; + } + } + +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf("Sink Information\r\n"); + + xil_printf(" Model name............... %s\r\n", + *monitor_model_name ? monitor_model_name : "n/a"); +#if XVIDC_EDID_VERBOSITY > 1 + xil_printf(" Manufacturer............. %s\r\n", + manufacturer); + + xil_printf(" Product code............. %u\r\n", + (u16) edid->product_u16); + + if (*(u32 *) edid->serial_number_u32) + xil_printf(" Module serial number..... %u\r\n", + (u32) edid->serial_number_u32); +#endif +#if defined(DISPLAY_UNKNOWN) + xil_printf(" Plug and Play ID......... %s\r\n", NULL); +#endif +#if XVIDC_EDID_VERBOSITY > 1 + xil_printf(" Serial number............ %s\r\n", + *monitor_serial_number ? monitor_serial_number : "n/a"); + + xil_printf(" Manufacture date......... %u", + edid->manufacture_year + 1990); + if (edid->manufacture_week <= 52) + xil_printf(", ISO week %u", edid->manufacture_week); + xil_printf("\r\n"); +#endif + xil_printf(" EDID revision............ %u.%u\r\n", + edid->version, edid->revision); +#if XVIDC_EDID_VERBOSITY > 1 + xil_printf(" Input signal type........ %s\r\n", + edid->video_input_definition.digital.digital ? "Digital" : "Analog"); + + if (edid->video_input_definition.digital.digital) { + xil_printf(" VESA DFP 1.x supported... %s\r\n", + edid->video_input_definition.digital.dfp_1x ? "Yes" : "No"); + } else { + /* Missing Piece: To print analog flags */ + } +#endif +#if defined(DISPLAY_UNKNOWN) + xil_printf(" Color bit depth.......... %s\r\n", NULL); +#endif +#if XVIDC_EDID_VERBOSITY > 1 + xil_printf(" Display type............. %s\r\n", + display_type[edid->feature_support.display_type]); + + xil_printf(" Screen size.............. %u mm x %u mm (%.1f in)\r\n", + CM_2_MM(hlen), CM_2_MM(vlen), + CM_2_IN(sqrt(hlen * hlen + vlen * vlen))); + + xil_printf(" Power management......... %s%s%s%s\r\n", + edid->feature_support.active_off ? "Active off, " : "", + edid->feature_support.suspend ? "Suspend, " : "", + edid->feature_support.standby ? "Standby, " : "", + + (edid->feature_support.active_off || + edid->feature_support.suspend || + edid->feature_support.standby) ? "\b\b " : "n/a"); +#endif + xil_printf(" Extension blocks......... %u\r\n", + edid->extensions); + +#if defined(DISPLAY_UNKNOWN) + xil_printf(" DDC/CI................... %s\r\n", NULL); +#endif + + xil_printf("\r\n"); + } +#endif + if (has_ascii_string) { + if (VerboseEn) { +#if XVIDC_EDID_VERBOSITY > 1 + xil_printf("General purpose ASCII string\r\n"); +#endif + } + + for (i = 0; i < ARRAY_SIZE(edid->detailed_timings); i++) { + if (!xvidc_edid_detailed_timing_is_monitor_descriptor(edid, i)) + continue; + } + + if (VerboseEn) { +#if XVIDC_EDID_VERBOSITY > 1 + xil_printf("\r\n"); +#endif + } + } +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf("Color characteristics\r\n"); + + xil_printf(" Default color space...... %ssRGB\r\n", + edid->feature_support.standard_default_color_space ? "":"Non-"); +#if XVIDC_EDID_VERBOSITY > 1 + min_doubleval = + Double2Int(xvidc_edid_gamma(edid)); + xil_printf(" Display gamma............ %d.%03d\r\n", + min_doubleval.Integer, min_doubleval.Decimal); + + characteristics = xvidc_edid_color_characteristics(edid); + + min_doubleval = + Double2Int(xvidc_edid_decode_fixed_point(characteristics.red.x)); + max_doubleval = + Double2Int(xvidc_edid_decode_fixed_point(characteristics.red.y)); + + xil_printf(" Red chromaticity......... Rx %d.%03d - Ry %d.%03d\r\n", + min_doubleval.Integer, min_doubleval.Decimal, + max_doubleval.Integer, max_doubleval.Decimal); + + min_doubleval = + Double2Int(xvidc_edid_decode_fixed_point(characteristics.green.x)); + max_doubleval = + Double2Int(xvidc_edid_decode_fixed_point(characteristics.green.y)); + + xil_printf(" Green chromaticity....... Gx %d.%03d - Gy %d.%03d\r\n", + min_doubleval.Integer, min_doubleval.Decimal, + max_doubleval.Integer, max_doubleval.Decimal); + + min_doubleval = + Double2Int(xvidc_edid_decode_fixed_point(characteristics.blue.x)); + max_doubleval = + Double2Int(xvidc_edid_decode_fixed_point(characteristics.blue.y)); + + xil_printf(" Blue chromaticity........ Bx %d.%03d - By %d.%03d\r\n", + min_doubleval.Integer, min_doubleval.Decimal, + max_doubleval.Integer, max_doubleval.Decimal); + + min_doubleval = + Double2Int(xvidc_edid_decode_fixed_point(characteristics.white.x)); + max_doubleval = + Double2Int(xvidc_edid_decode_fixed_point(characteristics.white.y)); + + xil_printf(" White point (default).... Wx %d.%03d - Wy %d.%03d\r\n", + min_doubleval.Integer, min_doubleval.Decimal, + max_doubleval.Integer, max_doubleval.Decimal); +#endif +#if defined(DISPLAY_UNKNOWN) + xil_printf(" Additional descriptors... %s\r\n", NULL); +#endif + xil_printf("\r\n"); + + xil_printf("VESA Timing characteristics\r\n"); + } +#endif + if (monitor_range_limits) { +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf(" Horizontal scan range.... %u - %u kHz\r\n", + monitor_range_limits->minimum_horizontal_rate, + monitor_range_limits->maximum_horizontal_rate); + + xil_printf(" Vertical scan range...... %u - %u Hz\r\n", + monitor_range_limits->minimum_vertical_rate, + monitor_range_limits->maximum_vertical_rate); + + xil_printf(" Video bandwidth.......... %u MHz\r\n", + monitor_range_limits->maximum_supported_pixel_clock * 10); + } +#endif + EdidCtrlParam->MaxFrameRateSupp = + monitor_range_limits->maximum_vertical_rate; + EdidCtrlParam->MaxTmdsMhz = + (monitor_range_limits->maximum_supported_pixel_clock * 10); + } + +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { +#if defined(DISPLAY_UNKNOWN) + xil_printf(" CVT standard............. %s\r\n", NULL); +#endif +#if XVIDC_EDID_VERBOSITY > 1 + xil_printf(" GTF standard............. %sSupported\r\n", + edid->feature_support.default_gtf ? "" : "Not "); +#endif +#if defined(DISPLAY_UNKNOWN) + xil_printf(" Additional descriptors... %s\r\n", NULL); +#endif +#if XVIDC_EDID_VERBOSITY > 0 + xil_printf(" Preferred timing......... %s\r\n", + edid->feature_support.preferred_timing_mode ? "Yes" : "No"); +#endif + for (i = 0; i < ARRAY_SIZE(edid->detailed_timings); i++) { + if (xvidc_edid_detailed_timing_is_monitor_descriptor(edid, i)) + continue; + + timing_params = XV_VidC_timing(&edid->detailed_timings[i].timing); + EdidCtrlParam->PreferedTiming[i] = + XV_VidC_timing(&edid->detailed_timings[i].timing); +#if XVIDC_EDID_VERBOSITY > 0 + if (edid->feature_support.preferred_timing_mode) { + xil_printf(" Native/preferred timing.. %ux%u%c at %uHz" + " (%u:%u)\r\n", + timing_params.hres, + timing_params.vres, + timing_params.vidfrmt ? 'i' : 'p', + timing_params.vfreq, + timing_params.aspect_ratio.width, + timing_params.aspect_ratio.height); + xil_printf(" Modeline............... \"%ux%u\" %u %u %u %u" + " %u %u %u %u %u %chsync %cvsync\r\n", + timing_params.hres, + timing_params.vres, + HZ_2_MHZ (timing_params.pixclk), + (timing_params.hres), + (timing_params.hres + timing_params.hfp), + (timing_params.hres + timing_params.hfp + + timing_params.hsync_width), + (timing_params.htotal), + (timing_params.vres), + (timing_params.vres + timing_params.vfp), + (timing_params.vres + timing_params.vfp + + timing_params.vsync_width), + (timing_params.vtotal), + timing_params.hsync_polarity ? '+' : '-', + timing_params.vsync_polarity ? '+' : '-'); + } else { + xil_printf(" Native/preferred timing.. n/a\r\n"); + } +#endif + } +#if XVIDC_EDID_VERBOSITY > 0 + xil_printf("\r\n"); +#endif +#if XVIDC_EDID_VERBOSITY > 1 + xil_printf("Established Timings supported\r\n"); + if (edid->established_timings.timing_720x400_70) + xil_printf(" 720 x 400p @ 70Hz - IBM VGA\r\n"); + if (edid->established_timings.timing_720x400_88) + xil_printf(" 720 x 400p @ 88Hz - IBM XGA2\r\n"); + if (edid->established_timings.timing_640x480_60) + xil_printf(" 640 x 480p @ 60Hz - IBM VGA\r\n"); + if (edid->established_timings.timing_640x480_67) + xil_printf(" 640 x 480p @ 67Hz - Apple Mac II\r\n"); + if (edid->established_timings.timing_640x480_72) + xil_printf(" 640 x 480p @ 72Hz - VESA\r\n"); + if (edid->established_timings.timing_640x480_75) + xil_printf(" 640 x 480p @ 75Hz - VESA\r\n"); + if (edid->established_timings.timing_800x600_56) + xil_printf(" 800 x 600p @ 56Hz - VESA\r\n"); + if (edid->established_timings.timing_800x600_60) + xil_printf(" 800 x 600p @ 60Hz - VESA\r\n"); + + if (edid->established_timings.timing_800x600_72) + xil_printf(" 800 x 600p @ 72Hz - VESA\r\n"); + if (edid->established_timings.timing_800x600_75) + xil_printf(" 800 x 600p @ 75Hz - VESA\r\n"); + if (edid->established_timings.timing_832x624_75) + xil_printf(" 832 x 624p @ 75Hz - Apple Mac II\r\n"); + if (edid->established_timings.timing_1024x768_87) + xil_printf(" 1024 x 768i @ 87Hz - VESA\r\n"); + if (edid->established_timings.timing_1024x768_60) + xil_printf(" 1024 x 768p @ 60Hz - VESA\r\n"); + if (edid->established_timings.timing_1024x768_70) + xil_printf(" 1024 x 768p @ 70Hz - VESA\r\n"); + if (edid->established_timings.timing_1024x768_75) + xil_printf(" 1024 x 768p @ 75Hz - VESA\r\n"); + if (edid->established_timings.timing_1280x1024_75) + xil_printf(" 1280 x 1024p @ 75Hz - VESA\r\n"); +#endif + } +#endif + +#if XVIDC_EDID_VERBOSITY > 1 + if (VerboseEn) { + xil_printf("Standard Timings supported\r\n"); + for (i = 0; i < ARRAY_SIZE(edid->standard_timing_id); i++) { + const struct xvidc_edid_standard_timing_descriptor * const desc = + &edid->standard_timing_id[i]; + + if (!memcmp(desc, XVIDC_EDID_STANDARD_TIMING_DESCRIPTOR_INVALID, + sizeof(*desc))) + { + continue; + } else { + if (((desc->horizontal_active_pixels + 31)* 8) >= 1000) { + xil_printf(" %u x",(desc->horizontal_active_pixels + 31)* 8); + } else { + xil_printf(" %u x",(desc->horizontal_active_pixels + 31)* 8); + } + switch (desc->image_aspect_ratio) { + case 0: //Aspect Ratio = 16:10 + xil_printf(" %up ", + (((desc->horizontal_active_pixels + 31)* 8) * 10) / 16); + break; + case 1: //Aspect Ratio = 4:3 + xil_printf(" %up ", + (((desc->horizontal_active_pixels + 31)* 8) * 3) / 4); + break; + case 2: //Aspect Ratio = 5:4 + xil_printf(" %up ", + (((desc->horizontal_active_pixels + 31)* 8) * 4) / 5); + break; + case 3: //Aspect Ratio = 16:9 + xil_printf(" %up ", + (((desc->horizontal_active_pixels + 31)* 8) * 9) / 16); + break; + default: //Aspect Ratio = 16:10 + xil_printf(" %up ", + (((desc->horizontal_active_pixels + 31)* 8) * 10) / 16); + break; + } + xil_printf("@ %uHz\r\n",(desc->refresh_rate + 60)); + } + } + } +#endif +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf("\r\n"); + } +#endif +} + + + +/*****************************************************************************/ +/** +* +* This function parse EDID on CEA 861 Audio Data +* +* @param data is a pointer to the EDID array. +* @param EdidCtrlParam is a pointer the EDID Control parameter +* @param VerboseEn is a pointer to the XV_HdmiTxSs core instance. +* +* @return None +* +* @note API Define below here are CEA861 routines +* +******************************************************************************/ +#if XVIDC_EDID_VERBOSITY > 1 +static void +xvidc_disp_cea861_audio_data( + const struct xvidc_cea861_audio_data_block * const adb, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn) { + /* For Future Usage */ + EdidCtrlParam = EdidCtrlParam; + + const u8 descriptors = adb->header.length / sizeof(*adb->sad); +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf("CE audio data (formats supported)\r\n"); + } +#endif + for (u8 i = 0; i < descriptors; i++) { + const struct xvidc_cea861_short_audio_descriptor * const sad = + (struct xvidc_cea861_short_audio_descriptor *) &adb->sad[i]; + + switch (sad->audio_format) { + case XVIDC_CEA861_AUDIO_FORMAT_LPCM: +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf(" LPCM %u-channel, %s%s%s\b%s", + sad->channels + 1, + sad->flags.lpcm.bitrate_16_bit ? "16/" : "", + sad->flags.lpcm.bitrate_20_bit ? "20/" : "", + sad->flags.lpcm.bitrate_24_bit ? "24/" : "", + + ((sad->flags.lpcm.bitrate_16_bit + + sad->flags.lpcm.bitrate_20_bit + + sad->flags.lpcm.bitrate_24_bit) > 1) ? + " bit depths" : "-bit"); + } +#endif + break; + case XVIDC_CEA861_AUDIO_FORMAT_AC_3: +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf(" AC-3 %u-channel, %4uk max. bit rate", + sad->channels + 1, + (sad->flags.maximum_bit_rate << 3)); + } +#endif + break; + default: +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf("Unknown audio format 0x%02x\r\n", + sad->audio_format); + } +#endif + continue; + } +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf(" at %s%s%s%s%s%s%s\b kHz\r\n", + sad->sample_rate_32_kHz ? "32/" : "", + sad->sample_rate_44_1_kHz ? "44.1/" : "", + sad->sample_rate_48_kHz ? "48/" : "", + sad->sample_rate_88_2_kHz ? "88.2/" : "", + sad->sample_rate_96_kHz ? "96/" : "", + sad->sample_rate_176_4_kHz ? "176.4/" : "", + sad->sample_rate_192_kHz ? "192/" : ""); + } +#endif + } +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf("\r\n"); + } +#endif +} +#endif + +/*****************************************************************************/ +/** +* +* This function parse EDID on CEA 861 Extended Data +* +* @param data is a pointer to the EDID array. +* @param EdidCtrlParam is a pointer the EDID Control parameter +* @param VerboseEn is a pointer to the XV_HdmiTxSs core instance. +* +* @return None +* +* @note None. +* +******************************************************************************/ +static void +xvidc_disp_cea861_extended_data( + const struct xvidc_cea861_extended_data_block * const edb, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn) { + + /* During Verbosity 0, VerboseEn won't be used */ + /* To avoid compilation warnings */ + VerboseEn = VerboseEn; + +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf("CEA Extended Tags\r\n"); + } +#endif + switch(edb->xvidc_cea861_extended_tag_codes) { +#if XVIDC_EDID_VERBOSITY > 1 + case XVIDC_CEA861_EXT_TAG_TYPE_VIDEO_CAPABILITY: + if (VerboseEn) { + xil_printf(" Video capability data block\r\n"); + } + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_VENDOR_SPECIFIC: + if (VerboseEn) { + xil_printf(" Vendor-specific video data block\r\n"); + } + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_VESA_DISPLAY_DEVICE: + if (VerboseEn) { + xil_printf(" VESA video display device data block\r\n"); + } + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_VESA_VIDEO_TIMING_BLOCK_EXT: + if (VerboseEn) { + xil_printf("VESA video timing block extension\r\n"); + } + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_RESERVED_FOR_HDMI_VIDEO_DATA_BLOCK: + if (VerboseEn) { + xil_printf("Reserved for HDMI video data block\r\n"); + } + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_COLORIMETRY: + if (VerboseEn) { + xil_printf(" Colorimetry data block\r\n"); + } + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_HDR_STATIC_METADATA: + if (VerboseEn) { + xil_printf("HDR static metadata data block\r\n"); + } + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_HDR_DYNAMIC_METADATA: + if (VerboseEn) { + xil_printf(" HDR dynamic metadata data block\r\n"); + } + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_VIDEO_FRMT_PREFERENCE: + if (VerboseEn) { + xil_printf(" Video format preference data block\r\n"); + } + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_CEA_MISC_AUDIO_FIELDS: + if (VerboseEn) { + xil_printf("Reserved for CEA miscellaneous audio fields\r\n"); + } + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_VENDOR_SPECIFC_AUDIO: + if (VerboseEn) { + xil_printf(" Vendor-specific audio data block\r\n\r\n"); + } + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_HDMI_AUDIO: + if (VerboseEn) { + xil_printf(" HDMI audio data block\r\n"); + } + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_ROOM_CONFIGURATION: + if (VerboseEn) { + xil_printf(" Room configuration data block\r\n"); + } + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_SPEAKER_LOCATION: + if (VerboseEn) { + xil_printf(" Speaker location data block\r\n"); + } + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_INFOFRAME: + if (VerboseEn) { + xil_printf(" Video capability data block\r\n"); + } + break; +#endif + case XVIDC_CEA861_EXT_TAG_TYPE_YCBCR420_VIDEO: +#if XVIDC_EDID_VERBOSITY > 1 + if (VerboseEn) { + xil_printf(" YCbCr 4:2:0 video data block\r\n"); + xil_printf(" YCbCr 4:2:0.............. Supported\r\n"); + } +#endif + EdidCtrlParam->IsYCbCr420Supp = XVIDC_SUPPORTED; + +#if XVIDC_EDID_VERBOSITY > 1 + if (VerboseEn) { + xil_printf(" CE video identifiers (VICs) - " + " timing/formats supported\r\n"); + } + for (u8 i = 0; i < edb->header.length - 1; i++) { + u8 vic; + u8 native=0; + if ((edb->data[i] & 0x7F) == 0) { + continue; + } else if (((edb->data[i]) >= 1) && ((edb->data[i]) <= 64)){ + vic = (edb->data[i]) & 0x7F; + } else if (((edb->data[i]) >= 65) && ((edb->data[i]) <= 127)){ + vic = (edb->data[i]); + } else if (((edb->data[i]) >= 129) && ((edb->data[i]) <= 192)){ + vic = (edb->data[i]) & 0x7F; + native = 1; + } else if (((edb->data[i]) >= 193) && ((edb->data[i]) <= 253)){ + vic = (edb->data[i]); + } else { + continue; + } + + const struct xvidc_cea861_timing * const timing = + &xvidc_cea861_timings[vic]; + + if (VerboseEn) { + xil_printf(" %s CEA Mode %02u: %4u x %4u%c @ %dHz\r\n", + native ? "*" : " ", + vic, + timing->hactive, timing->vactive, + (timing->mode == INTERLACED) ? 'i' : 'p', + (u32)(timing->vfreq)); + } + } + if (VerboseEn) { + xil_printf("\r\n"); + } +#endif + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_YCBCR420_CAPABILITY_MAP: +#if XVIDC_EDID_VERBOSITY > 1 + if (VerboseEn) { + xil_printf(" YCbCr 4:2:0 capability map data block\r\n"); + xil_printf(" YCbCr 4:2:0.............. Supported\r\n"); + } +#endif + EdidCtrlParam->IsYCbCr420Supp = XVIDC_SUPPORTED; +#if XVIDC_EDID_VERBOSITY > 1 + for (u8 i = 0; i < edb->header.length - 1; i++) { + u8 v = edb->data[i]; + + for (u8 j = 0; j < 8; j++) { + if (v & (1 << j)) { + if (VerboseEn) { + const struct xvidc_cea861_timing * const timing = + &xvidc_cea861_timings[EdidCtrlParam->SuppCeaVIC[(i * 8) + j]]; + xil_printf(" CEA Mode %02u: %4u x %4u%c" + "@ %dHz\r\n", + EdidCtrlParam->SuppCeaVIC[(i * 8) + j], + timing->hactive, timing->vactive, + (timing->mode == INTERLACED) ? 'i' : 'p', + (u32)(timing->vfreq)); + } + } + } + } +#endif +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf("\r\n"); + } +#endif + break; + + default : +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { +#if XVIDC_EDID_VERBOSITY > 1 + xil_printf(" Not Supported: Ext Tag: %03x\r\n", + edb->xvidc_cea861_extended_tag_codes); +#endif + xil_printf("\r\n"); + } +#endif + break; + } +} +#if XVIDC_EDID_VERBOSITY > 1 +static void +xvidc_disp_cea861_video_data( + const struct xvidc_cea861_video_data_block * const vdb, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn) { + /* For Future Usage */ + EdidCtrlParam = EdidCtrlParam; + + if (VerboseEn) { + xil_printf("CE video identifiers (VICs) - timing/formats" + " supported\r\n"); + } + + for (u8 i = 0; i < vdb->header.length; i++) { + + const struct xvidc_cea861_timing * const timing = + &xvidc_cea861_timings[vdb->svd[i].video_identification_code]; + + EdidCtrlParam->SuppCeaVIC[i] = vdb->svd[i].video_identification_code; + if (VerboseEn) { + xil_printf(" %s CEA Mode %02u: %4u x %4u%c @ %dHz\r\n", + vdb->svd[i].native ? "*" : " ", + vdb->svd[i].video_identification_code, + timing->hactive, timing->vactive, + (timing->mode == INTERLACED) ? 'i' : 'p', + (u32)(timing->vfreq)); + } + } + if (VerboseEn) { + xil_printf("\r\n"); + } +} +#endif + +/*****************************************************************************/ +/** +* +* This function parse EDID on CEA 861 Vendor Specific Data +* +* @param data is a pointer to the EDID array. +* @param EdidCtrlParam is a pointer the EDID Control parameter +* @param VerboseEn is a pointer to the XV_HdmiTxSs core instance. +* +* @return None +* +* @note None. +* +******************************************************************************/ +static void +xvidc_disp_cea861_vendor_data( + const struct xvidc_cea861_vendor_specific_data_block * vsdb, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn) { + + /* During Verbosity 0, VerboseEn won't be used */ + /* To avoid compilation warnings */ + VerboseEn = VerboseEn; + + const u8 oui[] = { vsdb->ieee_registration[2], + vsdb->ieee_registration[1], + vsdb->ieee_registration[0] }; +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf("CEA vendor specific data (VSDB)\r\n"); + xil_printf(" IEEE registration number. 0x"); + for (u8 i = 0; i < ARRAY_SIZE(oui); i++) + xil_printf("%02X", oui[i]); + xil_printf("\r\n"); + } +#endif + if (!memcmp(oui, HDMI_OUI, sizeof(oui))) { + const struct xvidc_cea861_hdmi_vendor_specific_data_block * const hdmi = + (struct xvidc_cea861_hdmi_vendor_specific_data_block *) vsdb; +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf(" CEC physical address..... %u.%u.%u.%u\r\n", + hdmi->port_configuration_a, + hdmi->port_configuration_b, + hdmi->port_configuration_c, + hdmi->port_configuration_d); + } +#endif + + if (hdmi->header.length >= HDMI_VSDB_EXTENSION_FLAGS_OFFSET) { +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { +#if XVIDC_EDID_VERBOSITY > 1 + xil_printf(" Supports AI (ACP, ISRC).. %s\r\n", + hdmi->audio_info_frame ? "Yes" : "No"); +#endif + xil_printf(" Supports 48bpp........... %s\r\n", + hdmi->colour_depth_48_bit ? "Yes" : "No"); + xil_printf(" Supports 36bpp........... %s\r\n", + hdmi->colour_depth_36_bit ? "Yes" : "No"); + xil_printf(" Supports 30bpp........... %s\r\n", + hdmi->colour_depth_30_bit ? "Yes" : "No"); + xil_printf(" Supp. YUV444 Deep Color.. %s\r\n", + hdmi->yuv_444_supported ? "Yes" : "No"); +#if XVIDC_EDID_VERBOSITY > 1 + xil_printf(" Supports dual-link DVI... %s\r\n", + hdmi->dvi_dual_link ? "Yes" : "No"); +#endif + } +#endif + EdidCtrlParam->Is30bppSupp = hdmi->colour_depth_30_bit; + EdidCtrlParam->Is36bppSupp = hdmi->colour_depth_36_bit; + EdidCtrlParam->Is48bppSupp = hdmi->colour_depth_48_bit; + EdidCtrlParam->IsYCbCr444DeepColSupp = hdmi->yuv_444_supported; + } + + if (hdmi->header.length >= HDMI_VSDB_MAX_TMDS_OFFSET) { + if (hdmi->max_tmds_clock) { +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf(" Maximum TMDS clock....... %uMHz\r\n", + hdmi->max_tmds_clock * 5); + } +#endif + EdidCtrlParam->MaxTmdsMhz = (hdmi->max_tmds_clock * 5); + } else { +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf(" Maximum TMDS clock....... n/a\r\n"); + } +#endif + } + } + + if (hdmi->header.length >= HDMI_VSDB_LATENCY_FIELDS_OFFSET) { + if (hdmi->latency_fields) { +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf(" Video latency %s........ %ums\r\n", + hdmi->interlaced_latency_fields ? "(p)" : "...", + (hdmi->video_latency - 1) << 1); + xil_printf(" Audio latency %s........ %ums\r\n", + hdmi->interlaced_latency_fields ? "(p)" : "...", + (hdmi->audio_latency - 1) << 1); + } +#endif + } + + if (hdmi->interlaced_latency_fields) { +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf(" Video latency (i)........ %ums\r\n", + hdmi->interlaced_video_latency); + xil_printf(" Audio latency (i)........ %ums\r\n", + hdmi->interlaced_audio_latency); + } +#endif + } + } + } else if (!memcmp(oui, HDMI_OUI_HF, sizeof(oui))) { + const struct xvidc_cea861_hdmi_hf_vendor_specific_data_block * const hdmi = + (struct xvidc_cea861_hdmi_hf_vendor_specific_data_block *) vsdb; + +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf(" Version.................. %d\r\n",hdmi->version); + } +#endif + + if (hdmi->max_tmds_char_rate) { +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf(" Maximum TMDS clock....... %uMHz\r\n", + hdmi->max_tmds_char_rate * 5); + } +#endif + EdidCtrlParam->MaxTmdsMhz = (hdmi->max_tmds_char_rate * 5); + } else { +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf(" Max. Supp. TMDS clock (<=340MHz)\r\n"); + } +#endif + } + + if (hdmi->header.length >= HDMI_VSDB_EXTENSION_FLAGS_OFFSET) { +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { +#if XVIDC_EDID_VERBOSITY > 1 + xil_printf(" RRC Capable Support...... %s\r\n", + hdmi->rr_capable ? "Yes" : "No"); + xil_printf(" SCDC Present............. %s\r\n", + hdmi->scdc_present ? "Yes" : "No"); + xil_printf(" HDMI1.4 Scramble Support. %s\r\n", + hdmi->lte_340mcsc_scramble ? "Yes" : "No"); +#endif + xil_printf(" YUV 420 Deep.C. Support..\r\n"); + xil_printf(" Supports 48bpp......... %s\r\n", + hdmi->dc_48bit_yuv420 ? "Yes" : "No"); + xil_printf(" Supports 36bpp......... %s\r\n", + hdmi->dc_36bit_yuv420 ? "Yes" : "No"); + xil_printf(" Supports 30bpp......... %s\r\n", + hdmi->dc_30bit_yuv420 ? "Yes" : "No"); + } +#endif + EdidCtrlParam->IsYCbCr420dc30bppSupp = hdmi->dc_30bit_yuv420; + EdidCtrlParam->IsYCbCr420dc36bppSupp = hdmi->dc_36bit_yuv420; + EdidCtrlParam->IsYCbCr420dc48bppSupp = hdmi->dc_48bit_yuv420; + EdidCtrlParam->IsSCDCReadRequestReady = hdmi->rr_capable; + EdidCtrlParam->IsSCDCPresent = hdmi->scdc_present; + } + } +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf("\r\n"); + } +#endif +} + +#if XVIDC_EDID_VERBOSITY > 1 +/*****************************************************************************/ +/** +* +* This function parse EDID on CEA 861 Speaker Allocation +* +* @param data is a pointer to the EDID array. +* @param EdidCtrlParam is a pointer the EDID Control parameter +* @param VerboseEn is a pointer to the XV_HdmiTxSs core instance. +* +* @return None +* +* @note None. +* +******************************************************************************/ +static void +xvidc_disp_cea861_speaker_allocation_data( + const struct xvidc_cea861_speaker_allocation_data_block * const sadb, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn) { + /* For Future Usage */ + EdidCtrlParam = EdidCtrlParam; + + const struct xvidc_cea861_speaker_allocation * const sa = &sadb->payload; + const u8 * const channel_configuration = (u8 *) sa; + + if (VerboseEn) { + xil_printf("CEA speaker allocation data\r\n"); + xil_printf(" Channel configuration.... %u.%u\r\n", + (__builtin_popcountll(channel_configuration[0] & 0xe9) << 1) + + (__builtin_popcountll(channel_configuration[0] & 0x14) << 0) + + (__builtin_popcountll(channel_configuration[1] & 0x01) << 1) + + (__builtin_popcountll(channel_configuration[1] & 0x06) << 0), + (channel_configuration[0] & 0x02)); + xil_printf(" Front left/right......... %s\r\n", + sa->front_left_right ? "Yes" : "No"); + xil_printf(" Front LFE................ %s\r\n", + sa->front_lfe ? "Yes" : "No"); + xil_printf(" Front center............. %s\r\n", + sa->front_center ? "Yes" : "No"); + xil_printf(" Rear left/right.......... %s\r\n", + sa->rear_left_right ? "Yes" : "No"); + xil_printf(" Rear center.............. %s\r\n", + sa->rear_center ? "Yes" : "No"); + xil_printf(" Front left/right center.. %s\r\n", + sa->front_left_right_center ? "Yes" : "No"); + xil_printf(" Rear left/right center... %s\r\n", + sa->rear_left_right_center ? "Yes" : "No"); + xil_printf(" Front left/right wide.... %s\r\n", + sa->front_left_right_wide ? "Yes" : "No"); + xil_printf(" Front left/right high.... %s\r\n", + sa->front_left_right_high ? "Yes" : "No"); + xil_printf(" Top center............... %s\r\n", + sa->top_center ? "Yes" : "No"); + xil_printf(" Front center high........ %s\r\n", + sa->front_center_high ? "Yes" : "No"); + + xil_printf("\r\n"); + } + +} +#endif + +/*****************************************************************************/ +/** +* +* This function Parse and Display the CEA-861 +* +* @param data is a pointer to the EDID array. +* @param EdidCtrlParam is a pointer the EDID Control parameter +* @param VerboseEn is a pointer to the XV_HdmiTxSs core instance. +* +* @return None +* +* @note None. +* +******************************************************************************/ +static void +xvidc_disp_cea861(const struct xvidc_edid_extension * const ext, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn) { + + const struct xvidc_cea861_timing_block * const ctb = + (struct xvidc_cea861_timing_block *) ext; + const u8 offset = offsetof(struct xvidc_cea861_timing_block, data); + u8 index = 0; + +#if XVIDC_EDID_VERBOSITY > 1 + const struct xvidc_edid_detailed_timing_descriptor *dtd = NULL; + u8 i; + + XV_VidC_TimingParam timing_params; +#endif + +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + + xil_printf("CEA-861 Information\r\n"); + xil_printf(" Revision number.......... %u\r\n", + ctb->revision); + } +#endif + + if (ctb->revision >= 2) { +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { +#if XVIDC_EDID_VERBOSITY > 1 + xil_printf(" IT underscan............. %supported\r\n", + ctb->underscan_supported ? "S" : "Not s"); +#endif + xil_printf(" Basic audio.............. %supported\r\n", + ctb->basic_audio_supported ? "S" : "Not s"); + xil_printf(" YCbCr 4:4:4.............. %supported\r\n", + ctb->yuv_444_supported ? "S" : "Not s"); + xil_printf(" YCbCr 4:2:2.............. %supported\r\n", + ctb->yuv_422_supported ? "S" : "Not s"); +#if XVIDC_EDID_VERBOSITY > 1 + xil_printf(" Native formats........... %u\r\n", + ctb->native_dtds); +#endif + } +#endif + EdidCtrlParam->IsYCbCr444Supp = ctb->yuv_444_supported; + EdidCtrlParam->IsYCbCr422Supp = ctb->yuv_422_supported; + } + +#if XVIDC_EDID_VERBOSITY > 1 + dtd = (struct xvidc_edid_detailed_timing_descriptor *) + ((u8 *) ctb + ctb->dtd_offset); + for (i = 0; dtd->pixel_clock; i++, dtd++) { + + timing_params = XV_VidC_timing(dtd); + if (VerboseEn) { + xil_printf(" Detailed timing #%u....... %ux%u%c at %uHz " + "(%u:%u)\r\n", + i + 1, + timing_params.hres, + timing_params.vres, + timing_params.vidfrmt ? 'i' : 'p', + timing_params.vfreq, + timing_params.aspect_ratio.width, + timing_params.aspect_ratio.height); + + xil_printf( + " Modeline............... \"%ux%u\" %u %u %u %u %u %u %u %u %u" + " %chsync %cvsync\r\n", + timing_params.hres, + timing_params.vres, + HZ_2_MHZ (timing_params.pixclk), + (timing_params.hres), + (timing_params.hres + timing_params.hfp), + (timing_params.hres + timing_params.hfp + + timing_params.hsync_width), + (timing_params.htotal), + (timing_params.vres), + (timing_params.vres + timing_params.vfp), + (timing_params.vres + timing_params.vfp + + timing_params.vsync_width), + (timing_params.vtotal), + timing_params.hsync_polarity ? '+' : '-', + timing_params.vsync_polarity ? '+' : '-'); + } + } +#endif +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf("\r\n"); + } +#endif + + if (ctb->revision >= 3) { + do { + const struct xvidc_cea861_data_block_header * const header = + (struct xvidc_cea861_data_block_header *) &ctb->data[index]; + + switch (header->tag) { + + case XVIDC_CEA861_DATA_BLOCK_TYPE_AUDIO: + { +#if XVIDC_EDID_VERBOSITY > 1 + const struct xvidc_cea861_audio_data_block * const db = + (struct xvidc_cea861_audio_data_block *) header; + + xvidc_disp_cea861_audio_data(db,EdidCtrlParam,VerboseEn); +#endif + } + break; + + case XVIDC_CEA861_DATA_BLOCK_TYPE_VIDEO: + { +#if XVIDC_EDID_VERBOSITY > 1 + const struct xvidc_cea861_video_data_block * const db = + (struct xvidc_cea861_video_data_block *) header; + + xvidc_disp_cea861_video_data(db,EdidCtrlParam,VerboseEn); +#endif + } + break; + + case XVIDC_CEA861_DATA_BLOCK_TYPE_VENDOR_SPECIFIC: + { + const struct + xvidc_cea861_vendor_specific_data_block * const db = + (struct xvidc_cea861_vendor_specific_data_block *) header; + + xvidc_disp_cea861_vendor_data(db,EdidCtrlParam,VerboseEn); + } + break; + + case XVIDC_CEA861_DATA_BLOCK_TYPE_SPEAKER_ALLOCATION: + { +#if XVIDC_EDID_VERBOSITY > 1 + const struct + xvidc_cea861_speaker_allocation_data_block * const db = + (struct xvidc_cea861_speaker_allocation_data_block *) header; + + xvidc_disp_cea861_speaker_allocation_data(db, + EdidCtrlParam,VerboseEn); +#endif + } + break; + + case XVIDC_CEA861_DATA_BLOCK_TYPE_EXTENDED: + { + const struct xvidc_cea861_extended_data_block * const db = + (struct xvidc_cea861_extended_data_block *) header; + + xvidc_disp_cea861_extended_data(db,EdidCtrlParam,VerboseEn); + } + break; + + default: +#if XVIDC_EDID_VERBOSITY > 1 + if (VerboseEn) { + xil_printf("Unknown CEA-861 data block type 0x%02x\r\n", + header->tag); + } +#endif + break; + } + + index = index + header->length + sizeof(*header); + } while (index < ctb->dtd_offset - offset); + } +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf("\r\n"); + } +#endif +} + + +/*****************************************************************************/ +/** +* +* This structure parse parse EDID routines +* +* +* @note None. +* +******************************************************************************/ +static const struct xvidc_edid_extension_handler { + void (* const inf_disp)(const struct xvidc_edid_extension * const, + XV_VidC_EdidCntrlParam *EdidCtrlParam, XV_VidC_Verbose VerboseEn); +} xvidc_edid_extension_handlers[] = { + [XVIDC_EDID_EXTENSION_CEA] = { xvidc_disp_cea861 }, +}; + + +/*****************************************************************************/ +/** +* +* This function parse and print the EDID of the Sink +* +* @param data is a pointer to the EDID array. +* @param EdidCtrlParam is a pointer the EDID Control parameter +* @param VerboseEn is a pointer to the XV_HdmiTxSs core instance. +* +* @return None +* +* @note None. +* +******************************************************************************/ +void +XV_VidC_parse_edid(const u8 * const data, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn) { + const struct edid * const edid = (struct edid *) data; + const struct xvidc_edid_extension * const extensions = + (struct xvidc_edid_extension *) (data + sizeof(*edid)); + + XV_VidC_EdidCtrlParamInit(EdidCtrlParam); + + xvidc_disp_edid1(edid,EdidCtrlParam,VerboseEn); + + for (u8 i = 0; i < edid->extensions; i++) { + const struct xvidc_edid_extension * const extension = &extensions[i]; + const struct xvidc_edid_extension_handler * const handler = + &xvidc_edid_extension_handlers[extension->tag]; + + if (!handler) { +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf("WARNING: block %u contains unknown extension " + " (%#04x)\r\n", i, extensions[i].tag); + } +#endif + continue; + } + + if (handler->inf_disp) { + (*handler->inf_disp)(extension,EdidCtrlParam,VerboseEn); + } + } +}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc_timings_table.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc_timings_table.c new file mode 100644 index 0000000..ee1cb4f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc_timings_table.c
@@ -0,0 +1,534 @@ +/******************************************************************************* + * + * Copyright (C) 2017 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xvidc_timings_table.c + * @addtogroup video_common_v4_2 + * @{ + * + * Contains video timings for various standard resolutions. + * + * @note None. + * + * <pre> + * MODIFICATION HISTORY: + * + * Ver Who Date Changes + * ----- ---- -------- ----------------------------------------------- + * 1.0 als, 01/10/15 Initial release. + * rc + * 2.0 als 08/14/15 Added new video timings. + * 2.1 als 11/04/15 Fixed video timings for some resolutions. + * rco 02/09/17 Fix c++ compilation warnings + * 4.2 jsr 07/08/17 Added new video timings for SDI supported resolutions + * aad 07/10/17 Add XVIDC_VM_3840x2160_60_P_RB video format + * aad 09/05/17 Fixed timings for 1366x768_60_P + * aad 09/05/17 Added 1366x768_60_P_RB + * </pre> + * +*******************************************************************************/ + +/******************************* Include Files ********************************/ + +#include "xvidc.h" + +/**************************** Variable Definitions ****************************/ + +/** + * This table contains the main stream attributes for various standard + * resolutions. Each entry is of the format: + * 1) ID: XVIDC_VM_<HRES>x<VRES>_<FRAME RATE (HZ)>_<P|I>(_RB = Reduced Blanking) + * 2) Resolution naming: "<HRES>x<VRES>@<FRAME RATE (HZ)>" + * 3) Frame rate: XVIDC_FR_<FRAME RATE (HZ)> + * 4) Video timing structure: + * 1) Horizontal active resolution (pixels) + * 2) Horizontal front porch (pixels) + * 3) Horizontal sync width (pixels) + * 4) Horizontal back porch (pixels) + * 5) Horizontal total (pixels) + * 6) Horizontal sync polarity (0=negative|1=positive) + * 7) Vertical active resolution (lines) + * 8) Frame 0: Vertical front porch (lines) + * 9) Frame 0: Vertical sync width (lines) + * 10) Frame 0: Vertical back porch (lines) + * 11) Frame 0: Vertical total (lines) + * 12) Frame 1: Vertical front porch (lines) + * 13) Frame 1: Vertical sync width (lines) + * 14) Frame 1: Vertical back porch (lines) + * 15) Frame 1: Vertical total (lines) + * 16) Vertical sync polarity (0=negative|1=positive) + */ +#ifdef __cplusplus +extern "C" +#endif +const XVidC_VideoTimingMode XVidC_VideoTimingModes[XVIDC_VM_NUM_SUPPORTED] = +{ + /* Interlaced modes. */ + { XVIDC_VM_720x480_60_I, "720x480@60Hz (I)", XVIDC_FR_60HZ, + {720, 19, 62, 57, 858, 0, + 240, 4, 3, 15, 262, 5, 3, 15, 263, 0} }, + { XVIDC_VM_720x576_50_I, "720x576@50Hz (I)", XVIDC_FR_50HZ, + {720, 12, 63, 69, 864, 0, + 288, 2, 3, 19, 312, 3, 3, 19, 313, 0} }, + { XVIDC_VM_1440x480_60_I, "1440x480@60Hz (I)", XVIDC_FR_60HZ, + {1440, 38, 124, 114, 1716, 0, + 240, 4, 3, 15, 262, 5, 3, 15, 263, 0} }, + { XVIDC_VM_1440x576_50_I, "1440x576@50Hz (I)", XVIDC_FR_50HZ, + {1440, 24, 126, 138, 1728, 0, + 288, 2, 3, 19, 312, 3, 3, 19, 313, 0} }, + { XVIDC_VM_1920x1080_48_I, "1920x1080@48Hz (I)", XVIDC_FR_48HZ, + {1920, 371, 88, 371, 2750, 1, + 540, 2, 5, 15, 562, 3, 5, 15, 563, 1} }, + { XVIDC_VM_1920x1080_50_I, "1920x1080@50Hz (I)", XVIDC_FR_50HZ, + {1920, 528, 44, 148, 2640, 1, + 540, 2, 5, 15, 562, 3, 5, 15, 563, 1} }, + { XVIDC_VM_1920x1080_60_I, "1920x1080@60Hz (I)", XVIDC_FR_60HZ, + {1920, 88, 44, 148, 2200, 1, + 540, 2, 5, 15, 562, 3, 5, 15, 563, 1} }, + { XVIDC_VM_1920x1080_96_I, "1920x1080@96Hz (I)", XVIDC_FR_96HZ, + {1920, 371, 88, 371, 2750, 1, + 1080, 4, 10, 30, 1124, 6, 10, 30, 1126, 1} }, + { XVIDC_VM_1920x1080_100_I, "1920x1080@100Hz (I)", XVIDC_FR_100HZ, + {1920, 528, 44, 148, 2640, 1, + 1080, 4, 10, 30, 1124, 6, 10, 30, 1126, 1} }, + { XVIDC_VM_1920x1080_120_I, "1920x1080@120Hz (I)", XVIDC_FR_120HZ, + {1920, 88, 44, 148, 2200, 1, + 1080, 4, 10, 30, 1124, 6, 10, 30, 1126, 1} }, + { XVIDC_VM_2048x1080_48_I, "2048x1080@48Hz (I)", XVIDC_FR_48HZ, + {2048, 329, 44, 329, 2750, 1, + 540, 2, 5, 15, 562, 3, 5, 15, 563, 1} }, + { XVIDC_VM_2048x1080_50_I, "2048x1080@50Hz (I)", XVIDC_FR_50HZ, + {2048, 274, 44, 274, 2640, 1, + 540, 2, 5, 15, 562, 3, 5, 15, 563, 1} }, + { XVIDC_VM_2048x1080_60_I, "2048x1080@60Hz (I)", XVIDC_FR_60HZ, + {2048, 66, 20, 66, 2200, 1, + 540, 2, 5, 15, 562, 3, 5, 15, 563, 1} }, + { XVIDC_VM_2048x1080_96_I, "2048x1080@96Hz (I)", XVIDC_FR_96HZ, + {2048, 329, 44, 329, 2750, 1, + 1080, 4, 10, 30, 1124, 6, 10, 30, 1126, 1} }, + { XVIDC_VM_2048x1080_100_I, "2048x1080@100Hz (I)", XVIDC_FR_100HZ, + {2048, 274, 44, 274, 2640, 1, + 1080, 4, 10, 30, 1124, 6, 10, 30, 1126, 1} }, + { XVIDC_VM_2048x1080_120_I, "2048x1080@120Hz (I)", XVIDC_FR_120HZ, + {2048, 66, 20, 66, 2200, 1, + 1080, 4, 10, 30, 1124, 6, 10, 30, 1126, 1} }, + + + /* Progressive modes. */ + { XVIDC_VM_640x350_85_P, "640x350@85Hz", XVIDC_FR_85HZ, + {640, 32, 64, 96, 832, 1, + 350, 32, 3, 60, 445, 0, 0, 0, 0, 0} }, + { XVIDC_VM_640x480_60_P, "640x480@60Hz", XVIDC_FR_60HZ, + {640, 8+8, 96, 40+8, 800, 0, + 480, 2+8, 2, 25+8, 525, 0, 0, 0, 0, 0} }, + { XVIDC_VM_640x480_72_P, "640x480@72Hz", XVIDC_FR_72HZ, + {640, 8+16, 40, 120+8, 832, 0, + 480, 8+1, 3, 20+8, 520, 0, 0, 0, 0, 0} }, + { XVIDC_VM_640x480_75_P, "640x480@75Hz", XVIDC_FR_75HZ, + {640, 16, 64, 120, 840, 0, + 480, 1, 3, 16, 500, 0, 0, 0, 0, 0} }, + { XVIDC_VM_640x480_85_P, "640x480@85Hz", XVIDC_FR_85HZ, + {640, 56, 56, 80, 832, 0, + 480, 1, 3, 25, 509, 0, 0, 0, 0, 0} }, + { XVIDC_VM_720x400_85_P, "720x400@85Hz", XVIDC_FR_85HZ, + {720, 36, 72, 108, 936, 0, + 400, 1, 3, 42, 446, 0, 0, 0, 0, 1} }, + { XVIDC_VM_720x480_60_P, "720x480@60Hz", XVIDC_FR_60HZ, + {720, 16, 62, 60, 858, 0, + 480, 9, 6, 30, 525, 0, 0, 0, 0, 0} }, + { XVIDC_VM_720x576_50_P, "720x576@50Hz", XVIDC_FR_50HZ, + {720, 12, 64, 68, 864, 0, + 576, 5, 5, 39, 625, 0, 0, 0, 0, 0} }, + { XVIDC_VM_800x600_56_P, "800x600@56Hz", XVIDC_FR_56HZ, + {800, 24, 72, 128, 1024, 1, + 600, 1, 2, 22, 625, 0, 0, 0, 0, 1} }, + { XVIDC_VM_800x600_60_P, "800x600@60Hz", XVIDC_FR_60HZ, + {800, 40, 128, 88, 1056, 1, + 600, 1, 4, 23, 628, 0, 0, 0, 0, 1} }, + { XVIDC_VM_800x600_72_P, "800x600@72Hz", XVIDC_FR_72HZ, + {800, 56, 120, 64, 1040, 1, + 600, 37, 6, 23, 666, 0, 0, 0, 0, 1} }, + { XVIDC_VM_800x600_75_P, "800x600@75Hz", XVIDC_FR_75HZ, + {800, 16, 80, 160, 1056, 1, + 600, 1, 3, 21, 625, 0, 0, 0, 0, 1} }, + { XVIDC_VM_800x600_85_P, "800x600@85Hz", XVIDC_FR_85HZ, + {800, 32, 64, 152, 1048, 1, + 600, 1, 3, 27, 631, 0, 0, 0, 0, 1} }, + { XVIDC_VM_800x600_120_P_RB, "800x600@120Hz (RB)", XVIDC_FR_120HZ, + {800, 48, 32, 80, 960, 1, + 600, 3, 4, 29, 636, 0, 0, 0, 0, 0} }, + { XVIDC_VM_848x480_60_P, "848x480@60Hz", XVIDC_FR_60HZ, + {848, 16, 112, 112, 1088, 1, + 480, 6, 8, 23, 517, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1024x768_60_P, "1024x768@60Hz", XVIDC_FR_60HZ, + {1024, 24, 136, 160, 1344, 0, + 768, 3, 6, 29, 806, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1024x768_70_P, "1024x768@70Hz", XVIDC_FR_70HZ, + {1024, 24, 136, 144, 1328, 0, + 768, 3, 6, 29, 806, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1024x768_75_P, "1024x768@75Hz", XVIDC_FR_75HZ, + {1024, 16, 96, 176, 1312, 1, + 768, 1, 3, 28, 800, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1024x768_85_P, "1024x768@85Hz", XVIDC_FR_85HZ, + {1024, 48, 96, 208, 1376, 1, + 768, 1, 3, 36, 808, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1024x768_120_P_RB, "1024x768@120Hz (RB)", XVIDC_FR_120HZ, + {1024, 48, 32, 80, 1184, 1, + 768, 3, 4, 38, 813, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1152x864_75_P, "1152x864@75Hz", XVIDC_FR_75HZ, + {1152, 64, 128, 256, 1600, 1, + 864, 1, 3, 32, 900, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x720_24_P, "1280x720@24Hz", XVIDC_FR_24HZ, + {1280, 970, 905, 970, 4125, 1, + 720, 5, 5, 20, 750, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x720_25_P, "1280x720@25Hz", XVIDC_FR_25HZ, + {1280, 970, 740, 970, 3960, 1, + 720, 5, 5, 20, 750, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x720_30_P, "1280x720@30Hz", XVIDC_FR_30HZ, + {1280, 970, 80, 970, 3300, 1, + 720, 5, 5, 20, 750, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x720_50_P, "1280x720@50Hz", XVIDC_FR_50HZ, + {1280, 440, 40, 220, 1980, 1, + 720, 5, 5, 20, 750, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x720_60_P, "1280x720@60Hz", XVIDC_FR_60HZ, + {1280, 110, 40, 220, 1650, 1, + 720, 5, 5, 20, 750, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x768_60_P, "1280x768@60Hz", XVIDC_FR_60HZ, + {1280, 64, 128, 192, 1664, 0, + 768, 3, 7, 20, 798, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x768_60_P_RB, "1280x768@60Hz (RB)", XVIDC_FR_60HZ, + {1280, 48, 32, 80, 1440, 1, + 768, 3, 7, 12, 790, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1280x768_75_P, "1280x768@75Hz", XVIDC_FR_75HZ, + {1280, 80, 128, 208, 1696, 0, + 768, 3, 7, 27, 805, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x768_85_P, "1280x768@85Hz", XVIDC_FR_85HZ, + {1280, 80, 136, 216, 1712, 0, + 768, 3, 7, 31, 809, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x768_120_P_RB, "1280x768@120Hz (RB)", XVIDC_FR_120HZ, + {1280, 48, 32, 80, 1440, 1, + 768, 3, 7, 35, 813, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1280x800_60_P, "1280x800@60Hz", XVIDC_FR_60HZ, + {1280, 72, 128, 200, 1680, 0, + 800, 3, 6, 22, 831, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x800_60_P_RB, "1280x800@60Hz (RB)", XVIDC_FR_60HZ, + {1280, 48, 32, 80, 1440, 1, + 800, 3, 6, 14, 823, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1280x800_75_P, "1280x800@75Hz", XVIDC_FR_75HZ, + {1280, 80, 128, 208, 1696, 0, + 800, 3, 6, 29, 838, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x800_85_P, "1280x800@85Hz", XVIDC_FR_85HZ, + {1280, 80, 136, 216, 1712, 0, + 800, 3, 6, 34, 843, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x800_120_P_RB, "1280x800@120Hz (RB)", XVIDC_FR_120HZ, + {1280, 48, 32, 80, 1440, 1, + 800, 3, 6, 38, 847, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1280x960_60_P, "1280x960@60Hz", XVIDC_FR_60HZ, + {1280, 96, 112, 312, 1800, 1, + 960, 1, 3, 36, 1000, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x960_85_P, "1280x960@85Hz", XVIDC_FR_85HZ, + {1280, 64, 160, 224, 1728, 1, + 960, 1, 3, 47, 1011, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x960_120_P_RB, "1280x960@120Hz (RB)", XVIDC_FR_120HZ, + {1280, 48, 32, 80, 1440, 1, + 960, 3, 4, 50, 1017, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1280x1024_60_P, "1280x1024@60Hz", XVIDC_FR_60HZ, + {1280, 48, 112, 248, 1688, 1, + 1024, 1, 3, 38, 1066, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x1024_75_P, "1280x1024@75Hz", XVIDC_FR_75HZ, + {1280, 16, 144, 248, 1688, 1, + 1024, 1, 3, 38, 1066, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x1024_85_P, "1280x1024@85Hz", XVIDC_FR_85HZ, + {1280, 64, 160, 224, 1728, 1, + 1024, 1, 3, 44, 1072, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x1024_120_P_RB, "1280x1024@120Hz (RB)", XVIDC_FR_120HZ, + {1280, 48, 32, 80, 1440, 1, + 1024, 3, 7, 50, 1084, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1360x768_60_P, "1360x768@60Hz", XVIDC_FR_60HZ, + {1360, 64, 112, 256, 1792, 1, + 768, 3, 6, 18, 795, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1360x768_120_P_RB, "1360x768@120Hz (RB)", XVIDC_FR_120HZ, + {1360, 48, 32, 80, 1520, 1, + 768, 3, 5, 37, 813, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1366x768_60_P, "1366x768@60Hz", XVIDC_FR_60HZ, + {1366, 70, 143, 213, 1792, 1, + 768, 3, 3, 24, 798, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1366x768_60_P_RB, "1366x768@60Hz (RB)", XVIDC_FR_60HZ, + {1366, 14, 56, 64, 1500, 1, + 768, 1, 3, 28, 800, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1400x1050_60_P, "1400x1050@60Hz", XVIDC_FR_60HZ, + {1400, 88, 144, 232, 1864, 0, + 1050, 3, 4, 32, 1089, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1400x1050_60_P_RB, "1400x1050@60Hz (RB)", XVIDC_FR_60HZ, + {1400, 48, 32, 80, 1560, 1, + 1050, 3, 4, 23, 1080, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1400x1050_75_P, "1400x1050@75Hz", XVIDC_FR_75HZ, + {1400, 104, 144, 248, 1896, 0, + 1050, 3, 4, 42, 1099, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1400x1050_85_P, "1400x1050@85Hz", XVIDC_FR_85HZ, + {1400, 104, 152, 256, 1912, 0, + 1050, 3, 4, 48, 1105, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1400x1050_120_P_RB, "1400x1050@120Hz (RB)", XVIDC_FR_120HZ, + {1400, 48, 32, 80, 1560, 1, + 1050, 3, 4, 55, 1112, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1440x240_60_P, "1440x240@60Hz", XVIDC_FR_60HZ, + {1440, 38, 124, 114, 1716, 0, + 240, 14, 3, 4, 262, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1440x900_60_P, "1440x900@60Hz", XVIDC_FR_60HZ, + {1440, 80, 152, 232, 1904, 0, + 900, 3, 6, 25, 934, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1440x900_60_P_RB, "1440x900@60Hz (RB)", XVIDC_FR_60HZ, + {1440, 48, 32, 80, 1600, 1, + 900, 3, 6, 17, 926, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1440x900_75_P, "1440x900@75Hz", XVIDC_FR_75HZ, + {1440, 96, 152, 248, 1936, 0, + 900, 3, 6, 33, 942, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1440x900_85_P, "1440x900@85Hz", XVIDC_FR_85HZ, + {1440, 104, 152, 256, 1952, 0, + 900, 3, 6, 39, 948, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1440x900_120_P_RB, "1440x900@120Hz (RB)", XVIDC_FR_120HZ, + {1440, 48, 32, 80, 1600, 1, + 900, 3, 6, 44, 953, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1600x1200_60_P, "1600x1200@60Hz", XVIDC_FR_60HZ, + {1600, 64, 192, 304, 2160, 1, + 1200, 1, 3, 46, 1250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1600x1200_65_P, "1600x1200@65Hz", XVIDC_FR_65HZ, + {1600, 64, 192, 304, 2160, 1, + 1200, 1, 3, 46, 1250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1600x1200_70_P, "1600x1200@70Hz", XVIDC_FR_70HZ, + {1600, 64, 192, 304, 2160, 1, + 1200, 1, 3, 46, 1250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1600x1200_75_P, "1600x1200@75Hz", XVIDC_FR_75HZ, + {1600, 64, 192, 304, 2160, 1, + 1200, 1, 3, 46, 1250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1600x1200_85_P, "1600x1200@85Hz", XVIDC_FR_85HZ, + {1600, 64, 192, 304, 2160, 1, + 1200, 1, 3, 46, 1250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1600x1200_120_P_RB, "1600x1200@120Hz (RB)", XVIDC_FR_120HZ, + {1600, 48, 32, 80, 1760, 1, + 1200, 3, 4, 64, 1271, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1680x720_50_P, "1680x720@50Hz", XVIDC_FR_50HZ, + {1680, 260, 40, 220, 2200, 1, + 720, 5, 5, 20, 750, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1680x720_60_P, "1680x720@60Hz", XVIDC_FR_60HZ, + {1680, 260, 40, 220, 2200, 1, + 720, 5, 5, 20, 750, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1680x720_100_P, "1680x720@100Hz", XVIDC_FR_100HZ, + {1680, 60, 40, 220, 2000, 1, + 720, 5, 5, 95, 825, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1680x720_120_P, "1680x720@120Hz", XVIDC_FR_120HZ, + {1680, 60, 40, 220, 2000, 1, + 720, 5, 5, 95, 825, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1680x1050_50_P, "1680x1050@50Hz", XVIDC_FR_50HZ, + {1680, 88, 176, 264, 2208, 0, + 1050, 3, 6, 24, 1083, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1680x1050_60_P, "1680x1050@60Hz", XVIDC_FR_60HZ, + {1680, 104, 176, 280, 2240, 0, + 1050, 3, 6, 30, 1089, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1680x1050_60_P_RB, "1680x1050@60Hz (RB)", XVIDC_FR_60HZ, + {1680, 48, 32, 80, 1840, 1, + 1050, 3, 6, 21, 1080, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1680x1050_75_P, "1680x1050@75Hz", XVIDC_FR_75HZ, + {1680, 120, 176, 296, 2272, 0, + 1050, 3, 6, 40, 1099, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1680x1050_85_P, "1680x1050@85Hz", XVIDC_FR_85HZ, + {1680, 128, 176, 304, 2288, 0, + 1050, 3, 6, 46, 1105, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1680x1050_120_P_RB, "1680x1050@120Hz (RB)", XVIDC_FR_120HZ, + {1680, 48, 32, 80, 1840, 1, + 1050, 3, 6, 53, 1112, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1792x1344_60_P, "1792x1344@60Hz", XVIDC_FR_60HZ, + {1792, 128, 200, 328, 2448, 0, + 1344, 1, 3, 46, 1394, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1792x1344_75_P, "1792x1344@75Hz", XVIDC_FR_75HZ, + {1792, 96, 216, 352, 2456, 0, + 1344, 1, 3, 69, 1417, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1792x1344_120_P_RB, "1792x1344@120Hz (RB)", XVIDC_FR_120HZ, + {1792, 48, 32, 80, 1952, 1, + 1344, 3, 4, 72, 1423, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1856x1392_60_P, "1856x1392@60Hz", XVIDC_FR_60HZ, + {1856, 96, 224, 352, 2528, 0, + 1392, 1, 3, 43, 1439, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1856x1392_75_P, "1856x1392@75Hz", XVIDC_FR_75HZ, + {1856, 128, 224, 352, 2560, 0, + 1392, 1, 3, 104, 1500, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1856x1392_120_P_RB, "1856x1392@120Hz (RB)", XVIDC_FR_120HZ, + {1856, 48, 32, 80, 2016, 1, + 1392, 3, 4, 75, 1474, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1920x1080_24_P, "1920x1080@24Hz", XVIDC_FR_24HZ, + {1920, 638, 44, 148, 2750, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1920x1080_25_P, "1920x1080@25Hz", XVIDC_FR_25HZ, + {1920, 528, 44, 148, 2640, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1920x1080_30_P, "1920x1080@30Hz", XVIDC_FR_30HZ, + {1920, 88, 44, 148, 2200, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1920x1080_48_P, "1920x1080@48Hz", XVIDC_FR_48HZ, + {1920, 638, 44, 148, 2750, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1920x1080_50_P, "1920x1080@50Hz", XVIDC_FR_50HZ, + {1920, 528, 44, 148, 2640, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1920x1080_60_P, "1920x1080@60Hz", XVIDC_FR_60HZ, + {1920, 88, 44, 148, 2200, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1920x1080_100_P, "1920x1080@100Hz", XVIDC_FR_100HZ, + {1920, 528, 44, 148, 2640, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1920x1080_120_P, "1920x1080@120Hz", XVIDC_FR_120HZ, + {1920, 88, 44, 148, 2200, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1920x1200_60_P, "1920x1200@60Hz", XVIDC_FR_60HZ, + {1920, 136, 200, 336, 2592, 0, + 1200, 3, 6, 36, 1245, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1920x1200_60_P_RB, "1920x1200@60Hz (RB)", XVIDC_FR_60HZ, + {1920, 48, 32, 80, 2080, 1, + 1200, 3, 6, 26, 1235, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1920x1200_75_P, "1920x1200@75Hz", XVIDC_FR_75HZ, + {1920, 136, 208, 344, 2608, 0, + 1200, 3, 6, 46, 1255, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1920x1200_85_P, "1920x1200@85Hz", XVIDC_FR_85HZ, + {1920, 144, 208, 352, 2624, 0, + 1200, 3, 6, 53, 1262, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1920x1200_120_P_RB, "1920x1200@120Hz (RB)", XVIDC_FR_120HZ, + {1920, 48, 32, 80, 2080, 1, + 1200, 3, 6, 62, 1271, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1920x1440_60_P, "1920x1440@60Hz", XVIDC_FR_60HZ, + {1920, 128, 208, 344, 2600, 0, + 1440, 1, 3, 56, 1500, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1920x1440_75_P, "1920x1440@75Hz", XVIDC_FR_75HZ, + {1920, 144, 224, 352, 2640, 0, + 1440, 1, 3, 56, 1500, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1920x1440_120_P_RB, "1920x1440@120Hz (RB)", XVIDC_FR_120HZ, + {1920, 48, 32, 80, 2080, 1, + 1440, 3, 4, 78, 1525, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1920x2160_60_P, "1920x2160@60Hz", XVIDC_FR_60HZ, + {1920, 88, 44, 148, 2200, 1, + 2160, 20, 10, 60, 2250, 0, 0, 0, 0, 0} }, + { XVIDC_VM_2048x1080_24_P, "2048x1080@24Hz", XVIDC_FR_24HZ, + {2048, 510, 44, 148, 2750, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2048x1080_25_P, "2048x1080@25Hz", XVIDC_FR_25HZ, + {2048, 400, 44, 148, 2640, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2048x1080_30_P, "2048x1080@30Hz", XVIDC_FR_30HZ, + {2048, 66, 20, 66, 2200, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2048x1080_48_P, "2048x1080@48Hz", XVIDC_FR_48HZ, + {2048, 510, 44, 148, 2750, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2048x1080_50_P, "2048x1080@50Hz", XVIDC_FR_50HZ, + {2048, 400, 44, 148, 2640, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2048x1080_60_P, "2048x1080@60Hz", XVIDC_FR_60HZ, + {2048, 88, 44, 20, 2200, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2048x1080_100_P, "2048x1080@100Hz", XVIDC_FR_100HZ, + {2048, 528, 44, 148, 2640, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2048x1080_120_P, "2048x1080@120Hz", XVIDC_FR_120HZ, + {2048, 88, 44, 148, 2200, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2560x1080_50_P, "2560x1080@50Hz", XVIDC_FR_50HZ, + {2560, 548, 44, 148, 3300, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2560x1080_60_P, "2560x1080@60Hz", XVIDC_FR_60HZ, + {2560, 248, 44, 148, 3000, 1, + 1080, 4, 5, 11, 1100, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2560x1080_100_P, "2560x1080@100Hz", XVIDC_FR_100HZ, + {2560, 218, 44, 148, 2970, 1, + 1080, 4, 5, 161, 1250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2560x1080_120_P, "2560x1080@120Hz", XVIDC_FR_120HZ, + {2560, 548, 44, 148, 3300, 1, + 1080, 4, 5, 161, 1250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2560x1600_60_P, "2560x1600@60Hz", XVIDC_FR_60HZ, + {2560, 192, 280, 472, 3504, 0, + 1600, 3, 6, 49, 1658, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2560x1600_60_P_RB, "2560x1600@60Hz (RB)", XVIDC_FR_60HZ, + {2560, 48, 32, 80, 2720, 1, + 1600, 3, 6, 37, 1646, 0, 0, 0, 0, 0} }, + { XVIDC_VM_2560x1600_75_P, "2560x1600@75Hz", XVIDC_FR_75HZ, + {2560, 208, 280, 488, 3536, 0, + 1600, 3, 6, 63, 1672, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2560x1600_85_P, "2560x1600@85Hz", XVIDC_FR_85HZ, + {2560, 208, 280, 488, 3536, 0, + 1600, 3, 6, 73, 1682, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2560x1600_120_P_RB, "2560x1600@120Hz (RB)", XVIDC_FR_120HZ, + {2560, 48, 32, 80, 2720, 1, + 1600, 3, 6, 85, 1694, 0, 0, 0, 0, 0} }, + { XVIDC_VM_3840x2160_24_P, "3840x2160@24Hz", XVIDC_FR_24HZ, + {3840, 1276, 88, 296, 5500, 1, + 2160, 8, 10, 72, 2250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_3840x2160_25_P, "3840x2160@25Hz", XVIDC_FR_25HZ, + {3840, 1056, 88, 296, 5280, 1, + 2160, 8, 10, 72, 2250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_3840x2160_30_P, "3840x2160@30Hz", XVIDC_FR_30HZ, + {3840, 176, 88, 296, 4400, 1, + 2160, 8, 10, 72, 2250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_3840x2160_48_P, "3840x2160@48Hz", XVIDC_FR_48HZ, + {3840, 1276, 88, 296, 5500, 1, + 2160, 8, 10, 72, 2250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_3840x2160_50_P, "3840x2160@50Hz", XVIDC_FR_50HZ, + {3840, 1056, 88, 296, 5280, 1, + 2160, 8, 10, 72, 2250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_3840x2160_60_P, "3840x2160@60Hz", XVIDC_FR_60HZ, + {3840, 176, 88, 296, 4400, 1, + 2160, 8, 10, 72, 2250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_3840x2160_60_P_RB, "3840x2160@60Hz (RB)", XVIDC_FR_60HZ, + {3840, 48, 32, 80, 4000, 1, + 2160, 3, 5, 54, 2222, 0, 0, 0, 0, 0} }, + { XVIDC_VM_4096x2160_24_P, "4096x2160@24Hz", XVIDC_FR_24HZ, + {4096, 1020, 88, 296, 5500, 1, + 2160, 8, 10, 72, 2250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_4096x2160_25_P, "4096x2160@25Hz", XVIDC_FR_25HZ, + {4096, 968, 88, 128, 5280, 1, + 2160, 8, 10, 72, 2250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_4096x2160_30_P, "4096x2160@30Hz", XVIDC_FR_30HZ, + {4096, 88, 88, 128, 4400, 1, + 2160, 8, 10, 72, 2250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_4096x2160_48_P, "4096x2160@48Hz", XVIDC_FR_48HZ, + {4096, 1020, 88, 296, 5500, 1, + 2160, 8, 10, 72, 2250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_4096x2160_50_P, "4096x2160@50Hz", XVIDC_FR_50HZ, + {4096, 968, 88, 128, 5280, 1, + 2160, 8, 10, 72, 2250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_4096x2160_60_P, "4096x2160@60Hz", XVIDC_FR_60HZ, + {4096, 88, 88, 128, 4400, 1, + 2160, 8, 10, 72, 2250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_4096x2160_60_P_RB, "4096x2160@60Hz (RB)", XVIDC_FR_60HZ, + {4096, 8, 32, 40, 4176, 1, + 2160, 48, 8, 6, 2222, 0, 0, 0, 0, 0} }, +}; + +/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps.h index 893d516..58e5596 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps.h
@@ -88,6 +88,8 @@ * for CR 658287 * 3.0 pkp 12/09/14 Added support for Zynq Ultrascale Mp.Also * modified code for MISRA-C:2012 compliance. +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. * </pre> * ******************************************************************************/
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps_g.c index 6ea6b19..94d8c47 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps_g.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps_g.c
@@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,9 +44,13 @@ * The configuration table for devices */ -XWdtPs_Config XWdtPs_ConfigTable[] = +XWdtPs_Config XWdtPs_ConfigTable[XPAR_XWDTPS_NUM_INSTANCES] = { { + XPAR_PSU_CSU_WDT_DEVICE_ID, + XPAR_PSU_CSU_WDT_BASEADDR + }, + { XPAR_PSU_WDT_0_DEVICE_ID, XPAR_PSU_WDT_0_BASEADDR },
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/Makefile rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/Makefile
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/xzdma.c similarity index 97% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/xzdma.c index c203f58..8cad941 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/xzdma.c
@@ -33,7 +33,7 @@ /** * * @file xzdma.c -* @addtogroup zdma_v1_0 +* @addtogroup zdma_v1_5 * @{ * * This file contains the implementation of the interface functions for ZDMA @@ -52,6 +52,7 @@ * scatter gather mode data transfer and corrected * XZDma_SetChDataConfig API to set over fetch and * src issue parameters correctly. +* 1.3 mus 08/14/17 Add CCI support for A53 in EL1 NS * </pre> * ******************************************************************************/ @@ -117,6 +118,7 @@ InstancePtr->Config.BaseAddress = CfgPtr->BaseAddress; InstancePtr->Config.DeviceId = CfgPtr->DeviceId; InstancePtr->Config.DmaType = CfgPtr->DmaType; + InstancePtr->Config.IsCacheCoherent = CfgPtr->IsCacheCoherent; InstancePtr->Config.BaseAddress = EffectiveAddr; @@ -279,8 +281,9 @@ (NoOfBytes >> 1) / Size; InstancePtr->Descriptor.SrcDscrPtr = (void *)Dscr_MemPtr; InstancePtr->Descriptor.DstDscrPtr = - (void *)Dscr_MemPtr + (Size * InstancePtr->Descriptor.DscrCount); + (void *)(Dscr_MemPtr + (Size * InstancePtr->Descriptor.DscrCount)); + if (!InstancePtr->Config.IsCacheCoherent) Xil_DCacheInvalidateRange((INTPTR)Dscr_MemPtr, NoOfBytes); return (InstancePtr->Descriptor.DscrCount); @@ -701,6 +704,17 @@ (void)XZDma_GetSrcIntrCnt(InstancePtr); (void)XZDma_GetDstIntrCnt(InstancePtr); + if (InstancePtr->Config.IsCacheCoherent) { + XZDma_WriteReg((InstancePtr->Config.BaseAddress), + XZDMA_CH_DSCR_ATTR_OFFSET, + InstancePtr->Config.IsCacheCoherent << XZDMA_DSCR_ATTR_AXCOHRNT_SHIFT); + XZDma_WriteReg((InstancePtr->Config.BaseAddress), + XZDMA_CH_SRC_DSCR_WORD3_OFFSET, + InstancePtr->Config.IsCacheCoherent & XZDMA_WORD3_COHRNT_MASK); + XZDma_WriteReg((InstancePtr->Config.BaseAddress), + XZDMA_CH_DST_DSCR_WORD3_OFFSET, + InstancePtr->Config.IsCacheCoherent & XZDMA_WORD3_COHRNT_MASK); + } InstancePtr->ChannelState = XZDMA_IDLE; }
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/xzdma.h similarity index 93% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/xzdma.h index 1f268d4..9ff6907 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/xzdma.h
@@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2014-2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,12 +33,12 @@ /** * * @file xzdma.h -* @addtogroup zdma_v1_0 +* @addtogroup zdma_v1_5 * @{ * @details * * ZDMA is a general purpose DMA designed to support memory to memory and memory -* to IO buffer transfers. ALTO has two instance of general purpose ZDMA. +* to IO buffer transfers. ZynqMP has two instance of general purpose ZDMA. * One is located in FPD (full power domain) which is GDMA and other is located * in LPD (low power domain) which is ADMA. * @@ -115,7 +115,20 @@ * scatter gather mode data transfer and corrected * XZDma_SetChDataConfig API to set over fetch and * src issue parameters correctly. - +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* ms 04/05/17 Modified comment lines notation in functions of zdma +* examples to avoid unnecessary description to get +* displayed while generating doxygen and also changed +* filename tag to include the readonly mode example file +* in doxygen. +* 1.3 mus 08/14/17 Update cache coherency information of the interface in +* its config structure. +* 1.4 adk 11/02/17 Updated examples to fix compilation errors for IAR +* compiler. +* 1.5 adk 11/22/17 Added peripheral test app support for ZDMA driver. +* 12/11/17 Fixed peripheral test app generation issues when dma +* buffers are configured on OCM memory(CR#990806). * </pre> * ******************************************************************************/ @@ -132,6 +145,7 @@ #include "xil_assert.h" #include "xstatus.h" #include "xil_cache.h" +#include "bspconfig.h" /************************** Constant Definitions *****************************/ @@ -202,24 +216,38 @@ /** * This typedef contains scatter gather descriptor fields for ZDMA core. */ +#if defined (__ICCARM__) +#pragma pack(push, 1) +#endif typedef struct { u64 Address; /**< Address */ u32 Size; /**< Word2, Size of data */ u32 Cntl; /**< Word3 Control data */ u64 NextDscr; /**< Address of next descriptor */ u64 Reserved; /**< Reserved address */ +#if defined (__ICCARM__) +} XZDma_LlDscr ; +#pragma pack(pop) +#else } __attribute__ ((packed)) XZDma_LlDscr; - +#endif /******************************************************************************/ /** * This typedef contains Linear descriptor fields for ZDMA core. */ +#if defined (__ICCARM__) +#pragma pack(push, 1) +#endif typedef struct { u64 Address; /**< Address */ u32 Size; /**< Word3, Size of data */ u32 Cntl; /**< Word4, control data */ +#if defined (__ICCARM__) +}XZDma_LiDscr; +#pragma pack(pop) +#else } __attribute__ ((packed)) XZDma_LiDscr; - +#endif /******************************************************************************/ /** * @@ -282,6 +310,8 @@ u16 DeviceId; /**< Device Id of ZDMA */ u32 BaseAddress; /**< BaseAddress of ZDMA */ u8 DmaType; /**< Type of DMA */ + u8 IsCacheCoherent; /**< Describes whether Cache Coherent or not; + * Applicable only to A53 in EL1 NS mode */ } XZDma_Config; /******************************************************************************/ @@ -300,6 +330,8 @@ XZDma_Mode Mode; /**< Mode of ZDMA core to be operated */ u8 IsSgDma; /**< Is ZDMA core is in scatter gather or * not will be specified */ + u32 Slcr_adma; /**< Used to hold SLCR ADMA register + * contents */ XZDma_Descriptor Descriptor; /**< It contains information about * descriptors */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/xzdma_g.c similarity index 70% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_g.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/xzdma_g.c index 194aac1..984bf9c 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_g.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/xzdma_g.c
@@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,87 +44,103 @@ * The configuration table for devices */ -XZDma_Config XZDma_ConfigTable[] = +XZDma_Config XZDma_ConfigTable[XPAR_XZDMA_NUM_INSTANCES] = { { XPAR_PSU_ADMA_0_DEVICE_ID, XPAR_PSU_ADMA_0_BASEADDR, - XPAR_PSU_ADMA_0_DMA_MODE + XPAR_PSU_ADMA_0_DMA_MODE, + XPAR_PSU_ADMA_0_IS_CACHE_COHERENT }, { XPAR_PSU_ADMA_1_DEVICE_ID, XPAR_PSU_ADMA_1_BASEADDR, - XPAR_PSU_ADMA_1_DMA_MODE + XPAR_PSU_ADMA_1_DMA_MODE, + XPAR_PSU_ADMA_1_IS_CACHE_COHERENT }, { XPAR_PSU_ADMA_2_DEVICE_ID, XPAR_PSU_ADMA_2_BASEADDR, - XPAR_PSU_ADMA_2_DMA_MODE + XPAR_PSU_ADMA_2_DMA_MODE, + XPAR_PSU_ADMA_2_IS_CACHE_COHERENT }, { XPAR_PSU_ADMA_3_DEVICE_ID, XPAR_PSU_ADMA_3_BASEADDR, - XPAR_PSU_ADMA_3_DMA_MODE + XPAR_PSU_ADMA_3_DMA_MODE, + XPAR_PSU_ADMA_3_IS_CACHE_COHERENT }, { XPAR_PSU_ADMA_4_DEVICE_ID, XPAR_PSU_ADMA_4_BASEADDR, - XPAR_PSU_ADMA_4_DMA_MODE + XPAR_PSU_ADMA_4_DMA_MODE, + XPAR_PSU_ADMA_4_IS_CACHE_COHERENT }, { XPAR_PSU_ADMA_5_DEVICE_ID, XPAR_PSU_ADMA_5_BASEADDR, - XPAR_PSU_ADMA_5_DMA_MODE + XPAR_PSU_ADMA_5_DMA_MODE, + XPAR_PSU_ADMA_5_IS_CACHE_COHERENT }, { XPAR_PSU_ADMA_6_DEVICE_ID, XPAR_PSU_ADMA_6_BASEADDR, - XPAR_PSU_ADMA_6_DMA_MODE + XPAR_PSU_ADMA_6_DMA_MODE, + XPAR_PSU_ADMA_6_IS_CACHE_COHERENT }, { XPAR_PSU_ADMA_7_DEVICE_ID, XPAR_PSU_ADMA_7_BASEADDR, - XPAR_PSU_ADMA_7_DMA_MODE + XPAR_PSU_ADMA_7_DMA_MODE, + XPAR_PSU_ADMA_7_IS_CACHE_COHERENT }, { XPAR_PSU_GDMA_0_DEVICE_ID, XPAR_PSU_GDMA_0_BASEADDR, - XPAR_PSU_GDMA_0_DMA_MODE + XPAR_PSU_GDMA_0_DMA_MODE, + XPAR_PSU_GDMA_0_IS_CACHE_COHERENT }, { XPAR_PSU_GDMA_1_DEVICE_ID, XPAR_PSU_GDMA_1_BASEADDR, - XPAR_PSU_GDMA_1_DMA_MODE + XPAR_PSU_GDMA_1_DMA_MODE, + XPAR_PSU_GDMA_1_IS_CACHE_COHERENT }, { XPAR_PSU_GDMA_2_DEVICE_ID, XPAR_PSU_GDMA_2_BASEADDR, - XPAR_PSU_GDMA_2_DMA_MODE + XPAR_PSU_GDMA_2_DMA_MODE, + XPAR_PSU_GDMA_2_IS_CACHE_COHERENT }, { XPAR_PSU_GDMA_3_DEVICE_ID, XPAR_PSU_GDMA_3_BASEADDR, - XPAR_PSU_GDMA_3_DMA_MODE + XPAR_PSU_GDMA_3_DMA_MODE, + XPAR_PSU_GDMA_3_IS_CACHE_COHERENT }, { XPAR_PSU_GDMA_4_DEVICE_ID, XPAR_PSU_GDMA_4_BASEADDR, - XPAR_PSU_GDMA_4_DMA_MODE + XPAR_PSU_GDMA_4_DMA_MODE, + XPAR_PSU_GDMA_4_IS_CACHE_COHERENT }, { XPAR_PSU_GDMA_5_DEVICE_ID, XPAR_PSU_GDMA_5_BASEADDR, - XPAR_PSU_GDMA_5_DMA_MODE + XPAR_PSU_GDMA_5_DMA_MODE, + XPAR_PSU_GDMA_5_IS_CACHE_COHERENT }, { XPAR_PSU_GDMA_6_DEVICE_ID, XPAR_PSU_GDMA_6_BASEADDR, - XPAR_PSU_GDMA_6_DMA_MODE + XPAR_PSU_GDMA_6_DMA_MODE, + XPAR_PSU_GDMA_6_IS_CACHE_COHERENT }, { XPAR_PSU_GDMA_7_DEVICE_ID, XPAR_PSU_GDMA_7_BASEADDR, - XPAR_PSU_GDMA_7_DMA_MODE + XPAR_PSU_GDMA_7_DMA_MODE, + XPAR_PSU_GDMA_7_IS_CACHE_COHERENT } };
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/xzdma_hw.h similarity index 98% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_hw.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/xzdma_hw.h index 85f6302..046921c 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_hw.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/xzdma_hw.h
@@ -33,7 +33,7 @@ /** * * @file xzdma_hw.h -* @addtogroup zdma_v1_0 +* @addtogroup zdma_v1_5 * @{ * * This header file contains identifiers and register-level driver functions (or @@ -107,6 +107,7 @@ #define XZDMA_CH_CTRL2_OFFSET (0x200U) /*@}*/ +#define XZDMA_SLCR_SECURE_OFFSET (0xff4b0024) /** @name Interrupt Enable/Disable/Mask/Status registers bit masks and shifts * @{ */ @@ -240,7 +241,7 @@ * mask */ #define XZDMA_DSCR_ATTR_AXCOHRNT_SHIFT (8U) /**< Descriptor coherent shift */ -#define XZDMA_DSCR_ATTR_AXCACHE_SHIFT (7U) /**< Descriptor cache shift */ +#define XZDMA_DSCR_ATTR_AXCACHE_SHIFT (4U) /**< Descriptor cache shift */ #define XZDMA_DSCR_ATTR_RESET_VALUE (0x00000000U) /**< Dscr Attributes * reset value */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/xzdma_intr.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_intr.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/xzdma_intr.c index e828d16..0e6af86 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_intr.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/xzdma_intr.c
@@ -33,7 +33,7 @@ /** * * @file xzdma_intr.c -* @addtogroup zdma_v1_0 +* @addtogroup zdma_v1_5 * @{ * * This file contains interrupt related functions of Xilinx ZDMA core.
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/xzdma_selftest.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_selftest.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/xzdma_selftest.c index 893a540..9e8b9dc 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_selftest.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/xzdma_selftest.c
@@ -33,7 +33,7 @@ /** * * @file xzdma_selftest.c -* @addtogroup zdma_v1_0 +* @addtogroup zdma_v1_5 * @{ * * This file contains the self-test function for the ZDMA core.
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/xzdma_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_sinit.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/xzdma_sinit.c index ae2c44d..b033d46 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_sinit.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/xzdma_sinit.c
@@ -33,7 +33,7 @@ /** * * @file xzdma_sinit.c -* @addtogroup zdma_v1_0 +* @addtogroup zdma_v1_5 * @{ * * This file contains static initialization methods for Xilinx ZDMA core.
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/system.mss b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/system.mss index 1c8fbdb..416b7a8 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/system.mss +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/system.mss
@@ -4,7 +4,7 @@ BEGIN OS PARAMETER OS_NAME = standalone - PARAMETER OS_VER = 6.1 + PARAMETER OS_VER = 6.6 PARAMETER PROC_INSTANCE = psu_cortexr5_0 PARAMETER stdin = psu_uart_0 PARAMETER stdout = psu_uart_0 @@ -13,62 +13,62 @@ BEGIN PROCESSOR PARAMETER DRIVER_NAME = cpu_cortexr5 - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.4 PARAMETER HW_INSTANCE = psu_cortexr5_0 END BEGIN DRIVER PARAMETER DRIVER_NAME = scugic - PARAMETER DRIVER_VER = 3.5 + PARAMETER DRIVER_VER = 3.9 PARAMETER HW_INSTANCE = psu_acpu_gic END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_adma_0 END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_adma_1 END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_adma_2 END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_adma_3 END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_adma_4 END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_adma_5 END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_adma_6 END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_adma_7 END @@ -116,31 +116,31 @@ BEGIN DRIVER PARAMETER DRIVER_NAME = sysmonpsu - PARAMETER DRIVER_VER = 2.0 + PARAMETER DRIVER_VER = 2.3 PARAMETER HW_INSTANCE = psu_ams END BEGIN DRIVER PARAMETER DRIVER_NAME = axipmon - PARAMETER DRIVER_VER = 6.5 + PARAMETER DRIVER_VER = 6.6 PARAMETER HW_INSTANCE = psu_apm_0 END BEGIN DRIVER PARAMETER DRIVER_NAME = axipmon - PARAMETER DRIVER_VER = 6.5 + PARAMETER DRIVER_VER = 6.6 PARAMETER HW_INSTANCE = psu_apm_1 END BEGIN DRIVER PARAMETER DRIVER_NAME = axipmon - PARAMETER DRIVER_VER = 6.5 + PARAMETER DRIVER_VER = 6.6 PARAMETER HW_INSTANCE = psu_apm_2 END BEGIN DRIVER PARAMETER DRIVER_NAME = axipmon - PARAMETER DRIVER_VER = 6.5 + PARAMETER DRIVER_VER = 6.6 PARAMETER HW_INSTANCE = psu_apm_5 END @@ -170,13 +170,13 @@ BEGIN DRIVER PARAMETER DRIVER_NAME = coresightps_dcc - PARAMETER DRIVER_VER = 1.3 + PARAMETER DRIVER_VER = 1.4 PARAMETER HW_INSTANCE = psu_coresight_0 END BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 2.0 + PARAMETER DRIVER_NAME = resetps + PARAMETER DRIVER_VER = 1.0 PARAMETER HW_INSTANCE = psu_crf_apb END @@ -187,14 +187,26 @@ END BEGIN DRIVER + PARAMETER DRIVER_NAME = wdtps + PARAMETER DRIVER_VER = 3.0 + PARAMETER HW_INSTANCE = psu_csu_wdt +END + +BEGIN DRIVER PARAMETER DRIVER_NAME = csudma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.2 PARAMETER HW_INSTANCE = psu_csudma END BEGIN DRIVER PARAMETER DRIVER_NAME = generic PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = psu_ctrl_ipi +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 PARAMETER HW_INSTANCE = psu_ddr_phy END @@ -247,14 +259,14 @@ END BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 2.0 + PARAMETER DRIVER_NAME = avbuf + PARAMETER DRIVER_VER = 2.1 PARAMETER HW_INSTANCE = psu_dp END BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 2.0 + PARAMETER DRIVER_NAME = dpdma + PARAMETER DRIVER_VER = 1.0 PARAMETER HW_INSTANCE = psu_dpdma END @@ -266,7 +278,7 @@ BEGIN DRIVER PARAMETER DRIVER_NAME = emacps - PARAMETER DRIVER_VER = 3.3 + PARAMETER DRIVER_VER = 3.7 PARAMETER HW_INSTANCE = psu_ethernet_3 END @@ -302,55 +314,55 @@ BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_gdma_0 END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_gdma_1 END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_gdma_2 END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_gdma_3 END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_gdma_4 END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_gdma_5 END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_gdma_6 END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_gdma_7 END BEGIN DRIVER PARAMETER DRIVER_NAME = gpiops - PARAMETER DRIVER_VER = 3.1 + PARAMETER DRIVER_VER = 3.3 PARAMETER HW_INSTANCE = psu_gpio_0 END @@ -362,13 +374,13 @@ BEGIN DRIVER PARAMETER DRIVER_NAME = iicps - PARAMETER DRIVER_VER = 3.4 + PARAMETER DRIVER_VER = 3.6 PARAMETER HW_INSTANCE = psu_i2c_0 END BEGIN DRIVER PARAMETER DRIVER_NAME = iicps - PARAMETER DRIVER_VER = 3.4 + PARAMETER DRIVER_VER = 3.6 PARAMETER HW_INSTANCE = psu_i2c_1 END @@ -398,7 +410,7 @@ BEGIN DRIVER PARAMETER DRIVER_NAME = ipipsu - PARAMETER DRIVER_VER = 2.1 + PARAMETER DRIVER_VER = 2.3 PARAMETER HW_INSTANCE = psu_ipi_1 END @@ -435,6 +447,12 @@ BEGIN DRIVER PARAMETER DRIVER_NAME = generic PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = psu_message_buffers +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 PARAMETER HW_INSTANCE = psu_ocm END @@ -471,6 +489,18 @@ BEGIN DRIVER PARAMETER DRIVER_NAME = generic PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = psu_pcie_high1 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = psu_pcie_high2 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 PARAMETER HW_INSTANCE = psu_pcie_low END @@ -481,14 +511,8 @@ END BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 2.0 - PARAMETER HW_INSTANCE = psu_pmu_iomodule -END - -BEGIN DRIVER PARAMETER DRIVER_NAME = qspipsu - PARAMETER DRIVER_VER = 1.3 + PARAMETER DRIVER_VER = 1.7 PARAMETER HW_INSTANCE = psu_qspi_0 END @@ -524,7 +548,7 @@ BEGIN DRIVER PARAMETER DRIVER_NAME = scugic - PARAMETER DRIVER_VER = 3.5 + PARAMETER DRIVER_VER = 3.9 PARAMETER HW_INSTANCE = psu_rcpu_gic END @@ -542,7 +566,7 @@ BEGIN DRIVER PARAMETER DRIVER_NAME = rtcpsu - PARAMETER DRIVER_VER = 1.3 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_rtc END @@ -554,7 +578,7 @@ BEGIN DRIVER PARAMETER DRIVER_NAME = sdps - PARAMETER DRIVER_VER = 3.1 + PARAMETER DRIVER_VER = 3.4 PARAMETER HW_INSTANCE = psu_sd_1 END @@ -584,47 +608,53 @@ BEGIN DRIVER PARAMETER DRIVER_NAME = ttcps - PARAMETER DRIVER_VER = 3.2 + PARAMETER DRIVER_VER = 3.5 PARAMETER HW_INSTANCE = psu_ttc_0 END BEGIN DRIVER PARAMETER DRIVER_NAME = ttcps - PARAMETER DRIVER_VER = 3.2 + PARAMETER DRIVER_VER = 3.5 PARAMETER HW_INSTANCE = psu_ttc_1 END BEGIN DRIVER PARAMETER DRIVER_NAME = ttcps - PARAMETER DRIVER_VER = 3.2 + PARAMETER DRIVER_VER = 3.5 PARAMETER HW_INSTANCE = psu_ttc_2 END BEGIN DRIVER PARAMETER DRIVER_NAME = ttcps - PARAMETER DRIVER_VER = 3.2 + PARAMETER DRIVER_VER = 3.5 PARAMETER HW_INSTANCE = psu_ttc_3 END BEGIN DRIVER PARAMETER DRIVER_NAME = uartps - PARAMETER DRIVER_VER = 3.3 + PARAMETER DRIVER_VER = 3.6 PARAMETER HW_INSTANCE = psu_uart_0 END BEGIN DRIVER PARAMETER DRIVER_NAME = uartps - PARAMETER DRIVER_VER = 3.3 + PARAMETER DRIVER_VER = 3.6 PARAMETER HW_INSTANCE = psu_uart_1 END BEGIN DRIVER - PARAMETER DRIVER_NAME = usbpsu - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 PARAMETER HW_INSTANCE = psu_usb_0 END BEGIN DRIVER + PARAMETER DRIVER_NAME = usbpsu + PARAMETER DRIVER_VER = 1.4 + PARAMETER HW_INSTANCE = psu_usb_xhci_0 +END + +BEGIN DRIVER PARAMETER DRIVER_NAME = wdtps PARAMETER DRIVER_VER = 3.0 PARAMETER HW_INSTANCE = psu_wdt_0