Add local copy of the library files as the common copy has changed and breaks this build.
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/cortexm3_macro.h b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/cortexm3_macro.h
new file mode 100644
index 0000000..c67240e
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/cortexm3_macro.h
@@ -0,0 +1,51 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : cortexm3_macro.h
+* Author : MCD Application Team
+* Date First Issued : 09/29/2006
+* Description : Header file for cortexm3_macro.s.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __CORTEXM3_MACRO_H
+#define __CORTEXM3_MACRO_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_type.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void __WFI(void);
+void __WFE(void);
+void __SEV(void);
+void __ISB(void);
+void __DSB(void);
+void __DMB(void);
+void __SVC(void);
+u32 __MRS_CONTROL(void);
+void __MSR_CONTROL(u32 Control);
+void __SETPRIMASK(void);
+void __RESETPRIMASK(void);
+void __SETFAULTMASK(void);
+void __RESETFAULTMASK(void);
+void __BASEPRICONFIG(u32 NewPriority);
+u32 __GetBASEPRI(void);
+u16 __REV_HalfWord(u16 Data);
+u32 __REV_Word(u32 Data);
+
+#endif /* __CORTEXM3_MACRO_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/lcd.h b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/lcd.h
new file mode 100644
index 0000000..73f44b9
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/lcd.h
@@ -0,0 +1,179 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : lcd.h
+* Author : MCD Application Team
+* Date First Issued : mm/dd/yyyy
+* Description : This file contains all the functions prototypes for the
+* lcd software driver.
+********************************************************************************
+* History:
+* mm/dd/yyyy
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __LCD_H
+#define __LCD_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_lib.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* LCD Registers */
+#define R0 0x00
+#define R1 0x01
+#define R2 0x02
+#define R3 0x03
+#define R5 0x05
+#define R6 0x06
+#define R13 0x0D
+#define R14 0x0E
+#define R15 0x0F
+#define R16 0x10
+#define R17 0x11
+#define R18 0x12
+#define R19 0x13
+#define R20 0x14
+#define R21 0x15
+#define R22 0x16
+#define R23 0x17
+#define R24 0x18
+#define R25 0x19
+#define R26 0x1A
+#define R27 0x1B
+#define R28 0x1C
+#define R29 0x1D
+#define R30 0x1E
+#define R31 0x1F
+#define R32 0x20
+#define R36 0x24
+#define R37 0x25
+#define R40 0x28
+#define R43 0x2B
+#define R45 0x2D
+#define R49 0x31
+#define R50 0x32
+#define R51 0x33
+#define R52 0x34
+#define R53 0x35
+#define R55 0x37
+#define R59 0x3B
+#define R60 0x3C
+#define R61 0x3D
+#define R62 0x3E
+#define R63 0x3F
+#define R64 0x40
+#define R65 0x41
+#define R66 0x42
+#define R67 0x43
+#define R68 0x44
+#define R69 0x45
+#define R70 0x46
+#define R71 0x47
+#define R72 0x48
+#define R73 0x49
+#define R74 0x4A
+#define R75 0x4B
+#define R76 0x4C
+#define R77 0x4D
+#define R78 0x4E
+#define R79 0x4F
+#define R80 0x50
+#define R118 0x76
+#define R134 0x86
+#define R135 0x87
+#define R136 0x88
+#define R137 0x89
+#define R139 0x8B
+#define R140 0x8C
+#define R141 0x8D
+#define R143 0x8F
+#define R144 0x90
+#define R145 0x91
+#define R146 0x92
+#define R147 0x93
+#define R148 0x94
+#define R149 0x95
+#define R150 0x96
+#define R151 0x97
+#define R152 0x98
+#define R153 0x99
+#define R154 0x9A
+#define R157 0x9D
+#define R192 0xC0
+#define R193 0xC1
+
+/* LCD Control pins */
+#define CtrlPin_NCS GPIO_Pin_2 /* PB.02 */
+#define CtrlPin_RS GPIO_Pin_7 /* PD.07 */
+#define CtrlPin_NWR GPIO_Pin_15 /* PD.15 */
+
+/* LCD color */
+#define White 0xFFFF
+#define Black 0x0000
+#define Blue 0x001F
+#define Orange 0x051F
+#define Red 0xF800
+#define Magenta 0xF81F
+#define Green 0x07E0
+#define Cyan 0x7FFF
+#define Yellow 0xFFE0
+
+#define Line0 0
+#define Line1 24
+#define Line2 48
+#define Line3 72
+#define Line4 96
+#define Line5 120
+#define Line6 144
+#define Line7 168
+#define Line8 192
+#define Line9 216
+
+#define Horizontal 0x00
+#define Vertical 0x01
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/*----- High layer function -----*/
+void LCD_Init(void);
+void LCD_SetTextColor(vu16 Color);
+void LCD_SetBackColor(vu16 Color);
+void LCD_ClearLine(u8 Line);
+void LCD_Clear(void);
+void LCD_SetCursor(u8 Xpos, u16 Ypos);
+void LCD_DrawChar(u8 Xpos, u16 Ypos, uc16 *c);
+void LCD_DisplayChar(u8 Line, u16 Column, u8 Ascii);
+void LCD_DisplayStringLine(u8 Line, u8 *ptr);
+void LCD_DisplayString(u8 Line, u8 *ptr);
+void LCD_ScrollText(u8 Line, u8 *ptr);
+void LCD_SetDisplayWindow(u8 Xpos, u16 Ypos, u8 Height, u16 Width);
+void LCD_DrawLine(u8 Xpos, u16 Ypos, u16 Length, u8 Direction);
+void LCD_DrawRect(u8 Xpos, u16 Ypos, u8 Height, u16 Width);
+void LCD_DrawCircle(u8 Xpos, u16 Ypos, u16 Radius);
+void LCD_DrawMonoPict(uc32 *Pict);
+void LCD_DrawBMP(u32 BmpAddress);
+
+/*----- Medium layer function -----*/
+void LCD_WriteReg(u8 LCD_Reg, u8 LCD_RegValue);
+u8 LCD_ReadReg(u8 LCD_Reg);
+void LCD_WriteRAM(u16 RGB_Code);
+u16 LCD_ReadRAM(void);
+void LCD_PowerOn(void);
+void LCD_DisplayOn(void);
+void LCD_DisplayOff(void);
+
+/*----- Low layer function -----*/
+void LCD_CtrlLinesConfig(void);
+void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, u16 CtrlPins, BitAction BitVal);
+void LCD_SPIConfig(void);
+
+#endif /* __LCD_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/spi_flash.h b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/spi_flash.h
new file mode 100644
index 0000000..5bd8a96
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/spi_flash.h
@@ -0,0 +1,53 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : spi_flash.h
+* Author : MCD Application Team
+* Date First Issued : 02/05/2007
+* Description : Header for spi_flash.c file.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __SPI_FLASH_H
+#define __SPI_FLASH_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_lib.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+#define Low 0x00 /* Chip Select line low */
+#define High 0x01 /* Chip Select line high */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/*----- High layer function -----*/
+void SPI_FLASH_Init(void);
+void SPI_FLASH_SectorErase(u32 SectorAddr);
+void SPI_FLASH_BulkErase(void);
+void SPI_FLASH_PageWrite(u8* pBuffer, u32 WriteAddr, u16 NumByteToWrite);
+void SPI_FLASH_BufferWrite(u8* pBuffer, u32 WriteAddr, u16 NumByteToWrite);
+void SPI_FLASH_BufferRead(u8* pBuffer, u32 ReadAddr, u16 NumByteToRead);
+u32 SPI_FLASH_ReadID(void);
+void SPI_FLASH_StartReadSequence(u32 ReadAddr);
+
+/*----- Low layer function -----*/
+u8 SPI_FLASH_ReadByte(void);
+void SPI_FLASH_ChipSelect(u8 State);
+u8 SPI_FLASH_SendByte(u8 byte);
+u16 SPI_FLASH_SendHalfWord(u16 HalfWord);
+void SPI_FLASH_WriteEnable(void);
+void SPI_FLASH_WaitForWriteEnd(void);
+
+#endif /* __SPI_FLASH_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_adc.h b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_adc.h
new file mode 100644
index 0000000..8e90539
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_adc.h
@@ -0,0 +1,269 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_adc.h
+* Author : MCD Application Team
+* Date First Issued : 09/29/2006
+* Description : This file contains all the functions prototypes for the
+* ADC firmware library.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_ADC_H
+#define __STM32F10x_ADC_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* ADC Init structure definition */
+typedef struct
+{
+ u32 ADC_Mode;
+ FunctionalState ADC_ScanConvMode;
+ FunctionalState ADC_ContinuousConvMode;
+ u32 ADC_ExternalTrigConv;
+ u32 ADC_DataAlign;
+ u8 ADC_NbrOfChannel;
+}ADC_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/* ADC dual mode -------------------------------------------------------------*/
+#define ADC_Mode_Independent ((u32)0x00000000)
+#define ADC_Mode_RegInjecSimult ((u32)0x00010000)
+#define ADC_Mode_RegSimult_AlterTrig ((u32)0x00020000)
+#define ADC_Mode_InjecSimult_FastInterl ((u32)0x00030000)
+#define ADC_Mode_InjecSimult_SlowInterl ((u32)0x00040000)
+#define ADC_Mode_InjecSimult ((u32)0x00050000)
+#define ADC_Mode_RegSimult ((u32)0x00060000)
+#define ADC_Mode_FastInterl ((u32)0x00070000)
+#define ADC_Mode_SlowInterl ((u32)0x00080000)
+#define ADC_Mode_AlterTrig ((u32)0x00090000)
+
+#define IS_ADC_MODE(MODE) ((MODE == ADC_Mode_Independent) || \
+ (MODE == ADC_Mode_RegInjecSimult) || \
+ (MODE == ADC_Mode_RegSimult_AlterTrig) || \
+ (MODE == ADC_Mode_InjecSimult_FastInterl) || \
+ (MODE == ADC_Mode_InjecSimult_SlowInterl) || \
+ (MODE == ADC_Mode_InjecSimult) || \
+ (MODE == ADC_Mode_RegSimult) || \
+ (MODE == ADC_Mode_FastInterl) || \
+ (MODE == ADC_Mode_SlowInterl) || \
+ (MODE == ADC_Mode_AlterTrig))
+
+/* ADC extrenal trigger sources for regular channels conversion --------------*/
+#define ADC_ExternalTrigConv_T1_CC1 ((u32)0x00000000)
+#define ADC_ExternalTrigConv_T1_CC2 ((u32)0x00020000)
+#define ADC_ExternalTrigConv_T1_CC3 ((u32)0x00040000)
+#define ADC_ExternalTrigConv_T2_CC2 ((u32)0x00060000)
+#define ADC_ExternalTrigConv_T3_TRGO ((u32)0x00080000)
+#define ADC_ExternalTrigConv_T4_CC4 ((u32)0x000A0000)
+#define ADC_ExternalTrigConv_Ext_IT11 ((u32)0x000C0000)
+#define ADC_ExternalTrigConv_None ((u32)0x000E0000)
+
+#define IS_ADC_EXT_TRIG(TRIG1) ((TRIG1 == ADC_ExternalTrigConv_T1_CC1) || \
+ (TRIG1 == ADC_ExternalTrigConv_T1_CC2) || \
+ (TRIG1 == ADC_ExternalTrigConv_T1_CC3) || \
+ (TRIG1 == ADC_ExternalTrigConv_T2_CC2) || \
+ (TRIG1 == ADC_ExternalTrigConv_T3_TRGO) || \
+ (TRIG1 == ADC_ExternalTrigConv_T4_CC4) || \
+ (TRIG1 == ADC_ExternalTrigConv_Ext_IT11) || \
+ (TRIG1 == ADC_ExternalTrigConv_None))
+
+/* ADC data align ------------------------------------------------------------*/
+#define ADC_DataAlign_Right ((u32)0x00000000)
+#define ADC_DataAlign_Left ((u32)0x00000800)
+
+#define IS_ADC_DATA_ALIGN(ALIGN) ((ALIGN == ADC_DataAlign_Right) || \
+ (ALIGN == ADC_DataAlign_Left))
+
+/* ADC channels --------------------------------------------------------------*/
+#define ADC_Channel_0 ((u8)0x00)
+#define ADC_Channel_1 ((u8)0x01)
+#define ADC_Channel_2 ((u8)0x02)
+#define ADC_Channel_3 ((u8)0x03)
+#define ADC_Channel_4 ((u8)0x04)
+#define ADC_Channel_5 ((u8)0x05)
+#define ADC_Channel_6 ((u8)0x06)
+#define ADC_Channel_7 ((u8)0x07)
+#define ADC_Channel_8 ((u8)0x08)
+#define ADC_Channel_9 ((u8)0x09)
+#define ADC_Channel_10 ((u8)0x0A)
+#define ADC_Channel_11 ((u8)0x0B)
+#define ADC_Channel_12 ((u8)0x0C)
+#define ADC_Channel_13 ((u8)0x0D)
+#define ADC_Channel_14 ((u8)0x0E)
+#define ADC_Channel_15 ((u8)0x0F)
+#define ADC_Channel_16 ((u8)0x10)
+#define ADC_Channel_17 ((u8)0x11)
+
+#define IS_ADC_CHANNEL(CHANNEL) ((CHANNEL == ADC_Channel_0) || (CHANNEL == ADC_Channel_1) || \
+ (CHANNEL == ADC_Channel_2) || (CHANNEL == ADC_Channel_3) || \
+ (CHANNEL == ADC_Channel_4) || (CHANNEL == ADC_Channel_5) || \
+ (CHANNEL == ADC_Channel_6) || (CHANNEL == ADC_Channel_7) || \
+ (CHANNEL == ADC_Channel_8) || (CHANNEL == ADC_Channel_9) || \
+ (CHANNEL == ADC_Channel_10) || (CHANNEL == ADC_Channel_11) || \
+ (CHANNEL == ADC_Channel_12) || (CHANNEL == ADC_Channel_13) || \
+ (CHANNEL == ADC_Channel_14) || (CHANNEL == ADC_Channel_15) || \
+ (CHANNEL == ADC_Channel_16) || (CHANNEL == ADC_Channel_17))
+
+/* ADC sampling times --------------------------------------------------------*/
+#define ADC_SampleTime_1Cycles5 ((u8)0x00)
+#define ADC_SampleTime_7Cycles5 ((u8)0x01)
+#define ADC_SampleTime_13Cycles5 ((u8)0x02)
+#define ADC_SampleTime_28Cycles5 ((u8)0x03)
+#define ADC_SampleTime_41Cycles5 ((u8)0x04)
+#define ADC_SampleTime_55Cycles5 ((u8)0x05)
+#define ADC_SampleTime_71Cycles5 ((u8)0x06)
+#define ADC_SampleTime_239Cycles5 ((u8)0x07)
+
+#define IS_ADC_SAMPLE_TIME(TIME) ((TIME == ADC_SampleTime_1Cycles5) || \
+ (TIME == ADC_SampleTime_7Cycles5) || \
+ (TIME == ADC_SampleTime_13Cycles5) || \
+ (TIME == ADC_SampleTime_28Cycles5) || \
+ (TIME == ADC_SampleTime_41Cycles5) || \
+ (TIME == ADC_SampleTime_55Cycles5) || \
+ (TIME == ADC_SampleTime_71Cycles5) || \
+ (TIME == ADC_SampleTime_239Cycles5))
+
+/* ADC extrenal trigger sources for injected channels conversion -------------*/
+#define ADC_ExternalTrigInjecConv_T1_TRGO ((u32)0x00000000)
+#define ADC_ExternalTrigInjecConv_T1_CC4 ((u32)0x00001000)
+#define ADC_ExternalTrigInjecConv_T2_TRGO ((u32)0x00002000)
+#define ADC_ExternalTrigInjecConv_T2_CC1 ((u32)0x00003000)
+#define ADC_ExternalTrigInjecConv_T3_CC4 ((u32)0x00004000)
+#define ADC_ExternalTrigInjecConv_T4_TRGO ((u32)0x00005000)
+#define ADC_ExternalTrigInjecConv_Ext_IT15 ((u32)0x00006000)
+#define ADC_ExternalTrigInjecConv_None ((u32)0x00007000)
+
+#define IS_ADC_EXT_INJEC_TRIG(TRIG) ((TRIG == ADC_ExternalTrigInjecConv_T1_TRGO) || \
+ (TRIG == ADC_ExternalTrigInjecConv_T1_CC4) || \
+ (TRIG == ADC_ExternalTrigInjecConv_T2_TRGO) || \
+ (TRIG == ADC_ExternalTrigInjecConv_T2_CC1) || \
+ (TRIG == ADC_ExternalTrigInjecConv_T3_CC4) || \
+ (TRIG == ADC_ExternalTrigInjecConv_T4_TRGO) || \
+ (TRIG == ADC_ExternalTrigInjecConv_Ext_IT15) || \
+ (TRIG == ADC_ExternalTrigInjecConv_None))
+
+/* ADC injected channel selection --------------------------------------------*/
+#define ADC_InjectedChannel_1 ((u8)0x14)
+#define ADC_InjectedChannel_2 ((u8)0x18)
+#define ADC_InjectedChannel_3 ((u8)0x1C)
+#define ADC_InjectedChannel_4 ((u8)0x20)
+
+#define IS_ADC_INJECTED_CHANNEL(CHANNEL) ((CHANNEL == ADC_InjectedChannel_1) || \
+ (CHANNEL == ADC_InjectedChannel_2) || \
+ (CHANNEL == ADC_InjectedChannel_3) || \
+ (CHANNEL == ADC_InjectedChannel_4))
+
+/* ADC analog watchdog selection ---------------------------------------------*/
+#define ADC_AnalogWatchdog_SingleRegEnable ((u32)0x00800200)
+#define ADC_AnalogWatchdog_SingleInjecEnable ((u32)0x00400200)
+#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((u32)0x00C00200)
+#define ADC_AnalogWatchdog_AllRegEnable ((u32)0x00800000)
+#define ADC_AnalogWatchdog_AllInjecEnable ((u32)0x00400000)
+#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((u32)0x00C00000)
+#define ADC_AnalogWatchdog_None ((u32)0x00000000)
+
+#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) ((WATCHDOG == ADC_AnalogWatchdog_SingleRegEnable) || \
+ (WATCHDOG == ADC_AnalogWatchdog_SingleInjecEnable) || \
+ (WATCHDOG == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
+ (WATCHDOG == ADC_AnalogWatchdog_AllRegEnable) || \
+ (WATCHDOG == ADC_AnalogWatchdog_AllInjecEnable) || \
+ (WATCHDOG == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
+ (WATCHDOG == ADC_AnalogWatchdog_None))
+
+/* ADC interrupts definition -------------------------------------------------*/
+#define ADC_IT_EOC ((u16)0x0220)
+#define ADC_IT_AWD ((u16)0x0140)
+#define ADC_IT_JEOC ((u16)0x0480)
+
+#define IS_ADC_IT(IT) (((IT & (u16)0xF81F) == 0x00) && (IT != 0x00))
+#define IS_ADC_GET_IT(IT) ((IT == ADC_IT_EOC) || (IT == ADC_IT_AWD) || \
+ (IT == ADC_IT_JEOC))
+
+/* ADC flags definition ------------------------------------------------------*/
+#define ADC_FLAG_AWD ((u8)0x01)
+#define ADC_FLAG_EOC ((u8)0x02)
+#define ADC_FLAG_JEOC ((u8)0x04)
+#define ADC_FLAG_JSTRT ((u8)0x08)
+#define ADC_FLAG_STRT ((u8)0x10)
+
+#define IS_ADC_CLEAR_FLAG(FLAG) (((FLAG & (u8)0xE0) == 0x00) && (FLAG != 0x00))
+#define IS_ADC_GET_FLAG(FLAG) ((FLAG == ADC_FLAG_AWD) || (FLAG == ADC_FLAG_EOC) || \
+ (FLAG == ADC_FLAG_JEOC) || (FLAG == ADC_FLAG_JSTRT) || \
+ (FLAG == ADC_FLAG_STRT))
+
+/* ADC thresholds ------------------------------------------------------------*/
+#define IS_ADC_THRESHOLD(THRESHOLD) (THRESHOLD <= 0xFFF)
+
+/* ADC injected offset -------------------------------------------------------*/
+#define IS_ADC_OFFSET(OFFSET) (OFFSET <= 0xFFF)
+
+/* ADC injected length -------------------------------------------------------*/
+#define IS_ADC_INJECTED_LENGTH(LENGTH) ((LENGTH >= 0x1) && (LENGTH <= 0x4))
+
+/* ADC injected rank ---------------------------------------------------------*/
+#define IS_ADC_INJECTED_RANK(RANK) ((RANK >= 0x1) && (RANK <= 0x4))
+
+/* ADC regular length --------------------------------------------------------*/
+#define IS_ADC_REGULAR_LENGTH(LENGTH) ((LENGTH >= 0x1) && (LENGTH <= 0x10))
+
+/* ADC regular rank ----------------------------------------------------------*/
+#define IS_ADC_REGULAR_RANK(RANK) ((RANK >= 0x1) && (RANK <= 0x10))
+
+/* ADC regular discontinuous mode number -------------------------------------*/
+#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) ((NUMBER >= 0x1) && (NUMBER <= 0x8))
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void ADC_DeInit(ADC_TypeDef* ADCx);
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_ITConfig(ADC_TypeDef* ADCx, u16 ADC_IT, FunctionalState NewState);
+void ADC_ResetCalibration(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);
+void ADC_StartCalibration(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
+void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, u8 Number);
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime);
+void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+u16 ADC_GetConversionValue(ADC_TypeDef* ADCx);
+u32 ADC_GetDualModeConversionValue(void);
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, u32 ADC_ExternalTrigInjecConv);
+void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime);
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, u8 Length);
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel, u16 Offset);
+u16 ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel);
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, u32 ADC_AnalogWatchdog);
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, u16 HighThreshold, u16 LowThreshold);
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel);
+void ADC_TempSensorCmd(FunctionalState NewState);
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, u8 ADC_FLAG);
+void ADC_ClearFlag(ADC_TypeDef* ADCx, u8 ADC_FLAG);
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, u16 ADC_IT);
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, u16 ADC_IT);
+
+#endif /*__STM32F10x_ADC_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_bkp.h b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_bkp.h
new file mode 100644
index 0000000..82224d1
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_bkp.h
@@ -0,0 +1,73 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_bkp.h
+* Author : MCD Application Team
+* Date First Issued : 09/29/2006
+* Description : This file contains all the functions prototypes for the
+* BKP firmware library.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_BKP_H
+#define __STM32F10x_BKP_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Tamper Pin active level*/
+#define BKP_TamperPinLevel_High ((u16)0x0000)
+#define BKP_TamperPinLevel_Low ((u16)0x0001)
+
+#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) ((LEVEL == BKP_TamperPinLevel_High) || \
+ (LEVEL == BKP_TamperPinLevel_Low))
+
+/* Data Backup Register */
+#define BKP_DR1 ((u16)0x0004)
+#define BKP_DR2 ((u16)0x0008)
+#define BKP_DR3 ((u16)0x000C)
+#define BKP_DR4 ((u16)0x0010)
+#define BKP_DR5 ((u16)0x0014)
+#define BKP_DR6 ((u16)0x0018)
+#define BKP_DR7 ((u16)0x001C)
+#define BKP_DR8 ((u16)0x0020)
+#define BKP_DR9 ((u16)0x0024)
+#define BKP_DR10 ((u16)0x0028)
+
+#define IS_BKP_DR(DR) ((DR == BKP_DR1) || (DR == BKP_DR2) || (DR == BKP_DR3) || \
+ (DR == BKP_DR4) || (DR == BKP_DR5) || (DR == BKP_DR6) || \
+ (DR == BKP_DR7) || (DR == BKP_DR8) || (DR == BKP_DR9) || \
+ (DR == BKP_DR10))
+
+#define IS_BKP_CALIBRATION_VALUE(VALUE) (VALUE <= 0x7F)
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void BKP_DeInit(void);
+void BKP_TamperPinLevelConfig(u16 BKP_TamperPinLevel);
+void BKP_TamperPinCmd(FunctionalState NewState);
+void BKP_ITConfig(FunctionalState NewState);
+void BKP_RTCCalibrationClockOutputCmd(FunctionalState NewState);
+void BKP_SetRTCCalibrationValue(u8 CalibrationValue);
+void BKP_WriteBackupRegister(u16 BKP_DR, u16 Data);
+u16 BKP_ReadBackupRegister(u16 BKP_DR);
+FlagStatus BKP_GetFlagStatus(void);
+void BKP_ClearFlag(void);
+ITStatus BKP_GetITStatus(void);
+void BKP_ClearITPendingBit(void);
+
+#endif /* __STM32F10x_BKP_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_can.h b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_can.h
new file mode 100644
index 0000000..bd7f538
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_can.h
@@ -0,0 +1,269 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_can.h
+* Author : MCD Application Team
+* Date First Issued : 09/29/2006
+* Description : This file contains all the functions prototypes for the
+* CAN firmware library.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CAN_H
+#define __STM32F10x_CAN_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* CAN init structure definition */
+typedef struct
+{
+ FunctionalState CAN_TTCM;
+ FunctionalState CAN_ABOM;
+ FunctionalState CAN_AWUM;
+ FunctionalState CAN_NART;
+ FunctionalState CAN_RFLM;
+ FunctionalState CAN_TXFP;
+ u8 CAN_Mode;
+ u8 CAN_SJW;
+ u8 CAN_BS1;
+ u8 CAN_BS2;
+ u8 CAN_Clock;
+ u16 CAN_Prescaler;
+} CAN_InitTypeDef;
+
+/* CAN filter init structure definition */
+typedef struct
+{
+ u8 CAN_FilterNumber;
+ u8 CAN_FilterMode;
+ u8 CAN_FilterScale;
+ u16 CAN_FilterIdHigh;
+ u16 CAN_FilterIdLow;
+ u16 CAN_FilterMaskIdHigh;
+ u16 CAN_FilterMaskIdLow;
+ u16 CAN_FilterFIFOAssignment;
+ FunctionalState CAN_FilterActivation;
+} CAN_FilterInitTypeDef;
+
+/* CAN Tx message structure definition */
+typedef struct
+{
+ u32 StdId;
+ u32 ExtId;
+ u8 IDE;
+ u8 RTR;
+ u8 DLC;
+ u8 Data[8];
+} CanTxMsg;
+
+/* CAN Rx message structure definition */
+typedef struct
+{
+ u32 StdId;
+ u32 ExtId;
+ u8 IDE;
+ u8 RTR;
+ u8 DLC;
+ u8 Data[8];
+ u8 FMI;
+} CanRxMsg;
+
+/* Exported constants --------------------------------------------------------*/
+
+/* CAN sleep constants */
+#define CANINITFAILED ((u8)0x00) /* CAN initialization failed */
+#define CANINITOK ((u8)0x01) /* CAN initialization failed */
+
+/* CAN operating mode */
+#define CAN_Mode_Normal ((u8)0x00) /* normal mode */
+#define CAN_Mode_LoopBack ((u8)0x01) /* loopback mode */
+#define CAN_Mode_Silent ((u8)0x02) /* silent mode */
+#define CAN_Mode_Silent_LoopBack ((u8)0x03) /* loopback combined with silent mode */
+
+#define IS_CAN_MODE(MODE) ((MODE == CAN_Mode_Normal) || (MODE == CAN_Mode_LoopBack)|| \
+ (MODE == CAN_Mode_Silent) || (MODE == CAN_Mode_Silent_LoopBack))
+
+/* CAN synchronisation jump width */
+#define CAN_SJW_0tq ((u8)0x00) /* 0 time quantum */
+#define CAN_SJW_1tq ((u8)0x01) /* 1 time quantum */
+#define CAN_SJW_2tq ((u8)0x02) /* 2 time quantum */
+#define CAN_SJW_3tq ((u8)0x03) /* 3 time quantum */
+
+#define IS_CAN_SJW(SJW) ((SJW == CAN_SJW_0tq) || (SJW == CAN_SJW_1tq)|| \
+ (SJW == CAN_SJW_2tq) || (SJW == CAN_SJW_3tq))
+
+/* time quantum in bit segment 1 */
+#define CAN_BS1_1tq ((u8)0x00) /* 1 time quantum */
+#define CAN_BS1_2tq ((u8)0x01) /* 2 time quantum */
+#define CAN_BS1_3tq ((u8)0x02) /* 3 time quantum */
+#define CAN_BS1_4tq ((u8)0x03) /* 4 time quantum */
+#define CAN_BS1_5tq ((u8)0x04) /* 5 time quantum */
+#define CAN_BS1_6tq ((u8)0x05) /* 6 time quantum */
+#define CAN_BS1_7tq ((u8)0x06) /* 7 time quantum */
+#define CAN_BS1_8tq ((u8)0x07) /* 8 time quantum */
+#define CAN_BS1_9tq ((u8)0x08) /* 9 time quantum */
+#define CAN_BS1_10tq ((u8)0x09) /* 10 time quantum */
+#define CAN_BS1_11tq ((u8)0x0A) /* 11 time quantum */
+#define CAN_BS1_12tq ((u8)0x0B) /* 12 time quantum */
+#define CAN_BS1_13tq ((u8)0x0C) /* 13 time quantum */
+#define CAN_BS1_14tq ((u8)0x0D) /* 14 time quantum */
+#define CAN_BS1_15tq ((u8)0x0E) /* 15 time quantum */
+#define CAN_BS1_16tq ((u8)0x0F) /* 16 time quantum */
+
+#define IS_CAN_BS1(BS1) (BS1 <= CAN_BS1_16tq)
+
+/* time quantum in bit segment 2 */
+#define CAN_BS2_1tq ((u8)0x00) /* 1 time quantum */
+#define CAN_BS2_2tq ((u8)0x01) /* 2 time quantum */
+#define CAN_BS2_3tq ((u8)0x02) /* 3 time quantum */
+#define CAN_BS2_4tq ((u8)0x03) /* 4 time quantum */
+#define CAN_BS2_5tq ((u8)0x04) /* 5 time quantum */
+#define CAN_BS2_6tq ((u8)0x05) /* 6 time quantum */
+#define CAN_BS2_7tq ((u8)0x06) /* 7 time quantum */
+#define CAN_BS2_8tq ((u8)0x07) /* 8 time quantum */
+
+#define IS_CAN_BS2(BS2) (BS2 <= CAN_BS2_8tq)
+
+/* CAN clock selected */
+#define CAN_Clock_8MHz ((u8)0x00) /* 8MHz XTAL clock selected */
+#define CAN_Clock_APB ((u8)0x01) /* APB clock selected */
+
+#define IS_CAN_CLOCK(CLOCK) ((CLOCK == CAN_Clock_8MHz) || (CLOCK == CAN_Clock_APB))
+
+/* CAN clock prescaler */
+#define IS_CAN_PRESCALER(PRESCALER) ((PRESCALER >= 1) && (PRESCALER <= 1024))
+
+/* CAN filter number */
+#define IS_CAN_FILTER_NUMBER(NUMBER) (NUMBER <= 13)
+
+/* CAN filter mode */
+#define CAN_FilterMode_IdMask ((u8)0x00) /* id/mask mode */
+#define CAN_FilterMode_IdList ((u8)0x01) /* identifier list mode */
+
+#define IS_CAN_FILTER_MODE(MODE) ((MODE == CAN_FilterMode_IdMask) || \
+ (MODE == CAN_FilterMode_IdList))
+
+/* CAN filter scale */
+#define CAN_FilterScale_16bit ((u8)0x00) /* 16-bit filter scale */
+#define CAN_FilterScale_32bit ((u8)0x01) /* 2-bit filter scale */
+
+#define IS_CAN_FILTER_SCALE(SCALE) ((SCALE == CAN_FilterScale_16bit) || \
+ (SCALE == CAN_FilterScale_32bit))
+
+/* CAN filter FIFO assignation */
+#define CAN_FilterFIFO0 ((u8)0x00) /* Filter FIFO 0 assignment for filter x */
+#define CAN_FilterFIFO1 ((u8)0x01) /* Filter FIFO 1 assignment for filter x */
+
+#define IS_CAN_FILTER_FIFO(FIFO) ((FIFO == CAN_FilterFIFO0) || \
+ (FIFO == CAN_FilterFIFO1))
+
+/* CAN Tx */
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) (TRANSMITMAILBOX <= ((u8)0x02))
+#define IS_CAN_STDID(STDID) (STDID <= ((u32)0x7FF))
+#define IS_CAN_EXTID(EXTID) (EXTID <= ((u32)0x3FFFF))
+#define IS_CAN_DLC(DLC) (DLC <= ((u8)0x08))
+
+/* CAN identifier type */
+#define CAN_ID_STD ((u32)0x00000000) /* Standard Id */
+#define CAN_ID_EXT ((u32)0x00000004) /* Extended Id */
+
+#define IS_CAN_IDTYPE(IDTYPE) ((IDTYPE == CAN_ID_STD) || (IDTYPE == CAN_ID_EXT))
+
+/* CAN remote transmission request */
+#define CAN_RTR_DATA ((u32)0x00000000) /* Data frame */
+#define CAN_RTR_REMOTE ((u32)0x00000002) /* Remote frame */
+
+#define IS_CAN_RTR(RTR) ((RTR == CAN_RTR_DATA) || (RTR == CAN_RTR_REMOTE))
+
+/* CAN transmit constants */
+#define CANTXFAILED ((u8)0x00) /* CAN transmission failed */
+#define CANTXOK ((u8)0x01) /* CAN transmission succeeded */
+#define CANTXPENDING ((u8)0x02) /* CAN transmission pending */
+#define CAN_NO_MB ((u8)0x04) /* CAN cell did not provide an empty mailbox */
+
+/* CAN receive FIFO number constants */
+#define CAN_FIFO0 ((u8)0x00) /* CAN FIFO0 used to receive */
+#define CAN_FIFO1 ((u8)0x01) /* CAN FIFO1 used to receive */
+
+#define IS_CAN_FIFO(FIFO) ((FIFO == CAN_FIFO0) || (FIFO == CAN_FIFO1))
+
+/* CAN sleep constants */
+#define CANSLEEPFAILED ((u8)0x00) /* CAN did not enter the sleep mode */
+#define CANSLEEPOK ((u8)0x01) /* CAN entered the sleep mode */
+
+/* CAN wake up constants */
+#define CANWAKEUPFAILED ((u8)0x00) /* CAN did not leave the sleep mode */
+#define CANWAKEUPOK ((u8)0x01) /* CAN leaved the sleep mode */
+
+/* CAN flags */
+#define CAN_FLAG_EWG ((u32)0x00000001) /* Error Warning Flag */
+#define CAN_FLAG_EPV ((u32)0x00000002) /* Error Passive Flag */
+#define CAN_FLAG_BOF ((u32)0x00000004) /* Bus-Off Flag */
+
+#define IS_CAN_FLAG(FLAG) ((FLAG == CAN_FLAG_EWG) || (FLAG == CAN_FLAG_EPV) ||\
+ (FLAG == CAN_FLAG_BOF))
+
+/* CAN interrupts */
+#define CAN_IT_RQCP0 ((u8)0x05) /* Request completed mailbox 0 */
+#define CAN_IT_RQCP1 ((u8)0x06) /* Request completed mailbox 1 */
+#define CAN_IT_RQCP2 ((u8)0x07) /* Request completed mailbox 2 */
+#define CAN_IT_TME ((u32)0x00000001) /* Transmit mailbox empty */
+#define CAN_IT_FMP0 ((u32)0x00000002) /* FIFO 0 message pending */
+#define CAN_IT_FF0 ((u32)0x00000004) /* FIFO 0 full */
+#define CAN_IT_FOV0 ((u32)0x00000008) /* FIFO 0 overrun */
+#define CAN_IT_FMP1 ((u32)0x00000010) /* FIFO 1 message pending */
+#define CAN_IT_FF1 ((u32)0x00000020) /* FIFO 1 full */
+#define CAN_IT_FOV1 ((u32)0x00000040) /* FIFO 1 overrun */
+#define CAN_IT_EWG ((u32)0x00000100) /* Error warning */
+#define CAN_IT_EPV ((u32)0x00000200) /* Error passive */
+#define CAN_IT_BOF ((u32)0x00000400) /* Bus-off */
+#define CAN_IT_LEC ((u32)0x00000800) /* Last error code */
+#define CAN_IT_ERR ((u32)0x00008000) /* Error */
+#define CAN_IT_WKU ((u32)0x00010000) /* Wake-up */
+#define CAN_IT_SLK ((u32)0x00020000) /* Sleep */
+
+#define IS_CAN_IT(IT) ((IT == CAN_IT_RQCP0) || (IT == CAN_IT_RQCP1) ||\
+ (IT == CAN_IT_RQCP2) || (IT == CAN_IT_TME) ||\
+ (IT == CAN_IT_FMP0) || (IT == CAN_IT_FF0) ||\
+ (IT == CAN_IT_FOV0) || (IT == CAN_IT_FMP1) ||\
+ (IT == CAN_IT_FF1) || (IT == CAN_IT_FOV1) ||\
+ (IT == CAN_IT_EWG) || (IT == CAN_IT_EPV) ||\
+ (IT == CAN_IT_BOF) || (IT == CAN_IT_LEC) ||\
+ (IT == CAN_IT_ERR) || (IT == CAN_IT_WKU) ||\
+ (IT == CAN_IT_SLK))
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported function protypes ----------------------------------------------- */
+void CAN_DeInit(void);
+u8 CAN_Init(CAN_InitTypeDef* CAN_InitStruct);
+void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
+void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
+void CAN_ITConfig(u32 CAN_IT, FunctionalState NewState);
+u8 CAN_Transmit(CanTxMsg* TxMessage);
+u32 CAN_TransmitStatus(u8 TransmitMailbox);
+void CAN_CancelTransmit(u8 Mailbox);
+void CAN_FIFORelease(u8 FIFONumber);
+u8 CAN_MessagePending(u8 FIFONumber);
+void CAN_Receive(u8 FIFONumber, CanRxMsg* RxMessage);
+u8 CAN_Sleep(void);
+u8 CAN_WakeUp(void);
+FlagStatus CAN_GetFlagStatus(u32 CAN_FLAG);
+void CAN_ClearFlag(u32 CAN_FLAG);
+ITStatus CAN_GetITStatus(u32 CAN_IT);
+void CAN_ClearITPendingBit(u32 CAN_IT);
+
+#endif /* __STM32F10x_CAN_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_dma.h b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_dma.h
new file mode 100644
index 0000000..95274ad
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_dma.h
@@ -0,0 +1,224 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_dma.h
+* Author : MCD Application Team
+* Date First Issued : 09/29/2006
+* Description : This file contains all the functions prototypes for the
+* DMA firmware library.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_DMA_H
+#define __STM32F10x_DMA_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* DMA Init structure definition */
+typedef struct
+{
+ u32 DMA_PeripheralBaseAddr;
+ u32 DMA_MemoryBaseAddr;
+ u32 DMA_DIR;
+ u32 DMA_BufferSize;
+ u32 DMA_PeripheralInc;
+ u32 DMA_MemoryInc;
+ u32 DMA_PeripheralDataSize;
+ u32 DMA_MemoryDataSize;
+ u32 DMA_Mode;
+ u32 DMA_Priority;
+ u32 DMA_M2M;
+}DMA_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/* DMA data transfer direction -----------------------------------------------*/
+#define DMA_DIR_PeripheralDST ((u32)0x00000010)
+#define DMA_DIR_PeripheralSRC ((u32)0x00000000)
+
+#define IS_DMA_DIR(DIR) ((DIR == DMA_DIR_PeripheralDST) || \
+ (DIR == DMA_DIR_PeripheralSRC))
+
+/* DMA peripheral incremented mode -------------------------------------------*/
+#define DMA_PeripheralInc_Enable ((u32)0x00000040)
+#define DMA_PeripheralInc_Disable ((u32)0x00000000)
+
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) ((STATE == DMA_PeripheralInc_Enable) || \
+ (STATE == DMA_PeripheralInc_Disable))
+
+/* DMA memory incremented mode -----------------------------------------------*/
+#define DMA_MemoryInc_Enable ((u32)0x00000080)
+#define DMA_MemoryInc_Disable ((u32)0x00000000)
+
+#define IS_DMA_MEMORY_INC_STATE(STATE) ((STATE == DMA_MemoryInc_Enable) || \
+ (STATE == DMA_MemoryInc_Disable))
+
+/* DMA peripheral data size --------------------------------------------------*/
+#define DMA_PeripheralDataSize_Byte ((u32)0x00000000)
+#define DMA_PeripheralDataSize_HalfWord ((u32)0x00000100)
+#define DMA_PeripheralDataSize_Word ((u32)0x00000200)
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) ((SIZE == DMA_PeripheralDataSize_Byte) || \
+ (SIZE == DMA_PeripheralDataSize_HalfWord) || \
+ (SIZE == DMA_PeripheralDataSize_Word))
+
+/* DMA memory data size ------------------------------------------------------*/
+#define DMA_MemoryDataSize_Byte ((u32)0x00000000)
+#define DMA_MemoryDataSize_HalfWord ((u32)0x00000400)
+#define DMA_MemoryDataSize_Word ((u32)0x00000800)
+
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) ((SIZE == DMA_MemoryDataSize_Byte) || \
+ (SIZE == DMA_MemoryDataSize_HalfWord) || \
+ (SIZE == DMA_MemoryDataSize_Word))
+
+/* DMA circular/normal mode --------------------------------------------------*/
+#define DMA_Mode_Circular ((u32)0x00000020)
+#define DMA_Mode_Normal ((u32)0x00000000)
+
+#define IS_DMA_MODE(MODE) ((MODE == DMA_Mode_Circular) || (MODE == DMA_Mode_Normal))
+
+/* DMA priority level --------------------------------------------------------*/
+#define DMA_Priority_VeryHigh ((u32)0x00003000)
+#define DMA_Priority_High ((u32)0x00002000)
+#define DMA_Priority_Medium ((u32)0x00001000)
+#define DMA_Priority_Low ((u32)0x00000000)
+
+#define IS_DMA_PRIORITY(PRIORITY) ((PRIORITY == DMA_Priority_VeryHigh) || \
+ (PRIORITY == DMA_Priority_High) || \
+ (PRIORITY == DMA_Priority_Medium) || \
+ (PRIORITY == DMA_Priority_Low))
+
+/* DMA memory to memory ------------------------------------------------------*/
+#define DMA_M2M_Enable ((u32)0x00004000)
+#define DMA_M2M_Disable ((u32)0x00000000)
+
+#define IS_DMA_M2M_STATE(STATE) ((STATE == DMA_M2M_Enable) || (STATE == DMA_M2M_Disable))
+
+/* DMA interrupts definition -------------------------------------------------*/
+#define DMA_IT_TC ((u32)0x00000002)
+#define DMA_IT_HT ((u32)0x00000004)
+#define DMA_IT_TE ((u32)0x00000008)
+
+#define IS_DMA_CONFIG_IT(IT) (((IT & 0xFFFFFFF1) == 0x00) && (IT != 0x00))
+
+#define DMA_IT_GL1 ((u32)0x00000001)
+#define DMA_IT_TC1 ((u32)0x00000002)
+#define DMA_IT_HT1 ((u32)0x00000004)
+#define DMA_IT_TE1 ((u32)0x00000008)
+#define DMA_IT_GL2 ((u32)0x00000010)
+#define DMA_IT_TC2 ((u32)0x00000020)
+#define DMA_IT_HT2 ((u32)0x00000040)
+#define DMA_IT_TE2 ((u32)0x00000080)
+#define DMA_IT_GL3 ((u32)0x00000100)
+#define DMA_IT_TC3 ((u32)0x00000200)
+#define DMA_IT_HT3 ((u32)0x00000400)
+#define DMA_IT_TE3 ((u32)0x00000800)
+#define DMA_IT_GL4 ((u32)0x00001000)
+#define DMA_IT_TC4 ((u32)0x00002000)
+#define DMA_IT_HT4 ((u32)0x00004000)
+#define DMA_IT_TE4 ((u32)0x00008000)
+#define DMA_IT_GL5 ((u32)0x00010000)
+#define DMA_IT_TC5 ((u32)0x00020000)
+#define DMA_IT_HT5 ((u32)0x00040000)
+#define DMA_IT_TE5 ((u32)0x00080000)
+#define DMA_IT_GL6 ((u32)0x00100000)
+#define DMA_IT_TC6 ((u32)0x00200000)
+#define DMA_IT_HT6 ((u32)0x00400000)
+#define DMA_IT_TE6 ((u32)0x00800000)
+#define DMA_IT_GL7 ((u32)0x01000000)
+#define DMA_IT_TC7 ((u32)0x02000000)
+#define DMA_IT_HT7 ((u32)0x04000000)
+#define DMA_IT_TE7 ((u32)0x08000000)
+
+#define IS_DMA_CLEAR_IT(IT) (((IT & 0xF0000000) == 0x00) && (IT != 0x00))
+#define IS_DMA_GET_IT(IT) ((IT == DMA_IT_GL1) || (IT == DMA_IT_TC1) || \
+ (IT == DMA_IT_HT1) || (IT == DMA_IT_TE1) || \
+ (IT == DMA_IT_GL2) || (IT == DMA_IT_TC2) || \
+ (IT == DMA_IT_HT2) || (IT == DMA_IT_TE2) || \
+ (IT == DMA_IT_GL3) || (IT == DMA_IT_TC3) || \
+ (IT == DMA_IT_HT3) || (IT == DMA_IT_TE3) || \
+ (IT == DMA_IT_GL4) || (IT == DMA_IT_TC4) || \
+ (IT == DMA_IT_HT4) || (IT == DMA_IT_TE4) || \
+ (IT == DMA_IT_GL5) || (IT == DMA_IT_TC5) || \
+ (IT == DMA_IT_HT5) || (IT == DMA_IT_TE5) || \
+ (IT == DMA_IT_GL6) || (IT == DMA_IT_TC6) || \
+ (IT == DMA_IT_HT6) || (IT == DMA_IT_TE6) || \
+ (IT == DMA_IT_GL7) || (IT == DMA_IT_TC7) || \
+ (IT == DMA_IT_HT7) || (IT == DMA_IT_TE7))
+
+/* DMA flags definition ------------------------------------------------------*/
+#define DMA_FLAG_GL1 ((u32)0x00000001)
+#define DMA_FLAG_TC1 ((u32)0x00000002)
+#define DMA_FLAG_HT1 ((u32)0x00000004)
+#define DMA_FLAG_TE1 ((u32)0x00000008)
+#define DMA_FLAG_GL2 ((u32)0x00000010)
+#define DMA_FLAG_TC2 ((u32)0x00000020)
+#define DMA_FLAG_HT2 ((u32)0x00000040)
+#define DMA_FLAG_TE2 ((u32)0x00000080)
+#define DMA_FLAG_GL3 ((u32)0x00000100)
+#define DMA_FLAG_TC3 ((u32)0x00000200)
+#define DMA_FLAG_HT3 ((u32)0x00000400)
+#define DMA_FLAG_TE3 ((u32)0x00000800)
+#define DMA_FLAG_GL4 ((u32)0x00001000)
+#define DMA_FLAG_TC4 ((u32)0x00002000)
+#define DMA_FLAG_HT4 ((u32)0x00004000)
+#define DMA_FLAG_TE4 ((u32)0x00008000)
+#define DMA_FLAG_GL5 ((u32)0x00010000)
+#define DMA_FLAG_TC5 ((u32)0x00020000)
+#define DMA_FLAG_HT5 ((u32)0x00040000)
+#define DMA_FLAG_TE5 ((u32)0x00080000)
+#define DMA_FLAG_GL6 ((u32)0x00100000)
+#define DMA_FLAG_TC6 ((u32)0x00200000)
+#define DMA_FLAG_HT6 ((u32)0x00400000)
+#define DMA_FLAG_TE6 ((u32)0x00800000)
+#define DMA_FLAG_GL7 ((u32)0x01000000)
+#define DMA_FLAG_TC7 ((u32)0x02000000)
+#define DMA_FLAG_HT7 ((u32)0x04000000)
+#define DMA_FLAG_TE7 ((u32)0x08000000)
+
+#define IS_DMA_CLEAR_FLAG(FLAG) (((FLAG & 0xF0000000) == 0x00) && (FLAG != 0x00))
+#define IS_DMA_GET_FLAG(FLAG) ((FLAG == DMA_FLAG_GL1) || (FLAG == DMA_FLAG_TC1) || \
+ (FLAG == DMA_FLAG_HT1) || (FLAG == DMA_FLAG_TE1) || \
+ (FLAG == DMA_FLAG_GL2) || (FLAG == DMA_FLAG_TC2) || \
+ (FLAG == DMA_FLAG_HT2) || (FLAG == DMA_FLAG_TE2) || \
+ (FLAG == DMA_FLAG_GL3) || (FLAG == DMA_FLAG_TC3) || \
+ (FLAG == DMA_FLAG_HT3) || (FLAG == DMA_FLAG_TE3) || \
+ (FLAG == DMA_FLAG_GL4) || (FLAG == DMA_FLAG_TC4) || \
+ (FLAG == DMA_FLAG_HT4) || (FLAG == DMA_FLAG_TE4) || \
+ (FLAG == DMA_FLAG_GL5) || (FLAG == DMA_FLAG_TC5) || \
+ (FLAG == DMA_FLAG_HT5) || (FLAG == DMA_FLAG_TE5) || \
+ (FLAG == DMA_FLAG_GL6) || (FLAG == DMA_FLAG_TC6) || \
+ (FLAG == DMA_FLAG_HT6) || (FLAG == DMA_FLAG_TE6) || \
+ (FLAG == DMA_FLAG_GL7) || (FLAG == DMA_FLAG_TC7) || \
+ (FLAG == DMA_FLAG_HT7) || (FLAG == DMA_FLAG_TE7))
+
+/* DMA Buffer Size -----------------------------------------------------------*/
+#define IS_DMA_BUFFER_SIZE(SIZE) ((SIZE >= 0x1) && (SIZE < 0x10000))
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void DMA_DeInit(DMA_Channel_TypeDef* DMA_Channelx);
+void DMA_Init(DMA_Channel_TypeDef* DMA_Channelx, DMA_InitTypeDef* DMA_InitStruct);
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
+void DMA_Cmd(DMA_Channel_TypeDef* DMA_Channelx, FunctionalState NewState);
+void DMA_ITConfig(DMA_Channel_TypeDef* DMA_Channelx, u32 DMA_IT, FunctionalState NewState);
+u16 DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMA_Channelx);
+FlagStatus DMA_GetFlagStatus(u32 DMA_FLAG);
+void DMA_ClearFlag(u32 DMA_FLAG);
+ITStatus DMA_GetITStatus(u32 DMA_IT);
+void DMA_ClearITPendingBit(u32 DMA_IT);
+
+#endif /*__STM32F10x_DMA_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_exti.h b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_exti.h
new file mode 100644
index 0000000..2c6d4b6
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_exti.h
@@ -0,0 +1,111 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_exti.h
+* Author : MCD Application Team
+* Date First Issued : 09/29/2006
+* Description : This file contains all the functions prototypes for the
+* EXTI firmware library.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_EXTI_H
+#define __STM32F10x_EXTI_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* EXTI mode enumeration -----------------------------------------------------*/
+typedef enum
+{
+ EXTI_Mode_Interrupt = 0x00,
+ EXTI_Mode_Event = 0x04
+}EXTIMode_TypeDef;
+
+#define IS_EXTI_MODE(MODE) ((MODE == EXTI_Mode_Interrupt) || (MODE == EXTI_Mode_Event))
+
+/* EXTI Trigger enumeration --------------------------------------------------*/
+typedef enum
+{
+ EXTI_Trigger_Rising = 0x08,
+ EXTI_Trigger_Falling = 0x0C,
+ EXTI_Trigger_Rising_Falling = 0x10
+}EXTITrigger_TypeDef;
+
+#define IS_EXTI_TRIGGER(TRIGGER) ((TRIGGER == EXTI_Trigger_Rising) || \
+ (TRIGGER == EXTI_Trigger_Falling) || \
+ (TRIGGER == EXTI_Trigger_Rising_Falling))
+
+/* EXTI Init Structure definition --------------------------------------------*/
+typedef struct
+{
+ u32 EXTI_Line;
+ EXTIMode_TypeDef EXTI_Mode;
+ EXTITrigger_TypeDef EXTI_Trigger;
+ FunctionalState EXTI_LineCmd;
+}EXTI_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/* EXTI Lines ----------------------------------------------------------------*/
+#define EXTI_Line0 ((u32)0x00001) /* External interrupt line 0 */
+#define EXTI_Line1 ((u32)0x00002) /* External interrupt line 1 */
+#define EXTI_Line2 ((u32)0x00004) /* External interrupt line 2 */
+#define EXTI_Line3 ((u32)0x00008) /* External interrupt line 3 */
+#define EXTI_Line4 ((u32)0x00010) /* External interrupt line 4 */
+#define EXTI_Line5 ((u32)0x00020) /* External interrupt line 5 */
+#define EXTI_Line6 ((u32)0x00040) /* External interrupt line 6 */
+#define EXTI_Line7 ((u32)0x00080) /* External interrupt line 7 */
+#define EXTI_Line8 ((u32)0x00100) /* External interrupt line 8 */
+#define EXTI_Line9 ((u32)0x00200) /* External interrupt line 9 */
+#define EXTI_Line10 ((u32)0x00400) /* External interrupt line 10 */
+#define EXTI_Line11 ((u32)0x00800) /* External interrupt line 11 */
+#define EXTI_Line12 ((u32)0x01000) /* External interrupt line 12 */
+#define EXTI_Line13 ((u32)0x02000) /* External interrupt line 13 */
+#define EXTI_Line14 ((u32)0x04000) /* External interrupt line 14 */
+#define EXTI_Line15 ((u32)0x08000) /* External interrupt line 15 */
+#define EXTI_Line16 ((u32)0x10000) /* External interrupt line 16
+ Connected to the PVD Output */
+#define EXTI_Line17 ((u32)0x20000) /* External interrupt line 17
+ Connected to the RTC Alarm event */
+#define EXTI_Line18 ((u32)0x40000) /* External interrupt line 18
+ Connected to the USB Wakeup from
+ suspend event */
+
+#define IS_EXTI_LINE(LINE) (((LINE & (u32)0xFFF80000) == 0x00) && (LINE != (u16)0x00))
+
+#define IS_GET_EXTI_LINE(LINE) ((LINE == EXTI_Line0) || (LINE == EXTI_Line1) || \
+ (LINE == EXTI_Line2) || (LINE == EXTI_Line3) || \
+ (LINE == EXTI_Line4) || (LINE == EXTI_Line5) || \
+ (LINE == EXTI_Line6) || (LINE == EXTI_Line7) || \
+ (LINE == EXTI_Line8) || (LINE == EXTI_Line9) || \
+ (LINE == EXTI_Line10) || (LINE == EXTI_Line11) || \
+ (LINE == EXTI_Line12) || (LINE == EXTI_Line13) || \
+ (LINE == EXTI_Line14) || (LINE == EXTI_Line15) || \
+ (LINE == EXTI_Line16) || (LINE == EXTI_Line17) || \
+ (LINE == EXTI_Line18))
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void EXTI_DeInit(void);
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_GenerateSWInterrupt(u32 EXTI_Line);
+FlagStatus EXTI_GetFlagStatus(u32 EXTI_Line);
+void EXTI_ClearFlag(u32 EXTI_Line);
+ITStatus EXTI_GetITStatus(u32 EXTI_Line);
+void EXTI_ClearITPendingBit(u32 EXTI_Line);
+
+#endif /* __STM32F10x_EXTI_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_gpio.h b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_gpio.h
new file mode 100644
index 0000000..bbe59f5
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_gpio.h
@@ -0,0 +1,195 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_gpio.h
+* Author : MCD Application Team
+* Date First Issued : 09/29/2006
+* Description : This file contains all the functions prototypes for the
+* GPIO firmware library.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_GPIO_H
+#define __STM32F10x_GPIO_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Output Maximum frequency selection ----------------------------------------*/
+typedef enum
+{
+ GPIO_Speed_10MHz = 1,
+ GPIO_Speed_2MHz,
+ GPIO_Speed_50MHz
+}GPIOSpeed_TypeDef;
+
+#define IS_GPIO_SPEED(SPEED) ((SPEED == GPIO_Speed_10MHz) || (SPEED == GPIO_Speed_2MHz) || \
+ (SPEED == GPIO_Speed_50MHz))
+
+/* Configuration Mode enumeration --------------------------------------------*/
+typedef enum
+{ GPIO_Mode_AIN = 0x0,
+ GPIO_Mode_IN_FLOATING = 0x04,
+ GPIO_Mode_IPD = 0x28,
+ GPIO_Mode_IPU = 0x48,
+ GPIO_Mode_Out_OD = 0x14,
+ GPIO_Mode_Out_PP = 0x10,
+ GPIO_Mode_AF_OD = 0x1C,
+ GPIO_Mode_AF_PP = 0x18
+}GPIOMode_TypeDef;
+
+#define IS_GPIO_MODE(MODE) ((MODE == GPIO_Mode_AIN) || (MODE == GPIO_Mode_IN_FLOATING) || \
+ (MODE == GPIO_Mode_IPD) || (MODE == GPIO_Mode_IPU) || \
+ (MODE == GPIO_Mode_Out_OD) || (MODE == GPIO_Mode_Out_PP) || \
+ (MODE == GPIO_Mode_AF_OD) || (MODE == GPIO_Mode_AF_PP))
+
+/* GPIO Init structure definition */
+typedef struct
+{
+ u16 GPIO_Pin;
+ GPIOSpeed_TypeDef GPIO_Speed;
+ GPIOMode_TypeDef GPIO_Mode;
+}GPIO_InitTypeDef;
+
+/* Bit_SET and Bit_RESET enumeration -----------------------------------------*/
+typedef enum
+{ Bit_RESET = 0,
+ Bit_SET
+}BitAction;
+#define IS_GPIO_BIT_ACTION(ACTION) ((ACTION == Bit_RESET) || (ACTION == Bit_SET))
+
+/* Exported constants --------------------------------------------------------*/
+/* GPIO pins define ----------------------------------------------------------*/
+#define GPIO_Pin_0 ((u16)0x0001) /* Pin 0 selected */
+#define GPIO_Pin_1 ((u16)0x0002) /* Pin 1 selected */
+#define GPIO_Pin_2 ((u16)0x0004) /* Pin 2 selected */
+#define GPIO_Pin_3 ((u16)0x0008) /* Pin 3 selected */
+#define GPIO_Pin_4 ((u16)0x0010) /* Pin 4 selected */
+#define GPIO_Pin_5 ((u16)0x0020) /* Pin 5 selected */
+#define GPIO_Pin_6 ((u16)0x0040) /* Pin 6 selected */
+#define GPIO_Pin_7 ((u16)0x0080) /* Pin 7 selected */
+#define GPIO_Pin_8 ((u16)0x0100) /* Pin 8 selected */
+#define GPIO_Pin_9 ((u16)0x0200) /* Pin 9 selected */
+#define GPIO_Pin_10 ((u16)0x0400) /* Pin 10 selected */
+#define GPIO_Pin_11 ((u16)0x0800) /* Pin 11 selected */
+#define GPIO_Pin_12 ((u16)0x1000) /* Pin 12 selected */
+#define GPIO_Pin_13 ((u16)0x2000) /* Pin 13 selected */
+#define GPIO_Pin_14 ((u16)0x4000) /* Pin 14 selected */
+#define GPIO_Pin_15 ((u16)0x8000) /* Pin 15 selected */
+#define GPIO_Pin_All ((u16)0xFFFF) /* All pins selected */
+
+#define IS_GPIO_PIN(PIN) (((PIN & (u16)0x00) == 0x00) && (PIN != (u16)0x00))
+
+/* GPIO Remap define ---------------------------------------------------------*/
+#define GPIO_Remap_SPI1 ((u32)0x00000001) /* SPI1 Alternate Function mapping */
+#define GPIO_Remap_I2C1 ((u32)0x00000002) /* I2C1 Alternate Function mapping */
+#define GPIO_Remap_USART1 ((u32)0x00000004) /* USART1 Alternate Function mapping */
+#define GPIO_Remap_USART2 ((u32)0x00000008) /* USART2 Alternate Function mapping */
+#define GPIO_PartialRemap_USART3 ((u32)0x00140010) /* USART3 Partial Alternate Function mapping */
+#define GPIO_FullRemap_USART3 ((u32)0x00140030) /* USART3 Full Alternate Function mapping */
+#define GPIO_PartialRemap_TIM1 ((u32)0x00160040) /* TIM1 Partial Alternate Function mapping */
+#define GPIO_FullRemap_TIM1 ((u32)0x001600C0) /* TIM1 Full Alternate Function mapping */
+#define GPIO_PartialRemap1_TIM2 ((u32)0x00180100) /* TIM2 Partial1 Alternate Function mapping */
+#define GPIO_PartialRemap2_TIM2 ((u32)0x00180200) /* TIM2 Partial2 Alternate Function mapping */
+#define GPIO_FullRemap_TIM2 ((u32)0x00180300) /* TIM2 Full Alternate Function mapping */
+#define GPIO_PartialRemap_TIM3 ((u32)0x001A0800) /* TIM3 Partial Alternate Function mapping */
+#define GPIO_FullRemap_TIM3 ((u32)0x001A0C00) /* TIM3 Full Alternate Function mapping */
+#define GPIO_Remap_TIM4 ((u32)0x00001000) /* TIM4 Alternate Function mapping */
+#define GPIO_Remap1_CAN ((u32)0x001D2000) /* CAN Alternate Function mapping */
+#define GPIO_Remap2_CAN ((u32)0x001D6000) /* CAN Alternate Function mapping */
+#define GPIO_Remap_PD01 ((u32)0x00008000) /* PD01 Alternate Function mapping */
+#define GPIO_Remap_SWJ_NoJTRST ((u32)0x00300100) /* Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
+#define GPIO_Remap_SWJ_JTAGDisable ((u32)0x00300200) /* JTAG-DP Disabled and SW-DP Enabled */
+#define GPIO_Remap_SWJ_Disable ((u32)0x00300400) /* Full SWJ Disabled (JTAG-DP + SW-DP) */
+
+#define IS_GPIO_REMAP(REMAP) ((REMAP == GPIO_Remap_SPI1) || (REMAP == GPIO_Remap_I2C1) || \
+ (REMAP == GPIO_Remap_USART1) || (REMAP == GPIO_Remap_USART2) || \
+ (REMAP == GPIO_PartialRemap_USART3) || (REMAP == GPIO_FullRemap_USART3) || \
+ (REMAP == GPIO_PartialRemap_TIM1) || (REMAP == GPIO_FullRemap_TIM1) || \
+ (REMAP == GPIO_PartialRemap1_TIM2) || (REMAP == GPIO_PartialRemap2_TIM2) || \
+ (REMAP == GPIO_FullRemap_TIM2) || (REMAP == GPIO_PartialRemap_TIM3) || \
+ (REMAP == GPIO_FullRemap_TIM3) || (REMAP == GPIO_Remap_TIM4) || \
+ (REMAP == GPIO_Remap1_CAN) || (REMAP == GPIO_Remap2_CAN) || \
+ (REMAP == GPIO_Remap_PD01) || (REMAP == GPIO_Remap_SWJ_NoJTRST) || \
+ (REMAP == GPIO_Remap_SWJ_JTAGDisable) || (REMAP == GPIO_Remap_SWJ_Disable))
+
+/* GPIO Port Sources ---------------------------------------------------------*/
+#define GPIO_PortSourceGPIOA ((u8)0x00)
+#define GPIO_PortSourceGPIOB ((u8)0x01)
+#define GPIO_PortSourceGPIOC ((u8)0x02)
+#define GPIO_PortSourceGPIOD ((u8)0x03)
+#define GPIO_PortSourceGPIOE ((u8)0x04)
+
+#define IS_GPIO_PORT_SOURCE(PORTSOURCE) ((PORTSOURCE == GPIO_PortSourceGPIOA) || \
+ (PORTSOURCE == GPIO_PortSourceGPIOB) || \
+ (PORTSOURCE == GPIO_PortSourceGPIOC) || \
+ (PORTSOURCE == GPIO_PortSourceGPIOD) || \
+ (PORTSOURCE == GPIO_PortSourceGPIOE))
+
+/* GPIO Pin sources ----------------------------------------------------------*/
+#define GPIO_PinSource0 ((u8)0x00)
+#define GPIO_PinSource1 ((u8)0x01)
+#define GPIO_PinSource2 ((u8)0x02)
+#define GPIO_PinSource3 ((u8)0x03)
+#define GPIO_PinSource4 ((u8)0x04)
+#define GPIO_PinSource5 ((u8)0x05)
+#define GPIO_PinSource6 ((u8)0x06)
+#define GPIO_PinSource7 ((u8)0x07)
+#define GPIO_PinSource8 ((u8)0x08)
+#define GPIO_PinSource9 ((u8)0x09)
+#define GPIO_PinSource10 ((u8)0x0A)
+#define GPIO_PinSource11 ((u8)0x0B)
+#define GPIO_PinSource12 ((u8)0x0C)
+#define GPIO_PinSource13 ((u8)0x0D)
+#define GPIO_PinSource14 ((u8)0x0E)
+#define GPIO_PinSource15 ((u8)0x0F)
+
+#define IS_GPIO_PIN_SOURCE(PINSOURCE) ((PINSOURCE == GPIO_PinSource0) || \
+ (PINSOURCE == GPIO_PinSource1) || \
+ (PINSOURCE == GPIO_PinSource2) || \
+ (PINSOURCE == GPIO_PinSource3) || \
+ (PINSOURCE == GPIO_PinSource4) || \
+ (PINSOURCE == GPIO_PinSource5) || \
+ (PINSOURCE == GPIO_PinSource6) || \
+ (PINSOURCE == GPIO_PinSource7) || \
+ (PINSOURCE == GPIO_PinSource8) || \
+ (PINSOURCE == GPIO_PinSource9) || \
+ (PINSOURCE == GPIO_PinSource10) || \
+ (PINSOURCE == GPIO_PinSource11) || \
+ (PINSOURCE == GPIO_PinSource12) || \
+ (PINSOURCE == GPIO_PinSource13) || \
+ (PINSOURCE == GPIO_PinSource14) || \
+ (PINSOURCE == GPIO_PinSource15))
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void GPIO_DeInit(GPIO_TypeDef* GPIOx);
+void GPIO_AFIODeInit(void);
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
+u8 GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin);
+u16 GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
+u8 GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin);
+u16 GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin, BitAction BitVal);
+void GPIO_Write(GPIO_TypeDef* GPIOx, u16 PortVal);
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, u16 GPIO_Pin);
+void GPIO_EventOutputConfig(u8 GPIO_PortSource, u8 GPIO_PinSource);
+void GPIO_EventOutputCmd(FunctionalState NewState);
+void GPIO_PinRemapConfig(u32 GPIO_Remap, FunctionalState NewState);
+void GPIO_EXTILineConfig(u8 GPIO_PortSource, u8 GPIO_PinSource);
+
+#endif /* __STM32F10x_GPIO_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_i2c.h b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_i2c.h
new file mode 100644
index 0000000..d0d000c
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_i2c.h
@@ -0,0 +1,286 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_i2c.h
+* Author : MCD Application Team
+* Date First Issued : 09/29/2006
+* Description : This file contains all the functions prototypes for the
+* I2C firmware library.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_I2C_H
+#define __STM32F10x_I2C_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* I2C Init structure definition */
+typedef struct
+{
+ u16 I2C_Mode;
+ u16 I2C_DutyCycle;
+ u16 I2C_OwnAddress1;
+ u16 I2C_Ack;
+ u16 I2C_AcknowledgedAddress;
+ u32 I2C_ClockSpeed;
+}I2C_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/* I2C modes */
+#define I2C_Mode_I2C ((u16)0x0000)
+#define I2C_Mode_SMBusDevice ((u16)0x0002)
+#define I2C_Mode_SMBusHost ((u16)0x000A)
+
+#define IS_I2C_MODE(MODE) ((MODE == I2C_Mode_I2C) || \
+ (MODE == I2C_Mode_SMBusDevice) || \
+ (MODE == I2C_Mode_SMBusHost))
+/* I2C duty cycle in fast mode */
+#define I2C_DutyCycle_16_9 ((u16)0x4000)
+#define I2C_DutyCycle_2 ((u16)0xBFFF)
+
+#define IS_I2C_DUTY_CYCLE(CYCLE) ((CYCLE == I2C_DutyCycle_16_9) || \
+ (CYCLE == I2C_DutyCycle_2))
+
+/* I2C cknowledgementy */
+#define I2C_Ack_Enable ((u16)0x0400)
+#define I2C_Ack_Disable ((u16)0x0000)
+
+#define IS_I2C_ACK_STATE(STATE) ((STATE == I2C_Ack_Enable) || \
+ (STATE == I2C_Ack_Disable))
+
+/* I2C transfer direction */
+#define I2C_Direction_Transmitter ((u8)0x00)
+#define I2C_Direction_Receiver ((u8)0x01)
+
+#define IS_I2C_DIRECTION(DIRECTION) ((DIRECTION == I2C_Direction_Transmitter) || \
+ (DIRECTION == I2C_Direction_Receiver))
+
+/* I2C acknowledged address defines */
+#define I2C_AcknowledgedAddress_7bit ((u16)0x4000)
+#define I2C_AcknowledgedAddress_10bit ((u16)0xC000)
+
+#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) ((ADDRESS == I2C_AcknowledgedAddress_7bit) || \
+ (ADDRESS == I2C_AcknowledgedAddress_10bit))
+
+/* I2C registers */
+#define I2C_Register_CR1 ((u8)0x00)
+#define I2C_Register_CR2 ((u8)0x04)
+#define I2C_Register_OAR1 ((u8)0x08)
+#define I2C_Register_OAR2 ((u8)0x0C)
+#define I2C_Register_DR ((u8)0x10)
+#define I2C_Register_SR1 ((u8)0x14)
+#define I2C_Register_SR2 ((u8)0x18)
+#define I2C_Register_CCR ((u8)0x1C)
+#define I2C_Register_TRISE ((u8)0x20)
+
+#define IS_I2C_REGISTER(REGISTER) ((REGISTER == I2C_Register_CR1) || \
+ (REGISTER == I2C_Register_CR2) || \
+ (REGISTER == I2C_Register_OAR1) || \
+ (REGISTER == I2C_Register_OAR2) || \
+ (REGISTER == I2C_Register_DR) || \
+ (REGISTER == I2C_Register_SR1) || \
+ (REGISTER == I2C_Register_SR2) || \
+ (REGISTER == I2C_Register_CCR) || \
+ (REGISTER == I2C_Register_TRISE))
+
+/* I2C SMBus alert pin level */
+#define I2C_SMBusAlert_Low ((u16)0x2000)
+#define I2C_SMBusAlert_High ((u16)0xCFFF)
+
+#define IS_I2C_SMBUS_ALERT(ALERT) ((ALERT == I2C_SMBusAlert_Low) || \
+ (ALERT == I2C_SMBusAlert_High))
+
+/* I2C PEC position */
+#define I2C_PECPosition_Next ((u16)0x0800)
+#define I2C_PECPosition_Current ((u16)0xF7FF)
+
+#define IS_I2C_PEC_POSITION(POSITION) ((POSITION == I2C_PECPosition_Next) || \
+ (POSITION == I2C_PECPosition_Current))
+
+/* I2C interrupts definition */
+#define I2C_IT_BUF ((u16)0x0400)
+#define I2C_IT_EVT ((u16)0x0200)
+#define I2C_IT_ERR ((u16)0x0100)
+
+#define IS_I2C_CONFIG_IT(IT) (((IT & (u16)0xF8FF) == 0x00) && (IT != 0x00))
+
+/* I2C interrupts definition */
+#define I2C_IT_SMBALERT ((u32)0x10008000)
+#define I2C_IT_TIMEOUT ((u32)0x10004000)
+#define I2C_IT_PECERR ((u32)0x10001000)
+#define I2C_IT_OVR ((u32)0x10000800)
+#define I2C_IT_AF ((u32)0x10000400)
+#define I2C_IT_ARLO ((u32)0x10000200)
+#define I2C_IT_BERR ((u32)0x10000100)
+#define I2C_IT_TXE ((u32)0x00000080)
+#define I2C_IT_RXNE ((u32)0x00000040)
+#define I2C_IT_STOPF ((u32)0x60000010)
+#define I2C_IT_ADD10 ((u32)0x20000008)
+#define I2C_IT_BTF ((u32)0x60000004)
+#define I2C_IT_ADDR ((u32)0xA0000002)
+#define I2C_IT_SB ((u32)0x20000001)
+
+#define IS_I2C_CLEAR_IT(IT) ((IT == I2C_IT_SMBALERT) || (IT == I2C_IT_TIMEOUT) || \
+ (IT == I2C_IT_PECERR) || (IT == I2C_IT_OVR) || \
+ (IT == I2C_IT_AF) || (IT == I2C_IT_ARLO) || \
+ (IT == I2C_IT_BERR) || (IT == I2C_IT_STOPF) || \
+ (IT == I2C_IT_ADD10) || (IT == I2C_IT_BTF) || \
+ (IT == I2C_IT_ADDR) || (IT == I2C_IT_SB))
+
+#define IS_I2C_GET_IT(IT) ((IT == I2C_IT_SMBALERT) || (IT == I2C_IT_TIMEOUT) || \
+ (IT == I2C_IT_PECERR) || (IT == I2C_IT_OVR) || \
+ (IT == I2C_IT_AF) || (IT == I2C_IT_ARLO) || \
+ (IT == I2C_IT_BERR) || (IT == I2C_IT_TXE) || \
+ (IT == I2C_IT_RXNE) || (IT == I2C_IT_STOPF) || \
+ (IT == I2C_IT_ADD10) || (IT == I2C_IT_BTF) || \
+ (IT == I2C_IT_ADDR) || (IT == I2C_IT_SB))
+
+/* I2C flags definition */
+#define I2C_FLAG_DUALF ((u32)0x00800000)
+#define I2C_FLAG_SMBHOST ((u32)0x00400000)
+#define I2C_FLAG_SMBDEFAULT ((u32)0x00200000)
+#define I2C_FLAG_GENCALL ((u32)0x00100000)
+#define I2C_FLAG_TRA ((u32)0x00040000)
+#define I2C_FLAG_BUSY ((u32)0x00020000)
+#define I2C_FLAG_MSL ((u32)0x00010000)
+#define I2C_FLAG_SMBALERT ((u32)0x10008000)
+#define I2C_FLAG_TIMEOUT ((u32)0x10004000)
+#define I2C_FLAG_PECERR ((u32)0x10001000)
+#define I2C_FLAG_OVR ((u32)0x10000800)
+#define I2C_FLAG_AF ((u32)0x10000400)
+#define I2C_FLAG_ARLO ((u32)0x10000200)
+#define I2C_FLAG_BERR ((u32)0x10000100)
+#define I2C_FLAG_TXE ((u32)0x00000080)
+#define I2C_FLAG_RXNE ((u32)0x00000040)
+#define I2C_FLAG_STOPF ((u32)0x60000010)
+#define I2C_FLAG_ADD10 ((u32)0x20000008)
+#define I2C_FLAG_BTF ((u32)0x60000004)
+#define I2C_FLAG_ADDR ((u32)0xA0000002)
+#define I2C_FLAG_SB ((u32)0x20000001)
+
+#define IS_I2C_CLEAR_FLAG(FLAG) ((FLAG == I2C_FLAG_SMBALERT) || (FLAG == I2C_FLAG_TIMEOUT) || \
+ (FLAG == I2C_FLAG_PECERR) || (FLAG == I2C_FLAG_OVR) || \
+ (FLAG == I2C_FLAG_AF) || (FLAG == I2C_FLAG_ARLO) || \
+ (FLAG == I2C_FLAG_BERR) || (FLAG == I2C_FLAG_STOPF) || \
+ (FLAG == I2C_FLAG_ADD10) || (FLAG == I2C_FLAG_BTF) || \
+ (FLAG == I2C_FLAG_ADDR) || (FLAG == I2C_FLAG_SB))
+
+#define IS_I2C_GET_FLAG(FLAG) ((FLAG == I2C_FLAG_DUALF) || (FLAG == I2C_FLAG_SMBHOST) || \
+ (FLAG == I2C_FLAG_SMBDEFAULT) || (FLAG == I2C_FLAG_GENCALL) || \
+ (FLAG == I2C_FLAG_TRA) || (FLAG == I2C_FLAG_BUSY) || \
+ (FLAG == I2C_FLAG_MSL) || (FLAG == I2C_FLAG_SMBALERT) || \
+ (FLAG == I2C_FLAG_TIMEOUT) || (FLAG == I2C_FLAG_PECERR) || \
+ (FLAG == I2C_FLAG_OVR) || (FLAG == I2C_FLAG_AF) || \
+ (FLAG == I2C_FLAG_ARLO) || (FLAG == I2C_FLAG_BERR) || \
+ (FLAG == I2C_FLAG_TXE) || (FLAG == I2C_FLAG_RXNE) || \
+ (FLAG == I2C_FLAG_STOPF) || (FLAG == I2C_FLAG_ADD10) || \
+ (FLAG == I2C_FLAG_BTF) || (FLAG == I2C_FLAG_ADDR) || \
+ (FLAG == I2C_FLAG_SB))
+
+/* I2C Events */
+/* EV1 */
+#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((u32)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
+#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((u32)0x00020002) /* BUSY and ADDR flags */
+#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((u32)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
+#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((u32)0x00820000) /* DUALF and BUSY flags */
+#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((u32)0x00120000) /* GENCALL and BUSY flags */
+
+/* EV2 */
+#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((u32)0x00020040) /* BUSY and RXNE flags */
+
+/* EV3 */
+#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((u32)0x00060084) /* TRA, BUSY, TXE and BTF flags */
+
+/* EV4 */
+#define I2C_EVENT_SLAVE_STOP_DETECTED ((u32)0x00000010) /* STOPF flag */
+
+/* EV5 */
+#define I2C_EVENT_MASTER_MODE_SELECT ((u32)0x00030001) /* BUSY, MSL and SB flag */
+
+/* EV6 */
+#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((u32)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
+#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((u32)0x00030002) /* BUSY, MSL and ADDR flags */
+
+/* EV7 */
+#define I2C_EVENT_MASTER_BYTE_RECEIVED ((u32)0x00030040) /* BUSY, MSL and RXNE flags */
+
+/* EV8 */
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((u32)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
+
+/* EV9 */
+#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((u32)0x00030008) /* BUSY, MSL and ADD10 flags */
+
+/* EV3_1 */
+#define I2C_EVENT_SLAVE_ACK_FAILURE ((u32)0x00000400) /* AF flag */
+
+#define IS_I2C_EVENT(EVENT) ((EVENT == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
+ (EVENT == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
+ (EVENT == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
+ (EVENT == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
+ (EVENT == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
+ (EVENT == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
+ (EVENT == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
+ (EVENT == I2C_EVENT_SLAVE_STOP_DETECTED) || \
+ (EVENT == I2C_EVENT_MASTER_MODE_SELECT) || \
+ (EVENT == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
+ (EVENT == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
+ (EVENT == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
+ (EVENT == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
+ (EVENT == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
+ (EVENT == I2C_EVENT_SLAVE_ACK_FAILURE))
+
+/* I2C own address1 -----------------------------------------------------------*/
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (ADDRESS1 <= 0x3FF)
+/* I2C clock speed ------------------------------------------------------------*/
+#define IS_I2C_CLOCK_SPEED(SPEED) ((SPEED >= 0x1) && (SPEED <= 400000))
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void I2C_DeInit(I2C_TypeDef* I2Cx);
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, u8 Address);
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_ITConfig(I2C_TypeDef* I2Cx, u16 I2C_IT, FunctionalState NewState);
+void I2C_SendData(I2C_TypeDef* I2Cx, u8 Data);
+u8 I2C_ReceiveData(I2C_TypeDef* I2Cx);
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, u8 Address, u8 I2C_Direction);
+u16 I2C_ReadRegister(I2C_TypeDef* I2Cx, u8 I2C_Register);
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, u16 I2C_SMBusAlert);
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx);
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, u16 I2C_PECPosition);
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
+u8 I2C_GetPEC(I2C_TypeDef* I2Cx);
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, u16 I2C_DutyCycle);
+u32 I2C_GetLastEvent(I2C_TypeDef* I2Cx);
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, u32 I2C_EVENT);
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, u32 I2C_FLAG);
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, u32 I2C_FLAG);
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, u32 I2C_IT);
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, u32 I2C_IT);
+
+#endif /*__STM32F10x_I2C_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_it.h b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_it.h
new file mode 100644
index 0000000..90ed398
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_it.h
@@ -0,0 +1,86 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_it.h
+* Author : MCD Application Team
+* Date First Issued : 09/29/2006
+* Description : This file contains the headers of the interrupt handlers.
+********************************************************************************
+* History:
+* mm/dd/yyyy: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_IT_H
+#define __STM32F10x_IT_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_lib.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+void NMIException(void);
+void HardFaultException(void);
+void MemManageException(void);
+void BusFaultException(void);
+void UsageFaultException(void);
+void DebugMonitor(void);
+void SVCHandler(void);
+void PendSVC(void);
+void SysTickHandler(void);
+void WWDG_IRQHandler(void);
+void PVD_IRQHandler(void);
+void TAMPER_IRQHandler(void);
+void RTC_IRQHandler(void);
+void FLASH_IRQHandler(void);
+void RCC_IRQHandler(void);
+void EXTI0_IRQHandler(void);
+void EXTI1_IRQHandler(void);
+void EXTI2_IRQHandler(void);
+void EXTI3_IRQHandler(void);
+void EXTI4_IRQHandler(void);
+void DMAChannel1_IRQHandler(void);
+void DMAChannel2_IRQHandler(void);
+void DMAChannel3_IRQHandler(void);
+void DMAChannel4_IRQHandler(void);
+void DMAChannel5_IRQHandler(void);
+void DMAChannel6_IRQHandler(void);
+void DMAChannel7_IRQHandler(void);
+void ADC_IRQHandler(void);
+void USB_HP_CAN_TX_IRQHandler(void);
+void USB_LP_CAN_RX0_IRQHandler(void);
+void CAN_RX1_IRQHandler(void);
+void CAN_SCE_IRQHandler(void);
+void EXTI9_5_IRQHandler(void);
+void TIM1_BRK_IRQHandler(void);
+void TIM1_UP_IRQHandler(void);
+void TIM1_TRG_COM_IRQHandler(void);
+void TIM1_CC_IRQHandler(void);
+void TIM2_IRQHandler(void);
+void TIM3_IRQHandler(void);
+void TIM4_IRQHandler(void);
+void I2C1_EV_IRQHandler(void);
+void I2C1_ER_IRQHandler(void);
+void I2C2_EV_IRQHandler(void);
+void I2C2_ER_IRQHandler(void);
+void SPI1_IRQHandler(void);
+void SPI2_IRQHandler(void);
+void USART1_IRQHandler(void);
+void USART2_IRQHandler(void);
+void USART3_IRQHandler(void);
+void EXTI15_10_IRQHandler(void);
+void RTCAlarm_IRQHandler(void);
+void USBWakeUp_IRQHandler(void);
+
+#endif /* __STM32F10x_IT_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_iwdg.h b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_iwdg.h
new file mode 100644
index 0000000..7cfc6ed
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_iwdg.h
@@ -0,0 +1,73 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_iwdg.h
+* Author : MCD Application Team
+* Date First Issued : 09/29/2006
+* Description : This file contains all the functions prototypes for the
+* IWDG firmware library.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_IWDG_H
+#define __STM32F10x_IWDG_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Write access to IWDG_PR and IWDG_RLR registers */
+#define IWDG_WriteAccess_Enable ((u16)0x5555)
+#define IWDG_WriteAccess_Disable ((u16)0x0000)
+
+#define IS_IWDG_WRITE_ACCESS(ACCESS) ((ACCESS == IWDG_WriteAccess_Enable) || \
+ (ACCESS == IWDG_WriteAccess_Disable))
+
+/* IWDG prescaler */
+#define IWDG_Prescaler_4 ((u8)0x00)
+#define IWDG_Prescaler_8 ((u8)0x01)
+#define IWDG_Prescaler_16 ((u8)0x02)
+#define IWDG_Prescaler_32 ((u8)0x03)
+#define IWDG_Prescaler_64 ((u8)0x04)
+#define IWDG_Prescaler_128 ((u8)0x05)
+#define IWDG_Prescaler_256 ((u8)0x06)
+
+#define IS_IWDG_PRESCALER(PRESCALER) ((PRESCALER == IWDG_Prescaler_4) || \
+ (PRESCALER == IWDG_Prescaler_8) || \
+ (PRESCALER == IWDG_Prescaler_16) || \
+ (PRESCALER == IWDG_Prescaler_32) || \
+ (PRESCALER == IWDG_Prescaler_64) || \
+ (PRESCALER == IWDG_Prescaler_128)|| \
+ (PRESCALER == IWDG_Prescaler_256))
+
+/* IWDG Flag */
+#define IWDG_FLAG_PVU ((u16)0x0001)
+#define IWDG_FLAG_RVU ((u16)0x0002)
+
+#define IS_IWDG_FLAG(FLAG) ((FLAG == IWDG_FLAG_PVU) || (FLAG == IWDG_FLAG_RVU))
+
+#define IS_IWDG_RELOAD(RELOAD) (RELOAD <= 0xFFF)
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void IWDG_WriteAccessCmd(u16 IWDG_WriteAccess);
+void IWDG_SetPrescaler(u8 IWDG_Prescaler);
+void IWDG_SetReload(u16 Reload);
+void IWDG_ReloadCounter(void);
+void IWDG_Enable(void);
+FlagStatus IWDG_GetFlagStatus(u16 IWDG_FLAG);
+
+#endif /* __STM32F10x_IWDG_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_lib.h b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_lib.h
new file mode 100644
index 0000000..26d4e41
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_lib.h
@@ -0,0 +1,112 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_lib.h
+* Author : MCD Application Team
+* Date First Issued : 09/29/2006
+* Description : This file includes the peripherals header files in the
+* user application.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_LIB_H
+#define __STM32F10x_LIB_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+#ifdef _ADC
+ #include "stm32f10x_adc.h"
+#endif /*_ADC */
+
+#ifdef _BKP
+ #include "stm32f10x_bkp.h"
+#endif /*_BKP */
+
+#ifdef _CAN
+ #include "stm32f10x_can.h"
+#endif /*_CAN */
+
+#ifdef _DMA
+ #include "stm32f10x_dma.h"
+#endif /*_DMA */
+
+#ifdef _EXTI
+ #include "stm32f10x_exti.h"
+#endif /*_EXTI */
+
+#ifdef _FLASH
+ #include "stm32f10x_flash.h"
+#endif /*_FLASH */
+
+#ifdef _GPIO
+ #include "stm32f10x_gpio.h"
+#endif /*_GPIO */
+
+#ifdef _I2C
+ #include "stm32f10x_i2c.h"
+#endif /*_I2C */
+
+#ifdef _IWDG
+ #include "stm32f10x_iwdg.h"
+#endif /*_IWDG */
+
+#ifdef _NVIC
+ #include "stm32f10x_nvic.h"
+#endif /*_NVIC */
+
+#ifdef _PWR
+ #include "stm32f10x_pwr.h"
+#endif /*_PWR */
+
+#ifdef _RCC
+ #include "stm32f10x_rcc.h"
+#endif /*_RCC */
+
+#ifdef _RTC
+ #include "stm32f10x_rtc.h"
+#endif /*_RTC */
+
+#ifdef _SPI
+ #include "stm32f10x_spi.h"
+#endif /*_SPI */
+
+#ifdef _SysTick
+ #include "stm32f10x_systick.h"
+#endif /*_SysTick */
+
+#ifdef _TIM1
+ #include "stm32f10x_tim1.h"
+#endif /*_TIM1 */
+
+#ifdef _TIM
+ #include "stm32f10x_tim.h"
+#endif /*_TIM */
+
+#ifdef _USART
+ #include "stm32f10x_usart.h"
+#endif /*_USART */
+
+#ifdef _WWDG
+ #include "stm32f10x_wwdg.h"
+#endif /*_WWDG */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void debug(void);
+
+#endif /* __STM32F10x_LIB_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_map.h b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_map.h
new file mode 100644
index 0000000..1c83a4f
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_map.h
@@ -0,0 +1,865 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_map.h
+* Author : MCD Application Team
+* Date First Issued : 09/29/2006
+* Description : This file contains all the peripheral register's definitions
+* and memory mapping.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_MAP_H
+#define __STM32F10x_MAP_H
+
+#ifndef EXT
+ #define EXT extern
+#endif /* EXT */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_conf.h"
+#include "stm32f10x_type.h"
+#include "cortexm3_macro.h"
+
+/* Exported types ------------------------------------------------------------*/
+/******************************************************************************/
+/* IP registers structures */
+/******************************************************************************/
+
+/*------------------------ Analog to Digital Converter -----------------------*/
+typedef struct
+{
+ vu32 SR;
+ vu32 CR1;
+ vu32 CR2;
+ vu32 SMPR1;
+ vu32 SMPR2;
+ vu32 JOFR1;
+ vu32 JOFR2;
+ vu32 JOFR3;
+ vu32 JOFR4;
+ vu32 HTR;
+ vu32 LTR;
+ vu32 SQR1;
+ vu32 SQR2;
+ vu32 SQR3;
+ vu32 JSQR;
+ vu32 JDR1;
+ vu32 JDR2;
+ vu32 JDR3;
+ vu32 JDR4;
+ vu32 DR;
+} ADC_TypeDef;
+
+/*------------------------ Backup Registers ----------------------------------*/
+typedef struct
+{
+ u32 RESERVED0;
+ vu16 DR1;
+ u16 RESERVED1;
+ vu16 DR2;
+ u16 RESERVED2;
+ vu16 DR3;
+ u16 RESERVED3;
+ vu16 DR4;
+ u16 RESERVED4;
+ vu16 DR5;
+ u16 RESERVED5;
+ vu16 DR6;
+ u16 RESERVED6;
+ vu16 DR7;
+ u16 RESERVED7;
+ vu16 DR8;
+ u16 RESERVED8;
+ vu16 DR9;
+ u16 RESERVED9;
+ vu16 DR10;
+ u16 RESERVED10;
+ vu16 RTCCR;
+ u16 RESERVED11;
+ vu16 CR;
+ u16 RESERVED12;
+ vu16 CSR;
+ u16 RESERVED13;
+} BKP_TypeDef;
+
+/*------------------------ Controller Area Network ---------------------------*/
+typedef struct
+{
+ vu32 TIR;
+ vu32 TDTR;
+ vu32 TDLR;
+ vu32 TDHR;
+} CAN_TxMailBox_TypeDef;
+
+typedef struct
+{
+ vu32 RIR;
+ vu32 RDTR;
+ vu32 RDLR;
+ vu32 RDHR;
+} CAN_FIFOMailBox_TypeDef;
+
+typedef struct
+{
+ vu32 FR0;
+ vu32 FR1;
+} CAN_FilterRegister_TypeDef;
+
+typedef struct
+{
+ vu32 MCR;
+ vu32 MSR;
+ vu32 TSR;
+ vu32 RF0R;
+ vu32 RF1R;
+ vu32 IER;
+ vu32 ESR;
+ vu32 BTR;
+ u32 RESERVED0[88];
+ CAN_TxMailBox_TypeDef sTxMailBox[3];
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
+ u32 RESERVED1[12];
+ vu32 FMR;
+ vu32 FM0R;
+ u32 RESERVED2[1];
+ vu32 FS0R;
+ u32 RESERVED3[1];
+ vu32 FFA0R;
+ u32 RESERVED4[1];
+ vu32 FA0R;
+ u32 RESERVED5[8];
+ CAN_FilterRegister_TypeDef sFilterRegister[14];
+} CAN_TypeDef;
+
+/*------------------------ DMA Controller ------------------------------------*/
+typedef struct
+{
+ vu32 CCR;
+ vu32 CNDTR;
+ vu32 CPAR;
+ vu32 CMAR;
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ vu32 ISR;
+ vu32 IFCR;
+} DMA_TypeDef;
+
+/*------------------------ External Interrupt/Event Controller ---------------*/
+typedef struct
+{
+ vu32 IMR;
+ vu32 EMR;
+ vu32 RTSR;
+ vu32 FTSR;
+ vu32 SWIER;
+ vu32 PR;
+} EXTI_TypeDef;
+
+/*------------------------ FLASH and Option Bytes Registers ------------------*/
+typedef struct
+{
+ vu32 ACR;
+ vu32 KEYR;
+ vu32 OPTKEYR;
+ vu32 SR;
+ vu32 CR;
+ vu32 AR;
+ vu32 RESERVED;
+ vu32 OBR;
+ vu32 WRPR;
+} FLASH_TypeDef;
+
+typedef struct
+{
+ vu16 RDP;
+ vu16 USER;
+ vu16 Data0;
+ vu16 Data1;
+ vu16 WRP0;
+ vu16 WRP1;
+ vu16 WRP2;
+ vu16 WRP3;
+} OB_TypeDef;
+
+/*------------------------ General Purpose and Alternate Function IO ---------*/
+typedef struct
+{
+ vu32 CRL;
+ vu32 CRH;
+ vu32 IDR;
+ vu32 ODR;
+ vu32 BSRR;
+ vu32 BRR;
+ vu32 LCKR;
+} GPIO_TypeDef;
+
+typedef struct
+{
+ vu32 EVCR;
+ vu32 MAPR;
+ vu32 EXTICR[4];
+} AFIO_TypeDef;
+
+/*------------------------ Inter-integrated Circuit Interface ----------------*/
+typedef struct
+{
+ vu16 CR1;
+ u16 RESERVED0;
+ vu16 CR2;
+ u16 RESERVED1;
+ vu16 OAR1;
+ u16 RESERVED2;
+ vu16 OAR2;
+ u16 RESERVED3;
+ vu16 DR;
+ u16 RESERVED4;
+ vu16 SR1;
+ u16 RESERVED5;
+ vu16 SR2;
+ u16 RESERVED6;
+ vu16 CCR;
+ u16 RESERVED7;
+ vu16 TRISE;
+ u16 RESERVED8;
+} I2C_TypeDef;
+
+/*------------------------ Independent WATCHDOG ------------------------------*/
+typedef struct
+{
+ vu32 KR;
+ vu32 PR;
+ vu32 RLR;
+ vu32 SR;
+} IWDG_TypeDef;
+
+/*------------------------ Nested Vectored Interrupt Controller --------------*/
+typedef struct
+{
+ vu32 Enable[2];
+ u32 RESERVED0[30];
+ vu32 Disable[2];
+ u32 RSERVED1[30];
+ vu32 Set[2];
+ u32 RESERVED2[30];
+ vu32 Clear[2];
+ u32 RESERVED3[30];
+ vu32 Active[2];
+ u32 RESERVED4[62];
+ vu32 Priority[11];
+} NVIC_TypeDef;
+
+typedef struct
+{
+ vu32 CPUID;
+ vu32 IRQControlState;
+ vu32 ExceptionTableOffset;
+ vu32 AIRC;
+ vu32 SysCtrl;
+ vu32 ConfigCtrl;
+ vu32 SystemPriority[3];
+ vu32 SysHandlerCtrl;
+ vu32 ConfigFaultStatus;
+ vu32 HardFaultStatus;
+ vu32 DebugFaultStatus;
+ vu32 MemoryManageFaultAddr;
+ vu32 BusFaultAddr;
+} SCB_TypeDef;
+
+/*------------------------ Power Controller ----------------------------------*/
+typedef struct
+{
+ vu32 CR;
+ vu32 CSR;
+} PWR_TypeDef;
+
+/*------------------------ Reset and Clock Controller ------------------------*/
+typedef struct
+{
+ vu32 CR;
+ vu32 CFGR;
+ vu32 CIR;
+ vu32 APB2RSTR;
+ vu32 APB1RSTR;
+ vu32 AHBENR;
+ vu32 APB2ENR;
+ vu32 APB1ENR;
+ vu32 BDCR;
+ vu32 CSR;
+} RCC_TypeDef;
+
+/*------------------------ Real-Time Clock -----------------------------------*/
+typedef struct
+{
+ vu16 CRH;
+ u16 RESERVED0;
+ vu16 CRL;
+ u16 RESERVED1;
+ vu16 PRLH;
+ u16 RESERVED2;
+ vu16 PRLL;
+ u16 RESERVED3;
+ vu16 DIVH;
+ u16 RESERVED4;
+ vu16 DIVL;
+ u16 RESERVED5;
+ vu16 CNTH;
+ u16 RESERVED6;
+ vu16 CNTL;
+ u16 RESERVED7;
+ vu16 ALRH;
+ u16 RESERVED8;
+ vu16 ALRL;
+ u16 RESERVED9;
+} RTC_TypeDef;
+
+/*------------------------ Serial Peripheral Interface -----------------------*/
+typedef struct
+{
+ vu16 CR1;
+ u16 RESERVED0;
+ vu16 CR2;
+ u16 RESERVED1;
+ vu16 SR;
+ u16 RESERVED2;
+ vu16 DR;
+ u16 RESERVED3;
+ vu16 CRCPR;
+ u16 RESERVED4;
+ vu16 RXCRCR;
+ u16 RESERVED5;
+ vu16 TXCRCR;
+ u16 RESERVED6;
+} SPI_TypeDef;
+
+/*------------------------ SystemTick ----------------------------------------*/
+typedef struct
+{
+ vu32 CTRL;
+ vu32 LOAD;
+ vu32 VAL;
+ vuc32 CALIB;
+} SysTick_TypeDef;
+
+/*------------------------ Advanced Control Timer ----------------------------*/
+typedef struct
+{
+ vu16 CR1;
+ u16 RESERVED0;
+ vu16 CR2;
+ u16 RESERVED1;
+ vu16 SMCR;
+ u16 RESERVED2;
+ vu16 DIER;
+ u16 RESERVED3;
+ vu16 SR;
+ u16 RESERVED4;
+ vu16 EGR;
+ u16 RESERVED5;
+ vu16 CCMR1;
+ u16 RESERVED6;
+ vu16 CCMR2;
+ u16 RESERVED7;
+ vu16 CCER;
+ u16 RESERVED8;
+ vu16 CNT;
+ u16 RESERVED9;
+ vu16 PSC;
+ u16 RESERVED10;
+ vu16 ARR;
+ u16 RESERVED11;
+ vu16 RCR;
+ u16 RESERVED12;
+ vu16 CCR1;
+ u16 RESERVED13;
+ vu16 CCR2;
+ u16 RESERVED14;
+ vu16 CCR3;
+ u16 RESERVED15;
+ vu16 CCR4;
+ u16 RESERVED16;
+ vu16 BDTR;
+ u16 RESERVED17;
+ vu16 DCR;
+ u16 RESERVED18;
+ vu16 DMAR;
+ u16 RESERVED19;
+} TIM1_TypeDef;
+
+/*------------------------ General Purpose Timer -----------------------------*/
+typedef struct
+{
+ vu16 CR1;
+ u16 RESERVED0;
+ vu16 CR2;
+ u16 RESERVED1;
+ vu16 SMCR;
+ u16 RESERVED2;
+ vu16 DIER;
+ u16 RESERVED3;
+ vu16 SR;
+ u16 RESERVED4;
+ vu16 EGR;
+ u16 RESERVED5;
+ vu16 CCMR1;
+ u16 RESERVED6;
+ vu16 CCMR2;
+ u16 RESERVED7;
+ vu16 CCER;
+ u16 RESERVED8;
+ vu16 CNT;
+ u16 RESERVED9;
+ vu16 PSC;
+ u16 RESERVED10;
+ vu16 ARR;
+ u16 RESERVED11[3];
+ vu16 CCR1;
+ u16 RESERVED12;
+ vu16 CCR2;
+ u16 RESERVED13;
+ vu16 CCR3;
+ u16 RESERVED14;
+ vu16 CCR4;
+ u16 RESERVED15[3];
+ vu16 DCR;
+ u16 RESERVED16;
+ vu16 DMAR;
+ u16 RESERVED17;
+} TIM_TypeDef;
+
+/*----------------- Universal Synchronous Asynchronous Receiver Transmitter --*/
+typedef struct
+{
+ vu16 SR;
+ u16 RESERVED0;
+ vu16 DR;
+ u16 RESERVED1;
+ vu16 BRR;
+ u16 RESERVED2;
+ vu16 CR1;
+ u16 RESERVED3;
+ vu16 CR2;
+ u16 RESERVED4;
+ vu16 CR3;
+ u16 RESERVED5;
+ vu16 GTPR;
+ u16 RESERVED6;
+} USART_TypeDef;
+
+/*------------------------ Window WATCHDOG -----------------------------------*/
+typedef struct
+{
+ vu32 CR;
+ vu32 CFR;
+ vu32 SR;
+} WWDG_TypeDef;
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+/* Peripheral and SRAM base address in the alias region */
+#define PERIPH_BB_BASE ((u32)0x42000000)
+#define SRAM_BB_BASE ((u32)0x22000000)
+
+/* Peripheral and SRAM base address in the bit-band region */
+#define SRAM_BASE ((u32)0x20000000)
+#define PERIPH_BASE ((u32)0x40000000)
+
+/* Flash refisters base address */
+#define FLASH_BASE ((u32)0x40022000)
+/* Flash Option Bytes base address */
+#define OB_BASE ((u32)0x1FFFF800)
+
+/* Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
+
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define CAN_BASE (APB1PERIPH_BASE + 0x6400)
+#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+
+#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
+#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
+
+#define DMA_BASE (AHBPERIPH_BASE + 0x0000)
+#define DMA_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
+#define DMA_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
+#define DMA_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
+#define DMA_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
+#define DMA_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
+#define DMA_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
+#define DMA_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
+#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
+
+/* System Control Space memory map */
+#define SCS_BASE ((u32)0xE000E000)
+
+#define SysTick_BASE (SCS_BASE + 0x0010)
+#define NVIC_BASE (SCS_BASE + 0x0100)
+#define SCB_BASE (SCS_BASE + 0x0D00)
+
+
+/******************************************************************************/
+/* IPs' declaration */
+/******************************************************************************/
+
+/*------------------- Non Debug Mode -----------------------------------------*/
+#ifndef DEBUG
+#ifdef _TIM2
+ #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#endif /*_TIM2 */
+
+#ifdef _TIM3
+ #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#endif /*_TIM3 */
+
+#ifdef _TIM4
+ #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#endif /*_TIM4 */
+
+#ifdef _RTC
+ #define RTC ((RTC_TypeDef *) RTC_BASE)
+#endif /*_RTC */
+
+#ifdef _WWDG
+ #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#endif /*_WWDG */
+
+#ifdef _IWDG
+ #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#endif /*_IWDG */
+
+#ifdef _SPI2
+ #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#endif /*_SPI2 */
+
+#ifdef _USART2
+ #define USART2 ((USART_TypeDef *) USART2_BASE)
+#endif /*_USART2 */
+
+#ifdef _USART3
+ #define USART3 ((USART_TypeDef *) USART3_BASE)
+#endif /*_USART3 */
+
+#ifdef _I2C1
+ #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#endif /*_I2C1 */
+
+#ifdef _I2C2
+ #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#endif /*_I2C2 */
+
+#ifdef _CAN
+ #define CAN ((CAN_TypeDef *) CAN_BASE)
+#endif /*_CAN */
+
+#ifdef _BKP
+ #define BKP ((BKP_TypeDef *) BKP_BASE)
+#endif /*_BKP */
+
+#ifdef _PWR
+ #define PWR ((PWR_TypeDef *) PWR_BASE)
+#endif /*_PWR */
+
+#ifdef _AFIO
+ #define AFIO ((AFIO_TypeDef *) AFIO_BASE)
+#endif /*_AFIO */
+
+#ifdef _EXTI
+ #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#endif /*_EXTI */
+
+#ifdef _GPIOA
+ #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#endif /*_GPIOA */
+
+#ifdef _GPIOB
+ #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#endif /*_GPIOB */
+
+#ifdef _GPIOC
+ #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#endif /*_GPIOC */
+
+#ifdef _GPIOD
+ #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#endif /*_GPIOD */
+
+#ifdef _GPIOE
+ #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#endif /*_GPIOE */
+
+#ifdef _ADC1
+ #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#endif /*_ADC1 */
+
+#ifdef _ADC2
+ #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#endif /*_ADC2 */
+
+#ifdef _TIM1
+ #define TIM1 ((TIM1_TypeDef *) TIM1_BASE)
+#endif /*_TIM1 */
+
+#ifdef _SPI1
+ #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#endif /*_SPI1 */
+
+#ifdef _USART1
+ #define USART1 ((USART_TypeDef *) USART1_BASE)
+#endif /*_USART1 */
+
+#ifdef _DMA
+ #define DMA ((DMA_TypeDef *) DMA_BASE)
+#endif /*_DMA */
+
+#ifdef _DMA_Channel1
+ #define DMA_Channel1 ((DMA_Channel_TypeDef *) DMA_Channel1_BASE)
+#endif /*_DMA_Channel1 */
+
+#ifdef _DMA_Channel2
+ #define DMA_Channel2 ((DMA_Channel_TypeDef *) DMA_Channel2_BASE)
+#endif /*_DMA_Channel2 */
+
+#ifdef _DMA_Channel3
+ #define DMA_Channel3 ((DMA_Channel_TypeDef *) DMA_Channel3_BASE)
+#endif /*_DMA_Channel3 */
+
+#ifdef _DMA_Channel4
+ #define DMA_Channel4 ((DMA_Channel_TypeDef *) DMA_Channel4_BASE)
+#endif /*_DMA_Channel4 */
+
+#ifdef _DMA_Channel5
+ #define DMA_Channel5 ((DMA_Channel_TypeDef *) DMA_Channel5_BASE)
+#endif /*_DMA_Channel5 */
+
+#ifdef _DMA_Channel6
+ #define DMA_Channel6 ((DMA_Channel_TypeDef *) DMA_Channel6_BASE)
+#endif /*_DMA_Channel6 */
+
+#ifdef _DMA_Channel7
+ #define DMA_Channel7 ((DMA_Channel_TypeDef *) DMA_Channel7_BASE)
+#endif /*_DMA_Channel7 */
+
+#ifdef _FLASH
+ #define FLASH ((FLASH_TypeDef *) FLASH_BASE)
+ #define OB ((OB_TypeDef *) OB_BASE)
+#endif /*_FLASH */
+
+#ifdef _RCC
+ #define RCC ((RCC_TypeDef *) RCC_BASE)
+#endif /*_RCC */
+
+#ifdef _SysTick
+ #define SysTick ((SysTick_TypeDef *) SysTick_BASE)
+#endif /*_SysTick */
+
+#ifdef _NVIC
+ #define NVIC ((NVIC_TypeDef *) NVIC_BASE)
+#endif /*_NVIC */
+
+#ifdef _SCB
+ #define SCB ((SCB_TypeDef *) SCB_BASE)
+#endif /*_SCB */
+/*---------------------- Debug Mode -----------------------------------------*/
+#else /* DEBUG */
+#ifdef _TIM2
+ EXT TIM_TypeDef *TIM2;
+#endif /*_TIM2 */
+
+#ifdef _TIM3
+ EXT TIM_TypeDef *TIM3;
+#endif /*_TIM3 */
+
+#ifdef _TIM4
+ EXT TIM_TypeDef *TIM4;
+#endif /*_TIM4 */
+
+#ifdef _RTC
+ EXT RTC_TypeDef *RTC;
+#endif /*_RTC */
+
+#ifdef _WWDG
+ EXT WWDG_TypeDef *WWDG;
+#endif /*_WWDG */
+
+#ifdef _IWDG
+ EXT IWDG_TypeDef *IWDG;
+#endif /*_IWDG */
+
+#ifdef _SPI2
+ EXT SPI_TypeDef *SPI2;
+#endif /*_SPI2 */
+
+#ifdef _USART2
+ EXT USART_TypeDef *USART2;
+#endif /*_USART2 */
+
+#ifdef _USART3
+ EXT USART_TypeDef *USART3;
+#endif /*_USART3 */
+
+#ifdef _I2C1
+ EXT I2C_TypeDef *I2C1;
+#endif /*_I2C1 */
+
+#ifdef _I2C2
+ EXT I2C_TypeDef *I2C2;
+#endif /*_I2C2 */
+
+#ifdef _CAN
+ EXT CAN_TypeDef *CAN;
+#endif /*_CAN */
+
+#ifdef _BKP
+ EXT BKP_TypeDef *BKP;
+#endif /*_BKP */
+
+#ifdef _PWR
+ EXT PWR_TypeDef *PWR;
+#endif /*_PWR */
+
+#ifdef _AFIO
+ EXT AFIO_TypeDef *AFIO;
+#endif /*_AFIO */
+
+#ifdef _EXTI
+ EXT EXTI_TypeDef *EXTI;
+#endif /*_EXTI */
+
+#ifdef _GPIOA
+ EXT GPIO_TypeDef *GPIOA;
+#endif /*_GPIOA */
+
+#ifdef _GPIOB
+ EXT GPIO_TypeDef *GPIOB;
+#endif /*_GPIOB */
+
+#ifdef _GPIOC
+ EXT GPIO_TypeDef *GPIOC;
+#endif /*_GPIOC */
+
+#ifdef _GPIOD
+ EXT GPIO_TypeDef *GPIOD;
+#endif /*_GPIOD */
+
+#ifdef _GPIOE
+ EXT GPIO_TypeDef *GPIOE;
+#endif /*_GPIOE */
+
+#ifdef _ADC1
+ EXT ADC_TypeDef *ADC1;
+#endif /*_ADC1 */
+
+#ifdef _ADC2
+ EXT ADC_TypeDef *ADC2;
+#endif /*_ADC2 */
+
+#ifdef _TIM1
+ EXT TIM1_TypeDef *TIM1;
+#endif /*_TIM1 */
+
+#ifdef _SPI1
+ EXT SPI_TypeDef *SPI1;
+#endif /*_SPI1 */
+
+#ifdef _USART1
+ EXT USART_TypeDef *USART1;
+#endif /*_USART1 */
+
+#ifdef _DMA
+ EXT DMA_TypeDef *DMA;
+#endif /*_DMA */
+
+#ifdef _DMA_Channel1
+ EXT DMA_Channel_TypeDef *DMA_Channel1;
+#endif /*_DMA_Channel1 */
+
+#ifdef _DMA_Channel2
+ EXT DMA_Channel_TypeDef *DMA_Channel2;
+#endif /*_DMA_Channel2 */
+
+#ifdef _DMA_Channel3
+ EXT DMA_Channel_TypeDef *DMA_Channel3;
+#endif /*_DMA_Channel3 */
+
+#ifdef _DMA_Channel4
+ EXT DMA_Channel_TypeDef *DMA_Channel4;
+#endif /*_DMA_Channel4 */
+
+#ifdef _DMA_Channel5
+ EXT DMA_Channel_TypeDef *DMA_Channel5;
+#endif /*_DMA_Channel5 */
+
+#ifdef _DMA_Channel6
+ EXT DMA_Channel_TypeDef *DMA_Channel6;
+#endif /*_DMA_Channel6 */
+
+#ifdef _DMA_Channel7
+ EXT DMA_Channel_TypeDef *DMA_Channel7;
+#endif /*_DMA_Channel7 */
+
+#ifdef _FLASH
+ EXT FLASH_TypeDef *FLASH;
+ EXT OB_TypeDef *OB;
+#endif /*_FLASH */
+
+#ifdef _RCC
+ EXT RCC_TypeDef *RCC;
+#endif /*_RCC */
+
+#ifdef _SysTick
+ EXT SysTick_TypeDef *SysTick;
+#endif /*_SysTick */
+
+#ifdef _NVIC
+ EXT NVIC_TypeDef *NVIC;
+#endif /*_NVIC */
+
+#ifdef _SCB
+ EXT SCB_TypeDef *SCB;
+#endif /*_SCB */
+
+#endif /* DEBUG */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+#endif /* __STM32F10x_MAP_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_nvic.h b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_nvic.h
new file mode 100644
index 0000000..5cfacf8
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_nvic.h
@@ -0,0 +1,255 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_nvic.h
+* Author : MCD Application Team
+* Date First Issued : 09/29/2006
+* Description : This file contains all the functions prototypes for the
+* NVIC firmware library.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_NVIC_H
+#define __STM32F10x_NVIC_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* NVIC Init Structure definition */
+typedef struct
+{
+ u8 NVIC_IRQChannel;
+ u8 NVIC_IRQChannelPreemptionPriority;
+ u8 NVIC_IRQChannelSubPriority;
+ FunctionalState NVIC_IRQChannelCmd;
+} NVIC_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/* IRQ Channels --------------------------------------------------------------*/
+#define WWDG_IRQChannel ((u8)0x00) /* Window WatchDog Interrupt */
+#define PVD_IRQChannel ((u8)0x01) /* PVD through EXTI Line detection Interrupt */
+#define TAMPER_IRQChannel ((u8)0x02) /* Tamper Interrupt */
+#define RTC_IRQChannel ((u8)0x03) /* RTC global Interrupt */
+#define FLASH_IRQChannel ((u8)0x04) /* FLASH global Interrupt */
+#define RCC_IRQChannel ((u8)0x05) /* RCC global Interrupt */
+#define EXTI0_IRQChannel ((u8)0x06) /* EXTI Line0 Interrupt */
+#define EXTI1_IRQChannel ((u8)0x07) /* EXTI Line1 Interrupt */
+#define EXTI2_IRQChannel ((u8)0x08) /* EXTI Line2 Interrupt */
+#define EXTI3_IRQChannel ((u8)0x09) /* EXTI Line3 Interrupt */
+#define EXTI4_IRQChannel ((u8)0x0A) /* EXTI Line4 Interrupt */
+#define DMAChannel1_IRQChannel ((u8)0x0B) /* DMA Channel 1 global Interrupt */
+#define DMAChannel2_IRQChannel ((u8)0x0C) /* DMA Channel 2 global Interrupt */
+#define DMAChannel3_IRQChannel ((u8)0x0D) /* DMA Channel 3 global Interrupt */
+#define DMAChannel4_IRQChannel ((u8)0x0E) /* DMA Channel 4 global Interrupt */
+#define DMAChannel5_IRQChannel ((u8)0x0F) /* DMA Channel 5 global Interrupt */
+#define DMAChannel6_IRQChannel ((u8)0x10) /* DMA Channel 6 global Interrupt */
+#define DMAChannel7_IRQChannel ((u8)0x11) /* DMA Channel 7 global Interrupt */
+#define ADC_IRQChannel ((u8)0x12) /* ADC global Interrupt */
+#define USB_HP_CAN_TX_IRQChannel ((u8)0x13) /* USB High Priority or CAN TX Interrupts */
+#define USB_LP_CAN_RX0_IRQChannel ((u8)0x14) /* USB Low Priority or CAN RX0 Interrupts */
+#define CAN_RX1_IRQChannel ((u8)0x15) /* CAN RX1 Interrupt */
+#define CAN_SCE_IRQChannel ((u8)0x16) /* CAN SCE Interrupt */
+#define EXTI9_5_IRQChannel ((u8)0x17) /* External Line[9:5] Interrupts */
+#define TIM1_BRK_IRQChannel ((u8)0x18) /* TIM1 Break Interrupt */
+#define TIM1_UP_IRQChannel ((u8)0x19) /* TIM1 Update Interrupt */
+#define TIM1_TRG_COM_IRQChannel ((u8)0x1A) /* TIM1 Trigger and Commutation Interrupt */
+#define TIM1_CC_IRQChannel ((u8)0x1B) /* TIM1 Capture Compare Interrupt */
+#define TIM2_IRQChannel ((u8)0x1C) /* TIM2 global Interrupt */
+#define TIM3_IRQChannel ((u8)0x1D) /* TIM3 global Interrupt */
+#define TIM4_IRQChannel ((u8)0x1E) /* TIM4 global Interrupt */
+#define I2C1_EV_IRQChannel ((u8)0x1F) /* I2C1 Event Interrupt */
+#define I2C1_ER_IRQChannel ((u8)0x20) /* I2C1 Error Interrupt */
+#define I2C2_EV_IRQChannel ((u8)0x21) /* I2C2 Event Interrupt */
+#define I2C2_ER_IRQChannel ((u8)0x22) /* I2C2 Error Interrupt */
+#define SPI1_IRQChannel ((u8)0x23) /* SPI1 global Interrupt */
+#define SPI2_IRQChannel ((u8)0x24) /* SPI2 global Interrupt */
+#define USART1_IRQChannel ((u8)0x25) /* USART1 global Interrupt */
+#define USART2_IRQChannel ((u8)0x26) /* USART2 global Interrupt */
+#define USART3_IRQChannel ((u8)0x27) /* USART3 global Interrupt */
+#define EXTI15_10_IRQChannel ((u8)0x28) /* External Line[15:10] Interrupts */
+#define RTCAlarm_IRQChannel ((u8)0x29) /* RTC Alarm through EXTI Line Interrupt */
+#define USBWakeUp_IRQChannel ((u8)0x2A) /* USB WakeUp from suspend through EXTI Line Interrupt */
+
+#define IS_NVIC_IRQ_CHANNEL(CHANNEL) ((CHANNEL == WWDG_IRQChannel) || \
+ (CHANNEL == PVD_IRQChannel) || \
+ (CHANNEL == TAMPER_IRQChannel) || \
+ (CHANNEL == RTC_IRQChannel) || \
+ (CHANNEL == FLASH_IRQChannel) || \
+ (CHANNEL == RCC_IRQChannel) || \
+ (CHANNEL == EXTI0_IRQChannel) || \
+ (CHANNEL == EXTI1_IRQChannel) || \
+ (CHANNEL == EXTI2_IRQChannel) || \
+ (CHANNEL == EXTI3_IRQChannel) || \
+ (CHANNEL == EXTI4_IRQChannel) || \
+ (CHANNEL == DMAChannel1_IRQChannel) || \
+ (CHANNEL == DMAChannel2_IRQChannel) || \
+ (CHANNEL == DMAChannel3_IRQChannel) || \
+ (CHANNEL == DMAChannel4_IRQChannel) || \
+ (CHANNEL == DMAChannel5_IRQChannel) || \
+ (CHANNEL == DMAChannel6_IRQChannel) || \
+ (CHANNEL == DMAChannel7_IRQChannel) || \
+ (CHANNEL == ADC_IRQChannel) || \
+ (CHANNEL == USB_HP_CAN_TX_IRQChannel) || \
+ (CHANNEL == USB_LP_CAN_RX0_IRQChannel) || \
+ (CHANNEL == CAN_RX1_IRQChannel) || \
+ (CHANNEL == CAN_SCE_IRQChannel) || \
+ (CHANNEL == EXTI9_5_IRQChannel) || \
+ (CHANNEL == TIM1_BRK_IRQChannel) || \
+ (CHANNEL == TIM1_UP_IRQChannel) || \
+ (CHANNEL == TIM1_TRG_COM_IRQChannel) || \
+ (CHANNEL == TIM1_CC_IRQChannel) || \
+ (CHANNEL == TIM2_IRQChannel) || \
+ (CHANNEL == TIM3_IRQChannel) || \
+ (CHANNEL == TIM4_IRQChannel) || \
+ (CHANNEL == I2C1_EV_IRQChannel) || \
+ (CHANNEL == I2C1_ER_IRQChannel) || \
+ (CHANNEL == I2C2_EV_IRQChannel) || \
+ (CHANNEL == I2C2_ER_IRQChannel) || \
+ (CHANNEL == SPI1_IRQChannel) || \
+ (CHANNEL == SPI2_IRQChannel) || \
+ (CHANNEL == USART1_IRQChannel) || \
+ (CHANNEL == USART2_IRQChannel) || \
+ (CHANNEL == USART3_IRQChannel) || \
+ (CHANNEL == EXTI15_10_IRQChannel) || \
+ (CHANNEL == RTCAlarm_IRQChannel) || \
+ (CHANNEL == USBWakeUp_IRQChannel))
+
+/* System Handlers -----------------------------------------------------------*/
+#define SystemHandler_NMI ((u32)0x00001F) /* NMI Handler */
+#define SystemHandler_HardFault ((u32)0x000000) /* Hard Fault Handler */
+#define SystemHandler_MemoryManage ((u32)0x043430) /* Memory Manage Handler */
+#define SystemHandler_BusFault ((u32)0x547931) /* Bus Fault Handler */
+#define SystemHandler_UsageFault ((u32)0x24C232) /* Usage Fault Handler */
+#define SystemHandler_SVCall ((u32)0x01FF40) /* SVCall Handler */
+#define SystemHandler_DebugMonitor ((u32)0x0A0080) /* Debug Monitor Handler */
+#define SystemHandler_PSV ((u32)0x02829C) /* PSV Handler */
+#define SystemHandler_SysTick ((u32)0x02C39A) /* SysTick Handler */
+
+#define IS_CONFIG_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \
+ (HANDLER == SystemHandler_BusFault) || \
+ (HANDLER == SystemHandler_UsageFault))
+
+#define IS_PRIORITY_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \
+ (HANDLER == SystemHandler_BusFault) || \
+ (HANDLER == SystemHandler_UsageFault) || \
+ (HANDLER == SystemHandler_SVCall) || \
+ (HANDLER == SystemHandler_DebugMonitor) || \
+ (HANDLER == SystemHandler_PSV) || \
+ (HANDLER == SystemHandler_SysTick))
+
+#define IS_GET_PENDING_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \
+ (HANDLER == SystemHandler_BusFault) || \
+ (HANDLER == SystemHandler_SVCall))
+
+#define IS_SET_PENDING_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_NMI) || \
+ (HANDLER == SystemHandler_PSV) || \
+ (HANDLER == SystemHandler_SysTick))
+
+#define IS_CLEAR_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_PSV) || \
+ (HANDLER == SystemHandler_SysTick))
+
+#define IS_GET_ACTIVE_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \
+ (HANDLER == SystemHandler_BusFault) || \
+ (HANDLER == SystemHandler_UsageFault) || \
+ (HANDLER == SystemHandler_SVCall) || \
+ (HANDLER == SystemHandler_DebugMonitor) || \
+ (HANDLER == SystemHandler_PSV) || \
+ (HANDLER == SystemHandler_SysTick))
+
+#define IS_FAULT_SOURCE_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_HardFault) || \
+ (HANDLER == SystemHandler_MemoryManage) || \
+ (HANDLER == SystemHandler_BusFault) || \
+ (HANDLER == SystemHandler_UsageFault) || \
+ (HANDLER == SystemHandler_DebugMonitor))
+
+#define IS_FAULT_ADDRESS_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \
+ (HANDLER == SystemHandler_BusFault))
+
+
+/* Vector Table Base ---------------------------------------------------------*/
+#define NVIC_VectTab_RAM ((u32)0x20000000)
+#define NVIC_VectTab_FLASH ((u32)0x00000000)
+
+#define IS_NVIC_VECTTAB(VECTTAB) ((VECTTAB == NVIC_VectTab_RAM) || \
+ (VECTTAB == NVIC_VectTab_FLASH))
+
+/* System Low Power ----------------------------------------------------------*/
+#define NVIC_LP_SEVONPEND ((u8)0x10)
+#define NVIC_LP_SLEEPDEEP ((u8)0x04)
+#define NVIC_LP_SLEEPONEXIT ((u8)0x02)
+
+#define IS_NVIC_LP(LP) ((LP == NVIC_LP_SEVONPEND) || \
+ (LP == NVIC_LP_SLEEPDEEP) || \
+ (LP == NVIC_LP_SLEEPONEXIT))
+
+/* Preemption Priority Group -------------------------------------------------*/
+#define NVIC_PriorityGroup_0 ((u32)0x700) /* 0 bits for pre-emption priority
+ 4 bits for subpriority */
+#define NVIC_PriorityGroup_1 ((u32)0x600) /* 1 bits for pre-emption priority
+ 3 bits for subpriority */
+#define NVIC_PriorityGroup_2 ((u32)0x500) /* 2 bits for pre-emption priority
+ 2 bits for subpriority */
+#define NVIC_PriorityGroup_3 ((u32)0x400) /* 3 bits for pre-emption priority
+ 1 bits for subpriority */
+#define NVIC_PriorityGroup_4 ((u32)0x300) /* 4 bits for pre-emption priority
+ 0 bits for subpriority */
+
+#define IS_NVIC_PRIORITY_GROUP(GROUP) ((GROUP == NVIC_PriorityGroup_0) || \
+ (GROUP == NVIC_PriorityGroup_1) || \
+ (GROUP == NVIC_PriorityGroup_2) || \
+ (GROUP == NVIC_PriorityGroup_3) || \
+ (GROUP == NVIC_PriorityGroup_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) (PRIORITY < 0x10)
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) (PRIORITY < 0x10)
+#define IS_NVIC_OFFSET(OFFSET) (OFFSET < 0x3FFFFF)
+#define IS_NVIC_BASE_PRI(PRI) ((PRI > 0x00) && (PRI < 0x10))
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void NVIC_DeInit(void);
+void NVIC_SCBDeInit(void);
+void NVIC_PriorityGroupConfig(u32 NVIC_PriorityGroup);
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
+void NVIC_StructInit(NVIC_InitTypeDef* NVIC_InitStruct);
+void NVIC_SETPRIMASK(void);
+void NVIC_RESETPRIMASK(void);
+void NVIC_SETFAULTMASK(void);
+void NVIC_RESETFAULTMASK(void);
+void NVIC_BASEPRICONFIG(u32 NewPriority);
+u32 NVIC_GetBASEPRI(void);
+u16 NVIC_GetCurrentPendingIRQChannel(void);
+ITStatus NVIC_GetIRQChannelPendingBitStatus(u8 NVIC_IRQChannel);
+void NVIC_SetIRQChannelPendingBit(u8 NVIC_IRQChannel);
+void NVIC_ClearIRQChannelPendingBit(u8 NVIC_IRQChannel);
+u16 NVIC_GetCurrentActiveHandler(void);
+ITStatus NVIC_GetIRQChannelActiveBitStatus(u8 NVIC_IRQChannel);
+u32 NVIC_GetCPUID(void);
+void NVIC_SetVectorTable(u32 NVIC_VectTab, u32 Offset);
+void NVIC_GenerateSystemReset(void);
+void NVIC_GenerateCoreReset(void);
+void NVIC_SystemLPConfig(u8 LowPowerMode, FunctionalState NewState);
+void NVIC_SystemHandlerConfig(u32 SystemHandler, FunctionalState NewState);
+void NVIC_SystemHandlerPriorityConfig(u32 SystemHandler, u8 SystemHandlerPreemptionPriority,
+ u8 SystemHandlerSubPriority);
+ITStatus NVIC_GetSystemHandlerPendingBitStatus(u32 SystemHandler);
+void NVIC_SetSystemHandlerPendingBit(u32 SystemHandler);
+void NVIC_ClearSystemHandlerPendingBit(u32 SystemHandler);
+ITStatus NVIC_GetSystemHandlerActiveBitStatus(u32 SystemHandler);
+u32 NVIC_GetFaultHandlerSources(u32 SystemHandler);
+u32 NVIC_GetFaultAddress(u32 SystemHandler);
+
+#endif /* __STM32F10x_NVIC_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_pwr.h b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_pwr.h
new file mode 100644
index 0000000..4bbc291
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_pwr.h
@@ -0,0 +1,81 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_pwr.h
+* Author : MCD Application Team
+* Date First Issued : 09/29/2006
+* Description : This file contains all the functions prototypes for the
+* PWR firmware library.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_PWR_H
+#define __STM32F10x_PWR_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* PVD detection level */
+#define PWR_PVDLevel_2V2 ((u32)0x00000000)
+#define PWR_PVDLevel_2V3 ((u32)0x00000020)
+#define PWR_PVDLevel_2V4 ((u32)0x00000040)
+#define PWR_PVDLevel_2V5 ((u32)0x00000060)
+#define PWR_PVDLevel_2V6 ((u32)0x00000080)
+#define PWR_PVDLevel_2V7 ((u32)0x000000A0)
+#define PWR_PVDLevel_2V8 ((u32)0x000000C0)
+#define PWR_PVDLevel_2V9 ((u32)0x000000E0)
+
+#define IS_PWR_PVD_LEVEL(LEVEL) ((LEVEL == PWR_PVDLevel_2V2) || (LEVEL == PWR_PVDLevel_2V3)|| \
+ (LEVEL == PWR_PVDLevel_2V4) || (LEVEL == PWR_PVDLevel_2V5)|| \
+ (LEVEL == PWR_PVDLevel_2V6) || (LEVEL == PWR_PVDLevel_2V7)|| \
+ (LEVEL == PWR_PVDLevel_2V8) || (LEVEL == PWR_PVDLevel_2V9))
+
+/* Regulator state is STOP mode */
+#define PWR_Regulator_ON ((u32)0x00000000)
+#define PWR_Regulator_LowPower ((u32)0x00000001)
+
+#define IS_PWR_REGULATOR(REGULATOR) ((REGULATOR == PWR_Regulator_ON) || \
+ (REGULATOR == PWR_Regulator_LowPower))
+
+/* STOP mode entry */
+#define PWR_STOPEntry_WFI ((u8)0x01)
+#define PWR_STOPEntry_WFE ((u8)0x02)
+
+#define IS_PWR_STOP_ENTRY(ENTRY) ((ENTRY == PWR_STOPEntry_WFI) || (ENTRY == PWR_STOPEntry_WFE))
+
+/* PWR Flag */
+#define PWR_FLAG_WU ((u32)0x00000001)
+#define PWR_FLAG_SB ((u32)0x00000002)
+#define PWR_FLAG_PVDO ((u32)0x00000004)
+
+#define IS_PWR_GET_FLAG(FLAG) ((FLAG == PWR_FLAG_WU) || (FLAG == PWR_FLAG_SB) || \
+ (FLAG == PWR_FLAG_PVDO))
+#define IS_PWR_CLEAR_FLAG(FLAG) ((FLAG == PWR_FLAG_WU) || (FLAG == PWR_FLAG_SB))
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void PWR_DeInit(void);
+void PWR_BackupAccessCmd(FunctionalState NewState);
+void PWR_PVDCmd(FunctionalState NewState);
+void PWR_PVDLevelConfig(u32 PWR_PVDLevel);
+void PWR_WakeUpPinCmd(FunctionalState NewState);
+void PWR_EnterSTOPMode(u32 PWR_Regulator, u8 PWR_STOPEntry);
+void PWR_EnterSTANDBYMode(void);
+FlagStatus PWR_GetFlagStatus(u32 PWR_FLAG);
+void PWR_ClearFlag(u32 PWR_FLAG);
+
+#endif /* __STM32F10x_PWR_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_rcc.h b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_rcc.h
new file mode 100644
index 0000000..b7d0aa3
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_rcc.h
@@ -0,0 +1,276 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_rcc.h
+* Author : MCD Application Team
+* Date First Issued : 09/29/2006
+* Description : This file contains all the functions prototypes for the
+* RCC firmware library.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_RCC_H
+#define __STM32F10x_RCC_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+typedef struct
+{
+ u32 SYSCLK_Frequency;
+ u32 HCLK_Frequency;
+ u32 PCLK1_Frequency;
+ u32 PCLK2_Frequency;
+ u32 ADCCLK_Frequency;
+}RCC_ClocksTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/* HSE configuration */
+#define RCC_HSE_OFF ((u32)0x00000000)
+#define RCC_HSE_ON ((u32)0x00010000)
+#define RCC_HSE_Bypass ((u32)0x00040000)
+
+#define IS_RCC_HSE(HSE) ((HSE == RCC_HSE_OFF) || (HSE == RCC_HSE_ON) || \
+ (HSE == RCC_HSE_Bypass))
+
+/* PLL entry clock source */
+#define RCC_PLLSource_HSI_Div2 ((u32)0x00000000)
+#define RCC_PLLSource_HSE_Div1 ((u32)0x00010000)
+#define RCC_PLLSource_HSE_Div2 ((u32)0x00030000)
+
+#define IS_RCC_PLL_SOURCE(SOURCE) ((SOURCE == RCC_PLLSource_HSI_Div2) || \
+ (SOURCE == RCC_PLLSource_HSE_Div1) || \
+ (SOURCE == RCC_PLLSource_HSE_Div2))
+
+/* PLL multiplication factor */
+#define RCC_PLLMul_2 ((u32)0x00000000)
+#define RCC_PLLMul_3 ((u32)0x00040000)
+#define RCC_PLLMul_4 ((u32)0x00080000)
+#define RCC_PLLMul_5 ((u32)0x000C0000)
+#define RCC_PLLMul_6 ((u32)0x00100000)
+#define RCC_PLLMul_7 ((u32)0x00140000)
+#define RCC_PLLMul_8 ((u32)0x00180000)
+#define RCC_PLLMul_9 ((u32)0x001C0000)
+#define RCC_PLLMul_10 ((u32)0x00200000)
+#define RCC_PLLMul_11 ((u32)0x00240000)
+#define RCC_PLLMul_12 ((u32)0x00280000)
+#define RCC_PLLMul_13 ((u32)0x002C0000)
+#define RCC_PLLMul_14 ((u32)0x00300000)
+#define RCC_PLLMul_15 ((u32)0x00340000)
+#define RCC_PLLMul_16 ((u32)0x00380000)
+
+#define IS_RCC_PLL_MUL(MUL) ((MUL == RCC_PLLMul_2) || (MUL == RCC_PLLMul_3) ||\
+ (MUL == RCC_PLLMul_4) || (MUL == RCC_PLLMul_5) ||\
+ (MUL == RCC_PLLMul_6) || (MUL == RCC_PLLMul_7) ||\
+ (MUL == RCC_PLLMul_8) || (MUL == RCC_PLLMul_9) ||\
+ (MUL == RCC_PLLMul_10) || (MUL == RCC_PLLMul_11) ||\
+ (MUL == RCC_PLLMul_12) || (MUL == RCC_PLLMul_13) ||\
+ (MUL == RCC_PLLMul_14) || (MUL == RCC_PLLMul_15) ||\
+ (MUL == RCC_PLLMul_16))
+
+/* System clock source */
+#define RCC_SYSCLKSource_HSI ((u32)0x00000000)
+#define RCC_SYSCLKSource_HSE ((u32)0x00000001)
+#define RCC_SYSCLKSource_PLLCLK ((u32)0x00000002)
+
+#define IS_RCC_SYSCLK_SOURCE(SOURCE) ((SOURCE == RCC_SYSCLKSource_HSI) || \
+ (SOURCE == RCC_SYSCLKSource_HSE) || \
+ (SOURCE == RCC_SYSCLKSource_PLLCLK))
+
+/* AHB clock source */
+#define RCC_SYSCLK_Div1 ((u32)0x00000000)
+#define RCC_SYSCLK_Div2 ((u32)0x00000080)
+#define RCC_SYSCLK_Div4 ((u32)0x00000090)
+#define RCC_SYSCLK_Div8 ((u32)0x000000A0)
+#define RCC_SYSCLK_Div16 ((u32)0x000000B0)
+#define RCC_SYSCLK_Div64 ((u32)0x000000C0)
+#define RCC_SYSCLK_Div128 ((u32)0x000000D0)
+#define RCC_SYSCLK_Div256 ((u32)0x000000E0)
+#define RCC_SYSCLK_Div512 ((u32)0x000000F0)
+
+#define IS_RCC_HCLK(HCLK) ((HCLK == RCC_SYSCLK_Div1) || (HCLK == RCC_SYSCLK_Div2) || \
+ (HCLK == RCC_SYSCLK_Div4) || (HCLK == RCC_SYSCLK_Div8) || \
+ (HCLK == RCC_SYSCLK_Div16) || (HCLK == RCC_SYSCLK_Div64) || \
+ (HCLK == RCC_SYSCLK_Div128) || (HCLK == RCC_SYSCLK_Div256) || \
+ (HCLK == RCC_SYSCLK_Div512))
+
+/* APB1/APB2 clock source */
+#define RCC_HCLK_Div1 ((u32)0x00000000)
+#define RCC_HCLK_Div2 ((u32)0x00000400)
+#define RCC_HCLK_Div4 ((u32)0x00000500)
+#define RCC_HCLK_Div8 ((u32)0x00000600)
+#define RCC_HCLK_Div16 ((u32)0x00000700)
+
+#define IS_RCC_PCLK(PCLK) ((PCLK == RCC_HCLK_Div1) || (PCLK == RCC_HCLK_Div2) || \
+ (PCLK == RCC_HCLK_Div4) || (PCLK == RCC_HCLK_Div8) || \
+ (PCLK == RCC_HCLK_Div16))
+
+/* RCC Interrupt source */
+#define RCC_IT_LSIRDY ((u8)0x01)
+#define RCC_IT_LSERDY ((u8)0x02)
+#define RCC_IT_HSIRDY ((u8)0x04)
+#define RCC_IT_HSERDY ((u8)0x08)
+#define RCC_IT_PLLRDY ((u8)0x10)
+#define RCC_IT_CSS ((u8)0x80)
+
+#define IS_RCC_IT(IT) (((IT & (u8)0xE0) == 0x00) && (IT != 0x00))
+#define IS_RCC_GET_IT(IT) ((IT == RCC_IT_LSIRDY) || (IT == RCC_IT_LSERDY) || \
+ (IT == RCC_IT_HSIRDY) || (IT == RCC_IT_HSERDY) || \
+ (IT == RCC_IT_PLLRDY) || (IT == RCC_IT_CSS))
+#define IS_RCC_CLEAR_IT(IT) (((IT & (u8)0x60) == 0x00) && (IT != 0x00))
+
+/* USB clock source */
+#define RCC_USBCLKSource_PLLCLK_1Div5 ((u8)0x00)
+#define RCC_USBCLKSource_PLLCLK_Div1 ((u8)0x01)
+
+#define IS_RCC_USBCLK_SOURCE(SOURCE) ((SOURCE == RCC_USBCLKSource_PLLCLK_1Div5) || \
+ (SOURCE == RCC_USBCLKSource_PLLCLK_Div1))
+
+/* ADC clock source */
+#define RCC_PCLK2_Div2 ((u32)0x00000000)
+#define RCC_PCLK2_Div4 ((u32)0x00004000)
+#define RCC_PCLK2_Div6 ((u32)0x00008000)
+#define RCC_PCLK2_Div8 ((u32)0x0000C000)
+
+#define IS_RCC_ADCCLK(ADCCLK) ((ADCCLK == RCC_PCLK2_Div2) || (ADCCLK == RCC_PCLK2_Div4) || \
+ (ADCCLK == RCC_PCLK2_Div6) || (ADCCLK == RCC_PCLK2_Div8))
+
+/* LSE configuration */
+#define RCC_LSE_OFF ((u8)0x00)
+#define RCC_LSE_ON ((u8)0x01)
+#define RCC_LSE_Bypass ((u8)0x04)
+
+#define IS_RCC_LSE(LSE) ((LSE == RCC_LSE_OFF) || (LSE == RCC_LSE_ON) || \
+ (LSE == RCC_LSE_Bypass))
+
+/* RTC clock source */
+#define RCC_RTCCLKSource_LSE ((u32)0x00000100)
+#define RCC_RTCCLKSource_LSI ((u32)0x00000200)
+#define RCC_RTCCLKSource_HSE_Div128 ((u32)0x00000300)
+
+#define IS_RCC_RTCCLK_SOURCE(SOURCE) ((SOURCE == RCC_RTCCLKSource_LSE) || \
+ (SOURCE == RCC_RTCCLKSource_LSI) || \
+ (SOURCE == RCC_RTCCLKSource_HSE_Div128))
+
+/* AHB peripheral */
+#define RCC_AHBPeriph_DMA ((u32)0x00000001)
+#define RCC_AHBPeriph_SRAM ((u32)0x00000004)
+#define RCC_AHBPeriph_FLITF ((u32)0x00000010)
+
+#define IS_RCC_AHB_PERIPH(PERIPH) (((PERIPH & 0xFFFFFFEA) == 0x00) && (PERIPH != 0x00))
+
+/* APB2 peripheral */
+#define RCC_APB2Periph_AFIO ((u32)0x00000001)
+#define RCC_APB2Periph_GPIOA ((u32)0x00000004)
+#define RCC_APB2Periph_GPIOB ((u32)0x00000008)
+#define RCC_APB2Periph_GPIOC ((u32)0x00000010)
+#define RCC_APB2Periph_GPIOD ((u32)0x00000020)
+#define RCC_APB2Periph_GPIOE ((u32)0x00000040)
+#define RCC_APB2Periph_ADC1 ((u32)0x00000200)
+#define RCC_APB2Periph_ADC2 ((u32)0x00000400)
+#define RCC_APB2Periph_TIM1 ((u32)0x00000800)
+#define RCC_APB2Periph_SPI1 ((u32)0x00001000)
+#define RCC_APB2Periph_USART1 ((u32)0x00004000)
+#define RCC_APB2Periph_ALL ((u32)0x00005E7D)
+
+#define IS_RCC_APB2_PERIPH(PERIPH) (((PERIPH & 0xFFFFA182) == 0x00) && (PERIPH != 0x00))
+
+/* APB1 peripheral */
+#define RCC_APB1Periph_TIM2 ((u32)0x00000001)
+#define RCC_APB1Periph_TIM3 ((u32)0x00000002)
+#define RCC_APB1Periph_TIM4 ((u32)0x00000004)
+#define RCC_APB1Periph_WWDG ((u32)0x00000800)
+#define RCC_APB1Periph_SPI2 ((u32)0x00004000)
+#define RCC_APB1Periph_USART2 ((u32)0x00020000)
+#define RCC_APB1Periph_USART3 ((u32)0x00040000)
+#define RCC_APB1Periph_I2C1 ((u32)0x00200000)
+#define RCC_APB1Periph_I2C2 ((u32)0x00400000)
+#define RCC_APB1Periph_USB ((u32)0x00800000)
+#define RCC_APB1Periph_CAN ((u32)0x02000000)
+#define RCC_APB1Periph_BKP ((u32)0x08000000)
+#define RCC_APB1Periph_PWR ((u32)0x10000000)
+#define RCC_APB1Periph_ALL ((u32)0x1AE64807)
+
+#define IS_RCC_APB1_PERIPH(PERIPH) (((PERIPH & 0xE519B7F8) == 0x00) && (PERIPH != 0x00))
+
+/* Clock source to output on MCO pin */
+#define RCC_MCO_NoClock ((u8)0x00)
+#define RCC_MCO_SYSCLK ((u8)0x04)
+#define RCC_MCO_HSI ((u8)0x05)
+#define RCC_MCO_HSE ((u8)0x06)
+#define RCC_MCO_PLLCLK_Div2 ((u8)0x07)
+
+#define IS_RCC_MCO(MCO) ((MCO == RCC_MCO_NoClock) || (MCO == RCC_MCO_HSI) || \
+ (MCO == RCC_MCO_SYSCLK) || (MCO == RCC_MCO_HSE) || \
+ (MCO == RCC_MCO_PLLCLK_Div2))
+
+/* RCC Flag */
+#define RCC_FLAG_HSIRDY ((u8)0x20)
+#define RCC_FLAG_HSERDY ((u8)0x31)
+#define RCC_FLAG_PLLRDY ((u8)0x39)
+#define RCC_FLAG_LSERDY ((u8)0x41)
+#define RCC_FLAG_LSIRDY ((u8)0x61)
+#define RCC_FLAG_PINRST ((u8)0x7A)
+#define RCC_FLAG_PORRST ((u8)0x7B)
+#define RCC_FLAG_SFTRST ((u8)0x7C)
+#define RCC_FLAG_IWDGRST ((u8)0x7D)
+#define RCC_FLAG_WWDGRST ((u8)0x7E)
+#define RCC_FLAG_LPWRRST ((u8)0x7F)
+
+#define IS_RCC_FLAG(FLAG) ((FLAG == RCC_FLAG_HSIRDY) || (FLAG == RCC_FLAG_HSERDY) || \
+ (FLAG == RCC_FLAG_PLLRDY) || (FLAG == RCC_FLAG_LSERDY) || \
+ (FLAG == RCC_FLAG_LSIRDY) || (FLAG == RCC_FLAG_PINRST) || \
+ (FLAG == RCC_FLAG_PORRST) || (FLAG == RCC_FLAG_SFTRST) || \
+ (FLAG == RCC_FLAG_IWDGRST)|| (FLAG == RCC_FLAG_WWDGRST)|| \
+ (FLAG == RCC_FLAG_LPWRRST))
+
+#define IS_RCC_CALIBRATION_VALUE(VALUE) (VALUE <= 0x1F)
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void RCC_DeInit(void);
+void RCC_HSEConfig(u32 RCC_HSE);
+void RCC_AdjustHSICalibrationValue(u8 HSICalibrationValue);
+void RCC_HSICmd(FunctionalState NewState);
+void RCC_PLLConfig(u32 RCC_PLLSource, u32 RCC_PLLMul);
+void RCC_PLLCmd(FunctionalState NewState);
+void RCC_SYSCLKConfig(u32 RCC_SYSCLKSource);
+u8 RCC_GetSYSCLKSource(void);
+void RCC_HCLKConfig(u32 RCC_HCLK);
+void RCC_PCLK1Config(u32 RCC_PCLK1);
+void RCC_PCLK2Config(u32 RCC_PCLK2);
+void RCC_ITConfig(u8 RCC_IT, FunctionalState NewState);
+void RCC_USBCLKConfig(u32 RCC_USBCLKSource);
+void RCC_ADCCLKConfig(u32 RCC_ADCCLK);
+void RCC_LSEConfig(u32 RCC_LSE);
+void RCC_LSICmd(FunctionalState NewState);
+void RCC_RTCCLKConfig(u32 RCC_RTCCLKSource);
+void RCC_RTCCLKCmd(FunctionalState NewState);
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
+void RCC_AHBPeriphClockCmd(u32 RCC_AHBPeriph, FunctionalState NewState);
+void RCC_APB2PeriphClockCmd(u32 RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphClockCmd(u32 RCC_APB1Periph, FunctionalState NewState);
+void RCC_APB2PeriphResetCmd(u32 RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphResetCmd(u32 RCC_APB1Periph, FunctionalState NewState);
+void RCC_BackupResetCmd(FunctionalState NewState);
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
+void RCC_MCOConfig(u8 RCC_MCO);
+FlagStatus RCC_GetFlagStatus(u8 RCC_FLAG);
+void RCC_ClearFlag(void);
+ITStatus RCC_GetITStatus(u8 RCC_IT);
+void RCC_ClearITPendingBit(u8 RCC_IT);
+
+#endif /* __STM32F10x_RCC_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_rtc.h b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_rtc.h
new file mode 100644
index 0000000..6f8c4e0
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_rtc.h
@@ -0,0 +1,75 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_rtc.h
+* Author : MCD Application Team
+* Date First Issued : 09/29/2006
+* Description : This file contains all the functions prototypes for the
+* RTC firmware library.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_RTC_H
+#define __STM32F10x_RTC_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* RTC interrupts define -----------------------------------------------------*/
+#define RTC_IT_OW ((u16)0x0004) /* Overflow interrupt */
+#define RTC_IT_ALR ((u16)0x0002) /* Alarm interrupt */
+#define RTC_IT_SEC ((u16)0x0001) /* Second interrupt */
+
+#define IS_RTC_IT(IT) (((IT & (u16)0xFFF8) == 0x00) && (IT != 0x00))
+
+#define IS_RTC_GET_IT(IT) ((IT == RTC_IT_OW) || (IT == RTC_IT_ALR) || \
+ (IT == RTC_IT_SEC))
+
+/* RTC interrupts flags ------------------------------------------------------*/
+#define RTC_FLAG_RTOFF ((u16)0x0020) /* RTC Operation OFF flag */
+#define RTC_FLAG_RSF ((u16)0x0008) /* Registers Synchronized flag */
+#define RTC_FLAG_OW ((u16)0x0004) /* Overflow flag */
+#define RTC_FLAG_ALR ((u16)0x0002) /* Alarm flag */
+#define RTC_FLAG_SEC ((u16)0x0001) /* Second flag */
+
+#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG & (u16)0xFFF0) == 0x00) && (FLAG != 0x00))
+
+#define IS_RTC_GET_FLAG(FLAG) ((FLAG == RTC_FLAG_RTOFF) || (FLAG == RTC_FLAG_RSF) || \
+ (FLAG == RTC_FLAG_OW) || (FLAG == RTC_FLAG_ALR) || \
+ (FLAG == RTC_FLAG_SEC))
+
+#define IS_RTC_PRESCALER(PRESCALER) (PRESCALER <= 0xFFFFF)
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void RTC_ITConfig(u16 RTC_IT, FunctionalState NewState);
+void RTC_EnterConfigMode(void);
+void RTC_ExitConfigMode(void);
+u32 RTC_GetCounter(void);
+void RTC_SetCounter(u32 CounterValue);
+u32 RTC_GetPrescaler(void);
+void RTC_SetPrescaler(u32 PrescalerValue);
+void RTC_SetAlarm(u32 AlarmValue);
+u32 RTC_GetDivider(void);
+void RTC_WaitForLastTask(void);
+void RTC_WaitForSynchro(void);
+FlagStatus RTC_GetFlagStatus(u16 RTC_FLAG);
+void RTC_ClearFlag(u16 RTC_FLAG);
+ITStatus RTC_GetITStatus(u16 RTC_IT);
+void RTC_ClearITPendingBit(u16 RTC_IT);
+
+#endif /* __STM32F10x_RTC_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_spi.h b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_spi.h
new file mode 100644
index 0000000..3ca55e4
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_spi.h
@@ -0,0 +1,202 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_spi.h
+* Author : MCD Application Team
+* Date First Issued : 09/29/2006
+* Description : This file contains all the functions prototypes for the
+* SPI firmware library.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_SPI_H
+#define __STM32F10x_SPI_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* SPI Init structure definition */
+typedef struct
+{
+ u16 SPI_Direction;
+ u16 SPI_Mode;
+ u16 SPI_DataSize;
+ u16 SPI_CPOL;
+ u16 SPI_CPHA;
+ u16 SPI_NSS;
+ u16 SPI_BaudRatePrescaler;
+ u16 SPI_FirstBit;
+ u16 SPI_CRCPolynomial;
+}SPI_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/* SPI data direction mode */
+#define SPI_Direction_2Lines_FullDuplex ((u16)0x0000)
+#define SPI_Direction_2Lines_RxOnly ((u16)0x0400)
+#define SPI_Direction_1Line_Rx ((u16)0x8000)
+#define SPI_Direction_1Line_Tx ((u16)0xC000)
+
+#define IS_SPI_DIRECTION_MODE(MODE) ((MODE == SPI_Direction_2Lines_FullDuplex) || \
+ (MODE == SPI_Direction_2Lines_RxOnly) || \
+ (MODE == SPI_Direction_1Line_Rx) || \
+ (MODE == SPI_Direction_1Line_Tx))
+
+/* SPI master/slave mode */
+#define SPI_Mode_Master ((u16)0x0104)
+#define SPI_Mode_Slave ((u16)0x0000)
+
+#define IS_SPI_MODE(MODE) ((MODE == SPI_Mode_Master) || \
+ (MODE == SPI_Mode_Slave))
+
+/* SPI data size */
+#define SPI_DataSize_16b ((u16)0x0800)
+#define SPI_DataSize_8b ((u16)0x0000)
+
+#define IS_SPI_DATASIZE(DATASIZE) ((DATASIZE == SPI_DataSize_16b) || \
+ (DATASIZE == SPI_DataSize_8b))
+
+/* SPI Clock Polarity */
+#define SPI_CPOL_Low ((u16)0x0000)
+#define SPI_CPOL_High ((u16)0x0002)
+
+#define IS_SPI_CPOL(CPOL) ((CPOL == SPI_CPOL_Low) || \
+ (CPOL == SPI_CPOL_High))
+
+/* SPI Clock Phase */
+#define SPI_CPHA_1Edge ((u16)0x0000)
+#define SPI_CPHA_2Edge ((u16)0x0001)
+
+#define IS_SPI_CPHA(CPHA) ((CPHA == SPI_CPHA_1Edge) || \
+ (CPHA == SPI_CPHA_2Edge))
+
+/* SPI Slave Select management */
+#define SPI_NSS_Soft ((u16)0x0200)
+#define SPI_NSS_Hard ((u16)0x0000)
+
+#define IS_SPI_NSS(NSS) ((NSS == SPI_NSS_Soft) || \
+ (NSS == SPI_NSS_Hard))
+
+/* SPI BaudRate Prescaler */
+#define SPI_BaudRatePrescaler_2 ((u16)0x0000)
+#define SPI_BaudRatePrescaler_4 ((u16)0x0008)
+#define SPI_BaudRatePrescaler_8 ((u16)0x0010)
+#define SPI_BaudRatePrescaler_16 ((u16)0x0018)
+#define SPI_BaudRatePrescaler_32 ((u16)0x0020)
+#define SPI_BaudRatePrescaler_64 ((u16)0x0028)
+#define SPI_BaudRatePrescaler_128 ((u16)0x0030)
+#define SPI_BaudRatePrescaler_256 ((u16)0x0038)
+
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) ((PRESCALER == SPI_BaudRatePrescaler_2) || \
+ (PRESCALER == SPI_BaudRatePrescaler_4) || \
+ (PRESCALER == SPI_BaudRatePrescaler_8) || \
+ (PRESCALER == SPI_BaudRatePrescaler_16) || \
+ (PRESCALER == SPI_BaudRatePrescaler_32) || \
+ (PRESCALER == SPI_BaudRatePrescaler_64) || \
+ (PRESCALER == SPI_BaudRatePrescaler_128) || \
+ (PRESCALER == SPI_BaudRatePrescaler_256))
+
+/* SPI MSB/LSB transmission */
+#define SPI_FirstBit_MSB ((u16)0x0000)
+#define SPI_FirstBit_LSB ((u16)0x0080)
+
+#define IS_SPI_FIRST_BIT(BIT) ((BIT == SPI_FirstBit_MSB) || \
+ (BIT == SPI_FirstBit_LSB))
+
+/* SPI DMA transfer requests */
+#define SPI_DMAReq_Tx ((u16)0x0002)
+#define SPI_DMAReq_Rx ((u16)0x0001)
+
+#define IS_SPI_DMA_REQ(REQ) (((REQ & (u16)0xFFFC) == 0x00) && (REQ != 0x00))
+
+/* SPI NSS internal software mangement */
+#define SPI_NSSInternalSoft_Set ((u16)0x0100)
+#define SPI_NSSInternalSoft_Reset ((u16)0xFEFF)
+
+#define IS_SPI_NSS_INTERNAL(INTERNAL) ((INTERNAL == SPI_NSSInternalSoft_Set) || \
+ (INTERNAL == SPI_NSSInternalSoft_Reset))
+
+/* SPI CRC Transmit/Receive */
+#define SPI_CRC_Tx ((u8)0x00)
+#define SPI_CRC_Rx ((u8)0x01)
+
+#define IS_SPI_CRC(CRC) ((CRC == SPI_CRC_Tx) || (CRC == SPI_CRC_Rx))
+
+/* SPI direction transmit/receive */
+#define SPI_Direction_Rx ((u16)0xBFFF)
+#define SPI_Direction_Tx ((u16)0x4000)
+
+#define IS_SPI_DIRECTION(DIRECTION) ((DIRECTION == SPI_Direction_Rx) || \
+ (DIRECTION == SPI_Direction_Tx))
+
+/* SPI interrupts definition */
+#define SPI_IT_TXE ((u8)0x71)
+#define SPI_IT_RXNE ((u8)0x60)
+#define SPI_IT_ERR ((u8)0x50)
+
+#define IS_SPI_CONFIG_IT(IT) ((IT == SPI_IT_TXE) || (IT == SPI_IT_RXNE) || \
+ (IT == SPI_IT_ERR))
+
+#define SPI_IT_OVR ((u8)0x56)
+#define SPI_IT_MODF ((u8)0x55)
+#define SPI_IT_CRCERR ((u8)0x54)
+
+#define IS_SPI_CLEAR_IT(IT) ((IT == SPI_IT_OVR) || (IT == SPI_IT_MODF) || \
+ (IT == SPI_IT_CRCERR))
+
+#define IS_SPI_GET_IT(IT) ((IT == SPI_IT_TXE) || (IT == SPI_IT_RXNE) || \
+ (IT == SPI_IT_OVR) || (IT == SPI_IT_MODF) || \
+ (IT == SPI_IT_CRCERR))
+
+/* SPI flags definition */
+#define SPI_FLAG_RXNE ((u16)0x0001)
+#define SPI_FLAG_TXE ((u16)0x0002)
+#define SPI_FLAG_CRCERR ((u16)0x0010)
+#define SPI_FLAG_MODF ((u16)0x0020)
+#define SPI_FLAG_OVR ((u16)0x0040)
+#define SPI_FLAG_BSY ((u16)0x0080)
+
+#define IS_SPI_CLEAR_FLAG(FLAG) (((FLAG & (u16)0xFF8F) == 0x00) && (FLAG != 0x00))
+#define IS_SPI_GET_FLAG(FLAG) ((FLAG == SPI_FLAG_BSY) || (FLAG == SPI_FLAG_OVR) || \
+ (FLAG == SPI_FLAG_MODF) || (FLAG == SPI_FLAG_CRCERR) || \
+ (FLAG == SPI_FLAG_TXE) || (FLAG == SPI_FLAG_RXNE))
+
+/* SPI CRC polynomial --------------------------------------------------------*/
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (POLYNOMIAL >= 0x1)
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void SPI_DeInit(SPI_TypeDef* SPIx);
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_ITConfig(SPI_TypeDef* SPIx, u8 SPI_IT, FunctionalState NewState);
+void SPI_DMACmd(SPI_TypeDef* SPIx, u16 SPI_DMAReq, FunctionalState NewState);
+void SPI_SendData(SPI_TypeDef* SPIx, u16 Data);
+u16 SPI_ReceiveData(SPI_TypeDef* SPIx);
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, u16 SPI_NSSInternalSoft);
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, u16 SPI_DataSize);
+void SPI_TransmitCRC(SPI_TypeDef* SPIx);
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
+u16 SPI_GetCRC(SPI_TypeDef* SPIx, u8 SPI_CRC);
+u16 SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, u16 SPI_Direction);
+FlagStatus SPI_GetFlagStatus(SPI_TypeDef* SPIx, u16 SPI_FLAG);
+void SPI_ClearFlag(SPI_TypeDef* SPIx, u16 SPI_FLAG);
+ITStatus SPI_GetITStatus(SPI_TypeDef* SPIx, u8 SPI_IT);
+void SPI_ClearITPendingBit(SPI_TypeDef* SPIx, u8 SPI_IT);
+
+#endif /*__STM32F10x_SPI_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_systick.h b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_systick.h
new file mode 100644
index 0000000..7060805
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_systick.h
@@ -0,0 +1,68 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_systick.h
+* Author : MCD Application Team
+* Date First Issued : 09/29/2006
+* Description : This file contains all the functions prototypes for the
+* SysTick firmware library.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_SYSTICK_H
+#define __STM32F10x_SYSTICK_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* SysTick clock source */
+#define SysTick_CLKSource_HCLK_Div8 ((u32)0xFFFFFFFB)
+#define SysTick_CLKSource_HCLK ((u32)0x00000004)
+
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) ((SOURCE == SysTick_CLKSource_HCLK) || \
+ (SOURCE == SysTick_CLKSource_HCLK_Div8))
+
+/* SysTick counter state */
+#define SysTick_Counter_Disable ((u32)0xFFFFFFFE)
+#define SysTick_Counter_Enable ((u32)0x00000001)
+#define SysTick_Counter_Clear ((u32)0x00000000)
+
+#define IS_SYSTICK_COUNTER(COUNTER) ((COUNTER == SysTick_Counter_Disable) || \
+ (COUNTER == SysTick_Counter_Enable) || \
+ (COUNTER == SysTick_Counter_Clear))
+
+/* SysTick Flag */
+#define SysTick_FLAG_COUNT ((u8)0x30)
+#define SysTick_FLAG_SKEW ((u8)0x5E)
+#define SysTick_FLAG_NOREF ((u8)0x5F)
+
+#define IS_SYSTICK_FLAG(FLAG) ((FLAG == SysTick_FLAG_COUNT) || \
+ (FLAG == SysTick_FLAG_SKEW) || \
+ (FLAG == SysTick_FLAG_NOREF))
+
+#define IS_SYSTICK_RELOAD(RELOAD) ((RELOAD > 0) || (RELOAD <= 0xFFFFFF))
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void SysTick_CLKSourceConfig(u32 SysTick_CLKSource);
+void SysTick_SetReload(u32 Reload);
+void SysTick_CounterCmd(u32 SysTick_Counter);
+void SysTick_ITConfig(FunctionalState NewState);
+u32 SysTick_GetCounter(void);
+FlagStatus SysTick_GetFlagStatus(u8 SysTick_FLAG);
+
+#endif /* __STM32F10x_SYSTICK_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_tim.h b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_tim.h
new file mode 100644
index 0000000..12f8378
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_tim.h
@@ -0,0 +1,513 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_tim.h
+* Author : MCD Application Team
+* Date First Issued : 09/29/2006
+* Description : This file contains all the functions prototypes for the
+* TIM firmware library.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_TIM_H
+#define __STM32F10x_TIM_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+
+/* TIM Base Init structure definition */
+typedef struct
+{
+ u16 TIM_Period; /* Period value */
+ u16 TIM_Prescaler; /* Prescaler value */
+ u16 TIM_ClockDivision; /* Timer clock division */
+ u16 TIM_CounterMode; /* Timer Counter mode */
+} TIM_TimeBaseInitTypeDef;
+
+/* TIM Output Compare Init structure definition */
+typedef struct
+{
+ u16 TIM_OCMode; /* Timer Output Compare Mode */
+ u16 TIM_Channel; /* Timer Channel */
+ u16 TIM_Pulse; /* PWM or OC Channel pulse length */
+ u16 TIM_OCPolarity; /* PWM, OCM or OPM Channel polarity */
+} TIM_OCInitTypeDef;
+
+/* TIM Input Capture Init structure definition */
+typedef struct
+{
+ u16 TIM_ICMode; /* Timer Input Capture Mode */
+ u16 TIM_Channel; /* Timer Channel */
+ u16 TIM_ICPolarity; /* Input Capture polarity */
+ u16 TIM_ICSelection; /* Input Capture selection */
+ u16 TIM_ICPrescaler; /* Input Capture prescaler */
+ u8 TIM_ICFilter; /* Input Capture filter */
+} TIM_ICInitTypeDef;
+
+/* Exported constants -------------------------------------------------------*/
+/* TIM Ouput Compare modes --------------------------------------------------*/
+#define TIM_OCMode_Timing ((u16)0x0000)
+#define TIM_OCMode_Active ((u16)0x0010)
+#define TIM_OCMode_Inactive ((u16)0x0020)
+#define TIM_OCMode_Toggle ((u16)0x0030)
+#define TIM_OCMode_PWM1 ((u16)0x0060)
+#define TIM_OCMode_PWM2 ((u16)0x0070)
+
+#define IS_TIM_OC_MODE(MODE) ((MODE == TIM_OCMode_Timing) || \
+ (MODE == TIM_OCMode_Active) || \
+ (MODE == TIM_OCMode_Inactive) || \
+ (MODE == TIM_OCMode_Toggle)|| \
+ (MODE == TIM_OCMode_PWM1) || \
+ (MODE == TIM_OCMode_PWM2))
+
+/* TIM Input Capture modes --------------------------------------------------*/
+#define TIM_ICMode_ICAP ((u16)0x0007)
+#define TIM_ICMode_PWMI ((u16)0x0006)
+
+#define IS_TIM_IC_MODE(MODE) ((MODE == TIM_ICMode_ICAP) || \
+ (MODE == TIM_ICMode_PWMI))
+
+/* TIM One Pulse Mode -------------------------------------------------------*/
+#define TIM_OPMode_Single ((u16)0x0008)
+#define TIM_OPMode_Repetitive ((u16)0x0000)
+
+#define IS_TIM_OPM_MODE(MODE) ((MODE == TIM_OPMode_Single) || \
+ (MODE == TIM_OPMode_Repetitive))
+
+/* TIM Channel --------------------------------------------------------------*/
+#define TIM_Channel_1 ((u16)0x0000)
+#define TIM_Channel_2 ((u16)0x0001)
+#define TIM_Channel_3 ((u16)0x0002)
+#define TIM_Channel_4 ((u16)0x0003)
+
+#define IS_TIM_CHANNEL(CHANNEL) ((CHANNEL == TIM_Channel_1) || \
+ (CHANNEL == TIM_Channel_2) || \
+ (CHANNEL == TIM_Channel_3) || \
+ (CHANNEL == TIM_Channel_4))
+
+/* TIM Clock Division CKD ---------------------------------------------------*/
+#define TIM_CKD_DIV1 ((u16)0x0000)
+#define TIM_CKD_DIV2 ((u16)0x0100)
+#define TIM_CKD_DIV4 ((u16)0x0200)
+
+#define IS_TIM_CKD_DIV(DIV) ((DIV == TIM_CKD_DIV1) || \
+ (DIV == TIM_CKD_DIV2) || \
+ (DIV == TIM_CKD_DIV4))
+
+/* TIM Counter Mode ---------------------------------------------------------*/
+#define TIM_CounterMode_Up ((u16)0x0000)
+#define TIM_CounterMode_Down ((u16)0x0010)
+#define TIM_CounterMode_CenterAligned1 ((u16)0x0020)
+#define TIM_CounterMode_CenterAligned2 ((u16)0x0040)
+#define TIM_CounterMode_CenterAligned3 ((u16)0x0060)
+
+#define IS_TIM_COUNTER_MODE(MODE) ((MODE == TIM_CounterMode_Up) || \
+ (MODE == TIM_CounterMode_Down) || \
+ (MODE == TIM_CounterMode_CenterAligned1) || \
+ (MODE == TIM_CounterMode_CenterAligned2) || \
+ (MODE == TIM_CounterMode_CenterAligned3))
+
+/* TIM Output Compare Polarity ----------------------------------------------*/
+#define TIM_OCPolarity_High ((u16)0x0000)
+#define TIM_OCPolarity_Low ((u16)0x0002)
+
+#define IS_TIM_OC_POLARITY(POLARITY) ((POLARITY == TIM_OCPolarity_High) || \
+ (POLARITY == TIM_OCPolarity_Low))
+
+/* TIM Input Capture Polarity -----------------------------------------------*/
+#define TIM_ICPolarity_Rising ((u16)0x0000)
+#define TIM_ICPolarity_Falling ((u16)0x0002)
+
+#define IS_TIM_IC_POLARITY(POLARITY) ((POLARITY == TIM_ICPolarity_Rising) || \
+ (POLARITY == TIM_ICPolarity_Falling))
+
+/* TIM Input Capture Channel Selection -------------------------------------*/
+#define TIM_ICSelection_DirectTI ((u16)0x0001)
+#define TIM_ICSelection_IndirectTI ((u16)0x0002)
+#define TIM_ICSelection_TRGI ((u16)0x0003)
+
+#define IS_TIM_IC_SELECTION(SELECTION) ((SELECTION == TIM_ICSelection_DirectTI) || \
+ (SELECTION == TIM_ICSelection_IndirectTI) || \
+ (SELECTION == TIM_ICSelection_TRGI))
+
+/* TIM Input Capture Prescaler ----------------------------------------------*/
+#define TIM_ICPSC_DIV1 ((u16)0x0000)
+#define TIM_ICPSC_DIV2 ((u16)0x0004)
+#define TIM_ICPSC_DIV4 ((u16)0x0008)
+#define TIM_ICPSC_DIV8 ((u16)0x000C)
+
+#define IS_TIM_IC_PRESCALER(PRESCALER) ((PRESCALER == TIM_ICPSC_DIV1) || \
+ (PRESCALER == TIM_ICPSC_DIV2) || \
+ (PRESCALER == TIM_ICPSC_DIV4) || \
+ (PRESCALER == TIM_ICPSC_DIV8))
+
+/* TIM Input Capture Filer Value ---------------------------------------------*/
+#define IS_TIM_IC_FILTER(ICFILTER) (ICFILTER <= 0xF)
+
+/* TIM interrupt sources ----------------------------------------------------*/
+#define TIM_IT_Update ((u16)0x0001)
+#define TIM_IT_CC1 ((u16)0x0002)
+#define TIM_IT_CC2 ((u16)0x0004)
+#define TIM_IT_CC3 ((u16)0x0008)
+#define TIM_IT_CC4 ((u16)0x0010)
+#define TIM_IT_Trigger ((u16)0x0040)
+
+#define IS_TIM_IT(IT) (((IT & (u16)0xFFA0) == 0x0000) && (IT != 0x0000))
+
+#define IS_TIM_GET_IT(IT) ((IT == TIM_IT_Update) || \
+ (IT == TIM_IT_CC1) || \
+ (IT == TIM_IT_CC2) || \
+ (IT == TIM_IT_CC3) || \
+ (IT == TIM_IT_CC4) || \
+ (IT == TIM_IT_Trigger))
+
+/* TIM DMA Base address -----------------------------------------------------*/
+#define TIM_DMABase_CR1 ((u16)0x0000)
+#define TIM_DMABase_CR2 ((u16)0x0001)
+#define TIM_DMABase_SMCR ((u16)0x0002)
+#define TIM_DMABase_DIER ((u16)0x0003)
+#define TIM_DMABase_SR ((u16)0x0004)
+#define TIM_DMABase_EGR ((u16)0x0005)
+#define TIM_DMABase_CCMR1 ((u16)0x0006)
+#define TIM_DMABase_CCMR2 ((u16)0x0007)
+#define TIM_DMABase_CCER ((u16)0x0008)
+#define TIM_DMABase_CNT ((u16)0x0009)
+#define TIM_DMABase_PSC ((u16)0x000A)
+#define TIM_DMABase_ARR ((u16)0x000B)
+#define TIM_DMABase_CCR1 ((u16)0x000D)
+#define TIM_DMABase_CCR2 ((u16)0x000E)
+#define TIM_DMABase_CCR3 ((u16)0x000F)
+#define TIM_DMABase_CCR4 ((u16)0x0010)
+#define TIM_DMABase_DCR ((u16)0x0012)
+
+#define IS_TIM_DMA_BASE(BASE) ((BASE == TIM_DMABase_CR1) || \
+ (BASE == TIM_DMABase_CR2) || \
+ (BASE == TIM_DMABase_SMCR) || \
+ (BASE == TIM_DMABase_DIER) || \
+ (BASE == TIM_DMABase_SR) || \
+ (BASE == TIM_DMABase_EGR) || \
+ (BASE == TIM_DMABase_CCMR1) || \
+ (BASE == TIM_DMABase_CCMR2) || \
+ (BASE == TIM_DMABase_CCER) || \
+ (BASE == TIM_DMABase_CNT) || \
+ (BASE == TIM_DMABase_PSC) || \
+ (BASE == TIM_DMABase_ARR) || \
+ (BASE == TIM_DMABase_CCR1) || \
+ (BASE == TIM_DMABase_CCR2) || \
+ (BASE == TIM_DMABase_CCR3) || \
+ (BASE == TIM_DMABase_CCR4) || \
+ (BASE == TIM_DMABase_DCR))
+
+/* TIM DMA Burst Length -----------------------------------------------------*/
+#define TIM_DMABurstLength_1Byte ((u16)0x0000)
+#define TIM_DMABurstLength_2Bytes ((u16)0x0100)
+#define TIM_DMABurstLength_3Bytes ((u16)0x0200)
+#define TIM_DMABurstLength_4Bytes ((u16)0x0300)
+#define TIM_DMABurstLength_5Bytes ((u16)0x0400)
+#define TIM_DMABurstLength_6Bytes ((u16)0x0500)
+#define TIM_DMABurstLength_7Bytes ((u16)0x0600)
+#define TIM_DMABurstLength_8Bytes ((u16)0x0700)
+#define TIM_DMABurstLength_9Bytes ((u16)0x0800)
+#define TIM_DMABurstLength_10Bytes ((u16)0x0900)
+#define TIM_DMABurstLength_11Bytes ((u16)0x0A00)
+#define TIM_DMABurstLength_12Bytes ((u16)0x0B00)
+#define TIM_DMABurstLength_13Bytes ((u16)0x0C00)
+#define TIM_DMABurstLength_14Bytes ((u16)0x0D00)
+#define TIM_DMABurstLength_15Bytes ((u16)0x0E00)
+#define TIM_DMABurstLength_16Bytes ((u16)0x0F00)
+#define TIM_DMABurstLength_17Bytes ((u16)0x1000)
+#define TIM_DMABurstLength_18Bytes ((u16)0x1100)
+
+#define IS_TIM_DMA_LENGTH(LENGTH) ((LENGTH == TIM_DMABurstLength_1Byte) || \
+ (LENGTH == TIM_DMABurstLength_2Bytes) || \
+ (LENGTH == TIM_DMABurstLength_3Bytes) || \
+ (LENGTH == TIM_DMABurstLength_4Bytes) || \
+ (LENGTH == TIM_DMABurstLength_5Bytes) || \
+ (LENGTH == TIM_DMABurstLength_6Bytes) || \
+ (LENGTH == TIM_DMABurstLength_7Bytes) || \
+ (LENGTH == TIM_DMABurstLength_8Bytes) || \
+ (LENGTH == TIM_DMABurstLength_9Bytes) || \
+ (LENGTH == TIM_DMABurstLength_10Bytes) || \
+ (LENGTH == TIM_DMABurstLength_11Bytes) || \
+ (LENGTH == TIM_DMABurstLength_12Bytes) || \
+ (LENGTH == TIM_DMABurstLength_13Bytes) || \
+ (LENGTH == TIM_DMABurstLength_14Bytes) || \
+ (LENGTH == TIM_DMABurstLength_15Bytes) || \
+ (LENGTH == TIM_DMABurstLength_16Bytes) || \
+ (LENGTH == TIM_DMABurstLength_17Bytes) || \
+ (LENGTH == TIM_DMABurstLength_18Bytes))
+
+/* TIM DMA sources ----------------------------------------------------------*/
+#define TIM_DMA_Update ((u16)0x0100)
+#define TIM_DMA_CC1 ((u16)0x0200)
+#define TIM_DMA_CC2 ((u16)0x0400)
+#define TIM_DMA_CC3 ((u16)0x0800)
+#define TIM_DMA_CC4 ((u16)0x1000)
+#define TIM_DMA_Trigger ((u16)0x4000)
+
+#define IS_TIM_DMA_SOURCE(SOURCE) (((SOURCE & (u16)0xA0FF) == 0x0000) && (SOURCE != 0x0000))
+
+/* TIM External Trigger Prescaler -------------------------------------------*/
+#define TIM_ExtTRGPSC_OFF ((u16)0x0000)
+#define TIM_ExtTRGPSC_DIV2 ((u16)0x1000)
+#define TIM_ExtTRGPSC_DIV4 ((u16)0x2000)
+#define TIM_ExtTRGPSC_DIV8 ((u16)0x3000)
+
+#define IS_TIM_EXT_PRESCALER(PRESCALER) ((PRESCALER == TIM_ExtTRGPSC_OFF) || \
+ (PRESCALER == TIM_ExtTRGPSC_DIV2) || \
+ (PRESCALER == TIM_ExtTRGPSC_DIV4) || \
+ (PRESCALER == TIM_ExtTRGPSC_DIV8))
+
+/* TIM Input Trigger Selection ---------------------------------------------*/
+#define TIM_TS_ITR0 ((u16)0x0000)
+#define TIM_TS_ITR1 ((u16)0x0010)
+#define TIM_TS_ITR2 ((u16)0x0020)
+#define TIM_TS_ITR3 ((u16)0x0030)
+#define TIM_TS_TI1F_ED ((u16)0x0040)
+#define TIM_TS_TI1FP1 ((u16)0x0050)
+#define TIM_TS_TI2FP2 ((u16)0x0060)
+#define TIM_TS_ETRF ((u16)0x0070)
+
+#define IS_TIM_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM_TS_ITR0) || \
+ (SELECTION == TIM_TS_ITR1) || \
+ (SELECTION == TIM_TS_ITR2) || \
+ (SELECTION == TIM_TS_ITR3) || \
+ (SELECTION == TIM_TS_TI1F_ED) || \
+ (SELECTION == TIM_TS_TI1FP1) || \
+ (SELECTION == TIM_TS_TI2FP2) || \
+ (SELECTION == TIM_TS_ETRF))
+
+#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM_TS_ITR0) || \
+ (SELECTION == TIM_TS_ITR1) || \
+ (SELECTION == TIM_TS_ITR2) || \
+ (SELECTION == TIM_TS_ITR3))
+
+#define IS_TIM_TIX_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM_TS_TI1F_ED) || \
+ (SELECTION == TIM_TS_TI1FP1) || \
+ (SELECTION == TIM_TS_TI2FP2))
+
+/* TIM External Trigger Polarity --------------------------------------------*/
+#define TIM_ExtTRGPolarity_Inverted ((u16)0x8000)
+#define TIM_ExtTRGPolarity_NonInverted ((u16)0x0000)
+
+#define IS_TIM_EXT_POLARITY(POLARITY) ((POLARITY == TIM_ExtTRGPolarity_Inverted) || \
+ (POLARITY == TIM_ExtTRGPolarity_NonInverted))
+
+/* TIM Prescaler Reload Mode ------------------------------------------------*/
+#define TIM_PSCReloadMode_Update ((u16)0x0000)
+#define TIM_PSCReloadMode_Immediate ((u16)0x0001)
+
+#define IS_TIM_PRESCALER_RELOAD(RELOAD) ((RELOAD == TIM_PSCReloadMode_Update) || \
+ (RELOAD == TIM_PSCReloadMode_Immediate))
+
+/* TIM Forced Action --------------------------------------------------------*/
+#define TIM_ForcedAction_Active ((u16)0x0050)
+#define TIM_ForcedAction_InActive ((u16)0x0040)
+
+#define IS_TIM_FORCED_ACTION(ACTION) ((ACTION == TIM_ForcedAction_Active) || \
+ (ACTION == TIM_ForcedAction_InActive))
+
+/* TIM Encoder Mode ---------------------------------------------------------*/
+#define TIM_EncoderMode_TI1 ((u16)0x0001)
+#define TIM_EncoderMode_TI2 ((u16)0x0002)
+#define TIM_EncoderMode_TI12 ((u16)0x0003)
+
+#define IS_TIM_ENCODER_MODE(MODE) ((MODE == TIM_EncoderMode_TI1) || \
+ (MODE == TIM_EncoderMode_TI2) || \
+ (MODE == TIM_EncoderMode_TI12))
+
+/* TIM Event Source ---------------------------------------------------------*/
+#define TIM_EventSource_Update ((u16)0x0001)
+#define TIM_EventSource_CC1 ((u16)0x0002)
+#define TIM_EventSource_CC2 ((u16)0x0004)
+#define TIM_EventSource_CC3 ((u16)0x0008)
+#define TIM_EventSource_CC4 ((u16)0x0010)
+#define TIM_EventSource_Trigger ((u16)0x0040)
+
+#define IS_TIM_EVENT_SOURCE(SOURCE) (((SOURCE & (u16)0xFFA0) == 0x0000) && (SOURCE != 0x0000))
+
+
+/* TIM Update Source --------------------------------------------------------*/
+#define TIM_UpdateSource_Global ((u16)0x0000)
+#define TIM_UpdateSource_Regular ((u16)0x0001)
+
+#define IS_TIM_UPDATE_SOURCE(SOURCE) ((SOURCE == TIM_UpdateSource_Global) || \
+ (SOURCE == TIM_UpdateSource_Regular))
+
+/* TIM Ouput Compare Preload State ------------------------------------------*/
+#define TIM_OCPreload_Enable ((u16)0x0008)
+#define TIM_OCPreload_Disable ((u16)0x0000)
+
+#define IS_TIM_OCPRELOAD_STATE(STATE) ((STATE == TIM_OCPreload_Enable) || \
+ (STATE == TIM_OCPreload_Disable))
+
+/* TIM Ouput Compare Fast State ---------------------------------------------*/
+#define TIM_OCFast_Enable ((u16)0x0004)
+#define TIM_OCFast_Disable ((u16)0x0000)
+
+#define IS_TIM_OCFAST_STATE(STATE) ((STATE == TIM_OCFast_Enable) || \
+ (STATE == TIM_OCFast_Disable))
+
+/* TIM Trigger Output Source ------------------------------------------------*/
+#define TIM_TRGOSource_Reset ((u16)0x0000)
+#define TIM_TRGOSource_Enable ((u16)0x0010)
+#define TIM_TRGOSource_Update ((u16)0x0020)
+#define TIM_TRGOSource_OC1 ((u16)0x0030)
+#define TIM_TRGOSource_OC1Ref ((u16)0x0040)
+#define TIM_TRGOSource_OC2Ref ((u16)0x0050)
+#define TIM_TRGOSource_OC3Ref ((u16)0x0060)
+#define TIM_TRGOSource_OC4Ref ((u16)0x0070)
+
+#define IS_TIM_TRGO_SOURCE(SOURCE) ((SOURCE == TIM_TRGOSource_Reset) || \
+ (SOURCE == TIM_TRGOSource_Enable) || \
+ (SOURCE == TIM_TRGOSource_Update) || \
+ (SOURCE == TIM_TRGOSource_OC1) || \
+ (SOURCE == TIM_TRGOSource_OC1Ref) || \
+ (SOURCE == TIM_TRGOSource_OC2Ref) || \
+ (SOURCE == TIM_TRGOSource_OC3Ref) || \
+ (SOURCE == TIM_TRGOSource_OC4Ref))
+
+/* TIM Slave Mode -----------------------------------------------------------*/
+#define TIM_SlaveMode_Reset ((u16)0x0004)
+#define TIM_SlaveMode_Gated ((u16)0x0005)
+#define TIM_SlaveMode_Trigger ((u16)0x0006)
+#define TIM_SlaveMode_External1 ((u16)0x0007)
+
+
+#define IS_TIM_SLAVE_MODE(MODE) ((MODE == TIM_SlaveMode_Reset) || \
+ (MODE == TIM_SlaveMode_Gated) || \
+ (MODE == TIM_SlaveMode_Trigger) || \
+ (MODE == TIM_SlaveMode_External1))
+
+/* TIM TIx External Clock Source --------------------------------------------*/
+#define TIM_TIxExternalCLK1Source_TI1 ((u16)0x0050)
+#define TIM_TIxExternalCLK1Source_TI2 ((u16)0x0060)
+#define TIM_TIxExternalCLK1Source_TI1ED ((u16)0x0040)
+
+#define IS_TIM_TIXCLK_SOURCE(SOURCE) ((SOURCE == TIM_TIxExternalCLK1Source_TI1) || \
+ (SOURCE == TIM_TIxExternalCLK1Source_TI2) || \
+ (SOURCE == TIM_TIxExternalCLK1Source_TI1ED))
+
+
+/* TIM Master Slave Mode ----------------------------------------------------*/
+#define TIM_MasterSlaveMode_Enable ((u16)0x0080)
+#define TIM_MasterSlaveMode_Disable ((u16)0x0000)
+
+#define IS_TIM_MSM_STATE(STATE) ((STATE == TIM_MasterSlaveMode_Enable) || \
+ (STATE == TIM_MasterSlaveMode_Disable))
+
+/* TIM Flags ----------------------------------------------------------------*/
+#define TIM_FLAG_Update ((u16)0x0001)
+#define TIM_FLAG_CC1 ((u16)0x0002)
+#define TIM_FLAG_CC2 ((u16)0x0004)
+#define TIM_FLAG_CC3 ((u16)0x0008)
+#define TIM_FLAG_CC4 ((u16)0x0010)
+#define TIM_FLAG_Trigger ((u16)0x0040)
+#define TIM_FLAG_CC1OF ((u16)0x0200)
+#define TIM_FLAG_CC2OF ((u16)0x0400)
+#define TIM_FLAG_CC3OF ((u16)0x0800)
+#define TIM_FLAG_CC4OF ((u16)0x1000)
+
+#define IS_TIM_GET_FLAG(FLAG) ((FLAG == TIM_FLAG_Update) || \
+ (FLAG == TIM_FLAG_CC1) || \
+ (FLAG == TIM_FLAG_CC2) || \
+ (FLAG == TIM_FLAG_CC3) || \
+ (FLAG == TIM_FLAG_CC4) || \
+ (FLAG == TIM_FLAG_Trigger) || \
+ (FLAG == TIM_FLAG_CC1OF) || \
+ (FLAG == TIM_FLAG_CC2OF) || \
+ (FLAG == TIM_FLAG_CC3OF) || \
+ (FLAG == TIM_FLAG_CC4OF))
+
+#define IS_TIM_CLEAR_FLAG(FLAG) (((FLAG & (u16)0xE1A0) == 0x0000) && (FLAG != 0x0000))
+
+
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+void TIM_DeInit(TIM_TypeDef* TIMx);
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
+void TIM_OCInit(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_ITConfig(TIM_TypeDef* TIMx, u16 TIM_IT, FunctionalState NewState);
+void TIM_DMAConfig(TIM_TypeDef* TIMx, u16 TIM_DMABase, u16 TIM_DMABurstLength);
+void TIM_DMACmd(TIM_TypeDef* TIMx, u16 TIM_DMASource, FunctionalState Newstate);
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource);
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, u16 TIM_TIxExternalCLKSource,
+ u16 TIM_ICPolarity, u8 ICFilter);
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity,
+ u8 ExtTRGFilter);
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity,
+ u8 ExtTRGFilter);
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource);
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, u16 Prescaler, u16 TIM_PSCReloadMode);
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, u16 TIM_CounterMode);
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction);
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction);
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction);
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction);
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState Newstate);
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState Newstate);
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload);
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload);
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload);
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload);
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast);
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast);
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast);
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast);
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState Newstate);
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, u16 TIM_EncoderMode,
+ u16 TIM_IC1Polarity, u16 TIM_IC2Polarity);
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, u16 TIM_EventSource);
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity);
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity);
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity);
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity);
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, u16 TIM_UpdateSource);
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState Newstate);
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, u16 TIM_OPMode);
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, u16 TIM_TRGOSource);
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, u16 TIM_SlaveMode);
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, u16 TIM_MasterSlaveMode);
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, u16 Autoreload);
+void TIM_SetCompare1(TIM_TypeDef* TIMx, u16 Compare1);
+void TIM_SetCompare2(TIM_TypeDef* TIMx, u16 Compare2);
+void TIM_SetCompare3(TIM_TypeDef* TIMx, u16 Compare3);
+void TIM_SetCompare4(TIM_TypeDef* TIMx, u16 Compare4);
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC1Prescaler);
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC2Prescaler);
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC3Prescaler);
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC4Prescaler);
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, u16 TIM_CKD);
+u16 TIM_GetCapture1(TIM_TypeDef* TIMx);
+u16 TIM_GetCapture2(TIM_TypeDef* TIMx);
+u16 TIM_GetCapture3(TIM_TypeDef* TIMx);
+u16 TIM_GetCapture4(TIM_TypeDef* TIMx);
+u16 TIM_GetCounter(TIM_TypeDef* TIMx);
+u16 TIM_GetPrescaler(TIM_TypeDef* TIMx);
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, u16 TIM_FLAG);
+void TIM_ClearFlag(TIM_TypeDef* TIMx, u16 TIM_FLAG);
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, u16 TIM_IT);
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, u16 TIM_IT);
+
+#endif /*__STM32F10x_TIM_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_tim1.h b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_tim1.h
new file mode 100644
index 0000000..b83761d
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_tim1.h
@@ -0,0 +1,644 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_tim1.h
+* Author : MCD Application Team
+* Date First Issued : 09/29/2006
+* Description : This file contains all the functions prototypes for the
+* TIM1 firmware library.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* mm/dd/yyyy: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_TIM1_H
+#define __STM32F10x_TIM1_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+
+/* TIM1 Time Base Init structure definition */
+typedef struct
+{
+ u16 TIM1_Prescaler;
+ u16 TIM1_CounterMode;
+ u16 TIM1_Period;
+ u16 TIM1_ClockDivision;
+ u8 TIM1_RepetitionCounter;
+} TIM1_TimeBaseInitTypeDef;
+
+/* TIM1 Output Compare Init structure definition */
+typedef struct
+{
+ u16 TIM1_OCMode;
+ u16 TIM1_OutputState;
+ u16 TIM1_OutputNState;
+ u16 TIM1_Pulse;
+ u16 TIM1_OCPolarity;
+ u16 TIM1_OCNPolarity;
+ u16 TIM1_OCIdleState;
+ u16 TIM1_OCNIdleState;
+} TIM1_OCInitTypeDef;
+
+/* TIM1 Input Capture Init structure definition */
+typedef struct
+{
+ u16 TIM1_Channel;
+ u16 TIM1_ICPolarity;
+ u16 TIM1_ICSelection;
+ u16 TIM1_ICPrescaler;
+ u8 TIM1_ICFilter;
+} TIM1_ICInitTypeDef;
+
+/* BDTR structure definition */
+typedef struct
+{
+ u16 TIM1_OSSRState;
+ u16 TIM1_OSSIState;
+ u16 TIM1_LOCKLevel;
+ u16 TIM1_DeadTime;
+ u16 TIM1_Break;
+ u16 TIM1_BreakPolarity;
+ u16 TIM1_AutomaticOutput;
+} TIM1_BDTRInitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/* TIM1 Output Compare and PWM modes ----------------------------------------*/
+#define TIM1_OCMode_Timing ((u16)0x0000)
+#define TIM1_OCMode_Active ((u16)0x0010)
+#define TIM1_OCMode_Inactive ((u16)0x0020)
+#define TIM1_OCMode_Toggle ((u16)0x0030)
+#define TIM1_OCMode_PWM1 ((u16)0x0060)
+#define TIM1_OCMode_PWM2 ((u16)0x0070)
+
+#define IS_TIM1_OC_MODE(MODE) ((MODE == TIM1_OCMode_Timing) || \
+ (MODE == TIM1_OCMode_Active) || \
+ (MODE == TIM1_OCMode_Inactive) || \
+ (MODE == TIM1_OCMode_Toggle)|| \
+ (MODE == TIM1_OCMode_PWM1) || \
+ (MODE == TIM1_OCMode_PWM2))
+
+#define IS_TIM1_OCM(MODE)((MODE == TIM1_OCMode_Timing) || \
+ (MODE == TIM1_OCMode_Active) || \
+ (MODE == TIM1_OCMode_Inactive) || \
+ (MODE == TIM1_OCMode_Toggle)|| \
+ (MODE == TIM1_OCMode_PWM1) || \
+ (MODE == TIM1_OCMode_PWM2) || \
+ (MODE == TIM1_ForcedAction_Active) || \
+ (MODE == TIM1_ForcedAction_InActive))
+/* TIM1 One Pulse Mode ------------------------------------------------------*/
+#define TIM1_OPMode_Single ((u16)0x0001)
+#define TIM1_OPMode_Repetitive ((u16)0x0000)
+
+#define IS_TIM1_OPM_MODE(MODE) ((MODE == TIM1_OPMode_Single) || \
+ (MODE == TIM1_OPMode_Repetitive))
+
+/* TIM1 Channel -------------------------------------------------------------*/
+#define TIM1_Channel_1 ((u16)0x0000)
+#define TIM1_Channel_2 ((u16)0x0001)
+#define TIM1_Channel_3 ((u16)0x0002)
+#define TIM1_Channel_4 ((u16)0x0003)
+
+#define IS_TIM1_CHANNEL(CHANNEL) ((CHANNEL == TIM1_Channel_1) || \
+ (CHANNEL == TIM1_Channel_2) || \
+ (CHANNEL == TIM1_Channel_3) || \
+ (CHANNEL == TIM1_Channel_4))
+
+#define IS_TIM1_PWMI_CHANNEL(CHANNEL) ((CHANNEL == TIM1_Channel_1) || \
+ (CHANNEL == TIM1_Channel_2))
+
+#define IS_TIM1_COMPLEMENTARY_CHANNEL(CHANNEL) ((CHANNEL == TIM1_Channel_1) || \
+ (CHANNEL == TIM1_Channel_2) || \
+ (CHANNEL == TIM1_Channel_3))
+/* TIM1 Clock Division CKD --------------------------------------------------*/
+#define TIM1_CKD_DIV1 ((u16)0x0000)
+#define TIM1_CKD_DIV2 ((u16)0x0100)
+#define TIM1_CKD_DIV4 ((u16)0x0200)
+
+#define IS_TIM1_CKD_DIV(DIV) ((DIV == TIM1_CKD_DIV1) || \
+ (DIV == TIM1_CKD_DIV2) || \
+ (DIV == TIM1_CKD_DIV4))
+
+/* TIM1 Counter Mode --------------------------------------------------------*/
+#define TIM1_CounterMode_Up ((u16)0x0000)
+#define TIM1_CounterMode_Down ((u16)0x0010)
+#define TIM1_CounterMode_CenterAligned1 ((u16)0x0020)
+#define TIM1_CounterMode_CenterAligned2 ((u16)0x0040)
+#define TIM1_CounterMode_CenterAligned3 ((u16)0x0060)
+
+#define IS_TIM1_COUNTER_MODE(MODE) ((MODE == TIM1_CounterMode_Up) || \
+ (MODE == TIM1_CounterMode_Down) || \
+ (MODE == TIM1_CounterMode_CenterAligned1) || \
+ (MODE == TIM1_CounterMode_CenterAligned2) || \
+ (MODE == TIM1_CounterMode_CenterAligned3))
+
+/* TIM1 Output Compare Polarity ---------------------------------------------*/
+#define TIM1_OCPolarity_High ((u16)0x0000)
+#define TIM1_OCPolarity_Low ((u16)0x0001)
+
+#define IS_TIM1_OC_POLARITY(POLARITY) ((POLARITY == TIM1_OCPolarity_High) || \
+ (POLARITY == TIM1_OCPolarity_Low))
+
+/* TIM1 Output Compare N Polarity -------------------------------------------*/
+#define TIM1_OCNPolarity_High ((u16)0x0000)
+#define TIM1_OCNPolarity_Low ((u16)0x0001)
+
+#define IS_TIM1_OCN_POLARITY(POLARITY) ((POLARITY == TIM1_OCNPolarity_High) || \
+ (POLARITY == TIM1_OCNPolarity_Low))
+
+/* TIM1 Output Compare states -----------------------------------------------*/
+#define TIM1_OutputState_Disable ((u16)0x0000)
+#define TIM1_OutputState_Enable ((u16)0x0001)
+
+#define IS_TIM1_OUTPUT_STATE(STATE) ((STATE == TIM1_OutputState_Disable) || \
+ (STATE == TIM1_OutputState_Enable))
+
+/* TIM1 Output Compare N States ---------------------------------------------*/
+#define TIM1_OutputNState_Disable ((u16)0x0000)
+#define TIM1_OutputNState_Enable ((u16)0x0001)
+
+#define IS_TIM1_OUTPUTN_STATE(STATE) ((STATE == TIM1_OutputNState_Disable) || \
+ (STATE == TIM1_OutputNState_Enable))
+
+/* Break Input enable/disable -----------------------------------------------*/
+#define TIM1_Break_Enable ((u16)0x1000)
+#define TIM1_Break_Disable ((u16)0x0000)
+
+#define IS_TIM1_BREAK_STATE(STATE) ((STATE == TIM1_Break_Enable) || \
+ (STATE == TIM1_Break_Disable))
+
+/* Break Polarity -----------------------------------------------------------*/
+#define TIM1_BreakPolarity_Low ((u16)0x0000)
+#define TIM1_BreakPolarity_High ((u16)0x2000)
+
+#define IS_TIM1_BREAK_POLARITY(POLARITY) ((POLARITY == TIM1_BreakPolarity_Low) || \
+ (POLARITY == TIM1_BreakPolarity_High))
+
+/* TIM1 AOE Bit Set/Reset ---------------------------------------------------*/
+#define TIM1_AutomaticOutput_Enable ((u16)0x4000)
+#define TIM1_AutomaticOutput_Disable ((u16)0x0000)
+
+#define IS_TIM1_AUTOMATIC_OUTPUT_STATE(STATE) ((STATE == TIM1_AutomaticOutput_Enable) || \
+ (STATE == TIM1_AutomaticOutput_Disable))
+/* Lock levels --------------------------------------------------------------*/
+#define TIM1_LOCKLevel_OFF ((u16)0x0000)
+#define TIM1_LOCKLevel_1 ((u16)0x0100)
+#define TIM1_LOCKLevel_2 ((u16)0x0200)
+#define TIM1_LOCKLevel_3 ((u16)0x0300)
+
+#define IS_TIM1_LOCK_LEVEL(LEVEL) ((LEVEL == TIM1_LOCKLevel_OFF) || \
+ (LEVEL == TIM1_LOCKLevel_1) || \
+ (LEVEL == TIM1_LOCKLevel_2) || \
+ (LEVEL == TIM1_LOCKLevel_3))
+
+/* OSSI: Off-State Selection for Idle mode states ---------------------------*/
+#define TIM1_OSSIState_Enable ((u16)0x0400)
+#define TIM1_OSSIState_Disable ((u16)0x0000)
+
+#define IS_TIM1_OSSI_STATE(STATE) ((STATE == TIM1_OSSIState_Enable) || \
+ (STATE == TIM1_OSSIState_Disable))
+
+/* OSSR: Off-State Selection for Run mode states ----------------------------*/
+#define TIM1_OSSRState_Enable ((u16)0x0800)
+#define TIM1_OSSRState_Disable ((u16)0x0000)
+
+#define IS_TIM1_OSSR_STATE(STATE) ((STATE == TIM1_OSSRState_Enable) || \
+ (STATE == TIM1_OSSRState_Disable))
+
+/* TIM1 Output Compare Idle State -------------------------------------------*/
+#define TIM1_OCIdleState_Set ((u16)0x0001)
+#define TIM1_OCIdleState_Reset ((u16)0x0000)
+
+#define IS_TIM1_OCIDLE_STATE(STATE) ((STATE == TIM1_OCIdleState_Set) || \
+ (STATE == TIM1_OCIdleState_Reset))
+
+/* TIM1 Output Compare N Idle State -----------------------------------------*/
+#define TIM1_OCNIdleState_Set ((u16)0x0001)
+#define TIM1_OCNIdleState_Reset ((u16)0x0000)
+
+#define IS_TIM1_OCNIDLE_STATE(STATE) ((STATE == TIM1_OCNIdleState_Set) || \
+ (STATE == TIM1_OCNIdleState_Reset))
+
+/* TIM1 Input Capture Polarity ----------------------------------------------*/
+#define TIM1_ICPolarity_Rising ((u16)0x0000)
+#define TIM1_ICPolarity_Falling ((u16)0x0001)
+
+#define IS_TIM1_IC_POLARITY(POLARITY) ((POLARITY == TIM1_ICPolarity_Rising) || \
+ (POLARITY == TIM1_ICPolarity_Falling))
+
+/* TIM1 Input Capture Selection ---------------------------------------------*/
+#define TIM1_ICSelection_DirectTI ((u16)0x0001)
+#define TIM1_ICSelection_IndirectTI ((u16)0x0002)
+#define TIM1_ICSelection_TRGI ((u16)0x0003)
+
+#define IS_TIM1_IC_SELECTION(SELECTION) ((SELECTION == TIM1_ICSelection_DirectTI) || \
+ (SELECTION == TIM1_ICSelection_IndirectTI) || \
+ (SELECTION == TIM1_ICSelection_TRGI))
+
+/* TIM1 Input Capture Prescaler ---------------------------------------------*/
+#define TIM1_ICPSC_DIV1 ((u16)0x0000)
+#define TIM1_ICPSC_DIV2 ((u16)0x0004)
+#define TIM1_ICPSC_DIV4 ((u16)0x0008)
+#define TIM1_ICPSC_DIV8 ((u16)0x000C)
+
+#define IS_TIM1_IC_PRESCALER(PRESCALER) ((PRESCALER == TIM1_ICPSC_DIV1) || \
+ (PRESCALER == TIM1_ICPSC_DIV2) || \
+ (PRESCALER == TIM1_ICPSC_DIV4) || \
+ (PRESCALER == TIM1_ICPSC_DIV8))
+
+/* TIM1 Input Capture Filer Value ---------------------------------------------*/
+#define IS_TIM1_IC_FILTER(ICFILTER) (ICFILTER <= 0xF)
+
+/* TIM1 interrupt sources ---------------------------------------------------*/
+#define TIM1_IT_Update ((u16)0x0001)
+#define TIM1_IT_CC1 ((u16)0x0002)
+#define TIM1_IT_CC2 ((u16)0x0004)
+#define TIM1_IT_CC3 ((u16)0x0008)
+#define TIM1_IT_CC4 ((u16)0x0010)
+#define TIM1_IT_COM ((u16)0x0020)
+#define TIM1_IT_Trigger ((u16)0x0040)
+#define TIM1_IT_Break ((u16)0x0080)
+
+#define IS_TIM1_IT(IT) (((IT & (u16)0xFF00) == 0x0000) && (IT != 0x0000))
+
+#define IS_TIM1_GET_IT(IT) ((IT == TIM1_IT_Update) || \
+ (IT == TIM1_IT_CC1) || \
+ (IT == TIM1_IT_CC2) || \
+ (IT == TIM1_IT_CC3) || \
+ (IT == TIM1_IT_CC4) || \
+ (IT == TIM1_IT_COM) || \
+ (IT == TIM1_IT_Trigger) || \
+ (IT == TIM1_IT_Break))
+
+/* TIM1 DMA Base address ----------------------------------------------------*/
+#define TIM1_DMABase_CR1 ((u16)0x0000)
+#define TIM1_DMABase_CR2 ((u16)0x0001)
+#define TIM1_DMABase_SMCR ((u16)0x0002)
+#define TIM1_DMABase_DIER ((u16)0x0003)
+#define TIM1_DMABase_SR ((u16)0x0004)
+#define TIM1_DMABase_EGR ((u16)0x0005)
+#define TIM1_DMABase_CCMR1 ((u16)0x0006)
+#define TIM1_DMABase_CCMR2 ((u16)0x0007)
+#define TIM1_DMABase_CCER ((u16)0x0008)
+#define TIM1_DMABase_CNT ((u16)0x0009)
+#define TIM1_DMABase_PSC ((u16)0x000A)
+#define TIM1_DMABase_ARR ((u16)0x000B)
+#define TIM1_DMABase_RCR ((u16)0x000C)
+#define TIM1_DMABase_CCR1 ((u16)0x000D)
+#define TIM1_DMABase_CCR2 ((u16)0x000E)
+#define TIM1_DMABase_CCR3 ((u16)0x000F)
+#define TIM1_DMABase_CCR4 ((u16)0x0010)
+#define TIM1_DMABase_BDTR ((u16)0x0011)
+#define TIM1_DMABase_DCR ((u16)0x0012)
+
+#define IS_TIM1_DMA_BASE(BASE) ((BASE == TIM1_DMABase_CR1) || \
+ (BASE == TIM1_DMABase_CR2) || \
+ (BASE == TIM1_DMABase_SMCR) || \
+ (BASE == TIM1_DMABase_DIER) || \
+ (BASE == TIM1_DMABase_SR) || \
+ (BASE == TIM1_DMABase_EGR) || \
+ (BASE == TIM1_DMABase_CCMR1) || \
+ (BASE == TIM1_DMABase_CCMR2) || \
+ (BASE == TIM1_DMABase_CCER) || \
+ (BASE == TIM1_DMABase_CNT) || \
+ (BASE == TIM1_DMABase_PSC) || \
+ (BASE == TIM1_DMABase_ARR) || \
+ (BASE == TIM1_DMABase_RCR) || \
+ (BASE == TIM1_DMABase_CCR1) || \
+ (BASE == TIM1_DMABase_CCR2) || \
+ (BASE == TIM1_DMABase_CCR3) || \
+ (BASE == TIM1_DMABase_CCR4) || \
+ (BASE == TIM1_DMABase_BDTR) || \
+ (BASE == TIM1_DMABase_DCR))
+
+/* TIM1 DMA Burst Length ----------------------------------------------------*/
+#define TIM1_DMABurstLength_1Byte ((u16)0x0000)
+#define TIM1_DMABurstLength_2Bytes ((u16)0x0100)
+#define TIM1_DMABurstLength_3Bytes ((u16)0x0200)
+#define TIM1_DMABurstLength_4Bytes ((u16)0x0300)
+#define TIM1_DMABurstLength_5Bytes ((u16)0x0400)
+#define TIM1_DMABurstLength_6Bytes ((u16)0x0500)
+#define TIM1_DMABurstLength_7Bytes ((u16)0x0600)
+#define TIM1_DMABurstLength_8Bytes ((u16)0x0700)
+#define TIM1_DMABurstLength_9Bytes ((u16)0x0800)
+#define TIM1_DMABurstLength_10Bytes ((u16)0x0900)
+#define TIM1_DMABurstLength_11Bytes ((u16)0x0A00)
+#define TIM1_DMABurstLength_12Bytes ((u16)0x0B00)
+#define TIM1_DMABurstLength_13Bytes ((u16)0x0C00)
+#define TIM1_DMABurstLength_14Bytes ((u16)0x0D00)
+#define TIM1_DMABurstLength_15Bytes ((u16)0x0E00)
+#define TIM1_DMABurstLength_16Bytes ((u16)0x0F00)
+#define TIM1_DMABurstLength_17Bytes ((u16)0x1000)
+#define TIM1_DMABurstLength_18Bytes ((u16)0x1100)
+
+#define IS_TIM1_DMA_LENGTH(LENGTH) ((LENGTH == TIM1_DMABurstLength_1Byte) || \
+ (LENGTH == TIM1_DMABurstLength_2Bytes) || \
+ (LENGTH == TIM1_DMABurstLength_3Bytes) || \
+ (LENGTH == TIM1_DMABurstLength_4Bytes) || \
+ (LENGTH == TIM1_DMABurstLength_5Bytes) || \
+ (LENGTH == TIM1_DMABurstLength_6Bytes) || \
+ (LENGTH == TIM1_DMABurstLength_7Bytes) || \
+ (LENGTH == TIM1_DMABurstLength_8Bytes) || \
+ (LENGTH == TIM1_DMABurstLength_9Bytes) || \
+ (LENGTH == TIM1_DMABurstLength_10Bytes) || \
+ (LENGTH == TIM1_DMABurstLength_11Bytes) || \
+ (LENGTH == TIM1_DMABurstLength_12Bytes) || \
+ (LENGTH == TIM1_DMABurstLength_13Bytes) || \
+ (LENGTH == TIM1_DMABurstLength_14Bytes) || \
+ (LENGTH == TIM1_DMABurstLength_15Bytes) || \
+ (LENGTH == TIM1_DMABurstLength_16Bytes) || \
+ (LENGTH == TIM1_DMABurstLength_17Bytes) || \
+ (LENGTH == TIM1_DMABurstLength_18Bytes))
+
+/* TIM1 DMA sources ---------------------------------------------------------*/
+#define TIM1_DMA_Update ((u16)0x0100)
+#define TIM1_DMA_CC1 ((u16)0x0200)
+#define TIM1_DMA_CC2 ((u16)0x0400)
+#define TIM1_DMA_CC3 ((u16)0x0800)
+#define TIM1_DMA_CC4 ((u16)0x1000)
+#define TIM1_DMA_COM ((u16)0x2000)
+#define TIM1_DMA_Trigger ((u16)0x4000)
+
+#define IS_TIM1_DMA_SOURCE(SOURCE) (((SOURCE & (u16)0x80FF) == 0x0000) && (SOURCE != 0x0000))
+
+/* TIM1 External Trigger Prescaler ------------------------------------------*/
+#define TIM1_ExtTRGPSC_OFF ((u16)0x0000)
+#define TIM1_ExtTRGPSC_DIV2 ((u16)0x1000)
+#define TIM1_ExtTRGPSC_DIV4 ((u16)0x2000)
+#define TIM1_ExtTRGPSC_DIV8 ((u16)0x3000)
+
+#define IS_TIM1_EXT_PRESCALER(PRESCALER) ((PRESCALER == TIM1_ExtTRGPSC_OFF) || \
+ (PRESCALER == TIM1_ExtTRGPSC_DIV2) || \
+ (PRESCALER == TIM1_ExtTRGPSC_DIV4) || \
+ (PRESCALER == TIM1_ExtTRGPSC_DIV8))
+
+/* TIM1 Internal Trigger Selection ------------------------------------------*/
+#define TIM1_TS_ITR0 ((u16)0x0000)
+#define TIM1_TS_ITR1 ((u16)0x0010)
+#define TIM1_TS_ITR2 ((u16)0x0020)
+#define TIM1_TS_ITR3 ((u16)0x0030)
+#define TIM1_TS_TI1F_ED ((u16)0x0040)
+#define TIM1_TS_TI1FP1 ((u16)0x0050)
+#define TIM1_TS_TI2FP2 ((u16)0x0060)
+#define TIM1_TS_ETRF ((u16)0x0070)
+
+#define IS_TIM1_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM1_TS_ITR0) || \
+ (SELECTION == TIM1_TS_ITR1) || \
+ (SELECTION == TIM1_TS_ITR2) || \
+ (SELECTION == TIM1_TS_ITR3) || \
+ (SELECTION == TIM1_TS_TI1F_ED) || \
+ (SELECTION == TIM1_TS_TI1FP1) || \
+ (SELECTION == TIM1_TS_TI2FP2) || \
+ (SELECTION == TIM1_TS_ETRF))
+
+#define IS_TIM1_INTERNAL_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM1_TS_ITR0) || \
+ (SELECTION == TIM1_TS_ITR1) || \
+ (SELECTION == TIM1_TS_ITR2) || \
+ (SELECTION == TIM1_TS_ITR3))
+
+#define IS_TIM1_TIX_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM1_TS_TI1F_ED) || \
+ (SELECTION == TIM1_TS_TI1FP1) || \
+ (SELECTION == TIM1_TS_TI2FP2))
+
+/* TIM1 External Trigger Polarity -------------------------------------------*/
+#define TIM1_ExtTRGPolarity_Inverted ((u16)0x8000)
+#define TIM1_ExtTRGPolarity_NonInverted ((u16)0x0000)
+
+#define IS_TIM1_EXT_POLARITY(POLARITY) ((POLARITY == TIM1_ExtTRGPolarity_Inverted) || \
+ (POLARITY == TIM1_ExtTRGPolarity_NonInverted))
+
+/* TIM1 Prescaler Reload Mode -----------------------------------------------*/
+#define TIM1_PSCReloadMode_Update ((u16)0x0000)
+#define TIM1_PSCReloadMode_Immediate ((u16)0x0001)
+
+#define IS_TIM1_PRESCALER_RELOAD(RELOAD) ((RELOAD == TIM1_PSCReloadMode_Update) || \
+ (RELOAD == TIM1_PSCReloadMode_Immediate))
+
+/* TIM1 Forced Action -------------------------------------------------------*/
+#define TIM1_ForcedAction_Active ((u16)0x0050)
+#define TIM1_ForcedAction_InActive ((u16)0x0040)
+
+#define IS_TIM1_FORCED_ACTION(ACTION) ((ACTION == TIM1_ForcedAction_Active) || \
+ (ACTION == TIM1_ForcedAction_InActive))
+
+/* TIM1 Encoder Mode --------------------------------------------------------*/
+#define TIM1_EncoderMode_TI1 ((u16)0x0001)
+#define TIM1_EncoderMode_TI2 ((u16)0x0002)
+#define TIM1_EncoderMode_TI12 ((u16)0x0003)
+
+#define IS_TIM1_ENCODER_MODE(MODE) ((MODE == TIM1_EncoderMode_TI1) || \
+ (MODE == TIM1_EncoderMode_TI2) || \
+ (MODE == TIM1_EncoderMode_TI12))
+
+/* TIM1 Event Source --------------------------------------------------------*/
+#define TIM1_EventSource_Update ((u16)0x0001)
+#define TIM1_EventSource_CC1 ((u16)0x0002)
+#define TIM1_EventSource_CC2 ((u16)0x0004)
+#define TIM1_EventSource_CC3 ((u16)0x0008)
+#define TIM1_EventSource_CC4 ((u16)0x0010)
+#define TIM1_EventSource_COM ((u16)0x0020)
+#define TIM1_EventSource_Trigger ((u16)0x0040)
+#define TIM1_EventSource_Break ((u16)0x0080)
+
+#define IS_TIM1_EVENT_SOURCE(SOURCE) (((SOURCE & (u16)0xFF00) == 0x0000) && (SOURCE != 0x0000))
+
+
+/* TIM1 Update Source -------------------------------------------------------*/
+#define TIM1_UpdateSource_Global ((u16)0x0000)
+#define TIM1_UpdateSource_Regular ((u16)0x0001)
+
+#define IS_TIM1_UPDATE_SOURCE(SOURCE) ((SOURCE == TIM1_UpdateSource_Global) || \
+ (SOURCE == TIM1_UpdateSource_Regular))
+
+/* TIM1 Ouput Compare Preload State ------------------------------------------*/
+#define TIM1_OCPreload_Enable ((u16)0x0001)
+#define TIM1_OCPreload_Disable ((u16)0x0000)
+
+#define IS_TIM1_OCPRELOAD_STATE(STATE) ((STATE == TIM1_OCPreload_Enable) || \
+ (STATE == TIM1_OCPreload_Disable))
+
+/* TIM1 Ouput Compare Fast State ---------------------------------------------*/
+#define TIM1_OCFast_Enable ((u16)0x0001)
+#define TIM1_OCFast_Disable ((u16)0x0000)
+
+#define IS_TIM1_OCFAST_STATE(STATE) ((STATE == TIM1_OCFast_Enable) || \
+ (STATE == TIM1_OCFast_Disable))
+
+/* TIM1 Trigger Output Source -----------------------------------------------*/
+#define TIM1_TRGOSource_Reset ((u16)0x0000)
+#define TIM1_TRGOSource_Enable ((u16)0x0010)
+#define TIM1_TRGOSource_Update ((u16)0x0020)
+#define TIM1_TRGOSource_OC1 ((u16)0x0030)
+#define TIM1_TRGOSource_OC1Ref ((u16)0x0040)
+#define TIM1_TRGOSource_OC2Ref ((u16)0x0050)
+#define TIM1_TRGOSource_OC3Ref ((u16)0x0060)
+#define TIM1_TRGOSource_OC4Ref ((u16)0x0070)
+
+#define IS_TIM1_TRGO_SOURCE(SOURCE) ((SOURCE == TIM1_TRGOSource_Reset) || \
+ (SOURCE == TIM1_TRGOSource_Enable) || \
+ (SOURCE == TIM1_TRGOSource_Update) || \
+ (SOURCE == TIM1_TRGOSource_OC1) || \
+ (SOURCE == TIM1_TRGOSource_OC1Ref) || \
+ (SOURCE == TIM1_TRGOSource_OC2Ref) || \
+ (SOURCE == TIM1_TRGOSource_OC3Ref) || \
+ (SOURCE == TIM1_TRGOSource_OC4Ref))
+
+/* TIM1 Slave Mode ----------------------------------------------------------*/
+#define TIM1_SlaveMode_Reset ((u16)0x0004)
+#define TIM1_SlaveMode_Gated ((u16)0x0005)
+#define TIM1_SlaveMode_Trigger ((u16)0x0006)
+#define TIM1_SlaveMode_External1 ((u16)0x0007)
+
+#define IS_TIM1_SLAVE_MODE(MODE) ((MODE == TIM1_SlaveMode_Reset) || \
+ (MODE == TIM1_SlaveMode_Gated) || \
+ (MODE == TIM1_SlaveMode_Trigger) || \
+ (MODE == TIM1_SlaveMode_External1))
+
+/* TIM1 TIx External Clock Source -------------------------------------------*/
+#define TIM1_TIxExternalCLK1Source_TI1 ((u16)0x0050)
+#define TIM1_TIxExternalCLK1Source_TI2 ((u16)0x0060)
+#define TIM1_TIxExternalCLK1Source_TI1ED ((u16)0x0040)
+
+#define IS_TIM1_TIXCLK_SOURCE(SOURCE) ((SOURCE == TIM1_TIxExternalCLK1Source_TI1) || \
+ (SOURCE == TIM1_TIxExternalCLK1Source_TI2) || \
+ (SOURCE == TIM1_TIxExternalCLK1Source_TI1ED))
+
+/* TIM1 Master Slave Mode ---------------------------------------------------*/
+#define TIM1_MasterSlaveMode_Enable ((u16)0x0001)
+#define TIM1_MasterSlaveMode_Disable ((u16)0x0000)
+
+#define IS_TIM1_MSM_STATE(STATE) ((STATE == TIM1_MasterSlaveMode_Enable) || \
+ (STATE == TIM1_MasterSlaveMode_Disable))
+
+/* TIM1 Flags ---------------------------------------------------------------*/
+#define TIM1_FLAG_Update ((u16)0x0001)
+#define TIM1_FLAG_CC1 ((u16)0x0002)
+#define TIM1_FLAG_CC2 ((u16)0x0004)
+#define TIM1_FLAG_CC3 ((u16)0x0008)
+#define TIM1_FLAG_CC4 ((u16)0x0010)
+#define TIM1_FLAG_COM ((u16)0x0020)
+#define TIM1_FLAG_Trigger ((u16)0x0040)
+#define TIM1_FLAG_Break ((u16)0x0080)
+#define TIM1_FLAG_CC1OF ((u16)0x0200)
+#define TIM1_FLAG_CC2OF ((u16)0x0400)
+#define TIM1_FLAG_CC3OF ((u16)0x0800)
+#define TIM1_FLAG_CC4OF ((u16)0x1000)
+
+#define IS_TIM1_GET_FLAG(FLAG) ((FLAG == TIM1_FLAG_Update) || \
+ (FLAG == TIM1_FLAG_CC1) || \
+ (FLAG == TIM1_FLAG_CC2) || \
+ (FLAG == TIM1_FLAG_CC3) || \
+ (FLAG == TIM1_FLAG_CC4) || \
+ (FLAG == TIM1_FLAG_COM) || \
+ (FLAG == TIM1_FLAG_Trigger) || \
+ (FLAG == TIM1_FLAG_Break) || \
+ (FLAG == TIM1_FLAG_CC1OF) || \
+ (FLAG == TIM1_FLAG_CC2OF) || \
+ (FLAG == TIM1_FLAG_CC3OF) || \
+ (FLAG == TIM1_FLAG_CC4OF))
+
+#define IS_TIM1_CLEAR_FLAG(FLAG) (((FLAG & (u16)0xE100) == 0x0000) && (FLAG != 0x0000))
+
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+void TIM1_DeInit(void);
+void TIM1_TimeBaseInit(TIM1_TimeBaseInitTypeDef* TIM1_TimeBaseInitStruct);
+void TIM1_OC1Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct);
+void TIM1_OC2Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct);
+void TIM1_OC3Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct);
+void TIM1_OC4Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct);
+void TIM1_BDTRConfig(TIM1_BDTRInitTypeDef *TIM1_BDTRInitStruct);
+void TIM1_ICInit(TIM1_ICInitTypeDef* TIM1_ICInitStruct);
+void TIM1_PWMIConfig(TIM1_ICInitTypeDef* TIM1_ICInitStruct);
+void TIM1_TimeBaseStructInit(TIM1_TimeBaseInitTypeDef* TIM1_TimeBaseInitStruct);
+void TIM1_OCStructInit(TIM1_OCInitTypeDef* TIM1_OCInitStruct);
+void TIM1_ICStructInit(TIM1_ICInitTypeDef* TIM1_ICInitStruct);
+void TIM1_BDTRStructInit(TIM1_BDTRInitTypeDef* TIM1_BDTRInitStruct);
+void TIM1_Cmd(FunctionalState NewState);
+void TIM1_CtrlPWMOutputs(FunctionalState Newstate);
+void TIM1_ITConfig(u16 TIM1_IT, FunctionalState NewState);
+void TIM1_DMAConfig(u16 TIM1_DMABase, u16 TIM1_DMABurstLength);
+void TIM1_DMACmd(u16 TIM1_DMASource, FunctionalState Newstate);
+void TIM1_InternalClockConfig(void);
+void TIM1_ETRClockMode1Config(u16 TIM1_ExtTRGPrescaler, u16 TIM1_ExtTRGPolarity,
+ u16 ExtTRGFilter);
+void TIM1_ETRClockMode2Config(u16 TIM1_ExtTRGPrescaler, u16 TIM1_ExtTRGPolarity,
+ u16 ExtTRGFilter);
+void TIM1_ITRxExternalClockConfig(u16 TIM1_InputTriggerSource);
+void TIM1_TIxExternalClockConfig(u16 TIM1_TIxExternalCLKSource, u16 TIM1_ICPolarity,
+ u8 ICFilter);
+void TIM1_SelectInputTrigger(u16 TIM1_InputTriggerSource);
+void TIM1_UpdateDisableConfig(FunctionalState Newstate);
+void TIM1_UpdateRequestConfig(u8 TIM1_UpdateSource);
+void TIM1_SelectHallSensor(FunctionalState Newstate);
+void TIM1_SelectOnePulseMode(u16 TIM1_OPMode);
+void TIM1_SelectOutputTrigger(u16 TIM1_TRGOSource);
+void TIM1_SelectSlaveMode(u16 TIM1_SlaveMode);
+void TIM1_SelectMasterSlaveMode(u16 TIM1_MasterSlaveMode);
+void TIM1_EncoderInterfaceConfig(u16 TIM1_EncoderMode, u16 TIM1_IC1Polarity,
+ u16 TIM1_IC2Polarity);
+void TIM1_PrescalerConfig(u16 Prescaler, u16 TIM1_PSCReloadMode);
+void TIM1_CounterModeConfig(u16 TIM1_CounterMode);
+void TIM1_ForcedOC1Config(u16 TIM1_ForcedAction);
+void TIM1_ForcedOC2Config(u16 TIM1_ForcedAction);
+void TIM1_ForcedOC3Config(u16 TIM1_ForcedAction);
+void TIM1_ForcedOC4Config(u16 TIM1_ForcedAction);
+void TIM1_ARRPreloadConfig(FunctionalState Newstate);
+void TIM1_SelectCOM(FunctionalState Newstate);
+void TIM1_SelectCCDMA(FunctionalState Newstate);
+void TIM1_CCPreloadControl(FunctionalState Newstate);
+void TIM1_OC1PreloadConfig(u16 TIM1_OCPreload);
+void TIM1_OC2PreloadConfig(u16 TIM1_OCPreload);
+void TIM1_OC3PreloadConfig(u16 TIM1_OCPreload);
+void TIM1_OC4PreloadConfig(u16 TIM1_OCPreload);
+void TIM1_OC1FastConfig(u16 TIM1_OCFast);
+void TIM1_OC2FastConfig(u16 TIM1_OCFast);
+void TIM1_OC3FastConfig(u16 TIM1_OCFast);
+void TIM1_OC4FastConfig(u16 TIM1_OCFast);
+void TIM1_GenerateEvent(u16 TIM1_EventSource);
+void TIM1_OC1PolarityConfig(u16 TIM1_OCPolarity);
+void TIM1_OC1NPolarityConfig(u16 TIM1_OCPolarity);
+void TIM1_OC2PolarityConfig(u16 TIM1_OCPolarity);
+void TIM1_OC2NPolarityConfig(u16 TIM1_OCPolarity);
+void TIM1_OC3PolarityConfig(u16 TIM1_OCPolarity);
+void TIM1_OC3NPolarityConfig(u16 TIM1_OCPolarity);
+void TIM1_OC4PolarityConfig(u16 TIM1_OCPolarity);
+void TIM1_CCxCmd(u16 TIM1_Channel, FunctionalState Newstate);
+void TIM1_CCxNCmd(u16 TIM1_Channel, FunctionalState Newstate);
+void TIM1_SelectOCxM(u16 TIM1_Channel, u16 TIM1_OCMode);
+void TIM1_SetAutoreload(u16 Autoreload);
+void TIM1_SetCompare1(u16 Compare1);
+void TIM1_SetCompare2(u16 Compare2);
+void TIM1_SetCompare3(u16 Compare3);
+void TIM1_SetCompare4(u16 Compare4);
+void TIM1_SetIC1Prescaler(u16 TIM1_IC1Prescaler);
+void TIM1_SetIC2Prescaler(u16 TIM1_IC2Prescaler);
+void TIM1_SetIC3Prescaler(u16 TIM1_IC3Prescaler);
+void TIM1_SetIC4Prescaler(u16 TIM1_IC4Prescaler);
+void TIM1_SetClockDivision(u16 TIM1_CKD);
+u16 TIM1_GetCapture1(void);
+u16 TIM1_GetCapture2(void);
+u16 TIM1_GetCapture3(void);
+u16 TIM1_GetCapture4(void);
+u16 TIM1_GetCounter(void);
+u16 TIM1_GetPrescaler(void);
+FlagStatus TIM1_GetFlagStatus(u16 TIM1_FLAG);
+void TIM1_ClearFlag(u16 TIM1_Flag);
+ITStatus TIM1_GetITStatus(u16 TIM1_IT);
+void TIM1_ClearITPendingBit(u16 TIM1_IT);
+
+#endif /*__STM32F10x_TIM1_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_type.h b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_type.h
new file mode 100644
index 0000000..d6e83a9
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_type.h
@@ -0,0 +1,76 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_type.h
+* Author : MCD Application Team
+* Date First Issued : 09/29/2006
+* Description : This file contains all the common data types used for the
+* STM32F10x firmware library.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_TYPE_H
+#define __STM32F10x_TYPE_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+typedef signed long s32;
+typedef signed short s16;
+typedef signed char s8;
+
+typedef volatile signed long vs32;
+typedef volatile signed short vs16;
+typedef volatile signed char vs8;
+
+typedef unsigned long u32;
+typedef unsigned short u16;
+typedef unsigned char u8;
+
+typedef unsigned long const uc32; /* Read Only */
+typedef unsigned short const uc16; /* Read Only */
+typedef unsigned char const uc8; /* Read Only */
+
+typedef volatile unsigned long vu32;
+typedef volatile unsigned short vu16;
+typedef volatile unsigned char vu8;
+
+typedef volatile unsigned long const vuc32; /* Read Only */
+typedef volatile unsigned short const vuc16; /* Read Only */
+typedef volatile unsigned char const vuc8; /* Read Only */
+
+typedef enum {FALSE = 0, TRUE = !FALSE} bool;
+
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
+
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) ((STATE == DISABLE) || (STATE == ENABLE))
+
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
+
+#define U8_MAX ((u8)255)
+#define S8_MAX ((s8)127)
+#define S8_MIN ((s8)-128)
+#define U16_MAX ((u16)65535u)
+#define S16_MAX ((s16)32767)
+#define S16_MIN ((s16)-32768)
+#define U32_MAX ((u32)4294967295uL)
+#define S32_MAX ((s32)2147483647)
+#define S32_MIN ((s32)2147483648uL)
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+#endif /* __STM32F10x_TYPE_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_usart.h b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_usart.h
new file mode 100644
index 0000000..e8c44aa
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_usart.h
@@ -0,0 +1,219 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_usart.h
+* Author : MCD Application Team
+* Date First Issued : 09/29/2006
+* Description : This file contains all the functions prototypes for the
+* USART firmware library.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_USART_H
+#define __STM32F10x_USART_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* UART Init Structure definition */
+typedef struct
+{
+ u32 USART_BaudRate;
+ u16 USART_WordLength;
+ u16 USART_StopBits;
+ u16 USART_Parity;
+ u16 USART_HardwareFlowControl;
+ u16 USART_Mode;
+ u16 USART_Clock;
+ u16 USART_CPOL;
+ u16 USART_CPHA;
+ u16 USART_LastBit;
+} USART_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/* USART Word Length ---------------------------------------------------------*/
+#define USART_WordLength_8b ((u16)0x0000)
+#define USART_WordLength_9b ((u16)0x1000)
+
+#define IS_USART_WORD_LENGTH(LENGTH) ((LENGTH == USART_WordLength_8b) || \
+ (LENGTH == USART_WordLength_9b))
+
+/* USART Stop Bits -----------------------------------------------------------*/
+#define USART_StopBits_1 ((u16)0x0000)
+#define USART_StopBits_0_5 ((u16)0x1000)
+#define USART_StopBits_2 ((u16)0x2000)
+#define USART_StopBits_1_5 ((u16)0x3000)
+
+#define IS_USART_STOPBITS(STOPBITS) ((STOPBITS == USART_StopBits_1) || \
+ (STOPBITS == USART_StopBits_0_5) || \
+ (STOPBITS == USART_StopBits_2) || \
+ (STOPBITS == USART_StopBits_1_5))
+/* USART Parity --------------------------------------------------------------*/
+#define USART_Parity_No ((u16)0x0000)
+#define USART_Parity_Even ((u16)0x0400)
+#define USART_Parity_Odd ((u16)0x0600)
+
+#define IS_USART_PARITY(PARITY) ((PARITY == USART_Parity_No) || \
+ (PARITY == USART_Parity_Even) || \
+ (PARITY == USART_Parity_Odd))
+
+/* USART Hardware Flow Control -----------------------------------------------*/
+#define USART_HardwareFlowControl_None ((u16)0x0000)
+#define USART_HardwareFlowControl_RTS ((u16)0x0100)
+#define USART_HardwareFlowControl_CTS ((u16)0x0200)
+#define USART_HardwareFlowControl_RTS_CTS ((u16)0x0300)
+
+#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
+ ((CONTROL == USART_HardwareFlowControl_None) || \
+ (CONTROL == USART_HardwareFlowControl_RTS) || \
+ (CONTROL == USART_HardwareFlowControl_CTS) || \
+ (CONTROL == USART_HardwareFlowControl_RTS_CTS))
+
+/* USART Mode ----------------------------------------------------------------*/
+#define USART_Mode_Rx ((u16)0x0004)
+#define USART_Mode_Tx ((u16)0x0008)
+
+#define IS_USART_MODE(MODE) (((MODE & (u16)0xFFF3) == 0x00) && (MODE != (u16)0x00))
+
+/* USART Clock ---------------------------------------------------------------*/
+#define USART_Clock_Disable ((u16)0x0000)
+#define USART_Clock_Enable ((u16)0x0800)
+
+#define IS_USART_CLOCK(CLOCK) ((CLOCK == USART_Clock_Disable) || \
+ (CLOCK == USART_Clock_Enable))
+
+/* USART Clock Polarity ------------------------------------------------------*/
+#define USART_CPOL_Low ((u16)0x0000)
+#define USART_CPOL_High ((u16)0x0400)
+
+#define IS_USART_CPOL(CPOL) ((CPOL == USART_CPOL_Low) || (CPOL == USART_CPOL_High))
+
+/* USART Clock Phase ---------------------------------------------------------*/
+#define USART_CPHA_1Edge ((u16)0x0000)
+#define USART_CPHA_2Edge ((u16)0x0200)
+#define IS_USART_CPHA(CPHA) ((CPHA == USART_CPHA_1Edge) || (CPHA == USART_CPHA_2Edge))
+
+/* USART Last Bit ------------------------------------------------------------*/
+#define USART_LastBit_Disable ((u16)0x0000)
+#define USART_LastBit_Enable ((u16)0x0100)
+
+#define IS_USART_LASTBIT(LASTBIT) ((LASTBIT == USART_LastBit_Disable) || \
+ (LASTBIT == USART_LastBit_Enable))
+
+/* USART Interrupt definition ------------------------------------------------*/
+#define USART_IT_PE ((u16)0x0028)
+#define USART_IT_TXE ((u16)0x0727)
+#define USART_IT_TC ((u16)0x0626)
+#define USART_IT_RXNE ((u16)0x0525)
+#define USART_IT_IDLE ((u16)0x0424)
+#define USART_IT_LBD ((u16)0x0846)
+#define USART_IT_CTS ((u16)0x096A)
+#define USART_IT_ERR ((u16)0x0060)
+#define USART_IT_ORE ((u16)0x0360)
+#define USART_IT_NE ((u16)0x0260)
+#define USART_IT_FE ((u16)0x0160)
+
+#define IS_USART_CONFIG_IT(IT) ((IT == USART_IT_PE) || (IT == USART_IT_TXE) || \
+ (IT == USART_IT_TC) || (IT == USART_IT_RXNE) || \
+ (IT == USART_IT_IDLE) || (IT == USART_IT_LBD) || \
+ (IT == USART_IT_CTS) || (IT == USART_IT_ERR))
+
+#define IS_USART_IT(IT) ((IT == USART_IT_PE) || (IT == USART_IT_TXE) || \
+ (IT == USART_IT_TC) || (IT == USART_IT_RXNE) || \
+ (IT == USART_IT_IDLE) || (IT == USART_IT_LBD) || \
+ (IT == USART_IT_CTS) || (IT == USART_IT_ORE) || \
+ (IT == USART_IT_NE) || (IT == USART_IT_FE))
+
+/* USART DMA Requests --------------------------------------------------------*/
+#define USART_DMAReq_Tx ((u16)0x0080)
+#define USART_DMAReq_Rx ((u16)0x0040)
+
+#define IS_USART_DMAREQ(DMAREQ) (((DMAREQ & (u16)0xFF3F) == 0x00) && (DMAREQ != (u16)0x00))
+
+/* USART WakeUp methods ------------------------------------------------------*/
+#define USART_WakeUp_IdleLine ((u16)0x0000)
+#define USART_WakeUp_AddressMark ((u16)0x0800)
+
+#define IS_USART_WAKEUP(WAKEUP) ((WAKEUP == USART_WakeUp_IdleLine) || \
+ (WAKEUP == USART_WakeUp_AddressMark))
+
+/* USART LIN Break Detection Length ------------------------------------------*/
+#define USART_LINBreakDetectLength_10b ((u16)0x0000)
+#define USART_LINBreakDetectLength_11b ((u16)0x0020)
+
+#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
+ ((LENGTH == USART_LINBreakDetectLength_10b) || \
+ (LENGTH == USART_LINBreakDetectLength_11b))
+
+/* USART IrDA Low Power ------------------------------------------------------*/
+#define USART_IrDAMode_LowPower ((u16)0x0004)
+#define USART_IrDAMode_Normal ((u16)0x0000)
+
+#define IS_USART_IRDA_MODE(MODE) ((MODE == USART_IrDAMode_LowPower) || \
+ (MODE == USART_IrDAMode_Normal))
+
+/* USART Flags ---------------------------------------------------------------*/
+#define USART_FLAG_CTS ((u16)0x0200)
+#define USART_FLAG_LBD ((u16)0x0100)
+#define USART_FLAG_TXE ((u16)0x0080)
+#define USART_FLAG_TC ((u16)0x0040)
+#define USART_FLAG_RXNE ((u16)0x0020)
+#define USART_FLAG_IDLE ((u16)0x0010)
+#define USART_FLAG_ORE ((u16)0x0008)
+#define USART_FLAG_NE ((u16)0x0004)
+#define USART_FLAG_FE ((u16)0x0002)
+#define USART_FLAG_PE ((u16)0x0001)
+
+#define IS_USART_FLAG(FLAG) ((FLAG == USART_FLAG_PE) || (FLAG == USART_FLAG_TXE) || \
+ (FLAG == USART_FLAG_TC) || (FLAG == USART_FLAG_RXNE) || \
+ (FLAG == USART_FLAG_IDLE) || (FLAG == USART_FLAG_LBD) || \
+ (FLAG == USART_FLAG_CTS) || (FLAG == USART_FLAG_ORE) || \
+ (FLAG == USART_FLAG_NE) || (FLAG == USART_FLAG_FE))
+
+#define IS_USART_CLEAR_FLAG(FLAG) (((FLAG & (u16)0xFC00) == 0x00) && (FLAG != (u16)0x00))
+
+#define IS_USART_ADDRESS(ADDRESS) (ADDRESS <= 0xF)
+#define IS_USART_DATA(DATA) (DATA <= 0x1FF)
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void USART_DeInit(USART_TypeDef* USARTx);
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_ITConfig(USART_TypeDef* USARTx, u16 USART_IT, FunctionalState NewState);
+void USART_DMACmd(USART_TypeDef* USARTx, u16 USART_DMAReq, FunctionalState NewState);
+void USART_SetAddress(USART_TypeDef* USARTx, u8 USART_Address);
+void USART_WakeUpConfig(USART_TypeDef* USARTx, u16 USART_WakeUp);
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, u16 USART_LINBreakDetectLength);
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SendData(USART_TypeDef* USARTx, u16 Data);
+u16 USART_ReceiveData(USART_TypeDef* USARTx);
+void USART_SendBreak(USART_TypeDef* USARTx);
+void USART_SetGuardTime(USART_TypeDef* USARTx, u8 USART_GuardTime);
+void USART_SetPrescaler(USART_TypeDef* USARTx, u8 USART_Prescaler);
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_IrDAConfig(USART_TypeDef* USARTx, u16 USART_IrDAMode);
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, u16 USART_FLAG);
+void USART_ClearFlag(USART_TypeDef* USARTx, u16 USART_FLAG);
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, u16 USART_IT);
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, u16 USART_IT);
+
+#endif /* __STM32F10x_USART_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_wwdg.h b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_wwdg.h
new file mode 100644
index 0000000..2230b58
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/inc/stm32f10x_wwdg.h
@@ -0,0 +1,58 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_wwdg.h
+* Author : MCD Application Team
+* Date First Issued : 09/29/2006
+* Description : This file contains all the functions prototypes for the
+* WWDG firmware library.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_WWDG_H
+#define __STM32F10x_WWDG_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* WWDG Prescaler */
+#define WWDG_Prescaler_1 ((u32)0x00000000)
+#define WWDG_Prescaler_2 ((u32)0x00000080)
+#define WWDG_Prescaler_4 ((u32)0x00000100)
+#define WWDG_Prescaler_8 ((u32)0x00000180)
+
+#define IS_WWDG_PRESCALER(PRESCALER) ((PRESCALER == WWDG_Prescaler_1) || \
+ (PRESCALER == WWDG_Prescaler_2) || \
+ (PRESCALER == WWDG_Prescaler_4) || \
+ (PRESCALER == WWDG_Prescaler_8))
+
+#define IS_WWDG_WINDOW_VALUE(VALUE) (VALUE <= 0x7F)
+
+#define IS_WWDG_COUNTER(COUNTER) ((COUNTER >= 0x40) && (COUNTER <= 0x7F))
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void WWDG_DeInit(void);
+void WWDG_SetPrescaler(u32 WWDG_Prescaler);
+void WWDG_SetWindowValue(u8 WindowValue);
+void WWDG_EnableIT(void);
+void WWDG_SetCounter(u8 Counter);
+void WWDG_Enable(u8 Counter);
+FlagStatus WWDG_GetFlagStatus(void);
+void WWDG_ClearFlag(void);
+
+#endif /* __STM32F10x_WWDG_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/cortexm3_macro.s b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/cortexm3_macro.s
new file mode 100644
index 0000000..cb20961
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/cortexm3_macro.s
@@ -0,0 +1,278 @@
+;******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+;* File Name : cortexm3_macro.s
+;* Author : MCD Application Team
+;* Date First Issued : 02/19/2007
+;* Description : Instruction wrappers for special Cortex-M3 instructions.
+;*******************************************************************************
+; History:
+; 04/02/2007: V0.2
+; 02/19/2007: V0.1
+;*******************************************************************************
+; THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+; CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+;*******************************************************************************
+
+ SECTION .text:CODE(2)
+
+ ; Exported functions
+ EXPORT __WFI
+ EXPORT __WFE
+ EXPORT __SEV
+ EXPORT __ISB
+ EXPORT __DSB
+ EXPORT __DMB
+ EXPORT __SVC
+ EXPORT __MRS_CONTROL
+ EXPORT __MSR_CONTROL
+ EXPORT __MRS_PSP
+ EXPORT __MSR_PSP
+ EXPORT __MRS_MSP
+ EXPORT __MSR_MSP
+ EXPORT __SETPRIMASK
+ EXPORT __RESETPRIMASK
+ EXPORT __SETFAULTMASK
+ EXPORT __RESETFAULTMASK
+ EXPORT __BASEPRICONFIG
+ EXPORT __GetBASEPRI
+ EXPORT __REV_HalfWord
+ EXPORT __REV_Word
+
+;*******************************************************************************
+; Function Name : __WFI
+; Description : Assembler function for the WFI instruction.
+; Input : None
+; Return : None
+;*******************************************************************************
+__WFI
+
+ WFI
+ BX r14
+
+;*******************************************************************************
+; Function Name : __WFE
+; Description : Assembler function for the WFE instruction.
+; Input : None
+; Return : None
+;*******************************************************************************
+__WFE
+
+ WFE
+ BX r14
+
+;*******************************************************************************
+; Function Name : __SEV
+; Description : Assembler function for the SEV instruction.
+; Input : None
+; Return : None
+;*******************************************************************************
+__SEV
+
+ SEV
+ BX r14
+
+;*******************************************************************************
+; Function Name : __ISB
+; Description : Assembler function for the ISB instruction.
+; Input : None
+; Return : None
+;*******************************************************************************
+__ISB
+
+ ISB
+ BX r14
+
+;*******************************************************************************
+; Function Name : __DSB
+; Description : Assembler function for the DSB instruction.
+; Input : None
+; Return : None
+;*******************************************************************************
+__DSB
+
+ DSB
+ BX r14
+
+;*******************************************************************************
+; Function Name : __DMB
+; Description : Assembler function for the DMB instruction.
+; Input : None
+; Return : None
+;*******************************************************************************
+__DMB
+
+ DMB
+ BX r14
+
+;*******************************************************************************
+; Function Name : __SVC
+; Description : Assembler function for the SVC instruction.
+; Input : None
+; Return : None
+;*******************************************************************************
+__SVC
+
+ SVC 0x01
+ BX r14
+
+;*******************************************************************************
+; Function Name : __MRS_CONTROL
+; Description : Assembler function for the MRS instruction.
+; Input : None
+; Return : - r0 : Cortex-M3 CONTROL register value.
+;*******************************************************************************
+__MRS_CONTROL
+
+ MRS r0, CONTROL
+ BX r14
+
+;*******************************************************************************
+; Function Name : __MSR_CONTROL
+; Description : Assembler function for the MSR instruction.
+; Input : - r0 : Cortex-M3 CONTROL register new value.
+; Return : None
+;*******************************************************************************
+__MSR_CONTROL
+
+ MSR CONTROL, r0
+ ISB
+ BX r14
+
+;*******************************************************************************
+; Function Name : __MRS_PSP
+; Description : Assembler function for the MRS instruction.
+; Input : None
+; Return : - r0 : Process Stack value.
+;*******************************************************************************
+__MRS_PSP
+
+ MRS r0, PSP
+ BX r14
+
+;*******************************************************************************
+; Function Name : __MSR_PSP
+; Description : Assembler function for the MSR instruction.
+; Input : - r0 : Process Stack new value.
+; Return : None
+;*******************************************************************************
+__MSR_PSP
+
+ MSR PSP, r0 ; set Process Stack value
+ BX r14
+
+;*******************************************************************************
+; Function Name : __MRS_MSP
+; Description : Assembler function for the MRS instruction.
+; Input : None
+; Return : - r0 : Main Stack value.
+;*******************************************************************************
+__MRS_MSP
+
+ MRS r0, MSP
+ BX r14
+
+;*******************************************************************************
+; Function Name : __MSR_MSP
+; Description : Assembler function for the MSR instruction.
+; Input : - r0 : Main Stack new value.
+; Return : None
+;*******************************************************************************
+__MSR_MSP
+
+ MSR MSP, r0 ; set Main Stack value
+ BX r14
+
+;*******************************************************************************
+; Function Name : __SETPRIMASK
+; Description : Assembler function to set the PRIMASK.
+; Input : None
+; Return : None
+;*******************************************************************************
+__SETPRIMASK
+
+ CPSID i
+ BX r14
+
+;*******************************************************************************
+; Function Name : __RESETPRIMASK
+; Description : Assembler function to reset the PRIMASK.
+; Input : None
+; Return : None
+;*******************************************************************************
+__RESETPRIMASK
+
+ CPSIE i
+ BX r14
+
+;*******************************************************************************
+; Function Name : __SETFAULTMASK
+; Description : Assembler function to set the FAULTMASK.
+; Input : None
+; Return : None
+;*******************************************************************************
+__SETFAULTMASK
+
+ CPSID f
+ BX r14
+
+;*******************************************************************************
+; Function Name : __RESETFAULTMASK
+; Description : Assembler function to reset the FAULTMASK.
+; Input : None
+; Return : None
+;*******************************************************************************
+__RESETFAULTMASK
+
+ CPSIE f
+ BX r14
+
+;*******************************************************************************
+; Function Name : __BASEPRICONFIG
+; Description : Assembler function to set the Base Priority.
+; Input : - r0 : Base Priority new value
+; Return : None
+;*******************************************************************************
+__BASEPRICONFIG
+
+ MSR BASEPRI, r0
+ BX r14
+
+;*******************************************************************************
+; Function Name : __GetBASEPRI
+; Description : Assembler function to get the Base Priority value.
+; Input : None
+; Return : - r0 : Base Priority value
+;*******************************************************************************
+__GetBASEPRI
+
+ MRS r0, BASEPRI_MAX
+ BX r14
+
+;*******************************************************************************
+; Function Name : __REV_HalfWord
+; Description : Reverses the byte order in HalfWord(16-bit) input variable.
+; Input : - r0 : specifies the input variable
+; Return : - r0 : holds tve variable value after byte reversing.
+;*******************************************************************************
+__REV_HalfWord
+
+ REV16 r0, r0
+ BX r14
+
+;*******************************************************************************
+; Function Name : __REV_Word
+; Description : Reverses the byte order in Word(32-bit) input variable.
+; Input : - r0 : specifies the input variable
+; Return : - r0 : holds tve variable value after byte reversing.
+;*******************************************************************************
+__REV_Word
+
+ REV r0, r0
+ BX r14
+
+ END
+
+;******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE*****
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/lcd.c b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/lcd.c
new file mode 100644
index 0000000..48d8625
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/lcd.c
@@ -0,0 +1,1305 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : lcd.c
+* Author : MCD Application Team
+* Date First Issued : mm/dd/yyyy
+* Description : This file includes the LCD driver for AM-240320LTNQW00H
+* liquid Crystal Display Module of STM32F10x-EVAL.
+********************************************************************************
+* History:
+* mm/dd/yyyy
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_type.h"
+#include "lcd.h"
+#include "spi_flash.h"
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+ /* ASCII Table: each character is 16 column (16dots large)
+ and 24 raw (24 dots high) */
+ const uc16 ASCII_Table[] =
+ {
+ /* Space ' ' */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* '!' */
+ 0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
+ 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0000, 0x0000,
+ 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* '"' */
+ 0x0000, 0x0000, 0x00CC, 0x00CC, 0x00CC, 0x00CC, 0x00CC, 0x00CC,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* '#' */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0C60, 0x0C60,
+ 0x0C60, 0x0630, 0x0630, 0x1FFE, 0x1FFE, 0x0630, 0x0738, 0x0318,
+ 0x1FFE, 0x1FFE, 0x0318, 0x0318, 0x018C, 0x018C, 0x018C, 0x0000,
+ /* '$' */
+ 0x0000, 0x0080, 0x03E0, 0x0FF8, 0x0E9C, 0x1C8C, 0x188C, 0x008C,
+ 0x0098, 0x01F8, 0x07E0, 0x0E80, 0x1C80, 0x188C, 0x188C, 0x189C,
+ 0x0CB8, 0x0FF0, 0x03E0, 0x0080, 0x0080, 0x0000, 0x0000, 0x0000,
+ /* '%' */
+ 0x0000, 0x0000, 0x0000, 0x180E, 0x0C1B, 0x0C11, 0x0611, 0x0611,
+ 0x0311, 0x0311, 0x019B, 0x018E, 0x38C0, 0x6CC0, 0x4460, 0x4460,
+ 0x4430, 0x4430, 0x4418, 0x6C18, 0x380C, 0x0000, 0x0000, 0x0000,
+ /* '&' */
+ 0x0000, 0x01E0, 0x03F0, 0x0738, 0x0618, 0x0618, 0x0330, 0x01F0,
+ 0x00F0, 0x00F8, 0x319C, 0x330E, 0x1E06, 0x1C06, 0x1C06, 0x3F06,
+ 0x73FC, 0x21F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* ''' */
+ 0x0000, 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* '(' */
+ 0x0000, 0x0200, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x0060, 0x0060,
+ 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030,
+ 0x0060, 0x0060, 0x00C0, 0x00C0, 0x0180, 0x0300, 0x0200, 0x0000,
+ /* ')' */
+ 0x0000, 0x0020, 0x0060, 0x00C0, 0x0180, 0x0180, 0x0300, 0x0300,
+ 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600,
+ 0x0300, 0x0300, 0x0180, 0x0180, 0x00C0, 0x0060, 0x0020, 0x0000,
+ /* '*' */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0,
+ 0x06D8, 0x07F8, 0x01E0, 0x0330, 0x0738, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* '+' */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180,
+ 0x0180, 0x0180, 0x0180, 0x3FFC, 0x3FFC, 0x0180, 0x0180, 0x0180,
+ 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* ',' */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0180, 0x0180, 0x0100, 0x0100, 0x0080, 0x0000, 0x0000,
+ /* '-' */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x07E0, 0x07E0, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* '.' */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* '/' */
+ 0x0000, 0x0C00, 0x0C00, 0x0600, 0x0600, 0x0600, 0x0300, 0x0300,
+ 0x0300, 0x0380, 0x0180, 0x0180, 0x0180, 0x00C0, 0x00C0, 0x00C0,
+ 0x0060, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* '0' */
+ 0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C18, 0x180C, 0x180C, 0x180C,
+ 0x180C, 0x180C, 0x180C, 0x180C, 0x180C, 0x180C, 0x0C18, 0x0E38,
+ 0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* '1' */
+ 0x0000, 0x0100, 0x0180, 0x01C0, 0x01F0, 0x0198, 0x0188, 0x0180,
+ 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
+ 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* '2' */
+ 0x0000, 0x03E0, 0x0FF8, 0x0C18, 0x180C, 0x180C, 0x1800, 0x1800,
+ 0x0C00, 0x0600, 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018,
+ 0x1FFC, 0x1FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* '3' */
+ 0x0000, 0x01E0, 0x07F8, 0x0E18, 0x0C0C, 0x0C0C, 0x0C00, 0x0600,
+ 0x03C0, 0x07C0, 0x0C00, 0x1800, 0x1800, 0x180C, 0x180C, 0x0C18,
+ 0x07F8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* '4' */
+ 0x0000, 0x0C00, 0x0E00, 0x0F00, 0x0F00, 0x0D80, 0x0CC0, 0x0C60,
+ 0x0C60, 0x0C30, 0x0C18, 0x0C0C, 0x3FFC, 0x3FFC, 0x0C00, 0x0C00,
+ 0x0C00, 0x0C00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* '5' */
+ 0x0000, 0x0FF8, 0x0FF8, 0x0018, 0x0018, 0x000C, 0x03EC, 0x07FC,
+ 0x0E1C, 0x1C00, 0x1800, 0x1800, 0x1800, 0x180C, 0x0C1C, 0x0E18,
+ 0x07F8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* '6' */
+ 0x0000, 0x07C0, 0x0FF0, 0x1C38, 0x1818, 0x0018, 0x000C, 0x03CC,
+ 0x0FEC, 0x0E3C, 0x1C1C, 0x180C, 0x180C, 0x180C, 0x1C18, 0x0E38,
+ 0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* '7' */
+ 0x0000, 0x1FFC, 0x1FFC, 0x0C00, 0x0600, 0x0600, 0x0300, 0x0380,
+ 0x0180, 0x01C0, 0x00C0, 0x00E0, 0x0060, 0x0060, 0x0070, 0x0030,
+ 0x0030, 0x0030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* '8' */
+ 0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C18, 0x0C18, 0x0C18, 0x0638,
+ 0x07F0, 0x07F0, 0x0C18, 0x180C, 0x180C, 0x180C, 0x180C, 0x0C38,
+ 0x0FF8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* '9' */
+ 0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C1C, 0x180C, 0x180C, 0x180C,
+ 0x1C1C, 0x1E38, 0x1BF8, 0x19E0, 0x1800, 0x0C00, 0x0C00, 0x0E1C,
+ 0x07F8, 0x01F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* ':' */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* ';' */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0180, 0x0180, 0x0100, 0x0100, 0x0080, 0x0000, 0x0000, 0x0000,
+ /* '<' */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x1000, 0x1C00, 0x0F80, 0x03E0, 0x00F8, 0x0018, 0x00F8, 0x03E0,
+ 0x0F80, 0x1C00, 0x1000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* '=' */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x1FF8, 0x0000, 0x0000, 0x0000, 0x1FF8, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* '>' */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0008, 0x0038, 0x01F0, 0x07C0, 0x1F00, 0x1800, 0x1F00, 0x07C0,
+ 0x01F0, 0x0038, 0x0008, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* '?' */
+ 0x0000, 0x03E0, 0x0FF8, 0x0C18, 0x180C, 0x180C, 0x1800, 0x0C00,
+ 0x0600, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x00C0, 0x0000, 0x0000,
+ 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* '@' */
+ 0x0000, 0x0000, 0x07E0, 0x1818, 0x2004, 0x29C2, 0x4A22, 0x4411,
+ 0x4409, 0x4409, 0x4409, 0x2209, 0x1311, 0x0CE2, 0x4002, 0x2004,
+ 0x1818, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'A' */
+ 0x0000, 0x0380, 0x0380, 0x06C0, 0x06C0, 0x06C0, 0x0C60, 0x0C60,
+ 0x1830, 0x1830, 0x1830, 0x3FF8, 0x3FF8, 0x701C, 0x600C, 0x600C,
+ 0xC006, 0xC006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'B' */
+ 0x0000, 0x03FC, 0x0FFC, 0x0C0C, 0x180C, 0x180C, 0x180C, 0x0C0C,
+ 0x07FC, 0x0FFC, 0x180C, 0x300C, 0x300C, 0x300C, 0x300C, 0x180C,
+ 0x1FFC, 0x07FC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'C' */
+ 0x0000, 0x07C0, 0x1FF0, 0x3838, 0x301C, 0x700C, 0x6006, 0x0006,
+ 0x0006, 0x0006, 0x0006, 0x0006, 0x0006, 0x6006, 0x700C, 0x301C,
+ 0x1FF0, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'D' */
+ 0x0000, 0x03FE, 0x0FFE, 0x0E06, 0x1806, 0x1806, 0x3006, 0x3006,
+ 0x3006, 0x3006, 0x3006, 0x3006, 0x3006, 0x1806, 0x1806, 0x0E06,
+ 0x0FFE, 0x03FE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'E' */
+ 0x0000, 0x3FFC, 0x3FFC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,
+ 0x1FFC, 0x1FFC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,
+ 0x3FFC, 0x3FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'F' */
+ 0x0000, 0x3FF8, 0x3FF8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,
+ 0x1FF8, 0x1FF8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,
+ 0x0018, 0x0018, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'G' */
+ 0x0000, 0x0FE0, 0x3FF8, 0x783C, 0x600E, 0xE006, 0xC007, 0x0003,
+ 0x0003, 0xFE03, 0xFE03, 0xC003, 0xC007, 0xC006, 0xC00E, 0xF03C,
+ 0x3FF8, 0x0FE0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'H' */
+ 0x0000, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C,
+ 0x3FFC, 0x3FFC, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C,
+ 0x300C, 0x300C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'I' */
+ 0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
+ 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
+ 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'J' */
+ 0x0000, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600,
+ 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0618, 0x0618, 0x0738,
+ 0x03F0, 0x01E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'K' */
+ 0x0000, 0x3006, 0x1806, 0x0C06, 0x0606, 0x0306, 0x0186, 0x00C6,
+ 0x0066, 0x0076, 0x00DE, 0x018E, 0x0306, 0x0606, 0x0C06, 0x1806,
+ 0x3006, 0x6006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'L' */
+ 0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,
+ 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,
+ 0x1FF8, 0x1FF8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'M' */
+ 0x0000, 0xE00E, 0xF01E, 0xF01E, 0xF01E, 0xD836, 0xD836, 0xD836,
+ 0xD836, 0xCC66, 0xCC66, 0xCC66, 0xC6C6, 0xC6C6, 0xC6C6, 0xC6C6,
+ 0xC386, 0xC386, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'N' */
+ 0x0000, 0x300C, 0x301C, 0x303C, 0x303C, 0x306C, 0x306C, 0x30CC,
+ 0x30CC, 0x318C, 0x330C, 0x330C, 0x360C, 0x360C, 0x3C0C, 0x3C0C,
+ 0x380C, 0x300C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'O' */
+ 0x0000, 0x07E0, 0x1FF8, 0x381C, 0x700E, 0x6006, 0xC003, 0xC003,
+ 0xC003, 0xC003, 0xC003, 0xC003, 0xC003, 0x6006, 0x700E, 0x381C,
+ 0x1FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'P' */
+ 0x0000, 0x0FFC, 0x1FFC, 0x380C, 0x300C, 0x300C, 0x300C, 0x300C,
+ 0x180C, 0x1FFC, 0x07FC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,
+ 0x000C, 0x000C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'Q' */
+ 0x0000, 0x07E0, 0x1FF8, 0x381C, 0x700E, 0x6006, 0xE003, 0xC003,
+ 0xC003, 0xC003, 0xC003, 0xC003, 0xE007, 0x6306, 0x3F0E, 0x3C1C,
+ 0x3FF8, 0xF7E0, 0xC000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'R' */
+ 0x0000, 0x0FFE, 0x1FFE, 0x3806, 0x3006, 0x3006, 0x3006, 0x3806,
+ 0x1FFE, 0x07FE, 0x0306, 0x0606, 0x0C06, 0x1806, 0x1806, 0x3006,
+ 0x3006, 0x6006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'S' */
+ 0x0000, 0x03E0, 0x0FF8, 0x0C1C, 0x180C, 0x180C, 0x000C, 0x001C,
+ 0x03F8, 0x0FE0, 0x1E00, 0x3800, 0x3006, 0x3006, 0x300E, 0x1C1C,
+ 0x0FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'T' */
+ 0x0000, 0x7FFE, 0x7FFE, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
+ 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
+ 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'U' */
+ 0x0000, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C,
+ 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x1818,
+ 0x1FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'V' */
+ 0x0000, 0x6003, 0x3006, 0x3006, 0x3006, 0x180C, 0x180C, 0x180C,
+ 0x0C18, 0x0C18, 0x0E38, 0x0630, 0x0630, 0x0770, 0x0360, 0x0360,
+ 0x01C0, 0x01C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'W' */
+ 0x0000, 0x6003, 0x61C3, 0x61C3, 0x61C3, 0x3366, 0x3366, 0x3366,
+ 0x3366, 0x3366, 0x3366, 0x1B6C, 0x1B6C, 0x1B6C, 0x1A2C, 0x1E3C,
+ 0x0E38, 0x0E38, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'X' */
+ 0x0000, 0xE00F, 0x700C, 0x3018, 0x1830, 0x0C70, 0x0E60, 0x07C0,
+ 0x0380, 0x0380, 0x03C0, 0x06E0, 0x0C70, 0x1C30, 0x1818, 0x300C,
+ 0x600E, 0xE007, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'Y' */
+ 0x0000, 0xC003, 0x6006, 0x300C, 0x381C, 0x1838, 0x0C30, 0x0660,
+ 0x07E0, 0x03C0, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
+ 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'Z' */
+ 0x0000, 0x7FFC, 0x7FFC, 0x6000, 0x3000, 0x1800, 0x0C00, 0x0600,
+ 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018, 0x000C, 0x0006,
+ 0x7FFE, 0x7FFE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* '[' */
+ 0x0000, 0x03E0, 0x03E0, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060,
+ 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060,
+ 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x03E0, 0x03E0, 0x0000,
+ /* '\' */
+ 0x0000, 0x0030, 0x0030, 0x0060, 0x0060, 0x0060, 0x00C0, 0x00C0,
+ 0x00C0, 0x01C0, 0x0180, 0x0180, 0x0180, 0x0300, 0x0300, 0x0300,
+ 0x0600, 0x0600, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* ']' */
+ 0x0000, 0x03E0, 0x03E0, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300,
+ 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300,
+ 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x03E0, 0x03E0, 0x0000,
+ /* '^' */
+ 0x0000, 0x0000, 0x01C0, 0x01C0, 0x0360, 0x0360, 0x0360, 0x0630,
+ 0x0630, 0x0C18, 0x0C18, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* '_' */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* ''' */
+ 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'a' */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03F0, 0x07F8,
+ 0x0C1C, 0x0C0C, 0x0F00, 0x0FF0, 0x0CF8, 0x0C0C, 0x0C0C, 0x0F1C,
+ 0x0FF8, 0x18F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'b' */
+ 0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x03D8, 0x0FF8,
+ 0x0C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C38,
+ 0x0FF8, 0x03D8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'c' */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x07F0,
+ 0x0E30, 0x0C18, 0x0018, 0x0018, 0x0018, 0x0018, 0x0C18, 0x0E30,
+ 0x07F0, 0x03C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'd' */
+ 0x0000, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x1BC0, 0x1FF0,
+ 0x1C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C30,
+ 0x1FF0, 0x1BC0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'e' */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x0FF0,
+ 0x0C30, 0x1818, 0x1FF8, 0x1FF8, 0x0018, 0x0018, 0x1838, 0x1C30,
+ 0x0FF0, 0x07C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'f' */
+ 0x0000, 0x0F80, 0x0FC0, 0x00C0, 0x00C0, 0x00C0, 0x07F0, 0x07F0,
+ 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
+ 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'g' */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0DE0, 0x0FF8,
+ 0x0E18, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0E18,
+ 0x0FF8, 0x0DE0, 0x0C00, 0x0C0C, 0x061C, 0x07F8, 0x01F0, 0x0000,
+ /* 'h' */
+ 0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x07D8, 0x0FF8,
+ 0x1C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818,
+ 0x1818, 0x1818, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'i' */
+ 0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0,
+ 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
+ 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'j' */
+ 0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0,
+ 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
+ 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00F8, 0x0078, 0x0000,
+ /* 'k' */
+ 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x0C0C, 0x060C,
+ 0x030C, 0x018C, 0x00CC, 0x006C, 0x00FC, 0x019C, 0x038C, 0x030C,
+ 0x060C, 0x0C0C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'l' */
+ 0x0000, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
+ 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
+ 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'm' */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3C7C, 0x7EFF,
+ 0xE3C7, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183,
+ 0xC183, 0xC183, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'n' */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0798, 0x0FF8,
+ 0x1C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818,
+ 0x1818, 0x1818, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'o' */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x0FF0,
+ 0x0C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C30,
+ 0x0FF0, 0x03C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'p' */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03D8, 0x0FF8,
+ 0x0C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C38,
+ 0x0FF8, 0x03D8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0000,
+ /* 'q' */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1BC0, 0x1FF0,
+ 0x1C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C30,
+ 0x1FF0, 0x1BC0, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x0000,
+ /* 'r' */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x07B0, 0x03F0,
+ 0x0070, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030,
+ 0x0030, 0x0030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 's' */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03E0, 0x03F0,
+ 0x0E38, 0x0C18, 0x0038, 0x03F0, 0x07C0, 0x0C00, 0x0C18, 0x0E38,
+ 0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 't' */
+ 0x0000, 0x0000, 0x0080, 0x00C0, 0x00C0, 0x00C0, 0x07F0, 0x07F0,
+ 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
+ 0x07C0, 0x0780, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'u' */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1818, 0x1818,
+ 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C38,
+ 0x1FF0, 0x19E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'v' */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x180C, 0x0C18,
+ 0x0C18, 0x0C18, 0x0630, 0x0630, 0x0630, 0x0360, 0x0360, 0x0360,
+ 0x01C0, 0x01C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'w' */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x41C1, 0x41C1,
+ 0x61C3, 0x6363, 0x6363, 0x6363, 0x3636, 0x3636, 0x3636, 0x1C1C,
+ 0x1C1C, 0x1C1C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'x' */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x381C, 0x1C38,
+ 0x0C30, 0x0660, 0x0360, 0x0360, 0x0360, 0x0360, 0x0660, 0x0C30,
+ 0x1C38, 0x381C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* 'y' */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3018, 0x1830,
+ 0x1830, 0x1870, 0x0C60, 0x0C60, 0x0CE0, 0x06C0, 0x06C0, 0x0380,
+ 0x0380, 0x0380, 0x0180, 0x0180, 0x01C0, 0x00F0, 0x0070, 0x0000,
+ /* 'z' */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1FFC, 0x1FFC,
+ 0x0C00, 0x0600, 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018,
+ 0x1FFC, 0x1FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ /* '{' */
+ 0x0000, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
+ 0x00C0, 0x0060, 0x0060, 0x0030, 0x0060, 0x0040, 0x00C0, 0x00C0,
+ 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x0180, 0x0300, 0x0000, 0x0000,
+ /* '|' */
+ 0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
+ 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
+ 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0000,
+ /* '}' */
+ 0x0000, 0x0060, 0x00C0, 0x01C0, 0x0180, 0x0180, 0x0180, 0x0180,
+ 0x0180, 0x0300, 0x0300, 0x0600, 0x0300, 0x0100, 0x0180, 0x0180,
+ 0x0180, 0x0180, 0x0180, 0x0180, 0x00C0, 0x0060, 0x0000, 0x0000,
+ /* '~' */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x10F0, 0x1FF8, 0x0F08, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ };
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+ /* Global variables to set the written text color */
+static vu16 TextColor = 0x0000, BackColor = 0xFFFF;
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+static u32 StrLength(u8 *Str);
+
+/*******************************************************************************
+* Function Name : LCD_Init
+* Description : Initializes LCD.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void LCD_Init(void)
+{
+/* Configure the LCD Control pins --------------------------------------------*/
+ LCD_CtrlLinesConfig();
+
+/* Configure the SPI2 interface ----------------------------------------------*/
+ LCD_SPIConfig();
+
+/* Enable the LCD Oscillator -------------------------------------------------*/
+ LCD_WriteReg(R1, 0x10);
+ LCD_WriteReg(R0, 0xA0);
+ LCD_WriteReg(R3, 0x01);
+ vTaskDelay( 10 / portTICK_RATE_MS ); /* Delay 10 ms */
+ LCD_WriteReg(R3, 0x00);
+ LCD_WriteReg(R43, 0x04);
+
+ LCD_WriteReg(R40, 0x18);
+ LCD_WriteReg(R26, 0x05);
+ LCD_WriteReg(R37, 0x05);
+ LCD_WriteReg(R25, 0x00);
+
+/* LCD Power On --------------------------------------------------------------*/
+ LCD_WriteReg(R28, 0x73);
+ LCD_WriteReg(R36, 0x74);
+ LCD_WriteReg(R30, 0x01);
+ LCD_WriteReg(R24, 0xC1);
+ vTaskDelay( 10 / portTICK_RATE_MS ); /* Delay 10 ms */
+ LCD_WriteReg(R24, 0xE1);
+ LCD_WriteReg(R24, 0xF1);
+ vTaskDelay( 60 / portTICK_RATE_MS ); /* Delay 60 ms */
+ LCD_WriteReg(R24, 0xF5);
+ vTaskDelay( 60 / portTICK_RATE_MS ); /* Delay 60 ms */
+ LCD_WriteReg(R27, 0x09);
+ vTaskDelay( 10 / portTICK_RATE_MS ); /* Delay 10 ms */
+ LCD_WriteReg(R31, 0x11);
+ LCD_WriteReg(R32, 0x0E);
+ LCD_WriteReg(R30, 0x81);
+ vTaskDelay( 10 / portTICK_RATE_MS ); /* Delay 10 ms */
+
+/* Chip Set ------------------------------------------------------------------*/
+ LCD_WriteReg(R157, 0x00);
+ LCD_WriteReg(R192, 0x00);
+
+ LCD_WriteReg(R14, 0x00);
+ LCD_WriteReg(R15, 0x00);
+ LCD_WriteReg(R16, 0x00);
+ LCD_WriteReg(R17, 0x00);
+ LCD_WriteReg(R18, 0x00);
+ LCD_WriteReg(R19, 0x00);
+ LCD_WriteReg(R20, 0x00);
+ LCD_WriteReg(R21, 0x00);
+ LCD_WriteReg(R22, 0x00);
+ LCD_WriteReg(R23, 0x00);
+
+ LCD_WriteReg(R52, 0x01);
+ LCD_WriteReg(R53, 0x00);
+
+ LCD_WriteReg(R75, 0x00);
+ LCD_WriteReg(R76, 0x00);
+ LCD_WriteReg(R78, 0x00);
+ LCD_WriteReg(R79, 0x00);
+ LCD_WriteReg(R80, 0x00);
+
+ LCD_WriteReg(R60, 0x00);
+ LCD_WriteReg(R61, 0x00);
+ LCD_WriteReg(R62, 0x01);
+ LCD_WriteReg(R63, 0x3F);
+ LCD_WriteReg(R64, 0x02);
+ LCD_WriteReg(R65, 0x02);
+ LCD_WriteReg(R66, 0x00);
+ LCD_WriteReg(R67, 0x00);
+ LCD_WriteReg(R68, 0x00);
+ LCD_WriteReg(R69, 0x00);
+ LCD_WriteReg(R70, 0xEF);
+ LCD_WriteReg(R71, 0x00);
+ LCD_WriteReg(R72, 0x00);
+ LCD_WriteReg(R73, 0x01);
+ LCD_WriteReg(R74, 0x3F);
+
+ LCD_WriteReg(R29, 0x08); /* R29:Gate scan direction setting */
+
+ LCD_WriteReg(R134, 0x00);
+ LCD_WriteReg(R135, 0x30);
+ LCD_WriteReg(R136, 0x02);
+ LCD_WriteReg(R137, 0x05);
+
+ LCD_WriteReg(R141, 0x01); /* R141:Register set-up mode for one line clock */
+ LCD_WriteReg(R139, 0x20); /* R139:One line SYSCLK number in one-line */
+ LCD_WriteReg(R51, 0x01); /* R51:N line inversion setting */
+ LCD_WriteReg(R55, 0x01); /* R55:Scanning method setting */
+ LCD_WriteReg(R118, 0x00);
+
+/* Gamma Set -----------------------------------------------------------------*/
+ LCD_WriteReg(R143, 0x10);
+ LCD_WriteReg(R144, 0x67);
+ LCD_WriteReg(R145, 0x07);
+ LCD_WriteReg(R146, 0x65);
+ LCD_WriteReg(R147, 0x07);
+ LCD_WriteReg(R148, 0x01);
+ LCD_WriteReg(R149, 0x76);
+ LCD_WriteReg(R150, 0x56);
+ LCD_WriteReg(R151, 0x00);
+ LCD_WriteReg(R152, 0x06);
+ LCD_WriteReg(R153, 0x03);
+ LCD_WriteReg(R154, 0x00);
+
+/* Display On ----------------------------------------------------------------*/
+ LCD_WriteReg(R1, 0x50);
+ LCD_WriteReg(R5, 0x04);
+
+ LCD_WriteReg(R0, 0x80);
+ LCD_WriteReg(R59, 0x01);
+ vTaskDelay( 40 / portTICK_RATE_MS ); /* Delay 40 ms */
+ LCD_WriteReg(R0, 0x20);
+}
+
+/*******************************************************************************
+* Function Name : LCD_SetTextColor
+* Description : Sets the Text color.
+* Input : - Color: specifies the Text color code RGB(5-6-5).
+* Output : - TextColor: Text color global variable used by LCD_DrawChar
+* and LCD_DrawPicture functions.
+* Return : None
+*******************************************************************************/
+void LCD_SetTextColor(vu16 Color)
+{
+ TextColor = Color;
+}
+
+/*******************************************************************************
+* Function Name : LCD_SetBackColor
+* Description : Sets the Background color.
+* Input : - Color: specifies the Background color code RGB(5-6-5).
+* Output : - BackColor: Background color global variable used by
+* LCD_DrawChar and LCD_DrawPicture functions.
+* Return : None
+*******************************************************************************/
+void LCD_SetBackColor(vu16 Color)
+{
+ BackColor = Color;
+}
+
+/*******************************************************************************
+* Function Name : LCD_ClearLine
+* Description : Clears the selected line.
+* Input : - Line: the Line to be cleared.
+* This parameter can be one of the following values:
+* - Linex: where x can be 0..9
+* Output : None
+* Return : None
+*******************************************************************************/
+void LCD_ClearLine(u8 Line)
+{
+ LCD_DisplayStringLine(Line, " ");
+}
+
+/*******************************************************************************
+* Function Name : LCD_Clear
+* Description : Clears the hole LCD.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void LCD_Clear(void)
+{
+ u32 index = 0;
+
+ LCD_SetCursor(0x00, 0x013F);
+
+ for(index = 0; index < 0x12C00; index++)
+ {
+ LCD_WriteRAM(White);
+ }
+}
+
+/*******************************************************************************
+* Function Name : LCD_SetCursor
+* Description : Sets the cursor position.
+* Input : - Xpos: specifies the X position.
+* - Ypos: specifies the Y position.
+* Output : None
+* Return : None
+*******************************************************************************/
+void LCD_SetCursor(u8 Xpos, u16 Ypos)
+{
+ LCD_WriteReg(R66, Xpos);
+ LCD_WriteReg(R67, ((Ypos & 0x100)>> 8));
+ LCD_WriteReg(R68, (Ypos & 0xFF));
+}
+
+/*******************************************************************************
+* Function Name : LCD_DrawChar
+* Description : Draws a character on LCD.
+* Input : - Xpos: the Line where to display the character shape.
+* This parameter can be one of the following values:
+* - Linex: where x can be 0..9
+* - Ypos: start column address.
+* - c: pointer to the character data.
+* Output : None
+* Return : None
+*******************************************************************************/
+void LCD_DrawChar(u8 Xpos, u16 Ypos, uc16 *c)
+{
+ u32 index = 0, i = 0;
+ u8 Xaddress = 0;
+
+ Xaddress = Xpos;
+
+ LCD_SetCursor(Xaddress, Ypos);
+
+ for(index = 0; index < 24; index++)
+ {
+ for(i = 0; i < 16; i++)
+ {
+ if((c[index] & (1 << i)) == 0x00)
+ {
+ LCD_WriteRAM(BackColor);
+ }
+ else
+ {
+ LCD_WriteRAM(TextColor);
+ }
+ }
+ Xaddress++;
+ LCD_SetCursor(Xaddress, Ypos);
+ }
+}
+
+/*******************************************************************************
+* Function Name : LCD_DisplayChar
+* Description : Displays one character (16dots width, 24dots height).
+* Input : - Line: the Line where to display the character shape .
+* This parameter can be one of the following values:
+* - Linex: where x can be 0..9
+* - Column: start column address.
+* - Ascii: character ascii code, must be between 0x20 and 0x7E.
+* Output : None
+* Return : None
+*******************************************************************************/
+void LCD_DisplayChar(u8 Line, u16 Column, u8 Ascii)
+{
+ Ascii -= 32;
+ LCD_DrawChar(Line, Column, &ASCII_Table[Ascii * 24]);
+}
+
+/*******************************************************************************
+* Function Name : LCD_DisplayStringLine
+* Description : Displays a maximum of 20 char on the LCD.
+* Input : - Line: the Line where to display the character shape .
+* This parameter can be one of the following values:
+* - Linex: where x can be 0..9
+* - *ptr: pointer to string to display on LCD.
+* Output : None
+* Return : None
+*******************************************************************************/
+void LCD_DisplayStringLine(u8 Line, u8 *ptr)
+{
+ u32 i = 0;
+ u16 refcolumn = 319;
+
+ /* Send the string character by character on lCD */
+ while ((*ptr != 0) & (i < 20))
+ {
+ /* Display one character on LCD */
+ LCD_DisplayChar(Line, refcolumn, *ptr);
+ /* Decrement the column position by 16 */
+ refcolumn -= 16;
+ /* Point on the next character */
+ ptr++;
+ /* Increment the character counter */
+ i++;
+ }
+}
+
+/*******************************************************************************
+* Function Name : LCD_DisplayString
+* Description : Displays a maximum of 200 char on the LCD.
+* Input : - Line: the starting Line where to display the character shape.
+* This parameter can be one of the following values:
+* - Linex: where x can be 0..9
+* - *ptr: pointer to string to display on LCD.
+* Output : None
+* Return : None
+*******************************************************************************/
+void LCD_DisplayString(u8 Line, u8 *ptr)
+{
+ u32 i = 0, column = 0, index = 0, spaceindex = 0;
+ u16 refcolumn = 319;
+ u32 length = 0;
+
+ /* Get the string length */
+ length = StrLength(ptr);
+ if(length > 200)
+ {
+ /* Set the Cursor position */
+ LCD_SetCursor(Line, 0x013F);
+ /* Clear the Selected Line */
+ LCD_ClearLine(Line);
+ LCD_DisplayStringLine(Line, " String too long ");
+ }
+ else
+ {
+ /* Set the Cursor position */
+ LCD_SetCursor(Line, 0x013F);
+ /* Clear the Selected Line */
+ LCD_ClearLine(Line);
+
+ while(length--)
+ {
+ if(index == 20)
+ {
+ if(*ptr == 0x20)
+ {
+ ptr++;
+ }
+ else
+ {
+ for(i = 0; i < spaceindex; i++)
+ {
+ LCD_DisplayChar(Line, column, ' ');
+ column -= 16;
+ }
+ ptr -= (spaceindex - 1);
+ length += (spaceindex - 1);
+ }
+ Line += 24;
+ /* Clear the Selected Line */
+ LCD_ClearLine(Line);
+ refcolumn = 319;
+ index = 0;
+ }
+ /* Display one character on LCD */
+ LCD_DisplayChar(Line, refcolumn, *ptr);
+
+ /* Increment character number in one line */
+ index++;
+
+ /* Decrement the column position by 16 */
+ refcolumn -= 16;
+ /* Point on the next character */
+ ptr++;
+ /* Increment the number of character after the last space */
+ spaceindex++;
+ if(*ptr == 0x20)
+ {
+ spaceindex = 0;
+ column = refcolumn - 16;
+ }
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name : LCD_ScrollText
+* Description :
+* Input :
+* Output : None
+* Return : None
+*******************************************************************************/
+void LCD_ScrollText(u8 Line, u8 *ptr)
+{
+ u32 i = 0, length = 0, x = 0;
+ u16 refcolumn = 319;
+
+ /* Get the string length */
+ length = StrLength(ptr);
+
+ while(1)
+ {
+ /* Send the string character by character on lCD */
+ while ((*ptr != 0) & (i < 20))
+ {
+ /* Display one character on LCD */
+ LCD_DisplayChar(Line, refcolumn, *ptr);
+ /* Decrement the column position by 16 */
+ refcolumn -= 16;
+ /* Point on the next character */
+ ptr++;
+ /* Increment the character counter */
+ i++;
+ }
+ vTaskDelay( 100 / portTICK_RATE_MS );
+ i = 0;
+ //LCD_ClearLine(Line);
+ ptr -= length;
+ x++;
+ if(refcolumn < 16)
+ {
+ x = 0;
+ }
+ refcolumn = 319 - (x * 16);
+ }
+}
+
+/*******************************************************************************
+* Function Name : LCD_SetDisplayWindow
+* Description : Sets a display window
+* Input : - Xpos: specifies the X position.
+* - Ypos: specifies the Y position.
+* - Height: display window height.
+* - Width: display window width.
+* Output : None
+* Return : None
+*******************************************************************************/
+void LCD_SetDisplayWindow(u8 Xpos, u16 Ypos, u8 Height, u16 Width)
+{
+ LCD_WriteReg(R1, 0xD0);
+ LCD_WriteReg(R5, 0x14);
+
+ LCD_WriteReg(R69, Xpos);
+ LCD_WriteReg(R70, (Xpos + Height + 1));
+
+ LCD_WriteReg(R71, ((Ypos & 0x100)>> 8));
+ LCD_WriteReg(R72, (Ypos & 0xFF));
+
+ LCD_WriteReg(R73, (((Ypos + Width + 1) & 0x100)>> 8));
+ LCD_WriteReg(R74, ((Ypos + Width + 1) & 0xFF));
+
+ LCD_SetCursor(Xpos, Ypos);
+}
+
+/*******************************************************************************
+* Function Name : LCD_DrawLine
+* Description : Displays a line.
+* Input : - Xpos: specifies the X position.
+* - Ypos: specifies the Y position.
+* - Length: line length.
+* - Direction: line direction.
+* This parameter can be one of the following values: Vertical
+* or Horizontal.
+* Output : None
+* Return : None
+*******************************************************************************/
+void LCD_DrawLine(u8 Xpos, u16 Ypos, u16 Length, u8 Direction)
+{
+ u32 i = 0;
+
+ LCD_SetCursor(Xpos, Ypos);
+
+ if(Direction == Horizontal)
+ {
+ for(i = 0; i < Length; i++)
+ {
+ LCD_WriteRAM(TextColor);
+ }
+ }
+ else
+ {
+ for(i = 0; i < Length; i++)
+ {
+
+ LCD_WriteRAM(TextColor);
+ Xpos++;
+ LCD_SetCursor(Xpos, Ypos);
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name : LCD_DrawRect
+* Description : Displays a rectangle.
+* Input : - Xpos: specifies the X position.
+* - Ypos: specifies the Y position.
+* - Height: display rectangle height.
+* - Width: display rectangle width.
+* Output : None
+* Return : None
+*******************************************************************************/
+void LCD_DrawRect(u8 Xpos, u16 Ypos, u8 Height, u16 Width)
+{
+ LCD_DrawLine(Xpos, Ypos, Width, Horizontal);
+ LCD_DrawLine((Xpos + Height), Ypos, Width, Horizontal);
+
+ LCD_DrawLine(Xpos, Ypos, Height, Vertical);
+ LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, Vertical);
+}
+
+/*******************************************************************************
+* Function Name : LCD_DrawCircle
+* Description : Displays a circle.
+* Input : - Xpos: specifies the X position.
+* - Ypos: specifies the Y position.
+* - Height: display rectangle height.
+* - Width: display rectangle width.
+* Output : None
+* Return : None
+*******************************************************************************/
+void LCD_DrawCircle(u8 Xpos, u16 Ypos, u16 Radius)
+{
+ s32 D; /* Decision Variable */
+ u32 CurX; /* Current X Value */
+ u32 CurY; /* Current Y Value */
+
+ D = 3 - (Radius << 1);
+ CurX = 0;
+ CurY = Radius;
+
+ while (CurX <= CurY)
+ {
+ LCD_SetCursor(Xpos + CurX, Ypos + CurY);
+ LCD_WriteRAM(TextColor);
+ LCD_SetCursor(Xpos + CurX, Ypos - CurY);
+ LCD_WriteRAM(TextColor);
+ LCD_SetCursor(Xpos - CurX, Ypos + CurY);
+ LCD_WriteRAM(TextColor);
+ LCD_SetCursor(Xpos - CurX, Ypos - CurY);
+ LCD_WriteRAM(TextColor);
+ LCD_SetCursor(Xpos + CurY, Ypos + CurX);
+ LCD_WriteRAM(TextColor);
+ LCD_SetCursor(Xpos + CurY, Ypos - CurX);
+ LCD_WriteRAM(TextColor);
+ LCD_SetCursor(Xpos - CurY, Ypos + CurX);
+ LCD_WriteRAM(TextColor);
+ LCD_SetCursor(Xpos - CurY, Ypos - CurX);
+ LCD_WriteRAM(TextColor);
+
+ if (D < 0)
+ {
+ D += (CurX << 2) + 6;
+ }
+ else
+ {
+ D += ((CurX - CurY) << 2) + 10;
+ CurY--;
+ }
+ CurX++;
+ }
+}
+
+/*******************************************************************************
+* Function Name : LCD_DrawMonoPict
+* Description : Displays a monocolor picture.
+* Input : - Pict: pointer to the picture array.
+* Output : None
+* Return : None
+*******************************************************************************/
+void LCD_DrawMonoPict(uc32 *Pict)
+{
+ u32 index = 0, i = 0;
+
+ LCD_SetCursor(0, 319);
+
+ for(index = 0; index < 2400; index++)
+ {
+ for(i = 0; i < 32; i++)
+ {
+ if((Pict[index] & (1 << i)) == 0x00)
+ {
+ LCD_WriteRAM(BackColor);
+ }
+ else
+ {
+ LCD_WriteRAM(TextColor);
+ }
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name : LCD_DrawBMP
+* Description : Displays a bitmap picture loaded in the SPI Flash.
+* Input : - BmpAddress: Bmp picture address in the SPI Flash.
+* Output : None
+* Return : None
+*******************************************************************************/
+void LCD_DrawBMP(u32 BmpAddress)
+{
+ u32 i = 0;
+
+ LCD_WriteReg(R1, 0xD0);
+ LCD_WriteReg(R5, 0x04);
+
+ LCD_SetCursor(239, 0x013F);
+
+ SPI_FLASH_StartReadSequence(BmpAddress);
+
+ /* Disable SPI1 */
+ SPI_Cmd(SPI1, DISABLE);
+ /* SPI in 16-bit mode */
+ SPI_DataSizeConfig(SPI1, SPI_DataSize_16b);
+ /* Enable SPI1 */
+ SPI_Cmd(SPI1, ENABLE);
+
+ for(i = 0; i < 76800; i++)
+ {
+ LCD_WriteRAM(__REV_HalfWord(SPI_FLASH_SendHalfWord(0xA5A5)));
+ }
+
+ /* Deselect the FLASH: Chip Select high */
+ SPI_FLASH_ChipSelect(1);
+
+ /* Disable SPI1 */
+ SPI_Cmd(SPI1, DISABLE);
+ /* SPI in 8-bit mode */
+ SPI_DataSizeConfig(SPI1, SPI_DataSize_8b);
+ /* Enable SPI1 */
+ SPI_Cmd(SPI1, ENABLE);
+}
+
+/*******************************************************************************
+* Function Name : LCD_WriteReg
+* Description : Writes to the selected LCD register.
+* Input : - LCD_Reg: address of the selected register.
+* - LCD_RegValue: value to write to the selected register.
+* Output : None
+* Return : None
+*******************************************************************************/
+void LCD_WriteReg(u8 LCD_Reg, u8 LCD_RegValue)
+{
+ u16 tmp = 0;
+
+ LCD_CtrlLinesWrite(GPIOD, CtrlPin_NWR, Bit_RESET);
+ LCD_CtrlLinesWrite(GPIOD, CtrlPin_RS, Bit_RESET);
+ LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_RESET);
+
+ tmp = LCD_Reg << 8;
+ tmp |= LCD_RegValue;
+
+ SPI_SendData(SPI2, tmp);
+ while(SPI_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET)
+ {
+ }
+
+ LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_SET);
+}
+
+/*******************************************************************************
+* Function Name : LCD_ReadReg
+* Description : Reads the selected LCD Register.
+* Input : None
+* Output : None
+* Return : LCD Register Value.
+*******************************************************************************/
+u8 LCD_ReadReg(u8 LCD_Reg)
+{
+ u16 tmp = 0;
+
+ LCD_CtrlLinesWrite(GPIOD, CtrlPin_NWR, Bit_RESET);
+ LCD_CtrlLinesWrite(GPIOD, CtrlPin_RS, Bit_RESET);
+ LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_RESET);
+
+ while(SPI_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET)
+ {
+ }
+ SPI_SendData(SPI2, LCD_Reg);
+
+ LCD_CtrlLinesWrite(GPIOD, CtrlPin_NWR, Bit_SET);
+
+ while(SPI_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET)
+ {
+ }
+ SPI_SendData(SPI2, 0xFF);
+
+ while(SPI_GetFlagStatus(SPI2, SPI_FLAG_RXNE)== RESET)
+ {
+ }
+ tmp = SPI_ReceiveData(SPI2);
+
+ LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_SET);
+ return tmp;
+}
+
+/*******************************************************************************
+* Function Name : LCD_WriteRAM
+* Description : Writes to the LCD RAM.
+* Input : - RGB_Code: the pixel color in RGB mode (5-6-5).
+* Output : None
+* Return : None
+*******************************************************************************/
+void LCD_WriteRAM(u16 RGB_Code)
+{
+ LCD_CtrlLinesWrite(GPIOD, CtrlPin_NWR, Bit_RESET);
+ LCD_CtrlLinesWrite(GPIOD, CtrlPin_RS, Bit_SET);
+ LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_RESET);
+
+ SPI_SendData(SPI2, RGB_Code);
+ while(SPI_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET)
+ {
+ }
+
+ LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_SET);
+}
+
+/*******************************************************************************
+* Function Name : LCD_ReadRAM
+* Description : Reads the LCD RAM.
+* Input : None
+* Output : None
+* Return : LCD RAM Value.
+*******************************************************************************/
+u16 LCD_ReadRAM(void)
+{
+ u16 tmp = 0;
+
+ LCD_CtrlLinesWrite(GPIOD, CtrlPin_NWR, Bit_SET);
+ LCD_CtrlLinesWrite(GPIOD, CtrlPin_RS, Bit_SET);
+ LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_RESET);
+
+ while(SPI_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET)
+ {
+ }
+ SPI_SendData(SPI2, 0xFF);
+ while(SPI_GetFlagStatus(SPI2, SPI_FLAG_RXNE)==RESET)
+ {
+ }
+ tmp = SPI_ReceiveData(SPI2);
+
+ LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_SET);
+
+ return tmp;
+}
+
+/*******************************************************************************
+* Function Name : LCD_PowerOn
+* Description :
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void LCD_PowerOn(void)
+{
+ /* Power On Set */
+ LCD_WriteReg(R28, 0x73);
+ LCD_WriteReg(R36, 0x74);
+ LCD_WriteReg(R30, 0x01);
+ LCD_WriteReg(R24, 0xC1);
+ vTaskDelay( 10 / portTICK_RATE_MS ); /* Delay 10 ms */
+ LCD_WriteReg(R24, 0xE1);
+ LCD_WriteReg(R24, 0xF1);
+ vTaskDelay( 60 / portTICK_RATE_MS ); /* Delay 60 ms */
+ LCD_WriteReg(R24, 0xF5);
+ vTaskDelay( 60 / portTICK_RATE_MS ); /* Delay 60 ms */
+ LCD_WriteReg(R27, 0x09);
+ vTaskDelay( 10 / portTICK_RATE_MS ); /* Delay 10 ms */
+ LCD_WriteReg(R31, 0x11);
+ LCD_WriteReg(R32, 0x0E);
+ LCD_WriteReg(R30, 0x81);
+ vTaskDelay( 10 / portTICK_RATE_MS ); /* Delay 10 ms */
+}
+
+/*******************************************************************************
+* Function Name : LCD_DisplayOn
+* Description : Enables the Display.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void LCD_DisplayOn(void)
+{
+ LCD_WriteReg(R1, 0x50);
+ LCD_WriteReg(R5, 0x04);
+
+ /* Display On */
+ LCD_WriteReg(R0, 0x80);
+ LCD_WriteReg(R59, 0x01);
+ vTaskDelay( 40 / portTICK_RATE_MS ); /* Delay 40 ms */
+ LCD_WriteReg(R0, 0x20);
+}
+
+/*******************************************************************************
+* Function Name : LCD_DisplayOff
+* Description : Disables the Display.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void LCD_DisplayOff(void)
+{
+ /* Display Off */
+ LCD_WriteReg(R0, 0xA0);
+ vTaskDelay( 40 / portTICK_RATE_MS ); /* Delay 40 ms */
+ LCD_WriteReg(R59, 0x00);
+}
+
+/*******************************************************************************
+* Function Name : LCD_CtrlLinesConfig
+* Description : Configures LCD control lines in Output Push-Pull mode.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void LCD_CtrlLinesConfig(void)
+{
+ GPIO_InitTypeDef GPIO_InitStructure;
+
+ /* Configure NCS (PB.02) in Output Push-Pull mode */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+ GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+ /* Configure NWR(RNW), RS (PD.15, PD.07) in Output Push-Pull mode */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_15;
+ GPIO_Init(GPIOD, &GPIO_InitStructure);
+}
+
+/*******************************************************************************
+* Function Name : LCD_CtrlLinesWrite
+* Description : Sets or reset LCD control lines.
+* Input : - GPIOx: where x can be B or D to select the GPIO peripheral.
+* - CtrlPins: the Control line. This parameter can be:
+* - CtrlPin_NCS: Chip Select pin (PB.02)
+* - CtrlPin_NWR: Read/Write Selection pin (PD.15)
+* - CtrlPin_RS: Register/RAM Selection pin (PD.07)
+* - BitVal: specifies the value to be written to the selected bit.
+* This parameter can be:
+* - Bit_RESET: to clear the port pin
+* - Bit_SET: to set the port pin
+* Output : None
+* Return : None
+*******************************************************************************/
+void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, u16 CtrlPins, BitAction BitVal)
+{
+ /* Set or Reset the control line */
+ GPIO_WriteBit(GPIOx, CtrlPins, BitVal);
+}
+
+/*******************************************************************************
+* Function Name : LCD_SPIConfig
+* Description : Configures the SPI2 interface.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void LCD_SPIConfig(void)
+{
+ SPI_InitTypeDef SPI_InitStructure;
+ GPIO_InitTypeDef GPIO_InitStructure;
+
+ /* Enable GPIOA clock */
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
+
+ /* Enable SPI2 clock */
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
+
+ /* Configure SPI2 pins: NSS, SCK, MISO and MOSI */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+ /* SPI2 Config */
+ SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
+ SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
+ SPI_InitStructure.SPI_DataSize = SPI_DataSize_16b;
+ SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
+ SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
+ SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
+ SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
+ SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
+ SPI_Init(SPI2, &SPI_InitStructure);
+
+ /* SPI2 enable */
+ SPI_Cmd(SPI2, ENABLE);
+}
+
+/*******************************************************************************
+* Function Name : StrLength
+* Description : Returns length of string.
+* Input : - Str: Character Pointer.
+* Output : None
+* Return : String length.
+*******************************************************************************/
+static u32 StrLength(u8 *Str)
+{
+ u32 Index = 0;
+
+ /* Increment the Index unless the end of string */
+ for(Index = 0; *Str != '\0'; Str++, Index++)
+ {
+ }
+
+ return Index;
+}
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_adc.c b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_adc.c
new file mode 100644
index 0000000..caf94a2
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_adc.c
@@ -0,0 +1,1321 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_adc.c
+* Author : MCD Application Team
+* Date First Issued : 09/29/2006
+* Description : This file provides all the ADC firmware functions.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_adc.h"
+#include "stm32f10x_rcc.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* ADC ADON mask */
+#define CR2_ADON_Set ((u32)0x00000001)
+#define CR2_ADON_Reset ((u32)0xFFFFFFFE)
+
+/* ADC DMA mask */
+#define CR2_DMA_Set ((u16)0x0100)
+#define CR2_DMA_Reset ((u16)0xFEFF)
+
+/* ADC RSTCAL mask */
+#define CR2_RSTCAL_Set ((u16)0x0008)
+
+/* ADC CAL mask */
+#define CR2_CAL_Set ((u16)0x0004)
+
+/* ADC SWSTRT mask */
+#define CR2_SWSTRT_Set ((u32)0x00400000)
+
+/* ADC DISCNUM mask */
+#define CR1_DISCNUM_Reset ((u32)0xFFFF1FFF)
+
+/* ADC DISCEN mask */
+#define CR1_DISCEN_Set ((u32)0x00000800)
+#define CR1_DISCEN_Reset ((u32)0xFFFFF7FF)
+
+/* ADC EXTTRIG mask */
+#define CR2_EXTTRIG_Set ((u32)0x00100000)
+#define CR2_EXTTRIG_Reset ((u32)0xFFEFFFFF)
+
+/* ADC Software start mask */
+#define CR2_EXTTRIG_SWSTRT_Set ((u32)0x00500000)
+#define CR2_EXTTRIG_SWSTRT_Reset ((u32)0xFFAFFFFF)
+
+/* ADC JAUTO mask */
+#define CR1_JAUTO_Set ((u32)0x00000400)
+#define CR1_JAUTO_Reset ((u32)0xFFFFFBFF)
+
+/* ADC JDISCEN mask */
+#define CR1_JDISCEN_Set ((u32)0x00001000)
+#define CR1_JDISCEN_Reset ((u32)0xFFFFEFFF)
+
+/* ADC JEXTSEL mask */
+#define CR2_JEXTSEL_Reset ((u32)0xFFFF8FFF)
+
+/* ADC JEXTTRIG mask */
+#define CR2_JEXTTRIG_Set ((u32)0x00008000)
+#define CR2_JEXTTRIG_Reset ((u32)0xFFFF7FFF)
+
+/* ADC JSWSTRT mask */
+#define CR2_JSWSTRT_Set ((u32)0x00200000)
+
+/* ADC injected software start mask */
+#define CR2_JEXTTRIG_JSWSTRT_Set ((u32)0x00208000)
+#define CR2_JEXTTRIG_JSWSTRT_Reset ((u32)0xFFDF7FFF)
+
+/* ADC AWDCH mask */
+#define CR1_AWDCH_Reset ((u32)0xFFFFFFE0)
+
+/* ADC SQx mask */
+#define SQR3_SQ_Set ((u8)0x1F)
+#define SQR2_SQ_Set ((u8)0x1F)
+#define SQR1_SQ_Set ((u8)0x1F)
+
+/* ADC JSQx mask */
+#define JSQR_JSQ_Set ((u8)0x1F)
+
+/* ADC JL mask */
+#define JSQR_JL_Reset ((u32)0xFFCFFFFF)
+
+/* ADC SMPx mask */
+#define SMPR1_SMP_Set ((u8)0x07)
+#define SMPR2_SMP_Set ((u8)0x07)
+
+/* ADC Analog watchdog enable mode mask */
+#define CR1_AWDMode_Reset ((u32)0xFF3FFDFF)
+
+/* ADC TSPD mask */
+#define CR2_TSPD_Set ((u32)0x00800000)
+#define CR2_TSPD_Reset ((u32)0xFF7FFFFF)
+
+/* ADC JDRx registers= offset */
+#define JDR_Offset ((u8)0x28)
+
+/* ADC registers Masks */
+#define CR1_CLEAR_Mask ((u32)0xFFF0FEFF)
+#define CR2_CLEAR_Mask ((u32)0xFFF1F7FD)
+#define SQR1_CLEAR_Mask ((u32)0xFF0FFFFF)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name : ADC_DeInit
+* Description : Deinitializes the ADCx peripheral registers to their default
+* reset values.
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+* Output : None
+* Return : None
+*******************************************************************************/
+void ADC_DeInit(ADC_TypeDef* ADCx)
+{
+ switch (*(u32*)&ADCx)
+ {
+ case ADC1_BASE:
+ /* Enable ADC1 reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);
+ /* Release ADC1 from reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);
+ break;
+
+ case ADC2_BASE:
+ /* Enable ADC2 reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE);
+ /* Release ADC2 from reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name : ADC_Init
+* Description : Initializes the ADCx according to the specified parameters
+* in the ADC_InitStruct.
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+* - ADC_InitStruct: pointer to a ADC_InitTypeDef structure that
+* contains the configuration information for the specified
+* ADC peripheral.
+* Output : None
+* Return : None
+******************************************************************************/
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
+{
+ u32 tmpreg1 = 0;
+ u8 tmpreg2 = 0;
+
+ /* Check the parameters */
+ assert(IS_ADC_MODE(ADC_InitStruct->ADC_Mode));
+ assert(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));
+ assert(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode));
+ assert(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv));
+ assert(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign));
+ assert(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel));
+
+ /*---------------------------- ADCx CR1 Configuration -----------------*/
+ /* Get the ADCx CR1 value */
+ tmpreg1 = ADCx->CR1;
+ /* Clear DUALMODE and SCAN bits */
+ tmpreg1 &= CR1_CLEAR_Mask;
+ /* Configure ADCx: Dual mode and scan conversion mode */
+ /* Set DUALMODE bits according to ADC_Mode value */
+ /* Set SCAN bit according to ADC_ScanConvMode value */
+ tmpreg1 |= (u32)(ADC_InitStruct->ADC_Mode | ((u32)ADC_InitStruct->ADC_ScanConvMode << 8));
+ /* Write to ADCx CR1 */
+ ADCx->CR1 = tmpreg1;
+
+ /*---------------------------- ADCx CR2 Configuration -----------------*/
+ /* Get the ADCx CR2 value */
+ tmpreg1 = ADCx->CR2;
+ /* Clear CONT, ALIGN and EXTTRIG bits */
+ tmpreg1 &= CR2_CLEAR_Mask;
+ /* Configure ADCx: external trigger event and continuous conversion mode */
+ /* Set ALIGN bit according to ADC_DataAlign value */
+ /* Set EXTTRIG bits according to ADC_ExternalTrigConv value */
+ /* Set CONT bit according to ADC_ContinuousConvMode value */
+ tmpreg1 |= (u32)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv |
+ ((u32)ADC_InitStruct->ADC_ContinuousConvMode << 1));
+ /* Write to ADCx CR2 */
+ ADCx->CR2 = tmpreg1;
+
+ /*---------------------------- ADCx SQR1 Configuration -----------------*/
+ /* Get the ADCx SQR1 value */
+ tmpreg1 = ADCx->SQR1;
+ /* Clear L bits */
+ tmpreg1 &= SQR1_CLEAR_Mask;
+ /* Configure ADCx: regular channel sequence length */
+ /* Set L bits according to ADC_NbrOfChannel value */
+ tmpreg2 |= (ADC_InitStruct->ADC_NbrOfChannel - 1);
+ tmpreg1 |= ((u32)tmpreg2 << 20);
+ /* Write to ADCx SQR1 */
+ ADCx->SQR1 = tmpreg1;
+}
+
+/*******************************************************************************
+* Function Name : ADC_StructInit
+* Description : Fills each ADC_InitStruct member with its default value.
+* Input : ADC_InitStruct : pointer to a ADC_InitTypeDef structure
+* which will be initialized.
+* Output : None
+* Return : None
+*******************************************************************************/
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)
+{
+ /* Reset ADC init structure parameters values */
+ /* Initialize the ADC_Mode member */
+ ADC_InitStruct->ADC_Mode = ADC_Mode_Independent;
+
+ /* initialize the ADC_ScanConvMode member */
+ ADC_InitStruct->ADC_ScanConvMode = DISABLE;
+
+ /* Initialize the ADC_ContinuousConvMode member */
+ ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
+
+ /* Initialize the ADC_ExternalTrigConv member */
+ ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1;
+
+ /* Initialize the ADC_DataAlign member */
+ ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
+
+ /* Initialize the ADC_NbrOfChannel member */
+ ADC_InitStruct->ADC_NbrOfChannel = 1;
+}
+
+/*******************************************************************************
+* Function Name : ADC_Cmd
+* Description : Enables or disables the specified ADC peripheral.
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+* - NewState: new state of the ADCx peripheral. This parameter
+* can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Set the ADON bit to wake up the ADC from power down mode */
+ ADCx->CR2 |= CR2_ADON_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC peripheral */
+ ADCx->CR2 &= CR2_ADON_Reset;
+ }
+}
+
+/*******************************************************************************
+* Function Name : ADC_DMACmd
+* Description : Enables or disables the specified ADC DMA request.
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+* - NewState: new state of the selected ADC DMA transfer.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC DMA request */
+ ADCx->CR2 |= CR2_DMA_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC DMA request */
+ ADCx->CR2 &= CR2_DMA_Reset;
+ }
+}
+
+/*******************************************************************************
+* Function Name : ADC_ITConfig
+* Description : Enables or disables the specified ADC interrupts.
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+* - ADC_IT: specifies the ADC interrupts sources to be enabled
+* or disabled.
+* This parameter can be any combination of the following values:
+* - ADC_IT_EOC: End of conversion interrupt mask
+* - ADC_IT_AWD: Analog watchdog interrupt mask
+* - ADC_IT_JEOC: End of injected conversion interrupt mask
+* - NewState: new state of the specified ADC interrupts.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void ADC_ITConfig(ADC_TypeDef* ADCx, u16 ADC_IT, FunctionalState NewState)
+{
+ u8 itmask = 0;
+
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+ assert(IS_ADC_IT(ADC_IT));
+
+ /* Get the ADC IT index */
+ itmask = (u8)ADC_IT;
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC interrupts */
+ ADCx->CR1 |= itmask;
+ }
+ else
+ {
+ /* Disable the selected ADC interrupts */
+ ADCx->CR1 &= (~(u32)itmask);
+ }
+}
+
+/*******************************************************************************
+* Function Name : ADC_ResetCalibration
+* Description : Resets the ADC calibration registers.
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+* Output : None
+* Return : None
+*******************************************************************************/
+void ADC_ResetCalibration(ADC_TypeDef* ADCx)
+{
+ /* Resets the selected ADC calibartion registers */
+ ADCx->CR2 |= CR2_RSTCAL_Set;
+}
+
+/*******************************************************************************
+* Function Name : ADC_GetResetCalibrationStatus
+* Description : Gets the ADC reset calibration registers status.
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+* Output : None
+* Return : The new state of ADC Reset Calibration registers (SET or RESET).
+*******************************************************************************/
+FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx)
+{
+ FlagStatus bitstatus = RESET;
+
+ /* Check the status of RSTCAL bit */
+ if ((ADCx->CR2 & CR2_RSTCAL_Set) != (u16)RESET)
+ {
+ /* RSTCAL bit is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* RSTCAL bit is reset */
+ bitstatus = RESET;
+ }
+ /* Return the RSTCAL bit status */
+ return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name : ADC_StartCalibration
+* Description : Starts the calibration process.
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+* Output : None
+* Return : None
+*******************************************************************************/
+void ADC_StartCalibration(ADC_TypeDef* ADCx)
+{
+ /* Enable the selected ADC calibration process */
+ ADCx->CR2 |= CR2_CAL_Set;
+}
+
+/*******************************************************************************
+* Function Name : ADC_GetCalibrationStatus
+* Description : Gets the ADC calibration status.
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+* Output : None
+* Return : The new state of ADC calibration (SET or RESET).
+*******************************************************************************/
+FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx)
+{
+ FlagStatus bitstatus = RESET;
+
+ /* Check the status of CAL bit */
+ if ((ADCx->CR2 & CR2_CAL_Set) != (u16)RESET)
+ {
+ /* CAL bit is set: calibration on going */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAL bit is reset: end of calibration */
+ bitstatus = RESET;
+ }
+ /* Return the CAL bit status */
+ return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name : ADC_SoftwareStartConvCmd
+* Description : Enables or disables the ADC software start conversion .
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+* - NewState: new state of the selected ADC software start conversion.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC conversion on external event */
+ /* Starts the selected ADC conversion */
+ ADCx->CR2 |= CR2_EXTTRIG_SWSTRT_Set;
+ }
+ else
+ {
+ /* Stops the selected ADC conversion */
+ /* Disable the selected ADC conversion on external event */
+ ADCx->CR2 &= CR2_EXTTRIG_SWSTRT_Reset;
+ }
+}
+
+/*******************************************************************************
+* Function Name : ADC_GetSoftwareStartConvStatus
+* Description : Gets the ADC Software start conversion Status.
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+* Output : None
+* Return : The new state of ADC software start conversion (SET or RESET).
+*******************************************************************************/
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)
+{
+ FlagStatus bitstatus = RESET;
+
+ /* Check the status of SWSTRT bit */
+ if ((ADCx->CR2 & CR2_SWSTRT_Set) != (u32)RESET)
+ {
+ /* SWSTRT bit is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* SWSTRT bit is reset */
+ bitstatus = RESET;
+ }
+ /* Return the SWSTRT bit status */
+ return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name : ADC_DiscModeChannelCountConfig
+* Description : Configures the discontinuous mode for the selected ADC regular
+* group channel.
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+* - Number: specifies the discontinuous mode regular channel
+* count value. This mumber must be between 1 and 8.
+* Output : None
+* Return : None
+*******************************************************************************/
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, u8 Number)
+{
+ u32 tmpreg1 = 0;
+ u8 tmpreg2 = 0;
+
+ /* Check the parameters */
+ assert(IS_ADC_REGULAR_DISC_NUMBER(Number));
+
+ /* Get the old register value */
+ tmpreg1 = ADCx->CR1;
+ /* Clear the old discontinuous mode channel count */
+ tmpreg1 &= CR1_DISCNUM_Reset;
+ /* Set the discontinuous mode channel count */
+ tmpreg2 = Number - 1;
+ tmpreg1 |= ((u32)tmpreg2 << 13);
+ /* Store the new register value */
+ ADCx->CR1 = tmpreg1;
+}
+
+/*******************************************************************************
+* Function Name : ADC_DiscModeCmd
+* Description : Enables or disables the discontinuous mode on regular group
+* channel for the specified ADC
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+* - NewState: new state of the selected ADC discontinuous mode
+* on regular group channel.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC regular discontinuous mode */
+ ADCx->CR1 |= CR1_DISCEN_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC regular discontinuous mode */
+ ADCx->CR1 &= CR1_DISCEN_Reset;
+ }
+}
+
+/*******************************************************************************
+* Function Name : ADC_RegularChannelConfig
+* Description : Configures for the selected ADC regular channel its corresponding
+* rank in the sequencer and its sample time.
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+* - ADC_Channel: the ADC channel to configure.
+* This parameter can be one of the following values:
+* - ADC_Channel_0: ADC Channel0 selected
+* - ADC_Channel_1: ADC Channel1 selected
+* - ADC_Channel_2: ADC Channel2 selected
+* - ADC_Channel_3: ADC Channel3 selected
+* - ADC_Channel_4: ADC Channel4 selected
+* - ADC_Channel_5: ADC Channel5 selected
+* - ADC_Channel_6: ADC Channel6 selected
+* - ADC_Channel_7: ADC Channel7 selected
+* - ADC_Channel_8: ADC Channel8 selected
+* - ADC_Channel_9: ADC Channel9 selected
+* - ADC_Channel_10: ADC Channel10 selected
+* - ADC_Channel_11: ADC Channel11 selected
+* - ADC_Channel_12: ADC Channel12 selected
+* - ADC_Channel_13: ADC Channel13 selected
+* - ADC_Channel_14: ADC Channel14 selected
+* - ADC_Channel_15: ADC Channel15 selected
+* - ADC_Channel_16: ADC Channel16 selected
+* - ADC_Channel_17: ADC Channel17 selected
+* - Rank: The rank in the regular group sequencer. This parameter
+* must be between 1 to 16.
+* - ADC_SampleTime: The sample time value to be set for the
+* selected channel.
+* This parameter can be one of the following values:
+* - ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles
+* - ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles
+* - ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles
+* - ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles
+* - ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles
+* - ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles
+* - ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles
+* - ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles
+* Output : None
+* Return : None
+*******************************************************************************/
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime)
+{
+ u32 tmpreg1 = 0, tmpreg2 = 0;
+
+ /* Check the parameters */
+ assert(IS_ADC_CHANNEL(ADC_Channel));
+ assert(IS_ADC_REGULAR_RANK(Rank));
+ assert(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
+
+ /* if ADC_Channel_10 ... ADC_Channel_17 is selected */
+ if (ADC_Channel > ADC_Channel_9)
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SMPR1;
+ /* Calculate the mask to clear */
+ tmpreg2 = (u32)SMPR1_SMP_Set << (3 * (ADC_Channel - 10));
+ /* Clear the old discontinuous mode channel count */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (u32)ADC_SampleTime << (3 * (ADC_Channel - 10));
+ /* Set the discontinuous mode channel count */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SMPR1 = tmpreg1;
+ }
+ else /* ADC_Channel include in ADC_Channel_[0..9] */
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SMPR2;
+ /* Calculate the mask to clear */
+ tmpreg2 = (u32)SMPR2_SMP_Set << (3 * ADC_Channel);
+ /* Clear the old discontinuous mode channel count */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (u32)ADC_SampleTime << (3 * ADC_Channel);
+ /* Set the discontinuous mode channel count */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SMPR2 = tmpreg1;
+ }
+ /* For Rank 1 to 6 */
+ if (Rank < 7)
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SQR3;
+ /* Calculate the mask to clear */
+ tmpreg2 = (u32)SQR3_SQ_Set << (5 * (Rank - 1));
+ /* Clear the old SQx bits for the selected rank */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (u32)ADC_Channel << (5 * (Rank - 1));
+ /* Set the SQx bits for the selected rank */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SQR3 = tmpreg1;
+ }
+ /* For Rank 7 to 12 */
+ else if (Rank < 13)
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SQR2;
+ /* Calculate the mask to clear */
+ tmpreg2 = (u32)SQR2_SQ_Set << (5 * (Rank - 7));
+ /* Clear the old SQx bits for the selected rank */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (u32)ADC_Channel << (5 * (Rank - 7));
+ /* Set the SQx bits for the selected rank */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SQR2 = tmpreg1;
+ }
+ /* For Rank 13 to 16 */
+ else
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SQR1;
+ /* Calculate the mask to clear */
+ tmpreg2 = (u32)SQR1_SQ_Set << (5 * (Rank - 13));
+ /* Clear the old SQx bits for the selected rank */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (u32)ADC_Channel << (5 * (Rank - 13));
+ /* Set the SQx bits for the selected rank */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SQR1 = tmpreg1;
+ }
+}
+
+/*******************************************************************************
+* Function Name : ADC_ExternalTrigConvCmd
+* Description : Enables or disables the ADCx conversion through external trigger.
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+* - NewState: new state of the selected ADC external trigger
+* start of conversion.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC conversion on external event */
+ ADCx->CR2 |= CR2_EXTTRIG_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC conversion on external event */
+ ADCx->CR2 &= CR2_EXTTRIG_Reset;
+ }
+}
+
+/*******************************************************************************
+* Function Name : ADC_GetConversionValue
+* Description : Returns the last ADC conversion result data for regular channel.
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+* Output : None
+* Return : The Data conversion value.
+*******************************************************************************/
+u16 ADC_GetConversionValue(ADC_TypeDef* ADCx)
+{
+ /* Return the selected ADC conversion value */
+ return (u16) ADCx->DR;
+}
+
+/*******************************************************************************
+* Function Name : ADC_GetDualModeConversionValue
+* Description : Returns the last ADCs conversion result data in dual mode.
+* Output : None
+* Return : The Data conversion value.
+*******************************************************************************/
+u32 ADC_GetDualModeConversionValue(void)
+{
+ /* Return the dual mode conversion value */
+ return ADC1->DR;
+}
+
+/*******************************************************************************
+* Function Name : ADC_AutoInjectedConvCmd
+* Description : Enables or disables the automatic injected group conversion
+* after regular one.
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+* - NewState: new state of the selected ADC auto injected
+* conversion
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC automatic injected group conversion */
+ ADCx->CR1 |= CR1_JAUTO_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC automatic injected group conversion */
+ ADCx->CR1 &= CR1_JAUTO_Reset;
+ }
+}
+
+/*******************************************************************************
+* Function Name : ADC_InjectedDiscModeCmd
+* Description : Enables or disables the discontinuous mode for injected group
+* channel for the specified ADC
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+* - NewState: new state of the selected ADC discontinuous mode
+* on injected group channel.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC injected discontinuous mode */
+ ADCx->CR1 |= CR1_JDISCEN_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC injected discontinuous mode */
+ ADCx->CR1 &= CR1_JDISCEN_Reset;
+ }
+}
+
+/*******************************************************************************
+* Function Name : ADC_ExternalTrigInjectedConvConfig
+* Description : Configures the external trigger for injected channels conversion.
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+* - ADC_ExternalTrigInjecConv: specifies the ADC trigger to
+* start injected conversion.
+* This parameter can be one of the following values:
+* - ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event
+* selected
+* - ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture
+* compare4 selected
+* - ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event
+* selected
+* - ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture
+* compare1 selected
+* - ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture
+* compare4 selected
+* - ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event
+* selected
+* - ADC_ExternalTrigInjecConv_Ext_Interrupt15: External
+* interrupt 15 event selected
+* - ADC_ExternalTrigInjecConv_None: Injected conversion
+* started by software and not by external trigger
+* Output : None
+* Return : None
+*******************************************************************************/
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, u32 ADC_ExternalTrigInjecConv)
+{
+ u32 tmpreg = 0;
+
+ /* Check the parameters */
+ assert(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv));
+
+ /* Get the old register value */
+ tmpreg = ADCx->CR2;
+ /* Clear the old external event selection for injected group */
+ tmpreg &= CR2_JEXTSEL_Reset;
+ /* Set the external event selection for injected group */
+ tmpreg |= ADC_ExternalTrigInjecConv;
+ /* Store the new register value */
+ ADCx->CR2 = tmpreg;
+}
+
+/*******************************************************************************
+* Function Name : ADC_ExternalTrigInjectedConvCmd
+* Description : Enables or disables the ADCx injected channels conversion
+* through external trigger
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+* - NewState: new state of the selected ADC external trigger
+* start of injected conversion.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC external event selection for injected group */
+ ADCx->CR2 |= CR2_JEXTTRIG_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC external event selection for injected group */
+ ADCx->CR2 &= CR2_JEXTTRIG_Reset;
+ }
+}
+
+/*******************************************************************************
+* Function Name : ADC_SoftwareStartInjectedConvCmd
+* Description : Enables or disables the start of the injected channels conversion.
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+* - NewState: new state of the selected ADC software start
+* injected conversion.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC external event selection for injected group */
+ /* Starts the selected ADC injected conversion */
+ ADCx->CR2 |= CR2_JEXTTRIG_JSWSTRT_Set;
+ }
+ else
+ {
+ /* Stops the selected ADC injected conversion */
+ /* Disable the selected ADC external event selection for injected group */
+ ADCx->CR2 &= CR2_JEXTTRIG_JSWSTRT_Reset;
+ }
+}
+
+/*******************************************************************************
+* Function Name : ADC_GetSoftwareStartInjectedConvCmdStatus
+* Description : Gets the ADC Software start injected conversion Status.
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+* Output : None
+* Return : The new state of ADC software start injected conversion (SET or RESET).
+*******************************************************************************/
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx)
+{
+ FlagStatus bitstatus = RESET;
+
+ /* Check the status of JSWSTRT bit */
+ if ((ADCx->CR2 & CR2_JSWSTRT_Set) != (u32)RESET)
+ {
+ /* JSWSTRT bit is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* JSWSTRT bit is reset */
+ bitstatus = RESET;
+ }
+ /* Return the JSWSTRT bit status */
+ return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name : ADC_InjectedChannelConfig
+* Description : Configures for the selected ADC injected channel its corresponding
+* rank in the sequencer and its sample time.
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+* - ADC_Channel: the ADC channel to configure.
+* This parameter can be one of the following values:
+* - ADC_Channel_0: ADC Channel0 selected
+* - ADC_Channel_1: ADC Channel1 selected
+* - ADC_Channel_2: ADC Channel2 selected
+* - ADC_Channel_3: ADC Channel3 selected
+* - ADC_Channel_4: ADC Channel4 selected
+* - ADC_Channel_5: ADC Channel5 selected
+* - ADC_Channel_6: ADC Channel6 selected
+* - ADC_Channel_7: ADC Channel7 selected
+* - ADC_Channel_8: ADC Channel8 selected
+* - ADC_Channel_9: ADC Channel9 selected
+* - ADC_Channel_10: ADC Channel10 selected
+* - ADC_Channel_11: ADC Channel11 selected
+* - ADC_Channel_12: ADC Channel12 selected
+* - ADC_Channel_13: ADC Channel13 selected
+* - ADC_Channel_14: ADC Channel14 selected
+* - ADC_Channel_15: ADC Channel15 selected
+* - ADC_Channel_16: ADC Channel16 selected
+* - ADC_Channel_17: ADC Channel17 selected
+* - Rank: The rank in the injected group sequencer. This parameter
+* must be between 1 to 4.
+* - ADC_SampleTime: The sample time value to be set for the
+* selected channel.
+* This parameter can be one of the following values:
+* - ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles
+* - ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles
+* - ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles
+* - ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles
+* - ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles
+* - ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles
+* - ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles
+* - ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles
+* Output : None
+* Return : None
+*******************************************************************************/
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime)
+{
+ u32 tmpreg1 = 0, tmpreg2 = 0;
+ u8 tmpreg3 = 0;
+
+ /* Check the parameters */
+ assert(IS_ADC_CHANNEL(ADC_Channel));
+ assert(IS_ADC_INJECTED_RANK(Rank));
+ assert(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
+
+ /* if ADC_Channel_10 ... ADC_Channel_17 is selected */
+ if (ADC_Channel > ADC_Channel_9)
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SMPR1;
+ /* Calculate the mask to clear */
+ tmpreg2 = (u32)SMPR1_SMP_Set << (3*(ADC_Channel - 10));
+ /* Clear the old discontinuous mode channel count */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (u32)ADC_SampleTime << (3*(ADC_Channel - 10));
+ /* Set the discontinuous mode channel count */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SMPR1 = tmpreg1;
+ }
+ else /* ADC_Channel include in ADC_Channel_[0..9] */
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SMPR2;
+ /* Calculate the mask to clear */
+ tmpreg2 = (u32)SMPR2_SMP_Set << (3 * ADC_Channel);
+ /* Clear the old discontinuous mode channel count */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (u32)ADC_SampleTime << (3 * ADC_Channel);
+ /* Set the discontinuous mode channel count */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SMPR2 = tmpreg1;
+ }
+
+ /* Rank configuration */
+ /* Get the old register value */
+ tmpreg1 = ADCx->JSQR;
+ /* Get JL value: Number = JL+1 */
+ tmpreg3 = (u8)((tmpreg1 & (u32)~JSQR_JL_Reset)>> 20);
+ /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */
+ tmpreg2 = (u32)JSQR_JSQ_Set << (5 * ((Rank + 3) - (tmpreg3 + 1)));
+ /* Clear the old JSQx bits for the selected rank */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */
+ tmpreg2 = (u32)ADC_Channel << (5 * ((Rank + 3) - (tmpreg3 + 1)));
+ /* Set the JSQx bits for the selected rank */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->JSQR = tmpreg1;
+}
+
+/*******************************************************************************
+* Function Name : ADC_InjectedSequencerLengthConfig
+* Description : Configures the sequencer for injected channels
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+* - Length: The sequencer length.
+* This parameter must be a number between 1 to 4.
+* Output : None
+* Return : None
+*******************************************************************************/
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, u8 Length)
+{
+ u32 tmpreg1 = 0;
+ u8 tmpreg2 = 0;
+
+ /* Check the parameters */
+ assert(IS_ADC_INJECTED_LENGTH(Length));
+
+ /* Get the old register value */
+ tmpreg1 = ADCx->JSQR;
+ /* Clear the old injected sequnence lenght JL bits */
+ tmpreg1 &= JSQR_JL_Reset;
+ /* Set the injected sequnence lenght JL bits */
+ tmpreg2 = Length - 1;
+ tmpreg1 |= (u32)tmpreg2 << 20;
+ /* Store the new register value */
+ ADCx->JSQR = tmpreg1;
+}
+
+/*******************************************************************************
+* Function Name : ADC_SetInjectedOffset
+* Description : Set the injected channels conversion value offset
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+* - ADC_InjectedChannel: the ADC injected channel to set its
+* offset.
+* This parameter can be one of the following values:
+* - ADC_InjectedChannel_1: Injected Channel1 selected
+* - ADC_InjectedChannel_2: Injected Channel2 selected
+* - ADC_InjectedChannel_3: Injected Channel3 selected
+* - ADC_InjectedChannel_4: Injected Channel4 selected
+* Output : None
+* Return : None
+*******************************************************************************/
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel, u16 Offset)
+{
+ /* Check the parameters */
+ assert(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
+ assert(IS_ADC_OFFSET(Offset));
+
+ /* Set the selected injected channel data offset */
+ *((u32 *)((*(u32*)&ADCx) + ADC_InjectedChannel)) = (u32)Offset;
+}
+
+/*******************************************************************************
+* Function Name : ADC_GetInjectedConversionValue
+* Description : Returns the ADC conversion result data for the selected
+* injected channel
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+* - ADC_InjectedChannel: the converted ADC injected channel.
+* This parameter can be one of the following values:
+* - ADC_InjectedChannel_1: Injected Channel1 selected
+* - ADC_InjectedChannel_2: Injected Channel2 selected
+* - ADC_InjectedChannel_3: Injected Channel3 selected
+* - ADC_InjectedChannel_4: Injected Channel4 selected
+* Output : None
+* Return : The Data conversion value.
+*******************************************************************************/
+u16 ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel)
+{
+ /* Check the parameters */
+ assert(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
+
+ /* Returns the selected injected channel conversion data value */
+ return (u16) (*(u32*) (((*(u32*)&ADCx) + ADC_InjectedChannel + JDR_Offset)));
+}
+
+/*******************************************************************************
+* Function Name : ADC_AnalogWatchdogCmd
+* Description : Enables or disables the analog watchdog on single/all regular
+* or injected channels
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+* - ADC_AnalogWatchdog: the ADC analog watchdog configuration.
+* This parameter can be one of the following values:
+* - ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on
+* a single regular channel
+* - ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on
+* a single injected channel
+* - ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog
+* watchdog on a single regular or injected channel
+* - ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on
+* all regular channel
+* - ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on
+* all injected channel
+* - ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog
+* on all regular and injected channels
+* - ADC_AnalogWatchdog_None: No channel guarded by the
+* analog watchdog
+* Output : None
+* Return : None
+*******************************************************************************/
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, u32 ADC_AnalogWatchdog)
+{
+ u32 tmpreg = 0;
+
+ /* Check the parameters */
+ assert(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));
+
+ /* Get the old register value */
+ tmpreg = ADCx->CR1;
+ /* Clear AWDEN, AWDENJ and AWDSGL bits */
+ tmpreg &= CR1_AWDMode_Reset;
+ /* Set the analog watchdog enable mode */
+ tmpreg |= ADC_AnalogWatchdog;
+ /* Store the new register value */
+ ADCx->CR1 = tmpreg;
+}
+
+/*******************************************************************************
+* Function Name : ADC_AnalogWatchdogThresholdsConfig
+* Description : Configures the High and low thresholds of the analog watchdog.
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+* - HighThreshold: the ADC analog watchdog High threshold value.
+* This parameter must be a 12bit value.
+* - LowThreshold: the ADC analog watchdog Low threshold value.
+* This parameter must be a 12bit value.
+* Output : None
+* Return : None
+*******************************************************************************/
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, u16 HighThreshold,
+ u16 LowThreshold)
+{
+ /* Check the parameters */
+ assert(IS_ADC_THRESHOLD(HighThreshold));
+ assert(IS_ADC_THRESHOLD(LowThreshold));
+
+ /* Set the ADCx high threshold */
+ ADCx->HTR = HighThreshold;
+ /* Set the ADCx low threshold */
+ ADCx->LTR = LowThreshold;
+}
+
+/*******************************************************************************
+* Function Name : ADC_AnalogWatchdogSingleChannelConfig
+* Description : Configures the analog watchdog guarded single channel
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+* - ADC_Channel: the ADC channel to configure for the analog
+* watchdog.
+* This parameter can be one of the following values:
+* - ADC_Channel_0: ADC Channel0 selected
+* - ADC_Channel_1: ADC Channel1 selected
+* - ADC_Channel_2: ADC Channel2 selected
+* - ADC_Channel_3: ADC Channel3 selected
+* - ADC_Channel_4: ADC Channel4 selected
+* - ADC_Channel_5: ADC Channel5 selected
+* - ADC_Channel_6: ADC Channel6 selected
+* - ADC_Channel_7: ADC Channel7 selected
+* - ADC_Channel_8: ADC Channel8 selected
+* - ADC_Channel_9: ADC Channel9 selected
+* - ADC_Channel_10: ADC Channel10 selected
+* - ADC_Channel_11: ADC Channel11 selected
+* - ADC_Channel_12: ADC Channel12 selected
+* - ADC_Channel_13: ADC Channel13 selected
+* - ADC_Channel_14: ADC Channel14 selected
+* - ADC_Channel_15: ADC Channel15 selected
+* - ADC_Channel_16: ADC Channel16 selected
+* - ADC_Channel_17: ADC Channel17 selected
+* Output : None
+* Return : None
+*******************************************************************************/
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel)
+{
+ u32 tmpreg = 0;
+
+ /* Check the parameters */
+ assert(IS_ADC_CHANNEL(ADC_Channel));
+
+ /* Get the old register value */
+ tmpreg = ADCx->CR1;
+ /* Clear the Analog watchdog channel select bits */
+ tmpreg &= CR1_AWDCH_Reset;
+ /* Set the Analog watchdog channel */
+ tmpreg |= ADC_Channel;
+ /* Store the new register value */
+ ADCx->CR1 = tmpreg;
+}
+
+/*******************************************************************************
+* Function Name : ADC_TempSensorCmd
+* Description : Enables or disables the temperature sensor.
+* Input : - NewState: new state of the temperature sensor.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void ADC_TempSensorCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the temperature sensor */
+ ADC1->CR2 |= CR2_TSPD_Set;
+ }
+ else
+ {
+ /* Disable the temperature sensor */
+ ADC1->CR2 &= CR2_TSPD_Reset;
+ }
+}
+
+/*******************************************************************************
+* Function Name : ADC_GetFlagStatus
+* Description : Checks whether the specified ADC flag is set or not.
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+* - ADC_FLAG: specifies the flag to check.
+* This parameter can be one of the following values:
+* - ADC_FLAG_AWD: Analog watchdog flag
+* - ADC_FLAG_EOC: End of conversion flag
+* - ADC_FLAG_JEOC: End of injected group conversion flag
+* - ADC_FLAG_JSTRT: Start of injected group conversion flag
+* - ADC_FLAG_STRT: Start of regular group conversion flag
+* Output : None
+* Return : The new state of ADC_FLAG (SET or RESET).
+*******************************************************************************/
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, u8 ADC_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert(IS_ADC_GET_FLAG(ADC_FLAG));
+
+ /* Check the status of the specified ADC flag */
+ if ((ADCx->SR & ADC_FLAG) != (u8)RESET)
+ {
+ /* ADC_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* ADC_FLAG is reset */
+ bitstatus = RESET;
+ }
+ /* Return the ADC_FLAG status */
+ return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name : ADC_ClearFlag
+* Description : Clears the ADCx's pending flags.
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+* - ADC_FLAG: specifies the flag to clear.
+* This parameter can be any combination of the following values:
+* - ADC_FLAG_AWD: Analog watchdog flag
+* - ADC_FLAG_EOC: End of conversion flag
+* - ADC_FLAG_JEOC: End of injected group conversion flag
+* - ADC_FLAG_JSTRT: Start of injected group conversion flag
+* - ADC_FLAG_STRT: Start of regular group conversion flag
+* Output : None
+* Return : None
+*******************************************************************************/
+void ADC_ClearFlag(ADC_TypeDef* ADCx, u8 ADC_FLAG)
+{
+ /* Check the parameters */
+ assert(IS_ADC_CLEAR_FLAG(ADC_FLAG));
+
+ /* Clear the selected ADC flags */
+ ADCx->SR &= ~(u32)ADC_FLAG;
+}
+
+/*******************************************************************************
+* Function Name : ADC_GetITStatus
+* Description : Checks whether the specified ADC interrupt has occurred or not.
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+* - ADC_IT: specifies the ADC interrupt source to check.
+* This parameter can be one of the following values:
+* - ADC_IT_EOC: End of conversion interrupt mask
+* - ADC_IT_AWD: Analog watchdog interrupt mask
+* - ADC_IT_JEOC: End of injected conversion interrupt mask
+* Output : None
+* Return : The new state of ADC_IT (SET or RESET).
+*******************************************************************************/
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, u16 ADC_IT)
+{
+ ITStatus bitstatus = RESET;
+ u8 itmask = 0, enablestatus;
+
+ /* Check the parameters */
+ assert(IS_ADC_GET_IT(ADC_IT));
+
+ /* Get the ADC IT index */
+ itmask = (u8)(ADC_IT >> 8);
+
+ /* Get the ADC_IT enable bit status */
+ enablestatus = (ADCx->CR1 & (u8)ADC_IT) ;
+
+ /* Check the status of the specified ADC interrupt */
+ if (((ADCx->SR & itmask) != (u8)RESET) && enablestatus)
+ {
+ /* ADC_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* ADC_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the ADC_IT status */
+ return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name : ADC_ClearITPendingBit
+* Description : Clears the ADCs interrupt pending bits.
+* Input : - ADC_IT: specifies the ADC interrupt pending bit to clear.
+* This parameter can be any combination of the following values:
+* - ADC_IT_EOC: End of conversion interrupt mask
+* - ADC_IT_AWD: Analog watchdog interrupt mask
+* - ADC_IT_JEOC: End of injected conversion interrupt mask
+* Output : None
+* Return : None
+*******************************************************************************/
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, u16 ADC_IT)
+{
+ u8 itmask = 0;
+
+ /* Check the parameters */
+ assert(IS_ADC_IT(ADC_IT));
+
+ /* Get the ADC IT index */
+ itmask = (u8)(ADC_IT >> 8);
+
+ /* Clear the selected ADC interrupt pending bits */
+ ADCx->SR &= ~(u32)itmask;
+}
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_bkp.c b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_bkp.c
new file mode 100644
index 0000000..a8616e0
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_bkp.c
@@ -0,0 +1,263 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_bkp.c
+* Author : MCD Application Team
+* Date First Issued : 09/29/2006
+* Description : This file provides all the BKP firmware functions.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_bkp.h"
+#include "stm32f10x_rcc.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* ------------ BKP registers bit address in the alias region ----------- */
+#define BKP_OFFSET (BKP_BASE - PERIPH_BASE)
+
+/* --- RTCCR Register ---*/
+/* Alias word address of CCO bit */
+#define RTCCR_OFFSET (BKP_OFFSET + 0x2C)
+#define CCO_BitNumber 0x07
+#define RTCCR_CCO_BB (PERIPH_BB_BASE + (RTCCR_OFFSET * 32) + (CCO_BitNumber * 4))
+
+/* --- CR Register ---*/
+/* Alias word address of TPAL bit */
+#define CR_OFFSET (BKP_OFFSET + 0x30)
+#define TPAL_BitNumber 0x01
+#define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4))
+
+/* Alias word address of TPE bit */
+#define TPE_BitNumber 0x00
+#define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4))
+
+/* --- CSR Register ---*/
+/* Alias word address of TPIE bit */
+#define CSR_OFFSET (BKP_OFFSET + 0x34)
+#define TPIE_BitNumber 0x02
+#define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4))
+
+/* Alias word address of TIF bit */
+#define TIF_BitNumber 0x09
+#define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4))
+
+/* Alias word address of TEF bit */
+#define TEF_BitNumber 0x08
+#define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4))
+
+
+/* ---------------------- BKP registers bit mask ------------------------ */
+/* RTCCR register bit mask */
+#define RTCCR_CAL_Mask ((u16)0xFF80)
+
+/* CSR register bit mask */
+#define CSR_CTE_Set ((u16)0x0001)
+#define CSR_CTI_Set ((u16)0x0002)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name : BKP_DeInit
+* Description : Deinitializes the BKP peripheral registers to their default
+* reset values.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void BKP_DeInit(void)
+{
+ RCC_BackupResetCmd(ENABLE);
+ RCC_BackupResetCmd(DISABLE);
+}
+
+/*******************************************************************************
+* Function Name : BKP_TamperPinLevelConfig
+* Description : Configures the Tamper Pin active level.
+* Input : - BKP_TamperPinLevel: specifies the Tamper Pin active level.
+* This parameter can be one of the following values:
+* - BKP_TamperPinLevel_High: Tamper pin active on high level
+* - BKP_TamperPinLevel_Low: Tamper pin active on low level
+* Output : None
+* Return : None
+*******************************************************************************/
+void BKP_TamperPinLevelConfig(u16 BKP_TamperPinLevel)
+{
+ /* Check the parameters */
+ assert(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel));
+
+ *(vu32 *) CR_TPAL_BB = BKP_TamperPinLevel;
+}
+
+/*******************************************************************************
+* Function Name : BKP_TamperPinCmd
+* Description : Enables or disables the Tamper Pin activation.
+* Input : - NewState: new state of the Tamper Pin activation.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void BKP_TamperPinCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ *(vu32 *) CR_TPE_BB = (u32)NewState;
+}
+
+/*******************************************************************************
+* Function Name : BKP_ITConfig
+* Description : Enables or disables the Tamper Pin Interrupt.
+* Input : - NewState: new state of the Tamper Pin Interrupt.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void BKP_ITConfig(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ *(vu32 *) CSR_TPIE_BB = (u32)NewState;
+}
+
+/*******************************************************************************
+* Function Name : BKP_RTCCalibrationClockOutputCmd
+* Description : Enables or disables the output of the Calibration Clock.
+* Input : - NewState: new state of the Calibration Clock output.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void BKP_RTCCalibrationClockOutputCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ *(vu32 *) RTCCR_CCO_BB = (u32)NewState;
+}
+
+/*******************************************************************************
+* Function Name : BKP_SetRTCCalibrationValue
+* Description : Sets RTC Clock Calibration value.
+* Input : - CalibrationValue: specifies the RTC Clock Calibration value.
+* This parameter must be a number between 0 and 0x7F.
+* Output : None
+* Return : None
+*******************************************************************************/
+void BKP_SetRTCCalibrationValue(u8 CalibrationValue)
+{
+ u16 tmpreg = 0;
+
+ /* Check the parameters */
+ assert(IS_BKP_CALIBRATION_VALUE(CalibrationValue));
+
+ tmpreg = BKP->RTCCR;
+
+ /* Clear CAL[6:0] bits */
+ tmpreg &= RTCCR_CAL_Mask;
+
+ /* Set CAL[6:0] bits according to CalibrationValue value */
+ tmpreg |= CalibrationValue;
+
+ /* Store the new value */
+ BKP->RTCCR = tmpreg;
+}
+
+/*******************************************************************************
+* Function Name : BKP_WriteBackupRegister
+* Description : Writes user data to the specified Data Backup Register.
+* Input : - BKP_DR: specifies the Data Backup Register.
+* This parameter can be BKP_DRx where x:[1, 10]
+* - Data: data to write
+* Output : None
+* Return : None
+*******************************************************************************/
+void BKP_WriteBackupRegister(u16 BKP_DR, u16 Data)
+{
+ /* Check the parameters */
+ assert(IS_BKP_DR(BKP_DR));
+
+ *(vu16 *) (BKP_BASE + BKP_DR) = Data;
+}
+
+/*******************************************************************************
+* Function Name : BKP_ReadBackupRegister
+* Description : Reads data from the specified Data Backup Register.
+* Input : - BKP_DR: specifies the Data Backup Register.
+* This parameter can be BKP_DRx where x:[1, 10]
+* Output : None
+* Return : The content of the specified Data Backup Register
+*******************************************************************************/
+u16 BKP_ReadBackupRegister(u16 BKP_DR)
+{
+ /* Check the parameters */
+ assert(IS_BKP_DR(BKP_DR));
+
+ return (*(vu16 *) (BKP_BASE + BKP_DR));
+}
+
+/*******************************************************************************
+* Function Name : BKP_GetFlagStatus
+* Description : Checks whether the Tamper Pin Event flag is set or not.
+* Input : None
+* Output : None
+* Return : The new state of the Tamper Pin Event flag (SET or RESET).
+*******************************************************************************/
+FlagStatus BKP_GetFlagStatus(void)
+{
+ return (FlagStatus)(*(vu32 *) CSR_TEF_BB);
+}
+
+/*******************************************************************************
+* Function Name : BKP_ClearFlag
+* Description : Clears Tamper Pin Event pending flag.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void BKP_ClearFlag(void)
+{
+ /* Set CTE bit to clear Tamper Pin Event flag */
+ BKP->CSR |= CSR_CTE_Set;
+}
+
+/*******************************************************************************
+* Function Name : BKP_GetITStatus
+* Description : Checks whether the Tamper Pin Interrupt has occurred or not.
+* Input : None
+* Output : None
+* Return : The new state of the Tamper Pin Interrupt (SET or RESET).
+*******************************************************************************/
+ITStatus BKP_GetITStatus(void)
+{
+ return (ITStatus)(*(vu32 *) CSR_TIF_BB);
+}
+
+/*******************************************************************************
+* Function Name : BKP_ClearITPendingBit
+* Description : Clears Tamper Pin Interrupt pending bit.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void BKP_ClearITPendingBit(void)
+{
+ /* Set CTI bit to clear Tamper Pin Interrupt pending bit */
+ BKP->CSR |= CSR_CTI_Set;
+}
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_can.c b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_can.c
new file mode 100644
index 0000000..3457f0d
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_can.c
@@ -0,0 +1,873 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_can.c
+* Author : MCD Application Team
+* Date First Issued : 09/29/2006
+* Description : This file provides all the CAN firmware functions.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_can.h"
+#include "stm32f10x_rcc.h"
+
+/* Private typedef -----------------------------------------------------------*/
+
+/* Private define ------------------------------------------------------------*/
+/* CAN Master Control Register bits */
+#define CAN_MCR_INRQ ((u32)0x00000001) /* Initialization request */
+#define CAN_MCR_SLEEP ((u32)0x00000002) /* Sleep mode request */
+#define CAN_MCR_TXFP ((u32)0x00000004) /* Transmit FIFO priority */
+#define CAN_MCR_RFLM ((u32)0x00000008) /* Receive FIFO locked mode */
+#define CAN_MCR_NART ((u32)0x00000010) /* No automatic retransmission */
+#define CAN_MCR_AWUM ((u32)0x00000020) /* Automatic wake up mode */
+#define CAN_MCR_ABOM ((u32)0x00000040) /* Automatic bus-off management */
+#define CAN_MCR_TTCM ((u32)0x00000080) /* time triggered communication */
+
+/* CAN Master Status Register bits */
+#define CAN_MSR_INAK ((u32)0x00000001) /* Initialization acknowledge */
+#define CAN_MSR_WKUI ((u32)0x00000008) /* Wake-up interrupt */
+#define CAN_MSR_SLAKI ((u32)0x00000010) /* Sleep acknowledge interrupt */
+
+/* CAN Transmit Status Register bits */
+#define CAN_TSR_RQCP0 ((u32)0x00000001) /* Request completed mailbox0 */
+#define CAN_TSR_TXOK0 ((u32)0x00000002) /* Transmission OK of mailbox0 */
+#define CAN_TSR_ABRQ0 ((u32)0x00000080) /* Abort request for mailbox0 */
+#define CAN_TSR_RQCP1 ((u32)0x00000100) /* Request completed mailbox1 */
+#define CAN_TSR_TXOK1 ((u32)0x00000200) /* Transmission OK of mailbox1 */
+#define CAN_TSR_ABRQ1 ((u32)0x00008000) /* Abort request for mailbox1 */
+#define CAN_TSR_RQCP2 ((u32)0x00010000) /* Request completed mailbox2 */
+#define CAN_TSR_TXOK2 ((u32)0x00020000) /* Transmission OK of mailbox2 */
+#define CAN_TSR_ABRQ2 ((u32)0x00800000) /* Abort request for mailbox2 */
+#define CAN_TSR_TME0 ((u32)0x04000000) /* Transmit mailbox 0 empty */
+#define CAN_TSR_TME1 ((u32)0x08000000) /* Transmit mailbox 1 empty */
+#define CAN_TSR_TME2 ((u32)0x10000000) /* Transmit mailbox 2 empty */
+
+/* CAN Receive FIFO 0 Register bits */
+#define CAN_RF0R_FULL0 ((u32)0x00000008) /* FIFO 0 full */
+#define CAN_RF0R_FOVR0 ((u32)0x00000010) /* FIFO 0 overrun */
+#define CAN_RF0R_RFOM0 ((u32)0x00000020) /* Release FIFO 0 output mailbox */
+
+/* CAN Receive FIFO 1 Register bits */
+#define CAN_RF1R_FULL1 ((u32)0x00000008) /* FIFO 1 full */
+#define CAN_RF1R_FOVR1 ((u32)0x00000010) /* FIFO 1 overrun */
+#define CAN_RF1R_RFOM1 ((u32)0x00000020) /* Release FIFO 1 output mailbox */
+
+/* CAN Error Status Register bits */
+#define CAN_ESR_EWGF ((u32)0x00000001) /* Error warning flag */
+#define CAN_ESR_EPVF ((u32)0x00000002) /* Error passive flag */
+#define CAN_ESR_BOFF ((u32)0x00000004) /* Bus-off flag */
+
+/* CAN Mailbox Transmit Request */
+#define CAN_TMIDxR_TXRQ ((u32)0x00000001) /* Transmit mailbox request */
+
+/* CAN Filter Master Register bits */
+#define CAN_FMR_FINIT ((u32)0x00000001) /* Filter init mode */
+
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static ITStatus CheckITStatus(u32 CAN_Reg, u32 It_Bit);
+
+/* Private functions ---------------------------------------------------------*/
+/*******************************************************************************
+* Function Name : CAN_DeInit
+* Description : Deinitializes the CAN peripheral registers to their default
+* reset values.
+* Input : None.
+* Output : None.
+* Return : None.
+*******************************************************************************/
+void CAN_DeInit(void)
+{
+ /* Enable CAN reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN, ENABLE);
+ /* Release CAN from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN, DISABLE);
+}
+
+/*******************************************************************************
+* Function Name : CAN_Init
+* Description : Initializes the CAN peripheral according to the specified
+* parameters in the CAN_InitStruct.
+* Input : CAN_InitStruct: pointer to a CAN_InitTypeDef structure that
+ contains the configuration information for the CAN peripheral.
+* Output : None.
+* Return : Constant indicates initialization succeed which will be
+* CANINITFAILED or CANINITOK.
+*******************************************************************************/
+u8 CAN_Init(CAN_InitTypeDef* CAN_InitStruct)
+{
+ u8 InitStatus = 0;
+
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM));
+ assert(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM));
+ assert(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM));
+ assert(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART));
+ assert(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM));
+ assert(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP));
+ assert(IS_CAN_MODE(CAN_InitStruct->CAN_Mode));
+ assert(IS_CAN_SJW(CAN_InitStruct->CAN_SJW));
+ assert(IS_CAN_BS1(CAN_InitStruct->CAN_BS1));
+ assert(IS_CAN_BS2(CAN_InitStruct->CAN_BS2));
+ assert(IS_CAN_CLOCK(CAN_InitStruct->CAN_Clock));
+ assert(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler));
+
+ /* Request initialisation */
+ CAN->MCR = CAN_MCR_INRQ;
+
+ /* ...and check acknowledged */
+ if ((CAN->MSR & CAN_MSR_INAK) == 0)
+ {
+ InitStatus = CANINITFAILED;
+ }
+ else
+ {
+ /* Set the time triggered communication mode */
+ if (CAN_InitStruct->CAN_TTCM == ENABLE)
+ {
+ CAN->MCR |= CAN_MCR_TTCM;
+ }
+ else
+ {
+ CAN->MCR &= ~CAN_MCR_TTCM;
+ }
+
+ /* Set the automatic bus-off management */
+ if (CAN_InitStruct->CAN_ABOM == ENABLE)
+ {
+ CAN->MCR |= CAN_MCR_ABOM;
+ }
+ else
+ {
+ CAN->MCR &= ~CAN_MCR_ABOM;
+ }
+
+ /* Set the automatic wake-up mode */
+ if (CAN_InitStruct->CAN_AWUM == ENABLE)
+ {
+ CAN->MCR |= CAN_MCR_AWUM;
+ }
+ else
+ {
+ CAN->MCR &= ~CAN_MCR_AWUM;
+ }
+
+ /* Set the no automatic retransmission */
+ if (CAN_InitStruct->CAN_NART == ENABLE)
+ {
+ CAN->MCR |= CAN_MCR_NART;
+ }
+ else
+ {
+ CAN->MCR &= ~CAN_MCR_NART;
+ }
+
+ /* Set the receive FIFO locked mode */
+ if (CAN_InitStruct->CAN_RFLM == ENABLE)
+ {
+ CAN->MCR |= CAN_MCR_RFLM;
+ }
+ else
+ {
+ CAN->MCR &= ~CAN_MCR_RFLM;
+ }
+
+ /* Set the transmit FIFO priority */
+ if (CAN_InitStruct->CAN_TXFP == ENABLE)
+ {
+ CAN->MCR |= CAN_MCR_TXFP;
+ }
+ else
+ {
+ CAN->MCR &= ~CAN_MCR_TXFP;
+ }
+
+ /* Set the bit timing register */
+ CAN->BTR = (u32)((u32)CAN_InitStruct->CAN_Mode << 30) | ((u32)CAN_InitStruct->CAN_SJW << 24) |
+ ((u32)CAN_InitStruct->CAN_BS1 << 16) | ((u32)CAN_InitStruct->CAN_BS2 << 20) |
+ ((u32)CAN_InitStruct->CAN_Clock << 15) | ((u32)CAN_InitStruct->CAN_Prescaler - 1);
+
+ InitStatus = CANINITOK;
+
+ /* Request leave initialisation */
+ CAN->MCR &= ~CAN_MCR_INRQ;
+
+ /* ...and check acknowledged */
+ if ((CAN->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
+ {
+ InitStatus = CANINITFAILED;
+ }
+ }
+
+ /* At this step, return the status of initialization */
+ return InitStatus;
+}
+
+/*******************************************************************************
+* Function Name : CAN_FilterInit
+* Description : Initializes the CAN peripheral according to the specified
+* parameters in the CAN_FilterInitStruct.
+* Input : CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef
+* structure that contains the configuration information.
+* Output : None.
+* Return : None.
+*******************************************************************************/
+void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct)
+{
+ u16 FilterNumber_BitPos = 0;
+
+ /* Check the parameters */
+ assert(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber));
+ assert(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode));
+ assert(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale));
+ assert(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment));
+ assert(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation));
+
+ FilterNumber_BitPos = (u16)((u16)0x0001 << ((u16)CAN_FilterInitStruct->CAN_FilterNumber));
+
+ /* Initialisation mode for the filter */
+ CAN->FMR |= CAN_FMR_FINIT;
+
+ /* Filter Deactivation */
+ CAN->FA0R &= ~(u32)FilterNumber_BitPos;
+
+ /* Filter Scale */
+ if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit)
+ {
+ /* 16-bit scale for the filter */
+ CAN->FS0R &= ~(u32)FilterNumber_BitPos;
+
+ /* First 16-bit identifier and First 16-bit mask */
+ /* Or First 16-bit identifier and Second 16-bit identifier */
+ CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR0 = ((u32)((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) |
+ ((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterIdLow);
+
+ /* Second 16-bit identifier and Second 16-bit mask */
+ /* Or Third 16-bit identifier and Fourth 16-bit identifier */
+ CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = ((u32)((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
+ ((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterIdHigh);
+ }
+ if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit)
+ {
+ /* 32-bit scale for the filter */
+ CAN->FS0R |= FilterNumber_BitPos;
+
+ /* 32-bit identifier or First 32-bit identifier */
+ CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR0 = ((u32)((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) |
+ ((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterIdLow);
+
+ /* 32-bit mask or Second 32-bit identifier */
+ CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = ((u32)((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
+ ((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterMaskIdLow);
+
+ }
+
+ /* Filter Mode */
+ if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask)
+ {
+ /*Id/Mask mode for the filter*/
+ CAN->FM0R &= ~(u32)FilterNumber_BitPos;
+ }
+ else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
+ {
+ /*Identifier list mode for the filter*/
+ CAN->FM0R |= (u32)FilterNumber_BitPos;
+ }
+
+ /* Filter FIFO assignment */
+ if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO0)
+ {
+ /* FIFO 0 assignation for the filter */
+ CAN->FFA0R &= ~(u32)FilterNumber_BitPos;
+ }
+ if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO1)
+ {
+ /* FIFO 1 assignation for the filter */
+ CAN->FFA0R |= (u32)FilterNumber_BitPos;
+ }
+
+ /* Filter activation */
+ if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE)
+ {
+ CAN->FA0R |= FilterNumber_BitPos;
+ }
+
+ /* Leave the initialisation mode for the filter */
+ CAN->FMR &= ~CAN_FMR_FINIT;
+}
+
+/*******************************************************************************
+* Function Name : CAN_StructInit
+* Description : Fills each CAN_InitStruct member with its default value.
+* Input : CAN_InitStruct: pointer to a CAN_InitTypeDef structure which
+* will be initialized.
+* Output : None.
+* Return : None.
+*******************************************************************************/
+void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct)
+{
+ /* Reset CAN init structure parameters values */
+
+ /* Initialize the time triggered communication mode */
+ CAN_InitStruct->CAN_TTCM = DISABLE;
+
+ /* Initialize the automatic bus-off management */
+ CAN_InitStruct->CAN_ABOM = DISABLE;
+
+ /* Initialize the automatic wake-up mode */
+ CAN_InitStruct->CAN_AWUM = DISABLE;
+
+ /* Initialize the no automatic retransmission */
+ CAN_InitStruct->CAN_NART = DISABLE;
+
+ /* Initialize the receive FIFO locked mode */
+ CAN_InitStruct->CAN_RFLM = DISABLE;
+
+ /* Initialize the transmit FIFO priority */
+ CAN_InitStruct->CAN_TXFP = DISABLE;
+
+ /* Initialize the CAN_Mode member */
+ CAN_InitStruct->CAN_Mode = CAN_Mode_Normal;
+
+ /* Initialize the CAN_SJW member */
+ CAN_InitStruct->CAN_SJW = CAN_SJW_0tq;
+
+ /* Initialize the CAN_BS1 member */
+ CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq;
+
+ /* Initialize the CAN_BS2 member */
+ CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq;
+
+ /* Initialize the CAN_Clock member */
+ CAN_InitStruct->CAN_Clock = CAN_Clock_APB;
+
+ /* Initialize the CAN_Prescaler member */
+ CAN_InitStruct->CAN_Prescaler = 1;
+}
+
+/*******************************************************************************
+* Function Name : CAN_ITConfig
+* Description : Enables or disables the CAN interrupts.
+* Input : - CAN_IT: specifies the CAN interrupt sources to be enabled or
+* disabled.
+* - NewState: new state of the CAN interrupts.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None.
+* Return : None.
+*******************************************************************************/
+void CAN_ITConfig(u32 CAN_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_CAN_IT(CAN_IT));
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected CAN interrupt */
+ CAN->IER |= CAN_IT;
+ }
+ else
+ {
+ /* Disable the selected CAN interrupt */
+ CAN->IER &= ~CAN_IT;
+ }
+}
+
+/*******************************************************************************
+* Function Name : CAN_Transmit
+* Description : Initiates the transmission of a message.
+* Input : TxMessage: pointer to a structure which contains CAN Id, CAN
+* DLC and CAN datas.
+* Output : None.
+* Return : The number of the mailbox that is used for transmission
+* or CAN_NO_MB if there is no empty mailbox.
+*******************************************************************************/
+u8 CAN_Transmit(CanTxMsg* TxMessage)
+{
+ u8 TransmitMailbox = 0;
+
+ /* Check the parameters */
+ assert(IS_CAN_STDID(TxMessage->StdId));
+ assert(IS_CAN_EXTID(TxMessage->StdId));
+ assert(IS_CAN_IDTYPE(TxMessage->IDE));
+ assert(IS_CAN_RTR(TxMessage->RTR));
+ assert(IS_CAN_DLC(TxMessage->DLC));
+
+ /* Select one empty transmit mailbox */
+ if ((CAN->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
+ {
+ TransmitMailbox = 0;
+ }
+ else if ((CAN->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
+ {
+ TransmitMailbox = 1;
+ }
+ else if ((CAN->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
+ {
+ TransmitMailbox = 2;
+ }
+ else
+ {
+ TransmitMailbox = CAN_NO_MB;
+ }
+
+ if (TransmitMailbox != CAN_NO_MB)
+ {
+ /* Set up the Id */
+ TxMessage->StdId &= (u32)0x000007FF;
+ TxMessage->StdId = TxMessage->StdId << 21;
+ TxMessage->ExtId &= (u32)0x0003FFFF;
+ TxMessage->ExtId <<= 3;
+
+ CAN->sTxMailBox[TransmitMailbox].TIR &= CAN_TMIDxR_TXRQ;
+ CAN->sTxMailBox[TransmitMailbox].TIR |= (TxMessage->StdId | TxMessage->ExtId |
+ TxMessage->IDE | TxMessage->RTR);
+
+ /* Set up the DLC */
+ TxMessage->DLC &= (u8)0x0000000F;
+ CAN->sTxMailBox[TransmitMailbox].TDTR &= (u32)0xFFFFFFF0;
+ CAN->sTxMailBox[TransmitMailbox].TDTR |= TxMessage->DLC;
+
+ /* Set up the data field */
+ CAN->sTxMailBox[TransmitMailbox].TDLR = (((u32)TxMessage->Data[3] << 24) | ((u32)TxMessage->Data[2] << 16) |
+ ((u32)TxMessage->Data[1] << 8) | ((u32)TxMessage->Data[0]));
+ CAN->sTxMailBox[TransmitMailbox].TDHR = (((u32)TxMessage->Data[7] << 24) | ((u32)TxMessage->Data[6] << 16) |
+ ((u32)TxMessage->Data[5] << 8) | ((u32)TxMessage->Data[4]));
+
+ /* Request transmission */
+ CAN->sTxMailBox[TransmitMailbox].TIR |= CAN_TMIDxR_TXRQ;
+ }
+
+ return TransmitMailbox;
+}
+
+/*******************************************************************************
+* Function Name : CAN_TransmitStatus
+* Description : Check the transmission of a message.
+* Input : TransmitMailbox: the number of the mailbox that is used for
+* transmission.
+* Output : None.
+* Return : CANTXOK if the CAN driver transmits the message, CANTXFAILED
+* in an other case.
+*******************************************************************************/
+u32 CAN_TransmitStatus(u8 TransmitMailbox)
+{
+ /* RQCP, TXOK and TME bits */
+ u32 State = 0;
+
+ /* Check the parameters */
+ assert(IS_CAN_TRANSMITMAILBOX(TransmitMailbox));
+
+ switch (TransmitMailbox)
+ {
+ case (0): State |= ((CAN->TSR & CAN_TSR_RQCP0) << 2);
+ State |= ((CAN->TSR & CAN_TSR_TXOK0) >> 0);
+ State |= ((CAN->TSR & CAN_TSR_TME0) >> 26);
+ break;
+ case (1): State |= ((CAN->TSR & CAN_TSR_RQCP1) >> 6);
+ State |= ((CAN->TSR & CAN_TSR_TXOK1) >> 8);
+ State |= ((CAN->TSR & CAN_TSR_TME1) >> 27);
+ break;
+ case (2): State |= ((CAN->TSR & CAN_TSR_RQCP2) >> 14);
+ State |= ((CAN->TSR & CAN_TSR_TXOK2) >> 16);
+ State |= ((CAN->TSR & CAN_TSR_TME2) >> 28);
+ break;
+ default:
+ State = CANTXFAILED;
+ break;
+ }
+
+ switch (State)
+ {
+ /* transmit pending */
+ case (0x0): State = CANTXPENDING;
+ break;
+ /* transmit failed */
+ case (0x5): State = CANTXFAILED;
+ break;
+ /* transmit succedeed */
+ case (0x7): State = CANTXOK;
+ break;
+ default:
+ State = CANTXFAILED;
+ break;
+ }
+
+ return State;
+}
+
+/*******************************************************************************
+* Function Name : CAN_CancelTransmit
+* Description : Cancels a transmit request.
+* Input : Mailbox number.
+* Output : None.
+* Return : None.
+*******************************************************************************/
+void CAN_CancelTransmit(u8 Mailbox)
+{
+ /* Check the parameters */
+ assert(IS_CAN_TRANSMITMAILBOX(Mailbox));
+
+ /* abort transmission */
+ switch (Mailbox)
+ {
+ case (0): CAN->TSR |= CAN_TSR_ABRQ0;
+ break;
+ case (1): CAN->TSR |= CAN_TSR_ABRQ1;
+ break;
+ case (2): CAN->TSR |= CAN_TSR_ABRQ2;
+ break;
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name : CAN_FIFORelease
+* Description : Release a FIFO.
+* Input : FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1.
+* Output : None.
+* Return : None.
+*******************************************************************************/
+void CAN_FIFORelease(u8 FIFONumber)
+{
+ /* Check the parameters */
+ assert(IS_CAN_FIFO(FIFONumber));
+
+ /* Release FIFO0 */
+ if (FIFONumber == CAN_FIFO0)
+ {
+ CAN->RF0R = CAN_RF0R_RFOM0;
+ }
+ /* Release FIFO1 */
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ CAN->RF1R = CAN_RF1R_RFOM1;
+ }
+}
+
+/*******************************************************************************
+* Function Name : CAN_MessagePending
+* Description : Return the number of pending messages.
+* Input : FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+* Output : None.
+* Return : NbMessage which is the number of pending message.
+*******************************************************************************/
+u8 CAN_MessagePending(u8 FIFONumber)
+{
+ u8 MessagePending=0;
+
+ /* Check the parameters */
+ assert(IS_CAN_FIFO(FIFONumber));
+
+ if (FIFONumber == CAN_FIFO0)
+ {
+ MessagePending = (u8)(CAN->RF0R&(u32)0x03);
+ }
+ else if (FIFONumber == CAN_FIFO1)
+ {
+ MessagePending = (u8)(CAN->RF1R&(u32)0x03);
+ }
+ else
+ {
+ MessagePending = 0;
+ }
+ return MessagePending;
+}
+
+/*******************************************************************************
+* Function Name : CAN_Receive
+* Description : Receives a message.
+* Input : FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+* Output : RxMessage: pointer to a structure which contains CAN Id,
+* CAN DLC, CAN datas and FMI number.
+* Return : None.
+*******************************************************************************/
+void CAN_Receive(u8 FIFONumber, CanRxMsg* RxMessage)
+{
+ /* Check the parameters */
+ assert(IS_CAN_FIFO(FIFONumber));
+
+ /* Get the Id */
+ RxMessage->StdId = (u32)0x000007FF & (CAN->sFIFOMailBox[FIFONumber].RIR >> 21);
+ RxMessage->ExtId = (u32)0x0003FFFF & (CAN->sFIFOMailBox[FIFONumber].RIR >> 3);
+
+ RxMessage->IDE = (u32)0x00000004 & CAN->sFIFOMailBox[FIFONumber].RIR;
+ RxMessage->RTR = (u32)0x00000002 & CAN->sFIFOMailBox[FIFONumber].RIR;
+
+ /* Get the DLC */
+ RxMessage->DLC = (u32)0x0000000F & CAN->sFIFOMailBox[FIFONumber].RDTR;
+
+ /* Get the FMI */
+ RxMessage->FMI = (u32)0x000000FF & (CAN->sFIFOMailBox[FIFONumber].RDTR >> 8);
+
+ /* Get the data field */
+ RxMessage->Data[0] = (u32)0x000000FF & CAN->sFIFOMailBox[FIFONumber].RDLR;
+ RxMessage->Data[1] = (u32)0x000000FF & (CAN->sFIFOMailBox[FIFONumber].RDLR >> 8);
+ RxMessage->Data[2] = (u32)0x000000FF & (CAN->sFIFOMailBox[FIFONumber].RDLR >> 16);
+ RxMessage->Data[3] = (u32)0x000000FF & (CAN->sFIFOMailBox[FIFONumber].RDLR >> 24);
+
+ RxMessage->Data[4] = (u32)0x000000FF & CAN->sFIFOMailBox[FIFONumber].RDHR;
+ RxMessage->Data[5] = (u32)0x000000FF & (CAN->sFIFOMailBox[FIFONumber].RDHR >> 8);
+ RxMessage->Data[6] = (u32)0x000000FF & (CAN->sFIFOMailBox[FIFONumber].RDHR >> 16);
+ RxMessage->Data[7] = (u32)0x000000FF & (CAN->sFIFOMailBox[FIFONumber].RDHR >> 24);
+
+ /* Release the FIFO */
+ CAN_FIFORelease(FIFONumber);
+}
+
+/*******************************************************************************
+* Function Name : CAN_Sleep
+* Description : Enters the low power mode.
+* Input : None.
+* Output : None.
+* Return : CANSLEEPOK if sleep entered, CANSLEEPFAILED in an other case.
+*******************************************************************************/
+u8 CAN_Sleep(void)
+{
+ u8 SleepStatus = 0;
+
+ /* Sleep mode entering request */
+ CAN->MCR |= CAN_MCR_SLEEP;
+ SleepStatus = CANSLEEPOK;
+
+ /* Sleep mode status */
+ if ((CAN->MCR&CAN_MCR_SLEEP) == 0)
+ {
+ /* Sleep mode not entered */
+ SleepStatus = CANSLEEPFAILED;
+ }
+
+ /* At this step, sleep mode status */
+ return SleepStatus;
+}
+
+/*******************************************************************************
+* Function Name : CAN_WakeUp
+* Description : Wakes the CAN up.
+* Input : None.
+* Output : None.
+* Return : CANWAKEUPOK if sleep mode left, CANWAKEUPFAILED in an other
+* case.
+*******************************************************************************/
+u8 CAN_WakeUp(void)
+{
+ u8 WakeUpStatus = 0;
+
+ /* Wake up request */
+ CAN->MCR &= ~CAN_MCR_SLEEP;
+ WakeUpStatus = CANWAKEUPFAILED;
+
+ /* Sleep mode status */
+ if ((CAN->MCR&CAN_MCR_SLEEP) == 0)
+ {
+ /* Sleep mode exited */
+ WakeUpStatus = CANWAKEUPOK;
+ }
+
+ /* At this step, sleep mode status */
+ return WakeUpStatus;
+}
+
+/*******************************************************************************
+* Function Name : CAN_GetFlagStatus
+* Description : Checks whether the CAN flag is set or not.
+* Input : CAN_FLAG: specifies the flag to check.
+* Output : None.
+* Return : The new state of CAN_FLAG (SET or RESET).
+*******************************************************************************/
+FlagStatus CAN_GetFlagStatus(u32 CAN_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert(IS_CAN_FLAG(CAN_FLAG));
+
+ /* Check the status of the specified CAN flag */
+ if ((CAN->ESR & CAN_FLAG) != (u32)RESET)
+ {
+ /* CAN_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAN_FLAG is reset */
+ bitstatus = RESET;
+ }
+ /* Return the CAN_FLAG status */
+ return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name : CAN_ClearFlag
+* Description : Clears the CAN's pending flags.
+* Input : CAN_FLAG: specifies the flag to clear.
+* Output : None.
+* Return : None.
+*******************************************************************************/
+void CAN_ClearFlag(u32 CAN_FLAG)
+{
+ /* Check the parameters */
+ assert(IS_CAN_FLAG(CAN_FLAG));
+
+ /* Clear the selected CAN flags */
+ CAN->ESR &= ~CAN_FLAG;
+}
+
+/*******************************************************************************
+* Function Name : CAN_GetITStatus
+* Description : Checks whether the CAN interrupt has occurred or not.
+* Input : CAN_IT: specifies the CAN interrupt source to check.
+* Output : None.
+* Return : The new state of CAN_IT (SET or RESET).
+*******************************************************************************/
+ITStatus CAN_GetITStatus(u32 CAN_IT)
+{
+ ITStatus pendingbitstatus = RESET;
+
+ /* Check the parameters */
+ assert(IS_CAN_IT(CAN_IT));
+
+ switch (CAN_IT)
+ {
+ case CAN_IT_RQCP0:
+ pendingbitstatus = CheckITStatus(CAN->TSR, CAN_TSR_RQCP0);
+ break;
+ case CAN_IT_RQCP1:
+ pendingbitstatus = CheckITStatus(CAN->TSR, CAN_TSR_RQCP1);
+ break;
+ case CAN_IT_RQCP2:
+ pendingbitstatus = CheckITStatus(CAN->TSR, CAN_TSR_RQCP2);
+ break;
+ case CAN_IT_FF0:
+ pendingbitstatus = CheckITStatus(CAN->RF0R, CAN_RF0R_FULL0);
+ break;
+ case CAN_IT_FOV0:
+ pendingbitstatus = CheckITStatus(CAN->RF0R, CAN_RF0R_FOVR0);
+ break;
+ case CAN_IT_FF1:
+ pendingbitstatus = CheckITStatus(CAN->RF1R, CAN_RF1R_FULL1);
+ break;
+ case CAN_IT_FOV1:
+ pendingbitstatus = CheckITStatus(CAN->RF1R, CAN_RF1R_FOVR1);
+ break;
+ case CAN_IT_EWG:
+ pendingbitstatus = CheckITStatus(CAN->ESR, CAN_ESR_EWGF);
+ break;
+ case CAN_IT_EPV:
+ pendingbitstatus = CheckITStatus(CAN->ESR, CAN_ESR_EPVF);
+ break;
+ case CAN_IT_BOF:
+ pendingbitstatus = CheckITStatus(CAN->ESR, CAN_ESR_BOFF);
+ break;
+ case CAN_IT_SLK:
+ pendingbitstatus = CheckITStatus(CAN->MSR, CAN_MSR_SLAKI);
+ break;
+ case CAN_IT_WKU:
+ pendingbitstatus = CheckITStatus(CAN->MSR, CAN_MSR_WKUI);
+ break;
+
+ default :
+ pendingbitstatus = RESET;
+ break;
+ }
+
+ /* Return the CAN_IT status */
+ return pendingbitstatus;
+}
+
+/*******************************************************************************
+* Function Name : CAN_ClearITPendingBit
+* Description : Clears the CANs interrupt pending bits.
+* Input : CAN_IT: specifies the interrupt pending bit to clear.
+* Output : None.
+* Return : None.
+*******************************************************************************/
+void CAN_ClearITPendingBit(u32 CAN_IT)
+{
+ /* Check the parameters */
+ assert(IS_CAN_IT(CAN_IT));
+
+ switch (CAN_IT)
+ {
+ case CAN_IT_RQCP0:
+ CAN->TSR = CAN_TSR_RQCP0; /* rc_w1*/
+ break;
+ case CAN_IT_RQCP1:
+ CAN->TSR = CAN_TSR_RQCP1; /* rc_w1*/
+ break;
+ case CAN_IT_RQCP2:
+ CAN->TSR = CAN_TSR_RQCP2; /* rc_w1*/
+ break;
+ case CAN_IT_FF0:
+ CAN->RF0R = CAN_RF0R_FULL0; /* rc_w1*/
+ break;
+ case CAN_IT_FOV0:
+ CAN->RF0R = CAN_RF0R_FOVR0; /* rc_w1*/
+ break;
+ case CAN_IT_FF1:
+ CAN->RF1R = CAN_RF1R_FULL1; /* rc_w1*/
+ break;
+ case CAN_IT_FOV1:
+ CAN->RF1R = CAN_RF1R_FOVR1; /* rc_w1*/
+ break;
+ case CAN_IT_EWG:
+ CAN->ESR &= ~ CAN_ESR_EWGF; /* rw */
+ break;
+ case CAN_IT_EPV:
+ CAN->ESR &= ~ CAN_ESR_EPVF; /* rw */
+ break;
+ case CAN_IT_BOF:
+ CAN->ESR &= ~ CAN_ESR_BOFF; /* rw */
+ break;
+ case CAN_IT_WKU:
+ CAN->MSR = CAN_MSR_WKUI; /* rc_w1*/
+ break;
+ case CAN_IT_SLK:
+ CAN->MSR = CAN_MSR_SLAKI; /* rc_w1*/
+ break;
+ default :
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name : CheckITStatus
+* Description : Checks whether the CAN interrupt has occurred or not.
+* Input : CAN_Reg: specifies the CAN interrupt register to check.
+* It_Bit: specifies the interrupt source bit to check.
+* Output : None.
+* Return : The new state of the CAN Interrupt (SET or RESET).
+*******************************************************************************/
+static ITStatus CheckITStatus(u32 CAN_Reg, u32 It_Bit)
+{
+ ITStatus pendingbitstatus = RESET;
+
+ if ((CAN_Reg & It_Bit) != (u32)RESET)
+ {
+ /* CAN_IT is set */
+ pendingbitstatus = SET;
+ }
+ else
+ {
+ /* CAN_IT is reset */
+ pendingbitstatus = RESET;
+ }
+
+ return pendingbitstatus;
+}
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_dma.c b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_dma.c
new file mode 100644
index 0000000..30239b7
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_dma.c
@@ -0,0 +1,503 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_dma.c
+* Author : MCD Application Team
+* Date First Issued : 09/29/2006
+* Description : This file provides all the DMA firmware functions.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_dma.h"
+#include "stm32f10x_rcc.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* DMA ENABLE mask */
+#define CCR_ENABLE_Set ((u32)0x00000001)
+#define CCR_ENABLE_Reset ((u32)0xFFFFFFFE)
+
+/* DMA Channelx interrupt pending bit masks */
+#define DMA_Channel1_IT_Mask ((u32)0x0000000F)
+#define DMA_Channel2_IT_Mask ((u32)0x000000F0)
+#define DMA_Channel3_IT_Mask ((u32)0x00000F00)
+#define DMA_Channel4_IT_Mask ((u32)0x0000F000)
+#define DMA_Channel5_IT_Mask ((u32)0x000F0000)
+#define DMA_Channel6_IT_Mask ((u32)0x00F00000)
+#define DMA_Channel7_IT_Mask ((u32)0x0F000000)
+
+/* DMA registers Masks */
+#define CCR_CLEAR_Mask ((u32)0xFFFF800F)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name : DMA_DeInit
+* Description : Deinitializes the DMA Channelx registers to their default reset
+* values.
+* Input : - DMA_Channelx: where x can be 1, 2 to 7 to select the DMA
+* Channel.
+* Output : None
+* Return : None
+*******************************************************************************/
+void DMA_DeInit(DMA_Channel_TypeDef* DMA_Channelx)
+{
+ /* DMA Channelx disable */
+ DMA_Cmd(DMA_Channelx, DISABLE);
+
+ /* Reset Channelx control register */
+ DMA_Channelx->CCR = 0;
+
+ /* Reset Channelx remaining bytes register */
+ DMA_Channelx->CNDTR = 0;
+
+ /* Reset Channelx peripheral address register */
+ DMA_Channelx->CPAR = 0;
+
+ /* Reset Channelx memory address register */
+ DMA_Channelx->CMAR = 0;
+
+ switch (*(u32*)&DMA_Channelx)
+ {
+ case DMA_Channel1_BASE:
+ /* Reset interrupt pending bits for Channel1 */
+ DMA->IFCR |= DMA_Channel1_IT_Mask;
+ break;
+
+ case DMA_Channel2_BASE:
+ /* Reset interrupt pending bits for Channel2 */
+ DMA->IFCR |= DMA_Channel2_IT_Mask;
+ break;
+
+ case DMA_Channel3_BASE:
+ /* Reset interrupt pending bits for Channel3 */
+ DMA->IFCR |= DMA_Channel3_IT_Mask;
+ break;
+
+ case DMA_Channel4_BASE:
+ /* Reset interrupt pending bits for Channel4 */
+ DMA->IFCR |= DMA_Channel4_IT_Mask;
+ break;
+
+ case DMA_Channel5_BASE:
+ /* Reset interrupt pending bits for Channel5 */
+ DMA->IFCR |= DMA_Channel5_IT_Mask;
+ break;
+
+ case DMA_Channel6_BASE:
+ /* Reset interrupt pending bits for Channel6 */
+ DMA->IFCR |= DMA_Channel6_IT_Mask;
+ break;
+
+ case DMA_Channel7_BASE:
+ /* Reset interrupt pending bits for Channel7 */
+ DMA->IFCR |= DMA_Channel7_IT_Mask;
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name : DMA_Init
+* Description : Initializes the DMA Channelx according to the specified
+* parameters in the DMA_InitStruct.
+* Input : - DMA_Channelx: where x can be 1, 2 to 7 to select the DMA
+* Channel.
+* - DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
+* contains the configuration information for the specified
+* DMA Channel.
+* Output : None
+* Return : None
+******************************************************************************/
+void DMA_Init(DMA_Channel_TypeDef* DMA_Channelx, DMA_InitTypeDef* DMA_InitStruct)
+{
+ u32 tmpreg = 0;
+
+ /* Check the parameters */
+ assert(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
+ assert(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
+ assert(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
+ assert(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
+ assert(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
+ assert(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
+ assert(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
+ assert(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
+ assert(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
+
+/*--------------------------- DMA Channelx CCR Configuration -----------------*/
+ /* Get the DMA_Channelx CCR value */
+ tmpreg = DMA_Channelx->CCR;
+ /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRCULAR and DIR bits */
+ tmpreg &= CCR_CLEAR_Mask;
+ /* Configure DMA Channelx: data transfer, data size, priority level and mode */
+ /* Set DIR bit according to DMA_DIR value */
+ /* Set CIRCULAR bit according to DMA_Mode value */
+ /* Set PINC bit according to DMA_PeripheralInc value */
+ /* Set MINC bit according to DMA_MemoryInc value */
+ /* Set PSIZE bits according to DMA_PeripheralDataSize value */
+ /* Set MSIZE bits according to DMA_MemoryDataSize value */
+ /* Set PL bits according to DMA_Priority value */
+ /* Set the MEM2MEM bit according to DMA_M2M value */
+ tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
+ DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
+ DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
+ DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
+ /* Write to DMA Channelx CCR */
+ DMA_Channelx->CCR = tmpreg;
+
+/*--------------------------- DMA Channelx CNBTR Configuration ---------------*/
+ /* Write to DMA Channelx CNBTR */
+ DMA_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
+
+/*--------------------------- DMA Channelx CPAR Configuration ----------------*/
+ /* Write to DMA Channelx CPAR */
+ DMA_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
+
+/*--------------------------- DMA Channelx CMAR Configuration ----------------*/
+ /* Write to DMA Channelx CMAR */
+ DMA_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
+}
+
+/*******************************************************************************
+* Function Name : DMA_StructInit
+* Description : Fills each DMA_InitStruct member with its default value.
+* Input : - DMA_InitStruct : pointer to a DMA_InitTypeDef structure
+* which will be initialized.
+* Output : None
+* Return : None
+*******************************************************************************/
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
+{
+/*-------------- Reset DMA init structure parameters values ------------------*/
+ /* Initialize the DMA_PeripheralBaseAddr member */
+ DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
+
+ /* Initialize the DMA_MemoryBaseAddr member */
+ DMA_InitStruct->DMA_MemoryBaseAddr = 0;
+
+ /* Initialize the DMA_DIR member */
+ DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
+
+ /* Initialize the DMA_BufferSize member */
+ DMA_InitStruct->DMA_BufferSize = 0;
+
+ /* Initialize the DMA_PeripheralInc member */
+ DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+
+ /* Initialize the DMA_MemoryInc member */
+ DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
+
+ /* Initialize the DMA_PeripheralDataSize member */
+ DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
+
+ /* Initialize the DMA_MemoryDataSize member */
+ DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
+
+ /* Initialize the DMA_Mode member */
+ DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
+
+ /* Initialize the DMA_Priority member */
+ DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
+
+ /* Initialize the DMA_M2M member */
+ DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
+}
+
+/*******************************************************************************
+* Function Name : DMA_Cmd
+* Description : Enables or disables the specified DMA Channel.
+* Input : - DMA_Channelx: where x can be 1, 2 to 7 to select the DMA
+* Channel.
+* - NewState: new state of the DMAx Channel.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void DMA_Cmd(DMA_Channel_TypeDef* DMA_Channelx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected DMA Channelx */
+ DMA_Channelx->CCR |= CCR_ENABLE_Set;
+ }
+ else
+ {
+ /* Disable the selected DMA Channelx */
+ DMA_Channelx->CCR &= CCR_ENABLE_Reset;
+ }
+}
+
+/*******************************************************************************
+* Function Name : DMA_ITConfig
+* Description : Enables or disables the specified DMA interrupts.
+* Input : - DMA_IT: specifies the DMA interrupts sources to be enabled
+* or disabled.
+* This parameter can be any combination of the following values:
+* - DMA_IT_TC: Transfer complete interrupt mask
+* - DMA_IT_HT: Half transfer interrupt mask
+* - DMA_IT_TE: Transfer error interrupt mask
+* - NewState: new state of the specified DMA interrupts.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void DMA_ITConfig(DMA_Channel_TypeDef* DMA_Channelx, u32 DMA_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_DMA_CONFIG_IT(DMA_IT));
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected DMA interrupts */
+ DMA_Channelx->CCR |= DMA_IT;
+ }
+ else
+ {
+ /* Disable the selected DMA interrupts */
+ DMA_Channelx->CCR &= ~DMA_IT;
+ }
+}
+
+/*******************************************************************************
+* Function Name : DMA_GetCurrDataCounter
+* Description : Returns the number of remaining data units in the current
+* DMA Channel transfer.
+* Input : - DMA_Channelx: where x can be 1, 2 to 7 to select the DMA
+* Channel.
+* Output : None
+* Return : The number of remaining data units in the current DMA Channel
+* transfer..
+*******************************************************************************/
+u16 DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMA_Channelx)
+{
+ /* Return the current memory address value for Channelx */
+ return ((u16)(DMA_Channelx->CNDTR));
+}
+
+/*******************************************************************************
+* Function Name : DMA_GetFlagStatus
+* Description : Checks whether the specified DMA flag is set or not.
+* Input : - DMA_FLAG: specifies the flag to check.
+* This parameter can be one of the following values:
+* - DMA_FLAG_GL1: Channel1 global flag.
+* - DMA_FLAG_TC1: Channel1 transfer complete flag.
+* - DMA_FLAG_HT1: Channel1 half transfer flag.
+* - DMA_FLAG_TE1: Channel1 transfer error flag.
+* - DMA_FLAG_GL2: Channel2 global flag.
+* - DMA_FLAG_TC2: Channel2 transfer complete flag.
+* - DMA_FLAG_HT2: Channel2 half transfer flag.
+* - DMA_FLAG_TE2: Channel2 transfer error flag.
+* - DMA_FLAG_GL3: Channel3 global flag.
+* - DMA_FLAG_TC3: Channel3 transfer complete flag.
+* - DMA_FLAG_HT3: Channel3 half transfer flag.
+* - DMA_FLAG_TE3: Channel3 transfer error flag.
+* - DMA_FLAG_GL4: Channel4 global flag.
+* - DMA_FLAG_TC4: Channel4 transfer complete flag.
+* - DMA_FLAG_HT4: Channel4 half transfer flag.
+* - DMA_FLAG_TE4: Channel4 transfer error flag.
+* - DMA_FLAG_GL5: Channel5 global flag.
+* - DMA_FLAG_TC5: Channel5 transfer complete flag.
+* - DMA_FLAG_HT5: Channel5 half transfer flag.
+* - DMA_FLAG_TE5: Channel5 transfer error flag.
+* - DMA_FLAG_GL6: Channel6 global flag.
+* - DMA_FLAG_TC6: Channel6 transfer complete flag.
+* - DMA_FLAG_HT6: Channel6 half transfer flag.
+* - DMA_FLAG_TE6: Channel6 transfer error flag.
+* - DMA_FLAG_GL7: Channel7 global flag.
+* - DMA_FLAG_TC7: Channel7 transfer complete flag.
+* - DMA_FLAG_HT7: Channel7 half transfer flag.
+* - DMA_FLAG_TE7: Channel7 transfer error flag.
+* Output : None
+* Return : The new state of DMA_FLAG (SET or RESET).
+*******************************************************************************/
+FlagStatus DMA_GetFlagStatus(u32 DMA_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert(IS_DMA_GET_FLAG(DMA_FLAG));
+
+ /* Check the status of the specified DMA flag */
+ if ((DMA->ISR & DMA_FLAG) != (u32)RESET)
+ {
+ /* DMA_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* DMA_FLAG is reset */
+ bitstatus = RESET;
+ }
+ /* Return the DMA_FLAG status */
+ return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name : DMA_ClearFlag
+* Description : Clears the DMA's pending flags.
+* Input : - DMA_FLAG: specifies the flag to clear.
+* This parameter can be any combination of the following values:
+* - DMA_FLAG_GL1: Channel1 global flag.
+* - DMA_FLAG_TC1: Channel1 transfer complete flag.
+* - DMA_FLAG_HT1: Channel1 half transfer flag.
+* - DMA_FLAG_TE1: Channel1 transfer error flag.
+* - DMA_FLAG_GL2: Channel2 global flag.
+* - DMA_FLAG_TC2: Channel2 transfer complete flag.
+* - DMA_FLAG_HT2: Channel2 half transfer flag.
+* - DMA_FLAG_TE2: Channel2 transfer error flag.
+* - DMA_FLAG_GL3: Channel3 global flag.
+* - DMA_FLAG_TC3: Channel3 transfer complete flag.
+* - DMA_FLAG_HT3: Channel3 half transfer flag.
+* - DMA_FLAG_TE3: Channel3 transfer error flag.
+* - DMA_FLAG_GL4: Channel4 global flag.
+* - DMA_FLAG_TC4: Channel4 transfer complete flag.
+* - DMA_FLAG_HT4: Channel4 half transfer flag.
+* - DMA_FLAG_TE4: Channel4 transfer error flag.
+* - DMA_FLAG_GL5: Channel5 global flag.
+* - DMA_FLAG_TC5: Channel5 transfer complete flag.
+* - DMA_FLAG_HT5: Channel5 half transfer flag.
+* - DMA_FLAG_TE5: Channel5 transfer error flag.
+* - DMA_FLAG_GL6: Channel6 global flag.
+* - DMA_FLAG_TC6: Channel6 transfer complete flag.
+* - DMA_FLAG_HT6: Channel6 half transfer flag.
+* - DMA_FLAG_TE6: Channel6 transfer error flag.
+* - DMA_FLAG_GL7: Channel7 global flag.
+* - DMA_FLAG_TC7: Channel7 transfer complete flag.
+* - DMA_FLAG_HT7: Channel7 half transfer flag.
+* - DMA_FLAG_TE7: Channel7 transfer error flag.
+* Output : None
+* Return : None
+*******************************************************************************/
+void DMA_ClearFlag(u32 DMA_FLAG)
+{
+ /* Check the parameters */
+ assert(IS_DMA_CLEAR_FLAG(DMA_FLAG));
+
+ /* Clear the selected DMA flags */
+ DMA->IFCR = DMA_FLAG;
+}
+
+/*******************************************************************************
+* Function Name : DMA_GetITStatus
+* Description : Checks whether the specified DMA interrupt has occurred or not.
+* Input : - DMA_IT: specifies the DMA interrupt source to check.
+* This parameter can be one of the following values:
+* - DMA_IT_GL1: Channel1 global interrupt.
+* - DMA_IT_TC1: Channel1 transfer complete interrupt.
+* - DMA_IT_HT1: Channel1 half transfer interrupt.
+* - DMA_IT_TE1: Channel1 transfer error interrupt.
+* - DMA_IT_GL2: Channel2 global interrupt.
+* - DMA_IT_TC2: Channel2 transfer complete interrupt.
+* - DMA_IT_HT2: Channel2 half transfer interrupt.
+* - DMA_IT_TE2: Channel2 transfer error interrupt.
+* - DMA_IT_GL3: Channel3 global interrupt.
+* - DMA_IT_TC3: Channel3 transfer complete interrupt.
+* - DMA_IT_HT3: Channel3 half transfer interrupt.
+* - DMA_IT_TE3: Channel3 transfer error interrupt.
+* - DMA_IT_GL4: Channel4 global interrupt.
+* - DMA_IT_TC4: Channel4 transfer complete interrupt.
+* - DMA_IT_HT4: Channel4 half transfer interrupt.
+* - DMA_IT_TE4: Channel4 transfer error interrupt.
+* - DMA_IT_GL5: Channel5 global interrupt.
+* - DMA_IT_TC5: Channel5 transfer complete interrupt.
+* - DMA_IT_HT5: Channel5 half transfer interrupt.
+* - DMA_IT_TE5: Channel5 transfer error interrupt.
+* - DMA_IT_GL6: Channel6 global interrupt.
+* - DMA_IT_TC6: Channel6 transfer complete interrupt.
+* - DMA_IT_HT6: Channel6 half transfer interrupt.
+* - DMA_IT_TE6: Channel6 transfer error interrupt.
+* - DMA_IT_GL7: Channel7 global interrupt.
+* - DMA_IT_TC7: Channel7 transfer complete interrupt.
+* - DMA_IT_HT7: Channel7 half transfer interrupt.
+* - DMA_IT_TE7: Channel7 transfer error interrupt.
+* Output : None
+* Return : The new state of DMA_IT (SET or RESET).
+*******************************************************************************/
+ITStatus DMA_GetITStatus(u32 DMA_IT)
+{
+ ITStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert(IS_DMA_GET_IT(DMA_IT));
+
+ /* Check the status of the specified DMA interrupt */
+ if ((DMA->ISR & DMA_IT) != (u32)RESET)
+ {
+ /* DMA_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* DMA_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the DMA_IT status */
+ return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name : DMA_ClearITPendingBit
+* Description : Clears the DMAs interrupt pending bits.
+* Input : - DMA_IT: specifies the DMA interrupt pending bit to clear.
+* This parameter can be any combination of the following values:
+* - DMA_IT_GL1: Channel1 global interrupt.
+* - DMA_IT_TC1: Channel1 transfer complete interrupt.
+* - DMA_IT_HT1: Channel1 half transfer interrupt.
+* - DMA_IT_TE1: Channel1 transfer error interrupt.
+* - DMA_IT_GL2: Channel2 global interrupt.
+* - DMA_IT_TC2: Channel2 transfer complete interrupt.
+* - DMA_IT_HT2: Channel2 half transfer interrupt.
+* - DMA_IT_TE2: Channel2 transfer error interrupt.
+* - DMA_IT_GL3: Channel3 global interrupt.
+* - DMA_IT_TC3: Channel3 transfer complete interrupt.
+* - DMA_IT_HT3: Channel3 half transfer interrupt.
+* - DMA_IT_TE3: Channel3 transfer error interrupt.
+* - DMA_IT_GL4: Channel4 global interrupt.
+* - DMA_IT_TC4: Channel4 transfer complete interrupt.
+* - DMA_IT_HT4: Channel4 half transfer interrupt.
+* - DMA_IT_TE4: Channel4 transfer error interrupt.
+* - DMA_IT_GL5: Channel5 global interrupt.
+* - DMA_IT_TC5: Channel5 transfer complete interrupt.
+* - DMA_IT_HT5: Channel5 half transfer interrupt.
+* - DMA_IT_TE5: Channel5 transfer error interrupt.
+* - DMA_IT_GL6: Channel6 global interrupt.
+* - DMA_IT_TC6: Channel6 transfer complete interrupt.
+* - DMA_IT_HT6: Channel6 half transfer interrupt.
+* - DMA_IT_TE6: Channel6 transfer error interrupt.
+* - DMA_IT_GL7: Channel7 global interrupt.
+* - DMA_IT_TC7: Channel7 transfer complete interrupt.
+* - DMA_IT_HT7: Channel7 half transfer interrupt.
+* - DMA_IT_TE7: Channel7 transfer error interrupt.
+* Output : None
+* Return : None
+*******************************************************************************/
+void DMA_ClearITPendingBit(u32 DMA_IT)
+{
+ /* Check the parameters */
+ assert(IS_DMA_CLEAR_IT(DMA_IT));
+
+ /* Clear the selected DMA interrupt pending bits */
+ DMA->IFCR = DMA_IT;
+}
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
+
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_exti.c b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_exti.c
new file mode 100644
index 0000000..811d94b
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_exti.c
@@ -0,0 +1,219 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_exti.c
+* Author : MCD Application Team
+* Date First Issued : 09/29/2006
+* Description : This file provides all the EXTI firmware functions.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_exti.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define EXTI_LineNone ((u32)0x00000) /* No interrupt selected */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name : EXTI_DeInit
+* Description : Deinitializes the EXTI peripheral registers to their default
+* reset values.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void EXTI_DeInit(void)
+{
+ EXTI->IMR = 0x00000000;
+ EXTI->EMR = 0x00000000;
+ EXTI->RTSR = 0x00000000;
+ EXTI->FTSR = 0x00000000;
+ EXTI->PR = 0x0007FFFF;
+}
+
+/*******************************************************************************
+* Function Name : EXTI_Init
+* Description : Initializes the EXTI peripheral according to the specified
+* parameters in the EXTI_InitStruct.
+* Input : - EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
+* that contains the configuration information for the EXTI
+* peripheral.
+* Output : None
+* Return : None
+*******************************************************************************/
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
+{
+ /* Check the parameters */
+ assert(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
+ assert(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
+ assert(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
+ assert(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
+
+ if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
+ {
+ *(u32 *)(EXTI_BASE + (u32)EXTI_InitStruct->EXTI_Mode)|= EXTI_InitStruct->EXTI_Line;
+
+ /* Clear Rising Falling edge configuration */
+ EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
+ EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
+
+ /* Select the trigger for the selected external interrupts */
+ if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
+ {
+ /* Rising Falling edge */
+ EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
+ EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
+ }
+ else
+ {
+ *(u32 *)(EXTI_BASE + (u32)EXTI_InitStruct->EXTI_Trigger)|= EXTI_InitStruct->EXTI_Line;
+ }
+ }
+ else
+ {
+ /* Disable the selected external lines */
+ *(u32 *)(EXTI_BASE + (u32)EXTI_InitStruct->EXTI_Mode)&= ~EXTI_InitStruct->EXTI_Line;
+ }
+}
+
+/*******************************************************************************
+* Function Name : EXTI_StructInit
+* Description : Fills each EXTI_InitStruct member with its reset value.
+* Input : - EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
+* which will be initialized.
+* Output : None
+* Return : None
+*******************************************************************************/
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
+{
+ EXTI_InitStruct->EXTI_Line = EXTI_LineNone;
+ EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
+ EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
+ EXTI_InitStruct->EXTI_LineCmd = DISABLE;
+}
+
+/*******************************************************************************
+* Function Name : EXTI_GenerateSWInterrupt
+* Description : Generates a Software interrupt.
+* Input : - EXTI_Line: specifies the EXTI lines to be enabled or
+* disabled.
+* This parameter can be:
+* - EXTI_Linex: External interrupt line x where x(0..18)
+* Output : None
+* Return : None
+*******************************************************************************/
+void EXTI_GenerateSWInterrupt(u32 EXTI_Line)
+{
+ /* Check the parameters */
+ assert(IS_EXTI_LINE(EXTI_Line));
+
+ EXTI->SWIER |= EXTI_Line;
+}
+
+/*******************************************************************************
+* Function Name : EXTI_GetFlagStatus
+* Description : Checks whether the specified EXTI line flag is set or not.
+* Input : - EXTI_Line: specifies the EXTI lines flag to check.
+* This parameter can be:
+* - EXTI_Linex: External interrupt line x where x(0..18)
+* Output : None
+* Return : The new state of EXTI_Line (SET or RESET).
+*******************************************************************************/
+FlagStatus EXTI_GetFlagStatus(u32 EXTI_Line)
+{
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert(IS_GET_EXTI_LINE(EXTI_Line));
+
+ if ((EXTI->PR & EXTI_Line) != (u32)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name : EXTI_ClearFlag
+* Description : Clears the EXTIs line pending flags.
+* Input : - EXTI_Line: specifies the EXTI lines flags to clear.
+* This parameter can be:
+* - EXTI_Linex: External interrupt line x where x(0..18)
+* Output : None
+* Return : None
+*******************************************************************************/
+void EXTI_ClearFlag(u32 EXTI_Line)
+{
+ /* Check the parameters */
+ assert(IS_EXTI_LINE(EXTI_Line));
+
+ EXTI->PR = EXTI_Line;
+}
+
+/*******************************************************************************
+* Function Name : EXTI_GetITStatus
+* Description : Checks whether the specified EXTI line is asserted or not.
+* Input : - EXTI_Line: specifies the EXTI lines to check.
+* This parameter can be:
+* - EXTI_Linex: External interrupt line x where x(0..18)
+* Output : None
+* Return : The new state of EXTI_Line (SET or RESET).
+*******************************************************************************/
+ITStatus EXTI_GetITStatus(u32 EXTI_Line)
+{
+ ITStatus bitstatus = RESET;
+ u32 enablestatus = 0;
+
+ /* Check the parameters */
+ assert(IS_GET_EXTI_LINE(EXTI_Line));
+
+ enablestatus = EXTI->IMR & EXTI_Line;
+
+ if (((EXTI->PR & EXTI_Line) != (u32)RESET) && enablestatus)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name : EXTI_ClearITPendingBit
+* Description : Clears the EXTIs line pending bits.
+* Input : - EXTI_Line: specifies the EXTI lines to clear.
+* This parameter can be:
+* - EXTI_Linex: External interrupt line x where x(0..18)
+* Output : None
+* Return : None
+*******************************************************************************/
+void EXTI_ClearITPendingBit(u32 EXTI_Line)
+{
+ /* Check the parameters */
+ assert(IS_EXTI_LINE(EXTI_Line));
+
+ EXTI->PR = EXTI_Line;
+}
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_gpio.c b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_gpio.c
new file mode 100644
index 0000000..571a00d
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_gpio.c
@@ -0,0 +1,515 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_gpio.c
+* Author : MCD Application Team
+* Date First Issued : 09/29/2006
+* Description : This file provides all the GPIO firmware functions.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_gpio.h"
+#include "stm32f10x_rcc.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* ------------ RCC registers bit address in the alias region ----------- */
+#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE)
+
+/* --- EVENTCR Register ---*/
+/* Alias word address of EVOE bit */
+#define EVCR_OFFSET (AFIO_OFFSET + 0x00)
+#define EVOE_BitNumber ((u8)0x07)
+#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4))
+
+#define EVCR_PORTPINCONFIG_MASK ((u16)0xFF80)
+#define LSB_MASK ((u16)0xFFFF)
+#define DBGAFR_POSITION_MASK ((u32)0x000F0000)
+#define DBGAFR_SWJCFG_MASK ((u32)0xF8FFFFFF)
+#define DBGAFR_LOCATION_MASK ((u32)0x00200000)
+#define DBGAFR_NUMBITS_MASK ((u32)0x00100000)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name : GPIO_DeInit
+* Description : Deinitializes the GPIOx peripheral registers to their default
+* reset values.
+* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral.
+* Output : None
+* Return : None
+*******************************************************************************/
+void GPIO_DeInit(GPIO_TypeDef* GPIOx)
+{
+ switch (*(u32*)&GPIOx)
+ {
+ case GPIOA_BASE:
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
+ break;
+
+ case GPIOB_BASE:
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);
+ break;
+
+ case GPIOC_BASE:
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);
+ break;
+
+ case GPIOD_BASE:
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);
+ break;
+
+ case GPIOE_BASE:
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name : GPIO_AFIODeInit
+* Description : Deinitializes the Alternate Functions (remap, event control
+* and EXTI configuration) registers to their default reset
+* values.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void GPIO_AFIODeInit(void)
+{
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);
+}
+
+/*******************************************************************************
+* Function Name : GPIO_Init
+* Description : Initializes the GPIOx peripheral according to the specified
+* parameters in the GPIO_InitStruct.
+* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral.
+* - GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
+* contains the configuration information for the specified GPIO
+* peripheral.
+* Output : None
+* Return : None
+*******************************************************************************/
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
+{
+ u32 currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
+ u32 tmpreg = 0x00, pinmask = 0x00;
+
+ /* Check the parameters */
+ assert(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
+ assert(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
+
+/*---------------------------- GPIO Mode Configuration -----------------------*/
+ currentmode = ((u32)GPIO_InitStruct->GPIO_Mode) & ((u32)0x0F);
+
+ if ((((u32)GPIO_InitStruct->GPIO_Mode) & ((u32)0x10)) != 0x00)
+ {
+ /* Check the parameters */
+ assert(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
+ /* Output mode */
+ currentmode |= (u32)GPIO_InitStruct->GPIO_Speed;
+ }
+
+/*---------------------------- GPIO CRL Configuration ------------------------*/
+ /* Configure the eight low port pins */
+ if (((u32)GPIO_InitStruct->GPIO_Pin & ((u32)0x00FF)) != 0x00)
+ {
+ tmpreg = GPIOx->CRL;
+
+ for (pinpos = 0x00; pinpos < 0x08; pinpos++)
+ {
+ pos = ((u32)0x01) << pinpos;
+ /* Get the port pins position */
+ currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
+
+ if (currentpin == pos)
+ {
+ pos = pinpos << 2;
+ /* Clear the corresponding low control register bits */
+ pinmask = ((u32)0x0F) << pos;
+ tmpreg &= ~pinmask;
+
+ /* Write the mode configuration in the corresponding bits */
+ tmpreg |= (currentmode << pos);
+
+ /* Reset the corresponding ODR bit */
+ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
+ {
+ GPIOx->BRR = (((u32)0x01) << pinpos);
+ }
+ /* Set the corresponding ODR bit */
+ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
+ {
+ GPIOx->BSRR = (((u32)0x01) << pinpos);
+ }
+ }
+ }
+ GPIOx->CRL = tmpreg;
+ tmpreg = 0;
+ }
+
+/*---------------------------- GPIO CRH Configuration ------------------------*/
+ /* Configure the eight high port pins */
+ if (GPIO_InitStruct->GPIO_Pin > 0x00FF)
+ {
+ tmpreg = GPIOx->CRH;
+ for (pinpos = 0x00; pinpos < 0x08; pinpos++)
+ {
+ pos = (((u32)0x01) << (pinpos + 0x08));
+ /* Get the port pins position */
+ currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
+ if (currentpin == pos)
+ {
+ pos = pinpos << 2;
+ /* Clear the corresponding high control register bits */
+ pinmask = ((u32)0x0F) << pos;
+ tmpreg &= ~pinmask;
+
+ /* Write the mode configuration in the corresponding bits */
+ tmpreg |= (currentmode << pos);
+
+ /* Reset the corresponding ODR bit */
+ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
+ {
+ GPIOx->BRR = (((u32)0x01) << (pinpos + 0x08));
+ }
+ /* Set the corresponding ODR bit */
+ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
+ {
+ GPIOx->BSRR = (((u32)0x01) << (pinpos + 0x08));
+ }
+ }
+ }
+ GPIOx->CRH = tmpreg;
+ }
+}
+
+/*******************************************************************************
+* Function Name : GPIO_StructInit
+* Description : Fills each GPIO_InitStruct member with its default value.
+* Input : - GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure
+* which will be initialized.
+* Output : None
+* Return : None
+*******************************************************************************/
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
+{
+ /* Reset GPIO init structure parameters values */
+ GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
+ GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
+ GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;
+}
+
+/*******************************************************************************
+* Function Name : GPIO_ReadInputDataBit
+* Description : Reads the specified input port pin.
+* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral.
+* : - GPIO_Pin: specifies the port bit to read.
+* This parameter can be GPIO_Pin_x where x can be (0..15).
+* Output : None
+* Return : The input port pin value.
+*******************************************************************************/
+u8 GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin)
+{
+ u8 bitstatus = 0x00;
+
+ /* Check the parameters */
+ assert(IS_GPIO_PIN(GPIO_Pin));
+
+ if ((GPIOx->IDR & GPIO_Pin) != (u32)Bit_RESET)
+ {
+ bitstatus = (u8)Bit_SET;
+ }
+ else
+ {
+ bitstatus = (u8)Bit_RESET;
+ }
+ return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name : GPIO_ReadInputData
+* Description : Reads the specified GPIO input data port.
+* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral.
+* Output : None
+* Return : GPIO input data port value.
+*******************************************************************************/
+u16 GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
+{
+ return ((u16)GPIOx->IDR);
+}
+
+/*******************************************************************************
+* Function Name : GPIO_ReadOutputDataBit
+* Description : Reads the specified output data port bit.
+* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral.
+* : - GPIO_Pin: specifies the port bit to read.
+* This parameter can be GPIO_Pin_x where x can be (0..15).
+* Output : None
+* Return : The output port pin value.
+*******************************************************************************/
+u8 GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin)
+{
+ u8 bitstatus = 0x00;
+
+ /* Check the parameters */
+ assert(IS_GPIO_PIN(GPIO_Pin));
+
+ if ((GPIOx->ODR & GPIO_Pin) != (u32)Bit_RESET)
+ {
+ bitstatus = (u8)Bit_SET;
+ }
+ else
+ {
+ bitstatus = (u8)Bit_RESET;
+ }
+ return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name : GPIO_ReadOutputData
+* Description : Reads the specified GPIO output data port.
+* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral.
+* Output : None
+* Return : GPIO output data port value.
+*******************************************************************************/
+u16 GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
+{
+ return ((u16)GPIOx->ODR);
+}
+
+/*******************************************************************************
+* Function Name : GPIO_WriteBit
+* Description : Sets or clears the selected data port bit.
+* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral.
+* - GPIO_Pin: specifies the port bit to be written.
+* This parameter can be GPIO_Pin_x where x can be (0..15).
+* - BitVal: specifies the value to be written to the selected bit.
+* This parameter can be one of the BitAction enum values:
+* - Bit_RESET: to clear the port pin
+* - Bit_SET: to set the port pin
+* Output : None
+* Return : None
+*******************************************************************************/
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin, BitAction BitVal)
+{
+ /* Check the parameters */
+ assert(IS_GPIO_PIN(GPIO_Pin));
+ assert(IS_GPIO_BIT_ACTION(BitVal));
+
+ if (BitVal != Bit_RESET)
+ {
+ GPIOx->BSRR = GPIO_Pin;
+ }
+ else
+ {
+ GPIOx->BRR = GPIO_Pin;
+ }
+}
+
+/*******************************************************************************
+* Function Name : GPIO_Write
+* Description : Writes data to the specified GPIO data port.
+* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral.
+* - PortVal: specifies the value to be written to the port output
+* data register.
+* Output : None
+* Return : None
+*******************************************************************************/
+void GPIO_Write(GPIO_TypeDef* GPIOx, u16 PortVal)
+{
+ GPIOx->ODR = PortVal;
+}
+
+/*******************************************************************************
+* Function Name : GPIO_PinLockConfig
+* Description : Locks GPIO Pins configuration registers.
+* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral.
+* - GPIO_Pin: specifies the port bit to be written.
+* This parameter can be GPIO_Pin_x where x can be (0..15).
+* Output : None
+* Return : None
+*******************************************************************************/
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, u16 GPIO_Pin)
+{
+ u32 tmp = 0x00010000;
+
+ /* Check the parameters */
+ assert(IS_GPIO_PIN(GPIO_Pin));
+
+ tmp |= GPIO_Pin;
+ /* Set LCKK bit */
+ GPIOx->LCKR = tmp;
+ /* Reset LCKK bit */
+ GPIOx->LCKR = GPIO_Pin;
+ /* Set LCKK bit */
+ GPIOx->LCKR = tmp;
+ /* Read LCKK bit*/
+ tmp = GPIOx->LCKR;
+ /* Read LCKK bit*/
+ tmp = GPIOx->LCKR;
+}
+
+/*******************************************************************************
+* Function Name : GPIO_EventOutputConfig
+* Description : Selects the GPIO pin used as Event output.
+* Input : - GPIO_PortSource: selects the GPIO port to be used as source
+* for Event output.
+* This parameter can be GPIO_PortSourceGPIOx where x can be
+* (A..E).
+* - GPIO_PinSource: specifies the pin for the Event output.
+* This parameter can be GPIO_PinSourcex where x can be (0..15).
+* Output : None
+* Return : None
+*******************************************************************************/
+void GPIO_EventOutputConfig(u8 GPIO_PortSource, u8 GPIO_PinSource)
+{
+ u32 tmpreg = 0x00;
+
+ /* Check the parameters */
+ assert(IS_GPIO_PORT_SOURCE(GPIO_PortSource));
+ assert(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
+
+ tmpreg = AFIO->EVCR;
+ /* Clear the PORT[6:4] and PIN[3:0] bits */
+ tmpreg &= EVCR_PORTPINCONFIG_MASK;
+ tmpreg |= (u32)GPIO_PortSource << 0x04;
+ tmpreg |= GPIO_PinSource;
+
+ AFIO->EVCR = tmpreg;
+}
+
+/*******************************************************************************
+* Function Name : GPIO_EventOutputCmd
+* Description : Enables or disables the Event Output.
+* Input : - NewState: new state of the Event output.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void GPIO_EventOutputCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ *(vu32 *) EVCR_EVOE_BB = (u32)NewState;
+}
+
+/*******************************************************************************
+* Function Name : GPIO_PinRemapConfig
+* Description : Changes the mapping of the specified pin.
+* Input : - GPIO_Remap: selects the pin to remap.
+* This parameter can be one of the following values:
+* - GPIO_Remap_SPI1
+* - GPIO_Remap_I2C1
+* - GPIO_Remap_USART1
+* - GPIO_Remap_USART2
+* - GPIO_PartialRemap_USART3
+* - GPIO_FullRemap_USART3
+* - GPIO_PartialRemap_TIM1
+* - GPIO_FullRemap_TIM1
+* - GPIO_PartialRemap1_TIM2
+* - GPIO_PartialRemap2_TIM2
+* - GPIO_FullRemap_TIM2
+* - GPIO_PartialRemap_TIM3
+* - GPIO_FullRemap_TIM3
+* - GPIO_Remap_TIM4
+* - GPIO_Remap1_CAN
+* - GPIO_Remap2_CAN
+* - GPIO_Remap_PD01
+* - GPIO_Remap_SWJ_NoJTRST
+* - GPIO_Remap_SWJ_JTAGDisable
+* - GPIO_Remap_SWJ_Disable
+* - NewState: new state of the port pin remapping.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void GPIO_PinRemapConfig(u32 GPIO_Remap, FunctionalState NewState)
+{
+ u32 tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;
+
+ /* Check the parameters */
+ assert(IS_GPIO_REMAP(GPIO_Remap));
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ tmpreg = AFIO->MAPR;
+
+ tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;
+ tmp = GPIO_Remap & LSB_MASK;
+
+ if ((GPIO_Remap & DBGAFR_LOCATION_MASK) == DBGAFR_LOCATION_MASK)
+ {
+ tmpreg &= DBGAFR_SWJCFG_MASK;
+ }
+ else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK)
+ {
+ tmp1 = ((u32)0x03) << tmpmask;
+ tmpreg &= ~tmp1;
+ }
+ else
+ {
+ tmpreg &= ~tmp;
+ }
+
+ if (NewState != DISABLE)
+ {
+ if ((GPIO_Remap & DBGAFR_LOCATION_MASK) == DBGAFR_LOCATION_MASK)
+ {
+ tmpreg |= (tmp << 0x10);
+ }
+ else
+ {
+ tmpreg |= tmp;
+ }
+ }
+ AFIO->MAPR = tmpreg;
+}
+
+/*******************************************************************************
+* Function Name : GPIO_EXTILineConfig
+* Description : Selects the GPIO pin used as EXTI Line.
+* Input : - GPIO_PortSource: selects the GPIO port to be used as
+* source for EXTI lines.
+* - GPIO_PinSource: specifies the EXTI line to be configured.
+* This parameter can be GPIO_PinSourcex where x can be (0..15).
+* Output : None
+* Return : None
+*******************************************************************************/
+void GPIO_EXTILineConfig(u8 GPIO_PortSource, u8 GPIO_PinSource)
+{
+ u32 tmp = 0x00;
+
+ /* Check the parameters */
+ assert(IS_GPIO_PORT_SOURCE(GPIO_PortSource));
+ assert(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
+
+ tmp = ((u32)0x0F) << (0x04 * (GPIO_PinSource & (u8)0x03));
+
+ AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp;
+ AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((u32)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (u8)0x03)));
+}
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_i2c.c b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_i2c.c
new file mode 100644
index 0000000..2809b83
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_i2c.c
@@ -0,0 +1,1186 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_i2c.c
+* Author : MCD Application Team
+* Date First Issued : 09/29/2006
+* Description : This file provides all the I2C firmware functions.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_i2c.h"
+#include "stm32f10x_rcc.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* I2C SPE mask */
+#define CR1_PE_Set ((u16)0x0001)
+#define CR1_PE_Reset ((u16)0xFFFE)
+
+/* I2C DMAEN mask */
+#define CR2_DMAEN_Set ((u16)0x0800)
+#define CR2_DMAEN_Reset ((u16)0xF7FF)
+
+/* I2C LAST mask */
+#define CR2_LAST_Set ((u16)0x1000)
+#define CR2_LAST_Reset ((u16)0xEFFF)
+
+/* I2C START mask */
+#define CR1_START_Set ((u16)0x0100)
+#define CR1_START_Reset ((u16)0xFEFF)
+
+/* I2C STOP mask */
+#define CR1_STOP_Set ((u16)0x0200)
+#define CR1_STOP_Reset ((u16)0xFDFF)
+
+/* I2C ACK mask */
+#define CR1_ACK_Set ((u16)0x0400)
+#define CR1_ACK_Reset ((u16)0xFBFF)
+
+/* I2C ENGC mask */
+#define CR1_ENGC_Set ((u16)0x0040)
+#define CR1_ENGC_Reset ((u16)0xFFBF)
+
+/* I2C ADD0 mask */
+#define OAR1_ADD0_Set ((u16)0x0001)
+#define OAR1_ADD0_Reset ((u16)0xFFFE)
+
+/* I2C SWRST mask */
+#define CR1_SWRST_Set ((u16)0x8000)
+#define CR1_SWRST_Reset ((u16)0x7FFF)
+
+/* I2C PEC mask */
+#define CR1_PEC_Set ((u16)0x1000)
+
+/* I2C ENPEC mask */
+#define CR1_ENPEC_Set ((u16)0x0020)
+#define CR1_ENPEC_Reset ((u16)0xFFDF)
+
+/* I2C ENARP mask */
+#define CR1_ENARP_Set ((u16)0x0010)
+#define CR1_ENARP_Reset ((u16)0xFFEF)
+
+/* I2C NOSTRETCH mask */
+#define CR1_NOSTRETCH_Set ((u16)0x0080)
+#define CR1_NOSTRETCH_Reset ((u16)0xFF7F)
+
+/* I2C ENDUAL mask */
+#define OAR2_ENDUAL_Set ((u16)0x0001)
+#define OAR2_ENDUAL_Reset ((u16)0xFFFE)
+
+/* I2C F/S mask */
+#define CCR_FS_Set ((u16)0x8000)
+
+/* I2C ADD2 mask */
+#define OAR2_ADD2_Reset ((u16)0xFF01)
+
+/* I2C FREQ mask */
+#define CR2_FREQ_Reset ((u16)0xFFC0)
+
+/* I2C CCR mask */
+#define CCR_CCR_Set ((u16)0x0FFF)
+
+/* I2C FLAG mask */
+#define I2C_FLAG_Mask ((u32)0x00FFFFFF)
+
+/* I2C registers Masks */
+#define CR1_CLEAR_Mask ((u16)0xFBF5)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name : I2C_DeInit
+* Description : Deinitializes the I2Cx peripheral registers to their default
+* reset values.
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* Output : None
+* Return : None
+*******************************************************************************/
+void I2C_DeInit(I2C_TypeDef* I2Cx)
+{
+ switch (*(u32*)&I2Cx)
+ {
+ case I2C1_BASE:
+ /* Enable I2C1 reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
+ /* Release I2C1 from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);
+ break;
+
+ case I2C2_BASE:
+ /* Enable I2C2 reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
+ /* Release I2C2 from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name : I2C_Init
+* Description : Initializes the I2Cx according to the specified parameters
+* in the I2C_InitStruct.
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* - I2C_InitStruct: pointer to a I2C_InitTypeDef structure that
+* contains the configuration information for the specified
+* I2C peripheral.
+* Output : None
+* Return : None
+******************************************************************************/
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
+{
+ u16 tmpreg = 0, freqrange = 0;
+ u16 result = 0x04;
+ u32 pclk1clock = 12000000;
+ RCC_ClocksTypeDef RCC_Clocks;
+
+ /* Check the parameters */
+ assert(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));
+ assert(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle));
+ assert(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));
+ assert(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack));
+ assert(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));
+ assert(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed));
+
+/*---------------------------- I2Cx CR2 Configuration ------------------------*/
+ /* Get the I2Cx CR2 value */
+ tmpreg = I2Cx->CR2;
+ /* Clear frequency FREQ[5:0] bits */
+ tmpreg &= CR2_FREQ_Reset;
+ /* Get PCLK1Clock frequency value */
+ RCC_GetClocksFreq(&RCC_Clocks);
+ pclk1clock = RCC_Clocks.PCLK1_Frequency;
+ /* Set frequency bits depending on PCLK1Clock value */
+ freqrange = (u16)(pclk1clock / 1000000);
+ tmpreg |= freqrange;
+ /* Write to I2Cx CR2 */
+ I2Cx->CR2 = tmpreg;
+
+/*---------------------------- I2Cx CCR Configuration ------------------------*/
+ /* Disable I2Cx to configure TRISE */
+ I2C_Cmd(I2Cx, DISABLE);
+
+ /* Reset tmpreg value */
+ /* Clear F/S, DUTY and CCR[11:0] bits */
+ tmpreg = 0;
+
+ /* Configure speed in standard mode */
+ if (I2C_InitStruct->I2C_ClockSpeed <= 100000)
+ {
+ /* Standard mode speed calculate */
+ result = (u16)(pclk1clock / (I2C_InitStruct->I2C_ClockSpeed << 1));
+ /* Test if CCR value is under 0x4*/
+ if (result < 0x04)
+ {
+ /* Set minimum allowed value */
+ result = 0x04;
+ }
+ /* Set speed value for standard mode */
+ tmpreg |= result;
+ /* Set Maximum Rise Time: ((1000/(1000000000/pclk1clock))+1 */
+ I2Cx->TRISE = freqrange + 1;
+ }
+ /* Configure speed in fast mode */
+ else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/
+ {
+ if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)
+ {
+ /* Fast mode speed calculate: Tlow/Thigh = 2 */
+ result = (u16)(pclk1clock / (I2C_InitStruct->I2C_ClockSpeed * 3));
+ }
+ else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/
+ {
+ /* Fast mode speed calculate: Tlow/Thigh = 16/9 */
+ result = (u16)(pclk1clock / (I2C_InitStruct->I2C_ClockSpeed * 25));
+ /* Set DUTY bit */
+ result |= I2C_DutyCycle_16_9;
+ }
+ /* Test if CCR value is under 0x1*/
+ if ((result & CCR_CCR_Set) == 0)
+ {
+ /* Set minimum allowed value */
+ result |= (u16)0x0001;
+ }
+ /* Set speed value and set F/S bit for fast mode */
+ tmpreg |= result | CCR_FS_Set;
+ /* Set Maximum Rise Time: ((300/(1000000000/pclk1clock))+1 */
+ I2Cx->TRISE = (u16)(((freqrange * 300) / 1000) + 1);
+ }
+ /* Write to I2Cx CCR */
+ I2Cx->CCR = tmpreg;
+
+ /* Enable I2Cx */
+ I2C_Cmd(I2Cx, ENABLE);
+
+/*---------------------------- I2Cx CR1 Configuration ------------------------*/
+ /* Get the I2Cx CR1 value */
+ tmpreg = I2Cx->CR1;
+ /* Clear ACK, SMBTYPE and SMBUS bits */
+ tmpreg &= CR1_CLEAR_Mask;
+ /* Configure I2Cx: mode and acknowledgement */
+ /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */
+ /* Set ACK bit according to I2C_Ack value */
+ tmpreg |= (u16)((u32)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);
+ /* Write to I2Cx CR1 */
+ I2Cx->CR1 = tmpreg;
+
+/*---------------------------- I2Cx OAR1 Configuration -----------------------*/
+ /* Set I2Cx Own Address1 and acknowledged address */
+ I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);
+}
+
+/*******************************************************************************
+* Function Name : I2C_StructInit
+* Description : Fills each I2C_InitStruct member with its default value.
+* Input : - I2C_InitStruct: pointer to a I2C_InitTypeDef structure
+* which will be initialized.
+* Output : None
+* Return : None
+*******************************************************************************/
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)
+{
+/*---------------- Reset I2C init structure parameters values ----------------*/
+ /* Initialize the I2C_Mode member */
+ I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
+
+ /* Initialize the I2C_DutyCycle member */
+ I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;
+
+ /* Initialize the I2C_OwnAddress1 member */
+ I2C_InitStruct->I2C_OwnAddress1 = 0;
+
+ /* Initialize the I2C_Ack member */
+ I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
+
+ /* Initialize the I2C_AcknowledgedAddress member */
+ I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
+
+ /* initialize the I2C_ClockSpeed member */
+ I2C_InitStruct->I2C_ClockSpeed = 5000;
+}
+
+/*******************************************************************************
+* Function Name : I2C_Cmd
+* Description : Enables or disables the specified I2C peripheral.
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* - NewState: new state of the I2Cx peripheral. This parameter
+* can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected I2C peripheral */
+ I2Cx->CR1 |= CR1_PE_Set;
+ }
+ else
+ {
+ /* Disable the selected I2C peripheral */
+ I2Cx->CR1 &= CR1_PE_Reset;
+ }
+}
+
+/*******************************************************************************
+* Function Name : I2C_DMACmd
+* Description : Enables or disables the specified I2C DMA requests.
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* - NewState: new state of the I2C DMA transfer.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected I2C DMA requests */
+ I2Cx->CR2 |= CR2_DMAEN_Set;
+ }
+ else
+ {
+ /* Disable the selected I2C DMA requests */
+ I2Cx->CR2 &= CR2_DMAEN_Reset;
+ }
+}
+
+/*******************************************************************************
+* Function Name : I2C_DMALastTransferCmd
+* Description : Specifies that the next DMA transfer is the last one.
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* - NewState: new state of the I2C DMA last transfer.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Next DMA end of transfer is the last transfer */
+ I2Cx->CR2 |= CR2_LAST_Set;
+ }
+ else
+ {
+ /* Next DMA end of transfer is not the last transfer */
+ I2Cx->CR2 &= CR2_LAST_Reset;
+ }
+}
+
+/*******************************************************************************
+* Function Name : I2C_GenerateSTART
+* Description : Generates I2Cx communication START condition.
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* - NewState: new state of the I2C START condition generation.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None.
+*******************************************************************************/
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Generate a START condition */
+ I2Cx->CR1 |= CR1_START_Set;
+ }
+ else
+ {
+ /* Disable the START condition generation */
+ I2Cx->CR1 &= CR1_START_Reset;
+ }
+}
+
+/*******************************************************************************
+* Function Name : I2C_GenerateSTOP
+* Description : Generates I2Cx communication STOP condition.
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* - NewState: new state of the I2C STOP condition generation.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None.
+*******************************************************************************/
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Generate a STOP condition */
+ I2Cx->CR1 |= CR1_STOP_Set;
+ }
+ else
+ {
+ /* Disable the STOP condition generation */
+ I2Cx->CR1 &= CR1_STOP_Reset;
+ }
+}
+
+/*******************************************************************************
+* Function Name : I2C_AcknowledgeConfig
+* Description : Enables or disables the specified I2C acknowledge feature.
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* - NewState: new state of the I2C Acknowledgement.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None.
+*******************************************************************************/
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the acknowledgement */
+ I2Cx->CR1 |= CR1_ACK_Set;
+ }
+ else
+ {
+ /* Disable the acknowledgement */
+ I2Cx->CR1 &= CR1_ACK_Reset;
+ }
+}
+
+/*******************************************************************************
+* Function Name : I2C_OwnAddress2Config
+* Description : Configures the specified I2C own address2.
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* - Address: specifies the 7bit I2C own address2.
+* Output : None
+* Return : None.
+*******************************************************************************/
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, u8 Address)
+{
+ u16 tmpreg = 0;
+
+ /* Get the old register value */
+ tmpreg = I2Cx->OAR2;
+ /* Reset I2Cx Own address2 bit [7:1] */
+ tmpreg &= OAR2_ADD2_Reset;
+ /* Set I2Cx Own address2 */
+ tmpreg |= (u16)(Address & (u16)0x00FE);
+ /* Store the new register value */
+ I2Cx->OAR2 = tmpreg;
+}
+
+/*******************************************************************************
+* Function Name : I2C_DualAddressCmd
+* Description : Enables or disables the specified I2C dual addressing mode.
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* - NewState: new state of the I2C dual addressing mode.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable dual addressing mode */
+ I2Cx->OAR2 |= OAR2_ENDUAL_Set;
+ }
+ else
+ {
+ /* Disable dual addressing mode */
+ I2Cx->OAR2 &= OAR2_ENDUAL_Reset;
+ }
+}
+
+/*******************************************************************************
+* Function Name : I2C_GeneralCallCmd
+* Description : Enables or disables the specified I2C general call feature.
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* - NewState: new state of the I2C General call.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable generall call */
+ I2Cx->CR1 |= CR1_ENGC_Set;
+ }
+ else
+ {
+ /* Disable generall call */
+ I2Cx->CR1 &= CR1_ENGC_Reset;
+ }
+}
+
+/*******************************************************************************
+* Function Name : I2C_ITConfig
+* Description : Enables or disables the specified I2C interrupts.
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* - I2C_IT: specifies the I2C interrupts sources to be enabled
+* or disabled.
+* This parameter can be any combination of the following values:
+* - I2C_IT_BUF: Buffer interrupt mask
+* - I2C_IT_EVT: Event interrupt mask
+* - I2C_IT_ERR: Error interrupt mask
+* - NewState: new state of the specified I2C interrupts.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void I2C_ITConfig(I2C_TypeDef* I2Cx, u16 I2C_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+ assert(IS_I2C_CONFIG_IT(I2C_IT));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected I2C interrupts */
+ I2Cx->CR2 |= I2C_IT;
+ }
+ else
+ {
+ /* Disable the selected I2C interrupts */
+ I2Cx->CR2 &= (u16)~I2C_IT;
+ }
+}
+
+/*******************************************************************************
+* Function Name : I2C_SendData
+* Description : Sends a data byte through the I2Cx peripheral.
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* - Data: Byte to be transmitted..
+* Output : None
+* Return : None
+*******************************************************************************/
+void I2C_SendData(I2C_TypeDef* I2Cx, u8 Data)
+{
+ /* Write in the DR register the data to be sent */
+ I2Cx->DR = Data;
+}
+
+/*******************************************************************************
+* Function Name : I2C_ReceiveData
+* Description : Returns the most recent received data by the I2Cx peripheral.
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* Output : None
+* Return : The value of the received data.
+*******************************************************************************/
+u8 I2C_ReceiveData(I2C_TypeDef* I2Cx)
+{
+ /* Return the data in the DR register */
+ return (u8)I2Cx->DR;
+}
+
+/*******************************************************************************
+* Function Name : I2C_Send7bitAddress
+* Description : Transmits the address byte to select the slave device.
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* - Address: specifies the slave address which will be transmitted
+* - Direction: specifies whether the I2C device will be a
+* Transmitter or a Receiver.
+* This parameter can be one of the following values
+* - I2C_Direction_Transmitter: Transmitter mode
+* - I2C_Direction_Receiver: Receiver mode
+* Output : None
+* Return : None.
+*******************************************************************************/
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, u8 Address, u8 I2C_Direction)
+{
+ /* Check the parameters */
+ assert(IS_I2C_DIRECTION(I2C_Direction));
+
+ /* Test on the direction to set/reset the read/write bit */
+ if (I2C_Direction != I2C_Direction_Transmitter)
+ {
+ /* Set the address ADD0 bit0 for read */
+ Address |= OAR1_ADD0_Set;
+ }
+ else
+ {
+ /* Reset the address bit0 for write */
+ Address &= OAR1_ADD0_Reset;
+ }
+ /* Send the address */
+ I2Cx->DR = Address;
+}
+
+/*******************************************************************************
+* Function Name : I2C_ReadRegister
+* Description : Reads the specified I2C register and returns its value.
+* Input1 : - I2C_Register: specifies the register to read.
+* This parameter can be one of the following values:
+* - I2C_Register_CR1: CR1 register.
+* - I2C_Register_CR2: CR2 register.
+* - I2C_Register_OAR1: OAR1 register.
+* - I2C_Register_OAR2: OAR2 register.
+* - I2C_Register_DR: DR register.
+* - I2C_Register_SR1: SR1 register.
+* - I2C_Register_SR2: SR2 register.
+* - I2C_Register_CCR: CCR register.
+* - I2C_Register_TRISE: TRISE register.
+* Output : None
+* Return : The value of the read register.
+*******************************************************************************/
+u16 I2C_ReadRegister(I2C_TypeDef* I2Cx, u8 I2C_Register)
+{
+ /* Check the parameters */
+ assert(IS_I2C_REGISTER(I2C_Register));
+
+ /* Return the selected register value */
+ return (*(u16 *)(*((u32 *)&I2Cx) + I2C_Register));
+}
+
+/*******************************************************************************
+* Function Name : I2C_SoftwareResetCmd
+* Description : Enables or disables the specified I2C software reset.
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* - NewState: new state of the I2C software reset.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Peripheral under reset */
+ I2Cx->CR1 |= CR1_SWRST_Set;
+ }
+ else
+ {
+ /* Peripheral not under reset */
+ I2Cx->CR1 &= CR1_SWRST_Reset;
+ }
+}
+
+/*******************************************************************************
+* Function Name : I2C_SMBusAlertConfig
+* Description : Drives the SMBusAlert pin high or low for the specified I2C.
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* - I2C_SMBusAlert: specifies SMBAlert pin level.
+* This parameter can be one of the following values:
+* - I2C_SMBusAlert_Low: SMBAlert pin driven low
+* - I2C_SMBusAlert_High: SMBAlert pin driven high
+* Output : None
+* Return : None
+*******************************************************************************/
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, u16 I2C_SMBusAlert)
+{
+ /* Check the parameters */
+ assert(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert));
+
+ if (I2C_SMBusAlert == I2C_SMBusAlert_Low)
+ {
+ /* Drive the SMBusAlert pin Low */
+ I2Cx->CR1 |= I2C_SMBusAlert_Low;
+ }
+ else
+ {
+ /* Drive the SMBusAlert pin High */
+ I2Cx->CR1 &= I2C_SMBusAlert_High;
+ }
+}
+
+/*******************************************************************************
+* Function Name : I2C_TransmitPEC
+* Description : Enables the specified I2C PEC transfer.
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* Output : None
+* Return : None
+*******************************************************************************/
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx)
+{
+ /* Enable the selected I2C PEC transmission */
+ I2Cx->CR1 |= CR1_PEC_Set;
+}
+
+/*******************************************************************************
+* Function Name : I2C_PECPositionConfig
+* Description : Selects the specified I2C PEC position.
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* - I2C_PECPosition: specifies the PEC position.
+* This parameter can be one of the following values:
+* - I2C_PECPosition_Next: PEC bit indicates that current
+* byte is PEC
+* - I2C_PECPosition_Current: PEC bit indicates that the
+* next byte is PEC
+* Output : None
+* Return : None
+*******************************************************************************/
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, u16 I2C_PECPosition)
+{
+ /* Check the parameters */
+ assert(IS_I2C_PEC_POSITION(I2C_PECPosition));
+
+ if (I2C_PECPosition == I2C_PECPosition_Next)
+ {
+ /* PEC indicates that the next byte in shift register is PEC */
+ I2Cx->CR1 |= I2C_PECPosition_Next;
+ }
+ else
+ {
+ /* PEC indicates that the current byte in shift register is PEC */
+ I2Cx->CR1 &= I2C_PECPosition_Current;
+ }
+}
+
+/*******************************************************************************
+* Function Name : I2C_CalculatePEC
+* Description : Enables or disables the PEC value calculation of the
+* transfered bytes.
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* - NewState: new state of the I2Cx PEC value calculation.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected I2C PEC calculation */
+ I2Cx->CR1 |= CR1_ENPEC_Set;
+ }
+ else
+ {
+ /* Disable the selected I2C PEC calculation */
+ I2Cx->CR1 &= CR1_ENPEC_Reset;
+ }
+}
+
+/*******************************************************************************
+* Function Name : I2C_GetPEC
+* Description : Returns the PEC value for the specified I2C.
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* Output : None
+* Return : The PEC value.
+*******************************************************************************/
+u8 I2C_GetPEC(I2C_TypeDef* I2Cx)
+{
+ u8 pec;
+
+ /* Get the PEC value */
+ pec = (I2Cx->SR2) >> 8;
+ /* Return the selected I2C PEC register value */
+ return pec;
+}
+
+/*******************************************************************************
+* Function Name : I2C_ARPCmd
+* Description : Enables or disables the specified I2C ARP.
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* - NewState: new state of the I2Cx ARP.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected I2C ARP */
+ I2Cx->CR1 |= CR1_ENARP_Set;
+ }
+ else
+ {
+ /* Disable the selected I2C ARP */
+ I2Cx->CR1 &= CR1_ENARP_Reset;
+ }
+}
+
+/*******************************************************************************
+* Function Name : I2C_StretchClockCmd
+* Description : Enables or disables the specified I2C Clock stretching.
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* - NewState: new state of the I2Cx Clock stretching.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState == DISABLE)
+ {
+ /* Enable the selected I2C Clock stretching */
+ I2Cx->CR1 |= CR1_NOSTRETCH_Set;
+ }
+ else
+ {
+ /* Disable the selected I2C Clock stretching */
+ I2Cx->CR1 &= CR1_NOSTRETCH_Reset;
+ }
+}
+
+/*******************************************************************************
+* Function Name : I2C_FastModeDutyCycleConfig
+* Description : Selects the specified I2C fast mode duty cycle.
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* - I2C_DutyCycle: specifies the fast mode duty cycle.
+* This parameter can be one of the following values:
+* - I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2
+* - I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9
+* Output : None
+* Return : None
+*******************************************************************************/
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, u16 I2C_DutyCycle)
+{
+ /* Check the parameters */
+ assert(IS_I2C_DUTY_CYCLE(I2C_DutyCycle));
+
+ if (I2C_DutyCycle != I2C_DutyCycle_16_9)
+ {
+ /* I2C fast mode Tlow/Thigh=2 */
+ I2Cx->CCR &= I2C_DutyCycle_2;
+ }
+ else
+ {
+ /* I2C fast mode Tlow/Thigh=16/9 */
+ I2Cx->CCR |= I2C_DutyCycle_16_9;
+ }
+}
+
+/*******************************************************************************
+* Function Name : I2C_GetLastEvent
+* Description : Returns the Last I2C Event.
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* Output : None
+* Return : The last event
+*******************************************************************************/
+u32 I2C_GetLastEvent(I2C_TypeDef* I2Cx)
+{
+ u32 LastEvent = 0;
+ u32 Flag1 = 0, Flag2 = 0;
+
+ Flag1 = I2Cx->SR1;
+ Flag2 = I2Cx->SR2;
+ Flag2 = Flag2 << 16;
+
+ /* Get the last event value from I2C status register */
+ LastEvent = (Flag1 | Flag2) & I2C_FLAG_Mask;
+
+ /* Return status */
+ return LastEvent;
+}
+
+/*******************************************************************************
+* Function Name : I2C_CheckEvent
+* Description : Checks whether the Last I2C Event is equal to the one passed
+* as parameter.
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* - I2C_EVENT: specifies the event to be checked.
+* This parameter can be one of the following values:
+* - I2C_EVENT_SLAVE_ADDRESS_MATCHED : EV1
+* - I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2
+* - I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3
+* - I2C_EVENT_SLAVE_ACK_FAILURE : EV3-1
+* - I2C_EVENT_MASTER_MODE_SELECT : EV5
+* - I2C_EVENT_MASTER_MODE_SELECTED : EV6
+* - I2C_EVENT_MASTER_BYTE_RECEIVED : EV7
+* - I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8
+* - I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9
+* - I2C_EVENT_SLAVE_STOP_DETECTED : EV4
+* Output : None
+* Return : An ErrorStatus enumuration value:
+* - SUCCESS: Last event is equal to the I2C_Event
+* - ERROR: Last event is different from the I2C_Event
+*******************************************************************************/
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, u32 I2C_EVENT)
+{
+ u32 LastEvent = 0;
+ u32 Flag1 = 0, Flag2 = 0;
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert(IS_I2C_EVENT(I2C_EVENT));
+
+ Flag1 = I2Cx->SR1;
+ Flag2 = I2Cx->SR2;
+ Flag2 = Flag2 << 16;
+
+ /* Get the last event value from I2C status register */
+ LastEvent = (Flag1 | Flag2) & I2C_FLAG_Mask;
+
+ /* Check whether the last event is equal to I2C_EVENT */
+ if (LastEvent == I2C_EVENT )
+ {
+ /* SUCCESS: last event is equal to I2C_EVENT */
+ status = SUCCESS;
+ }
+ else
+ {
+ /* ERROR: last event is different from I2C_EVENT */
+ status = ERROR;
+ }
+
+ /* Return status */
+ return status;
+}
+
+/*******************************************************************************
+* Function Name : I2C_GetFlagStatus
+* Description : Checks whether the specified I2C flag is set or not.
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* - I2C_FLAG: specifies the flag to check.
+* This parameter can be one of the following values:
+* - I2C_FLAG_DUALF: Dual flag (Slave mode)
+* - I2C_FLAG_SMBHOST: SMBus host header (Slave mode)
+* - I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode)
+* - I2C_FLAG_GENCALL: General call header flag (Slave mode)
+* - I2C_FLAG_TRA: Transmitter/Receiver flag
+* - I2C_FLAG_BUSY: Bus busy flag
+* - I2C_FLAG_MSL: Master/Slave flag
+* - I2C_FLAG_SMBALERT: SMBus Alert flag
+* - I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
+* - I2C_FLAG_PECERR: PEC error in reception flag
+* - I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
+* - I2C_FLAG_AF: Acknowledge failure flag
+* - I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
+* - I2C_FLAG_BERR: Bus error flag
+* - I2C_FLAG_TXE: Data register empty flag (Transmitter)
+* - I2C_FLAG_RXNE: Data register not empty (Receiver) flag
+* - I2C_FLAG_STOPF: Stop detection flag (Slave mode)
+* - I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)
+* - I2C_FLAG_BTF: Byte transfer finished flag
+* - I2C_FLAG_ADDR: Address sent flag (Master mode) ADSL
+* Address matched flag (Slave mode)ENDAD
+* - I2C_FLAG_SB: Start bit flag (Master mode)
+* Output : None
+* Return : The new state of I2C_FLAG (SET or RESET).
+*******************************************************************************/
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, u32 I2C_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ u32 i2cstatus = 0;
+ u32 Flag1 = 0, Flag2 = 0;
+
+ /* Check the parameters */
+ assert(IS_I2C_GET_FLAG(I2C_FLAG));
+
+ /* Read the I2Cx status register */
+ Flag1 = I2Cx->SR1;
+ Flag2 = I2Cx->SR2;
+ Flag2 = (Flag2 & I2C_FLAG_Mask) << 16;
+
+ /* Get the I2C status value */
+ i2cstatus = Flag1 | Flag2;
+
+ /* Get bit[27:0] of the flag */
+ I2C_FLAG &= I2C_FLAG_Mask;
+
+ /* Check the status of the specified I2C flag */
+ if ((i2cstatus & I2C_FLAG) != (u32)RESET)
+ {
+ /* I2C_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* I2C_FLAG is reset */
+ bitstatus = RESET;
+ }
+ /* Return the I2C_FLAG status */
+ return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name : I2C_ClearFlag
+* Description : Clears the I2Cx's pending flags.
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* - I2C_FLAG: specifies the flag to clear.
+* This parameter can be one of the following values:
+* - I2C_FLAG_SMBALERT: SMBus Alert flag
+* - I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
+* - I2C_FLAG_PECERR: PEC error in reception flag
+* - I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
+* - I2C_FLAG_AF: Acknowledge failure flag
+* - I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
+* - I2C_FLAG_BERR: Bus error flag
+* - I2C_FLAG_STOPF: Stop detection flag (Slave mode)
+* - I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)
+* - I2C_FLAG_BTF: Byte transfer finished flag
+* - I2C_FLAG_ADDR: Address sent flag (Master mode) ADSL
+* Address matched flag (Slave mode)ENDAD
+* - I2C_FLAG_SB: Start bit flag (Master mode)
+* Output : None
+* Return : None
+*******************************************************************************/
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, u32 I2C_FLAG)
+{
+ u32 flagpos = 0;
+ u8 flagindex = 0;
+
+ /* Check the parameters */
+ assert(IS_I2C_CLEAR_FLAG(I2C_FLAG));
+
+ /* Get the I2C flag position */
+ flagpos = I2C_FLAG & I2C_FLAG_Mask;
+
+ /* Get the I2C flag index */
+ flagindex = I2C_FLAG >> 28;
+
+ /* Clear the flag by writing 0 */
+ if (flagindex == 1)
+ {
+ /* Clear the selected I2C flag */
+ I2Cx->SR1 &= ~flagpos;
+ }
+ /* Flags that need a read of the SR1 register to be cleared */
+ else if (flagindex == 2)
+ {
+ /* Read the SR1 register */
+ (void)I2Cx->SR1;
+ }
+ /* Flags that need a read of SR1 and a write on CR2 registers to be cleared */
+ else if (flagindex == 6)
+ {
+ /* Read the SR1 register */
+ (void)I2Cx->SR1;
+
+ /* Write on the CR1 register */
+ I2Cx->CR1 |= CR1_PE_Set;
+ }
+ /* Flags that need a read of SR1 and a write on CR2 registers to be cleared */
+ else /*flagindex == 0xA*/
+ {
+ /* Read the SR1 register */
+ (void)I2Cx->SR1;
+
+ /* Read the SR2 register */
+ (void)I2Cx->SR2;
+ }
+}
+
+/*******************************************************************************
+* Function Name : I2C_GetITStatus
+* Description : Checks whether the specified I2C interrupt has occurred or not.
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* - I2C_IT: specifies the interrupt source to check.
+* This parameter can be one of the following values:
+* - I2C_IT_SMBALERT: SMBus Alert flag
+* - I2C_IT_TIMEOUT: Timeout or Tlow error flag
+* - I2C_IT_PECERR: PEC error in reception flag
+* - I2C_IT_OVR: Overrun/Underrun flag (Slave mode)
+* - I2C_IT_AF: Acknowledge failure flag
+* - I2C_IT_ARLO: Arbitration lost flag (Master mode)
+* - I2C_IT_BERR: Bus error flag
+* - I2C_IT_TXE: Data register empty flag (Transmitter)
+* - I2C_IT_RXNE: Data register not empty (Receiver) flag
+* - I2C_IT_STOPF: Stop detection flag (Slave mode)
+* - I2C_IT_ADD10: 10-bit header sent flag (Master mode)
+* - I2C_IT_BTF: Byte transfer finished flag
+* - I2C_IT_ADDR: Address sent flag (Master mode) ADSL
+* Address matched flag (Slave mode)ENDAD
+* - I2C_IT_SB: Start bit flag (Master mode)
+* Output : None
+* Return : The new state of I2C_IT (SET or RESET).
+*******************************************************************************/
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, u32 I2C_IT)
+{
+ ITStatus bitstatus = RESET;
+ u32 i2cstatus = 0;
+ u32 Flag1 = 0, Flag2 = 0;
+
+ /* Check the parameters */
+ assert(IS_I2C_GET_IT(I2C_IT));
+
+ /* Read the I2Cx status register */
+ Flag1 = I2Cx->SR1;
+ Flag2 = I2Cx->SR2;
+ Flag2 = (Flag2 & I2C_FLAG_Mask) << 16;
+
+ /* Get the I2C status value */
+ i2cstatus = Flag1 | Flag2;
+
+ /* Get bit[27:0] of the flag */
+ I2C_IT &= I2C_FLAG_Mask;
+
+ /* Check the status of the specified I2C flag */
+ if ((i2cstatus & I2C_IT) != (u32)RESET)
+ {
+ /* I2C_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* I2C_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the I2C_IT status */
+ return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name : I2C_ClearITPendingBit
+* Description : Clears the I2Cxs interrupt pending bits.
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* - I2C_IT: specifies the interrupt pending to clear.
+* This parameter can be one of the following values:
+* - I2C_IT_SMBALERT: SMBus Alert flag
+* - I2C_IT_TIMEOUT: Timeout or Tlow error flag
+* - I2C_IT_PECERR: PEC error in reception flag
+* - I2C_IT_OVR: Overrun/Underrun flag (Slave mode)
+* - I2C_IT_AF: Acknowledge failure flag
+* - I2C_IT_ARLO: Arbitration lost flag (Master mode)
+* - I2C_IT_BERR: Bus error flag
+* - I2C_IT_STOPF: Stop detection flag (Slave mode)
+* - I2C_IT_ADD10: 10-bit header sent flag (Master mode)
+* - I2C_IT_BTF: Byte transfer finished flag
+* - I2C_IT_ADDR: Address sent flag (Master mode) ADSL
+* Address matched flag (Slave mode)ENDAD
+* - I2C_IT_SB: Start bit flag (Master mode)
+* Output : None
+* Return : None
+*******************************************************************************/
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, u32 I2C_IT)
+{
+ u32 flagpos = 0;
+ u8 flagindex = 0;
+
+ /* Check the parameters */
+ assert(IS_I2C_CLEAR_IT(I2C_IT));
+
+ /* Get the I2C flag position */
+ flagpos = I2C_IT & I2C_FLAG_Mask;
+
+ /* Get the I2C flag index */
+ flagindex = I2C_IT >> 28;
+
+ /* Clear the flag by writing 0 */
+ if (flagindex == 1)
+ {
+ /* Clear the selected I2C flag */
+ I2Cx->SR1 &= ~flagpos;
+ }
+ /* Flags that need a read of the SR1 register to be cleared */
+ else if (flagindex == 2)
+ {
+ /* Read the SR1 register */
+ (void)I2Cx->SR1;
+ }
+ /* Flags that need a read of SR1 and a write on CR2 registers to be cleared */
+ else if (flagindex == 6)
+ {
+ /* Read the SR1 register */
+ (void)I2Cx->SR1;
+
+ /* Write on the CR1 register */
+ I2Cx->CR1 |= CR1_PE_Set;
+ }
+ /* Flags that need a read of SR1 and a write on CR2 registers to be cleared */
+ else /*flagindex == 0xA*/
+ {
+ /* Read the SR1 register */
+ (void)I2Cx->SR1;
+
+ /* Read the SR2 register */
+ (void)I2Cx->SR2;
+ }
+}
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_iwdg.c b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_iwdg.c
new file mode 100644
index 0000000..496e68d
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_iwdg.c
@@ -0,0 +1,152 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_iwdg.c
+* Author : MCD Application Team
+* Date First Issued : 09/29/2006
+* Description : This file provides all the IWDG firmware functions.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_iwdg.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* ---------------------- IWDG registers bit mask ------------------------ */
+/* KR register bit mask */
+#define KR_Reload ((u16)0xAAAA)
+#define KR_Enable ((u16)0xCCCC)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name : IWDG_WriteAccessCmd
+* Description : Enables or disables write access to IWDG_PR and IWDG_RLR
+* registers.
+* Input : - IWDG_WriteAccess: new state of write access to IWDG_PR and
+* IWDG_RLR registers.
+* This parameter can be one of the following values:
+* - IWDG_WriteAccess_Enable: Enable write access to
+* IWDG_PR and IWDG_RLR registers
+* - IWDG_WriteAccess_Disable: Disable write access to
+* IWDG_PR and IWDG_RLR registers
+* Output : None
+* Return : None
+*******************************************************************************/
+void IWDG_WriteAccessCmd(u16 IWDG_WriteAccess)
+{
+ /* Check the parameters */
+ assert(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
+
+ IWDG->KR = IWDG_WriteAccess;
+}
+
+/*******************************************************************************
+* Function Name : IWDG_SetPrescaler
+* Description : Sets IWDG Prescaler value.
+* Input : - IWDG_Prescaler: specifies the IWDG Prescaler value.
+* This parameter can be one of the following values:
+* - IWDG_Prescaler_4: IWDG prescaler set to 4
+* - IWDG_Prescaler_8: IWDG prescaler set to 8
+* - IWDG_Prescaler_16: IWDG prescaler set to 16
+* - IWDG_Prescaler_32: IWDG prescaler set to 32
+* - IWDG_Prescaler_64: IWDG prescaler set to 64
+* - IWDG_Prescaler_128: IWDG prescaler set to 128
+* - IWDG_Prescaler_256: IWDG prescaler set to 256
+* Output : None
+* Return : None
+*******************************************************************************/
+void IWDG_SetPrescaler(u8 IWDG_Prescaler)
+{
+ /* Check the parameters */
+ assert(IS_IWDG_PRESCALER(IWDG_Prescaler));
+
+ IWDG->PR = IWDG_Prescaler;
+}
+
+/*******************************************************************************
+* Function Name : IWDG_SetReload
+* Description : Sets IWDG Reload value.
+* Input : - Reload: specifies the IWDG Reload value.
+* This parameter must be a number between 0 and 0x0FFF.
+* Output : None
+* Return : None
+*******************************************************************************/
+void IWDG_SetReload(u16 Reload)
+{
+ /* Check the parameters */
+ assert(IS_IWDG_RELOAD(Reload));
+
+ IWDG->RLR = Reload;
+}
+
+/*******************************************************************************
+* Function Name : IWDG_ReloadCounter
+* Description : Reloads IWDG counter with value defined in the reload register
+* (write access to IWDG_PR and IWDG_RLR registers disabled).
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void IWDG_ReloadCounter(void)
+{
+ IWDG->KR = KR_Reload;
+}
+
+/*******************************************************************************
+* Function Name : IWDG_Enable
+* Description : Enables IWDG (write access to IWDG_PR and IWDG_RLR registers
+* disabled).
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void IWDG_Enable(void)
+{
+ IWDG->KR = KR_Enable;
+}
+
+/*******************************************************************************
+* Function Name : IWDG_GetFlagStatus
+* Description : Checks whether the specified IWDG flag is set or not.
+* Input : - IWDG_FLAG: specifies the flag to check.
+* This parameter can be one of the following values:
+* - IWDG_FLAG_PVU: Prescaler Value Update on going
+* - IWDG_FLAG_RVU: Reload Value Update on going
+* Output : None
+* Return : The new state of IWDG_FLAG (SET or RESET).
+*******************************************************************************/
+FlagStatus IWDG_GetFlagStatus(u16 IWDG_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert(IS_IWDG_FLAG(IWDG_FLAG));
+
+ if ((IWDG->SR & IWDG_FLAG) != (u32)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+
+ /* Return the flag status */
+ return bitstatus;
+}
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_lib.c b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_lib.c
new file mode 100644
index 0000000..7df2cb8
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_lib.c
@@ -0,0 +1,221 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_lib.c
+* Author : MCD Application Team
+* Date First Issued : 09/29/2006
+* Description : This file provides all peripherals pointers initialization.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+#define EXT
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_lib.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+#ifdef DEBUG
+/*******************************************************************************
+* Function Name : debug
+* Description : This function initialize peripherals pointers.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void debug(void)
+{
+
+/************************************* ADC ************************************/
+#ifdef _ADC1
+ ADC1 = (ADC_TypeDef *) ADC1_BASE;
+#endif /*_ADC1 */
+
+#ifdef _ADC2
+ ADC2 = (ADC_TypeDef *) ADC2_BASE;
+#endif /*_ADC2 */
+
+/************************************* BKP ************************************/
+#ifdef _BKP
+ BKP = (BKP_TypeDef *) BKP_BASE;
+#endif /*_BKP */
+
+/************************************* CAN ************************************/
+#ifdef _CAN
+ CAN = (CAN_TypeDef *) CAN_BASE;
+#endif /*_CAN */
+
+/************************************* DMA ************************************/
+#ifdef _DMA
+ DMA = (DMA_TypeDef *) DMA_BASE;
+#endif /*_DMA */
+
+#ifdef _DMA_Channel1
+ DMA_Channel1 = (DMA_Channel_TypeDef *) DMA_Channel1_BASE;
+#endif /*_DMA_Channel1 */
+
+#ifdef _DMA_Channel2
+ DMA_Channel2 = (DMA_Channel_TypeDef *) DMA_Channel2_BASE;
+#endif /*_DMA_Channel2 */
+
+#ifdef _DMA_Channel3
+ DMA_Channel3 = (DMA_Channel_TypeDef *) DMA_Channel3_BASE;
+#endif /*_DMA_Channel3 */
+
+#ifdef _DMA_Channel4
+ DMA_Channel4 = (DMA_Channel_TypeDef *) DMA_Channel4_BASE;
+#endif /*_DMA_Channel4 */
+
+#ifdef _DMA_Channel5
+ DMA_Channel5 = (DMA_Channel_TypeDef *) DMA_Channel5_BASE;
+#endif /*_DMA_Channel5 */
+
+#ifdef _DMA_Channel6
+ DMA_Channel6 = (DMA_Channel_TypeDef *) DMA_Channel6_BASE;
+#endif /*_DMA_Channel6 */
+
+#ifdef _DMA_Channel7
+ DMA_Channel7 = (DMA_Channel_TypeDef *) DMA_Channel7_BASE;
+#endif /*_DMA_Channel7 */
+
+/************************************* EXTI ***********************************/
+#ifdef _EXTI
+ EXTI = (EXTI_TypeDef *) EXTI_BASE;
+#endif /*_EXTI */
+
+/************************************* FLASH and Option Bytes *****************/
+#ifdef _FLASH
+ FLASH = (FLASH_TypeDef *) FLASH_BASE;
+ OB = (OB_TypeDef *) OB_BASE;
+#endif /*_FLASH */
+
+/************************************* GPIO ***********************************/
+#ifdef _GPIOA
+ GPIOA = (GPIO_TypeDef *) GPIOA_BASE;
+#endif /*_GPIOA */
+
+#ifdef _GPIOB
+ GPIOB = (GPIO_TypeDef *) GPIOB_BASE;
+#endif /*_GPIOB */
+
+#ifdef _GPIOC
+ GPIOC = (GPIO_TypeDef *) GPIOC_BASE;
+#endif /*_GPIOC */
+
+#ifdef _GPIOD
+ GPIOD = (GPIO_TypeDef *) GPIOD_BASE;
+#endif /*_GPIOD */
+
+#ifdef _GPIOE
+ GPIOE = (GPIO_TypeDef *) GPIOE_BASE;
+#endif /*_GPIOE */
+
+#ifdef _AFIO
+ AFIO = (AFIO_TypeDef *) AFIO_BASE;
+#endif /*_AFIO */
+
+/************************************* I2C ************************************/
+#ifdef _I2C1
+ I2C1 = (I2C_TypeDef *) I2C1_BASE;
+#endif /*_I2C1 */
+
+#ifdef _I2C2
+ I2C2 = (I2C_TypeDef *) I2C2_BASE;
+#endif /*_I2C2 */
+
+/************************************* IWDG ***********************************/
+#ifdef _IWDG
+ IWDG = (IWDG_TypeDef *) IWDG_BASE;
+#endif /*_IWDG */
+
+/************************************* NVIC ***********************************/
+#ifdef _NVIC
+ NVIC = (NVIC_TypeDef *) NVIC_BASE;
+#endif /*_NVIC */
+
+#ifdef _SCB
+ SCB = (SCB_TypeDef *) SCB_BASE;
+#endif /*_SCB */
+
+/************************************* PWR ************************************/
+#ifdef _PWR
+ PWR = (PWR_TypeDef *) PWR_BASE;
+#endif /*_PWR */
+
+/************************************* RCC ************************************/
+#ifdef _RCC
+ RCC = (RCC_TypeDef *) RCC_BASE;
+#endif /*_RCC */
+
+/************************************* RTC ************************************/
+#ifdef _RTC
+ RTC = (RTC_TypeDef *) RTC_BASE;
+#endif /*_RTC */
+
+/************************************* SPI ************************************/
+#ifdef _SPI1
+ SPI1 = (SPI_TypeDef *) SPI1_BASE;
+#endif /*_SPI1 */
+
+#ifdef _SPI2
+ SPI2 = (SPI_TypeDef *) SPI2_BASE;
+#endif /*_SPI2 */
+
+/************************************* SysTick ********************************/
+#ifdef _SysTick
+ SysTick = (SysTick_TypeDef *) SysTick_BASE;
+#endif /*_SysTick */
+
+/************************************* TIM1 ***********************************/
+#ifdef _TIM1
+ TIM1 = (TIM1_TypeDef *) TIM1_BASE;
+#endif /*_TIM1 */
+
+/************************************* TIM ************************************/
+#ifdef _TIM2
+ TIM2 = (TIM_TypeDef *) TIM2_BASE;
+#endif /*_TIM2 */
+
+#ifdef _TIM3
+ TIM3 = (TIM_TypeDef *) TIM3_BASE;
+#endif /*_TIM3 */
+
+#ifdef _TIM4
+ TIM4 = (TIM_TypeDef *) TIM4_BASE;
+#endif /*_TIM4 */
+
+/************************************* USART **********************************/
+#ifdef _USART1
+ USART1 = (USART_TypeDef *) USART1_BASE;
+#endif /*_USART1 */
+
+#ifdef _USART2
+ USART2 = (USART_TypeDef *) USART2_BASE;
+#endif /*_USART2 */
+
+#ifdef _USART3
+ USART3 = (USART_TypeDef *) USART3_BASE;
+#endif /*_USART3 */
+
+/************************************* WWDG ***********************************/
+#ifdef _WWDG
+ WWDG = (WWDG_TypeDef *) WWDG_BASE;
+#endif /*_WWDG */
+}
+#endif
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_nvic.c b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_nvic.c
new file mode 100644
index 0000000..79bb867
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_nvic.c
@@ -0,0 +1,755 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_nvic.c
+* Author : MCD Application Team
+* Date First Issued : 09/29/2006
+* Description : This file provides all the NVIC firmware functions.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_nvic.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define AIRC_VECTKEY_MASK ((u32)0x05FA0000)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name : NVIC_DeInit
+* Description : Deinitializes the NVIC peripheral registers to their default
+* reset values.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void NVIC_DeInit(void)
+{
+ u32 index = 0;
+
+ NVIC->Disable[0] = 0xFFFFFFFF;
+ NVIC->Disable[1] = 0x000007FF;
+ NVIC->Clear[0] = 0xFFFFFFFF;
+ NVIC->Clear[1] = 0x000007FF;
+
+ for(index = 0; index < 0x0B; index++)
+ {
+ NVIC->Priority[index] = 0x00000000;
+ }
+}
+
+/*******************************************************************************
+* Function Name : NVIC_SCBDeInit
+* Description : Deinitializes the SCB peripheral registers to their default
+* reset values.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void NVIC_SCBDeInit(void)
+{
+ u32 index = 0x00;
+
+ SCB->IRQControlState = 0x0A000000;
+ SCB->ExceptionTableOffset = 0x00000000;
+ SCB->AIRC = AIRC_VECTKEY_MASK;
+ SCB->SysCtrl = 0x00000000;
+ SCB->ConfigCtrl = 0x00000000;
+ for(index = 0; index < 0x03; index++)
+ {
+ SCB->SystemPriority[index] = 0;
+ }
+ SCB->SysHandlerCtrl = 0x00000000;
+ SCB->ConfigFaultStatus = 0xFFFFFFFF;
+ SCB->HardFaultStatus = 0xFFFFFFFF;
+ SCB->DebugFaultStatus = 0xFFFFFFFF;
+}
+
+/*******************************************************************************
+* Function Name : NVIC_PriorityGroupConfig
+* Description : Configures the priority grouping: pre-emption priority
+* and subpriority.
+* Input : - NVIC_PriorityGroup: specifies the priority grouping bits
+* length. This parameter can be one of the following values:
+* - NVIC_PriorityGroup_0: 0 bits for pre-emption priority
+* 4 bits for subpriority
+* - NVIC_PriorityGroup_1: 1 bits for pre-emption priority
+* 3 bits for subpriority
+* - NVIC_PriorityGroup_2: 2 bits for pre-emption priority
+* 2 bits for subpriority
+* - NVIC_PriorityGroup_3: 3 bits for pre-emption priority
+* 1 bits for subpriority
+* - NVIC_PriorityGroup_4: 4 bits for pre-emption priority
+* 0 bits for subpriority
+* Output : None
+* Return : None
+*******************************************************************************/
+void NVIC_PriorityGroupConfig(u32 NVIC_PriorityGroup)
+{
+ /* Check the parameters */
+ assert(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
+
+ /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
+ SCB->AIRC = AIRC_VECTKEY_MASK | NVIC_PriorityGroup;
+}
+
+/*******************************************************************************
+* Function Name : NVIC_Init
+* Description : Initializes the NVIC peripheral according to the specified
+* parameters in the NVIC_InitStruct.
+* Input : - NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure
+* that contains the configuration information for the
+* specified NVIC peripheral.
+* Output : None
+* Return : None
+*******************************************************************************/
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
+{
+ u32 tmppriority = 0x00, tmpreg = 0x00, tmpmask = 0x00;
+ u32 tmppre = 0, tmpsub = 0x0F;
+
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
+ assert(IS_NVIC_IRQ_CHANNEL(NVIC_InitStruct->NVIC_IRQChannel));
+ assert(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
+ assert(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
+
+ if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
+ {
+ /* Compute the Corresponding IRQ Priority --------------------------------*/
+ tmppriority = (0x700 - (SCB->AIRC & (u32)0x700))>> 0x08;
+ tmppre = (0x4 - tmppriority);
+ tmpsub = tmpsub >> tmppriority;
+
+ tmppriority = (u32)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
+ tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
+
+ tmppriority = tmppriority << 0x04;
+ tmppriority = ((u32)tmppriority) << ((NVIC_InitStruct->NVIC_IRQChannel & (u8)0x03) * 0x08);
+
+ tmpreg = NVIC->Priority[(NVIC_InitStruct->NVIC_IRQChannel >> 0x02)];
+ tmpmask = (u32)0xFF << ((NVIC_InitStruct->NVIC_IRQChannel & (u8)0x03) * 0x08);
+ tmpreg &= ~tmpmask;
+ tmppriority &= tmpmask;
+ tmpreg |= tmppriority;
+
+ NVIC->Priority[(NVIC_InitStruct->NVIC_IRQChannel >> 0x02)] = tmpreg;
+
+ /* Enable the Selected IRQ Channels --------------------------------------*/
+ NVIC->Enable[(NVIC_InitStruct->NVIC_IRQChannel >> 0x05)] =
+ (u32)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (u8)0x1F);
+ }
+ else
+ {
+ /* Disable the Selected IRQ Channels -------------------------------------*/
+ NVIC->Disable[(NVIC_InitStruct->NVIC_IRQChannel >> 0x05)] =
+ (u32)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (u8)0x1F);
+ }
+}
+
+/*******************************************************************************
+* Function Name : NVIC_StructInit
+* Description : Fills each NVIC_InitStruct member with its default value.
+* Input : - NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure which
+* will be initialized.
+* Output : None
+* Return : None
+*******************************************************************************/
+void NVIC_StructInit(NVIC_InitTypeDef* NVIC_InitStruct)
+{
+ /* NVIC_InitStruct members default value */
+ NVIC_InitStruct->NVIC_IRQChannel = 0x00;
+ NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority = 0x00;
+ NVIC_InitStruct->NVIC_IRQChannelSubPriority = 0x00;
+ NVIC_InitStruct->NVIC_IRQChannelCmd = DISABLE;
+}
+
+/*******************************************************************************
+* Function Name : NVIC_SETPRIMASK
+* Description : Enables the PRIMASK priority: Raises the execution priority to 0.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void NVIC_SETPRIMASK(void)
+{
+ __SETPRIMASK();
+}
+
+/*******************************************************************************
+* Function Name : NVIC_RESETPRIMASK
+* Description : Disables the PRIMASK priority.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void NVIC_RESETPRIMASK(void)
+{
+ __RESETPRIMASK();
+}
+
+/*******************************************************************************
+* Function Name : NVIC_SETFAULTMASK
+* Description : Enables the FAULTMASK priority: Raises the execution priority to -1.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void NVIC_SETFAULTMASK(void)
+{
+ __SETFAULTMASK();
+}
+
+/*******************************************************************************
+* Function Name : NVIC_RESETFAULTMASK
+* Description : Disables the FAULTMASK priority.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void NVIC_RESETFAULTMASK(void)
+{
+ __RESETFAULTMASK();
+}
+
+/*******************************************************************************
+* Function Name : NVIC_BASEPRICONFIG
+* Description : The execution priority can be changed from 15 (lowest
+ configurable priority) to 1.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void NVIC_BASEPRICONFIG(u32 NewPriority)
+{
+ /* Check the parameters */
+ assert(IS_NVIC_BASE_PRI(NewPriority));
+
+ __BASEPRICONFIG(NewPriority << 0x04);
+}
+
+/*******************************************************************************
+* Function Name : NVIC_GetBASEPRI
+* Description : Returns the BASEPRI mask value.
+* Input : None
+* Output : None
+* Return : BASEPRI register value
+*******************************************************************************/
+u32 NVIC_GetBASEPRI(void)
+{
+ return (__GetBASEPRI());
+}
+
+/*******************************************************************************
+* Function Name : NVIC_GetCurrentPendingIRQChannel
+* Description : Returns the current pending IRQ channel identifier.
+* Input : None
+* Output : None
+* Return : Pending IRQ Channel Identifier.
+*******************************************************************************/
+u16 NVIC_GetCurrentPendingIRQChannel(void)
+{
+ return ((u16)((SCB->IRQControlState & (u32)0x003FF000) >> 0x0C));
+}
+
+/*******************************************************************************
+* Function Name : NVIC_GetIRQChannelPendingBitStatus
+* Description : Checks whether the specified IRQ Channel pending bit is set
+* or not.
+* Input : - NVIC_IRQChannel: specifies the interrupt pending bit to check.
+* Output : None
+* Return : The new state of IRQ Channel pending bit(SET or RESET).
+*******************************************************************************/
+ITStatus NVIC_GetIRQChannelPendingBitStatus(u8 NVIC_IRQChannel)
+{
+ ITStatus pendingirqstatus = RESET;
+ u32 tmp = 0x00;
+
+ /* Check the parameters */
+ assert(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel));
+
+ tmp = ((u32)0x01 << (NVIC_IRQChannel & (u32)0x1F));
+
+ if (((NVIC->Set[(NVIC_IRQChannel >> 0x05)]) & tmp) == tmp)
+ {
+ pendingirqstatus = SET;
+ }
+ else
+ {
+ pendingirqstatus = RESET;
+ }
+ return pendingirqstatus;
+}
+
+/*******************************************************************************
+* Function Name : NVIC_SetIRQChannelPendingBit
+* Description : Sets the NVICs interrupt pending bit.
+* Input : - NVIC_IRQChannel: specifies the interrupt pending bit to Set.
+* Output : None
+* Return : None
+*******************************************************************************/
+void NVIC_SetIRQChannelPendingBit(u8 NVIC_IRQChannel)
+{
+ /* Check the parameters */
+ assert(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel));
+
+ *(u32*)0xE000EF00 = (u32)NVIC_IRQChannel;
+}
+
+/*******************************************************************************
+* Function Name : NVIC_ClearIRQChannelPendingBit
+* Description : Clears the NVICs interrupt pending bit.
+* Input : - NVIC_IRQChannel: specifies the interrupt pending bit to clear.
+* Output : None
+* Return : None
+*******************************************************************************/
+void NVIC_ClearIRQChannelPendingBit(u8 NVIC_IRQChannel)
+{
+ /* Check the parameters */
+ assert(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel));
+
+ NVIC->Clear[(NVIC_IRQChannel >> 0x05)] = (u32)0x01 << (NVIC_IRQChannel & (u32)0x1F);
+}
+
+/*******************************************************************************
+* Function Name : NVIC_GetCurrentActiveHandler
+* Description : Returns the current active Handler (IRQ Channel and
+* SystemHandler) identifier.
+* Input : None
+* Output : None
+* Return : Active Handler Identifier.
+*******************************************************************************/
+u16 NVIC_GetCurrentActiveHandler(void)
+{
+ return ((u16)(SCB->IRQControlState & (u32)0x3FF));
+}
+
+/*******************************************************************************
+* Function Name : NVIC_GetIRQChannelActiveBitStatus
+* Description : Checks whether the specified IRQ Channel active bit is set
+* or not.
+* Input : - NVIC_IRQChannel: specifies the interrupt active bit to check.
+* Output : None
+* Return : The new state of IRQ Channel active bit(SET or RESET).
+*******************************************************************************/
+ITStatus NVIC_GetIRQChannelActiveBitStatus(u8 NVIC_IRQChannel)
+{
+ ITStatus activeirqstatus = RESET;
+ u32 tmp = 0x00;
+
+ /* Check the parameters */
+ assert(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel));
+
+ tmp = ((u32)0x01 << (NVIC_IRQChannel & (u32)0x1F));
+
+ if (((NVIC->Active[(NVIC_IRQChannel >> 0x05)]) & tmp) == tmp )
+ {
+ activeirqstatus = SET;
+ }
+ else
+ {
+ activeirqstatus = RESET;
+ }
+ return activeirqstatus;
+}
+
+/*******************************************************************************
+* Function Name : NVIC_GetCPUID
+* Description : Returns the ID number, the version number and the implementation
+* details of the Cortex-M3 core.
+* Input : None
+* Output : None
+* Return : CPU ID.
+*******************************************************************************/
+u32 NVIC_GetCPUID(void)
+{
+ return (SCB->CPUID);
+}
+
+/*******************************************************************************
+* Function Name : NVIC_SetVectorTable
+* Description : Sets the vector table location and Offset.
+* Input : - NVIC_VectTab: specifies if the vector table is in RAM or
+* code memory.
+* This parameter can be one of the following values:
+* - NVIC_VectTab_RAM
+* - NVIC_VectTab_FLASH
+* - Offset: Vector Table base offset field.
+* Output : None
+* Return : None
+*******************************************************************************/
+void NVIC_SetVectorTable(u32 NVIC_VectTab, u32 Offset)
+{
+ /* Check the parameters */
+ assert(IS_NVIC_VECTTAB(NVIC_VectTab));
+ assert(IS_NVIC_OFFSET(Offset));
+
+ SCB->ExceptionTableOffset = (((u32)Offset << 0x07) & (u32)0x1FFFFF80);
+
+ SCB->ExceptionTableOffset |= NVIC_VectTab;
+}
+
+/*******************************************************************************
+* Function Name : NVIC_GenerateSystemReset
+* Description : Generates a system reset.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void NVIC_GenerateSystemReset(void)
+{
+ SCB->AIRC = AIRC_VECTKEY_MASK | (u32)0x04;
+}
+
+/*******************************************************************************
+* Function Name : NVIC_GenerateCoreReset
+* Description : Generates a Core (Core + NVIC) reset.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void NVIC_GenerateCoreReset(void)
+{
+ SCB->AIRC = AIRC_VECTKEY_MASK | (u32)0x01;
+}
+
+/*******************************************************************************
+* Function Name : NVIC_SystemLPConfig
+* Description : Selects the condition for the system to enter low power mode.
+* Input : - LowPowerMode: Specifies the new mode for the system to enter
+* low power mode.
+* This parameter can be one of the following values:
+* - NVIC_LP_SEVONPEND
+* - NVIC_LP_SLEEPDEEP
+* - NVIC_LP_SLEEPONEXIT
+* - NewState: new state of LP condition.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void NVIC_SystemLPConfig(u8 LowPowerMode, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_NVIC_LP(LowPowerMode));
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ SCB->SysCtrl |= LowPowerMode;
+ }
+ else
+ {
+ SCB->SysCtrl &= (u32)(~(u32)LowPowerMode);
+ }
+}
+
+/*******************************************************************************
+* Function Name : NVIC_SystemHandlerConfig
+* Description : Enables or disables the specified System Handlers.
+* Input : - SystemHandler: specifies the system handler to be enabled
+* or disabled.
+* This parameter can be one of the following values:
+* - SystemHandler_MemoryManage
+* - SystemHandler_BusFault
+* - SystemHandler_UsageFault
+* - NewState: new state of specified System Handlers.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void NVIC_SystemHandlerConfig(u32 SystemHandler, FunctionalState NewState)
+{
+ u32 tmpreg = 0x00;
+
+ /* Check the parameters */
+ assert(IS_CONFIG_SYSTEM_HANDLER(SystemHandler));
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ tmpreg = (u32)0x01 << (SystemHandler & (u32)0x1F);
+
+ if (NewState != DISABLE)
+ {
+ SCB->SysHandlerCtrl |= tmpreg;
+ }
+ else
+ {
+ SCB->SysHandlerCtrl &= ~tmpreg;
+ }
+}
+
+/*******************************************************************************
+* Function Name : NVIC_SystemHandlerPriorityConfig
+* Description : Configures the specified System Handlers priority.
+* Input : - SystemHandler: specifies the system handler to be
+* enabled or disabled.
+* This parameter can be one of the following values:
+* - SystemHandler_MemoryManage
+* - SystemHandler_BusFault
+* - SystemHandler_UsageFault
+* - SystemHandler_SVCall
+* - SystemHandler_DebugMonitor
+* - SystemHandler_PSV
+* - SystemHandler_SysTick
+* - SystemHandlerPreemptionPriority: new priority group of the
+* specified system handlers.
+* - SystemHandlerSubPriority: new sub priority of the specified
+* system handlers.
+* Output : None
+* Return : None
+*******************************************************************************/
+void NVIC_SystemHandlerPriorityConfig(u32 SystemHandler, u8 SystemHandlerPreemptionPriority,
+ u8 SystemHandlerSubPriority)
+{
+ u32 tmp1 = 0x00, tmp2 = 0xFF, handlermask = 0x00;
+ u32 tmppriority = 0x00;
+
+ /* Check the parameters */
+ assert(IS_PRIORITY_SYSTEM_HANDLER(SystemHandler));
+ assert(IS_NVIC_PREEMPTION_PRIORITY(SystemHandlerPreemptionPriority));
+ assert(IS_NVIC_SUB_PRIORITY(SystemHandlerSubPriority));
+
+ tmppriority = (0x700 - (SCB->AIRC & (u32)0x700))>> 0x08;
+ tmp1 = (0x4 - tmppriority);
+ tmp2 = tmp2 >> tmppriority;
+
+ tmppriority = (u32)SystemHandlerPreemptionPriority << tmp1;
+ tmppriority |= SystemHandlerSubPriority & tmp2;
+
+ tmppriority = tmppriority << 0x04;
+ tmp1 = SystemHandler & (u32)0xC0;
+ tmp1 = tmp1 >> 0x06;
+ tmp2 = (SystemHandler >> 0x08) & (u32)0x03;
+ tmppriority = tmppriority << (tmp2 * 0x08);
+ handlermask = (u32)0xFF << (tmp2 * 0x08);
+
+ SCB->SystemPriority[tmp1] &= ~handlermask;
+ SCB->SystemPriority[tmp1] |= tmppriority;
+}
+
+/*******************************************************************************
+* Function Name : NVIC_GetSystemHandlerPendingBitStatus
+* Description : Checks whether the specified System handlers pending bit is
+* set or not.
+* Input : - SystemHandler: specifies the system handler pending bit to
+* check.
+* This parameter can be one of the following values:
+* - SystemHandler_MemoryManage
+* - SystemHandler_BusFault
+* - SystemHandler_SVCall
+* Output : None
+* Return : The new state of System Handler pending bit(SET or RESET).
+*******************************************************************************/
+ITStatus NVIC_GetSystemHandlerPendingBitStatus(u32 SystemHandler)
+{
+ ITStatus bitstatus = RESET;
+ u32 tmp = 0x00, tmppos = 0x00;
+
+ /* Check the parameters */
+ assert(IS_GET_PENDING_SYSTEM_HANDLER(SystemHandler));
+
+ tmppos = (SystemHandler >> 0x0A);
+ tmppos &= (u32)0x0F;
+
+ tmppos = (u32)0x01 << tmppos;
+
+ tmp = SCB->SysHandlerCtrl & tmppos;
+
+ if (tmp == tmppos)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name : NVIC_SetSystemHandlerPendingBit
+* Description : Sets System Handler pending bit.
+* Input : - SystemHandler: specifies the system handler pending bit
+* to be set.
+* This parameter can be one of the following values:
+* - SystemHandler_NMI
+* - SystemHandler_PSV
+* - SystemHandler_SysTick
+* Output : None
+* Return : None
+*******************************************************************************/
+void NVIC_SetSystemHandlerPendingBit(u32 SystemHandler)
+{
+ u32 tmp = 0x00;
+
+ /* Check the parameters */
+ assert(IS_SET_PENDING_SYSTEM_HANDLER(SystemHandler));
+
+ /* Get the System Handler pending bit position */
+ tmp = SystemHandler & (u32)0x1F;
+ /* Set the corresponding System Handler pending bit */
+ SCB->IRQControlState |= ((u32)0x01 << tmp);
+}
+
+/*******************************************************************************
+* Function Name : NVIC_ClearSystemHandlerPendingBit
+* Description : Clears System Handler pending bit.
+* Input : - SystemHandler: specifies the system handler pending bit to
+* be clear.
+* This parameter can be one of the following values:
+* - SystemHandler_PSV
+* - SystemHandler_SysTick
+* Output : None
+* Return : None
+*******************************************************************************/
+void NVIC_ClearSystemHandlerPendingBit(u32 SystemHandler)
+{
+ u32 tmp = 0x00;
+
+ /* Check the parameters */
+ assert(IS_CLEAR_SYSTEM_HANDLER(SystemHandler));
+
+ /* Get the System Handler pending bit position */
+ tmp = SystemHandler & (u32)0x1F;
+ /* Clear the corresponding System Handler pending bit */
+ SCB->IRQControlState |= ((u32)0x01 << (tmp - 0x01));
+}
+
+/*******************************************************************************
+* Function Name : NVIC_GetSystemHandlerActiveBitStatus
+* Description : Checks whether the specified System handlers active bit is
+* set or not.
+* Input : - SystemHandler: specifies the system handler active bit to
+* check.
+* This parameter can be one of the following values:
+* - SystemHandler_MemoryManage
+* - SystemHandler_BusFault
+* - SystemHandler_UsageFault
+* - SystemHandler_SVCall
+* - SystemHandler_DebugMonitor
+* - SystemHandler_PSV
+* - SystemHandler_SysTick
+* Output : None
+* Return : The new state of System Handler active bit(SET or RESET).
+*******************************************************************************/
+ITStatus NVIC_GetSystemHandlerActiveBitStatus(u32 SystemHandler)
+{
+ ITStatus bitstatus = RESET;
+
+ u32 tmp = 0x00, tmppos = 0x00;
+
+ /* Check the parameters */
+ assert(IS_GET_ACTIVE_SYSTEM_HANDLER(SystemHandler));
+
+ tmppos = (SystemHandler >> 0x0E) & (u32)0x0F;
+
+ tmppos = (u32)0x01 << tmppos;
+
+ tmp = SCB->SysHandlerCtrl & tmppos;
+
+ if (tmp == tmppos)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name : NVIC_GetFaultHandlerSources
+* Description : Returns the system fault handlers sources.
+* Input : - SystemHandler: specifies the system handler to get its fault
+* sources.
+* This parameter can be one of the following values:
+* - SystemHandler_HardFault
+* - SystemHandler_MemoryManage
+* - SystemHandler_BusFault
+* - SystemHandler_UsageFault
+* - SystemHandler_DebugMonitor
+* Output : None
+* Return : Source of the fault handler.
+*******************************************************************************/
+u32 NVIC_GetFaultHandlerSources(u32 SystemHandler)
+{
+ u32 faultsources = 0x00;
+ u32 tmpreg = 0x00, tmppos = 0x00;
+
+ /* Check the parameters */
+ assert(IS_FAULT_SOURCE_SYSTEM_HANDLER(SystemHandler));
+
+ tmpreg = (SystemHandler >> 0x12) & (u32)0x03;
+ tmppos = (SystemHandler >> 0x14) & (u32)0x03;
+
+ if (tmpreg == 0x00)
+ {
+ faultsources = SCB->HardFaultStatus;
+ }
+ else if (tmpreg == 0x01)
+ {
+ faultsources = SCB->ConfigFaultStatus >> (tmppos * 0x08);
+ if (tmppos != 0x02)
+ {
+ faultsources &= (u32)0x0F;
+ }
+ else
+ {
+ faultsources &= (u32)0xFF;
+ }
+ }
+ else
+ {
+ faultsources = SCB->DebugFaultStatus;
+ }
+ return faultsources;
+}
+
+/*******************************************************************************
+* Function Name : NVIC_GetFaultAddress
+* Description : Returns the address of the location that generated a fault
+* handler.
+* Input : - SystemHandler: specifies the system handler to get its
+* fault address.
+* This parameter can be one of the following values:
+* - SystemHandler_MemoryManage
+* - SystemHandler_BusFault
+* Output : None
+* Return : Fault address.
+*******************************************************************************/
+u32 NVIC_GetFaultAddress(u32 SystemHandler)
+{
+ u32 faultaddress = 0x00;
+ u32 tmp = 0x00;
+
+ /* Check the parameters */
+ assert(IS_FAULT_ADDRESS_SYSTEM_HANDLER(SystemHandler));
+
+ tmp = (SystemHandler >> 0x16) & (u32)0x01;
+
+ if (tmp == 0x00)
+ {
+ faultaddress = SCB->MemoryManageFaultAddr;
+ }
+ else
+ {
+ faultaddress = SCB->BusFaultAddr;
+ }
+ return faultaddress;
+}
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_pwr.c b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_pwr.c
new file mode 100644
index 0000000..26b6dcc
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_pwr.c
@@ -0,0 +1,283 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_pwr.c
+* Author : MCD Application Team
+* Date First Issued : 09/29/2006
+* Description : This file provides all the PWR firmware functions.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_pwr.h"
+#include "stm32f10x_rcc.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* --------- PWR registers bit address in the alias region ---------- */
+#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
+
+/* --- CR Register ---*/
+/* Alias word address of DBP bit */
+#define CR_OFFSET (PWR_OFFSET + 0x00)
+#define DBP_BitNumber 0x08
+#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
+
+/* Alias word address of PVDE bit */
+#define PVDE_BitNumber 0x04
+#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
+
+/* --- CSR Register ---*/
+/* Alias word address of EWUP bit */
+#define CSR_OFFSET (PWR_OFFSET + 0x04)
+#define EWUP_BitNumber 0x08
+#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
+
+/* ------------------ PWR registers bit mask ------------------------ */
+/* CR register bit mask */
+#define CR_PDDS_Set ((u32)0x00000002)
+#define CR_DS_Mask ((u32)0xFFFFFFFC)
+#define CR_CWUF_Set ((u32)0x00000004)
+#define CR_PLS_Mask ((u32)0xFFFFFF1F)
+
+/* --------- Cortex System Control register bit mask ---------------- */
+/* Cortex System Control register address */
+#define SCB_SysCtrl ((u32)0xE000ED10)
+/* SLEEPDEEP bit mask */
+#define SysCtrl_SLEEPDEEP_Set ((u32)0x00000004)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name : PWR_DeInit
+* Description : Deinitializes the PWR peripheral registers to their default
+* reset values.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void PWR_DeInit(void)
+{
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
+}
+
+/*******************************************************************************
+* Function Name : PWR_BackupAccessCmd
+* Description : Enables or disables access to the RTC and backup registers.
+* Input : - NewState: new state of the access to the RTC and backup
+* registers. This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void PWR_BackupAccessCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ *(vu32 *) CR_DBP_BB = (u32)NewState;
+}
+
+/*******************************************************************************
+* Function Name : PWR_PVDCmd
+* Description : Enables or disables the Power Voltage Detector(PVD).
+* Input : - NewState: new state of the PVD.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void PWR_PVDCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ *(vu32 *) CR_PVDE_BB = (u32)NewState;
+}
+
+/*******************************************************************************
+* Function Name : PWR_PVDLevelConfig
+* Description : Configures the value detected by the Power Voltage Detector(PVD).
+* Input : - PWR_PVDLevel: specifies the PVD detection level
+* This parameter can be one of the following values:
+* - PWR_PVDLevel_2V2: PVD detection level set to 2.2V
+* - PWR_PVDLevel_2V3: PVD detection level set to 2.3V
+* - PWR_PVDLevel_2V4: PVD detection level set to 2.4V
+* - PWR_PVDLevel_2V5: PVD detection level set to 2.5V
+* - PWR_PVDLevel_2V6: PVD detection level set to 2.6V
+* - PWR_PVDLevel_2V7: PVD detection level set to 2.7V
+* - PWR_PVDLevel_2V8: PVD detection level set to 2.8V
+* - PWR_PVDLevel_2V9: PVD detection level set to 2.9V
+* Output : None
+* Return : None
+*******************************************************************************/
+void PWR_PVDLevelConfig(u32 PWR_PVDLevel)
+{
+ u32 tmpreg = 0;
+
+ /* Check the parameters */
+ assert(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
+
+ tmpreg = PWR->CR;
+
+ /* Clear PLS[7:5] bits */
+ tmpreg &= CR_PLS_Mask;
+
+ /* Set PLS[7:5] bits according to PWR_PVDLevel value */
+ tmpreg |= PWR_PVDLevel;
+
+ /* Store the new value */
+ PWR->CR = tmpreg;
+}
+
+/*******************************************************************************
+* Function Name : PWR_WakeUpPinCmd
+* Description : Enables or disables the WakeUp Pin functionality.
+* Input : - NewState: new state of the WakeUp Pin functionality.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void PWR_WakeUpPinCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ *(vu32 *) CSR_EWUP_BB = (u32)NewState;
+}
+
+/*******************************************************************************
+* Function Name : PWR_EnterSTOPMode
+* Description : Enters STOP mode.
+* Input : - PWR_Regulator: specifies the regulator state in STOP mode.
+* This parameter can be one of the following values:
+* - PWR_Regulator_ON: STOP mode with regulator ON
+* - PWR_Regulator_LowPower: STOP mode with
+* regulator in low power mode
+* - PWR_STOPEntry: specifies if STOP mode in entered with WFI or
+* WFE instruction.
+* This parameter can be one of the following values:
+* - PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
+* - PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
+* Output : None
+* Return : None
+*******************************************************************************/
+void PWR_EnterSTOPMode(u32 PWR_Regulator, u8 PWR_STOPEntry)
+{
+ u32 tmpreg = 0;
+
+ /* Check the parameters */
+ assert(IS_PWR_REGULATOR(PWR_Regulator));
+ assert(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
+
+ /* Select the regulator state in STOP mode ---------------------------------*/
+ tmpreg = PWR->CR;
+
+ /* Clear PDDS and LPDS bits */
+ tmpreg &= CR_DS_Mask;
+
+ /* Set LPDS bit according to PWR_Regulator value */
+ tmpreg |= PWR_Regulator;
+
+ /* Store the new value */
+ PWR->CR = tmpreg;
+
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ *(vu32 *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set;
+
+ /* Select STOP mode entry --------------------------------------------------*/
+ if(PWR_STOPEntry == PWR_STOPEntry_WFI)
+ {
+ /* Request Wait For Interrupt */
+ __WFI();
+ }
+ else
+ {
+ /* Request Wait For Event */
+ __WFE();
+ }
+}
+
+/*******************************************************************************
+* Function Name : PWR_EnterSTANDBYMode
+* Description : Enters STANDBY mode.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void PWR_EnterSTANDBYMode(void)
+{
+ /* Clear Wake-up flag */
+ PWR->CR |= CR_CWUF_Set;
+
+ /* Select STANDBY mode */
+ PWR->CR |= CR_PDDS_Set;
+
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ *(vu32 *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set;
+
+ /* Request Wait For Interrupt */
+ __WFI();
+}
+
+/*******************************************************************************
+* Function Name : PWR_GetFlagStatus
+* Description : Checks whether the specified PWR flag is set or not.
+* Input : - PWR_FLAG: specifies the flag to check.
+* This parameter can be one of the following values:
+* - PWR_FLAG_WU: Wake Up flag
+* - PWR_FLAG_SB: StandBy flag
+* - PWR_FLAG_PVDO: PVD Output
+* Output : None
+* Return : The new state of PWR_FLAG (SET or RESET).
+*******************************************************************************/
+FlagStatus PWR_GetFlagStatus(u32 PWR_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert(IS_PWR_GET_FLAG(PWR_FLAG));
+
+ if ((PWR->CSR & PWR_FLAG) != (u32)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+
+ /* Return the flag status */
+ return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name : PWR_ClearFlag
+* Description : Clears the PWR's pending flags.
+* Input : - PWR_FLAG: specifies the flag to clear.
+* This parameter can be one of the following values:
+* - PWR_FLAG_WU: Wake Up flag
+* - PWR_FLAG_SB: StandBy flag
+* Output : None
+* Return : None
+*******************************************************************************/
+void PWR_ClearFlag(u32 PWR_FLAG)
+{
+ /* Check the parameters */
+ assert(IS_PWR_CLEAR_FLAG(PWR_FLAG));
+
+ PWR->CR |= PWR_FLAG << 2;
+}
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_rcc.c b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_rcc.c
new file mode 100644
index 0000000..1cd00bd
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_rcc.c
@@ -0,0 +1,1069 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_rcc.c
+* Author : MCD Application Team
+* Date First Issued : 09/29/2006
+* Description : This file provides all the RCC firmware functions.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_rcc.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* ------------ RCC registers bit address in the alias region ----------- */
+#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
+
+/* --- CR Register ---*/
+/* Alias word address of HSION bit */
+#define CR_OFFSET (RCC_OFFSET + 0x00)
+#define HSION_BitNumber 0x00
+#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
+
+/* Alias word address of PLLON bit */
+#define PLLON_BitNumber 0x18
+#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
+
+/* Alias word address of CSSON bit */
+#define CSSON_BitNumber 0x13
+#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
+
+/* --- CFGR Register ---*/
+/* Alias word address of USBPRE bit */
+#define CFGR_OFFSET (RCC_OFFSET + 0x04)
+#define USBPRE_BitNumber 0x16
+#define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))
+
+/* --- BDCR Register ---*/
+/* Alias word address of RTCEN bit */
+#define BDCR_OFFSET (RCC_OFFSET + 0x20)
+#define RTCEN_BitNumber 0x0F
+#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
+
+/* Alias word address of BDRST bit */
+#define BDRST_BitNumber 0x10
+#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
+
+/* --- CSR Register ---*/
+/* Alias word address of LSION bit */
+#define CSR_OFFSET (RCC_OFFSET + 0x24)
+#define LSION_BitNumber 0x00
+#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
+
+/* ---------------------- RCC registers bit mask ------------------------ */
+/* CR register bit mask */
+#define CR_HSEBYP_Reset ((u32)0xFFFBFFFF)
+#define CR_HSEBYP_Set ((u32)0x00040000)
+#define CR_HSEON_Reset ((u32)0xFFFEFFFF)
+#define CR_HSEON_Set ((u32)0x00010000)
+#define CR_HSITRIM_Mask ((u32)0xFFFFFF07)
+
+/* CFGR register bit mask */
+#define CFGR_PLL_Mask ((u32)0xFFC0FFFF)
+#define CFGR_PLLMull_Mask ((u32)0x003C0000)
+#define CFGR_PLLSRC_Mask ((u32)0x00010000)
+#define CFGR_PLLXTPRE_Mask ((u32)0x00020000)
+#define CFGR_SWS_Mask ((u32)0x0000000C)
+#define CFGR_SW_Mask ((u32)0xFFFFFFFC)
+#define CFGR_HPRE_Reset_Mask ((u32)0xFFFFFF0F)
+#define CFGR_HPRE_Set_Mask ((u32)0x000000F0)
+#define CFGR_PPRE1_Reset_Mask ((u32)0xFFFFF8FF)
+#define CFGR_PPRE1_Set_Mask ((u32)0x00000700)
+#define CFGR_PPRE2_Reset_Mask ((u32)0xFFFFC7FF)
+#define CFGR_PPRE2_Set_Mask ((u32)0x00003800)
+#define CFGR_ADCPRE_Reset_Mask ((u32)0xFFFF3FFF)
+#define CFGR_ADCPRE_Set_Mask ((u32)0x0000C000)
+
+/* CSR register bit mask */
+#define CSR_RVMF_Set ((u32)0x01000000)
+
+/* RCC Flag Mask */
+#define FLAG_Mask ((u8)0x1F)
+
+/* Typical Value of the HSI in Hz */
+#define HSI_Value ((u32)8000000)
+
+/* BDCR register base address */
+#define BDCR_BASE (PERIPH_BASE + BDCR_OFFSET)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+static uc8 APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+static uc8 ADCPrescTable[4] = {2, 4, 6, 8};
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name : RCC_DeInit
+* Description : Deinitializes the RCC peripheral registers to their default
+* reset values.
+* - The HSITRIM[4:0] bits in RCC_CR register are not modified
+* by this function.
+* - The RCC_BDCR and RCC_CSR registers are not reset by this
+* function.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void RCC_DeInit(void)
+{
+ /* Disable APB2 Peripheral Reset */
+ RCC->APB2RSTR = 0x00000000;
+
+ /* Disable APB1 Peripheral Reset */
+ RCC->APB1RSTR = 0x00000000;
+
+ /* FLITF and SRAM Clock ON */
+ RCC->AHBENR = 0x00000014;
+
+ /* Disable APB2 Peripheral Clock */
+ RCC->APB2ENR = 0x00000000;
+
+ /* Disable APB1 Peripheral Clock */
+ RCC->APB1ENR = 0x00000000;
+
+ /* Set HSION bit */
+ RCC->CR |= (u32)0x00000001;
+
+ /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], ADCPRE[1:0] and MCO[2:0] bits*/
+ RCC->CFGR &= 0xF8FF0000;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= 0xFEF6FFFF;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= 0xFFFBFFFF;
+
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL[3:0] and USBPRE bits */
+ RCC->CFGR &= 0xFF80FFFF;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+}
+
+/*******************************************************************************
+* Function Name : RCC_HSEConfig
+* Description : Configures the External High Speed oscillator (HSE).
+* Input : - RCC_HSE: specifies the new state of the HSE.
+* This parameter can be one of the following values:
+* - RCC_HSE_OFF: HSE oscillator OFF
+* - RCC_HSE_ON: HSE oscillator ON
+* - RCC_HSE_Bypass: HSE oscillator bypassed with external
+* clock
+* Output : None
+* Return : None
+*******************************************************************************/
+void RCC_HSEConfig(u32 RCC_HSE)
+{
+ /* Check the parameters */
+ assert(IS_RCC_HSE(RCC_HSE));
+
+ /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
+ /* Reset HSEON bit */
+ RCC->CR &= CR_HSEON_Reset;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= CR_HSEBYP_Reset;
+
+ /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */
+ switch(RCC_HSE)
+ {
+ case RCC_HSE_ON:
+ /* Set HSEON bit */
+ RCC->CR |= CR_HSEON_Set;
+ break;
+
+ case RCC_HSE_Bypass:
+ /* Set HSEBYP and HSEON bits */
+ RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name : RCC_AdjustHSICalibrationValue
+* Description : Adjusts the Internal High Speed oscillator (HSI) calibration
+* value.
+* Input : - HSICalibrationValue: specifies the calibration trimming value.
+* This parameter must be a number between 0 and 0x1F.
+* Output : None
+* Return : None
+*******************************************************************************/
+void RCC_AdjustHSICalibrationValue(u8 HSICalibrationValue)
+{
+ u32 tmpreg = 0;
+
+ /* Check the parameters */
+ assert(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
+
+ tmpreg = RCC->CR;
+
+ /* Clear HSITRIM[7:3] bits */
+ tmpreg &= CR_HSITRIM_Mask;
+
+ /* Set the HSITRIM[7:3] bits according to HSICalibrationValue value */
+ tmpreg |= (u32)HSICalibrationValue << 3;
+
+ /* Store the new value */
+ RCC->CR = tmpreg;
+}
+
+/*******************************************************************************
+* Function Name : RCC_HSICmd
+* Description : Enables or disables the Internal High Speed oscillator (HSI).
+* HSI can not be stopped if it is used directly or through the
+* PLL as system clock, or if a Flash programmation is on going.
+* Input : - NewState: new state of the HSI.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void RCC_HSICmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ *(vu32 *) CR_HSION_BB = (u32)NewState;
+}
+
+/*******************************************************************************
+* Function Name : RCC_PLLConfig
+* Description : Configures the PLL clock source and multiplication factor.
+* This function must be used only when the PLL is disabled.
+* Input : - RCC_PLLSource: specifies the PLL entry clock source.
+* This parameter can be one of the following values:
+* - RCC_PLLSource_HSI_Div2: HSI oscillator clock divided
+* by 2 selected as PLL clock entry
+* - RCC_PLLSource_HSE_Div1: HSE oscillator clock selected
+* as PLL clock entry
+* - RCC_PLLSource_HSE_Div2: HSE oscillator clock divided
+* by 2 selected as PLL clock entry
+* - RCC_PLLMul: specifies the PLL multiplication factor.
+* This parameter can be RCC_PLLMul_x where x:[2,16]
+* Output : None
+* Return : None
+*******************************************************************************/
+void RCC_PLLConfig(u32 RCC_PLLSource, u32 RCC_PLLMul)
+{
+ u32 tmpreg = 0;
+
+ /* Check the parameters */
+ assert(IS_RCC_PLL_SOURCE(RCC_PLLSource));
+ assert(IS_RCC_PLL_MUL(RCC_PLLMul));
+
+ tmpreg = RCC->CFGR;
+
+ /* Clear PLLSRC, PLLXTPRE and PLLMUL[21:18] bits */
+ tmpreg &= CFGR_PLL_Mask;
+
+ /* Set the PLL configuration bits */
+ tmpreg |= RCC_PLLSource | RCC_PLLMul;
+
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+
+/*******************************************************************************
+* Function Name : RCC_PLLCmd
+* Description : Enables or disables the PLL.
+* The PLL can not be disabled if it is used as system clock.
+* Input : - NewState: new state of the PLL.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void RCC_PLLCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ *(vu32 *) CR_PLLON_BB = (u32)NewState;
+}
+
+/*******************************************************************************
+* Function Name : RCC_SYSCLKConfig
+* Description : Configures the system clock (SYSCLK).
+* Input : - RCC_SYSCLKSource: specifies the clock source used as system
+* clock. This parameter can be one of the following values:
+* - RCC_SYSCLKSource_HSI: HSI selected as system clock
+* - RCC_SYSCLKSource_HSE: HSE selected as system clock
+* - RCC_SYSCLKSource_PLLCLK: PLL selected as system clock
+* Output : None
+* Return : None
+*******************************************************************************/
+void RCC_SYSCLKConfig(u32 RCC_SYSCLKSource)
+{
+ u32 tmpreg = 0;
+
+ /* Check the parameters */
+ assert(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
+
+ tmpreg = RCC->CFGR;
+
+ /* Clear SW[1:0] bits */
+ tmpreg &= CFGR_SW_Mask;
+
+ /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
+ tmpreg |= RCC_SYSCLKSource;
+
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+
+/*******************************************************************************
+* Function Name : RCC_GetSYSCLKSource
+* Description : Returns the clock source used as system clock.
+* Input : None
+* Output : None
+* Return : The clock source used as system clock. The returned value can
+* be one of the following:
+* - 0x00: HSI used as system clock
+* - 0x04: HSE used as system clock
+* - 0x08: PLL used as system clock
+*******************************************************************************/
+u8 RCC_GetSYSCLKSource(void)
+{
+ return ((u8)(RCC->CFGR & CFGR_SWS_Mask));
+}
+
+/*******************************************************************************
+* Function Name : RCC_HCLKConfig
+* Description : Configures the AHB clock (HCLK).
+* Input : - RCC_HCLK: defines the AHB clock. This clock is derived
+* from the system clock (SYSCLK).
+* This parameter can be one of the following values:
+* - RCC_SYSCLK_Div1: AHB clock = SYSCLK
+* - RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
+* - RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
+* - RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
+* - RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
+* - RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
+* - RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
+* - RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
+* - RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
+* Output : None
+* Return : None
+*******************************************************************************/
+void RCC_HCLKConfig(u32 RCC_HCLK)
+{
+ u32 tmpreg = 0;
+
+ /* Check the parameters */
+ assert(IS_RCC_HCLK(RCC_HCLK));
+
+ tmpreg = RCC->CFGR;
+
+ /* Clear HPRE[7:4] bits */
+ tmpreg &= CFGR_HPRE_Reset_Mask;
+
+ /* Set HPRE[7:4] bits according to RCC_HCLK value */
+ tmpreg |= RCC_HCLK;
+
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+
+/*******************************************************************************
+* Function Name : RCC_PCLK1Config
+* Description : Configures the Low Speed APB clock (PCLK1).
+* Input : - RCC_PCLK1: defines the APB1 clock. This clock is derived
+* from the AHB clock (HCLK).
+* This parameter can be one of the following values:
+* - RCC_HCLK_Div1: APB1 clock = HCLK
+* - RCC_HCLK_Div2: APB1 clock = HCLK/2
+* - RCC_HCLK_Div4: APB1 clock = HCLK/4
+* - RCC_HCLK_Div8: APB1 clock = HCLK/8
+* - RCC_HCLK_Div16: APB1 clock = HCLK/16
+* Output : None
+* Return : None
+*******************************************************************************/
+void RCC_PCLK1Config(u32 RCC_PCLK1)
+{
+ u32 tmpreg = 0;
+
+ /* Check the parameters */
+ assert(IS_RCC_PCLK(RCC_PCLK1));
+
+ tmpreg = RCC->CFGR;
+
+ /* Clear PPRE1[10:8] bits */
+ tmpreg &= CFGR_PPRE1_Reset_Mask;
+
+ /* Set PPRE1[10:8] bits according to RCC_PCLK1 value */
+ tmpreg |= RCC_PCLK1;
+
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+
+/*******************************************************************************
+* Function Name : RCC_PCLK2Config
+* Description : Configures the High Speed APB clock (PCLK2).
+* Input : - RCC_PCLK2: defines the APB2 clock. This clock is derived
+* from the AHB clock (HCLK).
+* This parameter can be one of the following values:
+* - RCC_HCLK_Div1: APB2 clock = HCLK
+* - RCC_HCLK_Div2: APB2 clock = HCLK/2
+* - RCC_HCLK_Div4: APB2 clock = HCLK/4
+* - RCC_HCLK_Div8: APB2 clock = HCLK/8
+* - RCC_HCLK_Div16: APB2 clock = HCLK/16
+* Output : None
+* Return : None
+*******************************************************************************/
+void RCC_PCLK2Config(u32 RCC_PCLK2)
+{
+ u32 tmpreg = 0;
+
+ /* Check the parameters */
+ assert(IS_RCC_PCLK(RCC_PCLK2));
+
+ tmpreg = RCC->CFGR;
+
+ /* Clear PPRE2[13:11] bits */
+ tmpreg &= CFGR_PPRE2_Reset_Mask;
+
+ /* Set PPRE2[13:11] bits according to RCC_PCLK2 value */
+ tmpreg |= RCC_PCLK2 << 3;
+
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+
+/*******************************************************************************
+* Function Name : RCC_ITConfig
+* Description : Enables or disables the specified RCC interrupts.
+* Input : - RCC_IT: specifies the RCC interrupt sources to be enabled
+* or disabled.
+* This parameter can be any combination of the following values:
+* - RCC_IT_LSIRDY: LSI ready interrupt
+* - RCC_IT_LSERDY: LSE ready interrupt
+* - RCC_IT_HSIRDY: HSI ready interrupt
+* - RCC_IT_HSERDY: HSE ready interrupt
+* - RCC_IT_PLLRDY: PLL ready interrupt
+* - NewState: new state of the specified RCC interrupts.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void RCC_ITConfig(u8 RCC_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_RCC_IT(RCC_IT));
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */
+ *(vu8 *) 0x40021009 |= RCC_IT;
+ }
+ else
+ {
+ /* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */
+ *(vu8 *) 0x40021009 &= ~(u32)RCC_IT;
+ }
+}
+
+/*******************************************************************************
+* Function Name : RCC_USBCLKConfig
+* Description : Configures the USB clock (USBCLK).
+* Input : - RCC_USBCLKSource: specifies the USB clock source. This clock
+* is derived from the PLL output.
+* This parameter can be one of the following values:
+* - RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5
+* selected as USB clock source
+* - RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB
+* clock source
+* Output : None
+* Return : None
+*******************************************************************************/
+void RCC_USBCLKConfig(u32 RCC_USBCLKSource)
+{
+ /* Check the parameters */
+ assert(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
+
+ *(vu32 *) CFGR_USBPRE_BB = RCC_USBCLKSource;
+}
+
+/*******************************************************************************
+* Function Name : RCC_ADCCLKConfig
+* Description : Configures the ADC clock (ADCCLK).
+* Input : - RCC_ADCCLK: defines the ADC clock. This clock is derived
+* from the APB2 clock (PCLK2).
+* This parameter can be one of the following values:
+* - RCC_PCLK2_Div2: ADC clock = PCLK2/2
+* - RCC_PCLK2_Div4: ADC clock = PCLK2/4
+* - RCC_PCLK2_Div6: ADC clock = PCLK2/6
+* - RCC_PCLK2_Div8: ADC clock = PCLK2/8
+* Output : None
+* Return : None
+*******************************************************************************/
+void RCC_ADCCLKConfig(u32 RCC_ADCCLK)
+{
+ u32 tmpreg = 0;
+
+ /* Check the parameters */
+ assert(IS_RCC_ADCCLK(RCC_ADCCLK));
+
+ tmpreg = RCC->CFGR;
+
+ /* Clear ADCPRE[15:14] bits */
+ tmpreg &= CFGR_ADCPRE_Reset_Mask;
+
+ /* Set ADCPRE[15:14] bits according to RCC_ADCCLK value */
+ tmpreg |= RCC_ADCCLK;
+
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+
+/*******************************************************************************
+* Function Name : RCC_LSEConfig
+* Description : Configures the External Low Speed oscillator (LSE).
+* Input : - RCC_LSE: specifies the new state of the LSE.
+* This parameter can be one of the following values:
+* - RCC_LSE_OFF: LSE oscillator OFF
+* - RCC_LSE_ON: LSE oscillator ON
+* - RCC_LSE_Bypass: LSE oscillator bypassed with external
+* clock
+* Output : None
+* Return : None
+*******************************************************************************/
+void RCC_LSEConfig(u32 RCC_LSE)
+{
+ /* Check the parameters */
+ assert(IS_RCC_LSE(RCC_LSE));
+
+ /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
+ /* Reset LSEON bit */
+ *(vu8 *) BDCR_BASE = RCC_LSE_OFF;
+
+ /* Reset LSEBYP bit */
+ *(vu8 *) BDCR_BASE = RCC_LSE_OFF;
+
+ /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
+ switch(RCC_LSE)
+ {
+ case RCC_LSE_ON:
+ /* Set LSEON bit */
+ *(vu8 *) BDCR_BASE = RCC_LSE_ON;
+ break;
+
+ case RCC_LSE_Bypass:
+ /* Set LSEBYP and LSEON bits */
+ *(vu8 *) BDCR_BASE = RCC_LSE_Bypass | RCC_LSE_ON;
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name : RCC_LSICmd
+* Description : Enables or disables the Internal Low Speed oscillator (LSI).
+* LSI can not be disabled if the IWDG is running.
+* Input : - NewState: new state of the LSI.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void RCC_LSICmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ *(vu32 *) CSR_LSION_BB = (u32)NewState;
+}
+
+/*******************************************************************************
+* Function Name : RCC_RTCCLKConfig
+* Description : Configures the RTC clock (RTCCLK).
+* Once the RTC clock is selected it cant be changed unless the
+* Backup domain is reset.
+* Input : - RCC_RTCCLKSource: specifies the RTC clock source.
+* This parameter can be one of the following values:
+* - RCC_RTCCLKSource_LSE: LSE oscillator clock used as RTC
+* clock
+* - RCC_RTCCLKSource_LSI: LSI oscillator clock used as RTC
+* clock
+* - RCC_RTCCLKSource_HSE_Div128: HSE oscillator clock divided
+* by 128 used as RTC clock
+* Output : None
+* Return : None
+*******************************************************************************/
+void RCC_RTCCLKConfig(u32 RCC_RTCCLKSource)
+{
+ /* Check the parameters */
+ assert(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
+
+ /* Select the RTC clock source */
+ RCC->BDCR |= RCC_RTCCLKSource;
+}
+
+/*******************************************************************************
+* Function Name : RCC_RTCCLKCmd
+* Description : Enables or disables the RTC clock.
+* This function must be used only after the RTC clock was
+* selected using the RCC_RTCCLKConfig function.
+* Input : - NewState: new state of the RTC clock.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void RCC_RTCCLKCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ *(vu32 *) BDCR_RTCEN_BB = (u32)NewState;
+}
+
+/*******************************************************************************
+* Function Name : RCC_GetClocksFreq
+* Description : Returns the frequencies of different on chip clocks.
+* Input : - RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which
+* will hold the clocks frequencies.
+* Output : None
+* Return : None
+*******************************************************************************/
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
+{
+ u32 tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFGR & CFGR_SWS_Mask;
+
+ switch (tmp)
+ {
+ case 0x00: /* HSI used as system clock */
+ RCC_Clocks->SYSCLK_Frequency = HSI_Value;
+ break;
+
+ case 0x04: /* HSE used as system clock */
+ RCC_Clocks->SYSCLK_Frequency = HSE_Value;
+ break;
+
+ case 0x08: /* PLL used as system clock */
+ /* Get PLL clock source and multiplication factor ----------------------*/
+ pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
+ pllmull = ( pllmull >> 18) + 2;
+
+ pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
+
+ if (pllsource == 0x00)
+ {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
+ RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull;
+ }
+ else
+ {/* HSE selected as PLL clock entry */
+
+ if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (u32)RESET)
+ {/* HSE oscillator clock divided by 2 */
+
+ RCC_Clocks->SYSCLK_Frequency = (HSE_Value >> 1) * pllmull;
+ }
+ else
+ {
+ RCC_Clocks->SYSCLK_Frequency = HSE_Value * pllmull;
+ }
+ }
+ break;
+
+ default:
+ RCC_Clocks->SYSCLK_Frequency = HSI_Value;
+ break;
+ }
+
+ /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
+ /* Get HCLK prescaler */
+ tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
+ tmp = tmp >> 4;
+ presc = APBAHBPrescTable[tmp];
+
+ /* HCLK clock frequency */
+ RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
+
+ /* Get PCLK1 prescaler */
+ tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
+ tmp = tmp >> 8;
+ presc = APBAHBPrescTable[tmp];
+
+ /* PCLK1 clock frequency */
+ RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
+
+ /* Get PCLK2 prescaler */
+ tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
+ tmp = tmp >> 11;
+ presc = APBAHBPrescTable[tmp];
+
+ /* PCLK2 clock frequency */
+ RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
+
+ /* Get ADCCLK prescaler */
+ tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
+ tmp = tmp >> 14;
+ presc = ADCPrescTable[tmp];
+
+ /* ADCCLK clock frequency */
+ RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
+}
+
+/*******************************************************************************
+* Function Name : RCC_AHBPeriphClockCmd
+* Description : Enables or disables the AHB peripheral clock.
+* Input : - RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
+* This parameter can be any combination of the following values:
+* - RCC_AHBPeriph_DMA
+* - RCC_AHBPeriph_SRAM
+* - RCC_AHBPeriph_FLITF
+* SRAM and FLITF clock can be disabled only during sleep mode.
+* - NewState: new state of the specified peripheral clock.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void RCC_AHBPeriphClockCmd(u32 RCC_AHBPeriph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ RCC->AHBENR |= RCC_AHBPeriph;
+ }
+ else
+ {
+ RCC->AHBENR &= ~RCC_AHBPeriph;
+ }
+}
+
+/*******************************************************************************
+* Function Name : RCC_APB2PeriphClockCmd
+* Description : Enables or disables the High Speed APB (APB2) peripheral clock.
+* Input : - RCC_APB2Periph: specifies the APB2 peripheral to gates its
+* clock.
+* This parameter can be any combination of the following values:
+* - RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB
+* RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE
+* RCC_APB2Periph_ADC1, RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1
+* RCC_APB2Periph_SPI1, RCC_APB2Periph_USART1, RCC_APB2Periph_ALL
+* - NewState: new state of the specified peripheral clock.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void RCC_APB2PeriphClockCmd(u32 RCC_APB2Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ RCC->APB2ENR |= RCC_APB2Periph;
+ }
+ else
+ {
+ RCC->APB2ENR &= ~RCC_APB2Periph;
+ }
+}
+
+/*******************************************************************************
+* Function Name : RCC_APB1PeriphClockCmd
+* Description : Enables or disables the Low Speed APB (APB1) peripheral clock.
+* Input : - RCC_APB1Periph: specifies the APB1 peripheral to gates its
+* clock.
+* This parameter can be any combination of the following values:
+* - RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4
+* RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_USART2
+* RCC_APB1Periph_USART3, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2
+* RCC_APB1Periph_USB, RCC_APB1Periph_CAN, RCC_APB1Periph_BKP
+* RCC_APB1Periph_PWR, RCC_APB1Periph_ALL
+* - NewState: new state of the specified peripheral clock.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void RCC_APB1PeriphClockCmd(u32 RCC_APB1Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ RCC->APB1ENR |= RCC_APB1Periph;
+ }
+ else
+ {
+ RCC->APB1ENR &= ~RCC_APB1Periph;
+ }
+}
+
+/*******************************************************************************
+* Function Name : RCC_APB2PeriphResetCmd
+* Description : Forces or releases High Speed APB (APB2) peripheral reset.
+* Input : - RCC_APB2Periph: specifies the APB2 peripheral to reset.
+* This parameter can be any combination of the following values:
+* - RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB
+* RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE
+* RCC_APB2Periph_ADC1, RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1
+* RCC_APB2Periph_SPI1, RCC_APB2Periph_USART1, RCC_APB2Periph_ALL
+* - NewState: new state of the specified peripheral reset.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void RCC_APB2PeriphResetCmd(u32 RCC_APB2Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ RCC->APB2RSTR |= RCC_APB2Periph;
+ }
+ else
+ {
+ RCC->APB2RSTR &= ~RCC_APB2Periph;
+ }
+}
+
+/*******************************************************************************
+* Function Name : RCC_APB1PeriphResetCmd
+* Description : Forces or releases Low Speed APB (APB1) peripheral reset.
+* Input : - RCC_APB1Periph: specifies the APB1 peripheral to reset.
+* This parameter can be any combination of the following values:
+* - RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4
+* RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_USART2
+* RCC_APB1Periph_USART3, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2
+* RCC_APB1Periph_USB, RCC_APB1Periph_CAN, RCC_APB1Periph_BKP
+* RCC_APB1Periph_PWR, RCC_APB1Periph_ALL
+* - NewState: new state of the specified peripheral clock.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void RCC_APB1PeriphResetCmd(u32 RCC_APB1Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ RCC->APB1RSTR |= RCC_APB1Periph;
+ }
+ else
+ {
+ RCC->APB1RSTR &= ~RCC_APB1Periph;
+ }
+}
+
+/*******************************************************************************
+* Function Name : RCC_BackupResetCmd
+* Description : Forces or releases the Backup domain reset.
+* Input : - NewState: new state of the Backup domain reset.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void RCC_BackupResetCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ *(vu32 *) BDCR_BDRST_BB = (u32)NewState;
+}
+
+/*******************************************************************************
+* Function Name : RCC_ClockSecuritySystemCmd
+* Description : Enables or disables the Clock Security System.
+* Input : - NewState: new state of the Clock Security System..
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ *(vu32 *) CR_CSSON_BB = (u32)NewState;
+}
+
+/*******************************************************************************
+* Function Name : RCC_MCOConfig
+* Description : Selects the clock source to output on MCO pin.
+* Input : - RCC_MCO: specifies the clock source to output.
+* This parameter can be one of the following values:
+* - RCC_MCO_NoClock: No clock selected
+* - RCC_MCO_SYSCLK: System clock selected
+* - RCC_MCO_HSI: HSI oscillator clock selected
+* - RCC_MCO_HSE: HSE oscillator clock selected
+* - RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
+* Output : None
+* Return : None
+*******************************************************************************/
+void RCC_MCOConfig(u8 RCC_MCO)
+{
+ /* Check the parameters */
+ assert(IS_RCC_MCO(RCC_MCO));
+
+ /* Perform Byte access to MCO[26:24] bits to select the MCO source */
+ *(vu8 *) 0x40021007 = RCC_MCO;
+}
+
+/*******************************************************************************
+* Function Name : RCC_GetFlagStatus
+* Description : Checks whether the specified RCC flag is set or not.
+* Input : - RCC_FLAG: specifies the flag to check.
+* This parameter can be one of the following values:
+* - RCC_FLAG_HSIRDY: HSI oscillator clock ready
+* - RCC_FLAG_HSERDY: HSE oscillator clock ready
+* - RCC_FLAG_PLLRDY: PLL clock ready
+* - RCC_FLAG_LSERDY: LSE oscillator clock ready
+* - RCC_FLAG_LSIRDY: LSI oscillator clock ready
+* - RCC_FLAG_PINRST: Pin reset
+* - RCC_FLAG_PORRST: POR/PDR reset
+* - RCC_FLAG_SFTRST: Software reset
+* - RCC_FLAG_IWDGRST: Independent Watchdog reset
+* - RCC_FLAG_WWDGRST: Window Watchdog reset
+* - RCC_FLAG_LPWRRST: Low Power reset
+* Output : None
+* Return : The new state of RCC_FLAG (SET or RESET).
+*******************************************************************************/
+FlagStatus RCC_GetFlagStatus(u8 RCC_FLAG)
+{
+ u32 tmp = 0;
+ u32 statusreg = 0;
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert(IS_RCC_FLAG(RCC_FLAG));
+
+ /* Get the RCC register index */
+ tmp = RCC_FLAG >> 5;
+
+ if (tmp == 1) /* The flag to check is in CR register */
+ {
+ statusreg = RCC->CR;
+ }
+ else if (tmp == 2) /* The flag to check is in BDCR register */
+ {
+ statusreg = RCC->BDCR;
+ }
+ else /* The flag to check is in CSR register */
+ {
+ statusreg = RCC->CSR;
+ }
+
+ /* Get the flag position */
+ tmp = RCC_FLAG & FLAG_Mask;
+
+ if ((statusreg & ((u32)1 << tmp)) != (u32)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+
+ /* Return the flag status */
+ return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name : RCC_ClearFlag
+* Description : Clears the RCC reset flags.
+* The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
+* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST,
+* RCC_FLAG_LPWRRST
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void RCC_ClearFlag(void)
+{
+ /* Set RVMF bit to clear the reset flags */
+ RCC->CSR |= CSR_RVMF_Set;
+}
+
+/*******************************************************************************
+* Function Name : RCC_GetITStatus
+* Description : Checks whether the specified RCC interrupt has occurred or not.
+* Input : - RCC_IT: specifies the RCC interrupt source to check.
+* This parameter can be one of the following values:
+* - RCC_IT_LSIRDY: LSI ready interrupt
+* - RCC_IT_LSERDY: LSE ready interrupt
+* - RCC_IT_HSIRDY: HSI ready interrupt
+* - RCC_IT_HSERDY: HSE ready interrupt
+* - RCC_IT_PLLRDY: PLL ready interrupt
+* - RCC_IT_CSS: Clock Security System interrupt
+* Output : None
+* Return : The new state of RCC_IT (SET or RESET).
+*******************************************************************************/
+ITStatus RCC_GetITStatus(u8 RCC_IT)
+{
+ ITStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert(IS_RCC_GET_IT(RCC_IT));
+
+ /* Check the status of the specified RCC interrupt */
+ if ((RCC->CIR & RCC_IT) != (u32)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+
+ /* Return the RCC_IT status */
+ return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name : RCC_ClearITPendingBit
+* Description : Clears the RCCs interrupt pending bits.
+* Input : - RCC_IT: specifies the interrupt pending bit to clear.
+* This parameter can be any combination of the following values:
+* - RCC_IT_LSIRDY: LSI ready interrupt
+* - RCC_IT_LSERDY: LSE ready interrupt
+* - RCC_IT_HSIRDY: HSI ready interrupt
+* - RCC_IT_HSERDY: HSE ready interrupt
+* - RCC_IT_PLLRDY: PLL ready interrupt
+* - RCC_IT_CSS: Clock Security System interrupt
+* Output : None
+* Return : None
+*******************************************************************************/
+void RCC_ClearITPendingBit(u8 RCC_IT)
+{
+ /* Check the parameters */
+ assert(IS_RCC_CLEAR_IT(RCC_IT));
+
+ /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
+ pending bits */
+ *(vu8 *) 0x4002100A = RCC_IT;
+}
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_rtc.c b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_rtc.c
new file mode 100644
index 0000000..2163791
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_rtc.c
@@ -0,0 +1,342 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_rtc.c
+* Author : MCD Application Team
+* Date First Issued : 09/29/2006
+* Description : This file provides all the RTC firmware functions.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_rtc.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define CRL_CNF_Set ((u16)0x0010) /* Configuration Flag Enable Mask */
+#define CRL_CNF_Reset ((u16)0xFFEF) /* Configuration Flag Disable Mask */
+#define RTC_LSB_Mask ((u32)0x0000FFFF) /* RTC LSB Mask */
+#define RTC_MSB_Mask ((u32)0xFFFF0000) /* RTC MSB Mask */
+#define PRLH_MSB_Mask ((u32)0x000F0000) /* RTC Prescaler MSB Mask */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name : RTC_ITConfig
+* Description : Enables or disables the specified RTC interrupts.
+* Input : - RTC_IT: specifies the RTC interrupts sources to be enabled
+* or disabled.
+* This parameter can be any combination of the following values:
+* - RTC_IT_OW: Overflow interrupt
+* - RTC_IT_ALR: Alarm interrupt
+* - RTC_IT_SEC: Second interrupt
+* - NewState: new state of the specified RTC interrupts.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void RTC_ITConfig(u16 RTC_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_RTC_IT(RTC_IT));
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ RTC->CRH |= RTC_IT;
+ }
+ else
+ {
+ RTC->CRH &= (u16)~RTC_IT;
+ }
+}
+
+/*******************************************************************************
+* Function Name : RTC_EnterConfigMode
+* Description : Enters the RTC configuration mode.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void RTC_EnterConfigMode(void)
+{
+ /* Set the CNF flag to enter in the Configuration Mode */
+ RTC->CRL |= CRL_CNF_Set;
+}
+
+/*******************************************************************************
+* Function Name : RTC_ExitConfigMode
+* Description : Exits from the RTC configuration mode.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void RTC_ExitConfigMode(void)
+{
+ /* Reset the CNF flag to exit from the Configuration Mode */
+ RTC->CRL &= CRL_CNF_Reset;
+}
+
+/*******************************************************************************
+* Function Name : RTC_GetCounter
+* Description : Gets the RTC counter value.
+* Input : None
+* Output : None
+* Return : RTC counter value.
+*******************************************************************************/
+u32 RTC_GetCounter(void)
+{
+ u16 tmp = 0;
+ tmp = RTC->CNTL;
+
+ return (((u32)RTC->CNTH << 16 ) | tmp) ;
+}
+
+/*******************************************************************************
+* Function Name : RTC_SetCounter
+* Description : Sets the RTC counter value.
+* Input : - CounterValue: RTC counter new value.
+* Output : None
+* Return : None
+*******************************************************************************/
+void RTC_SetCounter(u32 CounterValue)
+{
+ RTC_EnterConfigMode();
+
+ /* Set RTC COUNTER MSB word */
+ RTC->CNTH = (CounterValue & RTC_MSB_Mask) >> 16;
+ /* Set RTC COUNTER LSB word */
+ RTC->CNTL = (CounterValue & RTC_LSB_Mask);
+
+ RTC_ExitConfigMode();
+}
+
+/*******************************************************************************
+* Function Name : RTC_GetPrescaler
+* Description : Gets the RTC prescaler value.
+* Input : None
+* Output : None
+* Return : RTC prescaler value.
+*******************************************************************************/
+u32 RTC_GetPrescaler(void)
+{
+ u32 tmp = 0x00;
+
+ tmp = ((u32)RTC->PRLH & (u32)0x000F) << 0x10;
+ tmp |= RTC->PRLL;
+
+ return tmp;
+}
+
+/*******************************************************************************
+* Function Name : RTC_SetPrescaler
+* Description : Sets the RTC prescaler value.
+* Input : - PrescalerValue: RTC prescaler new value.
+* Output : None
+* Return : None
+*******************************************************************************/
+void RTC_SetPrescaler(u32 PrescalerValue)
+{
+ /* Check the parameters */
+ assert(IS_RTC_PRESCALER(PrescalerValue));
+
+ RTC_EnterConfigMode();
+
+ /* Set RTC PRESCALER MSB word */
+ RTC->PRLH = (PrescalerValue & PRLH_MSB_Mask) >> 0x10;
+ /* Set RTC PRESCALER LSB word */
+ RTC->PRLL = (PrescalerValue & RTC_LSB_Mask);
+
+ RTC_ExitConfigMode();
+}
+
+/*******************************************************************************
+* Function Name : RTC_SetAlarm
+* Description : Sets the RTC alarm value.
+* Input : - AlarmValue: RTC alarm new value.
+* Output : None
+* Return : None
+*******************************************************************************/
+void RTC_SetAlarm(u32 AlarmValue)
+{
+ RTC_EnterConfigMode();
+
+ /* Set the ALARM MSB word */
+ RTC->ALRH = (AlarmValue & RTC_MSB_Mask) >> 16;
+ /* Set the ALARM LSB word */
+ RTC->ALRL = (AlarmValue & RTC_LSB_Mask);
+
+ RTC_ExitConfigMode();
+}
+
+/*******************************************************************************
+* Function Name : RTC_GetDivider
+* Description : Gets the RTC divider value.
+* Input : None
+* Output : None
+* Return : RTC Divider value.
+*******************************************************************************/
+u32 RTC_GetDivider(void)
+{
+ u32 tmp = 0x00;
+
+ tmp = ((u32)RTC->DIVH & (u32)0x000F) << 0x10;
+ tmp |= RTC->DIVL;
+
+ return tmp;
+}
+
+/*******************************************************************************
+* Function Name : RTC_WaitForLastTask
+* Description : Waits until last write operation on RTC registers has finished.
+* This function must be called before any write to RTC registers.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void RTC_WaitForLastTask(void)
+{
+ /* Loop until RTOFF flag is set */
+ while ((RTC->CRL & RTC_FLAG_RTOFF) == (u16)RESET)
+ {
+ }
+}
+
+/*******************************************************************************
+* Function Name : RTC_WaitForSynchro
+* Description : Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL)
+* are synchronized with RTC APB clock.
+* This function must be called before any read operation after
+* an APB reset or an APB clock stop.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void RTC_WaitForSynchro(void)
+{
+ /* Clear RSF flag */
+ RTC->CRL &= (u16)~RTC_FLAG_RSF;
+
+ /* Loop until RSF flag is set */
+ while ((RTC->CRL & RTC_FLAG_RSF) == (u16)RESET)
+ {
+ }
+}
+
+/*******************************************************************************
+* Function Name : RTC_GetFlagStatus
+* Description : Checks whether the specified RTC flag is set or not.
+* Input : - RTC_FLAG: specifies the flag to check.
+* This parameter can be one the following values:
+* - RTC_FLAG_RTOFF: RTC Operation OFF flag
+* - RTC_FLAG_RSF: Registers Synchronized flag
+* - RTC_FLAG_OW: Overflow flag
+* - RTC_FLAG_ALR: Alarm flag
+* - RTC_FLAG_SEC: Second flag
+* Output : None
+* Return : The new state of RTC_FLAG (SET or RESET).
+*******************************************************************************/
+FlagStatus RTC_GetFlagStatus(u16 RTC_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert(IS_RTC_GET_FLAG(RTC_FLAG));
+
+ if ((RTC->CRL & RTC_FLAG) != (u16)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name : RTC_ClearFlag
+* Description : Clears the RTCs pending flags.
+* Input : - RTC_FLAG: specifies the flag to clear.
+* This parameter can be any combination of the following values:
+* - RTC_FLAG_RSF: Registers Synchronized flag. This flag
+* is cleared only after an APB reset or an APB Clock stop.
+* - RTC_FLAG_OW: Overflow flag
+* - RTC_FLAG_ALR: Alarm flag
+* - RTC_FLAG_SEC: Second flag
+* Output : None
+* Return : None
+*******************************************************************************/
+void RTC_ClearFlag(u16 RTC_FLAG)
+{
+ /* Check the parameters */
+ assert(IS_RTC_CLEAR_FLAG(RTC_FLAG));
+
+ /* Clear the coressponding RTC flag */
+ RTC->CRL &= (u16)~RTC_FLAG;
+}
+
+/*******************************************************************************
+* Function Name : RTC_GetITStatus
+* Description : Checks whether the specified RTC interrupt has occured or not.
+* Input : - RTC_IT: specifies the RTC interrupts sources to check.
+* This parameter can be one of the following values:
+* - RTC_IT_OW: Overflow interrupt
+* - RTC_IT_ALR: Alarm interrupt
+* - RTC_IT_SEC: Second interrupt
+* Output : None
+* Return : The new state of the RTC_IT (SET or RESET).
+*******************************************************************************/
+ITStatus RTC_GetITStatus(u16 RTC_IT)
+{
+ ITStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert(IS_RTC_GET_IT(RTC_IT));
+
+ bitstatus = (ITStatus)((RTC->CRL & RTC_IT) != (u16)RESET);
+
+ if (((RTC->CRH & RTC_IT) != (u16)RESET) && bitstatus)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name : RTC_ClearITPendingBit
+* Description : Clears the RTCs interrupt pending bits.
+* Input : - RTC_IT: specifies the interrupt pending bit to clear.
+* This parameter can be any combination of the following values:
+* - RTC_IT_OW: Overflow interrupt
+* - RTC_IT_ALR: Alarm interrupt
+* - RTC_IT_SEC: Second interrupt
+* Output : None
+* Return : None
+*******************************************************************************/
+void RTC_ClearITPendingBit(u16 RTC_IT)
+{
+ /* Check the parameters */
+ assert(IS_RTC_IT(RTC_IT));
+
+ /* Clear the coressponding RTC pending bit */
+ RTC->CRL &= (u16)~RTC_IT;
+}
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_spi.c b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_spi.c
new file mode 100644
index 0000000..ae507dc
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_spi.c
@@ -0,0 +1,658 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_spi.c
+* Author : MCD Application Team
+* Date First Issued : 09/29/2006
+* Description : This file provides all the SPI firmware functions.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_spi.h"
+#include "stm32f10x_rcc.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* SPI SPE mask */
+#define CR1_SPE_Set ((u16)0x0040)
+#define CR1_SPE_Reset ((u16)0xFFBF)
+
+/* SPI CRCNext mask */
+#define CR1_CRCNext_Set ((u16)0x1000)
+
+/* SPI CRCEN mask */
+#define CR1_CRCEN_Set ((u16)0x2000)
+#define CR1_CRCEN_Reset ((u16)0xDFFF)
+
+/* SPI SSOE mask */
+#define CR2_SSOE_Set ((u16)0x0004)
+#define CR2_SSOE_Reset ((u16)0xFFFB)
+
+/* SPI registers Masks */
+#define CR1_CLEAR_Mask ((u16)0x3040)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name : SPI_DeInit
+* Description : Deinitializes the SPIx peripheral registers to their default
+* reset values.
+* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral.
+* Output : None
+* Return : None
+*******************************************************************************/
+void SPI_DeInit(SPI_TypeDef* SPIx)
+{
+ switch (*(u32*)&SPIx)
+ {
+ case SPI1_BASE:
+ /* Enable SPI1 reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
+ /* Release SPI1 from reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
+ break;
+
+ case SPI2_BASE:
+ /* Enable SPI2 reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
+ /* Release SPI2 from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name : SPI_Init
+* Description : Initializes the SPIx according to the specified parameters
+* in the SPI_InitStruct.
+* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral.
+* - SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
+* contains the configuration information for the specified
+* SPI peripheral.
+* Output : None
+* Return : None
+******************************************************************************/
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
+{
+ u16 tmpreg = 0;
+
+ /* Check the parameters */
+ assert(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
+ assert(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
+ assert(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));
+ assert(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
+ assert(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
+ assert(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
+ assert(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
+ assert(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
+ assert(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
+
+/*---------------------------- SPIx CR1 Configuration ------------------------*/
+ /* Get the SPIx CR1 value */
+ tmpreg = SPIx->CR1;
+ /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
+ tmpreg &= CR1_CLEAR_Mask;
+ /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
+ master/salve mode, CPOL and CPHA */
+ /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
+ /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
+ /* Set LSBFirst bit according to SPI_FirstBit value */
+ /* Set BR bits according to SPI_BaudRatePrescaler value */
+ /* Set CPOL bit according to SPI_CPOL value */
+ /* Set CPHA bit according to SPI_CPHA value */
+ tmpreg |= (u16)((u32)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
+ SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |
+ SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |
+ SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
+ /* Write to SPIx CR1 */
+ SPIx->CR1 = tmpreg;
+
+/*---------------------------- SPIx CRCPOLY Configuration --------------------*/
+ /* Write to SPIx CRCPOLY */
+ SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
+}
+
+/*******************************************************************************
+* Function Name : SPI_StructInit
+* Description : Fills each SPI_InitStruct member with its default value.
+* Input : - SPI_InitStruct : pointer to a SPI_InitTypeDef structure
+* which will be initialized.
+* Output : None
+* Return : None
+*******************************************************************************/
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
+{
+/*--------------- Reset SPI init structure parameters values -----------------*/
+ /* Initialize the SPI_Direction member */
+ SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
+
+ /* initialize the SPI_Mode member */
+ SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
+
+ /* initialize the SPI_DataSize member */
+ SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
+
+ /* Initialize the SPI_CPOL member */
+ SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
+
+ /* Initialize the SPI_CPHA member */
+ SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
+
+ /* Initialize the SPI_NSS member */
+ SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
+
+ /* Initialize the SPI_BaudRatePrescaler member */
+ SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
+
+ /* Initialize the SPI_FirstBit member */
+ SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
+
+ /* Initialize the SPI_CRCPolynomial member */
+ SPI_InitStruct->SPI_CRCPolynomial = 7;
+}
+
+/*******************************************************************************
+* Function Name : SPI_Cmd
+* Description : Enables or disables the specified SPI peripheral.
+* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral.
+* - NewState: new state of the SPIx peripheral.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected SPI peripheral */
+ SPIx->CR1 |= CR1_SPE_Set;
+ }
+ else
+ {
+ /* Disable the selected SPI peripheral */
+ SPIx->CR1 &= CR1_SPE_Reset;
+ }
+}
+
+/*******************************************************************************
+* Function Name : SPI_ITConfig
+* Description : Enables or disables the specified SPI interrupts.
+* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral.
+* - SPI_IT: specifies the SPI interrupts sources to be enabled
+* or disabled.
+* This parameter can be one of the following values:
+* - SPI_IT_TXE: Tx buffer empty interrupt mask
+* - SPI_IT_RXNE: Rx buffer not empty interrupt mask
+* - SPI_IT_ERR: Error interrupt mask
+* - NewState: new state of the specified SPI interrupts.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void SPI_ITConfig(SPI_TypeDef* SPIx, u8 SPI_IT, FunctionalState NewState)
+{
+ u16 itpos = 0, itmask = 0 ;
+
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+ assert(IS_SPI_CONFIG_IT(SPI_IT));
+
+ /* Get the SPI IT index */
+ itpos = SPI_IT >> 4;
+ /* Set the IT mask */
+ itmask = (u16)((u16)1 << itpos);
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected SPI interrupt */
+ SPIx->CR2 |= itmask;
+ }
+ else
+ {
+ /* Disable the selected SPI interrupt */
+ SPIx->CR2 &= (u16)~itmask;
+ }
+}
+
+/*******************************************************************************
+* Function Name : SPI_DMACmd
+* Description : Enables or disables the SPIxs DMA interface.
+* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral.
+* - SPI_DMAReq: specifies the SPI DMA transfer request to be
+* enabled or disabled.
+* This parameter can be any combination of the following values:
+* - SPI_DMAReq_Tx: Tx buffer DMA transfer request
+* - SPI_DMAReq_Rx: Rx buffer DMA transfer request
+* - NewState: new state of the selected SPI DMA transfer request.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void SPI_DMACmd(SPI_TypeDef* SPIx, u16 SPI_DMAReq, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+ assert(IS_SPI_DMA_REQ(SPI_DMAReq));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected SPI DMA requests */
+ SPIx->CR2 |= SPI_DMAReq;
+ }
+ else
+ {
+ /* Disable the selected SPI DMA requests */
+ SPIx->CR2 &= (u16)~SPI_DMAReq;
+ }
+}
+
+/*******************************************************************************
+* Function Name : SPI_SendData
+* Description : Transmits a Data through the SPIx peripheral.
+* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral.
+* - Data : Data to be transmitted..
+* Output : None
+* Return : None
+*******************************************************************************/
+void SPI_SendData(SPI_TypeDef* SPIx, u16 Data)
+{
+ /* Write in the DR register the data to be sent */
+ SPIx->DR = Data;
+}
+
+/*******************************************************************************
+* Function Name : SPI_ReceiveData
+* Description : Returns the most recent received data by the SPIx peripheral.
+* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral.
+* Output : None
+* Return : The value of the received data.
+*******************************************************************************/
+u16 SPI_ReceiveData(SPI_TypeDef* SPIx)
+{
+ /* Return the data in the DR register */
+ return SPIx->DR;
+}
+
+/*******************************************************************************
+* Function Name : SPI_NSSInternalSoftwareConfig
+* Description : Configures internally by software the NSS pin for the selected
+* SPI.
+* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral.
+* - SPI_NSSInternalSoft: specifies the SPI NSS internal state.
+* This parameter can be one of the following values:
+* - SPI_NSSInternalSoft_Set: Set NSS pin internally
+* - SPI_NSSInternalSoft_Reset: Reset NSS pin internally
+* Output : None
+* Return : None
+*******************************************************************************/
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, u16 SPI_NSSInternalSoft)
+{
+ /* Check the parameters */
+ assert(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
+
+ if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
+ {
+ /* Set NSS pin internally by software */
+ SPIx->CR1 |= SPI_NSSInternalSoft_Set;
+ }
+ else
+ {
+ /* Reset NSS pin internally by software */
+ SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
+ }
+}
+
+/*******************************************************************************
+* Function Name : SPI_SSOutputCmd
+* Description : Enables or disables the SS output for the selected SPI.
+* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral.
+* - NewState: new state of the SPIx SS output.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected SPI SS output */
+ SPIx->CR2 |= CR2_SSOE_Set;
+ }
+ else
+ {
+ /* Disable the selected SPI SS output */
+ SPIx->CR2 &= CR2_SSOE_Reset;
+ }
+}
+
+/*******************************************************************************
+* Function Name : SPI_DataSizeConfig
+* Description : Configures the data size for the selected SPI.
+* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral.
+* - SPI_DataSize: specifies the SPI data size.
+* This parameter can be one of the following values:
+* - SPI_DataSize_16b: Set data frame format to 16bit
+* - SPI_DataSize_8b: Set data frame format to 8bit
+* Output : None
+* Return : None
+*******************************************************************************/
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, u16 SPI_DataSize)
+{
+ /* Check the parameters */
+ assert(IS_SPI_DATASIZE(SPI_DataSize));
+
+ if (SPI_DataSize != SPI_DataSize_8b)
+ {
+ /* Set data frame format to 16bit */
+ SPIx->CR1 |= SPI_DataSize_16b;
+ }
+ else
+ {
+ /* Set data frame format to 8bit */
+ SPIx->CR1 &= SPI_DataSize_8b;
+ }
+}
+
+/*******************************************************************************
+* Function Name : SPI_TransmitCRC
+* Description : Transmit the SPIx CRC value.
+* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral.
+* Output : None
+* Return : None
+*******************************************************************************/
+void SPI_TransmitCRC(SPI_TypeDef* SPIx)
+{
+ /* Enable the selected SPI CRC transmission */
+ SPIx->CR1 |= CR1_CRCNext_Set;
+}
+
+/*******************************************************************************
+* Function Name : SPI_CalculateCRC
+* Description : Enables or disables the CRC value calculation of the
+* transfered bytes.
+* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral.
+* - NewState: new state of the SPIx CRC value calculation.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected SPI CRC calculation */
+ SPIx->CR1 |= CR1_CRCEN_Set;
+ }
+ else
+ {
+ /* Disable the selected SPI CRC calculation */
+ SPIx->CR1 &= CR1_CRCEN_Reset;
+ }
+}
+
+/*******************************************************************************
+* Function Name : SPI_GetCRC
+* Description : Returns the transmit or the receive CRC register value for
+* the specified SPI.
+* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral.
+* - SPI_CRC: specifies the CRC register to be read.
+* This parameter can be one of the following values:
+* - SPI_CRC_Tx: Selects Tx CRC register
+* - SPI_CRC_Rx: Selects Rx CRC register
+* Output : None
+* Return : The selected CRC register value..
+*******************************************************************************/
+u16 SPI_GetCRC(SPI_TypeDef* SPIx, u8 SPI_CRC)
+{
+ u16 crcreg = 0;
+
+ /* Check the parameters */
+ assert(IS_SPI_CRC(SPI_CRC));
+
+ if (SPI_CRC != SPI_CRC_Rx)
+ {
+ /* Get the Tx CRC register */
+ crcreg = SPIx->TXCRCR;
+ }
+ else
+ {
+ /* Get the Rx CRC register */
+ crcreg = SPIx->RXCRCR;
+ }
+
+ /* Return the selected CRC register */
+ return crcreg;
+}
+
+/*******************************************************************************
+* Function Name : SPI_GetCRCPolynomial
+* Description : Returns the CRC Polynomial register value for the specified SPI.
+* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral.
+* Output : None
+* Return : The CRC Polynomial register value.
+*******************************************************************************/
+u16 SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
+{
+ /* Return the CRC polynomial register */
+ return SPIx->CRCPR;
+}
+
+/*******************************************************************************
+* Function Name : SPI_BiDirectionalLineConfig
+* Description : Selects the data transfer direction in bi-directional mode
+* for the specified SPI.
+* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral.
+* - SPI_Direction: specifies the data transfer direction in
+* bi-directional mode.
+* This parameter can be one of the following values:
+* - SPI_Direction_Tx: Selects Tx transmission direction
+* - SPI_Direction_Rx: Selects Rx receive direction
+* Output : None
+* Return : None
+*******************************************************************************/
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, u16 SPI_Direction)
+{
+ /* Check the parameters */
+ assert(IS_SPI_DIRECTION(SPI_Direction));
+
+ if (SPI_Direction == SPI_Direction_Tx)
+ {
+ /* Set the Tx only mode */
+ SPIx->CR1 |= SPI_Direction_Tx;
+ }
+ else
+ {
+ /* Set the Rx only mode */
+ SPIx->CR1 &= SPI_Direction_Rx;
+ }
+}
+
+/*******************************************************************************
+* Function Name : SPI_GetFlagStatus
+* Description : Checks whether the specified SPI flag is set or not.
+* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral.
+* - SPI_FLAG: specifies the flag to check.
+* This parameter can be one of the following values:
+* - SPI_FLAG_BSY: Busy flag.
+* - SPI_FLAG_OVR: Overrun flag.
+* - SPI_FLAG_MODF: Mode Fault flag.
+* - SPI_FLAG_CRCERR: CRC Error flag.
+* - SPI_FLAG_TXE: Transmit buffer empty flag.
+* - SPI_FLAG_RXNE: Receive buffer not empty flag.
+* Output : None
+* Return : The new state of SPI_FLAG (SET or RESET).
+*******************************************************************************/
+FlagStatus SPI_GetFlagStatus(SPI_TypeDef* SPIx, u16 SPI_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert(IS_SPI_GET_FLAG(SPI_FLAG));
+
+ /* Check the status of the specified SPI flag */
+ if ((SPIx->SR & SPI_FLAG) != (u16)RESET)
+ {
+ /* SPI_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* SPI_FLAG is reset */
+ bitstatus = RESET;
+ }
+ /* Return the SPI_FLAG status */
+ return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name : SPI_ClearFlag
+* Description : Clears the SPIx's pending flags.
+* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral.
+* - SPI_FLAG: specifies the flag to clear.
+* This parameter can be any combination of the following values:
+* - SPI_FLAG_OVR: Overrun flag.
+* - SPI_FLAG_MODF: Mode Fault flag.
+* - SPI_FLAG_CRCERR: CRC Error flag.
+* Output : None
+* Return : None
+*******************************************************************************/
+void SPI_ClearFlag(SPI_TypeDef* SPIx, u16 SPI_FLAG)
+{
+ /* Check the parameters */
+ assert(IS_SPI_CLEAR_FLAG(SPI_FLAG));
+
+ /* SPI_FLAG_MODF flag clear */
+ if(SPI_FLAG == SPI_FLAG_MODF)
+ {
+ /* Read SR register */
+ (void)SPIx->SR;
+ /* Write on CR1 register */
+ SPIx->CR1 |= CR1_SPE_Set;
+ }
+ /* SPI_FLAG_OVR flag clear */
+ else if(SPI_FLAG == SPI_FLAG_OVR)
+ {
+ /* Read SR register */
+ (void)SPIx->SR;
+ }
+ else /* SPI_FLAG_CRCERR flag clear */
+ {
+ /* Clear the selected SPI flag */
+ SPIx->SR &= (u16)~SPI_FLAG;
+ }
+}
+
+/*******************************************************************************
+* Function Name : SPI_GetITStatus
+* Description : Checks whether the specified SPI interrupt has occurred or not.
+* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral.
+* - SPI_IT: specifies the SPI interrupt source to check.
+* This parameter can be one of the following values:
+* - SPI_IT_OVR: Overrun interrupt.
+* - SPI_IT_MODF: Mode Fault interrupt.
+* - SPI_IT_CRCERR: CRC Error interrupt.
+* - SPI_IT_TXE: Transmit buffer empty interrupt.
+* - SPI_IT_RXNE: Receive buffer not empty interrupt.
+* Output : None
+* Return : The new state of SPI_IT (SET or RESET).
+*******************************************************************************/
+ITStatus SPI_GetITStatus(SPI_TypeDef* SPIx, u8 SPI_IT)
+{
+ ITStatus bitstatus = RESET;
+ u16 itpos = 0, itmask = 0, enablestatus = 0;
+
+ /* Check the parameters */
+ assert(IS_SPI_GET_IT(SPI_IT));
+
+ /* Get the SPI IT index */
+ itpos = (u16)((u16)0x01 << (SPI_IT & (u8)0x0F));
+
+ /* Get the SPI IT index */
+ itmask = SPI_IT >> 4;
+ /* Set the IT mask */
+ itmask = (u16)((u16)0x01 << itmask);
+ /* Get the SPI_IT enable bit status */
+ enablestatus = (SPIx->CR2 & itmask) ;
+
+ /* Check the status of the specified SPI interrupt */
+ if (((SPIx->SR & itpos) != (u16)RESET) && enablestatus)
+ {
+ /* SPI_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* SPI_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the SPI_IT status */
+ return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name : SPI_ClearITPendingBit
+* Description : Clears the SPIs interrupt pending bits.
+* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral.
+* - SPI_IT: specifies the SPI interrupt pending bit to clear.
+* This parameter can be one of the following values:
+* - SPI_IT_OVR: Overrun interrupt.
+* - SPI_IT_MODF: Mode Fault interrupt.
+* - SPI_IT_CRCERR: CRC Error interrupt.
+* Output : None
+* Return : None
+*******************************************************************************/
+void SPI_ClearITPendingBit(SPI_TypeDef* SPIx, u8 SPI_IT)
+{
+ u16 itpos = 0;
+
+ /* Check the parameters */
+ assert(IS_SPI_CLEAR_IT(SPI_IT));
+
+ /* SPI_IT_MODF pending bit clear */
+ if(SPI_IT == SPI_IT_MODF)
+ {
+ /* Read SR register */
+ (void)SPIx->SR;
+ /* Write on CR1 register */
+ SPIx->CR1 |= CR1_SPE_Set;
+ }
+ else if(SPI_IT == SPI_IT_OVR) /* SPI_IT_OVR pending bit clear */
+ {
+ /* Read SR register */
+ (void)(SPIx->SR);
+ }
+ else /* SPI_IT_CRCERR pending bit clear */
+ {
+ /* Get the SPI IT index */
+ itpos = (u16)((u16)0x01 << (SPI_IT & (u8)0x0F));
+ /* Clear the selected SPI interrupt pending bits */
+ SPIx->SR &= (u16)~itpos;
+ }
+}
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_systick.c b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_systick.c
new file mode 100644
index 0000000..6f7a27e
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_systick.c
@@ -0,0 +1,195 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_systick.c
+* Author : MCD Application Team
+* Date First Issued : 09/29/2006
+* Description : This file provides all the SysTick firmware functions.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_systick.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* ---------------------- SysTick registers bit mask -------------------- */
+/* CTRL TICKINT Mask */
+#define CTRL_TICKINT_Set ((u32)0x00000002)
+#define CTRL_TICKINT_Reset ((u32)0xFFFFFFFD)
+
+/* SysTick Flag Mask */
+#define FLAG_Mask ((u8)0x1F)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name : SysTick_CLKSourceConfig
+* Description : Configures the SysTick clock source.
+* Input : - SysTick_CLKSource: specifies the SysTick clock source.
+* This parameter can be one of the following values:
+* - SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8
+* selected as SysTick clock source.
+* - SysTick_CLKSource_HCLK: AHB clock selected as
+* SysTick clock source.
+* Output : None
+* Return : None
+*******************************************************************************/
+void SysTick_CLKSourceConfig(u32 SysTick_CLKSource)
+{
+ /* Check the parameters */
+ assert(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
+
+ if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
+ {
+ SysTick->CTRL |= SysTick_CLKSource_HCLK;
+ }
+ else
+ {
+ SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
+ }
+}
+
+/*******************************************************************************
+* Function Name : SysTick_SetReload
+* Description : Sets SysTick Reload value.
+* Input : - Reload: SysTick Reload new value.
+* This parameter must be a number between 1 and 0xFFFFFF.
+* Output : None
+* Return : None
+*******************************************************************************/
+void SysTick_SetReload(u32 Reload)
+{
+ /* Check the parameters */
+ assert(IS_SYSTICK_RELOAD(Reload));
+
+ SysTick->LOAD = Reload;
+}
+
+/*******************************************************************************
+* Function Name : SysTick_CounterCmd
+* Description : Enables or disables the SysTick counter.
+* Input : - SysTick_Counter: new state of the SysTick counter.
+* This parameter can be one of the following values:
+* - SysTick_Counter_Disable: Disable counter
+* - SysTick_Counter_Enable: Enable counter
+* - SysTick_Counter_Clear: Clear counter value to 0
+* Output : None
+* Return : None
+*******************************************************************************/
+void SysTick_CounterCmd(u32 SysTick_Counter)
+{
+ /* Check the parameters */
+ assert(IS_SYSTICK_COUNTER(SysTick_Counter));
+
+ if (SysTick_Counter == SysTick_Counter_Clear)
+ {
+ SysTick->VAL = SysTick_Counter_Clear;
+ }
+ else
+ {
+ if (SysTick_Counter == SysTick_Counter_Enable)
+ {
+ SysTick->CTRL |= SysTick_Counter_Enable;
+ }
+ else
+ {
+ SysTick->CTRL &= SysTick_Counter_Disable;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name : SysTick_ITConfig
+* Description : Enables or disables the SysTick Interrupt.
+* Input : - NewState: new state of the SysTick Interrupt.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void SysTick_ITConfig(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ SysTick->CTRL |= CTRL_TICKINT_Set;
+ }
+ else
+ {
+ SysTick->CTRL &= CTRL_TICKINT_Reset;
+ }
+}
+
+/*******************************************************************************
+* Function Name : SysTick_GetCounter
+* Description : Gets SysTick counter value.
+* Input : None
+* Output : None
+* Return : SysTick current value
+*******************************************************************************/
+u32 SysTick_GetCounter(void)
+{
+ return(SysTick->VAL);
+}
+
+/*******************************************************************************
+* Function Name : SysTick_GetFlagStatus
+* Description : Checks whether the specified SysTick flag is set or not.
+* Input : - SysTick_FLAG: specifies the flag to check.
+* This parameter can be one of the following values:
+* - SysTick_FLAG_COUNT
+* - SysTick_FLAG_SKEW
+* - SysTick_FLAG_NOREF
+* Output : None
+* Return : None
+*******************************************************************************/
+FlagStatus SysTick_GetFlagStatus(u8 SysTick_FLAG)
+{
+ u32 tmp = 0;
+ u32 statusreg = 0;
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert(IS_SYSTICK_FLAG(SysTick_FLAG));
+
+ /* Get the SysTick register index */
+ tmp = SysTick_FLAG >> 5;
+
+ if (tmp == 1) /* The flag to check is in CTRL register */
+ {
+ statusreg = SysTick->CTRL;
+ }
+ else /* The flag to check is in CALIB register */
+ {
+ statusreg = SysTick->CALIB;
+ }
+
+ /* Get the flag position */
+ tmp = SysTick_FLAG & FLAG_Mask;
+
+ if ((statusreg & ((u32)1 << tmp)) != (u32)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_tim.c b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_tim.c
new file mode 100644
index 0000000..5fd374e
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_tim.c
@@ -0,0 +1,2348 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_tim.c
+* Author : MCD Application Team
+* Date First Issued : 09/29/2006
+* Description : This file provides all the TIM firmware functions.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_tim.h"
+#include "stm32f10x_rcc.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* ---------------------- TIM registers bit mask ------------------------ */
+#define CR1_CEN_Set ((u16)0x0001)
+#define CR1_CEN_Reset ((u16)0x03FE)
+#define CR1_UDIS_Set ((u16)0x0002)
+#define CR1_UDIS_Reset ((u16)0x03FD)
+#define CR1_URS_Set ((u16)0x0004)
+#define CR1_URS_Reset ((u16)0x03FB)
+#define CR1_OPM_Mask ((u16)0x03F7)
+#define CR1_CounterMode_Mask ((u16)0x039F)
+#define CR1_ARPE_Set ((u16)0x0080)
+#define CR1_ARPE_Reset ((u16)0x037F)
+#define CR1_CKD_Mask ((u16)0x00FF)
+
+#define CR2_CCDS_Set ((u16)0x0008)
+#define CR2_CCDS_Reset ((u16)0x0007)
+#define CR2_MMS_Mask ((u16)0x0080)
+#define CR2_TI1S_Set ((u16)0x0080)
+#define CR2_TI1S_Reset ((u16)0xFF70)
+
+#define SMCR_SMS_Mask ((u16)0xFFF0)
+#define SMCR_ETR_Mask ((u16)0x00F7)
+#define SMCR_TS_Mask ((u16)0xFF87)
+#define SMCR_MSM_Mask ((u16)0xFF77)
+#define SMCR_ECE_Set ((u16)0x4000)
+
+#define CCMR_CC13S_Mask ((u16)0x7F7C)
+#define CCMR_CC24S_Mask ((u16)0x7C7F)
+#define CCMR_TI13Direct_Set ((u16)0x0001)
+#define CCMR_TI24Direct_Set ((u16)0x0100)
+#define CCMR_OC13FE_Mask ((u16)0x7F7B)
+#define CCMR_OC24FE_Mask ((u16)0x7B7F)
+#define CCMR_OC13PE_Mask ((u16)0x7F77)
+#define CCMR_OC24PE_Mask ((u16)0x777F)
+#define CCMR_OCM13_Mask ((u16)0x7F0F)
+#define CCMR_OCM24_Mask ((u16)0x0F7F)
+#define CCMR_IC13PSC_Mask ((u16)0xFFF3)
+#define CCMR_IC24PSC_Mask ((u16)0xF3FF)
+#define CCMR_IC13F_Mask ((u16)0xFF0F)
+#define CCMR_IC24F_Mask ((u16)0x0FFF)
+#define CCER_CC1P_Mask ((u16)0xFFFD)
+
+#define CCER_CC2P_Mask ((u16)0xFFDF)
+#define CCER_CC3P_Mask ((u16)0xFDFF)
+#define CCER_CC4P_Mask ((u16)0xDFFF)
+
+#define CCRE_CC1E_Set ((u16)0x0001)
+#define CCRE_CC1E_Reset ((u16)0xFFFE)
+#define CCRE_CC1E_Mask ((u16)0xFFFE)
+
+#define CCRE_CC2E_Set ((u16)0x0010)
+#define CCRE_CC2E_Reset ((u16)0xFFEF)
+#define CCRE_CC2E_Mask ((u16)0xFFEF)
+
+#define CCRE_CC3E_Set ((u16)0x0100)
+#define CCRE_CC3E_Reset ((u16)0xFEFF)
+
+#define CCRE_CC4E_Set ((u16)0x1000)
+#define CCRE_CC4E_Reset ((u16)0xEFFF)
+#define CCRE_CC4E_Mask ((u16)0xEFFF)
+
+#define DCR_DMA_Mask ((u16)0x0000)
+
+/* TIM private Masks */
+#define TIM_Period_Reset_Mask ((u16)0x0000)
+#define TIM_Prescaler_Reset_Mask ((u16)0x0000)
+#define TIM_Pulse_Reset_Mask ((u16)0x0000)
+#define TIM_ICFilter_Mask ((u8)0x00)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+static uc16 Tab_OCModeMask[4] = {0xFF00, 0x00FF, 0xFF00, 0x00FF};
+static uc16 Tab_PolarityMask[4] = {CCER_CC1P_Mask, CCER_CC2P_Mask, CCER_CC3P_Mask, CCER_CC4P_Mask};
+
+/* Private function prototypes -----------------------------------------------*/
+static void PWMI_Config(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
+static void TI1_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection,
+ u8 TIM_ICFilter);
+static void TI2_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection,
+ u8 TIM_ICFilter);
+static void TI3_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection,
+ u8 TIM_ICFilter);
+static void TI4_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection,
+ u8 TIM_ICFilter);
+static void ETR_Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler,
+ u16 TIM_ExtTRGPolarity, u8 ExtTRGFilter);
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name : TIM_DeInit
+* Description : Deinitializes the TIMx peripheral registers to their default
+* reset values.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_DeInit(TIM_TypeDef* TIMx)
+{
+ switch (*(u32*)&TIMx)
+ {
+ case TIM2_BASE:
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
+ break;
+
+ case TIM3_BASE:
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
+ break;
+
+ case TIM4_BASE:
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name : TIM_TimeBaseInit
+* Description : Initializes the TIMx Time Base Unit peripheral according to
+* the specified parameters in the TIM_TimeBaseInitStruct.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef
+* structure that contains the configuration information for
+* the specified TIM peripheral.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
+{
+ /* Check the parameters */
+ assert(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
+ assert(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
+
+ /* Set the Autoreload value */
+ TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
+
+ /* Set the Prescaler value */
+ TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
+
+ /* Select the Counter Mode and set the clock division */
+ TIMx->CR1 &= CR1_CKD_Mask & CR1_CounterMode_Mask;
+ TIMx->CR1 |= (u32)TIM_TimeBaseInitStruct->TIM_ClockDivision |
+ TIM_TimeBaseInitStruct->TIM_CounterMode;
+}
+/*******************************************************************************
+* Function Name : TIM_OCInit
+* Description : Initializes the TIMx peripheral according to the specified
+* parameters in the TIM_OCInitStruct.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
+* that contains the configuration information for the specified
+* TIM peripheral.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_OCInit(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+ u32 tmpccmrx = 0, tmpccer = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+ assert(IS_TIM_CHANNEL(TIM_OCInitStruct->TIM_Channel));
+ assert(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
+
+ tmpccer = TIMx->CCER;
+
+ if ((TIM_OCInitStruct->TIM_Channel == (u16)TIM_Channel_1) ||
+ (TIM_OCInitStruct->TIM_Channel == (u16)TIM_Channel_2))
+ {
+ tmpccmrx = TIMx->CCMR1;
+
+ /* Reset the Output Compare Bits */
+ tmpccmrx &= Tab_OCModeMask[TIM_OCInitStruct->TIM_Channel];
+
+ /* Set the Output Polarity level */
+ tmpccer &= Tab_PolarityMask[TIM_OCInitStruct->TIM_Channel];
+
+ if (TIM_OCInitStruct->TIM_Channel == TIM_Channel_1)
+ {
+ /* Disable the Channel 1: Reset the CCE Bit */
+ TIMx->CCER &= CCRE_CC1E_Reset;
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
+
+ /* Set the Capture Compare Enable Bit */
+ tmpccer |= CCRE_CC1E_Set;
+
+ /* Set the Capture Compare Polarity */
+ tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
+ }
+ else /* TIM_Channel_2 */
+ {
+ /* Disable the Channel 2: Reset the CCE Bit */
+ TIMx->CCER &= CCRE_CC2E_Reset;
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (u32)TIM_OCInitStruct->TIM_OCMode << 8;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
+
+ /* Set the Capture Compare Enable Bit */
+ tmpccer |= CCRE_CC2E_Set;
+
+ /* Set the Capture Compare Polarity */
+ tmpccer |= (u32)TIM_OCInitStruct->TIM_OCPolarity << 4;
+ }
+
+ TIMx->CCMR1 = (u16)tmpccmrx;
+ }
+ else
+ {
+ if ((TIM_OCInitStruct->TIM_Channel == TIM_Channel_3) ||
+ (TIM_OCInitStruct->TIM_Channel == TIM_Channel_4))
+ {
+ tmpccmrx = TIMx->CCMR2;
+
+ /* Reset the Output Compare Bits */
+ tmpccmrx &= Tab_OCModeMask[TIM_OCInitStruct->TIM_Channel];
+
+ /* Set the Output Polarity level */
+ tmpccer &= Tab_PolarityMask[TIM_OCInitStruct->TIM_Channel];
+
+ if (TIM_OCInitStruct->TIM_Channel == TIM_Channel_3)
+ {
+ /* Disable the Channel 3: Reset the CCE Bit */
+ TIMx->CCER &= CCRE_CC3E_Reset;
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
+
+ /* Set the Capture Compare Enable Bit */
+ tmpccer |= CCRE_CC3E_Set;
+
+ /* Set the Capture Compare Polarity */
+ tmpccer |= (u32)TIM_OCInitStruct->TIM_OCPolarity << 8;
+ }
+ else /* TIM_Channel_4 */
+ {
+ /* Disable the Channel 4: Reset the CCE Bit */
+ TIMx->CCER &= CCRE_CC4E_Reset;
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (u32)TIM_OCInitStruct->TIM_OCMode << 8;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
+
+ /* Set the Capture Compare Enable Bit */
+ tmpccer |= CCRE_CC4E_Set;
+
+ /* Set the Capture Compare Polarity */
+ tmpccer |= (u32)TIM_OCInitStruct->TIM_OCPolarity << 12;
+ }
+
+ TIMx->CCMR2 = (u16)tmpccmrx;
+ }
+ }
+
+ TIMx->CCER = (u16)tmpccer;
+}
+
+/*******************************************************************************
+* Function Name : TIM_ICInit
+* Description : Initializes the TIMx peripheral according to the specified
+* parameters in the TIM_ICInitStruct.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
+* that contains the configuration information for the specified
+* TIM peripheral.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
+{
+ /* Check the parameters */
+ assert(IS_TIM_IC_MODE(TIM_ICInitStruct->TIM_ICMode));
+ assert(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel));
+ assert(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
+ assert(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
+ assert(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
+ assert(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
+
+ if (TIM_ICInitStruct->TIM_ICMode == TIM_ICMode_ICAP)
+ {
+ if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
+ {
+ /* TI1 Configuration */
+ TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+ TIM_ICInitStruct->TIM_ICSelection,
+ TIM_ICInitStruct->TIM_ICFilter);
+
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ }
+ else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
+ {
+ /* TI2 Configuration */
+ TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+ TIM_ICInitStruct->TIM_ICSelection,
+ TIM_ICInitStruct->TIM_ICFilter);
+
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ }
+ else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
+ {
+ /* TI3 Configuration */
+ TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+ TIM_ICInitStruct->TIM_ICSelection,
+ TIM_ICInitStruct->TIM_ICFilter);
+
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ }
+ else /* TIM_Channel_4 */
+ {
+ /* TI4 Configuration */
+ TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+ TIM_ICInitStruct->TIM_ICSelection,
+ TIM_ICInitStruct->TIM_ICFilter);
+
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ }
+ }
+ else
+ {
+ PWMI_Config(TIMx, TIM_ICInitStruct);
+ }
+}
+
+/*******************************************************************************
+* Function Name : TIM_TimeBaseStructInit
+* Description : Fills each TIM_TimeBaseInitStruct member with its default value.
+* Input : - TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef
+* structure which will be initialized.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
+{
+ /* Set the default configuration */
+ TIM_TimeBaseInitStruct->TIM_Period = TIM_Period_Reset_Mask;
+ TIM_TimeBaseInitStruct->TIM_Prescaler = TIM_Prescaler_Reset_Mask;
+ TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
+ TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
+}
+
+/*******************************************************************************
+* Function Name : TIM_OCStructInit
+* Description : Fills each TIM_OCInitStruct member with its default value.
+* Input : - TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
+* which will be initialized.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+ /* Set the default configuration */
+ TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
+ TIM_OCInitStruct->TIM_Channel = TIM_Channel_1;
+ TIM_OCInitStruct->TIM_Pulse = TIM_Pulse_Reset_Mask;
+ TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
+}
+
+/*******************************************************************************
+* Function Name : TIM_ICStructInit
+* Description : Fills each TIM_InitStruct member with its default value.
+* Input : - TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
+* which will be initialized.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
+{
+ /* Set the default configuration */
+ TIM_ICInitStruct->TIM_ICMode = TIM_ICMode_ICAP;
+ TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
+ TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
+ TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
+ TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
+ TIM_ICInitStruct->TIM_ICFilter = TIM_ICFilter_Mask;
+}
+
+/*******************************************************************************
+* Function Name : TIM_Cmd
+* Description : Enables or disables the specified TIM peripheral.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIMx peripheral.
+* - Newstate: new state of the TIMx peripheral.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the TIM Counter */
+ TIMx->CR1 |= CR1_CEN_Set;
+ }
+ else
+ {
+ /* Disable the TIM Counter */
+ TIMx->CR1 &= CR1_CEN_Reset;
+ }
+}
+
+/*******************************************************************************
+* Function Name : TIM_ITConfig
+* Description : Enables or disables the TIMx interrupts.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_IT: specifies the TIM interrupts sources to be enabled
+* or disabled.
+* This parameter can be any combination of the following values:
+* - TIM_IT_Update: Timer update Interrupt
+* - TIM_IT_CC1: Capture Compare 1 Interrupt
+* - TIM_IT_CC2: Capture Compare 2 Interrupt
+* - TIM_IT_CC3: Capture Compare 3 Interrupt
+* - TIM_IT_CC4: Capture Compare 4 Interrupt
+* - TIM_IT_Trigger: Trigger Interrupt
+* - Newstate: new state of the specified TIMx interrupts.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_ITConfig(TIM_TypeDef* TIMx, u16 TIM_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_TIM_IT(TIM_IT));
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the Interrupt sources */
+ TIMx->DIER |= TIM_IT;
+ }
+ else
+ {
+ /* Disable the Interrupt sources */
+ TIMx->DIER &= (u16)(~TIM_IT);
+ }
+}
+
+/*******************************************************************************
+* Function Name : TIM_DMAConfig
+* Description : Configures the TIMxs DMA interface.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_DMABase: DMA Base address.
+* This parameter can be one of the following values:
+* - TIM_DMABase_CR1, TIM_DMABase_CR2, TIM_DMABase_SMCR,
+* TIM_DMABase_DIER, TIM_DMABase_SR, TIM_DMABase_EGR,
+* TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,
+* TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,
+* TIM_DMABase_CCR1, TIM_DMABase_CCR2, TIM_DMABase_CCR3,
+* TIM_DMABase_CCR4, TIM_DMABase_DCR.
+* - TIM_DMABurstLength: DMA Burst length.
+* This parameter can be one value between:
+* TIM_DMABurstLength_1Byte and TIM_DMABurstLength_18Bytes.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_DMAConfig(TIM_TypeDef* TIMx, u16 TIM_DMABase, u16 TIM_DMABurstLength)
+{
+ u32 tmpdcr = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM_DMA_BASE(TIM_DMABase));
+ assert(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
+
+ tmpdcr = TIMx->DCR;
+
+ /* Reset the DBA and the DBL Bits */
+ tmpdcr &= DCR_DMA_Mask;
+
+ /* Set the DMA Base and the DMA Burst Length */
+ tmpdcr |= TIM_DMABase | TIM_DMABurstLength;
+
+ TIMx->DCR = (u16)tmpdcr;
+}
+
+/*******************************************************************************
+* Function Name : TIM_DMACmd
+* Description : Enables or disables the TIMxs DMA Requests.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_DMASources: specifies the DMA Request sources.
+* This parameter can be any combination of the following values:
+* - TIM_DMA_CC1: Capture Compare 1 DMA source
+* - TIM_DMA_CC2: Capture Compare 2 DMA source
+* - TIM_DMA_CC3: Capture Compare 3 DMA source
+* - TIM_DMA_CC4: Capture Compare 4 DMA source
+* - TIM_DMA_Trigger: Trigger DMA source
+* - Newstate: new state of the DMA Request sources.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_DMACmd(TIM_TypeDef* TIMx, u16 TIM_DMASource, FunctionalState Newstate)
+{
+ u32 tmpdier = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM_DMA_SOURCE(TIM_DMASource));
+ assert(IS_FUNCTIONAL_STATE(Newstate));
+
+ tmpdier = TIMx->DIER;
+
+ if (Newstate != DISABLE)
+ {
+ /* Enable the DMA sources */
+ tmpdier |= TIM_DMASource;
+ }
+ else
+ {
+ /* Disable the DMA sources */
+ tmpdier &= (u16)(~TIM_DMASource);
+ }
+ TIMx->DIER = (u16)tmpdier;
+}
+
+/*******************************************************************************
+* Function Name : TIM_InternalClockConfig
+* Description : Configures the TIMx interrnal Clock
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
+{
+ /* Disable slave mode to clock the prescaler directly with the internal clock */
+ TIMx->SMCR &= SMCR_SMS_Mask;
+}
+/*******************************************************************************
+* Function Name : TIM_ITRxExternalClockConfig
+* Description : Configures the TIMx Internal Trigger as External Clock
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_ITRSource: Trigger source.
+* This parameter can be one of the following values:
+* - TIM_TS_ITR0: Internal Trigger 0
+* - TIM_TS_ITR1: Internal Trigger 1
+* - TIM_TS_ITR2: Internal Trigger 2
+* - TIM_TS_ITR3: Internal Trigger 3
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource)
+{
+ /* Check the parameters */
+ assert(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
+
+ /* Select the Internal Trigger */
+ TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
+
+ /* Select the External clock mode1 */
+ TIMx->SMCR |= TIM_SlaveMode_External1;
+}
+/*******************************************************************************
+* Function Name : TIM_TIxExternalClockConfig
+* Description : Configures the TIMx Trigger as External Clock
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_TIxExternalCLKSource: Trigger source.
+* This parameter can be one of the following values:
+* - TIM_TS_TI1F_ED: TI1 Edge Detector
+* - TIM_TS_TI1FP1: Filtered Timer Input 1
+* - TIM_TS_TI2FP2: Filtered Timer Input 2
+* - TIM_ICPolarity: specifies the TIx Polarity.
+* This parameter can be:
+* - TIM_ICPolarity_Rising
+* - TIM_ICPolarity_Falling
+* - ICFilter : specifies the filter value.
+* This parameter must be a value between 0x0 and 0xF.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, u16 TIM_TIxExternalCLKSource,
+ u16 TIM_ICPolarity, u8 ICFilter)
+{
+ /* Check the parameters */
+ assert(IS_TIM_TIX_TRIGGER_SELECTION(TIM_TIxExternalCLKSource));
+ assert(IS_TIM_IC_POLARITY(TIM_ICPolarity));
+ assert(IS_TIM_IC_FILTER(ICFilter));
+
+ /* Configure the Timer Input Clock Source */
+ if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
+ {
+ TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
+ }
+ else
+ {
+ TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
+ }
+
+ /* Select the Trigger source */
+ TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
+
+ /* Select the External clock mode1 */
+ TIMx->SMCR |= TIM_SlaveMode_External1;
+}
+
+/*******************************************************************************
+* Function Name : TIM_ETRClockMode1Config
+* Description : Configures the External clock Mode1
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+* It can be one of the following values:
+* - TIM_ExtTRGPSC_OFF
+* - TIM_ExtTRGPSC_DIV2
+* - TIM_ExtTRGPSC_DIV4
+* - TIM_ExtTRGPSC_DIV8.
+* - TIM_ExtTRGPolarity: The external Trigger Polarity.
+* It can be one of the following values:
+* - TIM_ExtTRGPolarity_Inverted
+* - TIM_ExtTRGPolarity_NonInverted
+* - ExtTRGFilter: External Trigger Filter.
+* This parameter must be a value between 0x00 and 0x0F
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity,
+ u8 ExtTRGFilter)
+{
+ /* Check the parameters */
+ assert(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
+ assert(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
+
+ /* Configure the ETR Clock source */
+ ETR_Config(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
+
+ /* Select the External clock mode1 */
+ TIMx->SMCR &= SMCR_SMS_Mask;
+ TIMx->SMCR |= TIM_SlaveMode_External1;
+
+ /* Select the Trigger selection : ETRF */
+ TIMx->SMCR &= SMCR_TS_Mask;
+ TIMx->SMCR |= TIM_TS_ETRF;
+}
+
+/*******************************************************************************
+* Function Name : TIM_ETRClockMode2Config
+* Description : Configures the External clock Mode2
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+* It can be one of the following values:
+* - TIM_ExtTRGPSC_OFF
+* - TIM_ExtTRGPSC_DIV2
+* - TIM_ExtTRGPSC_DIV4
+* - TIM_ExtTRGPSC_DIV8
+* - TIM_ExtTRGPolarity: The external Trigger Polarity.
+* It can be one of the following values:
+* - TIM_ExtTRGPolarity_Inverted
+* - TIM_ExtTRGPolarity_NonInverted
+* - ExtTRGFilter: External Trigger Filter.
+* This parameter must be a value between 0x00 and 0x0F
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler,
+ u16 TIM_ExtTRGPolarity, u8 ExtTRGFilter)
+{
+ /* Check the parameters */
+ assert(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
+ assert(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
+
+ /* Configure the ETR Clock source */
+ ETR_Config(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
+
+ /* Enable the External clock mode2 */
+ TIMx->SMCR |= SMCR_ECE_Set;
+}
+/*******************************************************************************
+* Function Name : TIM_SelectInputTrigger
+* Description : Selects the Input Trigger source
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_InputTriggerSource: The Input Trigger source.
+* This parameter can be one of the following values:
+* - TIM_TS_ITR0: Internal Trigger 0
+* - TIM_TS_ITR1: Internal Trigger 1
+* - TIM_TS_ITR2: Internal Trigger 2
+* - TIM_TS_ITR3: Internal Trigger 3
+* - TIM_TS_TI1F_ED: TI1 Edge Detector
+* - TIM_TS_TI1FP1: Filtered Timer Input 1
+* - TIM_TS_TI2FP2: Filtered Timer Input 2
+* - TIM_TS_ETRF: External Trigger input
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource)
+{
+ u32 tmpsmcr = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
+
+ tmpsmcr = TIMx->SMCR;
+
+ /* Select the Tgigger Source */
+ tmpsmcr &= SMCR_TS_Mask;
+ tmpsmcr |= TIM_InputTriggerSource;
+
+ TIMx->SMCR = (u16)tmpsmcr;
+}
+
+/*******************************************************************************
+* Function Name : TIM_PrescalerConfig
+* Description : Configures the TIMx Prescaler.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - Prescaler: specifies the Prescaler Register value
+* - TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
+* This parameter can be one of the following values:
+* - TIM_PSCReloadMode_Update: The Prescaler is loaded at
+* the update event.
+* - TIM_PSCReloadMode_Immediate: The Prescaler is loaded
+* immediatly.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, u16 Prescaler, u16 TIM_PSCReloadMode)
+{
+ /* Check the parameters */
+ assert(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
+
+ /* Set the Prescaler value */
+ TIMx->PSC = Prescaler;
+
+ /* Set or reset the UG Bit */
+ if (TIM_PSCReloadMode == TIM_PSCReloadMode_Immediate)
+ {
+ TIMx->EGR |= TIM_EventSource_Update;
+ }
+ else
+ {
+ TIMx->EGR &= TIM_EventSource_Update;
+ }
+}
+
+/*******************************************************************************
+* Function Name : TIM_CounterModeConfig
+* Description : Specifies the TIMx Counter Mode to be used.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_CounterMode: specifies the Counter Mode to be used
+* This parameter can be one of the following values:
+* - TIM_CounterMode_Up: TIM Up Counting Mode
+* - TIM_CounterMode_Down: TIM Down Counting Mode
+* - TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
+* - TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
+* - TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, u16 TIM_CounterMode)
+{
+ u32 tmpcr1 = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM_COUNTER_MODE(TIM_CounterMode));
+
+ tmpcr1 = TIMx->CR1;
+
+ /* Reset the CMS and DIR Bits */
+ tmpcr1 &= CR1_CounterMode_Mask;
+
+ /* Set the Counter Mode */
+ tmpcr1 |= TIM_CounterMode;
+
+ TIMx->CR1 = (u16)tmpcr1;
+}
+
+/*******************************************************************************
+* Function Name : TIM_ForcedOC1Config
+* Description : Forces the TIMx output 1 waveform to active or inactive level.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_ForcedAction: specifies the forced Action to be set to
+* the output waveform.
+* This parameter can be one of the following values:
+* - TIM_ForcedAction_Active: Force active level on OC1REF
+* - TIM_ForcedAction_InActive: Force inactive level on
+* OC1REF.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction)
+{
+ u32 tmpccmr1 = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+
+ tmpccmr1 = TIMx->CCMR1;
+
+ /* Reset the OCM Bits */
+ tmpccmr1 &= CCMR_OCM13_Mask;
+
+ /* Configure The Forced output Mode */
+ tmpccmr1 |= TIM_ForcedAction;
+
+ TIMx->CCMR1 = (u16)tmpccmr1;
+}
+
+/*******************************************************************************
+* Function Name : TIM_ForcedOC2Config
+* Description : Forces the TIMx output 2 waveform to active or inactive level.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_ForcedAction: specifies the forced Action to be set to
+* the output waveform.
+* This parameter can be one of the following values:
+* - TIM_ForcedAction_Active: Force active level on OC2REF
+* - TIM_ForcedAction_InActive: Force inactive level on
+* OC2REF.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction)
+{
+ u32 tmpccmr1 = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+
+ tmpccmr1 = TIMx->CCMR1;
+
+ /* Reset the OCM Bits */
+ tmpccmr1 &= CCMR_OCM24_Mask;
+
+ /* Configure The Forced output Mode */
+ tmpccmr1 |= (u16)(TIM_ForcedAction << 8);
+
+ TIMx->CCMR1 = (u16)tmpccmr1;
+}
+
+/*******************************************************************************
+* Function Name : TIM_ForcedOC3Config
+* Description : Forces the TIMx output 3 waveform to active or inactive level.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_ForcedAction: specifies the forced Action to be set to
+* the output waveform.
+* This parameter can be one of the following values:
+* - TIM_ForcedAction_Active: Force active level on OC3REF
+* - TIM_ForcedAction_InActive: Force inactive level on
+* OC3REF.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction)
+{
+ u32 tmpccmr2 = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+
+ tmpccmr2 = TIMx->CCMR2;
+
+ /* Reset the OCM Bits */
+ tmpccmr2 &= CCMR_OCM13_Mask;
+
+ /* Configure The Forced output Mode */
+ tmpccmr2 |= TIM_ForcedAction;
+
+ TIMx->CCMR2 = (u16)tmpccmr2;
+}
+
+/*******************************************************************************
+* Function Name : TIM_ForcedOC4Config
+* Description : Forces the TIMx output 4 waveform to active or inactive level.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_ForcedAction: specifies the forced Action to be set to
+* the output waveform.
+* This parameter can be one of the following values:
+* - TIM_ForcedAction_Active: Force active level on OC4REF
+* - TIM_ForcedAction_InActive: Force inactive level on
+* OC4REF.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction)
+{
+ u32 tmpccmr2 = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+
+ tmpccmr2 = TIMx->CCMR2;
+
+ /* Reset the OCM Bits */
+ tmpccmr2 &= CCMR_OCM24_Mask;
+
+ /* Configure The Forced output Mode */
+ tmpccmr2 |= (u16)(TIM_ForcedAction << 8);
+
+ TIMx->CCMR2 = (u16)tmpccmr2;
+}
+
+/*******************************************************************************
+* Function Name : TIM_ARRPreloadConfig
+* Description : Enables or disables TIMx peripheral Preload register on ARR.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - Newstate: new state of the TIMx peripheral Preload register
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState Newstate)
+{
+ u32 tmpcr1 = 0;
+
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(Newstate));
+
+ tmpcr1 = TIMx->CR1;
+
+ if (Newstate != DISABLE)
+ {
+ /* Set the ARR Preload Bit */
+ tmpcr1 |= CR1_ARPE_Set;
+ }
+ else
+ {
+ /* Reset the ARR Preload Bit */
+ tmpcr1 &= CR1_ARPE_Reset;
+ }
+
+ TIMx->CR1 = (u16)tmpcr1;
+}
+
+/*******************************************************************************
+* Function Name : TIM_SelectCCDMA
+* Description : Selects the TIMx peripheral Capture Compare DMA source.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - Newstate: new state of the Capture Compare DMA source
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState Newstate)
+{
+ u32 tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(Newstate));
+
+ tmpcr2 = TIMx->CR2;
+
+ if (Newstate != DISABLE)
+ {
+ /* Set the CCDS Bit */
+ tmpcr2 |= CR2_CCDS_Set;
+ }
+ else
+ {
+ /* Reset the CCDS Bit */
+ tmpcr2 &= CR2_CCDS_Reset;
+ }
+
+ TIMx->CR2 = (u16)tmpcr2;
+}
+
+/*******************************************************************************
+* Function Name : TIM_OC1PreloadConfig
+* Description : Enables or disables the TIMx peripheral Preload register on CCR1.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_OCPreload: new state of the TIMx peripheral Preload
+* register
+* This parameter can be one of the following values:
+* - TIM_OCPreload_Enable
+* - TIM_OCPreload_Disable
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload)
+{
+ u32 tmpccmr1 = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+
+ tmpccmr1 = TIMx->CCMR1;
+
+ /* Reset the OCPE Bit */
+ tmpccmr1 &= CCMR_OC13PE_Mask;
+
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr1 |= TIM_OCPreload;
+
+ TIMx->CCMR1 = (u16)tmpccmr1;
+}
+
+/*******************************************************************************
+* Function Name : TIM_OC2PreloadConfig
+* Description : Enables or disables the TIMx peripheral Preload register on CCR2.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_OCPreload: new state of the TIMx peripheral Preload
+* register
+* This parameter can be one of the following values:
+* - TIM_OCPreload_Enable
+* - TIM_OCPreload_Disable
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload)
+{
+ u32 tmpccmr1 = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+
+ tmpccmr1 = TIMx->CCMR1;
+
+ /* Reset the OCPE Bit */
+ tmpccmr1 &= CCMR_OC24PE_Mask;
+
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr1 |= (u16)(TIM_OCPreload << 8);
+
+ TIMx->CCMR1 = (u16)tmpccmr1;
+}
+
+/*******************************************************************************
+* Function Name : TIM_OC3PreloadConfig
+* Description : Enables or disables the TIMx peripheral Preload register on CCR3.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_OCPreload: new state of the TIMx peripheral Preload
+* register
+* This parameter can be one of the following values:
+* - TIM_OCPreload_Enable
+* - TIM_OCPreload_Disable
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload)
+{
+ u32 tmpccmr2 = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+
+ tmpccmr2 = TIMx->CCMR2;
+
+ /* Reset the OCPE Bit */
+ tmpccmr2 &= CCMR_OC13PE_Mask;
+
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr2 |= TIM_OCPreload;
+
+ TIMx->CCMR2 = (u16)tmpccmr2;
+}
+
+/*******************************************************************************
+* Function Name : TIM_OC4PreloadConfig
+* Description : Enables or disables the TIMx peripheral Preload register on CCR4.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_OCPreload: new state of the TIMx peripheral Preload
+* register
+* This parameter can be one of the following values:
+* - TIM_OCPreload_Enable
+* - TIM_OCPreload_Disable
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload)
+{
+ u32 tmpccmr2 = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+
+ tmpccmr2 = TIMx->CCMR2;
+
+ /* Reset the OCPE Bit */
+ tmpccmr2 &= CCMR_OC24PE_Mask;
+
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr2 |= (u16)(TIM_OCPreload << 8);
+
+ TIMx->CCMR2 = (u16)tmpccmr2;
+}
+
+/*******************************************************************************
+* Function Name : TIM_OC1FastConfig
+* Description : Configures the TIMx Output Compare 1 Fast feature.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+* This parameter can be one of the following values:
+* - TIM_OCFast_Enable
+* - TIM_OCFast_Disable
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast)
+{
+ u32 tmpccmr1 = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM_OCFAST_STATE(TIM_OCFast));
+
+ tmpccmr1 = TIMx->CCMR1;
+
+ /* Reset the OCFE Bit */
+ tmpccmr1 &= CCMR_OC13FE_Mask;
+
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr1 |= TIM_OCFast;
+
+ TIMx->CCMR1 = (u16)tmpccmr1;
+}
+
+/*******************************************************************************
+* Function Name : TIM_OC2FastConfig
+* Description : Configures the TIMx Output Compare 2 Fast feature.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+* This parameter can be one of the following values:
+* - TIM_OCFast_Enable
+* - TIM_OCFast_Disable
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast)
+{
+ u32 tmpccmr1 = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM_OCFAST_STATE(TIM_OCFast));
+
+ tmpccmr1 = TIMx->CCMR1;
+
+ /* Reset the OCFE Bit */
+ tmpccmr1 &= CCMR_OC24FE_Mask;
+
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr1 |= (u16)(TIM_OCFast << 8);
+
+ TIMx->CCMR1 = (u16)tmpccmr1;
+}
+
+/*******************************************************************************
+* Function Name : TIM_OC3FastConfig
+* Description : Configures the TIMx Output Compare 3 Fast feature.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+* This parameter can be one of the following values:
+* - TIM_OCFast_Enable
+* - TIM_OCFast_Disable
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast)
+{
+ u32 tmpccmr2 = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM_OCFAST_STATE(TIM_OCFast));
+
+ tmpccmr2 = TIMx->CCMR2;
+
+ /* Reset the OCFE Bit */
+ tmpccmr2 &= CCMR_OC13FE_Mask;
+
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr2 |= TIM_OCFast;
+
+ TIMx->CCMR2 = (u16)tmpccmr2;
+}
+
+/*******************************************************************************
+* Function Name : TIM_OC4FastConfig
+* Description : Configures the TIMx Output Compare 4 Fast feature.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+* This parameter can be one of the following values:
+* - TIM_OCFast_Enable
+* - TIM_OCFast_Disable
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast)
+{
+ u32 tmpccmr2 = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM_OCFAST_STATE(TIM_OCFast));
+
+ tmpccmr2 = TIMx->CCMR2;
+
+ /* Reset the OCFE Bit */
+ tmpccmr2 &= CCMR_OC24FE_Mask;
+
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr2 |= (u16)(TIM_OCFast << 8);
+
+ TIMx->CCMR2 = (u16)tmpccmr2;
+}
+
+/*******************************************************************************
+* Function Name : TIM_UpdateDisableConfig
+* Description : Enables or Disables the TIMx Update event.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - Newstate: new state of the TIMx peripheral Preload register
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState Newstate)
+{
+ u32 tmpcr1 = 0;
+
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(Newstate));
+
+ tmpcr1 = TIMx->CR1;
+
+ if (Newstate != DISABLE)
+ {
+ /* Set the Update Disable Bit */
+ tmpcr1 |= CR1_UDIS_Set;
+ }
+ else
+ {
+ /* Reset the Update Disable Bit */
+ tmpcr1 &= CR1_UDIS_Reset;
+ }
+
+ TIMx->CR1 = (u16)tmpcr1;
+}
+
+/*******************************************************************************
+* Function Name : TIM_EncoderInterfaceConfig
+* Description : Configures the TIMx Encoder Interface.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_EncoderMode: specifies the TIMx Encoder Mode.
+* This parameter can be one of the following values:
+* - TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge
+* depending on TI2FP2 level.
+* - TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge
+* depending on TI1FP1 level.
+* - TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and
+* TI2FP2 edges depending on the level of the other input.
+* - TIM_IC1Polarity: specifies the IC1 Polarity
+* This parmeter can be one of the following values:
+* - TIM_ICPolarity_Falling
+* - TIM_ICPolarity_Rising
+* - TIM_IC2Polarity: specifies the IC2 Polarity
+* This parmeter can be one of the following values:
+* - TIM_ICPolarity_Falling
+* - TIM_ICPolarity_Rising
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, u16 TIM_EncoderMode,
+ u16 TIM_IC1Polarity, u16 TIM_IC2Polarity)
+{
+ u32 tmpsmcr = 0;
+ u32 tmpccmr1 = 0;
+ u32 tmpccer = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
+ assert(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
+ assert(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
+
+ tmpsmcr = TIMx->SMCR;
+ tmpccmr1 = TIMx->CCMR1;
+ tmpccer = TIMx->CCER;
+
+ /* Set the encoder Mode */
+ tmpsmcr &= SMCR_SMS_Mask;
+ tmpsmcr |= TIM_EncoderMode;
+
+ /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+ tmpccmr1 &= CCMR_CC13S_Mask & CCMR_CC24S_Mask;
+ tmpccmr1 |= CCMR_TI13Direct_Set | CCMR_TI24Direct_Set;
+
+ /* Set the TI1 and the TI2 Polarities */
+ tmpccer &= CCER_CC1P_Mask & CCER_CC2P_Mask;
+ tmpccer |= (TIM_IC1Polarity | (u16)((u16)TIM_IC2Polarity << 4));
+
+ TIMx->SMCR = (u16)tmpsmcr;
+
+ TIMx->CCMR1 = (u16)tmpccmr1;
+
+ TIMx->CCER = (u16)tmpccer;
+}
+
+/*******************************************************************************
+* Function Name : TIM_GenerateEvent
+* Description : Configures the TIMx event to be generate by software.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_EventSource: specifies the event source.
+* This parameter can be one or more of the following values:
+* - TIM_EventSource_Update: Timer update Event source
+* - TIM_EventSource_CC1: Timer Capture Compare 1 Event source
+* - TIM_EventSource_CC2: Timer Capture Compare 2 Event source
+* - TIM_EventSource_CC3: Timer Capture Compare 3 Event source
+* - TIM_EventSource_CC4: Timer Capture Compare 4 Event source
+* - TIM_EventSource_Trigger: Timer Trigger Event source
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, u16 TIM_EventSource)
+{
+ /* Check the parameters */
+ assert(IS_TIM_EVENT_SOURCE(TIM_EventSource));
+
+ /* Set the event sources */
+ TIMx->EGR |= TIM_EventSource;
+}
+
+/*******************************************************************************
+* Function Name : TIM_OC1PolarityConfig
+* Description : Configures the TIMx channel 1 polarity.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_OCPolarity: specifies the OC1 Polarity
+* This parmeter can be one of the following values:
+* - TIM_OCPolarity_High: Output Compare active high
+* - TIM_OCPolarity_Low: Output Compare active low
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity)
+{
+ u32 tmpccer = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+
+ tmpccer = TIMx->CCER;
+
+ /* Set or Reset the CC1P Bit */
+ tmpccer &= CCER_CC1P_Mask;
+ tmpccer |= TIM_OCPolarity;
+
+ TIMx->CCER = (u16)tmpccer;
+}
+
+/*******************************************************************************
+* Function Name : TIM_OC2PolarityConfig
+* Description : Configures the TIMx channel 2 polarity.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_OCPolarity: specifies the OC2 Polarity
+* This parmeter can be one of the following values:
+* - TIM_OCPolarity_High: Output Compare active high
+* - TIM_OCPolarity_Low: Output Compare active low
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity)
+{
+ u32 tmpccer = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+
+ tmpccer = TIMx->CCER;
+
+ /* Set or Reset the CC2P Bit */
+ tmpccer &= CCER_CC2P_Mask;
+ tmpccer |= (u16)((u16)TIM_OCPolarity << 4);
+
+ TIMx->CCER = (u16)tmpccer;
+}
+
+/*******************************************************************************
+* Function Name : TIM_OC3PolarityConfig
+* Description : Configures the TIMx channel 3 polarity.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_OCPolarity: specifies the OC3 Polarity
+* This parmeter can be one of the following values:
+* - TIM_OCPolarity_High: Output Compare active high
+* - TIM_OCPolarity_Low: Output Compare active low
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity)
+{
+ u32 tmpccer = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+
+ tmpccer = TIMx->CCER;
+
+ /* Set or Reset the CC3P Bit */
+ tmpccer &= CCER_CC3P_Mask;
+ tmpccer |= (u16)((u16)TIM_OCPolarity << 8);
+
+ TIMx->CCER = (u16)tmpccer;
+}
+
+/*******************************************************************************
+* Function Name : TIM_OC4PolarityConfig
+* Description : Configures the TIMx channel 4 polarity.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_OCPolarity: specifies the OC4 Polarity
+* This parmeter can be one of the following values:
+* - TIM_OCPolarity_High: Output Compare active high
+* - TIM_OCPolarity_Low: Output Compare active low
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity)
+{
+ u32 tmpccer = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+
+ tmpccer = TIMx->CCER;
+
+ /* Set or Reset the CC4P Bit */
+ tmpccer &= CCER_CC4P_Mask;
+ tmpccer |= (u16)((u16)TIM_OCPolarity << 12);
+
+ TIMx->CCER = (u16)tmpccer;
+}
+
+/*******************************************************************************
+* Function Name : TIM_UpdateRequestConfig
+* Description : Configures the TIMx Update Request Interrupt source.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_UpdateSource: specifies the Update source.
+* This parameter can be one of the following values:
+* - TIM_UpdateSource_Regular
+* - TIM_UpdateSource_Global
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, u16 TIM_UpdateSource)
+{
+ u32 tmpcr1 = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
+
+ tmpcr1 = TIMx->CR1;
+
+ if (TIM_UpdateSource == TIM_UpdateSource_Regular)
+ {
+ /* Set the URS Bit */
+ tmpcr1 |= CR1_URS_Set;
+ }
+ else
+ {
+ /* Reset the URS Bit */
+ tmpcr1 &= CR1_URS_Reset;
+ }
+ TIMx->CR1 = (u16)tmpcr1;
+}
+
+/*******************************************************************************
+* Function Name : TIM_SelectHallSensor
+* Description : Enables or disables the TIMxs Hall sensor interface.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - Newstate: new state of the TIMx Hall sensor interface.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState Newstate)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(Newstate));
+
+ if (Newstate != DISABLE)
+ {
+ /* Set the TI1S Bit */
+ TIMx->CR2 |= CR2_TI1S_Set;
+ }
+ else
+ {
+ /* Reset the TI1S Bit */
+ TIMx->CR2 &= CR2_TI1S_Reset;
+ }
+}
+
+/*******************************************************************************
+* Function Name : TIM_SelectOnePulseMode
+* Description : Selects the TIMxs One Pulse Mode.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_OPMode: specifies the OPM Mode to be used.
+* This parameter can be one of the following values:
+* - TIM_OPMode_Single
+* - TIM_OPMode_Repetitive
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, u16 TIM_OPMode)
+{
+ u32 tmpcr1 = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM_OPM_MODE(TIM_OPMode));
+
+ tmpcr1 = TIMx->CR1;
+
+ /* Reset the OPM Bit */
+ tmpcr1 &= CR1_OPM_Mask;
+
+ /* Configure the OPM Mode */
+ tmpcr1 |= TIM_OPMode;
+
+ TIMx->CR1 = (u16)tmpcr1;
+}
+
+/*******************************************************************************
+* Function Name : TIM_SelectOutputTrigger
+* Description : Selects the TIMx Trigger Output Mode.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_TRGOSource: specifies the Trigger Output source.
+* This paramter can be one of the following values:
+* - TIM_TRGOSource_Reset
+* - TIM_TRGOSource_Enable
+* - TIM_TRGOSource_Update
+* - TIM_TRGOSource_OC1
+* - TIM_TRGOSource_OC1Ref
+* - TIM_TRGOSource_OC2Ref
+* - TIM_TRGOSource_OC3Ref
+* - TIM_TRGOSource_OC4Ref
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, u16 TIM_TRGOSource)
+{
+ u32 tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
+
+ tmpcr2 = TIMx->CR2;
+ /* Reset the MMS Bits */
+ tmpcr2 &= CR2_MMS_Mask;
+
+ /* Select the TRGO source */
+ tmpcr2 |= TIM_TRGOSource;
+
+ TIMx->CR2 = (u16)tmpcr2;
+}
+
+/*******************************************************************************
+* Function Name : TIM_SelectSlaveMode
+* Description : Selects the TIMx Slave Mode.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_SlaveMode: specifies the Timer Slave Mode.
+* This paramter can be one of the following values:
+* - TIM_SlaveMode_Reset
+* - TIM_SlaveMode_Gated
+* - TIM_SlaveMode_Trigger
+* - TIM_SlaveMode_External1
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, u16 TIM_SlaveMode)
+{
+ u32 tmpsmcr = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
+
+ tmpsmcr = TIMx->SMCR;
+
+ /* Reset the SMS Bits */
+ tmpsmcr &= SMCR_SMS_Mask;
+
+ /* Select the Slave Mode */
+ tmpsmcr |= TIM_SlaveMode;
+
+ TIMx->SMCR = (u16)tmpsmcr;
+}
+
+/*******************************************************************************
+* Function Name : TIM_SelectMasterSlaveMode
+* Description : Sets or Resets the TIMx Master/Slave Mode.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
+* This paramter can be one of the following values:
+* - TIM_MasterSlaveMode_Enable: synchronization between the
+* current timer and its slaves (through TRGO).
+* - TIM_MasterSlaveMode_Disable: No action
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, u16 TIM_MasterSlaveMode)
+{
+ u32 tmpsmcr = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
+
+ tmpsmcr = TIMx->SMCR;
+
+ /* Set or Reset the MSM Bit */
+ tmpsmcr &= SMCR_MSM_Mask;
+ tmpsmcr |= TIM_MasterSlaveMode;
+
+ TIMx->SMCR = (u16)tmpsmcr;
+}
+
+/*******************************************************************************
+* Function Name : TIM_SetAutoreload
+* Description : Sets the TIMx Autoreload Register value
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - Autoreload: specifies the Autoreload register new value.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, u16 Autoreload)
+{
+ /* Set the Autoreload Register value */
+ TIMx->ARR = Autoreload;
+}
+
+/*******************************************************************************
+* Function Name : TIM_SetCompare1
+* Description : Sets the TIMx Capture Compare1 Register value
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - Compare1: specifies the Capture Compare1 register new value.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_SetCompare1(TIM_TypeDef* TIMx, u16 Compare1)
+{
+ /* Set the Capture Compare1 Register value */
+ TIMx->CCR1 = Compare1;
+}
+
+/*******************************************************************************
+* Function Name : TIM_SetCompare2
+* Description : Sets the TIMx Capture Compare2 Register value
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - Compare2: specifies the Capture Compare2 register new value.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_SetCompare2(TIM_TypeDef* TIMx, u16 Compare2)
+{
+ /* Set the Capture Compare2 Register value */
+ TIMx->CCR2 = Compare2;
+}
+
+/*******************************************************************************
+* Function Name : TIM_SetCompare3
+* Description : Sets the TIMx Capture Compare3 Register value
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - Compare3: specifies the Capture Compare3 register new value.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_SetCompare3(TIM_TypeDef* TIMx, u16 Compare3)
+{
+ /* Set the Capture Compare3 Register value */
+ TIMx->CCR3 = Compare3;
+}
+
+/*******************************************************************************
+* Function Name : TIM_SetCompare4
+* Description : Sets the TIMx Capture Compare4 Register value
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - Compare4: specifies the Capture Compare4 register new value.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_SetCompare4(TIM_TypeDef* TIMx, u16 Compare4)
+{
+ /* Set the Capture Compare4 Register value */
+ TIMx->CCR4 = Compare4;
+}
+
+/*******************************************************************************
+* Function Name : TIM_SetIC1Prescaler
+* Description : Sets the TIMx Input Capture 1 prescaler.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_IC1Prescaler: specifies the Input Capture1 prescaler
+* new value.
+* This parameter can be one of the following values:
+* - TIM_ICPSC_DIV1: no prescaler
+* - TIM_ICPSC_DIV2: capture is done once every 2 events
+* - TIM_ICPSC_DIV4: capture is done once every 4 events
+* - TIM_ICPSC_DIV8: capture is done once every 8 events
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC1Prescaler)
+{
+ u32 tmpccmr1 = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM_IC_PRESCALER(TIM_IC1Prescaler));
+
+ tmpccmr1 = TIMx->CCMR1;
+
+ /* Reset the IC1PSC Bits */
+ tmpccmr1 &= CCMR_IC13PSC_Mask;
+
+ /* Set the IC1PSC value */
+ tmpccmr1 |= TIM_IC1Prescaler;
+
+ TIMx->CCMR1 = (u16)tmpccmr1;
+}
+
+/*******************************************************************************
+* Function Name : TIM_SetIC2Prescaler
+* Description : Sets the TIMx Input Capture 2 prescaler.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_IC2Prescaler: specifies the Input Capture2 prescaler
+* new value.
+* This parameter can be one of the following values:
+* - TIM_ICPSC_DIV1: no prescaler
+* - TIM_ICPSC_DIV2: capture is done once every 2 events
+* - TIM_ICPSC_DIV4: capture is done once every 4 events
+* - TIM_ICPSC_DIV8: capture is done once every 8 events
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC2Prescaler)
+{
+ u32 tmpccmr1 = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM_IC_PRESCALER(TIM_IC2Prescaler));
+
+ tmpccmr1 = TIMx->CCMR1;
+
+ /* Reset the IC2PSC Bits */
+ tmpccmr1 &= CCMR_IC24PSC_Mask;
+
+ /* Set the IC2PSC value */
+ tmpccmr1 |= (u16)((u16)TIM_IC2Prescaler << 8);
+
+ TIMx->CCMR1 = (u16)tmpccmr1;
+}
+
+/*******************************************************************************
+* Function Name : TIM_SetIC3Prescaler
+* Description : Sets the TIMx Input Capture 3 prescaler.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_IC3Prescaler: specifies the Input Capture3 prescaler
+* new value.
+* This parameter can be one of the following values:
+* - TIM_ICPSC_DIV1: no prescaler
+* - TIM_ICPSC_DIV2: capture is done once every 2 events
+* - TIM_ICPSC_DIV4: capture is done once every 4 events
+* - TIM_ICPSC_DIV8: capture is done once every 8 events
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC3Prescaler)
+{
+ u32 tmpccmr2 = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM_IC_PRESCALER(TIM_IC3Prescaler));
+
+ tmpccmr2 = TIMx->CCMR2;
+
+ /* Reset the IC3PSC Bits */
+ tmpccmr2 &= CCMR_IC13PSC_Mask;
+
+ /* Set the IC3PSC value */
+ tmpccmr2 |= TIM_IC3Prescaler;
+
+ TIMx->CCMR2 = (u16)tmpccmr2;
+}
+
+/*******************************************************************************
+* Function Name : TIM_SetIC4Prescaler
+* Description : Sets the TIMx Input Capture 4 prescaler.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_IC4Prescaler: specifies the Input Capture4 prescaler
+* new value.
+* This parameter can be one of the following values:
+* - TIM_ICPSC_DIV1: no prescaler
+* - TIM_ICPSC_DIV2: capture is done once every 2 events
+* - TIM_ICPSC_DIV4: capture is done once every 4 events
+* - TIM_ICPSC_DIV8: capture is done once every 8 events
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC4Prescaler)
+{
+ u32 tmpccmr2 = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM_IC_PRESCALER(TIM_IC4Prescaler));
+
+ tmpccmr2 = TIMx->CCMR2;
+
+ /* Reset the IC4PSC Bits */
+ tmpccmr2 &= CCMR_IC24PSC_Mask;
+
+ /* Set the IC4PSC value */
+ tmpccmr2 |= (u16)((u16)TIM_IC4Prescaler << 8);
+
+ TIMx->CCMR2 = (u16)tmpccmr2;
+}
+
+/*******************************************************************************
+* Function Name : TIM_SetClockDivision
+* Description : Sets the TIMx Clock Division value.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_CKD: specifies the clock division value.
+* This parameter can be one of the following value:
+* - TIM_CKD_DIV1: TDTS = Tck_tim
+* - TIM_CKD_DIV2: TDTS = 2*Tck_tim
+* - TIM_CKD_DIV4: TDTS = 4*Tck_tim
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, u16 TIM_CKD)
+{
+ u32 tmpcr1 = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM_CKD_DIV(TIM_CKD));
+
+ tmpcr1 = TIMx->CR1;
+
+ /* Reset the CKD Bits */
+ tmpcr1 &= CR1_CKD_Mask;
+
+ /* Set the CKD value */
+ tmpcr1 |= TIM_CKD;
+
+ TIMx->CR1 = (u16)tmpcr1;
+}
+
+/*******************************************************************************
+* Function Name : TIM_GetCapture1
+* Description : Gets the TIMx Input Capture 1 value.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* Output : None
+* Return : Capture Compare 1 Register value.
+*******************************************************************************/
+u16 TIM_GetCapture1(TIM_TypeDef* TIMx)
+{
+ /* Get the Capture 1 Register value */
+ return TIMx->CCR1;
+}
+
+/*******************************************************************************
+* Function Name : TIM_GetCapture2
+* Description : Gets the TIMx Input Capture 2 value.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* Output : None
+* Return : Capture Compare 2 Register value.
+*******************************************************************************/
+u16 TIM_GetCapture2(TIM_TypeDef* TIMx)
+{
+ /* Get the Capture 2 Register value */
+ return TIMx->CCR2;
+}
+
+/*******************************************************************************
+* Function Name : TIM_GetCapture3
+* Description : Gets the TIMx Input Capture 3 value.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* Output : None
+* Return : Capture Compare 3 Register value.
+*******************************************************************************/
+u16 TIM_GetCapture3(TIM_TypeDef* TIMx)
+{
+ /* Get the Capture 3 Register value */
+ return TIMx->CCR3;
+}
+
+/*******************************************************************************
+* Function Name : TIM_GetCapture4
+* Description : Gets the TIMx Input Capture 4 value.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* Output : None
+* Return : Capture Compare 4 Register value.
+*******************************************************************************/
+u16 TIM_GetCapture4(TIM_TypeDef* TIMx)
+{
+ /* Get the Capture 4 Register value */
+ return TIMx->CCR4;
+}
+
+/*******************************************************************************
+* Function Name : TIM_GetCounter
+* Description : Gets the TIMx Counter value.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* Output : None
+* Return : Counter Register value.
+*******************************************************************************/
+u16 TIM_GetCounter(TIM_TypeDef* TIMx)
+{
+ /* Get the Counter Register value */
+ return TIMx->CNT;
+}
+
+/*******************************************************************************
+* Function Name : TIM_GetPrescaler
+* Description : Gets the TIMx Prescaler value.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* Output : None
+* Return : Prescaler Register value.
+*******************************************************************************/
+u16 TIM_GetPrescaler(TIM_TypeDef* TIMx)
+{
+ /* Get the Prescaler Register value */
+ return TIMx->PSC;
+}
+
+/*******************************************************************************
+* Function Name : TIM_GetFlagStatus
+* Description : Checks whether the specified TIMx flag is set or not.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_FLAG: specifies the flag to check.
+* This parameter can be one of the following values:
+* - TIM_FLAG_Update: Timer update Flag
+* - TIM_FLAG_CC1: Timer Capture Compare 1 Flag
+* - TIM_FLAG_CC2: Timer Capture Compare 2 Flag
+* - TIM_FLAG_CC3: Timer Capture Compare 3 Flag
+* - TIM_FLAG_CC4: Timer Capture Compare 4 Flag
+* - TIM_FLAG_Trigger: Timer Trigger Flag
+* - TIM_FLAG_CC1OF: Timer Capture Compare 1 overcapture Flag
+* - TIM_FLAG_CC2OF: Timer Capture Compare 2 overcapture Flag
+* - TIM_FLAG_CC3OF: Timer Capture Compare 3 overcapture Flag
+* - TIM_FLAG_CC4OF: Timer Capture Compare 4 overcapture Flag
+* Output : None
+* Return : The new state of TIM_FLAG (SET or RESET).
+*******************************************************************************/
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, u16 TIM_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert(IS_TIM_GET_FLAG(TIM_FLAG));
+
+ if ((TIMx->SR & TIM_FLAG) != (u16)RESET )
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name : TIM_ClearFlag
+* Description : Clears the TIMx's pending flags.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_FLAG: specifies the flag bit to clear.
+* This parameter can be any combination of the following values:
+* - TIM_FLAG_Update: Timer update Flag
+* - TIM_FLAG_CC1: Timer Capture Compare 1 Flag
+* - TIM_FLAG_CC2: Timer Capture Compare 2 Flag
+* - TIM_FLAG_CC3: Timer Capture Compare 3 Flag
+* - TIM_FLAG_CC4: Timer Capture Compare 4 Flag
+* - TIM_FLAG_Trigger: Timer Trigger Flag
+* - TIM_FLAG_CC1OF: Timer Capture Compare 1 overcapture Flag
+* - TIM_FLAG_CC2OF: Timer Capture Compare 2 overcapture Flag
+* - TIM_FLAG_CC3OF: Timer Capture Compare 3 overcapture Flag
+* - TIM_FLAG_CC4OF: Timer Capture Compare 4 overcapture Flag
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_ClearFlag(TIM_TypeDef* TIMx, u16 TIM_FLAG)
+{
+ /* Check the parameters */
+ assert(IS_TIM_CLEAR_FLAG(TIM_FLAG));
+
+ /* Clear the flags */
+ TIMx->SR &= (u16)~TIM_FLAG;
+}
+
+/*******************************************************************************
+* Function Name : TIM_GetITStatus
+* Description : Checks whether the TIMx interrupt has occurred or not.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_IT: specifies the TIM interrupt source to check.
+* This parameter can be one of the following values:
+* - TIM_IT_Update: Timer update Interrupt source
+* - TIM_IT_CC1: Timer Capture Compare 1 Interrupt source
+* - TIM_IT_CC2: Timer Capture Compare 2 Interrupt source
+* - TIM_IT_CC3: Timer Capture Compare 3 Interrupt source
+* - TIM_IT_CC4: Timer Capture Compare 4 Interrupt source
+* - TIM_IT_Trigger: Timer Trigger Interrupt source
+* Output : None
+* Return : The new state of the TIM_IT(SET or RESET).
+*******************************************************************************/
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, u16 TIM_IT)
+{
+ ITStatus bitstatus = RESET;
+
+ u16 itstatus = 0x0, itenable = 0x0;
+
+ /* Check the parameters */
+ assert(IS_TIM_GET_IT(TIM_IT));
+
+ itstatus = TIMx->SR & TIM_IT;
+
+ itenable = TIMx->DIER & TIM_IT;
+
+ if ((itstatus != (u16)RESET) && (itenable != (u16)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name : TIM_ClearITPendingBit
+* Description : Clears the TIMx's interrupt pending bits.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_IT: specifies the pending bit to clear.
+* This parameter can be any combination of the following values:
+* - TIM_IT_Update: Timer update Interrupt source
+* - TIM_IT_CC1: Timer Capture Compare 1 Interrupt source
+* - TIM_IT_CC2: Timer Capture Compare 2 Interrupt source
+* - TIM_IT_CC3: Timer Capture Compare 3 Interrupt source
+* - TIM_IT_CC4: Timer Capture Compare 4 Interrupt source
+* - TIM_IT_Trigger: Timer Trigger Interrupt source
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, u16 TIM_IT)
+{
+ /* Check the parameters */
+ assert(IS_TIM_IT(TIM_IT));
+
+ /* Clear the IT pending Bit */
+ TIMx->SR &= (u16)~TIM_IT;
+}
+
+/*******************************************************************************
+* Function Name : PWMInput_Config
+* Description : Configures the TIM peripheral according to the specified
+* parameters in the TIM_ICInitStruct to measure an external PWM
+* signal.
+* Input : - TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
+* that contains the configuration information for the specified
+* TIM peripheral.
+* Output : None
+* Return : None
+*******************************************************************************/
+static void PWMI_Config(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
+{
+ u8 ICPolarity = TIM_ICPolarity_Rising;
+ u8 ICSelection = TIM_ICSelection_DirectTI;
+
+ /* Select the Opposite Input Polarity */
+ if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
+ {
+ ICPolarity = TIM_ICPolarity_Falling;
+ }
+ else
+ {
+ ICPolarity = TIM_ICPolarity_Rising;
+ }
+
+ /* Select the Opposite Input */
+ if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
+ {
+ ICSelection = TIM_ICSelection_IndirectTI;
+ }
+ else
+ {
+ ICSelection = TIM_ICSelection_DirectTI;
+ }
+
+ if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
+ {
+ /* TI1 Configuration */
+ TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
+ TIM_ICInitStruct->TIM_ICFilter);
+
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+
+ /* TI2 Configuration */
+ TI2_Config(TIMx, ICPolarity, ICSelection, TIM_ICInitStruct->TIM_ICFilter);
+
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ }
+ else
+ {
+ /* TI1 Configuration */
+ TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
+ TIM_ICInitStruct->TIM_ICFilter);
+
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+
+ /* TI2 Configuration */
+ TI1_Config(TIMx, ICPolarity, ICSelection, TIM_ICInitStruct->TIM_ICFilter);
+
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ }
+}
+
+/*******************************************************************************
+* Function Name : TI1_Config
+* Description : Configure the TI1 as Input.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_ICPolarity : The Input Polarity.
+* This parameter can be one of the following values:
+* - TIM_ICPolarity_Rising
+* - TIM_ICPolarity_Falling
+* - TIM_ICSelection: specifies the input to be used.
+* This parameter can be one of the following values:
+* - TIM_ICSelection_DirectTI: TIM Input 1 is selected to
+* be connected to IC1.
+* - TIM_ICSelection_IndirectTI: TIM Input 1 is selected to
+* be connected to IC2.
+* - TIM_ICSelection_TRGI: TIM Input 1 is selected to be
+* connected to TRGI.
+* - TIM_ICFilter: Specifies the Input Capture Filter.
+* This parameter must be a value between 0x00 and 0x0F.
+* Output : None
+* Return : None
+*******************************************************************************/
+static void TI1_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection,
+ u8 TIM_ICFilter)
+{
+ u32 tmpccmr1 = 0, tmpccer = 0;
+
+ tmpccmr1 = TIMx->CCMR1;
+ tmpccer = TIMx->CCER;
+
+ /* Disable the Channel 1: Reset the CCE Bit */
+ TIMx->CCER &= CCRE_CC1E_Reset;
+
+ /* Select the Input and set the filter */
+ tmpccmr1 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask;
+ tmpccmr1 |= TIM_ICSelection | (u16)((u16)TIM_ICFilter << 4);
+
+ /* Select the Polarity and set the CCE Bit */
+ tmpccer &= CCER_CC1P_Mask & CCRE_CC1E_Mask;
+ tmpccer |= TIM_ICPolarity | CCRE_CC1E_Set;
+
+ TIMx->CCMR1 = 0x0000;
+ TIMx->CCMR1 = (u16)tmpccmr1;
+ TIMx->CCER = (u16)tmpccer;
+}
+
+/*******************************************************************************
+* Function Name : TI2_Config
+* Description : Configure the TI2 as Input.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_ICPolarity : The Input Polarity.
+* This parameter can be one of the following values:
+* - TIM_ICPolarity_Rising
+* - TIM_ICPolarity_Falling
+* - TIM_ICSelection: specifies the input to be used.
+* This parameter can be one of the following values:
+* - TIM_ICSelection_DirectTI: TIM Input 2 is selected to
+* be connected to IC2.
+* - TIM_ICSelection_IndirectTI: TIM Input 2 is selected to
+* be connected to IC1.
+* - TIM_ICSelection_TRGI: TIM Input 2 is selected to be
+* connected to TRGI.
+* - TIM_ICFilter: Specifies the Input Capture Filter.
+* This parameter must be a value between 0x00 and 0x0F.
+* Output : None
+* Return : None
+*******************************************************************************/
+static void TI2_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection,
+ u8 TIM_ICFilter)
+{
+ u32 tmpccmr1 = 0, tmpccer = 0, tmp = 0;
+
+ tmpccmr1 = TIMx->CCMR1;
+ tmpccer = TIMx->CCER;
+ tmp = (u16)((u16)TIM_ICPolarity << 4);
+
+ /* Disable the Channel 2: Reset the CCE Bit */
+ TIMx->CCER &= CCRE_CC2E_Reset;
+
+ /* Select the Input and set the filter */
+ tmpccmr1 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask;
+ tmpccmr1 |= (u16)((u16)TIM_ICFilter << 12);
+ tmpccmr1 |= (u16)((u16)TIM_ICSelection << 8);
+
+ /* Select the Polarity and set the CCE Bit */
+ tmpccer &= CCER_CC2P_Mask & CCRE_CC2E_Mask;
+ tmpccer |= tmp | CCRE_CC2E_Set;
+
+ TIMx->CCMR1 = (u16)tmpccmr1 ;
+ TIMx->CCER = (u16)tmpccer;
+}
+
+/*******************************************************************************
+* Function Name : TI3_Config
+* Description : Configure the TI3 as Input.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_ICPolarity : The Input Polarity.
+* This parameter can be one of the following values:
+* - TIM_ICPolarity_Rising
+* - TIM_ICPolarity_Falling
+* - TIM_ICSelection: specifies the input to be used.
+* This parameter can be one of the following values:
+* - TIM_ICSelection_DirectTI: TIM Input 3 is selected to
+* be connected to IC3.
+* - TIM_ICSelection_IndirectTI: TIM Input 3 is selected to
+* be connected to IC4.
+* - TIM_ICSelection_TRGI: TIM Input 3 is selected to be
+* connected to TRGI.
+* - TIM_ICFilter: Specifies the Input Capture Filter.
+* This parameter must be a value between 0x00 and 0x0F.
+* Output : None
+* Return : None
+*******************************************************************************/
+static void TI3_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection,
+ u8 TIM_ICFilter)
+{
+ u32 tmpccmr2 = 0, tmpccer = 0, tmp = 0;
+
+ tmpccmr2 = TIMx->CCMR2;
+ tmpccer = TIMx->CCER;
+ tmp = (u16)((u16)TIM_ICPolarity << 8);
+
+ /* Disable the Channel 3: Reset the CCE Bit */
+ TIMx->CCER &= CCRE_CC3E_Reset;
+
+ /* Select the Input and set the filter */
+ tmpccmr2 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask;
+ tmpccmr2 |= TIM_ICSelection | (u16)((u16)TIM_ICFilter << 4);
+
+ /* Select the Polarity and set the CCE Bit */
+ tmpccer &= CCER_CC1P_Mask & CCRE_CC1E_Mask;
+ tmpccer |= tmp | CCRE_CC3E_Set;
+
+ TIMx->CCMR2 = (u16)tmpccmr2;
+ TIMx->CCER = (u16)tmpccer;
+}
+
+/*******************************************************************************
+* Function Name : TI4_Config
+* Description : Configure the TI1 as Input.
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_ICPolarity : The Input Polarity.
+* This parameter can be one of the following values:
+* - TIM_ICPolarity_Rising
+* - TIM_ICPolarity_Falling
+* - TIM_ICSelection: specifies the input to be used.
+* This parameter can be one of the following values:
+* - TIM_ICSelection_DirectTI: TIM Input 4 is selected to
+* be connected to IC4.
+* - TIM_ICSelection_IndirectTI: TIM Input 4 is selected to
+* be connected to IC3.
+* - TIM_ICSelection_TRGI: TIM Input 4 is selected to be
+* connected to TRGI.
+* - TIM_ICFilter: Specifies the Input Capture Filter.
+* This parameter must be a value between 0x00 and 0x0F.
+* Output : None
+* Return : None
+*******************************************************************************/
+static void TI4_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection,
+ u8 TIM_ICFilter)
+{
+ u32 tmpccmr2 = 0, tmpccer = 0, tmp = 0;
+
+ tmpccmr2 = TIMx->CCMR2;
+ tmpccer = TIMx->CCER;
+ tmp = (u16)((u16)TIM_ICPolarity << 12);
+
+ /* Disable the Channel 4: Reset the CCE Bit */
+ TIMx->CCER &= CCRE_CC4E_Reset;
+
+ /* Select the Input and set the filter */
+ tmpccmr2 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask;
+ tmpccmr2 |= (u16)((u16)TIM_ICSelection << 8) | (u16)((u16)TIM_ICFilter << 12);
+
+ /* Select the Polarity and set the CCE Bit */
+ tmpccer &= CCER_CC4P_Mask & CCRE_CC4E_Mask;
+ tmpccer |= tmp | CCRE_CC4E_Set;
+
+ TIMx->CCMR2 = (u16)tmpccmr2;
+ TIMx->CCER = (u16)tmpccer ;
+}
+
+/*******************************************************************************
+* Function Name : ETR_Config
+* Description : Configure the External Trigger
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* - TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+* This parameter can be one of the following values:
+* - TIM_ExtTRGPSC_OFF
+* - TIM_ExtTRGPSC_DIV2
+* - TIM_ExtTRGPSC_DIV4
+* - TIM_ExtTRGPSC_DIV8
+* - TIM_ExtTRGPolarity: The external Trigger Polarity.
+* This parameter can be one of the following values:
+* - TIM_ExtTRGPolarity_Inverted
+* - TIM_ExtTRGPolarity_NonInverted
+* - ExtTRGFilter: External Trigger Filter.
+* This parameter must be a value between 0x00 and 0x0F.
+* Output : None
+* Return : None
+*******************************************************************************/
+static void ETR_Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity,
+ u8 ExtTRGFilter)
+{
+ u32 tmpsmcr = 0;
+
+ tmpsmcr = TIMx->SMCR;
+
+ /* Set the Prescaler, the Filter value and the Polarity */
+ tmpsmcr &= SMCR_ETR_Mask;
+ tmpsmcr |= TIM_ExtTRGPrescaler | TIM_ExtTRGPolarity | (u16)((u16)ExtTRGFilter << 8);
+
+ TIMx->SMCR = (u16)tmpsmcr;
+}
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_tim1.c b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_tim1.c
new file mode 100644
index 0000000..deac420
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_tim1.c
@@ -0,0 +1,2664 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_tim1.c
+* Author : MCD Application Team
+* Date First Issued : 09/29/2006
+* Description : This file provides all the TIM1 software functions.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* mm/dd/yyyy: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_tim1.h"
+#include "stm32f10x_rcc.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* ------------ TIM1 registers bit address in the alias region ----------- */
+#define TIM1_OFFSET (TIM1_BASE - PERIPH_BASE)
+
+/* --- TIM1 CR1 Register ---*/
+/* Alias word address of CEN bit */
+#define CR1_OFFSET (TIM1_OFFSET + 0x00)
+#define CEN_BitNumber 0x00
+#define CR1_CEN_BB (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (CEN_BitNumber * 4))
+
+/* Alias word address of UDIS bit */
+#define UDIS_BitNumber 0x01
+#define CR1_UDIS_BB (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (UDIS_BitNumber * 4))
+
+/* Alias word address of URS bit */
+#define URS_BitNumber 0x02
+#define CR1_URS_BB (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (URS_BitNumber * 4))
+
+/* Alias word address of OPM bit */
+#define OPM_BitNumber 0x03
+#define CR1_OPM_BB (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (OPM_BitNumber * 4))
+
+/* Alias word address of ARPE bit */
+#define ARPE_BitNumber 0x07
+#define CR1_ARPE_BB (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (ARPE_BitNumber * 4))
+
+/* --- TIM1 CR2 Register --- */
+/* Alias word address of CCPC bit */
+#define CR2_OFFSET (TIM1_OFFSET + 0x04)
+#define CCPC_BitNumber 0x00
+#define CR2_CCPC_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (CCPC_BitNumber * 4))
+
+/* Alias word address of CCUS bit */
+#define CCUS_BitNumber 0x02
+#define CR2_CCUS_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (CCUS_BitNumber * 4))
+
+/* Alias word address of CCDS bit */
+#define CCDS_BitNumber 0x03
+#define CR2_CCDS_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (CCDS_BitNumber * 4))
+
+/* Alias word address of TI1S bit */
+#define TI1S_BitNumber 0x07
+#define CR2_TI1S_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (TI1S_BitNumber * 4))
+
+/* Alias word address of OIS1 bit */
+#define OIS1_BitNumber 0x08
+#define CR2_OIS1_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS1_BitNumber * 4))
+
+/* Alias word address of OIS1N bit */
+#define OIS1N_BitNumber 0x09
+#define CR2_OIS1N_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS1N_BitNumber * 4))
+
+/* Alias word address of OIS2 bit */
+#define OIS2_BitNumber 0x0A
+#define CR2_OIS2_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS2_BitNumber * 4))
+
+/* Alias word address of OIS2N bit */
+#define OIS2N_BitNumber 0x0B
+#define CR2_OIS2N_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS2N_BitNumber * 4))
+
+/* Alias word address of OIS3 bit */
+#define OIS3_BitNumber 0x0C
+#define CR2_OIS3_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS3_BitNumber * 4))
+
+/* Alias word address of OIS3N bit */
+#define OIS3N_BitNumber 0x0D
+#define CR2_OIS3N_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS3N_BitNumber * 4))
+
+/* Alias word address of OIS4 bit */
+#define OIS4_BitNumber 0x0E
+#define CR2_OIS4_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS4_BitNumber * 4))
+
+/* --- TIM1 SMCR Register --- */
+/* Alias word address of MSM bit */
+#define SMCR_OFFSET (TIM1_OFFSET + 0x08)
+#define MSM_BitNumber 0x07
+#define SMCR_MSM_BB (PERIPH_BB_BASE + (SMCR_OFFSET * 32) + (MSM_BitNumber * 4))
+
+/* Alias word address of ECE bit */
+#define ECE_BitNumber 0x0E
+#define SMCR_ECE_BB (PERIPH_BB_BASE + (SMCR_OFFSET * 32) + (ECE_BitNumber * 4))
+
+/* --- TIM1 EGR Register --- */
+/* Alias word address of UG bit */
+#define EGR_OFFSET (TIM1_OFFSET + 0x14)
+#define UG_BitNumber 0x00
+#define EGR_UG_BB (PERIPH_BB_BASE + (EGR_OFFSET * 32) + (UG_BitNumber * 4))
+
+/* --- TIM1 CCER Register --- */
+/* Alias word address of CC1E bit */
+#define CCER_OFFSET (TIM1_OFFSET + 0x20)
+#define CC1E_BitNumber 0x00
+#define CCER_CC1E_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC1E_BitNumber * 4))
+
+/* Alias word address of CC1P bit */
+#define CC1P_BitNumber 0x01
+#define CCER_CC1P_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC1P_BitNumber * 4))
+
+/* Alias word address of CC1NE bit */
+#define CC1NE_BitNumber 0x02
+#define CCER_CC1NE_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC1NE_BitNumber * 4))
+
+/* Alias word address of CC1NP bit */
+#define CC1NP_BitNumber 0x03
+#define CCER_CC1NP_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC1NP_BitNumber * 4))
+
+/* Alias word address of CC2E bit */
+#define CC2E_BitNumber 0x04
+#define CCER_CC2E_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC2E_BitNumber * 4))
+
+/* Alias word address of CC2P bit */
+#define CC2P_BitNumber 0x05
+#define CCER_CC2P_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC2P_BitNumber * 4))
+
+/* Alias word address of CC2NE bit */
+#define CC2NE_BitNumber 0x06
+#define CCER_CC2NE_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC2NE_BitNumber * 4))
+
+/* Alias word address of CC2NP bit */
+#define CC2NP_BitNumber 0x07
+#define CCER_CC2NP_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC2NP_BitNumber * 4))
+
+/* Alias word address of CC3E bit */
+#define CC3E_BitNumber 0x08
+#define CCER_CC3E_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC3E_BitNumber * 4))
+
+/* Alias word address of CC3P bit */
+#define CC3P_BitNumber 0x09
+#define CCER_CC3P_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC3P_BitNumber * 4))
+
+/* Alias word address of CC3NE bit */
+#define CC3NE_BitNumber 0x0A
+#define CCER_CC3NE_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC3NE_BitNumber * 4))
+
+/* Alias word address of CC3NP bit */
+#define CC3NP_BitNumber 0x0B
+#define CCER_CC3NP_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC3NP_BitNumber * 4))
+
+/* Alias word address of CC4E bit */
+#define CC4E_BitNumber 0x0C
+#define CCER_CC4E_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC4E_BitNumber * 4))
+
+/* Alias word address of CC4P bit */
+#define CC4P_BitNumber 0x0D
+#define CCER_CC4P_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC4P_BitNumber * 4))
+
+/* --- TIM1 BDTR Register --- */
+/* Alias word address of MOE bit */
+#define BDTR_OFFSET (TIM1_OFFSET + 0x44)
+#define MOE_BitNumber 0x0F
+#define BDTR_MOE_BB (PERIPH_BB_BASE + (BDTR_OFFSET * 32) + (MOE_BitNumber * 4))
+
+/* --- TIM1 CCMR1 Register --- */
+/* Alias word address of OC1FE bit */
+#define CCMR1_OFFSET (TIM1_OFFSET + 0x18)
+#define OC1FE_BitNumber 0x02
+#define CCMR1_OC1FE_BB (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC1FE_BitNumber * 4))
+
+/* Alias word address of OC1PE bit */
+#define OC1PE_BitNumber 0x03
+#define CCMR1_OC1PE_BB (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC1PE_BitNumber * 4))
+
+/* Alias word address of OC2FE bit */
+#define OC2FE_BitNumber 0x0A
+#define CCMR1_OC2FE_BB (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC2FE_BitNumber * 4))
+
+/* Alias word address of OC2PE bit */
+#define OC2PE_BitNumber 0x0B
+#define CCMR1_OC2PE_BB (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC2PE_BitNumber * 4))
+
+/* --- TIM1 CCMR2 Register ---- */
+/* Alias word address of OC3FE bit */
+#define CCMR2_OFFSET (TIM1_OFFSET + 0x1C)
+#define OC3FE_BitNumber 0x02
+#define CCMR2_OC3FE_BB (PERIPH_BB_BASE + (CCMR2_OFFSET * 32) + (OC3FE_BitNumber * 4))
+
+/* Alias word address of OC3PE bit */
+#define OC3PE_BitNumber 0x03
+#define CCMR2_OC3PE_BB (PERIPH_BB_BASE + (CCMR2_OFFSET * 32) + (OC3PE_BitNumber * 4))
+
+/* Alias word address of OC4FE bit */
+#define OC4FE_BitNumber 0x0A
+#define CCMR2_OC4FE_BB (PERIPH_BB_BASE + (CCMR2_OFFSET * 32) + (OC4FE_BitNumber * 4))
+
+/* Alias word address of OC4PE bit */
+#define OC4PE_BitNumber 0x0B
+#define CCMR2_OC4PE_BB (PERIPH_BB_BASE + (CCMR2_OFFSET * 32) + (OC4PE_BitNumber * 4))
+
+/* --------------------- TIM1 registers bit mask ------------------------- */
+/* TIM1 CR1 Mask */
+#define CR1_CounterMode_Mask ((u16)0x039F)
+#define CR1_CKD_Mask ((u16)0x00FF)
+
+/* TIM1 CR2 Mask */
+#define CR2_MMS_Mask ((u16)0x0080)
+
+/* TIM1 SMCR Mask */
+#define SMCR_SMS_Mask ((u16)0xFFF0)
+#define SMCR_ETR_Mask ((u16)0x40F7)
+#define SMCR_TS_Mask ((u16)0xFF87)
+#define SMCR_ECE_Set ((u16)0x0001)
+
+/* TIM1 CCMRx Mask */
+#define CCMR_CC13S_Mask ((u16)0xFFFC)
+#define CCMR_CC24S_Mask ((u16)0xFCFF)
+#define CCMR_TI13Direct_Set ((u16)0x0001)
+#define CCMR_TI24Direct_Set ((u16)0x0100)
+#define CCMR_OCM13_Mask ((u16)0x7F0F)
+#define CCMR_OCM24_Mask ((u16)0x0F7F)
+#define CCMR_IC13PSC_Mask ((u16)0xFFF3)
+#define CCMR_IC24PSC_Mask ((u16)0xF3FF)
+#define CCMR_IC13F_Mask ((u16)0xFF0F)
+#define CCMR_IC24F_Mask ((u16)0x0FFF)
+#define OC13Mode_Mask ((u16)0xFF00)
+#define OC24Mode_Mask ((u16)0x00FF)
+
+/* TIM1 CCER Set/Reset Bit */
+#define CCER_CCE_Set ((u16)0x0001)
+#define CCER_CCE_Reset ((u16)0x0000)
+
+/* TIM1 DMA Mask */
+#define DCR_DMA_Mask ((u16)0x0000)
+
+/* TIM1 private Masks */
+#define TIM1_Period_Reset_Mask ((u16)0xFFFF)
+#define TIM1_Prescaler_Reset_Mask ((u16)0x0000)
+#define TIM1_RepetitionCounter_Reset_Mask ((u16)0x0000)
+#define TIM1_Pulse_Reset_Mask ((u16)0x0000)
+#define TIM1_ICFilter_Mask ((u8)0x00)
+#define TIM1_DeadTime_Reset_Mask ((u16)0x0000)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void ETR_Config(u16 TIM1_ExtTRGPrescaler, u16 TIM1_ExtTRGPolarity,
+ u16 ExtTRGFilter);
+static void TI1_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection,
+ u8 TIM1_ICFilter);
+static void TI2_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection,
+ u8 TIM1_ICFilter);
+static void TI3_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection,
+ u8 TIM1_ICFilter);
+static void TI4_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection,
+ u8 TIM1_ICFilter);
+
+/*******************************************************************************
+* Function Name : TIM1_DeInit
+* Description : Deinitializes the TIM1 peripheral registers to their default
+* reset values.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_DeInit(void)
+{
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
+}
+
+/*******************************************************************************
+* Function Name : TIM1_TimeBaseInit
+* Description : Initializes the TIM1 Time Base Unit according to the specified
+* parameters in the TIM1_TimeBaseInitStruct.
+* Input : - TIM1_TimeBaseInitStruct: pointer to a TIM1_TimeBaseInitTypeDef
+* structure that contains the configuration information for
+* the specified TIM1 peripheral.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_TimeBaseInit(TIM1_TimeBaseInitTypeDef* TIM1_TimeBaseInitStruct)
+{
+ /* Check the parameters */
+ assert(IS_TIM1_COUNTER_MODE(TIM1_TimeBaseInitStruct->TIM1_CounterMode));
+ assert(IS_TIM1_CKD_DIV(TIM1_TimeBaseInitStruct->TIM1_ClockDivision));
+
+ /* Set the Autoreload value */
+ TIM1->ARR = TIM1_TimeBaseInitStruct->TIM1_Period ;
+
+ /* Set the Prescaler value */
+ TIM1->PSC = TIM1_TimeBaseInitStruct->TIM1_Prescaler;
+
+ /* Select the Counter Mode and set the clock division */
+ TIM1->CR1 &= CR1_CKD_Mask & CR1_CounterMode_Mask;
+ TIM1->CR1 |= (u32)TIM1_TimeBaseInitStruct->TIM1_ClockDivision |
+ TIM1_TimeBaseInitStruct->TIM1_CounterMode;
+
+ /* Set the Repetition Counter value */
+ TIM1->RCR = TIM1_TimeBaseInitStruct->TIM1_RepetitionCounter;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_OC1Init
+* Description : Initializes the TIM1 Channel1 according to the specified
+* parameters in the TIM1_OCInitStruct.
+* Input : - TIM1_OCInitStruct: pointer to a TIM1_OCInitTypeDef structure that
+* contains the configuration information for the TIM1 peripheral.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_OC1Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct)
+{
+ u16 tmpccmr = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM1_OC_MODE(TIM1_OCInitStruct->TIM1_OCMode));
+ assert(IS_TIM1_OUTPUT_STATE(TIM1_OCInitStruct->TIM1_OutputState));
+ assert(IS_TIM1_OUTPUTN_STATE(TIM1_OCInitStruct->TIM1_OutputNState));
+ assert(IS_TIM1_OC_POLARITY(TIM1_OCInitStruct->TIM1_OCPolarity));
+ assert(IS_TIM1_OCN_POLARITY(TIM1_OCInitStruct->TIM1_OCNPolarity));
+ assert(IS_TIM1_OCIDLE_STATE(TIM1_OCInitStruct->TIM1_OCIdleState));
+ assert(IS_TIM1_OCNIDLE_STATE(TIM1_OCInitStruct->TIM1_OCNIdleState));
+
+ tmpccmr = TIM1->CCMR1;
+
+ /* Disable the Channel 1: Reset the CCE Bit */
+ *(vu32 *) CCER_CC1E_BB = CCER_CCE_Reset;
+
+ /* Reset the Output Compare Bits */
+ tmpccmr &= OC13Mode_Mask;
+
+ /* Set the Ouput Compare Mode */
+ tmpccmr |= TIM1_OCInitStruct->TIM1_OCMode;
+
+ TIM1->CCMR1 = tmpccmr;
+
+ /* Set the Output State */
+ *(vu32 *) CCER_CC1E_BB = TIM1_OCInitStruct->TIM1_OutputState;
+
+ /* Set the Output N State */
+ *(vu32 *) CCER_CC1NE_BB = TIM1_OCInitStruct->TIM1_OutputNState;
+
+ /* Set the Output Polarity */
+ *(vu32 *) CCER_CC1P_BB = TIM1_OCInitStruct->TIM1_OCPolarity;
+
+ /* Set the Output N Polarity */
+ *(vu32 *) CCER_CC1NP_BB = TIM1_OCInitStruct->TIM1_OCNPolarity;
+
+ /* Set the Output Idle state */
+ *(vu32 *) CR2_OIS1_BB = TIM1_OCInitStruct->TIM1_OCIdleState;
+
+ /* Set the Output N Idle state */
+ *(vu32 *) CR2_OIS1N_BB = TIM1_OCInitStruct->TIM1_OCNIdleState;
+
+ /* Set the Pulse value */
+ TIM1->CCR1 = TIM1_OCInitStruct->TIM1_Pulse;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_OC2Init
+* Description : Initializes the TIM1 Channel2 according to the specified
+* parameters in the TIM1_OCInitStruct.
+* Input : - TIM1_OCInitStruct: pointer to a TIM1_OCInitTypeDef structure that
+* contains the configuration information for the TIM1 peripheral.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_OC2Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct)
+{
+ u32 tmpccmr = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM1_OC_MODE(TIM1_OCInitStruct->TIM1_OCMode));
+ assert(IS_TIM1_OUTPUT_STATE(TIM1_OCInitStruct->TIM1_OutputState));
+ assert(IS_TIM1_OUTPUTN_STATE(TIM1_OCInitStruct->TIM1_OutputNState));
+ assert(IS_TIM1_OC_POLARITY(TIM1_OCInitStruct->TIM1_OCPolarity));
+ assert(IS_TIM1_OCN_POLARITY(TIM1_OCInitStruct->TIM1_OCNPolarity));
+ assert(IS_TIM1_OCIDLE_STATE(TIM1_OCInitStruct->TIM1_OCIdleState));
+ assert(IS_TIM1_OCNIDLE_STATE(TIM1_OCInitStruct->TIM1_OCNIdleState));
+
+ tmpccmr = TIM1->CCMR1;
+
+ /* Disable the Channel 2: Reset the CCE Bit */
+ *(vu32 *) CCER_CC2E_BB = CCER_CCE_Reset;
+
+ /* Reset the Output Compare Bits */
+ tmpccmr &= OC24Mode_Mask;
+
+ /* Set the Ouput Compare Mode */
+ tmpccmr |= (u32)TIM1_OCInitStruct->TIM1_OCMode << 8;
+
+ TIM1->CCMR1 = (u16)tmpccmr;
+
+ /* Set the Output State */
+ *(vu32 *) CCER_CC2E_BB = TIM1_OCInitStruct->TIM1_OutputState;
+
+ /* Set the Output N State */
+ *(vu32 *) CCER_CC2NE_BB = TIM1_OCInitStruct->TIM1_OutputNState;
+
+ /* Set the Output Polarity */
+ *(vu32 *) CCER_CC2P_BB = TIM1_OCInitStruct->TIM1_OCPolarity;
+
+ /* Set the Output N Polarity */
+ *(vu32 *) CCER_CC2NP_BB = TIM1_OCInitStruct->TIM1_OCNPolarity;
+
+ /* Set the Output Idle state */
+ *(vu32 *) CR2_OIS2_BB = TIM1_OCInitStruct->TIM1_OCIdleState;
+
+ /* Set the Output N Idle state */
+ *(vu32 *) CR2_OIS2N_BB = TIM1_OCInitStruct->TIM1_OCNIdleState;
+
+ /* Set the Pulse value */
+ TIM1->CCR2 = TIM1_OCInitStruct->TIM1_Pulse;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_OC3Init
+* Description : Initializes the TIM1 Channel3 according to the specified
+* parameters in the TIM1_OCInitStruct.
+* Input : - TIM1_OCInitStruct: pointer to a TIM1_OCInitTypeDef structure that
+* contains the configuration information for the TIM1 peripheral.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_OC3Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct)
+{
+ u16 tmpccmr = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM1_OC_MODE(TIM1_OCInitStruct->TIM1_OCMode));
+ assert(IS_TIM1_OUTPUT_STATE(TIM1_OCInitStruct->TIM1_OutputState));
+ assert(IS_TIM1_OUTPUTN_STATE(TIM1_OCInitStruct->TIM1_OutputNState));
+ assert(IS_TIM1_OC_POLARITY(TIM1_OCInitStruct->TIM1_OCPolarity));
+ assert(IS_TIM1_OCN_POLARITY(TIM1_OCInitStruct->TIM1_OCNPolarity));
+ assert(IS_TIM1_OCIDLE_STATE(TIM1_OCInitStruct->TIM1_OCIdleState));
+ assert(IS_TIM1_OCNIDLE_STATE(TIM1_OCInitStruct->TIM1_OCNIdleState));
+
+ tmpccmr = TIM1->CCMR2;
+
+ /* Disable the Channel 3: Reset the CCE Bit */
+ *(vu32 *) CCER_CC3E_BB = CCER_CCE_Reset;
+
+ /* Reset the Output Compare Bits */
+ tmpccmr &= OC13Mode_Mask;
+
+ /* Set the Ouput Compare Mode */
+ tmpccmr |= TIM1_OCInitStruct->TIM1_OCMode;
+
+ TIM1->CCMR2 = tmpccmr;
+
+ /* Set the Output State */
+ *(vu32 *) CCER_CC3E_BB = TIM1_OCInitStruct->TIM1_OutputState;
+
+ /* Set the Output N State */
+ *(vu32 *) CCER_CC3NE_BB = TIM1_OCInitStruct->TIM1_OutputNState;
+
+ /* Set the Output Polarity */
+ *(vu32 *) CCER_CC3P_BB = TIM1_OCInitStruct->TIM1_OCPolarity;
+
+ /* Set the Output N Polarity */
+ *(vu32 *) CCER_CC3NP_BB = TIM1_OCInitStruct->TIM1_OCNPolarity;
+
+ /* Set the Output Idle state */
+ *(vu32 *) CR2_OIS3_BB = TIM1_OCInitStruct->TIM1_OCIdleState;
+
+ /* Set the Output N Idle state */
+ *(vu32 *) CR2_OIS3N_BB = TIM1_OCInitStruct->TIM1_OCNIdleState;
+
+ /* Set the Pulse value */
+ TIM1->CCR3 = TIM1_OCInitStruct->TIM1_Pulse;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_OC4Init
+* Description : Initializes the TIM1 Channel4 according to the specified
+* parameters in the TIM1_OCInitStruct.
+* Input : - TIM1_OCInitStruct: pointer to a TIM1_OCInitTypeDef structure that
+* contains the configuration information for the TIM1 peripheral.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_OC4Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct)
+{
+ u32 tmpccmr = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM1_OC_MODE(TIM1_OCInitStruct->TIM1_OCMode));
+ assert(IS_TIM1_OUTPUT_STATE(TIM1_OCInitStruct->TIM1_OutputState));
+ assert(IS_TIM1_OC_POLARITY(TIM1_OCInitStruct->TIM1_OCPolarity));
+ assert(IS_TIM1_OCIDLE_STATE(TIM1_OCInitStruct->TIM1_OCIdleState));
+
+ tmpccmr = TIM1->CCMR2;
+
+ /* Disable the Channel 4: Reset the CCE Bit */
+ *(vu32 *) CCER_CC4E_BB = CCER_CCE_Reset;
+
+ /* Reset the Output Compare Bits */
+ tmpccmr &= OC24Mode_Mask;
+
+ /* Set the Ouput Compare Mode */
+ tmpccmr |= (u32)TIM1_OCInitStruct->TIM1_OCMode << 8;
+
+ TIM1->CCMR2 = (u16)tmpccmr;
+
+ /* Set the Output State */
+ *(vu32 *) CCER_CC4E_BB = TIM1_OCInitStruct->TIM1_OutputState;
+
+ /* Set the Output Polarity */
+ *(vu32 *) CCER_CC4P_BB = TIM1_OCInitStruct->TIM1_OCPolarity;
+
+ /* Set the Output Idle state */
+ *(vu32 *) CR2_OIS4_BB = TIM1_OCInitStruct->TIM1_OCIdleState;
+
+ /* Set the Pulse value */
+ TIM1->CCR4 = TIM1_OCInitStruct->TIM1_Pulse;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_BDTRConfig
+* Description : Configures the: Break feature, dead time, Lock level, the OSSI,
+* the OSSR State and the AOE(automatic output enable).
+* Input : - TIM1_BDTRInitStruct: pointer to a TIM1_BDTRInitTypeDef
+* structure that contains the BDTR Register configuration
+* information for the TIM1 peripheral.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_BDTRConfig(TIM1_BDTRInitTypeDef *TIM1_BDTRInitStruct)
+{
+ u16 tmpbdtr = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM1_OSSR_STATE(TIM1_BDTRInitStruct->TIM1_OSSRState));
+ assert(IS_TIM1_OSSI_STATE(TIM1_BDTRInitStruct->TIM1_OSSIState));
+ assert(IS_TIM1_LOCK_LEVEL(TIM1_BDTRInitStruct->TIM1_LOCKLevel));
+ assert(IS_TIM1_BREAK_STATE(TIM1_BDTRInitStruct->TIM1_Break));
+ assert(IS_TIM1_BREAK_POLARITY(TIM1_BDTRInitStruct->TIM1_BreakPolarity));
+ assert(IS_TIM1_AUTOMATIC_OUTPUT_STATE(TIM1_BDTRInitStruct->TIM1_AutomaticOutput));
+
+ tmpbdtr = TIM1->BDTR;
+
+ /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
+ the OSSI State, the dead time value and the Automatic Output Enable Bit */
+
+ tmpbdtr = (u32)TIM1_BDTRInitStruct->TIM1_OSSRState | TIM1_BDTRInitStruct->TIM1_OSSIState |
+ TIM1_BDTRInitStruct->TIM1_LOCKLevel | TIM1_BDTRInitStruct->TIM1_DeadTime |
+ TIM1_BDTRInitStruct->TIM1_Break | TIM1_BDTRInitStruct->TIM1_BreakPolarity |
+ TIM1_BDTRInitStruct->TIM1_AutomaticOutput;
+
+ TIM1->BDTR = tmpbdtr;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_ICInit
+* Description : Initializes the TIM1 peripheral according to the specified
+* parameters in the TIM1_ICInitStruct.
+* Input : - TIM1_ICInitStruct: pointer to a TIM1_ICInitTypeDef structure
+* that contains the configuration information for the specified
+* TIM1 peripheral.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_ICInit(TIM1_ICInitTypeDef* TIM1_ICInitStruct)
+{
+ /* Check the parameters */
+ assert(IS_TIM1_CHANNEL(TIM1_ICInitStruct->TIM1_Channel));
+ assert(IS_TIM1_IC_POLARITY(TIM1_ICInitStruct->TIM1_ICPolarity));
+ assert(IS_TIM1_IC_SELECTION(TIM1_ICInitStruct->TIM1_ICSelection));
+ assert(IS_TIM1_IC_PRESCALER(TIM1_ICInitStruct->TIM1_ICPrescaler));
+ assert(IS_TIM1_IC_FILTER(TIM1_ICInitStruct->TIM1_ICFilter));
+
+ if (TIM1_ICInitStruct->TIM1_Channel == TIM1_Channel_1)
+ {
+ /* TI1 Configuration */
+ TI1_Config(TIM1_ICInitStruct->TIM1_ICPolarity,
+ TIM1_ICInitStruct->TIM1_ICSelection,
+ TIM1_ICInitStruct->TIM1_ICFilter);
+
+ /* Set the Input Capture Prescaler value */
+ TIM1_SetIC1Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler);
+ }
+ else if (TIM1_ICInitStruct->TIM1_Channel == TIM1_Channel_2)
+ {
+ /* TI2 Configuration */
+ TI2_Config(TIM1_ICInitStruct->TIM1_ICPolarity,
+ TIM1_ICInitStruct->TIM1_ICSelection,
+ TIM1_ICInitStruct->TIM1_ICFilter);
+
+ /* Set the Input Capture Prescaler value */
+ TIM1_SetIC2Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler);
+ }
+ else if (TIM1_ICInitStruct->TIM1_Channel == TIM1_Channel_3)
+ {
+ /* TI3 Configuration */
+ TI3_Config(TIM1_ICInitStruct->TIM1_ICPolarity,
+ TIM1_ICInitStruct->TIM1_ICSelection,
+ TIM1_ICInitStruct->TIM1_ICFilter);
+
+ /* Set the Input Capture Prescaler value */
+ TIM1_SetIC3Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler);
+ }
+ else
+ {
+ /* TI4 Configuration */
+ TI4_Config(TIM1_ICInitStruct->TIM1_ICPolarity,
+ TIM1_ICInitStruct->TIM1_ICSelection,
+ TIM1_ICInitStruct->TIM1_ICFilter);
+
+ /* Set the Input Capture Prescaler value */
+ TIM1_SetIC4Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler);
+ }
+}
+
+/*******************************************************************************
+* Function Name : TIM1_PWMIConfig
+* Description : Configures the TIM1 peripheral in PWM Input Mode according
+* to the specified parameters in the TIM1_ICInitStruct.
+* Input : - TIM1_ICInitStruct: pointer to a TIM1_ICInitTypeDef structure
+* that contains the configuration information for the specified
+* TIM1 peripheral.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_PWMIConfig(TIM1_ICInitTypeDef* TIM1_ICInitStruct)
+{
+ u8 ICPolarity = TIM1_ICPolarity_Rising;
+ u8 ICSelection = TIM1_ICSelection_DirectTI;
+
+ /* Check the parameters */
+ assert(IS_TIM1_PWMI_CHANNEL(TIM1_ICInitStruct->TIM1_Channel));
+ assert(IS_TIM1_IC_POLARITY(TIM1_ICInitStruct->TIM1_ICPolarity));
+ assert(IS_TIM1_IC_SELECTION(TIM1_ICInitStruct->TIM1_ICSelection));
+ assert(IS_TIM1_IC_PRESCALER(TIM1_ICInitStruct->TIM1_ICPrescaler));
+
+ /* Select the Opposite Input Polarity */
+ if (TIM1_ICInitStruct->TIM1_ICPolarity == TIM1_ICPolarity_Rising)
+ {
+ ICPolarity = TIM1_ICPolarity_Falling;
+ }
+ else
+ {
+ ICPolarity = TIM1_ICPolarity_Rising;
+ }
+
+ /* Select the Opposite Input */
+ if (TIM1_ICInitStruct->TIM1_ICSelection == TIM1_ICSelection_DirectTI)
+ {
+ ICSelection = TIM1_ICSelection_IndirectTI;
+ }
+ else
+ {
+ ICSelection = TIM1_ICSelection_DirectTI;
+ }
+
+ if (TIM1_ICInitStruct->TIM1_Channel == TIM1_Channel_1)
+ {
+ /* TI1 Configuration */
+ TI1_Config(TIM1_ICInitStruct->TIM1_ICPolarity, TIM1_ICInitStruct->TIM1_ICSelection,
+ TIM1_ICInitStruct->TIM1_ICFilter);
+
+ /* Set the Input Capture Prescaler value */
+ TIM1_SetIC1Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler);
+
+ /* TI2 Configuration */
+ TI2_Config(ICPolarity, ICSelection, TIM1_ICInitStruct->TIM1_ICFilter);
+
+ /* Set the Input Capture Prescaler value */
+ TIM1_SetIC2Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler);
+ }
+ else
+ {
+ /* TI2 Configuration */
+ TI2_Config(TIM1_ICInitStruct->TIM1_ICPolarity, TIM1_ICInitStruct->TIM1_ICSelection,
+ TIM1_ICInitStruct->TIM1_ICFilter);
+
+ /* Set the Input Capture Prescaler value */
+ TIM1_SetIC2Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler);
+
+ /* TI1 Configuration */
+ TI1_Config(ICPolarity, ICSelection, TIM1_ICInitStruct->TIM1_ICFilter);
+
+ /* Set the Input Capture Prescaler value */
+ TIM1_SetIC1Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler);
+ }
+}
+/*******************************************************************************
+* Function Name : TIM1_OCStructInit
+* Description : Fills each TIM1_OCInitStruct member with its default value.
+* Input : - TIM1_OCInitStruct : pointer to a TIM1_OCInitTypeDef structure
+* which will be initialized.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_OCStructInit(TIM1_OCInitTypeDef* TIM1_OCInitStruct)
+{
+ /* Set the default configuration */
+ TIM1_OCInitStruct->TIM1_OCMode = TIM1_OCMode_Timing;
+ TIM1_OCInitStruct->TIM1_OutputState = TIM1_OutputState_Disable;
+ TIM1_OCInitStruct->TIM1_OutputNState = TIM1_OutputNState_Disable;
+ TIM1_OCInitStruct->TIM1_Pulse = TIM1_Pulse_Reset_Mask;
+ TIM1_OCInitStruct->TIM1_OCPolarity = TIM1_OCPolarity_High;
+ TIM1_OCInitStruct->TIM1_OCNPolarity = TIM1_OCPolarity_High;
+ TIM1_OCInitStruct->TIM1_OCIdleState = TIM1_OCIdleState_Reset;
+ TIM1_OCInitStruct->TIM1_OCNIdleState = TIM1_OCNIdleState_Reset;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_ICStructInit
+* Description : Fills each TIM1_ICInitStruct member with its default value.
+* Input : - TIM1_ICInitStruct : pointer to a TIM1_ICInitTypeDef structure
+* which will be initialized.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_ICStructInit(TIM1_ICInitTypeDef* TIM1_ICInitStruct)
+{
+ /* Set the default configuration */
+ TIM1_ICInitStruct->TIM1_Channel = TIM1_Channel_1;
+ TIM1_ICInitStruct->TIM1_ICSelection = TIM1_ICSelection_DirectTI;
+ TIM1_ICInitStruct->TIM1_ICPolarity = TIM1_ICPolarity_Rising;
+ TIM1_ICInitStruct->TIM1_ICPrescaler = TIM1_ICPSC_DIV1;
+ TIM1_ICInitStruct->TIM1_ICFilter = TIM1_ICFilter_Mask;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_TimeBaseStructInit
+* Description : Fills each TIM1_TimeBaseInitStruct member with its default value.
+* Input : - TIM1_TimeBaseInitStruct : pointer to a TIM1_TimeBaseInitTypeDef
+* structure which will be initialized.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_TimeBaseStructInit(TIM1_TimeBaseInitTypeDef* TIM1_TimeBaseInitStruct)
+{
+ /* Set the default configuration */
+ TIM1_TimeBaseInitStruct->TIM1_Period = TIM1_Period_Reset_Mask;
+ TIM1_TimeBaseInitStruct->TIM1_Prescaler = TIM1_Prescaler_Reset_Mask;
+ TIM1_TimeBaseInitStruct->TIM1_ClockDivision = TIM1_CKD_DIV1;
+ TIM1_TimeBaseInitStruct->TIM1_CounterMode = TIM1_CounterMode_Up;
+ TIM1_TimeBaseInitStruct->TIM1_RepetitionCounter = TIM1_RepetitionCounter_Reset_Mask;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_BDTRStructInit
+* Description : Fills each TIM1_BDTRInitStruct member with its default value.
+* Input : - TIM1_BDTRInitStruct : pointer to a TIM1_BDTRInitTypeDef
+* structure which will be initialized.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_BDTRStructInit(TIM1_BDTRInitTypeDef* TIM1_BDTRInitStruct)
+{
+ /* Set the default configuration */
+ TIM1_BDTRInitStruct->TIM1_OSSRState = TIM1_OSSRState_Disable;
+ TIM1_BDTRInitStruct->TIM1_OSSIState = TIM1_OSSIState_Disable;
+ TIM1_BDTRInitStruct->TIM1_LOCKLevel = TIM1_LOCKLevel_OFF;
+ TIM1_BDTRInitStruct->TIM1_DeadTime = TIM1_DeadTime_Reset_Mask;
+ TIM1_BDTRInitStruct->TIM1_Break = TIM1_Break_Disable;
+ TIM1_BDTRInitStruct->TIM1_BreakPolarity = TIM1_BreakPolarity_Low;
+ TIM1_BDTRInitStruct->TIM1_AutomaticOutput = TIM1_AutomaticOutput_Disable;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_Cmd
+* Description : Enables or disables the TIM1 peripheral.
+* Input : - Newstate: new state of the TIM1 peripheral.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_Cmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ /* set or Reset the CEN Bit */
+ *(vu32 *) CR1_CEN_BB = (u16)NewState;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_CtrlPWMOutputs
+* Description : Enables or disables the TIM1 peripheral Main Outputs.
+* Input : - Newstate: new state of the TIM1 peripheral Main Outputs.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_CtrlPWMOutputs(FunctionalState Newstate)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(Newstate));
+
+ /* Set or Reset the MOE Bit */
+ *(vu32 *) BDTR_MOE_BB = (u16)Newstate;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_ITConfig
+* Description : Enables or disables the specified TIM1 interrupts.
+* Input : - TIM1_IT: specifies the TIM1 interrupts sources to be enabled
+* or disabled.
+* This parameter can be any combination of the following values:
+* - TIM1_IT_Update: TIM1 update Interrupt source
+* - TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source
+* - TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source
+* - TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source
+* - TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source
+* - TIM1_IT_CCUpdate: TIM1 Capture Compare Update Interrupt
+* source
+* - TIM1_IT_Trigger: TIM1 Trigger Interrupt source
+* - TIM1_IT_Break: TIM1 Break Interrupt source
+* - Newstate: new state of the TIM1 interrupts.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_ITConfig(u16 TIM1_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_TIM1_IT(TIM1_IT));
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState == ENABLE)
+ {
+ /* Enable the Interrupt sources */
+ TIM1->DIER |= TIM1_IT;
+ }
+ else
+ {
+ /* Disable the Interrupt sources */
+ TIM1->DIER &= (u16)~TIM1_IT;
+ }
+}
+
+/*******************************************************************************
+* Function Name : TIM1_DMAConfig
+* Description : Configures the TIM1s DMA interface.
+* Input : - TIM1_DMABase: DMA Base address.
+* This parameter can be one of the following values:
+* - TIM1_DMABase_CR1, TIM1_DMABase_CR2, TIM1_DMABase_SMCR,
+* TIM1_DMABase_DIER, TIM1_DMABase_SR, TIM1_DMABase_EGR,
+* TIM1_DMABase_CCMR1, TIM1_DMABase_CCMR2, TIM1_DMABase_CCER,
+* TIM1_DMABase_CNT, TIM1_DMABase_PSC, TIM1_DMABase_ARR,
+* TIM1_DMABase_RCR, TIM1_DMABase_CCR1, TIM1_DMABase_CCR2,
+* TIM1_DMABase_CCR3, TIM1_DMABase_CCR4, TIM1_DMABase_BDTR,
+* TIM1_DMABase_DCR.
+* - TIM1_DMABurstLength: DMA Burst length.
+* This parameter can be one value between:
+* TIM1_DMABurstLength_1Byte and TIM1_DMABurstLength_18Bytes.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_DMAConfig(u16 TIM1_DMABase, u16 TIM1_DMABurstLength)
+{
+ u32 tmpdcr = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM1_DMA_BASE(TIM1_DMABase));
+ assert(IS_TIM1_DMA_LENGTH(TIM1_DMABurstLength));
+
+ tmpdcr = TIM1->DCR;
+
+ /* Reset the DBA and the DBL Bits */
+ tmpdcr &= DCR_DMA_Mask;
+
+ /* Set the DMA Base and the DMA Burst Length */
+ tmpdcr |= TIM1_DMABase | TIM1_DMABurstLength;
+
+ TIM1->DCR = (u16)tmpdcr;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_DMACmd
+* Description : Enables or disables the TIM1s DMA Requests.
+* Input : - TIM1_DMASources: specifies the DMA Request sources.
+* This parameter can be any combination of the following values:
+* - TIM1_DMA_Update: TIM1 update Interrupt source
+* - TIM1_DMA_CC1: TIM1 Capture Compare 1 DMA source
+* - TIM1_DMA_CC2: TIM1 Capture Compare 2 DMA source
+* - TIM1_DMA_CC3: TIM1 Capture Compare 3 DMA source
+* - TIM1_DMA_CC4: TIM1 Capture Compare 4 DMA source
+* - TIM1_DMA_COM: TIM1 Capture Compare Update DMA
+* source
+* - TIM1_DMA_Trigger: TIM1 Trigger DMA source
+* - Newstate: new state of the DMA Request sources.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_DMACmd(u16 TIM1_DMASource, FunctionalState Newstate)
+{
+ u32 tmpdier = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM1_DMA_SOURCE(TIM1_DMASource));
+ assert(IS_FUNCTIONAL_STATE(Newstate));
+
+ tmpdier = TIM1->DIER;
+
+ if (Newstate == ENABLE)
+ {
+ /* Enable the DMA sources */
+ tmpdier |= TIM1_DMASource;
+ }
+ else
+ {
+ /* Disable the DMA sources */
+ tmpdier &= (u16)~TIM1_DMASource;
+ }
+ TIM1->DIER = (u16)tmpdier;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_InternalClockConfig
+* Description : Configures the TIM1 interrnal Clock
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_InternalClockConfig(void)
+{
+ /* Disable slave mode to clock the prescaler directly with the internal clock */
+ TIM1->SMCR &= SMCR_SMS_Mask;
+}
+/*******************************************************************************
+* Function Name : TIM1_ETRClockMode1Config
+* Description : Configures the TIM1 External clock Mode1
+* Input : - TIM1_ExtTRGPrescaler: The external Trigger Prescaler.
+* It can be one of the following values:
+* - TIM1_ExtTRGPSC_OFF
+* - TIM1_ExtTRGPSC_DIV2
+* - TIM1_ExtTRGPSC_DIV4
+* - TIM1_ExtTRGPSC_DIV8.
+* - TIM1_ExtTRGPolarity: The external Trigger Polarity.
+* It can be one of the following values:
+* - TIM1_ExtTRGPolarity_Inverted
+* - TIM1_ExtTRGPolarity_NonInverted
+* - ExtTRGFilter: External Trigger Filter.
+* This parameter must be a value between 0x00 and 0x0F
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_ETRClockMode1Config(u16 TIM1_ExtTRGPrescaler, u16 TIM1_ExtTRGPolarity,
+ u16 ExtTRGFilter)
+{
+ /* Check the parameters */
+ assert(IS_TIM1_EXT_PRESCALER(TIM1_ExtTRGPrescaler));
+ assert(IS_TIM1_EXT_POLARITY(TIM1_ExtTRGPolarity));
+
+ /* Configure the ETR Clock source */
+ ETR_Config(TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity, ExtTRGFilter);
+
+ /* Select the External clock mode1 */
+ TIM1->SMCR &= SMCR_SMS_Mask;
+ TIM1->SMCR |= TIM1_SlaveMode_External1;
+
+ /* Select the Trigger selection : ETRF */
+ TIM1->SMCR &= SMCR_TS_Mask;
+ TIM1->SMCR |= TIM1_TS_ETRF;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_ETRClockMode2Config
+* Description : Configures the TIM1 External clock Mode2
+* Input : - TIM1_ExtTRGPrescaler: The external Trigger Prescaler.
+* It can be one of the following values:
+* - TIM1_ExtTRGPSC_OFF
+* - TIM1_ExtTRGPSC_DIV2
+* - TIM1_ExtTRGPSC_DIV4
+* - TIM1_ExtTRGPSC_DIV8
+* - TIM1_ExtTRGPolarity: The external Trigger Polarity.
+* It can be one of the following values:
+* - TIM1_ExtTRGPolarity_Inverted
+* - TIM1_ExtTRGPolarity_NonInverted
+* - ExtTRGFilter: External Trigger Filter.
+* This parameter must be a value between 0x00 and 0x0F
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_ETRClockMode2Config(u16 TIM1_ExtTRGPrescaler, u16 TIM1_ExtTRGPolarity,
+ u16 ExtTRGFilter)
+{
+ /* Check the parameters */
+ assert(IS_TIM1_EXT_PRESCALER(TIM1_ExtTRGPrescaler));
+ assert(IS_TIM1_EXT_POLARITY(TIM1_ExtTRGPolarity));
+
+ /* Configure the ETR Clock source */
+ ETR_Config(TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity, ExtTRGFilter);
+
+ /* Enable the External clock mode2 */
+ *(vu32 *) SMCR_ECE_BB = SMCR_ECE_Set;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_ITRxExternalClockConfig
+* Description : Configures the TIM1 Internal Trigger as External Clock
+* Input : - TIM1_ITRSource: Internal Trigger source.
+* This parameter can be one of the following values:
+* - TIM1_TS_ITR0: Internal Trigger 0
+* - TIM1_TS_ITR1: Internal Trigger 1
+* - TIM1_TS_ITR2: Internal Trigger 2
+* - TIM1_TS_ITR3: Internal Trigger 3
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_ITRxExternalClockConfig(u16 TIM1_InputTriggerSource)
+{
+ /* Check the parameters */
+ assert(IS_TIM1_INTERNAL_TRIGGER_SELECTION(TIM1_InputTriggerSource));
+
+ /* Select the Internal Trigger */
+ TIM1_SelectInputTrigger(TIM1_InputTriggerSource);
+
+ /* Select the External clock mode1 */
+ TIM1->SMCR |= TIM1_SlaveMode_External1;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_TIxExternalClockConfig
+* Description : Configures the TIM1 Trigger as External Clock
+* Input : - TIM1_TIxExternalCLKSource: Trigger source.
+* This parameter can be one of the following values:
+* - TIM1_TS_TI1F_ED: TI1 Edge Detector
+* - TIM1_TS_TI1FP1: Filtered TIM1 Input 1
+* - TIM1_TS_TI2FP2: Filtered TIM1 Input 2
+* - TIM1_ICPolarity: specifies the TIx Polarity.
+* This parameter can be:
+* - TIM1_ICPolarity_Rising
+* - TIM1_ICPolarity_Falling
+* - ICFilter : specifies the filter value.
+* This parameter must be a value between 0x0 and 0xF.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_TIxExternalClockConfig(u16 TIM1_TIxExternalCLKSource,
+ u16 TIM1_ICPolarity, u8 ICFilter)
+{
+ /* Check the parameters */
+ assert(IS_TIM1_TIX_TRIGGER_SELECTION(TIM1_TIxExternalCLKSource));
+ assert(IS_TIM1_IC_POLARITY(TIM1_ICPolarity));
+ assert(IS_TIM1_IC_FILTER(ICFilter));
+
+ /* Configure the TIM1 Input Clock Source */
+ if (TIM1_TIxExternalCLKSource == TIM1_TIxExternalCLK1Source_TI2)
+ {
+ TI2_Config(TIM1_ICPolarity, TIM1_ICSelection_DirectTI, ICFilter);
+ }
+ else
+ {
+ TI1_Config(TIM1_ICPolarity, TIM1_ICSelection_DirectTI, ICFilter);
+ }
+
+ /* Select the Trigger source */
+ TIM1_SelectInputTrigger(TIM1_TIxExternalCLKSource);
+
+ /* Select the External clock mode1 */
+ TIM1->SMCR |= TIM1_SlaveMode_External1;
+}
+/*******************************************************************************
+* Function Name : TIM1_SelectInputTrigger
+* Description : Selects the TIM1 Input Trigger source
+* Input : - TIM1_InputTriggerSource: The Trigger source.
+* This parameter can be one of the following values:
+* - TIM1_TS_ITR0: Internal Trigger 0
+* - TIM1_TS_ITR1: Internal Trigger 1
+* - TIM1_TS_ITR2: Internal Trigger 2
+* - TIM1_TS_ITR3: Internal Trigger 3
+* - TIM1_TS_TI1F_ED: TI1 Edge Detector
+* - TIM1_TS_TI1FP1: Filtered Timer Input 1
+* - TIM1_TS_TI2FP2: Filtered Timer Input 2
+* - TIM1_TS_ETRF: External Trigger input
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_SelectInputTrigger(u16 TIM1_InputTriggerSource)
+{
+ u32 tmpsmcr = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM1_TRIGGER_SELECTION(TIM1_InputTriggerSource));
+
+ tmpsmcr = TIM1->SMCR;
+
+ /* Select the Tgigger Source */
+ tmpsmcr &= SMCR_TS_Mask;
+ tmpsmcr |= TIM1_InputTriggerSource;
+
+ TIM1->SMCR = (u16)tmpsmcr;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_UpdateDisableConfig
+* Description : Enables or Disables the TIM1 Update event.
+* Input : - Newstate: new state of the TIM1 peripheral Preload register
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_UpdateDisableConfig(FunctionalState Newstate)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(Newstate));
+
+ /* Set or Reset the UDIS Bit */
+ *(vu32 *) CR1_UDIS_BB = (u16)Newstate;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_UpdateRequestConfig
+* Description : Selects the TIM1 Update Request Interrupt source.
+* Input : - TIM1_UpdateSource: specifies the Update source.
+* This parameter can be one of the following values:
+* - TIM1_UpdateSource_Regular
+* - TIM1_UpdateSource_Global
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_UpdateRequestConfig(u8 TIM1_UpdateSource)
+{
+ /* Check the parameters */
+ assert(IS_TIM1_UPDATE_SOURCE(TIM1_UpdateSource));
+
+ /* Set or Reset the URS Bit */
+ *(vu32 *) CR1_URS_BB = TIM1_UpdateSource;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_SelectHallSensor
+* Description : Enables or disables the TIM1s Hall sensor interface.
+* Input : - Newstate: new state of the TIM1 Hall sensor interface
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_SelectHallSensor(FunctionalState Newstate)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(Newstate));
+
+ /* Set or Reset the TI1S Bit */
+ *(vu32 *) CR2_TI1S_BB = (u16)Newstate;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_SelectOPM
+* Description : Enables or disables the TIM1s One Pulse Mode.
+* Input : - TIM1_OPMode: specifies the OPM Mode to be used.
+* This parameter can be one of the following values:
+* - TIM1_OPMode_Single
+* - TIM1_OPMode_Repetitive
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_SelectOnePulseMode(u16 TIM1_OPMode)
+{
+ /* Check the parameters */
+ assert(IS_TIM1_OPM_MODE(TIM1_OPMode));
+
+ /* Set or Reset the OPM Bit */
+ *(vu32 *) CR1_OPM_BB = TIM1_OPMode;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_SelectOutputTrigger
+* Description : Selects the TIM1 Trigger Output Mode.
+* Input : - TIM1_TRGOSource: specifies the Trigger Output source.
+* This paramter can be one of the following values:
+* - TIM1_TRGOSource_Reset
+* - TIM1_TRGOSource_Enable
+* - TIM1_TRGOSource_Update
+* - TIM1_TRGOSource_OC1
+* - TIM1_TRGOSource_OC1Ref
+* - TIM1_TRGOSource_OC2Ref
+* - TIM1_TRGOSource_OC3Ref
+* - TIM1_TRGOSource_OC4Ref
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_SelectOutputTrigger(u16 TIM1_TRGOSource)
+{
+ u32 tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM1_TRGO_SOURCE(TIM1_TRGOSource));
+
+ tmpcr2 = TIM1->CR2;
+
+ /* Reset the MMS Bits */
+ tmpcr2 &= CR2_MMS_Mask;
+
+ /* Select the TRGO source */
+ tmpcr2 |= TIM1_TRGOSource;
+
+ TIM1->CR2 = (u16)tmpcr2;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_SelectSlaveMode
+* Description : Selects the TIM1 Slave Mode.
+* Input : - TIM1_SlaveMode: specifies the TIM1 Slave Mode.
+* This paramter can be one of the following values:
+* - TIM1_SlaveMode_Reset
+* - TIM1_SlaveMode_Gated
+* - TIM1_SlaveMode_Trigger
+* - TIM1_SlaveMode_External1
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_SelectSlaveMode(u16 TIM1_SlaveMode)
+{
+ u32 tmpsmcr = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM1_SLAVE_MODE(TIM1_SlaveMode));
+
+ tmpsmcr = TIM1->SMCR;
+
+ /* Reset the SMS Bits */
+ tmpsmcr &= SMCR_SMS_Mask;
+
+ /* Select the Slave Mode */
+ tmpsmcr |= TIM1_SlaveMode;
+
+ TIM1->SMCR = (u16)tmpsmcr;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_SelectMasterSlaveMode
+* Description : Sets or Resets the TIM1 Master/Slave Mode.
+* Input : - TIM1_MasterSlaveMode: specifies the TIM1 Master Slave Mode.
+* This paramter can be one of the following values:
+* - TIM1_MasterSlaveMode_Enable: synchronization between
+* the current timer and its slaves (through TRGO).
+* - TIM1_MasterSlaveMode_Disable: No action
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_SelectMasterSlaveMode(u16 TIM1_MasterSlaveMode)
+{
+ /* Check the parameters */
+ assert(IS_TIM1_MSM_STATE(TIM1_MasterSlaveMode));
+
+ /* Set or Reset the MSM Bit */
+ *(vu32 *) SMCR_MSM_BB = TIM1_MasterSlaveMode;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_EncoderInterfaceConfig
+* Description : Configures the TIM1 Encoder Interface.
+* Input : - TIM1_EncoderMode: specifies the TIM1 Encoder Mode.
+* This parameter can be one of the following values:
+* - TIM1_EncoderMode_TI1: Counter counts on TI1FP1 edge
+* depending on TI2FP2 level.
+* - TIM1_EncoderMode_TI2: Counter counts on TI2FP2 edge
+* depending on TI1FP1 level.
+* - TIM1_EncoderMode_TI12: Counter counts on both TI1FP1 and
+* TI2FP2 edges depending on the level of the other input.
+* - TIM1_IC1Polarity: specifies the IC1 Polarity
+* This parmeter can be one of the following values:
+* - TIM1_ICPolarity_Falling
+* - TIM1_ICPolarity_Rising
+* - TIM1_IC2Polarity: specifies the IC2 Polarity
+* This parmeter can be one of the following values:
+* - TIM1_ICPolarity_Falling
+* - TIM1_ICPolarity_Rising
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_EncoderInterfaceConfig(u16 TIM1_EncoderMode, u16 TIM1_IC1Polarity,
+ u16 TIM1_IC2Polarity)
+{
+ u32 tmpsmcr = 0;
+ u32 tmpccmr1 = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM1_ENCODER_MODE(TIM1_EncoderMode));
+ assert(IS_TIM1_IC_POLARITY(TIM1_IC1Polarity));
+ assert(IS_TIM1_IC_POLARITY(TIM1_IC2Polarity));
+
+ tmpsmcr = TIM1->SMCR;
+ tmpccmr1 = TIM1->CCMR1;
+
+ /* Set the encoder Mode */
+ tmpsmcr &= SMCR_SMS_Mask;
+ tmpsmcr |= TIM1_EncoderMode;
+
+ /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+ tmpccmr1 &= CCMR_CC13S_Mask & CCMR_CC24S_Mask;
+ tmpccmr1 |= CCMR_TI13Direct_Set | CCMR_TI24Direct_Set;
+
+ /* Set the TI1 and the TI2 Polarities */
+ *(vu32 *) CCER_CC1P_BB = TIM1_IC1Polarity;
+ *(vu32 *) CCER_CC2P_BB = TIM1_IC2Polarity;
+
+ TIM1->SMCR = (u16)tmpsmcr;
+
+ TIM1->CCMR1 = (u16)tmpccmr1;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_PrescalerConfig
+* Description : Configures the TIM1 Prescaler.
+* Input : - Prescaler: specifies the Prescaler Register value
+* - TIM1_PSCReloadMode: specifies the TIM1 Prescaler Reload mode.
+* This parmeter can be one of the following values:
+* - TIM1_PSCReloadMode_Update: The Prescaler is loaded at
+* the update event.
+* - TIM1_PSCReloadMode_Immediate: The Prescaler is loaded
+* immediatly.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_PrescalerConfig(u16 Prescaler, u16 TIM1_PSCReloadMode)
+{
+ /* Check the parameters */
+ assert(IS_TIM1_PRESCALER_RELOAD(TIM1_PSCReloadMode));
+
+ /* Set the Prescaler value */
+ TIM1->PSC = Prescaler;
+
+ /* Set or reset the UG Bit */
+ *(vu32 *) EGR_UG_BB = TIM1_PSCReloadMode;
+}
+/*******************************************************************************
+* Function Name : TIM1_CounterModeConfig
+* Description : Specifies the TIM1 Counter Mode to be used.
+* Input : - TIM1_CounterMode: specifies the Counter Mode to be used
+* This parameter can be one of the following values:
+* - TIM1_CounterMode_Up: TIM1 Up Counting Mode
+* - TIM1_CounterMode_Down: TIM1 Down Counting Mode
+* - TIM1_CounterMode_CenterAligned1: TIM1 Center Aligned Mode1
+* - TIM1_CounterMode_CenterAligned2: TIM1 Center Aligned Mode2
+* - TIM1_CounterMode_CenterAligned3: TIM1 Center Aligned Mode3
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_CounterModeConfig(u16 TIM1_CounterMode)
+{
+ u32 tmpcr1 = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM1_COUNTER_MODE(TIM1_CounterMode));
+
+ tmpcr1 = TIM1->CR1;
+
+ /* Reset the CMS and DIR Bits */
+ tmpcr1 &= CR1_CounterMode_Mask;
+
+ /* Set the Counter Mode */
+ tmpcr1 |= TIM1_CounterMode;
+
+ TIM1->CR1 = (u16)tmpcr1;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_ForcedOC1Config
+* Description : Forces the TIM1 Channel1 output waveform to active or inactive
+* level.
+* Input : - TIM1_ForcedAction: specifies the forced Action to be set to
+* the output waveform.
+* This parameter can be one of the following values:
+* - TIM1_ForcedAction_Active: Force active level on OC1REF
+* - TIM1_ForcedAction_InActive: Force inactive level on
+* OC1REF.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_ForcedOC1Config(u16 TIM1_ForcedAction)
+{
+ u32 tmpccmr1 = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM1_FORCED_ACTION(TIM1_ForcedAction));
+
+ tmpccmr1 = TIM1->CCMR1;
+
+ /* Reset the OCM Bits */
+ tmpccmr1 &= CCMR_OCM13_Mask;
+
+ /* Configure The Forced output Mode */
+ tmpccmr1 |= TIM1_ForcedAction;
+
+ TIM1->CCMR1 = (u16)tmpccmr1;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_ForcedOC2Config
+* Description : Forces the TIM1 Channel2 output waveform to active or inactive
+* level.
+* Input : - TIM1_ForcedAction: specifies the forced Action to be set to
+* the output waveform.
+* This parameter can be one of the following values:
+* - TIM1_ForcedAction_Active: Force active level on OC2REF
+* - TIM1_ForcedAction_InActive: Force inactive level on
+* OC2REF.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_ForcedOC2Config(u16 TIM1_ForcedAction)
+{
+ u32 tmpccmr1 = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM1_FORCED_ACTION(TIM1_ForcedAction));
+
+ tmpccmr1 = TIM1->CCMR1;
+
+ /* Reset the OCM Bits */
+ tmpccmr1 &= CCMR_OCM24_Mask;
+
+ /* Configure The Forced output Mode */
+ tmpccmr1 |= (u32)TIM1_ForcedAction << 8;
+
+ TIM1->CCMR1 = (u16)tmpccmr1;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_ForcedOC3Config
+* Description : Forces the TIM1 Channel3 output waveform to active or inactive
+* level.
+* Input : - TIM1_ForcedAction: specifies the forced Action to be set to
+* the output waveform.
+* This parameter can be one of the following values:
+* - TIM1_ForcedAction_Active: Force active level on OC3REF
+* - TIM1_ForcedAction_InActive: Force inactive level on
+* OC3REF.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_ForcedOC3Config(u16 TIM1_ForcedAction)
+{
+ u32 tmpccmr2 = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM1_FORCED_ACTION(TIM1_ForcedAction));
+
+ tmpccmr2 = TIM1->CCMR2;
+
+ /* Reset the OCM Bits */
+ tmpccmr2 &= CCMR_OCM13_Mask;
+
+ /* Configure The Forced output Mode */
+ tmpccmr2 |= TIM1_ForcedAction;
+
+ TIM1->CCMR2 = (u16)tmpccmr2;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_ForcedOC4Config
+* Description : Forces the TIM1 Channel4 output waveform to active or inactive
+* level.
+* Input : - TIM1_ForcedAction: specifies the forced Action to be set to
+* the output waveform.
+* This parameter can be one of the following values:
+* - TIM1_ForcedAction_Active: Force active level on OC4REF
+* - TIM1_ForcedAction_InActive: Force inactive level on
+* OC4REF.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_ForcedOC4Config(u16 TIM1_ForcedAction)
+{
+ u32 tmpccmr2 = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM1_FORCED_ACTION(TIM1_ForcedAction));
+
+ tmpccmr2 = TIM1->CCMR1;
+
+ /* Reset the OCM Bits */
+ tmpccmr2 &= CCMR_OCM24_Mask;
+
+ /* Configure The Forced output Mode */
+ tmpccmr2 |= (u16)((u16)TIM1_ForcedAction << 8);
+
+ TIM1->CCMR2 = (u16)tmpccmr2;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_ARRPreloadConfig
+* Description : Enables or disables TIM1 peripheral Preload register on ARR.
+* Input : - Newstate: new state of the TIM1 peripheral Preload register
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_ARRPreloadConfig(FunctionalState Newstate)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(Newstate));
+
+ /* Set or Reset the ARPE Bit */
+ *(vu32 *) CR1_ARPE_BB = (u16)Newstate;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_SelectCOM
+* Description : Selects the TIM1 peripheral Commutation event.
+* Input : - Newstate: new state of the Commutation event.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_SelectCOM(FunctionalState Newstate)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(Newstate));
+
+ /* Set or Reset the CCUS Bit */
+ *(vu32 *) CR2_CCUS_BB = (u16)Newstate;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_SelectCCDMA
+* Description : Selects the TIM1 peripheral Capture Compare DMA source.
+* Input : - Newstate: new state of the Capture Compare DMA source
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_SelectCCDMA(FunctionalState Newstate)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(Newstate));
+
+ /* Set or Reset the CCDS Bit */
+ *(vu32 *) CR2_CCDS_BB = (u16)Newstate;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_CCPreloadControl
+* Description : Sets or Resets the TIM1 peripheral Capture Compare Preload
+* Control bit.
+* Input : - Newstate: new state of the Capture Compare Preload Control bit
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_CCPreloadControl(FunctionalState Newstate)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(Newstate));
+
+ /* Set or Reset the CCPC Bit */
+ *(vu32 *) CR2_CCPC_BB = (u16)Newstate;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_OC1PreloadConfig
+* Description : Enables or disables the TIM1 peripheral Preload Register on CCR1.
+* Input : - TIM1_OCPreload: new state of the Capture Compare Preload
+* register.
+* This parameter can be one of the following values:
+* - TIM1_OCPreload_Enable
+* - TIM1_OCPreload_Disable
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_OC1PreloadConfig(u16 TIM1_OCPreload)
+{
+ /* Check the parameters */
+ assert(IS_TIM1_OCPRELOAD_STATE(TIM1_OCPreload));
+
+ /* Set or Reset the OC1PE Bit */
+ *(vu32 *) CCMR1_OC1PE_BB = (u16)TIM1_OCPreload;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_OC2PreloadConfig
+* Description : Enables or disables the TIM1 peripheral Preload Register on CCR2.
+* Input : - TIM1_OCPreload: new state of the Capture Compare Preload
+* register.
+* This parameter can be one of the following values:
+* - TIM1_OCPreload_Enable
+* - TIM1_OCPreload_Disable
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_OC2PreloadConfig(u16 TIM1_OCPreload)
+{
+ /* Check the parameters */
+ assert(IS_TIM1_OCPRELOAD_STATE(TIM1_OCPreload));
+
+ /* Set or Reset the OC2PE Bit */
+ *(vu32 *) CCMR1_OC2PE_BB = (u16)TIM1_OCPreload;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_OC3PreloadConfig
+* Description : Enables or disables the TIM1 peripheral Preload Register on CCR3.
+* Input : - TIM1_OCPreload: new state of the Capture Compare Preload
+* register.
+* This parameter can be one of the following values:
+* - TIM1_OCPreload_Enable
+* - TIM1_OCPreload_Disable
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_OC3PreloadConfig(u16 TIM1_OCPreload)
+{
+ /* Check the parameters */
+ assert(IS_TIM1_OCPRELOAD_STATE(TIM1_OCPreload));
+
+ /* Set or Reset the OC3PE Bit */
+ *(vu32 *) CCMR2_OC3PE_BB = (u16)TIM1_OCPreload;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_OC4PreloadConfig
+* Description : Enables or disables the TIM1 peripheral Preload Register on CCR4.
+* Input : - TIM1_OCPreload: new state of the Capture Compare Preload
+* register.
+* This parameter can be one of the following values:
+* - TIM1_OCPreload_Enable
+* - TIM1_OCPreload_Disable
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_OC4PreloadConfig(u16 TIM1_OCPreload)
+{
+ /* Check the parameters */
+ assert(IS_TIM1_OCPRELOAD_STATE(TIM1_OCPreload));
+
+ /* Set or Reset the OC4PE Bit */
+ *(vu32 *) CCMR2_OC4PE_BB = (u16)TIM1_OCPreload;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_OC1FastConfig
+* Description : Configures the TIM1 Capture Compare 1 Fast feature.
+* Input : - TIM1_OCFast: new state of the Output Compare Fast Enable bit.
+* This parameter can be one of the following values:
+* - TIM1_OCFast_Enable
+* - TIM1_OCFast_Disable
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_OC1FastConfig(u16 TIM1_OCFast)
+{
+ /* Check the parameters */
+ assert(IS_TIM1_OCFAST_STATE(TIM1_OCFast));
+
+ /* Set or Reset the OC1FE Bit */
+ *(vu32 *) CCMR1_OC1FE_BB = (u16)TIM1_OCFast;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_OC2FastConfig
+* Description : Configures the TIM1 Capture Compare Fast feature.
+* Input : - TIM1_OCFast: new state of the Output Compare Fast Enable bit.
+* This parameter can be one of the following values:
+* - TIM1_OCFast_Enable
+* - TIM1_OCFast_Disable
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_OC2FastConfig(u16 TIM1_OCFast)
+{
+ /* Check the parameters */
+ assert(IS_TIM1_OCFAST_STATE(TIM1_OCFast));
+
+ /* Set or Reset the OC2FE Bit */
+ *(vu32 *) CCMR1_OC2FE_BB = (u16)TIM1_OCFast;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_OC3FastConfig
+* Description : Configures the TIM1 Capture Compare Fast feature.
+* Input : - TIM1_OCFast: new state of the Output Compare Fast Enable bit.
+* This parameter can be one of the following values:
+* - TIM1_OCFast_Enable
+* - TIM1_OCFast_Disable
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_OC3FastConfig(u16 TIM1_OCFast)
+{
+ /* Check the parameters */
+ assert(IS_TIM1_OCFAST_STATE(TIM1_OCFast));
+
+ /* Set or Reset the OC3FE Bit */
+ *(vu32 *) CCMR2_OC3FE_BB = (u16)TIM1_OCFast;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_OC4FastConfig
+* Description : Configures the TIM1 Capture Compare Fast feature.
+* Input : - TIM1_OCFast: new state of the Output Compare Fast Enable bit.
+* This parameter can be one of the following values:
+* - TIM1_OCFast_Enable
+* - TIM1_OCFast_Disable
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_OC4FastConfig(u16 TIM1_OCFast)
+{
+ /* Check the parameters */
+ assert(IS_TIM1_OCFAST_STATE(TIM1_OCFast));
+
+ /* Set or Reset the OC4FE Bit */
+ *(vu32 *) CCMR2_OC4FE_BB = (u16)TIM1_OCFast;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_GenerateEvent
+* Description : Configures the TIM1 event to be generate by software.
+* Input : - TIM1_EventSource: specifies the event source.
+* This parameter can be one or more of the following values:
+* - TIM1_EventSource_Update: TIM1 update Event source
+* - TIM1_EventSource_CC1: TIM1 Capture Compare 1 Event source
+* - TIM1_EventSource_CC2: TIM1 Capture Compare 2 Event source
+* - TIM1_EventSource_CC3: TIM1 Capture Compare 3 Event source
+* - TIM1_EventSource_CC4: TIM1 Capture Compare 4 Event source
+* - TIM1_EventSource_COM: TIM1 COM Event source
+* - TIM1_EventSource_Trigger: TIM1 Trigger Event source
+* - TIM1_EventSourceBreak: TIM1 Break Event source
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_GenerateEvent(u16 TIM1_EventSource)
+{
+ /* Check the parameters */
+ assert(IS_TIM1_EVENT_SOURCE(TIM1_EventSource));
+
+ /* Set the event sources */
+ TIM1->EGR |= TIM1_EventSource;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_OC1PolarityConfig
+* Description : Configures the TIM1 Channel 1 polarity.
+* Input : - TIM1_OCPolarity: specifies the OC1 Polarity
+* This parmeter can be one of the following values:
+* - TIM1_OCPolarity_High: Output Compare active high
+* - TIM1_OCPolarity_Low: Output Compare active low
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_OC1PolarityConfig(u16 TIM1_OCPolarity)
+{
+ /* Check the parameters */
+ assert(IS_TIM1_OC_POLARITY(TIM1_OCPolarity));
+
+ /* Set or Reset the CC1P Bit */
+ *(vu32 *) CCER_CC1P_BB = (u16)TIM1_OCPolarity;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_OC1NPolarityConfig
+* Description : Configures the TIM1 Channel 1N polarity.
+* Input : - TIM1_OCPolarity: specifies the OC1N Polarity
+* This parmeter can be one of the following values:
+* - TIM1_OCPolarity_High: Output Compare active high
+* - TIM1_OCPolarity_Low: Output Compare active low
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_OC1NPolarityConfig(u16 TIM1_OCPolarity)
+{
+ /* Check the parameters */
+ assert(IS_TIM1_OC_POLARITY(TIM1_OCPolarity));
+
+ /* Set or Reset the CC3P Bit */
+ *(vu32 *) CCER_CC1NP_BB = (u16)TIM1_OCPolarity;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_OC2PolarityConfig
+* Description : Configures the TIM1 Channel 2 polarity.
+* Input : - TIM1_OCPolarity: specifies the OC2 Polarity
+* This parmeter can be one of the following values:
+* - TIM1_OCPolarity_High: Output Compare active high
+* - TIM1_OCPolarity_Low: Output Compare active low
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_OC2PolarityConfig(u16 TIM1_OCPolarity)
+{
+ /* Check the parameters */
+ assert(IS_TIM1_OC_POLARITY(TIM1_OCPolarity));
+
+ /* Set or Reset the CC2P Bit */
+ *(vu32 *) CCER_CC2P_BB = (u16)TIM1_OCPolarity;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_OC2NPolarityConfig
+* Description : Configures the TIM1 Channel 2N polarity.
+* Input : - TIM1_OCPolarity: specifies the OC2N Polarity
+* This parmeter can be one of the following values:
+* - TIM1_OCPolarity_High: Output Compare active high
+* - TIM1_OCPolarity_Low: Output Compare active low
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_OC2NPolarityConfig(u16 TIM1_OCPolarity)
+{
+ /* Check the parameters */
+ assert(IS_TIM1_OC_POLARITY(TIM1_OCPolarity));
+
+ /* Set or Reset the CC3P Bit */
+ *(vu32 *) CCER_CC2NP_BB = (u16)TIM1_OCPolarity;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_OC3PolarityConfig
+* Description : Configures the TIM1 Channel 3 polarity.
+* Input : - TIM1_OCPolarity: specifies the OC3 Polarity
+* This parmeter can be one of the following values:
+* - TIM1_OCPolarity_High: Output Compare active high
+* - TIM1_OCPolarity_Low: Output Compare active low
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_OC3PolarityConfig(u16 TIM1_OCPolarity)
+{
+ /* Check the parameters */
+ assert(IS_TIM1_OC_POLARITY(TIM1_OCPolarity));
+
+ /* Set or Reset the CC3P Bit */
+ *(vu32 *) CCER_CC3P_BB = (u16)TIM1_OCPolarity;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_OC3NPolarityConfig
+* Description : Configures the TIM1 Channel 3N polarity.
+* Input : - TIM1_OCPolarity: specifies the OC3N Polarity
+* This parmeter can be one of the following values:
+* - TIM1_OCPolarity_High: Output Compare active high
+* - TIM1_OCPolarity_Low: Output Compare active low
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_OC3NPolarityConfig(u16 TIM1_OCPolarity)
+{
+ /* Check the parameters */
+ assert(IS_TIM1_OC_POLARITY(TIM1_OCPolarity));
+
+ /* Set or Reset the CC3P Bit */
+ *(vu32 *) CCER_CC3NP_BB = (u16)TIM1_OCPolarity;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_OC4PolarityConfig
+* Description : Configures the TIM1 Channel 4 polarity.
+* Input : - TIM1_OCPolarity: specifies the OC4 Polarity
+* This parmeter can be one of the following values:
+* - TIM1_OCPolarity_High: Output Compare active high
+* - TIM1_OCPolarity_Low: Output Compare active low
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_OC4PolarityConfig(u16 TIM1_OCPolarity)
+{
+ /* Check the parameters */
+ assert(IS_TIM1_OC_POLARITY(TIM1_OCPolarity));
+
+ /* Set or Reset the CC4P Bit */
+ *(vu32 *) CCER_CC4P_BB = (u16)TIM1_OCPolarity;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_CCxCmd
+* Description : Enables or disables the TIM1 Capture Compare Channel x.
+* Input : - TIM1_Channel: specifies the TIM1 Channel
+* This parmeter can be one of the following values:
+* - TIM1_Channel1: TIM1 Channel1
+* - TIM1_Channel2: TIM1 Channel2
+* - TIM1_Channel3: TIM1 Channel3
+* - TIM1_Channel4: TIM1 Channel4
+* - Newstate: specifies the TIM1 Channel CCxE bit new state.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_CCxCmd(u16 TIM1_Channel, FunctionalState Newstate)
+{
+ /* Check the parameters */
+ assert(IS_TIM1_CHANNEL(TIM1_Channel));
+ assert(IS_FUNCTIONAL_STATE(Newstate));
+
+ if(TIM1_Channel == TIM1_Channel_1)
+ {
+ /* Set or Reset the CC1E Bit */
+ *(vu32 *) CCER_CC1E_BB = (u16)Newstate;
+ }
+ else if(TIM1_Channel == TIM1_Channel_2)
+ {
+ /* Set or Reset the CC2E Bit */
+ *(vu32 *) CCER_CC2E_BB = (u16)Newstate;
+ }
+ else if(TIM1_Channel == TIM1_Channel_3)
+ {
+ /* Set or Reset the CC3E Bit */
+ *(vu32 *) CCER_CC3E_BB = (u16)Newstate;
+ }
+ else
+ {
+ /* Set or Reset the CC4E Bit */
+ *(vu32 *) CCER_CC4E_BB = (u16)Newstate;
+ }
+}
+
+/*******************************************************************************
+* Function Name : TIM1_CCxNCmd
+* Description : Enables or disables the TIM1 Capture Compare Channel xN.
+* Input : - TIM1_Channel: specifies the TIM1 Channel
+* This parmeter can be one of the following values:
+* - TIM1_Channel1: TIM1 Channel1
+* - TIM1_Channel2: TIM1 Channel2
+* - TIM1_Channel3: TIM1 Channel3
+* - Newstate: specifies the TIM1 Channel CCxNE bit new state.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_CCxNCmd(u16 TIM1_Channel, FunctionalState Newstate)
+{
+ /* Check the parameters */
+ assert(IS_TIM1_COMPLEMENTARY_CHANNEL(TIM1_Channel));
+ assert(IS_FUNCTIONAL_STATE(Newstate));
+
+ if(TIM1_Channel == TIM1_Channel_1)
+ {
+ /* Set or Reset the CC1NE Bit */
+ *(vu32 *) CCER_CC1NE_BB = (u16)Newstate;
+ }
+ else if(TIM1_Channel == TIM1_Channel_2)
+ {
+ /* Set or Reset the CC2NE Bit */
+ *(vu32 *) CCER_CC2NE_BB = (u16)Newstate;
+ }
+ else
+ {
+ /* Set or Reset the CC3NE Bit */
+ *(vu32 *) CCER_CC3NE_BB = (u16)Newstate;
+ }
+}
+
+/*******************************************************************************
+* Function Name : TIM1_SelectOCxM
+* Description : Selects the TIM1 Ouput Compare Mode.
+* This function disables the selected channel before changing
+* the Ouput Compare Mode. User has to enable this channel using
+* TIM1_CCxCmd and TIM1_CCxNCmd functions.
+* Input : - TIM1_Channel: specifies the TIM1 Channel
+* This parmeter can be one of the following values:
+* - TIM1_Channel1: TIM1 Channel1
+* - TIM1_Channel2: TIM1 Channel2
+* - TIM1_Channel3: TIM1 Channel3
+* - TIM1_Channel4: TIM1 Channel4
+* - TIM1_OCMode: specifies the TIM1 Output Compare Mode.
+* This paramter can be one of the following values:
+* - TIM1_OCMode_Timing
+* - TIM1_OCMode_Active
+* - TIM1_OCMode_Toggle
+* - TIM1_OCMode_PWM1
+* - TIM1_OCMode_PWM2
+* - TIM1_ForcedAction_Active
+* - TIM1_ForcedAction_InActive
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_SelectOCxM(u16 TIM1_Channel, u16 TIM1_OCMode)
+{
+ /* Check the parameters */
+ assert(IS_TIM1_CHANNEL(TIM1_Channel));
+ assert(IS_TIM1_OCM(TIM1_OCMode));
+
+ if(TIM1_Channel == TIM1_Channel_1)
+ {
+ /* Disable the Channel 1: Reset the CCE Bit */
+ *(vu32 *) CCER_CC1E_BB = CCER_CCE_Reset;
+
+ /* Reset the Output Compare Bits */
+ TIM1->CCMR1 &= OC13Mode_Mask;
+
+ /* Set the Ouput Compare Mode */
+ TIM1->CCMR1 |= TIM1_OCMode;
+ }
+ else if(TIM1_Channel == TIM1_Channel_2)
+ {
+ /* Disable the Channel 2: Reset the CCE Bit */
+ *(vu32 *) CCER_CC2E_BB = CCER_CCE_Reset;
+
+ /* Reset the Output Compare Bits */
+ TIM1->CCMR1 &= OC24Mode_Mask;
+
+ /* Set the Ouput Compare Mode */
+ TIM1->CCMR1 |= (u16)((u16)TIM1_OCMode << 8);
+ }
+ else if(TIM1_Channel == TIM1_Channel_3)
+ {
+ /* Disable the Channel 3: Reset the CCE Bit */
+ *(vu32 *) CCER_CC3E_BB = CCER_CCE_Reset;
+
+ /* Reset the Output Compare Bits */
+ TIM1->CCMR2 &= OC13Mode_Mask;
+
+ /* Set the Ouput Compare Mode */
+ TIM1->CCMR2 |= TIM1_OCMode;
+ }
+ else
+ {
+ /* Disable the Channel 4: Reset the CCE Bit */
+ *(vu32 *) CCER_CC4E_BB = CCER_CCE_Reset;
+
+ /* Reset the Output Compare Bits */
+ TIM1->CCMR2 &= OC24Mode_Mask;
+
+ /* Set the Ouput Compare Mode */
+ TIM1->CCMR2 |= (u16)((u16)TIM1_OCMode << 8);
+ }
+}
+
+/*******************************************************************************
+* Function Name : TIM1_SetAutoreload
+* Description : Sets the TIM1 Autoreload Register value.
+* Input : - Autoreload: specifies the Autoreload register new value.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_SetAutoreload(u16 Autoreload)
+{
+ /* Set the Autoreload Register value */
+ TIM1->ARR = Autoreload;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_SetCompare1
+* Description : Sets the TIM1 Capture Compare1 Register value.
+* Input : - Compare1: specifies the Capture Compare1 register new value.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_SetCompare1(u16 Compare1)
+{
+ /* Set the Capture Compare1 Register value */
+ TIM1->CCR1 = Compare1;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_SetCompare2
+* Description : Sets the TIM1 Capture Compare2 Register value.
+* Input : - Compare2: specifies the Capture Compare2 register new value.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_SetCompare2(u16 Compare2)
+{
+ /* Set the Capture Compare2 Register value */
+ TIM1->CCR2 = Compare2;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_SetCompare3
+* Description : Sets the TIM1 Capture Compare3 Register value.
+* Input : - Compare3: specifies the Capture Compare3 register new value.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_SetCompare3(u16 Compare3)
+{
+ /* Set the Capture Compare3 Register value */
+ TIM1->CCR3 = Compare3;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_SetCompare4
+* Description : Sets the TIM1 Capture Compare4 Register value.
+* Input : - Compare4: specifies the Capture Compare4 register new value.
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_SetCompare4(u16 Compare4)
+{
+ /* Set the Capture Compare4 Register value */
+ TIM1->CCR4 = Compare4;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_SetIC1Prescaler
+* Description : Sets the TIM1 Input Capture 1 prescaler.
+* Input : - TIM1_IC1Prescaler: specifies the Input Capture prescaler
+* new value.
+* This parameter can be one of the following values:
+* - TIM1_ICPSC_DIV1: no prescaler
+* - TIM1_ICPSC_DIV2: capture is done once every 2 events
+* - TIM1_ICPSC_DIV4: capture is done once every 4 events
+* - TIM1_ICPSC_DIV8: capture is done once every 8 events
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_SetIC1Prescaler(u16 TIM1_IC1Prescaler)
+{
+ u32 tmpccmr1 = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM1_IC_PRESCALER(TIM1_IC1Prescaler));
+
+ tmpccmr1 = TIM1->CCMR1;
+
+ /* Reset the IC1PSC Bits */
+ tmpccmr1 &= CCMR_IC13PSC_Mask;
+
+ /* Set the IC1PSC value */
+ tmpccmr1 |= TIM1_IC1Prescaler;
+
+ TIM1->CCMR1 = (u16)tmpccmr1;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_SetIC2Prescaler
+* Description : Sets the TIM1 Input Capture 2 prescaler.
+* Input : - TIM1_IC2Prescaler: specifies the Input Capture prescaler
+* new value.
+* This parameter can be one of the following values:
+* - TIM1_ICPSC_DIV1: no prescaler
+* - TIM1_ICPSC_DIV2: capture is done once every 2 events
+* - TIM1_ICPSC_DIV4: capture is done once every 4 events
+* - TIM1_ICPSC_DIV8: capture is done once every 8 events
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_SetIC2Prescaler(u16 TIM1_IC2Prescaler)
+{
+ u32 tmpccmr1 = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM1_IC_PRESCALER(TIM1_IC2Prescaler));
+
+ tmpccmr1 = TIM1->CCMR1;
+
+ /* Reset the IC2PSC Bits */
+ tmpccmr1 &= CCMR_IC24PSC_Mask;
+
+ /* Set the IC2PSC value */
+ tmpccmr1 |= (u16)((u16)TIM1_IC2Prescaler << 8);
+
+ TIM1->CCMR1 = (u16)tmpccmr1;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_SetIC3Prescaler
+* Description : Sets the TIM1 Input Capture 3 prescaler.
+* Input : - TIM1_IC3Prescaler: specifies the Input Capture prescaler
+* new value.
+* This parameter can be one of the following values:
+* - TIM1_ICPSC_DIV1: no prescaler
+* - TIM1_ICPSC_DIV2: capture is done once every 2 events
+* - TIM1_ICPSC_DIV4: capture is done once every 4 events
+* - TIM1_ICPSC_DIV8: capture is done once every 8 events
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_SetIC3Prescaler(u16 TIM1_IC3Prescaler)
+{
+ u32 tmpccmr2 = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM1_IC_PRESCALER(TIM1_IC3Prescaler));
+
+ tmpccmr2 = TIM1->CCMR2;
+
+ /* Reset the IC3PSC Bits */
+ tmpccmr2 &= CCMR_IC13PSC_Mask;
+
+ /* Set the IC3PSC value */
+ tmpccmr2 |= TIM1_IC3Prescaler;
+
+ TIM1->CCMR2 = (u16)tmpccmr2;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_SetIC4Prescaler
+* Description : Sets the TIM1 Input Capture 4 prescaler.
+* Input : - TIM1_IC4Prescaler: specifies the Input Capture prescaler
+* new value.
+* This parameter can be one of the following values:
+* - TIM1_ICPSC_DIV1: no prescaler
+* - TIM1_ICPSC_DIV2: capture is done once every 2 events
+* - TIM1_ICPSC_DIV4: capture is done once every 4 events
+* - TIM1_ICPSC_DIV8: capture is done once every 8 events
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_SetIC4Prescaler(u16 TIM1_IC4Prescaler)
+{
+ u32 tmpccmr2 = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM1_IC_PRESCALER(TIM1_IC4Prescaler));
+
+ tmpccmr2 = TIM1->CCMR2;
+
+ /* Reset the IC4PSC Bits */
+ tmpccmr2 &= CCMR_IC24PSC_Mask;
+
+ /* Set the IC4PSC value */
+ tmpccmr2 |= (u16)((u16)TIM1_IC4Prescaler << 8);
+
+ TIM1->CCMR2 = (u16)tmpccmr2;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_SetClockDivision
+* Description : Sets the TIM1 Clock Division value.
+* Input : - TIM1_CKD: specifies the clock division value.
+* This parameter can be one of the following value:
+* - TIM1_CKD_DIV1: TDTS = Tck_tim
+* - TIM1_CKD_DIV2: TDTS = 2*Tck_tim
+* - TIM1_CKD_DIV4: TDTS = 4*Tck_tim
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_SetClockDivision(u16 TIM1_CKD)
+{
+ u32 tmpcr1 = 0;
+
+ /* Check the parameters */
+ assert(IS_TIM1_CKD_DIV(TIM1_CKD));
+
+ tmpcr1 = TIM1->CR1;
+
+ /* Reset the CKD Bits */
+ tmpcr1 &= CR1_CKD_Mask;
+
+ /* Set the CKD value */
+ tmpcr1 |= TIM1_CKD;
+
+ TIM1->CR1 = (u16)tmpcr1;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_GetCapture1
+* Description : Gets the TIM1 Input Capture 1 value.
+* Input : None
+* Output : None
+* Return : Capture Compare 1 Register value.
+*******************************************************************************/
+u16 TIM1_GetCapture1(void)
+{
+ /* Get the Capture 1 Register value */
+ return TIM1->CCR1;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_GetCapture2
+* Description : Gets the TIM1 Input Capture 2 value.
+* Input : None
+* Output : None
+* Return : Capture Compare 2 Register value.
+*******************************************************************************/
+u16 TIM1_GetCapture2(void)
+{
+ /* Get the Capture 2 Register value */
+ return TIM1->CCR2;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_GetCapture3
+* Description : Gets the TIM1 Input Capture 3 value.
+* Input : None
+* Output : None
+* Return : Capture Compare 3 Register value.
+*******************************************************************************/
+u16 TIM1_GetCapture3(void)
+{
+ /* Get the Capture 3 Register value */
+ return TIM1->CCR3;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_GetCapture4
+* Description : Gets the TIM1 Input Capture 4 value.
+* Input : None
+* Output : None
+* Return : Capture Compare 4 Register value.
+*******************************************************************************/
+u16 TIM1_GetCapture4(void)
+{
+ /* Get the Capture 4 Register value */
+ return TIM1->CCR4;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_GetCounter
+* Description : Gets the TIM1 Counter value.
+* Input : None
+* Output : None
+* Return : Counter Register value.
+*******************************************************************************/
+u16 TIM1_GetCounter(void)
+{
+ /* Get the Counter Register value */
+ return TIM1->CNT;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_GetPrescaler
+* Description : Gets the TIM1 Prescaler value.
+* Input : None
+* Output : None
+* Return : Prescaler Register value.
+*******************************************************************************/
+u16 TIM1_GetPrescaler(void)
+{
+ /* Get the Prescaler Register value */
+ return TIM1->PSC;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_GetFlagStatus
+* Description : Checks whether the specified TIM1 flag is set or not.
+* Input : - TIM1_FLAG: specifies the flag to check.
+* This parameter can be one of the following values:
+* - TIM1_FLAG_Update: TIM1 update Flag
+* - TIM1_FLAG_CC1: TIM1 Capture Compare 1 Flag
+* - TIM1_FLAG_CC2: TIM1 Capture Compare 2 Flag
+* - TIM1_FLAG_CC3: TIM1 Capture Compare 3 Flag
+* - TIM1_FLAG_CC4: TIM1 Capture Compare 4 Flag
+* - TIM1_FLAG_COM: TIM1 Commutation Flag
+* - TIM1_FLAG_Trigger: TIM1 Trigger Flag
+* - TIM1_FLAG_Break: TIM1 Break Flag
+* - TIM1_FLAG_CC1OF: TIM1 Capture Compare 1 overcapture Flag
+* - TIM1_FLAG_CC2OF: TIM1 Capture Compare 2 overcapture Flag
+* - TIM1_FLAG_CC3OF: TIM1 Capture Compare 3 overcapture Flag
+* - TIM1_FLAG_CC4OF: TIM1 Capture Compare 4 overcapture Flag
+* Output : None
+* Return : The new state of TIM1_FLAG (SET or RESET).
+*******************************************************************************/
+FlagStatus TIM1_GetFlagStatus(u16 TIM1_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert(IS_TIM1_GET_FLAG(TIM1_FLAG));
+
+ if ((TIM1->SR & TIM1_FLAG) != (u16)RESET )
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_ClearFlag
+* Description : Clears the TIM1s pending flags.
+* Input : - TIM1_FLAG: specifies the flag to clear.
+* This parameter can be any combination of the following values:
+* - TIM1_FLAG_Update: TIM1 update Flag
+* - TIM1_FLAG_CC1: TIM1 Capture Compare 1 Flag
+* - TIM1_FLAG_CC2: TIM1 Capture Compare 2 Flag
+* - TIM1_FLAG_CC3: TIM1 Capture Compare 3 Flag
+* - TIM1_FLAG_CC4: TIM1 Capture Compare 4 Flag
+* - TIM1_FLAG_COM: TIM1 Commutation Flag
+* - TIM1_FLAG_Trigger: TIM1 Trigger Flag
+* - TIM1_FLAG_Break: TIM1 Break Flag
+* - TIM1_FLAG_CC1OF: TIM1 Capture Compare 1 overcapture Flag
+* - TIM1_FLAG_CC2OF: TIM1 Capture Compare 2 overcapture Flag
+* - TIM1_FLAG_CC3OF: TIM1 Capture Compare 3 overcapture Flag
+* - TIM1_FLAG_CC4OF: TIM1 Capture Compare 4 overcapture Flag
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_ClearFlag(u16 TIM1_FLAG)
+{
+ /* Check the parameters */
+ assert(IS_TIM1_CLEAR_FLAG(TIM1_FLAG));
+
+ /* Clear the flags */
+ TIM1->SR &= (u16)~TIM1_FLAG;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_GetITStatus
+* Description : Checks whether the TIM1 interrupt has occurred or not.
+* Input : - TIM1_IT: specifies the TIM1 interrupt source to check.
+* This parameter can be one of the following values:
+* - TIM1_IT_Update: TIM1 update Interrupt source
+* - TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source
+* - TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source
+* - TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source
+* - TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source
+* - TIM1_IT_COM: TIM1 Commutation Interrupt
+* source
+* - TIM1_IT_Trigger: TIM1 Trigger Interrupt source
+* - TIM1_IT_Break: TIM1 Break Interrupt source
+* Output : None
+* Return : The new state of the TIM1_IT(SET or RESET).
+*******************************************************************************/
+ITStatus TIM1_GetITStatus(u16 TIM1_IT)
+{
+ ITStatus bitstatus = RESET;
+
+ u16 TIM1_itStatus = 0x0, TIM1_itEnable = 0x0;
+
+ /* Check the parameters */
+ assert(IS_TIM1_GET_IT(TIM1_IT));
+
+ TIM1_itStatus = TIM1->SR & TIM1_IT;
+
+ TIM1_itEnable = TIM1->DIER & TIM1_IT;
+
+ if ((TIM1_itStatus != (u16)RESET ) && (TIM1_itEnable != (u16)RESET ))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name : TIM1_ClearITPendingBit
+* Description : Clears the TIM1's interrupt pending bits.
+* Input : - TIM1_IT: specifies the pending bit to clear.
+* This parameter can be any combination of the following values:
+* - TIM1_IT_Update: TIM1 update Interrupt source
+* - TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source
+* - TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source
+* - TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source
+* - TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source
+* - TIM1_IT_COM: TIM1 Commutation Interrupt
+* source
+* - TIM1_IT_Trigger: TIM1 Trigger Interrupt source
+* - TIM1_IT_Break: TIM1 Break Interrupt source
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_ClearITPendingBit(u16 TIM1_IT)
+{
+ /* Check the parameters */
+ assert(IS_TIM1_IT(TIM1_IT));
+
+ /* Clear the IT pending Bit */
+ TIM1->SR &= (u16)~TIM1_IT;
+}
+
+/*******************************************************************************
+* Function Name : TI1_Config
+* Description : Configure the TI1 as Input.
+* Input : - TIM1_ICPolarity : The Input Polarity.
+* This parameter can be one of the following values:
+* - TIM1_ICPolarity_Rising
+* - TIM1_ICPolarity_Falling
+* - TIM1_ICSelection: specifies the input to be used.
+* This parameter can be one of the following values:
+* - TIM1_ICSelection_DirectTI: TIM1 Input 1 is selected to
+* be connected to IC1.
+* - TIM1_ICSelection_IndirectTI: TIM1 Input 1 is selected to
+* be connected to IC2.
+* - TIM1_ICSelection_TRGI:TIM1 Input 1 is selected to be
+* connected to TRGI.
+* - TIM1_ICFilter: Specifies the Input Capture Filter.
+* This parameter must be a value between 0x00 and 0x0F.
+* Output : None
+* Return : None
+*******************************************************************************/
+static void TI1_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection,
+ u8 TIM1_ICFilter)
+{
+ u32 tmpccmr1 = 0;
+
+ tmpccmr1 = TIM1->CCMR1;
+
+ /* Disable the Channel 1: Reset the CCE Bit */
+ *(vu32 *) CCER_CC1E_BB = CCER_CCE_Reset;
+
+ /* Select the Input and set the filter */
+ tmpccmr1 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask;
+ tmpccmr1 |= (u16)TIM1_ICSelection | (u16)((u16)TIM1_ICFilter << 4);
+
+ TIM1->CCMR1 = (u16)tmpccmr1;
+
+ /* Select the Polarity */
+ *(vu32 *) CCER_CC1P_BB = TIM1_ICPolarity;
+
+ /* Set the CCE Bit */
+ *(vu32 *) CCER_CC1E_BB = CCER_CCE_Set;
+}
+
+/*******************************************************************************
+* Function Name : TI2_Config
+* Description : Configure the TI2 as Input.
+* Input : - TIM1_ICPolarity : The Input Polarity.
+* This parameter can be one of the following values:
+* - TIM1_ICPolarity_Rising
+* - TIM1_ICPolarity_Falling
+* - TIM1_ICSelection: specifies the input to be used.
+* This parameter can be one of the following values:
+* - TIM1_ICSelection_DirectTI: TIM1 Input 2 is selected to
+* be connected to IC2.
+* - TIM1_ICSelection_IndirectTI: TIM1 Input 2 is selected to
+* be connected to IC1.
+* - TIM1_ICSelection_TRGI: TIM1 Input 2 is selected to be
+* connected to TRGI.
+* - TIM1_ICFilter: Specifies the Input Capture Filter.
+* This parameter must be a value between 0x00 and 0x0F.
+* Output : None
+* Return : None
+*******************************************************************************/
+static void TI2_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection,
+ u8 TIM1_ICFilter)
+{
+ u32 tmpccmr1 = 0;
+
+ tmpccmr1 = TIM1->CCMR1;
+
+ /* Disable the Channel 2: Reset the CCE Bit */
+ *(vu32 *) CCER_CC2E_BB = CCER_CCE_Reset;
+
+ /* Select the Input and set the filter */
+ tmpccmr1 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask;
+ tmpccmr1 |= (u16)((u16)TIM1_ICSelection << 8) | (u16)((u16)TIM1_ICFilter <<12);
+
+ TIM1->CCMR1 = (u16)tmpccmr1;
+
+ /* Select the Polarity */
+ *(vu32 *) CCER_CC2P_BB = TIM1_ICPolarity;
+
+ /* Set the CCE Bit */
+ *(vu32 *) CCER_CC2E_BB = CCER_CCE_Set;
+
+}
+
+/*******************************************************************************
+* Function Name : TI3_Config
+* Description : Configure the TI3 as Input.
+* Input : - TIM1_ICPolarity : The Input Polarity.
+* This parameter can be one of the following values:
+* - TIM1_ICPolarity_Rising
+* - TIM1_ICPolarity_Falling
+* - TIM1_ICSelection: specifies the input to be used.
+* This parameter can be one of the following values:
+* - TIM1_ICSelection_DirectTI: TIM1 Input 3 is selected to
+* be connected to IC3.
+* - TIM1_ICSelection_IndirectTI: TIM1 Input 3 is selected to
+* be connected to IC4.
+* - TIM1_ICSelection_TRGI: TIM1 Input 3 is selected to be
+* connected to TRGI.
+* - TIM1_ICFilter: Specifies the Input Capture Filter.
+* This parameter must be a value between 0x00 and 0x0F.
+* Output : None
+* Return : None
+*******************************************************************************/
+static void TI3_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection,
+ u8 TIM1_ICFilter)
+{
+ u32 tmpccmr2 = 0;
+
+ tmpccmr2 = TIM1->CCMR2;
+
+ /* Disable the Channel 3: Reset the CCE Bit */
+ *(vu32 *) CCER_CC3E_BB = CCER_CCE_Reset;
+
+ /* Select the Input and set the filter */
+ tmpccmr2 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask;
+ tmpccmr2 |= (u16)TIM1_ICSelection | (u16)((u16)TIM1_ICFilter << 4);
+
+ TIM1->CCMR2 = (u16)tmpccmr2;
+
+ /* Select the Polarity */
+ *(vu32 *) CCER_CC3P_BB = TIM1_ICPolarity;
+
+ /* Set the CCE Bit */
+ *(vu32 *) CCER_CC3E_BB = CCER_CCE_Set;
+}
+
+/*******************************************************************************
+* Function Name : TI4_Config
+* Description : Configure the TI4 as Input.
+* Input : - TIM1_ICPolarity : The Input Polarity.
+* This parameter can be one of the following values:
+* - TIM1_ICPolarity_Rising
+* - TIM1_ICPolarity_Falling
+* - TIM1_ICSelection: specifies the input to be used.
+* This parameter can be one of the following values:
+* - TIM1_ICSelection_DirectTI: TIM1 Input 4 is selected to
+* be connected to IC4.
+* - TIM1_ICSelection_IndirectTI: TIM1 Input 4 is selected to
+* be connected to IC3.
+* - TIM1_ICSelection_TRGI: TIM1 Input 4 is selected to be
+* connected to TRGI.
+* - TIM1_ICFilter: Specifies the Input Capture Filter.
+* This parameter must be a value between 0x00 and 0x0F.
+* Output : None
+* Return : None
+*******************************************************************************/
+static void TI4_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection,
+ u8 TIM1_ICFilter)
+{
+ u32 tmpccmr2 = 0;
+
+ tmpccmr2 = TIM1->CCMR2;
+
+ /* Disable the Channel 4: Reset the CCE Bit */
+ *(vu32 *) CCER_CC4E_BB = CCER_CCE_Reset;
+
+ /* Select the Input and set the filter */
+ tmpccmr2 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask;
+ tmpccmr2 |= (u16)((u16)TIM1_ICSelection << 8) | (u16)((u16)TIM1_ICFilter << 12);
+
+ TIM1->CCMR2 = (u16)tmpccmr2;
+
+ /* Select the Polarity */
+ *(vu32 *) CCER_CC4P_BB = TIM1_ICPolarity;
+
+ /* Set the CCE Bit */
+ *(vu32 *) CCER_CC4E_BB = CCER_CCE_Set;
+}
+
+/*******************************************************************************
+* Function Name : ETR_Config
+* Description : Configure the External Trigger
+* Input : - TIM1_ExtTRGPrescaler: The external Trigger Prescaler.
+* This parameter can be one of the following values:
+* - TIM1_ExtTRGPSC_OFF
+* - TIM1_ExtTRGPSC_DIV2
+* - TIM1_ExtTRGPSC_DIV4
+* - TIM1_ExtTRGPSC_DIV8
+* - TIM1_ExtTRGPolarity: The external Trigger Polarity.
+* This parameter can be one of the following values:
+* - TIM1_ExtTRGPolarity_Inverted
+* - TIM1_ExtTRGPolarity_NonInverted
+* - ExtTRGFilter: External Trigger Filter.
+* This parameter must be a value between 0x00 and 0x0F.
+* Output : None
+* Return : None
+*******************************************************************************/
+static void ETR_Config(u16 TIM1_ExtTRGPrescaler, u16 TIM1_ExtTRGPolarity,
+ u16 ExtTRGFilter)
+{
+ u32 tmpsmcr = 0;
+
+ tmpsmcr = TIM1->SMCR;
+
+ /* Set the Prescaler, the Filter value and the Polarity */
+ tmpsmcr &= SMCR_ETR_Mask;
+ tmpsmcr |= TIM1_ExtTRGPrescaler | TIM1_ExtTRGPolarity | (u16)((u16)ExtTRGFilter << 8);
+
+ TIM1->SMCR = (u16)tmpsmcr;
+}
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_usart.c b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_usart.c
new file mode 100644
index 0000000..7bc288a
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_usart.c
@@ -0,0 +1,852 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_usart.c
+* Author : MCD Application Team
+* Date First Issued : 09/29/2006
+* Description : This file provides all the USART firmware functions.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_usart.h"
+#include "stm32f10x_rcc.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* USART RUN Mask */
+#define CR1_RUN_Set ((u16)0x2000) /* USART Enable Mask */
+#define CR1_RUN_Reset ((u16)0xDFFF) /* USART Disable Mask */
+
+#define CR2_Address_Mask ((u16)0xFFF0) /* USART address Mask */
+
+/* USART RWU Mask */
+#define CR1_RWU_Set ((u16)0x0002) /* USART mute mode Enable Mask */
+#define CR1_RWU_Reset ((u16)0xFFFD) /* USART mute mode Enable Mask */
+
+#define USART_IT_Mask ((u16)0x001F) /* USART Interrupt Mask */
+
+/* USART LIN Mask */
+#define CR2_LINE_Set ((u16)0x4000) /* USART LIN Enable Mask */
+#define CR2_LINE_Reset ((u16)0xBFFF) /* USART LIN Disable Mask */
+
+#define CR1_SBK_Set ((u16)0x0001) /* USART Break Character send Mask */
+
+/* USART SC Mask */
+#define CR3_SCEN_Set ((u16)0x0020) /* USART SC Enable Mask */
+#define CR3_SCEN_Reset ((u16)0xFFDF) /* USART SC Disable Mask */
+
+/* USART SC NACK Mask */
+#define CR3_NACK_Set ((u16)0x0010) /* USART SC NACK Enable Mask */
+#define CR3_NACK_Reset ((u16)0xFFEF) /* USART SC NACK Disable Mask */
+
+/* USART Half-Duplex Mask */
+#define CR3_HDSEL_Set ((u16)0x0008) /* USART Half-Duplex Enable Mask */
+#define CR3_HDSEL_Reset ((u16)0xFFF7) /* USART Half-Duplex Disable Mask */
+
+/* USART IrDA Mask */
+#define CR3_IRLP_Mask ((u16)0xFFFB) /* USART IrDA LowPower mode Mask */
+
+/* USART LIN Break detection */
+#define CR3_LBDL_Mask ((u16)0xFFDF) /* USART LIN Break detection Mask */
+
+/* USART WakeUp Method */
+#define CR3_WAKE_Mask ((u16)0xF7FF) /* USART WakeUp Method Mask */
+
+/* USART IrDA Mask */
+#define CR3_IREN_Set ((u16)0x0002) /* USART IrDA Enable Mask */
+#define CR3_IREN_Reset ((u16)0xFFFD) /* USART IrDA Disable Mask */
+
+#define GTPR_LSB_Mask ((u16)0x00FF) /* Guard Time Register LSB Mask */
+#define GTPR_MSB_Mask ((u16)0xFF00) /* Guard Time Register MSB Mask */
+
+#define CR1_CLEAR_Mask ((u16)0xE9F3) /* USART CR1 Mask */
+#define CR2_CLEAR_Mask ((u16)0xC0FF) /* USART CR2 Mask */
+#define CR3_CLEAR_Mask ((u16)0xFCFF) /* USART CR3 Mask */
+
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name : USART_DeInit
+* Description : Deinitializes the USARTx peripheral registers to their
+* default reset values.
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART
+* peripheral.
+* Output : None
+* Return : None
+*******************************************************************************/
+void USART_DeInit(USART_TypeDef* USARTx)
+{
+ switch (*(u32*)&USARTx)
+ {
+ case USART1_BASE:
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
+ break;
+
+ case USART2_BASE:
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
+ break;
+
+ case USART3_BASE:
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name : USART_Init
+* Description : Initializes the USARTx peripheral according to the specified
+* parameters in the USART_InitStruct .
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART peripheral.
+* - USART_InitStruct: pointer to a USART_InitTypeDef structure
+* that contains the configuration information for the
+* specified USART peripheral.
+* Output : None
+* Return : None
+*******************************************************************************/
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
+{
+ u32 tmpreg = 0x00, apbclock = 0x00;
+ u32 integerdivider = 0x00;
+ u32 fractionaldivider = 0x00;
+ RCC_ClocksTypeDef RCC_ClocksStatus;
+
+ /* Check the parameters */
+ assert(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));
+ assert(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));
+ assert(IS_USART_PARITY(USART_InitStruct->USART_Parity));
+ assert(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));
+ assert(IS_USART_MODE(USART_InitStruct->USART_Mode));
+ assert(IS_USART_CLOCK(USART_InitStruct->USART_Clock));
+ assert(IS_USART_CPOL(USART_InitStruct->USART_CPOL));
+ assert(IS_USART_CPHA(USART_InitStruct->USART_CPHA));
+ assert(IS_USART_LASTBIT(USART_InitStruct->USART_LastBit));
+
+/*---------------------------- USART CR2 Configuration -----------------------*/
+ tmpreg = USARTx->CR2;
+ /* Clear STOP[13:12], CLKEN, CPOL, CPHA and LBCL bits */
+ tmpreg &= CR2_CLEAR_Mask;
+
+ /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/
+ /* Set STOP[13:12] bits according to USART_Mode value */
+ /* Set CPOL bit according to USART_CPOL value */
+ /* Set CPHA bit according to USART_CPHA value */
+ /* Set LBCL bit according to USART_LastBit value */
+ tmpreg |= (u32)USART_InitStruct->USART_StopBits | USART_InitStruct->USART_Clock |
+ USART_InitStruct->USART_CPOL | USART_InitStruct->USART_CPHA |
+ USART_InitStruct->USART_LastBit;
+
+ /* Write to USART CR2 */
+ USARTx->CR2 = (u16)tmpreg;
+
+/*---------------------------- USART CR1 Configuration -----------------------*/
+ tmpreg = 0x00;
+ tmpreg = USARTx->CR1;
+ /* Clear M, PCE, PS, TE and RE bits */
+ tmpreg &= CR1_CLEAR_Mask;
+
+ /* Configure the USART Word Length, Parity and mode ----------------------- */
+ /* Set the M bits according to USART_WordLength value */
+ /* Set PCE and PS bits according to USART_Parity value */
+ /* Set TE and RE bits according to USART_Mode value */
+ tmpreg |= (u32)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
+ USART_InitStruct->USART_Mode;
+
+ /* Write to USART CR1 */
+ USARTx->CR1 = (u16)tmpreg;
+
+/*---------------------------- USART CR3 Configuration -----------------------*/
+ tmpreg = 0x00;
+ tmpreg = USARTx->CR3;
+ /* Clear CTSE and RTSE bits */
+ tmpreg &= CR3_CLEAR_Mask;
+
+ /* Configure the USART HFC -------------------------------------------------*/
+ /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */
+ tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
+
+ /* Write to USART CR3 */
+ USARTx->CR3 = (u16)tmpreg;
+
+/*---------------------------- USART BRR Configuration -----------------------*/
+ tmpreg = 0x00;
+
+ /* Configure the USART Baud Rate -------------------------------------------*/
+ RCC_GetClocksFreq(&RCC_ClocksStatus);
+ if ((*(u32*)&USARTx) == USART1_BASE)
+ {
+ apbclock = RCC_ClocksStatus.PCLK2_Frequency;
+ }
+ else
+ {
+ apbclock = RCC_ClocksStatus.PCLK1_Frequency;
+ }
+
+ /* Determine the integer part */
+ integerdivider = ((0x19 * apbclock) / (0x04 * (USART_InitStruct->USART_BaudRate)));
+ tmpreg = (integerdivider / 0x64) << 0x04;
+
+ /* Determine the fractional part */
+ fractionaldivider = integerdivider - (0x64 * (tmpreg >> 0x04));
+ tmpreg |= ((((fractionaldivider * 0x10) + 0x32) / 0x64)) & ((u8)0x0F);
+
+ /* Write to USART BRR */
+ USARTx->BRR = (u16)tmpreg;
+}
+
+/*******************************************************************************
+* Function Name : USART_StructInit
+* Description : Fills each USART_InitStruct member with its default value.
+* Input : - USART_InitStruct: pointer to a USART_InitTypeDef structure
+* which will be initialized.
+* Output : None
+* Return : None
+*******************************************************************************/
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct)
+{
+ /* USART_InitStruct members default value */
+ USART_InitStruct->USART_BaudRate = 0x2580; /* 9600 Baud */
+ USART_InitStruct->USART_WordLength = USART_WordLength_8b;
+ USART_InitStruct->USART_StopBits = USART_StopBits_1;
+ USART_InitStruct->USART_Parity = USART_Parity_No ;
+ USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+ USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+ USART_InitStruct->USART_Clock = USART_Clock_Disable;
+ USART_InitStruct->USART_CPOL = USART_CPOL_Low;
+ USART_InitStruct->USART_CPHA = USART_CPHA_1Edge;
+ USART_InitStruct->USART_LastBit = USART_LastBit_Disable;
+}
+
+/*******************************************************************************
+* Function Name : USART_Cmd
+* Description : Enables or disables the specified USART peripheral.
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART
+* peripheral.
+* : - NewState: new state of the USARTx peripheral.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected USART by setting the RUN bit in the CR1 register */
+ USARTx->CR1 |= CR1_RUN_Set;
+ }
+ else
+ {
+ /* Disable the selected USART by clearing the RUN bit in the CR1 register */
+ USARTx->CR1 &= CR1_RUN_Reset;
+ }
+}
+
+/*******************************************************************************
+* Function Name : USART_ITConfig
+* Description : Enables or disables the specified USART interrupts.
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART
+* peripheral.
+* - USART_IT: specifies the USART interrupt sources to be
+* enabled or disabled.
+* This parameter can be one of the following values:
+* - USART_IT_PE
+* - USART_IT_TXE
+* - USART_IT_TC
+* - USART_IT_RXNE
+* - USART_IT_IDLE
+* - USART_IT_LBD
+* - USART_IT_CTS
+* - USART_IT_ERR
+* - NewState: new state of the specified USARTx interrupts.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void USART_ITConfig(USART_TypeDef* USARTx, u16 USART_IT, FunctionalState NewState)
+{
+ u32 usartreg = 0x00, itpos = 0x00, itmask = 0x00;
+ u32 address = 0x00;
+
+ /* Check the parameters */
+ assert(IS_USART_CONFIG_IT(USART_IT));
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ /* Get the USART register index */
+ usartreg = (((u8)USART_IT) >> 0x05);
+
+ /* Get the interrupt position */
+ itpos = USART_IT & USART_IT_Mask;
+
+ itmask = (((u32)0x01) << itpos);
+ address = *(u32*)&(USARTx);
+
+ if (usartreg == 0x01) /* The IT is in CR1 register */
+ {
+ address += 0x0C;
+ }
+ else if (usartreg == 0x02) /* The IT is in CR2 register */
+ {
+ address += 0x10;
+ }
+ else /* The IT is in CR3 register */
+ {
+ address += 0x14;
+ }
+ if (NewState != DISABLE)
+ {
+ *(u32*)address |= itmask;
+ }
+ else
+ {
+ *(u32*)address &= ~itmask;
+ }
+}
+
+/*******************************************************************************
+* Function Name : USART_DMACmd
+* Description : Enables or disables the USARTs DMA interface.
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART
+* peripheral.
+* - USART_DMAReq: specifies the DMA request.
+* This parameter can be any combination of the following values:
+* - USART_DMAReq_Tx
+* - USART_DMAReq_Rx
+* - NewState: new state of the DMA Request sources.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void USART_DMACmd(USART_TypeDef* USARTx, u16 USART_DMAReq, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_USART_DMAREQ(USART_DMAReq));
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the DMA transfer for selected requests by setting the DMAT and/or
+ DMAR bits in the USART CR3 register */
+ USARTx->CR3 |= USART_DMAReq;
+ }
+ else
+ {
+ /* Disable the DMA transfer for selected requests by clearing the DMAT and/or
+ DMAR bits in the USART CR3 register */
+ USARTx->CR3 &= (u16)~USART_DMAReq;
+ }
+}
+
+/*******************************************************************************
+* Function Name : USART_SetAddress
+* Description : Sets the address of the USART node.
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART
+* peripheral.
+* - USART_Address: Indicates the address of the USART node.
+* Output : None
+* Return : None
+*******************************************************************************/
+void USART_SetAddress(USART_TypeDef* USARTx, u8 USART_Address)
+{
+ /* Check the parameters */
+ assert(IS_USART_ADDRESS(USART_Address));
+
+ /* Clear the USART address */
+ USARTx->CR2 &= CR2_Address_Mask;
+ /* Set the USART address node */
+ USARTx->CR2 |= USART_Address;
+}
+
+/*******************************************************************************
+* Function Name : USART_WakeUpConfig
+* Description : Selects the USART WakeUp method.
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART
+* peripheral.
+* - USART_WakeUp: specifies the USART wakeup method.
+* This parameter can be one of the following values:
+* - USART_WakeUp_IdleLine
+* - USART_WakeUp_AddressMark
+* Output : None
+* Return : None
+*******************************************************************************/
+void USART_WakeUpConfig(USART_TypeDef* USARTx, u16 USART_WakeUp)
+{
+ /* Check the parameters */
+ assert(IS_USART_WAKEUP(USART_WakeUp));
+
+ USARTx->CR1 &= CR3_WAKE_Mask;
+ USARTx->CR1 |= USART_WakeUp;
+}
+
+/*******************************************************************************
+* Function Name : USART_ReceiverWakeUpCmd
+* Description : Determines if the USART is in mute mode or not.
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART
+* peripheral.
+* - NewState: new state of the USART mode.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the mute mode USART by setting the RWU bit in the CR1 register */
+ USARTx->CR1 |= CR1_RWU_Set;
+ }
+ else
+ {
+ /* Disable the mute mode USART by clearing the RWU bit in the CR1 register */
+ USARTx->CR1 &= CR1_RWU_Reset;
+ }
+}
+
+/*******************************************************************************
+* Function Name : USART_LINBreakDetectLengthConfig
+* Description : Sets the USART LIN Break detection length.
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART
+* peripheral.
+* - USART_LINBreakDetectLength: specifies the LIN break
+* detection length.
+* This parameter can be one of the following values:
+* - USART_LINBreakDetectLength_10b
+* - USART_LINBreakDetectLength_11b
+* Output : None
+* Return : None
+*******************************************************************************/
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, u16 USART_LINBreakDetectLength)
+{
+ /* Check the parameters */
+ assert(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));
+
+ USARTx->CR2 &= CR3_LBDL_Mask;
+ USARTx->CR2 |= USART_LINBreakDetectLength;
+}
+
+/*******************************************************************************
+* Function Name : USART_LINCmd
+* Description : Enables or disables the USARTs LIN mode.
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART
+* peripheral.
+* - NewState: new state of the USART LIN mode.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the LIN mode by setting the LINE bit in the CR2 register */
+ USARTx->CR2 |= CR2_LINE_Set;
+ }
+ else
+ {
+ /* Disable the LIN mode by clearing the LINE bit in the CR2 register */
+ USARTx->CR2 &= CR2_LINE_Reset;
+ }
+}
+
+/*******************************************************************************
+* Function Name : USART_SendData
+* Description : Transmits signle data through the USARTx peripheral.
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART
+* peripheral.
+* - Data: the data to transmit.
+* Output : None
+* Return : None
+*******************************************************************************/
+void USART_SendData(USART_TypeDef* USARTx, u16 Data)
+{
+ /* Check the parameters */
+ assert(IS_USART_DATA(Data));
+
+ /* Transmit Data */
+ USARTx->DR = (Data & (u16)0x01FF);
+}
+
+/*******************************************************************************
+* Function Name : USART_ReceiveData
+* Description : Returns the most recent received data by the USARTx peripheral.
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART
+* peripheral.
+* Output : None
+* Return : The received data.
+*******************************************************************************/
+u16 USART_ReceiveData(USART_TypeDef* USARTx)
+{
+ /* Receive Data */
+ return (u16)(USARTx->DR & (u16)0x01FF);
+}
+
+/*******************************************************************************
+* Function Name : USART_SendBreak
+* Description : Transmits break characters.
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART
+* peripheral.
+* Output : None
+* Return : None
+*******************************************************************************/
+void USART_SendBreak(USART_TypeDef* USARTx)
+{
+ /* Send break characters */
+ USARTx->CR1 |= CR1_SBK_Set;
+}
+
+/*******************************************************************************
+* Function Name : USART_SetGuardTime
+* Description : Sets the specified USART guard time.
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART
+* peripheral.
+* - USART_GuardTime: specifies the guard time.
+* Output : None
+* Return : None
+*******************************************************************************/
+void USART_SetGuardTime(USART_TypeDef* USARTx, u8 USART_GuardTime)
+{
+ /* Clear the USART Guard time */
+ USARTx->GTPR &= GTPR_LSB_Mask;
+ /* Set the USART guard time */
+ USARTx->GTPR |= (u16)((u16)USART_GuardTime << 0x08);
+}
+
+/*******************************************************************************
+* Function Name : USART_SetPrescaler
+* Description : Sets the system clock prescaler.
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART
+* peripheral.
+* - USART_Prescaler: specifies the prescaler clock.
+* Output : None
+* Return : None
+*******************************************************************************/
+void USART_SetPrescaler(USART_TypeDef* USARTx, u8 USART_Prescaler)
+{
+ /* Clear the USART prescaler */
+ USARTx->GTPR &= GTPR_MSB_Mask;
+ /* Set the USART prescaler */
+ USARTx->GTPR |= USART_Prescaler;
+}
+
+/*******************************************************************************
+* Function Name : USART_SmartCardCmd
+* Description : Enables or disables the USARTs Smart Card mode.
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART
+* peripheral.
+* - NewState: new state of the Smart Card mode.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the SC mode by setting the SCEN bit in the CR3 register */
+ USARTx->CR3 |= CR3_SCEN_Set;
+ }
+ else
+ {
+ /* Disable the SC mode by clearing the SCEN bit in the CR3 register */
+ USARTx->CR3 &= CR3_SCEN_Reset;
+ }
+}
+
+/*******************************************************************************
+* Function Name : USART_SmartCardNACKCmd
+* Description : Enables or disables NACK transmission.
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART
+* peripheral.
+* - NewState: new state of the NACK transmission.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the NACK transmission by setting the NACK bit in the CR3 register */
+ USARTx->CR3 |= CR3_NACK_Set;
+ }
+ else
+ {
+ /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */
+ USARTx->CR3 &= CR3_NACK_Reset;
+ }
+
+}
+
+/*******************************************************************************
+* Function Name : USART_HalfDuplexCmd
+* Description : Enables or disables the USARTs Half Duplex communication.
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART
+* peripheral.
+* - NewState: new state of the USART Communication.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
+ USARTx->CR3 |= CR3_HDSEL_Set;
+ }
+ else
+ {
+ /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */
+ USARTx->CR3 &= CR3_HDSEL_Reset;
+ }
+}
+
+/*******************************************************************************
+* Function Name : USART_IrDAConfig
+* Description : Configures the USARTs IrDA interface.
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART
+* peripheral.
+* - USART_IrDAMode: specifies the IrDA mode.
+* This parameter can be one of the following values:
+* - USART_IrDAMode_LowPower
+* - USART_IrDAMode_Normal
+* Output : None
+* Return : None
+*******************************************************************************/
+void USART_IrDAConfig(USART_TypeDef* USARTx, u16 USART_IrDAMode)
+{
+ /* Check the parameters */
+ assert(IS_USART_IRDA_MODE(USART_IrDAMode));
+
+ USARTx->CR3 &= CR3_IRLP_Mask;
+ USARTx->CR3 |= USART_IrDAMode;
+}
+
+/*******************************************************************************
+* Function Name : USART_IrDACmd
+* Description : Enables or disables the USARTs IrDA interface.
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART
+* peripheral.
+* - NewState: new state of the IrDA mode.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
+ USARTx->CR3 |= CR3_IREN_Set;
+ }
+ else
+ {
+ /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */
+ USARTx->CR3 &= CR3_IREN_Reset;
+ }
+}
+
+/*******************************************************************************
+* Function Name : USART_GetFlagStatus
+* Description : Checks whether the specified USART flag is set or not.
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART
+* peripheral.
+* - USART_FLAG: specifies the flag to check.
+* This parameter can be one of the following values:
+* - USART_FLAG_CTS
+* - USART_FLAG_LBD
+* - USART_FLAG_TXE
+* - USART_FLAG_TC
+* - USART_FLAG_RXNE
+* - USART_FLAG_IDLE
+* - USART_FLAG_ORE
+* - USART_FLAG_NE
+* - USART_FLAG_FE
+* - USART_FLAG_PE
+* Output : None
+* Return : The new state of USART_FLAG (SET or RESET).
+*******************************************************************************/
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, u16 USART_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert(IS_USART_FLAG(USART_FLAG));
+
+ if ((USARTx->SR & USART_FLAG) != (u16)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name : USART_ClearFlag
+* Description : Clears the USARTx's pending flags.
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART
+* peripheral.
+* - USART_FLAG: specifies the flag to clear.
+* This parameter can be any combination of the following values:
+* - USART_FLAG_CTS
+* - USART_FLAG_LBD
+* - USART_FLAG_TXE
+* - USART_FLAG_TC
+* - USART_FLAG_RXNE
+* - USART_FLAG_IDLE
+* - USART_FLAG_ORE
+* - USART_FLAG_NE
+* - USART_FLAG_FE
+* - USART_FLAG_PE
+* Output : None
+* Return : None
+*******************************************************************************/
+void USART_ClearFlag(USART_TypeDef* USARTx, u16 USART_FLAG)
+{
+ /* Check the parameters */
+ assert(IS_USART_CLEAR_FLAG(USART_FLAG));
+
+ USARTx->SR &= (u16)~USART_FLAG;
+}
+
+/*******************************************************************************
+* Function Name : USART_GetITStatus
+* Description : Checks whether the specified USART interrupt has occurred or not.
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART
+* peripheral.
+* - USART_IT: specifies the USART interrupt source to check.
+* This parameter can be one of the following values:
+* - USART_IT_PE
+* - USART_IT_TXE
+* - USART_IT_TC
+* - USART_IT_RXNE
+* - USART_IT_IDLE
+* - USART_IT_LBD
+* - USART_IT_CTS
+* - USART_IT_ORE
+* - USART_IT_NE
+* - USART_IT_FE
+* Output : None
+* Return : The new state of USART_IT (SET or RESET).
+*******************************************************************************/
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, u16 USART_IT)
+{
+ u32 bitpos = 0x00, itmask = 0x00, usartreg = 0;
+ ITStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert(IS_USART_IT(USART_IT));
+
+ /* Get the USART register index */
+ usartreg = (((u8)USART_IT) >> 0x05);
+
+ /* Get the interrupt position */
+ itmask = USART_IT & USART_IT_Mask;
+
+ itmask = (u32)0x01 << itmask;
+
+ if (usartreg == 0x01) /* The IT is in CR1 register */
+ {
+ itmask &= USARTx->CR1;
+ }
+ else if (usartreg == 0x02) /* The IT is in CR2 register */
+ {
+ itmask &= USARTx->CR2;
+ }
+ else /* The IT is in CR3 register */
+ {
+ itmask &= USARTx->CR3;
+ }
+
+ bitpos = USART_IT >> 0x08;
+
+ bitpos = (u32)0x01 << bitpos;
+ bitpos &= USARTx->SR;
+
+ if ((itmask != (u16)RESET)&&(bitpos != (u16)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name : USART_ClearITPendingBit
+* Description : Clears the USARTxs interrupt pending bits.
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART
+* peripheral.
+* - USART_IT: specifies the interrupt pending bit to clear.
+* This parameter can be one of the following values:
+* - USART_IT_PE
+* - USART_IT_TXE
+* - USART_IT_TC
+* - USART_IT_RXNE
+* - USART_IT_IDLE
+* - USART_IT_LBD
+* - USART_IT_CTS
+* - USART_IT_ORE
+* - USART_IT_NE
+* - USART_IT_FE
+* Output : None
+* Return : None
+*******************************************************************************/
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, u16 USART_IT)
+{
+ u32 bitpos = 0x00, itmask = 0x00;
+
+ /* Check the parameters */
+ assert(IS_USART_IT(USART_IT));
+
+ bitpos = USART_IT >> 0x08;
+
+ itmask = (u32)0x01 << bitpos;
+ USARTx->SR &= ~itmask;
+}
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_wwdg.c b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_wwdg.c
new file mode 100644
index 0000000..e1cb58d
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_wwdg.c
@@ -0,0 +1,194 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_wwdg.c
+* Author : MCD Application Team
+* Date First Issued : 09/29/2006
+* Description : This file provides all the WWDG firmware functions.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_wwdg.h"
+#include "stm32f10x_rcc.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* ----------- WWDG registers bit address in the alias region ----------- */
+#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)
+
+/* Alias word address of EWI bit */
+#define CFR_OFFSET (WWDG_OFFSET + 0x04)
+#define EWI_BitNumber 0x09
+#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
+
+/* Alias word address of EWIF bit */
+#define SR_OFFSET (WWDG_OFFSET + 0x08)
+#define EWIF_BitNumber 0x00
+#define SR_EWIF_BB (PERIPH_BB_BASE + (SR_OFFSET * 32) + (EWIF_BitNumber * 4))
+
+/* --------------------- WWDG registers bit mask ------------------------ */
+/* CR register bit mask */
+#define CR_WDGA_Set ((u32)0x00000080)
+
+/* CFR register bit mask */
+#define CFR_WDGTB_Mask ((u32)0xFFFFFE7F)
+#define CFR_W_Mask ((u32)0xFFFFFF80)
+
+#define BIT_Mask ((u8)0x7F)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name : WWDG_DeInit
+* Description : Deinitializes the WWDG peripheral registers to their default
+* reset values.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void WWDG_DeInit(void)
+{
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
+}
+
+/*******************************************************************************
+* Function Name : WWDG_SetPrescaler
+* Description : Sets the WWDG Prescaler.
+* Input : - WWDG_Prescaler: specifies the WWDG Prescaler.
+* This parameter can be one of the following values:
+* - WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
+* - WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
+* - WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
+* - WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
+* Output : None
+* Return : None
+*******************************************************************************/
+void WWDG_SetPrescaler(u32 WWDG_Prescaler)
+{
+ u32 tmpreg = 0;
+
+ /* Check the parameters */
+ assert(IS_WWDG_PRESCALER(WWDG_Prescaler));
+
+ /* Clear WDGTB[8:7] bits */
+ tmpreg = WWDG->CFR & CFR_WDGTB_Mask;
+
+ /* Set WDGTB[8:7] bits according to WWDG_Prescaler value */
+ tmpreg |= WWDG_Prescaler;
+
+ /* Store the new value */
+ WWDG->CFR = tmpreg;
+}
+
+/*******************************************************************************
+* Function Name : WWDG_SetWindowValue
+* Description : Sets the WWDG window value.
+* Input : - WindowValue: specifies the window value to be compared to
+* the downcounter.
+* This parameter value must be lower than 0x80.
+* Output : None
+* Return : None
+*******************************************************************************/
+void WWDG_SetWindowValue(u8 WindowValue)
+{
+ u32 tmpreg = 0;
+
+ /* Check the parameters */
+ assert(IS_WWDG_WINDOW_VALUE(WindowValue));
+
+ /* Clear W[6:0] bits */
+ tmpreg = WWDG->CFR & CFR_W_Mask;
+
+ /* Set W[6:0] bits according to WindowValue value */
+ tmpreg |= WindowValue & BIT_Mask;
+
+ /* Store the new value */
+ WWDG->CFR = tmpreg;
+}
+
+/*******************************************************************************
+* Function Name : WWDG_EnableIT
+* Description : Enables the WWDG Early Wakeup interrupt(EWI).
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void WWDG_EnableIT(void)
+{
+ *(vu32 *) CFR_EWI_BB = (u32)ENABLE;
+}
+
+/*******************************************************************************
+* Function Name : WWDG_SetCounter
+* Description : Sets the WWDG counter value.
+* Input : - Counter: specifies the watchdog counter value.
+* This parameter must be a number between 0x40 and 0x7F.
+* Output : None
+* Return : None
+*******************************************************************************/
+void WWDG_SetCounter(u8 Counter)
+{
+ /* Check the parameters */
+ assert(IS_WWDG_COUNTER(Counter));
+
+ /* Write to T[6:0] bits to configure the counter value, no need to do
+ a read-modify-write; writing a 0 to WDGA bit does nothing */
+ WWDG->CR = Counter & BIT_Mask;
+}
+
+/*******************************************************************************
+* Function Name : WWDG_Enable
+* Description : Enables WWDG and load the counter value.
+* - Counter: specifies the watchdog counter value.
+* This parameter must be a number between 0x40 and 0x7F.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void WWDG_Enable(u8 Counter)
+{
+ /* Check the parameters */
+ assert(IS_WWDG_COUNTER(Counter));
+
+ WWDG->CR = CR_WDGA_Set | Counter;
+}
+
+/*******************************************************************************
+* Function Name : WWDG_GetFlagStatus
+* Description : Checks whether the Early Wakeup interrupt flag is set or not.
+* Input : None
+* Output : None
+* Return : The new state of the Early Wakeup interrupt flag (SET or RESET)
+*******************************************************************************/
+FlagStatus WWDG_GetFlagStatus(void)
+{
+ return (FlagStatus)(*(vu32 *) SR_EWIF_BB);
+}
+
+/*******************************************************************************
+* Function Name : WWDG_ClearFlag
+* Description : Clears Early Wakeup interrupt flag.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void WWDG_ClearFlag(void)
+{
+ WWDG->SR = (u32)RESET;
+}
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/version.txt b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/version.txt
new file mode 100644
index 0000000..72d3001
--- /dev/null
+++ b/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/version.txt
@@ -0,0 +1,22 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : version.txt
+* Author : MCD Application Team
+* Date First Issued : 09/29/2006
+* Description : Version file for STM32F10x Firmware Library.
+********************************************************************************
+
+* 04/02/2007: V0.2
+===================
+ Updated version
+
+* 02/05/2007 : V0.1
+===================
+ Updated version
+
+* 09/29/2006 : V0.01
+===================
+ Created.
+
+******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE******
+
+
