Handle interrupt acknowledge register in Cortex-A53 SRE port (#392)
Let the FreeRTOS IRQ handler properly store and restore the ICCIAR
register value around the vApplicationIRQHandler() call.
Signed-off-by: Stephane Viau <stephane.viau@oss.nxp.com>
Co-authored-by: Stephane Viau <stephane.viau@oss.nxp.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
diff --git a/portable/GCC/ARM_CA53_64_BIT_SRE/portASM.S b/portable/GCC/ARM_CA53_64_BIT_SRE/portASM.S
index 79a5465..7df2b27 100644
--- a/portable/GCC/ARM_CA53_64_BIT_SRE/portASM.S
+++ b/portable/GCC/ARM_CA53_64_BIT_SRE/portASM.S
@@ -303,6 +303,13 @@
/* Maintain the interrupt nesting information across the function call. */
STP X1, X5, [SP, #-0x10]!
+ /* Read value from the interrupt acknowledge register, which is stored in W0
+ for future parameter and interrupt clearing use. */
+ MRS X0, S3_0_C12_C12_0 /* read ICC_IAR1_EL1 and store ICCIAR in X0 as parameter */
+
+ /* Maintain the ICCIAR value across the function call. */
+ STP X0, X1, [SP, #-0x10]!
+
/* Call the C handler. */
BL vApplicationIRQHandler
@@ -311,6 +318,12 @@
DSB SY
ISB SY
+ /* Restore the ICCIAR value. */
+ LDP X0, X1, [SP], #0x10
+
+ /* End IRQ processing by writing ICCIAR to the EOI register. */
+ MSR S3_0_C12_C12_1, X0 /* ICC_EOIR1_EL1 */
+
/* Restore the critical nesting count. */
LDP X1, X5, [SP], #0x10
STR X1, [X5]
