Use UBaseType_t as interrupt mask (#689)
* Use UBaseType_t as interrupt mask
* Update GCC posix port to use UBaseType_t as interrupt mask
diff --git a/queue.c b/queue.c
index 27776f0..23e9704 100644
--- a/queue.c
+++ b/queue.c
@@ -1099,7 +1099,7 @@
const BaseType_t xCopyPosition )
{
BaseType_t xReturn;
- portBASE_TYPE xSavedInterruptStatus;
+ UBaseType_t uxSavedInterruptStatus;
Queue_t * const pxQueue = xQueue;
configASSERT( pxQueue );
@@ -1127,7 +1127,7 @@
* read, instead return a flag to say whether a context switch is required or
* not (i.e. has a task with a higher priority than us been woken by this
* post). */
- xSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
{
if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
{
@@ -1252,7 +1252,7 @@
xReturn = errQUEUE_FULL;
}
}
- portCLEAR_INTERRUPT_MASK_FROM_ISR( xSavedInterruptStatus );
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
return xReturn;
}
@@ -1262,7 +1262,7 @@
BaseType_t * const pxHigherPriorityTaskWoken )
{
BaseType_t xReturn;
- portBASE_TYPE xSavedInterruptStatus;
+ UBaseType_t uxSavedInterruptStatus;
Queue_t * const pxQueue = xQueue;
/* Similar to xQueueGenericSendFromISR() but used with semaphores where the
@@ -1298,7 +1298,7 @@
* link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
- xSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
{
const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
@@ -1418,7 +1418,7 @@
xReturn = errQUEUE_FULL;
}
}
- portCLEAR_INTERRUPT_MASK_FROM_ISR( xSavedInterruptStatus );
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
return xReturn;
}
@@ -1933,7 +1933,7 @@
BaseType_t * const pxHigherPriorityTaskWoken )
{
BaseType_t xReturn;
- portBASE_TYPE xSavedInterruptStatus;
+ UBaseType_t uxSavedInterruptStatus;
Queue_t * const pxQueue = xQueue;
configASSERT( pxQueue );
@@ -1955,7 +1955,7 @@
* link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
- xSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
{
const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
@@ -2015,7 +2015,7 @@
traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue );
}
}
- portCLEAR_INTERRUPT_MASK_FROM_ISR( xSavedInterruptStatus );
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
return xReturn;
}
@@ -2025,7 +2025,7 @@
void * const pvBuffer )
{
BaseType_t xReturn;
- portBASE_TYPE xSavedInterruptStatus;
+ UBaseType_t uxSavedInterruptStatus;
int8_t * pcOriginalReadPosition;
Queue_t * const pxQueue = xQueue;
@@ -2049,7 +2049,7 @@
* link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
- xSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
{
/* Cannot block in an ISR, so check there is data available. */
if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
@@ -2070,7 +2070,7 @@
traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue );
}
}
- portCLEAR_INTERRUPT_MASK_FROM_ISR( xSavedInterruptStatus );
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
return xReturn;
}