Update RISC-V_IGLOO2_Creative_SoftConsole demo to make use of new RISC-V porting layer structure and exercise some external interrupts - all tests currently passing in Renode.
diff --git a/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/.cproject b/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/.cproject
index a4718e7..19414c5 100644
--- a/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/.cproject
+++ b/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/.cproject
@@ -41,7 +41,7 @@
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.addtools.printsize.306588546" name="Print size" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.addtools.printsize" useByScannerDiscovery="false" value="true" valueType="boolean"/>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.level.1940053873" name="Optimization Level" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.level" useByScannerDiscovery="true" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.level.none" valueType="enumerated"/>
+ <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.level.1940053873" name="Optimization Level" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.level" useByScannerDiscovery="true" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.level.most" valueType="enumerated"/>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.messagelength.565243439" name="Message length (-fmessage-length=0)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.messagelength" useByScannerDiscovery="true" value="false" valueType="boolean"/>
@@ -85,9 +85,9 @@
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.freestanding.224053313" name="Assume freestanding environment (-ffreestanding)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.freestanding" useByScannerDiscovery="true" value="false" valueType="boolean"/>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.noinlinefunctions.1322946455" name="Do not inline functions (-fno-inline-functions)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.noinlinefunctions" value="false" valueType="boolean"/>
+ <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.noinlinefunctions.1322946455" name="Do not inline functions (-fno-inline-functions)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.noinlinefunctions" useByScannerDiscovery="true" value="false" valueType="boolean"/>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.nobuiltin.1525203912" name="Disable builtin (-fno-builtin)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.nobuiltin" value="true" valueType="boolean"/>
+ <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.nobuiltin.1525203912" name="Disable builtin (-fno-builtin)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.nobuiltin" useByScannerDiscovery="true" value="true" valueType="boolean"/>
<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform.1851994667" isAbstract="false" osList="all" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform"/>
@@ -97,6 +97,12 @@
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.usepreprocessor.1853992692" name="Use preprocessor" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.usepreprocessor" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+ <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.include.paths.1792818218" name="Include paths (-I)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.include.paths" useByScannerDiscovery="true" valueType="includePath">
+
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/FreeRTOS_Source/portable/GCC/RISC-V-RV32/CLINT}""/>
+
+ </option>
+
<inputType id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.assembler.input.1786331150" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.assembler.input"/>
</tool>
diff --git a/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/.settings/language.settings.xml b/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/.settings/language.settings.xml
index 5b37960..69a0ac0 100644
--- a/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/.settings/language.settings.xml
+++ b/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/.settings/language.settings.xml
@@ -11,7 +11,7 @@
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
- <provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-564858745062802889" id="ilg.gnumcueclipse.managedbuild.cross.riscv.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT RISC-V Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
+ <provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="247273655846757705" id="ilg.gnumcueclipse.managedbuild.cross.riscv.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT RISC-V Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
<language-scope id="org.eclipse.cdt.core.gcc"/>
diff --git a/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/FreeRTOSConfig.h b/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/FreeRTOSConfig.h
index e657e63..8dbf46c 100644
--- a/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/FreeRTOSConfig.h
+++ b/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/FreeRTOSConfig.h
@@ -144,4 +144,8 @@
#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); __asm volatile( "ebreak" ); for( ;; ); }
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+
+#define handle_m_ext_interrupt vPortHandleInterrupt
+
+
#endif /* FREERTOS_CONFIG_H */
diff --git a/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/Microsemi_Code/riscv_hal/microsemi-riscv-igloo2.ld b/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/Microsemi_Code/riscv_hal/microsemi-riscv-igloo2.ld
index 99d1c10..68d030d 100644
--- a/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/Microsemi_Code/riscv_hal/microsemi-riscv-igloo2.ld
+++ b/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/Microsemi_Code/riscv_hal/microsemi-riscv-igloo2.ld
@@ -1,17 +1,17 @@
/*******************************************************************************
* (c) Copyright 2016-2018 Microsemi SoC Products Group. All rights reserved.
- *
+ *
* file name : microsemi-riscv-igloo2.ld
* Mi-V soft processor linker script for creating a SoftConsole downloadable
* image executing in eNVM.
- *
+ *
* This linker script assumes that the eNVM is connected at on the Mi-V soft
- * processor memory space.
+ * processor memory space.
*
* SVN $Revision: 9661 $
* SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $
*/
-
+
OUTPUT_ARCH( "riscv" )
ENTRY(_start)
@@ -24,19 +24,19 @@
RAM_START_ADDRESS = 0x80000000; /* Must be the same value MEMORY region ram ORIGIN above. */
RAM_SIZE = 64k; /* Must be the same value MEMORY region ram LENGTH above. */
-STACK_SIZE = 2k; /* needs to be calculated for your application */
+STACK_SIZE = 2k; /* needs to be calculated for your application */
HEAP_SIZE = 2k; /* needs to be calculated for your application */
SECTIONS
{
.text : ALIGN(0x10)
{
- KEEP (*(SORT_NONE(.text.entry)))
+ KEEP (*(SORT_NONE(.text.entry)))
. = ALIGN(0x10);
*(.text .text.* .gnu.linkonce.t.*)
*(.plt)
. = ALIGN(0x10);
-
+
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
@@ -45,12 +45,12 @@
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
-
+
*(.rodata .rodata.* .gnu.linkonce.r.*)
- *(.gcc_except_table)
+ *(.gcc_except_table)
*(.eh_frame_hdr)
*(.eh_frame)
-
+
KEEP (*(.init))
KEEP (*(.fini))
@@ -66,14 +66,14 @@
KEEP (*(SORT(.fini_array.*)))
PROVIDE_HIDDEN (__fini_array_end = .);
. = ALIGN(0x10);
-
+
} >envm
/* short/global data section */
.sdata : ALIGN(0x10)
{
__sdata_load = LOADADDR(.sdata);
- __sdata_start = .;
+ __sdata_start = .;
PROVIDE( __global_pointer$ = . + 0x800);
*(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
*(.srodata*)
@@ -84,9 +84,9 @@
/* data section */
.data : ALIGN(0x10)
- {
+ {
__data_load = LOADADDR(.data);
- __data_start = .;
+ __data_start = .;
*(.got.plt) *(.got)
*(.shdata)
*(.data .data.* .gnu.linkonce.d.*)
@@ -103,10 +103,10 @@
. = ALIGN(0x10);
__sbss_end = .;
} > ram
-
+
/* sbss section */
.bss : ALIGN(0x10)
- {
+ {
__bss_start = .;
*(.shbss)
*(.bss .bss.* .gnu.linkonce.b.*)
@@ -117,7 +117,7 @@
/* End of uninitialized data segment */
_end = .;
-
+
.heap : ALIGN(0x10)
{
__heap_start = .;
@@ -126,13 +126,14 @@
. = ALIGN(0x10);
_heap_end = __heap_end;
} > ram
-
+
.stack : ALIGN(0x10)
{
__stack_bottom = .;
. += STACK_SIZE;
__stack_top = .;
_sp = .;
+ __freertos_irq_stack_top = .;
} > ram
}
diff --git a/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/Microsemi_Code/riscv_hal/microsemi-riscv-ram.ld b/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/Microsemi_Code/riscv_hal/microsemi-riscv-ram.ld
index 47b7707..305cb0e 100644
--- a/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/Microsemi_Code/riscv_hal/microsemi-riscv-ram.ld
+++ b/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/Microsemi_Code/riscv_hal/microsemi-riscv-ram.ld
@@ -1,10 +1,10 @@
/*******************************************************************************
* (c) Copyright 2016-2018 Microsemi SoC Products Group. All rights reserved.
- *
+ *
* file name : microsemi-riscv-ram.ld
* Mi-V soft processor linker script for creating a SoftConsole downloadable
* debug image executing in SRAM.
- *
+ *
* This linker script assumes that the SRAM is connected at on the Mi-V soft
* processor memory space. The start address and size of the memory space must
* be correct as per the Libero design.
@@ -12,7 +12,7 @@
* SVN $Revision: 9661 $
* SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $
*/
-
+
OUTPUT_ARCH( "riscv" )
ENTRY(_start)
@@ -24,19 +24,19 @@
RAM_START_ADDRESS = 0x80000000; /* Must be the same value MEMORY region ram ORIGIN above. */
RAM_SIZE = 512k; /* Must be the same value MEMORY region ram LENGTH above. */
-STACK_SIZE = 64k; /* needs to be calculated for your application */
+STACK_SIZE = 64k; /* needs to be calculated for your application */
HEAP_SIZE = 64k; /* needs to be calculated for your application */
SECTIONS
{
.text : ALIGN(0x10)
{
- KEEP (*(SORT_NONE(.text.entry)))
+ KEEP (*(SORT_NONE(.text.entry)))
. = ALIGN(0x10);
*(.text .text.* .gnu.linkonce.t.*)
*(.plt)
. = ALIGN(0x10);
-
+
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
@@ -45,12 +45,12 @@
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
-
+
*(.rodata .rodata.* .gnu.linkonce.r.*)
- *(.gcc_except_table)
+ *(.gcc_except_table)
*(.eh_frame_hdr)
*(.eh_frame)
-
+
KEEP (*(.init))
KEEP (*(.fini))
@@ -66,14 +66,14 @@
KEEP (*(SORT(.fini_array.*)))
PROVIDE_HIDDEN (__fini_array_end = .);
. = ALIGN(0x10);
-
+
} > ram
/* short/global data section */
.sdata : ALIGN(0x10)
{
__sdata_load = LOADADDR(.sdata);
- __sdata_start = .;
+ __sdata_start = .;
PROVIDE( __global_pointer$ = . + 0x800);
*(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
*(.srodata*)
@@ -84,9 +84,9 @@
/* data section */
.data : ALIGN(0x10)
- {
+ {
__data_load = LOADADDR(.data);
- __data_start = .;
+ __data_start = .;
*(.got.plt) *(.got)
*(.shdata)
*(.data .data.* .gnu.linkonce.d.*)
@@ -103,10 +103,10 @@
. = ALIGN(0x10);
__sbss_end = .;
} > ram
-
+
/* sbss section */
.bss : ALIGN(0x10)
- {
+ {
__bss_start = .;
*(.shbss)
*(.bss .bss.* .gnu.linkonce.b.*)
@@ -117,7 +117,7 @@
/* End of uninitialized data segment */
_end = .;
-
+
.heap : ALIGN(0x10)
{
__heap_start = .;
@@ -126,13 +126,14 @@
. = ALIGN(0x10);
_heap_end = __heap_end;
} > ram
-
+
.stack : ALIGN(0x10)
{
__stack_bottom = .;
. += STACK_SIZE;
__stack_top = .;
_sp = .;
+ __freertos_irq_stack_top = .;
} > ram
}
diff --git a/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/Microsemi_Code/riscv_hal/riscv_hal.c b/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/Microsemi_Code/riscv_hal/riscv_hal.c
index 1bf02d6..14ecf7b 100644
--- a/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/Microsemi_Code/riscv_hal/riscv_hal.c
+++ b/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/Microsemi_Code/riscv_hal/riscv_hal.c
@@ -1,4 +1,3 @@
-#if 0
/*******************************************************************************
* (c) Copyright 2016-2018 Microsemi SoC Products Group. All rights reserved.
*
@@ -15,6 +14,8 @@
#include "riscv_hal.h"
+#include "FreeRTOS.h"
+
#ifdef __cplusplus
extern "C" {
#endif
@@ -67,70 +68,6 @@
extern void Timer_IRQHandle( void );
/*------------------------------------------------------------------------------
- * Increment value for the mtimecmp register in order to achieve a system tick
- * interrupt as specified through the SysTick_Config() function.
- */
-static uint64_t g_systick_increment = 0U;
-
-/*------------------------------------------------------------------------------
- * Disable all interrupts.
- */
-void __disable_irq(void)
-{
- clear_csr(mstatus, MSTATUS_MPIE);
- clear_csr(mstatus, MSTATUS_MIE);
-}
-
-/*------------------------------------------------------------------------------
- * Enabler all interrupts.
- */
-void __enable_irq(void)
-{
- set_csr(mstatus, MSTATUS_MIE);
-}
-
-/*------------------------------------------------------------------------------
- * Configure the machine timer to generate an interrupt.
- */
-uint32_t SysTick_Config(uint32_t ticks)
-{
- uint32_t ret_val = ERROR;
-
- g_systick_increment = (uint64_t)(ticks) / RTC_PRESCALER;
-
- if (g_systick_increment > 0U)
- {
- uint32_t mhart_id = read_csr(mhartid);
-
- PRCI->MTIMECMP[mhart_id] = PRCI->MTIME + g_systick_increment;
-
- set_csr(mie, MIP_MTIP);
-
- __enable_irq();
-
- ret_val = SUCCESS;
- }
-
- return ret_val;
-}
-
-/*------------------------------------------------------------------------------
- * RISC-V interrupt handler for machine timer interrupts.
- */
-volatile uint32_t ulTimerInterrupts = 0;
-extern void Timer_IRQHandler( void );
-static void handle_m_timer_interrupt(void)
-{
-// clear_csr(mie, MIP_MTIP);
-
- Timer_IRQHandler();
-
-// PRCI->MTIMECMP[read_csr(mhartid)] = PRCI->MTIME + g_systick_increment;
-
-// set_csr(mie, MIP_MTIP);
-}
-
-/*------------------------------------------------------------------------------
* RISC-V interrupt handler for external interrupts.
*/
uint8_t (*ext_irq_handler_table[32])(void) =
@@ -172,7 +109,7 @@
/*------------------------------------------------------------------------------
*
*/
-static void handle_m_ext_interrupt(void)
+void handle_m_ext_interrupt(void)
{
uint32_t int_num = PLIC_ClaimIRQ();
uint8_t disable = EXT_IRQ_KEEP_ENABLED;
@@ -187,82 +124,7 @@
}
}
-static void handle_m_soft_interrupt(void)
-{
- Software_IRQHandler();
-
- /*Clear software interrupt*/
- PRCI->MSIP[0] = 0x00U;
-}
-
-/*------------------------------------------------------------------------------
- * Trap/Interrupt handler
- */
-#define ENV_CALL_FROM_M_MODE 11
-extern void vTaskSwitchContext( void );
-
-uintptr_t handle_trap(uintptr_t mcause, uintptr_t mepc)
-{
- /*_RB_*/
- if( mcause == ENV_CALL_FROM_M_MODE )
- {
- vTaskSwitchContext();
-
- /* Ensure not to return to the instruction that generated the exception. */
- mepc += 4;
- } else
- /*end _RB_*/
- if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT))
- {
- handle_m_ext_interrupt();
- }
- else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER))
- {
- handle_m_timer_interrupt();
- }
- else if ( (mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_SOFT))
- {
- handle_m_soft_interrupt();
- }
- else
- {
-#ifndef NDEBUG
- /*
- Arguments supplied to this function are mcause, mepc (exception PC) and stack pointer
- based onprivileged-isa specification
- mcause values and meanings are:
- 0 Instruction address misaligned (mtval/mbadaddr is the address)
- 1 Instruction access fault (mtval/mbadaddr is the address)
- 2 Illegal instruction (mtval/mbadaddr contains the offending instruction opcode)
- 3 Breakpoint
- 4 Load address misaligned (mtval/mbadaddr is the address)
- 5 Load address fault (mtval/mbadaddr is the address)
- 6 Store/AMO address fault (mtval/mbadaddr is the address)
- 7 Store/AMO access fault (mtval/mbadaddr is the address)
- 8 Environment call from U-mode
- 9 Environment call from S-mode
- A Environment call from M-mode
- B Instruction page fault
- C Load page fault (mtval/mbadaddr is the address)
- E Store page fault (mtval/mbadaddr is the address)
- */
-
- uintptr_t mip = read_csr(mip); /* interrupt pending */
- uintptr_t mbadaddr = read_csr(mbadaddr); /* additional info and meaning depends on mcause */
- uintptr_t mtvec = read_csr(mtvec); /* trap vector */
- uintptr_t mscratch = read_csr(mscratch); /* temporary, sometimes might hold temporary value of a0 */
- uintptr_t mstatus = read_csr(mstatus); /* status contains many smaller fields: */
-
- /* breakpoint*/
- __asm("ebreak");
-#else
- _exit(1 + mcause);
-#endif
- }
- return mepc;
-}
#ifdef __cplusplus
}
#endif
-#endif
diff --git a/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/Microsemi_Code/riscv_hal/riscv_plic.h b/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/Microsemi_Code/riscv_hal/riscv_plic.h
index b306c5b..2d09518 100644
--- a/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/Microsemi_Code/riscv_hal/riscv_plic.h
+++ b/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/Microsemi_Code/riscv_hal/riscv_plic.h
@@ -143,7 +143,7 @@
PLIC->TARGET[hart_id].PRIORITY_THRESHOLD = 0;
/* Enable machine external interrupts. */
-// set_csr(mie, MIP_MEIP);
+ set_csr(mie, MIP_MEIP);
}
/*==============================================================================
diff --git a/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/full_demo/main_full.c b/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/full_demo/main_full.c
index a0efe8d..f86b8c6 100644
--- a/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/full_demo/main_full.c
+++ b/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/full_demo/main_full.c
@@ -70,6 +70,10 @@
#include "timers.h"
#include "semphr.h"
+/* Microsemi incldues. */
+#include "core_timer.h"
+#include "riscv_hal.h"
+
/* Standard demo application includes. */
#include "dynamic.h"
#include "blocktim.h"
@@ -124,6 +128,12 @@
static void prvCheckTask( void *pvParameters );
/*
+ * Initialise and start the peripheral timers that are used to exercise external
+ * interrupt processing.
+ */
+static void prvSetupPeripheralTimers( void );
+
+/*
* Register check tasks as described at the top of this file. The nature of
* these files necessitates that they are written in an assembly file, but the
* entry points are kept in the C file for the convenience of checking the task
@@ -142,6 +152,13 @@
/*-----------------------------------------------------------*/
+/* Timers used to exercise external interrupt processing. */
+static timer_instance_t g_timer0, g_timer1;
+
+/* Variables incremented by the peripheral timers used to exercise external
+interrupts. */
+volatile uint32_t ulTimer0Interrupts = 0, ulTimer1Interrupts = 0;
+
/* The following two variables are used to communicate the status of the
register check tasks to the check task. If the variables keep incrementing,
then the register check tasks have not discovered any errors. If a variable
@@ -188,6 +205,9 @@
running. */
vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );
+ /* Start the timers that are used to exercise external interrupt handling. */
+ prvSetupPeripheralTimers();
+
/* Start the scheduler. */
vTaskStartScheduler();
@@ -205,7 +225,8 @@
{
TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD;
TickType_t xLastExecutionTime;
-static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;
+uint32_t ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;
+uint32_t ulLastTimer0Interrupts = 0, ulLastTimer1Interrupts = 0;
char * const pcPassMessage = "Pass.\r\n";
char * pcStatusMessage = pcPassMessage;
extern void vSendString( const char * const pcString );
@@ -310,9 +331,21 @@
}
ulLastRegTest2Value = ulRegTest2LoopCounter;
+ /* Check interrupts from the peripheral timers are being handled. */
+ if( ulLastTimer0Interrupts == ulTimer0Interrupts )
+ {
+ pcStatusMessage = "ERROR: Peripheral timer 0.\r\n";
+ }
+ ulLastTimer0Interrupts = ulTimer0Interrupts;
+
+ if( ulLastTimer1Interrupts == ulTimer1Interrupts )
+ {
+ pcStatusMessage = "ERROR: Peripheral timer 1.\r\n";
+ }
+ ulLastTimer1Interrupts = ulTimer1Interrupts;
+
/* Write the status message to the UART. */
vSendString( pcStatusMessage );
- vToggleLED();
/* If an error has been found then increase the LED toggle rate by
increasing the cycle frequency. */
@@ -383,3 +416,60 @@
/* Called from vApplicationTickHook() when the project is configured to
build the full test/demo applications. */
}
+/*-----------------------------------------------------------*/
+
+static void prvSetupPeripheralTimers( void )
+{
+ TMR_init( &g_timer0,
+ CORETIMER0_BASE_ADDR,
+ TMR_CONTINUOUS_MODE,
+ PRESCALER_DIV_1024,
+ 83000 );
+
+ TMR_init( &g_timer1,
+ CORETIMER1_BASE_ADDR,
+ TMR_CONTINUOUS_MODE,
+ PRESCALER_DIV_512,
+ 42000 );
+
+ /* In this version of the PLIC, the priorities are fixed at 1.
+ Lower numbered devices have higher priorities. But this code is given as
+ an example.
+ */
+ PLIC_SetPriority( External_30_IRQn, 1 );
+ PLIC_SetPriority( External_31_IRQn, 1 );
+
+ /*Enable Timer 1 & 0 Interrupt*/
+ PLIC_EnableIRQ( External_30_IRQn );
+ PLIC_EnableIRQ( External_31_IRQn );
+
+ /* Enable the timers */
+ TMR_enable_int( &g_timer0 );
+ TMR_enable_int( &g_timer1 );
+
+ /* Make sure timers don't interrupt until the scheduler is running. */
+ portDISABLE_INTERRUPTS();
+
+ /*Start the timer*/
+ TMR_start( &g_timer0 );
+ TMR_start( &g_timer1 );
+}
+/*-----------------------------------------------------------*/
+
+/*Core Timer 0 Interrupt Handler*/
+uint8_t External_30_IRQHandler( void )
+{
+ ulTimer0Interrupts++;
+ TMR_clear_int(&g_timer0);
+ return( EXT_IRQ_KEEP_ENABLED );
+}
+/*-----------------------------------------------------------*/
+
+/*Core Timer 1 Interrupt Handler*/
+uint8_t External_31_IRQHandler( void )
+{
+ ulTimer1Interrupts++;
+ TMR_clear_int(&g_timer1);
+
+ return( EXT_IRQ_KEEP_ENABLED );
+}
diff --git a/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/main.c b/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/main.c
index be526c2..59c3093 100644
--- a/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/main.c
+++ b/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/main.c
@@ -107,7 +107,6 @@
{
PLIC_init();
UART_init( &g_uart, COREUARTAPB0_BASE_ADDR, BAUD_VALUE_115200, ( DATA_8_BITS | NO_PARITY ) );
- GPIO_init( &g_gpio_out, COREGPIO_OUT_BASE_ADDR, GPIO_APB_32_BITS_BUS );
}
/*-----------------------------------------------------------*/
@@ -182,3 +181,5 @@
}
#endif
}
+
+
