Added portMEMORY_BARRIER() implemented as __asm volatile( "" ::: "memory" ) into ARM GCC ports to assist with link time optimisation.
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portmacro.h
index 15ca36b..9825cbc 100644
--- a/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portmacro.h
+++ b/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portmacro.h
@@ -205,5 +205,7 @@
#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+
#endif /* PORTMACRO_H */
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CA9/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CA9/portmacro.h
index a8be773..a473877 100644
--- a/FreeRTOS/Source/portable/GCC/ARM_CA9/portmacro.h
+++ b/FreeRTOS/Source/portable/GCC/ARM_CA9/portmacro.h
@@ -202,5 +202,7 @@
#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+
#endif /* PORTMACRO_H */
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM0/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CM0/portmacro.h
index 1552ac0..2392bfb 100644
--- a/FreeRTOS/Source/portable/GCC/ARM_CM0/portmacro.h
+++ b/FreeRTOS/Source/portable/GCC/ARM_CM0/portmacro.h
@@ -107,6 +107,8 @@
#define portNOP()
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+
#ifdef __cplusplus
}
#endif
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h
index 71c09de..cd6fb37 100644
--- a/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h
+++ b/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h
@@ -233,6 +233,7 @@
}
/*-----------------------------------------------------------*/
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
#ifdef __cplusplus
}
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/portmacro.h
index 08efbd4..f0e51fb 100644
--- a/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/portmacro.h
+++ b/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/portmacro.h
@@ -291,6 +291,7 @@
}
/*-----------------------------------------------------------*/
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
#ifdef __cplusplus
}
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h
index 85c718c..261c5ae 100644
--- a/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h
+++ b/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h
@@ -233,6 +233,7 @@
}
/*-----------------------------------------------------------*/
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
#ifdef __cplusplus
}
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/portmacro.h
index 08efbd4..f0e51fb 100644
--- a/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/portmacro.h
+++ b/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/portmacro.h
@@ -291,6 +291,7 @@
}
/*-----------------------------------------------------------*/
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
#ifdef __cplusplus
}
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h
index 4341327..aa28b51 100644
--- a/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h
+++ b/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h
@@ -237,6 +237,7 @@
}
/*-----------------------------------------------------------*/
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
#ifdef __cplusplus
}
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CR5/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CR5/portmacro.h
index b93ca71..111cdc3 100644
--- a/FreeRTOS/Source/portable/GCC/ARM_CR5/portmacro.h
+++ b/FreeRTOS/Source/portable/GCC/ARM_CR5/portmacro.h
@@ -189,5 +189,7 @@
#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+
#endif /* PORTMACRO_H */
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/portmacro.h
index 595cade..a4510ac 100644
--- a/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/portmacro.h
+++ b/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/portmacro.h
@@ -164,6 +164,8 @@
#define portNOP() __asm volatile( "NOP" )
#define portINLINE __inline
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+
#ifdef __cplusplus
} /* extern C */
#endif
diff --git a/FreeRTOS/Source/portable/GCC/RISC-V/portmacro.h b/FreeRTOS/Source/portable/GCC/RISC-V/portmacro.h
index c43cd92..5cc1261 100644
--- a/FreeRTOS/Source/portable/GCC/RISC-V/portmacro.h
+++ b/FreeRTOS/Source/portable/GCC/RISC-V/portmacro.h
@@ -144,6 +144,8 @@
#define portFORCE_INLINE inline __attribute__(( always_inline))
#endif
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+
#ifdef __cplusplus
}
#endif
