Interrupt priority assert improvements for CM3/4/7 (#602)
* Interrupt priority assert improvements for CM3/4/7
In the ARM_CM3, ARM_CM4, and ARM_CM7 ports, change the assertion that
`configMAX_SYSCALL_INTERRUPT_PRIORITY` is nonzero to account for the
number of priority bits implemented by the hardware.
Change these ports to also use the lowest priority for PendSV and
SysTick, ignoring `configKERNEL_INTERRUPT_PRIORITY`.
* Remove not needed configKERNEL_INTERRUPT_PRIORITY define
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---------
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
diff --git a/portable/CCS/ARM_CM3/port.c b/portable/CCS/ARM_CM3/port.c
index 80e0b0a..dfdb240 100644
--- a/portable/CCS/ARM_CM3/port.c
+++ b/portable/CCS/ARM_CM3/port.c
@@ -52,8 +52,9 @@
#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
-#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )
+#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
/* Constants required to check the validity of an interrupt priority. */
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
@@ -239,6 +240,14 @@
/* Use the same mask on the maximum system call priority. */
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+ /* Check that the maximum system call priority is nonzero after
+ * accounting for the number of priority bits supported by the
+ * hardware. A priority of 0 is invalid because setting the BASEPRI
+ * register to 0 unmasks all interrupts, and interrupts with priority 0
+ * cannot be masked using BASEPRI.
+ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( ucMaxSysCallPriority );
+
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
diff --git a/portable/CCS/ARM_CM4F/port.c b/portable/CCS/ARM_CM4F/port.c
index 4006191..360e83d 100644
--- a/portable/CCS/ARM_CM4F/port.c
+++ b/portable/CCS/ARM_CM4F/port.c
@@ -56,8 +56,9 @@
#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
-#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )
+#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
/* Constants required to check the validity of an interrupt priority. */
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
@@ -258,6 +259,14 @@
/* Use the same mask on the maximum system call priority. */
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+ /* Check that the maximum system call priority is nonzero after
+ * accounting for the number of priority bits supported by the
+ * hardware. A priority of 0 is invalid because setting the BASEPRI
+ * register to 0 unmasks all interrupts, and interrupts with priority 0
+ * cannot be masked using BASEPRI.
+ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( ucMaxSysCallPriority );
+
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
diff --git a/portable/GCC/ARM_CM3/port.c b/portable/GCC/ARM_CM3/port.c
index 7f650fd..a5cea1e 100644
--- a/portable/GCC/ARM_CM3/port.c
+++ b/portable/GCC/ARM_CM3/port.c
@@ -34,13 +34,6 @@
#include "FreeRTOS.h"
#include "task.h"
-/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is
- * defined. The value should also ensure backward compatibility.
- * FreeRTOS.org versions prior to V4.4.0 did not include this definition. */
-#ifndef configKERNEL_INTERRUPT_PRIORITY
- #define configKERNEL_INTERRUPT_PRIORITY 255
-#endif
-
/* Constants required to manipulate the core. Registers first... */
#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
@@ -55,8 +48,9 @@
#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
-#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )
+#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
/* Constants required to check the validity of an interrupt priority. */
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
@@ -265,10 +259,6 @@
*/
BaseType_t xPortStartScheduler( void )
{
- /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
- * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
- configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
-
#if ( configASSERT_DEFINED == 1 )
{
volatile uint32_t ulOriginalPriority;
@@ -293,6 +283,14 @@
/* Use the same mask on the maximum system call priority. */
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+ /* Check that the maximum system call priority is nonzero after
+ * accounting for the number of priority bits supported by the
+ * hardware. A priority of 0 is invalid because setting the BASEPRI
+ * register to 0 unmasks all interrupts, and interrupts with priority 0
+ * cannot be masked using BASEPRI.
+ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( ucMaxSysCallPriority );
+
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
diff --git a/portable/GCC/ARM_CM3_MPU/port.c b/portable/GCC/ARM_CM3_MPU/port.c
index e0f1d17..5f7d2c8 100644
--- a/portable/GCC/ARM_CM3_MPU/port.c
+++ b/portable/GCC/ARM_CM3_MPU/port.c
@@ -83,8 +83,9 @@
/* Constants required to access and manipulate the SysTick. */
#define portNVIC_SYSTICK_INT ( 0x00000002UL )
#define portNVIC_SYSTICK_ENABLE ( 0x00000001UL )
-#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )
+#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
#define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
/* Constants required to set up the initial stack. */
@@ -381,10 +382,6 @@
*/
BaseType_t xPortStartScheduler( void )
{
- /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See
- * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
- configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
-
#if ( configASSERT_DEFINED == 1 )
{
volatile uint32_t ulOriginalPriority;
@@ -409,6 +406,14 @@
/* Use the same mask on the maximum system call priority. */
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+ /* Check that the maximum system call priority is nonzero after
+ * accounting for the number of priority bits supported by the
+ * hardware. A priority of 0 is invalid because setting the BASEPRI
+ * register to 0 unmasks all interrupts, and interrupts with priority 0
+ * cannot be masked using BASEPRI.
+ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( ucMaxSysCallPriority );
+
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
diff --git a/portable/GCC/ARM_CM4F/port.c b/portable/GCC/ARM_CM4F/port.c
index b946e6e..b978f0a 100644
--- a/portable/GCC/ARM_CM4F/port.c
+++ b/portable/GCC/ARM_CM4F/port.c
@@ -58,8 +58,9 @@
#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )
#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )
-#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )
+#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
/* Constants required to check the validity of an interrupt priority. */
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
@@ -295,10 +296,6 @@
*/
BaseType_t xPortStartScheduler( void )
{
- /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
- * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
- configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
-
/* This port can be used on all revisions of the Cortex-M7 core other than
* the r0p1 parts. r0p1 parts should use the port from the
* /source/portable/GCC/ARM_CM7/r0p1 directory. */
@@ -329,6 +326,14 @@
/* Use the same mask on the maximum system call priority. */
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+ /* Check that the maximum system call priority is nonzero after
+ * accounting for the number of priority bits supported by the
+ * hardware. A priority of 0 is invalid because setting the BASEPRI
+ * register to 0 unmasks all interrupts, and interrupts with priority 0
+ * cannot be masked using BASEPRI.
+ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( ucMaxSysCallPriority );
+
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
diff --git a/portable/GCC/ARM_CM4_MPU/port.c b/portable/GCC/ARM_CM4_MPU/port.c
index 3125f78..57d0ea5 100644
--- a/portable/GCC/ARM_CM4_MPU/port.c
+++ b/portable/GCC/ARM_CM4_MPU/port.c
@@ -93,8 +93,9 @@
/* Constants required to access and manipulate the SysTick. */
#define portNVIC_SYSTICK_INT ( 0x00000002UL )
#define portNVIC_SYSTICK_ENABLE ( 0x00000001UL )
-#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )
+#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
#define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
/* Constants required to manipulate the VFP. */
@@ -412,10 +413,6 @@
*/
BaseType_t xPortStartScheduler( void )
{
- /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See
- * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
- configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
-
/* Errata 837070 workaround must only be enabled on Cortex-M7 r0p0
* and r0p1 cores. */
#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
@@ -452,6 +449,14 @@
/* Use the same mask on the maximum system call priority. */
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+ /* Check that the maximum system call priority is nonzero after
+ * accounting for the number of priority bits supported by the
+ * hardware. A priority of 0 is invalid because setting the BASEPRI
+ * register to 0 unmasks all interrupts, and interrupts with priority 0
+ * cannot be masked using BASEPRI.
+ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( ucMaxSysCallPriority );
+
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
diff --git a/portable/GCC/ARM_CM7/r0p1/port.c b/portable/GCC/ARM_CM7/r0p1/port.c
index a9c69aa..c602bd2 100644
--- a/portable/GCC/ARM_CM7/r0p1/port.c
+++ b/portable/GCC/ARM_CM7/r0p1/port.c
@@ -52,8 +52,9 @@
#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
-#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )
+#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
/* Constants required to check the validity of an interrupt priority. */
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
@@ -289,10 +290,6 @@
*/
BaseType_t xPortStartScheduler( void )
{
- /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
- * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
- configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
-
#if ( configASSERT_DEFINED == 1 )
{
volatile uint32_t ulOriginalPriority;
@@ -317,6 +314,14 @@
/* Use the same mask on the maximum system call priority. */
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+ /* Check that the maximum system call priority is nonzero after
+ * accounting for the number of priority bits supported by the
+ * hardware. A priority of 0 is invalid because setting the BASEPRI
+ * register to 0 unmasks all interrupts, and interrupts with priority 0
+ * cannot be masked using BASEPRI.
+ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( ucMaxSysCallPriority );
+
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
diff --git a/portable/IAR/ARM_CM0/port.c b/portable/IAR/ARM_CM0/port.c
index ad168e5..c55af1f 100644
--- a/portable/IAR/ARM_CM0/port.c
+++ b/portable/IAR/ARM_CM0/port.c
@@ -56,13 +56,6 @@
/* Constants required to set up the initial stack. */
#define portINITIAL_XPSR ( 0x01000000 )
-/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is
- * defined. The value 255 should also ensure backward compatibility.
- * FreeRTOS.org versions prior to V4.3.0 did not include this definition. */
-#ifndef configKERNEL_INTERRUPT_PRIORITY
- #define configKERNEL_INTERRUPT_PRIORITY 0
-#endif
-
/* Each task maintains its own interrupt status in the critical nesting
* variable. */
static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
diff --git a/portable/IAR/ARM_CM3/port.c b/portable/IAR/ARM_CM3/port.c
index cef6c24..f35ee98 100644
--- a/portable/IAR/ARM_CM3/port.c
+++ b/portable/IAR/ARM_CM3/port.c
@@ -55,8 +55,9 @@
#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
-#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )
+#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
/* Constants required to check the validity of an interrupt priority. */
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
@@ -86,13 +87,6 @@
* have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
-/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is
- * defined. The value 255 should also ensure backward compatibility.
- * FreeRTOS.org versions prior to V4.3.0 did not include this definition. */
-#ifndef configKERNEL_INTERRUPT_PRIORITY
- #define configKERNEL_INTERRUPT_PRIORITY 255
-#endif
-
/* Let the user override the default SysTick clock rate. If defined by the
* user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
* configuration register. */
@@ -214,10 +208,6 @@
*/
BaseType_t xPortStartScheduler( void )
{
- /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
- * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
- configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
-
#if ( configASSERT_DEFINED == 1 )
{
volatile uint32_t ulOriginalPriority;
@@ -242,6 +232,14 @@
/* Use the same mask on the maximum system call priority. */
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+ /* Check that the maximum system call priority is nonzero after
+ * accounting for the number of priority bits supported by the
+ * hardware. A priority of 0 is invalid because setting the BASEPRI
+ * register to 0 unmasks all interrupts, and interrupts with priority 0
+ * cannot be masked using BASEPRI.
+ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( ucMaxSysCallPriority );
+
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
diff --git a/portable/IAR/ARM_CM4F/port.c b/portable/IAR/ARM_CM4F/port.c
index 243d057..90be11d 100644
--- a/portable/IAR/ARM_CM4F/port.c
+++ b/portable/IAR/ARM_CM4F/port.c
@@ -65,8 +65,9 @@
#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )
#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )
-#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )
+#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
/* Constants required to check the validity of an interrupt priority. */
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
@@ -239,10 +240,6 @@
*/
BaseType_t xPortStartScheduler( void )
{
- /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
- * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
- configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
-
/* This port can be used on all revisions of the Cortex-M7 core other than
* the r0p1 parts. r0p1 parts should use the port from the
* /source/portable/GCC/ARM_CM7/r0p1 directory. */
@@ -273,6 +270,14 @@
/* Use the same mask on the maximum system call priority. */
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+ /* Check that the maximum system call priority is nonzero after
+ * accounting for the number of priority bits supported by the
+ * hardware. A priority of 0 is invalid because setting the BASEPRI
+ * register to 0 unmasks all interrupts, and interrupts with priority 0
+ * cannot be masked using BASEPRI.
+ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( ucMaxSysCallPriority );
+
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
diff --git a/portable/IAR/ARM_CM4F_MPU/port.c b/portable/IAR/ARM_CM4F_MPU/port.c
index 2f4d1b9..dd6bde2 100644
--- a/portable/IAR/ARM_CM4F_MPU/port.c
+++ b/portable/IAR/ARM_CM4F_MPU/port.c
@@ -104,8 +104,9 @@
#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )
#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )
-#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )
+#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
#define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
/* Constants required to check the validity of an interrupt priority. */
@@ -346,10 +347,6 @@
*/
BaseType_t xPortStartScheduler( void )
{
- /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
- * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
- configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
-
/* Errata 837070 workaround must only be enabled on Cortex-M7 r0p0
* and r0p1 cores. */
#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
@@ -386,6 +383,14 @@
/* Use the same mask on the maximum system call priority. */
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+ /* Check that the maximum system call priority is nonzero after
+ * accounting for the number of priority bits supported by the
+ * hardware. A priority of 0 is invalid because setting the BASEPRI
+ * register to 0 unmasks all interrupts, and interrupts with priority 0
+ * cannot be masked using BASEPRI.
+ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( ucMaxSysCallPriority );
+
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
diff --git a/portable/IAR/ARM_CM7/r0p1/port.c b/portable/IAR/ARM_CM7/r0p1/port.c
index 207f0b3..e9e3805 100644
--- a/portable/IAR/ARM_CM7/r0p1/port.c
+++ b/portable/IAR/ARM_CM7/r0p1/port.c
@@ -59,8 +59,9 @@
#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
-#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )
+#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
/* Constants required to check the validity of an interrupt priority. */
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
@@ -233,10 +234,6 @@
*/
BaseType_t xPortStartScheduler( void )
{
- /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
- * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
- configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
-
#if ( configASSERT_DEFINED == 1 )
{
volatile uint32_t ulOriginalPriority;
@@ -261,6 +258,14 @@
/* Use the same mask on the maximum system call priority. */
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+ /* Check that the maximum system call priority is nonzero after
+ * accounting for the number of priority bits supported by the
+ * hardware. A priority of 0 is invalid because setting the BASEPRI
+ * register to 0 unmasks all interrupts, and interrupts with priority 0
+ * cannot be masked using BASEPRI.
+ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( ucMaxSysCallPriority );
+
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
diff --git a/portable/MikroC/ARM_CM4F/port.c b/portable/MikroC/ARM_CM4F/port.c
index a0b83eb..886913f 100644
--- a/portable/MikroC/ARM_CM4F/port.c
+++ b/portable/MikroC/ARM_CM4F/port.c
@@ -48,8 +48,9 @@
#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
-#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )
+#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
/* Constants required to check the validity of an interrupt priority. */
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
@@ -295,10 +296,6 @@
*/
BaseType_t xPortStartScheduler( void )
{
- /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
- * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
- configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
-
#if ( configASSERT_DEFINED == 1 )
{
volatile uint32_t ulOriginalPriority;
@@ -320,13 +317,17 @@
/* Read the value back to see how many bits stuck. */
ucMaxPriorityValue = *pucFirstUserPriorityRegister;
- /* The kernel interrupt priority should be set to the lowest
- * priority. */
- configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) );
-
/* Use the same mask on the maximum system call priority. */
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+ /* Check that the maximum system call priority is nonzero after
+ * accounting for the number of priority bits supported by the
+ * hardware. A priority of 0 is invalid because setting the BASEPRI
+ * register to 0 unmasks all interrupts, and interrupts with priority 0
+ * cannot be masked using BASEPRI.
+ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( ucMaxSysCallPriority );
+
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
diff --git a/portable/RVDS/ARM_CM3/port.c b/portable/RVDS/ARM_CM3/port.c
index 551fb34..ac4bef2 100644
--- a/portable/RVDS/ARM_CM3/port.c
+++ b/portable/RVDS/ARM_CM3/port.c
@@ -34,10 +34,6 @@
#include "FreeRTOS.h"
#include "task.h"
-#ifndef configKERNEL_INTERRUPT_PRIORITY
- #define configKERNEL_INTERRUPT_PRIORITY 255
-#endif
-
#if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0
#error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
#endif
@@ -65,8 +61,9 @@
#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
-#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )
+#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
/* Constants required to check the validity of an interrupt priority. */
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
@@ -285,13 +282,17 @@
/* Read the value back to see how many bits stuck. */
ucMaxPriorityValue = *pucFirstUserPriorityRegister;
- /* The kernel interrupt priority should be set to the lowest
- * priority. */
- configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) );
-
/* Use the same mask on the maximum system call priority. */
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+ /* Check that the maximum system call priority is nonzero after
+ * accounting for the number of priority bits supported by the
+ * hardware. A priority of 0 is invalid because setting the BASEPRI
+ * register to 0 unmasks all interrupts, and interrupts with priority 0
+ * cannot be masked using BASEPRI.
+ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( ucMaxSysCallPriority );
+
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
diff --git a/portable/RVDS/ARM_CM4F/port.c b/portable/RVDS/ARM_CM4F/port.c
index d6fb9d7..cdc063d 100644
--- a/portable/RVDS/ARM_CM4F/port.c
+++ b/portable/RVDS/ARM_CM4F/port.c
@@ -71,8 +71,9 @@
#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )
#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )
-#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )
+#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
/* Constants required to check the validity of an interrupt priority. */
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
@@ -347,13 +348,17 @@
/* Read the value back to see how many bits stuck. */
ucMaxPriorityValue = *pucFirstUserPriorityRegister;
- /* The kernel interrupt priority should be set to the lowest
- * priority. */
- configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) );
-
/* Use the same mask on the maximum system call priority. */
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+ /* Check that the maximum system call priority is nonzero after
+ * accounting for the number of priority bits supported by the
+ * hardware. A priority of 0 is invalid because setting the BASEPRI
+ * register to 0 unmasks all interrupts, and interrupts with priority 0
+ * cannot be masked using BASEPRI.
+ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( ucMaxSysCallPriority );
+
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
diff --git a/portable/RVDS/ARM_CM4_MPU/port.c b/portable/RVDS/ARM_CM4_MPU/port.c
index 22680d7..b9c7f90 100644
--- a/portable/RVDS/ARM_CM4_MPU/port.c
+++ b/portable/RVDS/ARM_CM4_MPU/port.c
@@ -83,8 +83,9 @@
#define portNVIC_SYSTICK_CLK ( 0x00000004UL )
#define portNVIC_SYSTICK_INT ( 0x00000002UL )
#define portNVIC_SYSTICK_ENABLE ( 0x00000001UL )
-#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )
+#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
#define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
/* Constants required to manipulate the VFP. */
@@ -442,6 +443,14 @@
/* Use the same mask on the maximum system call priority. */
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+ /* Check that the maximum system call priority is nonzero after
+ * accounting for the number of priority bits supported by the
+ * hardware. A priority of 0 is invalid because setting the BASEPRI
+ * register to 0 unmasks all interrupts, and interrupts with priority 0
+ * cannot be masked using BASEPRI.
+ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( ucMaxSysCallPriority );
+
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
diff --git a/portable/RVDS/ARM_CM7/r0p1/port.c b/portable/RVDS/ARM_CM7/r0p1/port.c
index ae0a4a6..7dadb9a 100644
--- a/portable/RVDS/ARM_CM7/r0p1/port.c
+++ b/portable/RVDS/ARM_CM7/r0p1/port.c
@@ -65,8 +65,9 @@
#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
-#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )
+#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
/* Constants required to check the validity of an interrupt priority. */
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
@@ -331,13 +332,17 @@
/* Read the value back to see how many bits stuck. */
ucMaxPriorityValue = *pucFirstUserPriorityRegister;
- /* The kernel interrupt priority should be set to the lowest
- * priority. */
- configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) );
-
/* Use the same mask on the maximum system call priority. */
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+ /* Check that the maximum system call priority is nonzero after
+ * accounting for the number of priority bits supported by the
+ * hardware. A priority of 0 is invalid because setting the BASEPRI
+ * register to 0 unmasks all interrupts, and interrupts with priority 0
+ * cannot be masked using BASEPRI.
+ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( ucMaxSysCallPriority );
+
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
diff --git a/portable/Tasking/ARM_CM4F/port.c b/portable/Tasking/ARM_CM4F/port.c
index d33a398..66b0d62 100644
--- a/portable/Tasking/ARM_CM4F/port.c
+++ b/portable/Tasking/ARM_CM4F/port.c
@@ -41,8 +41,9 @@
#define portNVIC_SYSTICK_CLK 0x00000004
#define portNVIC_SYSTICK_INT 0x00000002
#define portNVIC_SYSTICK_ENABLE 0x00000001
-#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16 )
-#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24 )
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )
+#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
#define portVECTACTIVE_MASK ( 0xFFUL )
@@ -70,7 +71,7 @@
/* The priority used by the kernel is assigned to a variable to make access
* from inline assembler easier. */
-const uint32_t ulKernelPriority = configKERNEL_INTERRUPT_PRIORITY;
+const uint32_t ulKernelPriority = portMIN_INTERRUPT_PRIORITY;
/* Each task maintains its own interrupt status in the critical nesting
* variable. */
