diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_adc.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_adc.h new file mode 100644 index 0000000..850e8c0 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_adc.h
@@ -0,0 +1,90 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_ADC_INSTANCE_ +#define _SAMA5_ADC_INSTANCE_ + +/* ========== Register definition for ADC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_ADC_CR (0xF8018000U) /**< \brief (ADC) Control Register */ +#define REG_ADC_MR (0xF8018004U) /**< \brief (ADC) Mode Register */ +#define REG_ADC_SEQR1 (0xF8018008U) /**< \brief (ADC) Channel Sequence Register 1 */ +#define REG_ADC_SEQR2 (0xF801800CU) /**< \brief (ADC) Channel Sequence Register 2 */ +#define REG_ADC_CHER (0xF8018010U) /**< \brief (ADC) Channel Enable Register */ +#define REG_ADC_CHDR (0xF8018014U) /**< \brief (ADC) Channel Disable Register */ +#define REG_ADC_CHSR (0xF8018018U) /**< \brief (ADC) Channel Status Register */ +#define REG_ADC_LCDR (0xF8018020U) /**< \brief (ADC) Last Converted Data Register */ +#define REG_ADC_IER (0xF8018024U) /**< \brief (ADC) Interrupt Enable Register */ +#define REG_ADC_IDR (0xF8018028U) /**< \brief (ADC) Interrupt Disable Register */ +#define REG_ADC_IMR (0xF801802CU) /**< \brief (ADC) Interrupt Mask Register */ +#define REG_ADC_ISR (0xF8018030U) /**< \brief (ADC) Interrupt Status Register */ +#define REG_ADC_OVER (0xF801803CU) /**< \brief (ADC) Overrun Status Register */ +#define REG_ADC_EMR (0xF8018040U) /**< \brief (ADC) Extended Mode Register */ +#define REG_ADC_CWR (0xF8018044U) /**< \brief (ADC) Compare Window Register */ +#define REG_ADC_CGR (0xF8018048U) /**< \brief (ADC) Channel Gain Register */ +#define REG_ADC_COR (0xF801804CU) /**< \brief (ADC) Channel Offset Register */ +#define REG_ADC_CDR (0xF8018050U) /**< \brief (ADC) Channel Data Register */ +#define REG_ADC_ACR (0xF8018094U) /**< \brief (ADC) Analog Control Register */ +#define REG_ADC_TSMR (0xF80180B0U) /**< \brief (ADC) Touchscreen Mode Register */ +#define REG_ADC_XPOSR (0xF80180B4U) /**< \brief (ADC) Touchscreen X Position Register */ +#define REG_ADC_YPOSR (0xF80180B8U) /**< \brief (ADC) Touchscreen Y Position Register */ +#define REG_ADC_PRESSR (0xF80180BCU) /**< \brief (ADC) Touchscreen Pressure Register */ +#define REG_ADC_TRGR (0xF80180C0U) /**< \brief (ADC) Trigger Register */ +#define REG_ADC_WPMR (0xF80180E4U) /**< \brief (ADC) Write Protect Mode Register */ +#define REG_ADC_WPSR (0xF80180E8U) /**< \brief (ADC) Write Protect Status Register */ +#else +#define REG_ADC_CR (*(WoReg*)0xF8018000U) /**< \brief (ADC) Control Register */ +#define REG_ADC_MR (*(RwReg*)0xF8018004U) /**< \brief (ADC) Mode Register */ +#define REG_ADC_SEQR1 (*(RwReg*)0xF8018008U) /**< \brief (ADC) Channel Sequence Register 1 */ +#define REG_ADC_SEQR2 (*(RwReg*)0xF801800CU) /**< \brief (ADC) Channel Sequence Register 2 */ +#define REG_ADC_CHER (*(WoReg*)0xF8018010U) /**< \brief (ADC) Channel Enable Register */ +#define REG_ADC_CHDR (*(WoReg*)0xF8018014U) /**< \brief (ADC) Channel Disable Register */ +#define REG_ADC_CHSR (*(RoReg*)0xF8018018U) /**< \brief (ADC) Channel Status Register */ +#define REG_ADC_LCDR (*(RoReg*)0xF8018020U) /**< \brief (ADC) Last Converted Data Register */ +#define REG_ADC_IER (*(WoReg*)0xF8018024U) /**< \brief (ADC) Interrupt Enable Register */ +#define REG_ADC_IDR (*(WoReg*)0xF8018028U) /**< \brief (ADC) Interrupt Disable Register */ +#define REG_ADC_IMR (*(RoReg*)0xF801802CU) /**< \brief (ADC) Interrupt Mask Register */ +#define REG_ADC_ISR (*(RoReg*)0xF8018030U) /**< \brief (ADC) Interrupt Status Register */ +#define REG_ADC_OVER (*(RoReg*)0xF801803CU) /**< \brief (ADC) Overrun Status Register */ +#define REG_ADC_EMR (*(RwReg*)0xF8018040U) /**< \brief (ADC) Extended Mode Register */ +#define REG_ADC_CWR (*(RwReg*)0xF8018044U) /**< \brief (ADC) Compare Window Register */ +#define REG_ADC_CGR (*(RwReg*)0xF8018048U) /**< \brief (ADC) Channel Gain Register */ +#define REG_ADC_COR (*(RwReg*)0xF801804CU) /**< \brief (ADC) Channel Offset Register */ +#define REG_ADC_CDR (*(RoReg*)0xF8018050U) /**< \brief (ADC) Channel Data Register */ +#define REG_ADC_ACR (*(RwReg*)0xF8018094U) /**< \brief (ADC) Analog Control Register */ +#define REG_ADC_TSMR (*(RwReg*)0xF80180B0U) /**< \brief (ADC) Touchscreen Mode Register */ +#define REG_ADC_XPOSR (*(RoReg*)0xF80180B4U) /**< \brief (ADC) Touchscreen X Position Register */ +#define REG_ADC_YPOSR (*(RoReg*)0xF80180B8U) /**< \brief (ADC) Touchscreen Y Position Register */ +#define REG_ADC_PRESSR (*(RoReg*)0xF80180BCU) /**< \brief (ADC) Touchscreen Pressure Register */ +#define REG_ADC_TRGR (*(RwReg*)0xF80180C0U) /**< \brief (ADC) Trigger Register */ +#define REG_ADC_WPMR (*(RwReg*)0xF80180E4U) /**< \brief (ADC) Write Protect Mode Register */ +#define REG_ADC_WPSR (*(RoReg*)0xF80180E8U) /**< \brief (ADC) Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_ADC_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_aes.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_aes.h new file mode 100644 index 0000000..0f61006 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_aes.h
@@ -0,0 +1,58 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_AES_INSTANCE_ +#define _SAMA5_AES_INSTANCE_ + +/* ========== Register definition for AES peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_AES_CR (0xF8038000U) /**< \brief (AES) Control Register */ +#define REG_AES_MR (0xF8038004U) /**< \brief (AES) Mode Register */ +#define REG_AES_IER (0xF8038010U) /**< \brief (AES) Interrupt Enable Register */ +#define REG_AES_IDR (0xF8038014U) /**< \brief (AES) Interrupt Disable Register */ +#define REG_AES_IMR (0xF8038018U) /**< \brief (AES) Interrupt Mask Register */ +#define REG_AES_ISR (0xF803801CU) /**< \brief (AES) Interrupt Status Register */ +#define REG_AES_KEYWR (0xF8038020U) /**< \brief (AES) Key Word Register */ +#define REG_AES_IDATAR (0xF8038040U) /**< \brief (AES) Input Data Register */ +#define REG_AES_ODATAR (0xF8038050U) /**< \brief (AES) Output Data Register */ +#define REG_AES_IVR (0xF8038060U) /**< \brief (AES) Initialization Vector Register */ +#else +#define REG_AES_CR (*(WoReg*)0xF8038000U) /**< \brief (AES) Control Register */ +#define REG_AES_MR (*(RwReg*)0xF8038004U) /**< \brief (AES) Mode Register */ +#define REG_AES_IER (*(WoReg*)0xF8038010U) /**< \brief (AES) Interrupt Enable Register */ +#define REG_AES_IDR (*(WoReg*)0xF8038014U) /**< \brief (AES) Interrupt Disable Register */ +#define REG_AES_IMR (*(RoReg*)0xF8038018U) /**< \brief (AES) Interrupt Mask Register */ +#define REG_AES_ISR (*(RoReg*)0xF803801CU) /**< \brief (AES) Interrupt Status Register */ +#define REG_AES_KEYWR (*(WoReg*)0xF8038020U) /**< \brief (AES) Key Word Register */ +#define REG_AES_IDATAR (*(WoReg*)0xF8038040U) /**< \brief (AES) Input Data Register */ +#define REG_AES_ODATAR (*(RoReg*)0xF8038050U) /**< \brief (AES) Output Data Register */ +#define REG_AES_IVR (*(WoReg*)0xF8038060U) /**< \brief (AES) Initialization Vector Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_AES_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_aic.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_aic.h new file mode 100644 index 0000000..cc03443 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_aic.h
@@ -0,0 +1,86 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_AIC_INSTANCE_ +#define _SAMA5_AIC_INSTANCE_ + +/* ========== Register definition for AIC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_AIC_SSR (0xFFFFF000U) /**< \brief (AIC) Source Select Register */ +#define REG_AIC_SMR (0xFFFFF004U) /**< \brief (AIC) Source Mode Register */ +#define REG_AIC_SVR (0xFFFFF008U) /**< \brief (AIC) Source Vector Register */ +#define REG_AIC_IVR (0xFFFFF010U) /**< \brief (AIC) Interrupt Vector Register */ +#define REG_AIC_FVR (0xFFFFF014U) /**< \brief (AIC) FIQ Interrupt Vector Register */ +#define REG_AIC_ISR (0xFFFFF018U) /**< \brief (AIC) Interrupt Status Register */ +#define REG_AIC_IPR0 (0xFFFFF020U) /**< \brief (AIC) Interrupt Pending Register 0 */ +#define REG_AIC_IPR1 (0xFFFFF024U) /**< \brief (AIC) Interrupt Pending Register 1 */ +#define REG_AIC_IPR2 (0xFFFFF028U) /**< \brief (AIC) Interrupt Pending Register 2 */ +#define REG_AIC_IPR3 (0xFFFFF02CU) /**< \brief (AIC) Interrupt Pending Register 3 */ +#define REG_AIC_IMR (0xFFFFF030U) /**< \brief (AIC) Interrupt Mask Register */ +#define REG_AIC_CISR (0xFFFFF034U) /**< \brief (AIC) Core Interrupt Status Register */ +#define REG_AIC_EOICR (0xFFFFF038U) /**< \brief (AIC) End of Interrupt Command Register */ +#define REG_AIC_SPU (0xFFFFF03CU) /**< \brief (AIC) Spurious Interrupt Vector Register */ +#define REG_AIC_IECR (0xFFFFF040U) /**< \brief (AIC) Interrupt Enable Command Register */ +#define REG_AIC_IDCR (0xFFFFF044U) /**< \brief (AIC) Interrupt Disable Command Register */ +#define REG_AIC_ICCR (0xFFFFF048U) /**< \brief (AIC) Interrupt Clear Command Register */ +#define REG_AIC_ISCR (0xFFFFF04CU) /**< \brief (AIC) Interrupt Set Command Register */ +#define REG_AIC_FFER (0xFFFFF050U) /**< \brief (AIC) Fast Forcing Enable Register */ +#define REG_AIC_FFDR (0xFFFFF054U) /**< \brief (AIC) Fast Forcing Disable Register */ +#define REG_AIC_FFSR (0xFFFFF058U) /**< \brief (AIC) Fast Forcing Status Register */ +#define REG_AIC_DCR (0xFFFFF06CU) /**< \brief (AIC) Debug Control Register */ +#define REG_AIC_WPMR (0xFFFFF0E4U) /**< \brief (AIC) Write Protect Mode Register */ +#define REG_AIC_WPSR (0xFFFFF0E8U) /**< \brief (AIC) Write Protect Status Register */ +#else +#define REG_AIC_SSR (*(RwReg*)0xFFFFF000U) /**< \brief (AIC) Source Select Register */ +#define REG_AIC_SMR (*(RwReg*)0xFFFFF004U) /**< \brief (AIC) Source Mode Register */ +#define REG_AIC_SVR (*(RwReg*)0xFFFFF008U) /**< \brief (AIC) Source Vector Register */ +#define REG_AIC_IVR (*(RoReg*)0xFFFFF010U) /**< \brief (AIC) Interrupt Vector Register */ +#define REG_AIC_FVR (*(RoReg*)0xFFFFF014U) /**< \brief (AIC) FIQ Interrupt Vector Register */ +#define REG_AIC_ISR (*(RoReg*)0xFFFFF018U) /**< \brief (AIC) Interrupt Status Register */ +#define REG_AIC_IPR0 (*(RoReg*)0xFFFFF020U) /**< \brief (AIC) Interrupt Pending Register 0 */ +#define REG_AIC_IPR1 (*(RoReg*)0xFFFFF024U) /**< \brief (AIC) Interrupt Pending Register 1 */ +#define REG_AIC_IPR2 (*(RoReg*)0xFFFFF028U) /**< \brief (AIC) Interrupt Pending Register 2 */ +#define REG_AIC_IPR3 (*(RoReg*)0xFFFFF02CU) /**< \brief (AIC) Interrupt Pending Register 3 */ +#define REG_AIC_IMR (*(RoReg*)0xFFFFF030U) /**< \brief (AIC) Interrupt Mask Register */ +#define REG_AIC_CISR (*(RoReg*)0xFFFFF034U) /**< \brief (AIC) Core Interrupt Status Register */ +#define REG_AIC_EOICR (*(WoReg*)0xFFFFF038U) /**< \brief (AIC) End of Interrupt Command Register */ +#define REG_AIC_SPU (*(RwReg*)0xFFFFF03CU) /**< \brief (AIC) Spurious Interrupt Vector Register */ +#define REG_AIC_IECR (*(WoReg*)0xFFFFF040U) /**< \brief (AIC) Interrupt Enable Command Register */ +#define REG_AIC_IDCR (*(WoReg*)0xFFFFF044U) /**< \brief (AIC) Interrupt Disable Command Register */ +#define REG_AIC_ICCR (*(WoReg*)0xFFFFF048U) /**< \brief (AIC) Interrupt Clear Command Register */ +#define REG_AIC_ISCR (*(WoReg*)0xFFFFF04CU) /**< \brief (AIC) Interrupt Set Command Register */ +#define REG_AIC_FFER (*(WoReg*)0xFFFFF050U) /**< \brief (AIC) Fast Forcing Enable Register */ +#define REG_AIC_FFDR (*(WoReg*)0xFFFFF054U) /**< \brief (AIC) Fast Forcing Disable Register */ +#define REG_AIC_FFSR (*(RoReg*)0xFFFFF058U) /**< \brief (AIC) Fast Forcing Status Register */ +#define REG_AIC_DCR (*(RwReg*)0xFFFFF06CU) /**< \brief (AIC) Debug Control Register */ +#define REG_AIC_WPMR (*(RwReg*)0xFFFFF0E4U) /**< \brief (AIC) Write Protect Mode Register */ +#define REG_AIC_WPSR (*(RoReg*)0xFFFFF0E8U) /**< \brief (AIC) Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_AIC_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_aximx.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_aximx.h new file mode 100644 index 0000000..00b6ef9 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_aximx.h
@@ -0,0 +1,74 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_AXIMX_INSTANCE_ +#define _SAMA5_AXIMX_INSTANCE_ + +/* ========== Register definition for AXIMX peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_AXIMX_REMAP (0x00800000U) /**< \brief (AXIMX) Remap Register */ +#define REG_AXIMX_PERIPH_ID4 (0x00801FD0U) /**< \brief (AXIMX) Peripheral ID Register 4 */ +#define REG_AXIMX_PERIPH_ID5 (0x00801FD4U) /**< \brief (AXIMX) Peripheral ID Register 5 */ +#define REG_AXIMX_PERIPH_ID6 (0x00801FD8U) /**< \brief (AXIMX) Peripheral ID Register 6 */ +#define REG_AXIMX_PERIPH_ID7 (0x00801FDCU) /**< \brief (AXIMX) Peripheral ID Register 7 */ +#define REG_AXIMX_PERIPH_ID0 (0x00801FE0U) /**< \brief (AXIMX) Peripheral ID Register 0 */ +#define REG_AXIMX_PERIPH_ID1 (0x00801FE4U) /**< \brief (AXIMX) Peripheral ID Register 1 */ +#define REG_AXIMX_PERIPH_ID2 (0x00801FE8U) /**< \brief (AXIMX) Peripheral ID Register 2 */ +#define REG_AXIMX_PERIPH_ID3 (0x00801FECU) /**< \brief (AXIMX) Peripheral ID Register 3 */ +#define REG_AXIMX_COMP_ID (0x00801FF0U) /**< \brief (AXIMX) Component ID Register */ +#define REG_AXIMX_AMIB3_FN_MOD_BM_ISS (0x00805008U) /**< \brief (AXIMX) AMIB3 Bus Matrix Functionality Modification Register */ +#define REG_AXIMX_AMIB3_FN_MOD2 (0x00805024U) /**< \brief (AXIMX) AMIB3 Bypass Merge */ +#define REG_AXIMX_ASIB0_READ_QOS (0x00842100U) /**< \brief (AXIMX) ASIB0 Read Channel QoS Register */ +#define REG_AXIMX_ASIB0_WRITE_QOS (0x00842104U) /**< \brief (AXIMX) ASIB0 Write Channel QoS Register */ +#define REG_AXIMX_ASIB1_FN_MOD_AHB (0x00843028U) /**< \brief (AXIMX) ASIB1 AHB Functionality Modification Register */ +#define REG_AXIMX_ASIB1_READ_QOS (0x00843100U) /**< \brief (AXIMX) ASIB1 Read Channel QoS Register */ +#define REG_AXIMX_ASIB1_WRITE_QOS (0x00843104U) /**< \brief (AXIMX) ASIB1 Write Channel QoS Register */ +#define REG_AXIMX_ASIB1_FN_MOD (0x00843108U) /**< \brief (AXIMX) ASIB1 Issuing Functionality Modification Register */ +#else +#define REG_AXIMX_REMAP (*(WoReg*)0x00800000U) /**< \brief (AXIMX) Remap Register */ +#define REG_AXIMX_PERIPH_ID4 (*(RoReg*)0x00801FD0U) /**< \brief (AXIMX) Peripheral ID Register 4 */ +#define REG_AXIMX_PERIPH_ID5 (*(RoReg*)0x00801FD4U) /**< \brief (AXIMX) Peripheral ID Register 5 */ +#define REG_AXIMX_PERIPH_ID6 (*(RoReg*)0x00801FD8U) /**< \brief (AXIMX) Peripheral ID Register 6 */ +#define REG_AXIMX_PERIPH_ID7 (*(RoReg*)0x00801FDCU) /**< \brief (AXIMX) Peripheral ID Register 7 */ +#define REG_AXIMX_PERIPH_ID0 (*(RoReg*)0x00801FE0U) /**< \brief (AXIMX) Peripheral ID Register 0 */ +#define REG_AXIMX_PERIPH_ID1 (*(RoReg*)0x00801FE4U) /**< \brief (AXIMX) Peripheral ID Register 1 */ +#define REG_AXIMX_PERIPH_ID2 (*(RoReg*)0x00801FE8U) /**< \brief (AXIMX) Peripheral ID Register 2 */ +#define REG_AXIMX_PERIPH_ID3 (*(RoReg*)0x00801FECU) /**< \brief (AXIMX) Peripheral ID Register 3 */ +#define REG_AXIMX_COMP_ID (*(RoReg*)0x00801FF0U) /**< \brief (AXIMX) Component ID Register */ +#define REG_AXIMX_AMIB3_FN_MOD_BM_ISS (*(RwReg*)0x00805008U) /**< \brief (AXIMX) AMIB3 Bus Matrix Functionality Modification Register */ +#define REG_AXIMX_AMIB3_FN_MOD2 (*(RwReg*)0x00805024U) /**< \brief (AXIMX) AMIB3 Bypass Merge */ +#define REG_AXIMX_ASIB0_READ_QOS (*(RwReg*)0x00842100U) /**< \brief (AXIMX) ASIB0 Read Channel QoS Register */ +#define REG_AXIMX_ASIB0_WRITE_QOS (*(RwReg*)0x00842104U) /**< \brief (AXIMX) ASIB0 Write Channel QoS Register */ +#define REG_AXIMX_ASIB1_FN_MOD_AHB (*(RwReg*)0x00843028U) /**< \brief (AXIMX) ASIB1 AHB Functionality Modification Register */ +#define REG_AXIMX_ASIB1_READ_QOS (*(RwReg*)0x00843100U) /**< \brief (AXIMX) ASIB1 Read Channel QoS Register */ +#define REG_AXIMX_ASIB1_WRITE_QOS (*(RwReg*)0x00843104U) /**< \brief (AXIMX) ASIB1 Write Channel QoS Register */ +#define REG_AXIMX_ASIB1_FN_MOD (*(RwReg*)0x00843108U) /**< \brief (AXIMX) ASIB1 Issuing Functionality Modification Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_AXIMX_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_bsc.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_bsc.h new file mode 100644 index 0000000..d79cc1f --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_bsc.h
@@ -0,0 +1,40 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_BSC_INSTANCE_ +#define _SAMA5_BSC_INSTANCE_ + +/* ========== Register definition for BSC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_BSC_CR (0xFFFFFE54U) /**< \brief (BSC) Boot Sequence Configuration Register */ +#else +#define REG_BSC_CR (*(RwReg*)0xFFFFFE54U) /**< \brief (BSC) Boot Sequence Configuration Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_BSC_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_can0.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_can0.h new file mode 100644 index 0000000..69e79ff --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_can0.h
@@ -0,0 +1,192 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_CAN0_INSTANCE_ +#define _SAMA5_CAN0_INSTANCE_ + +/* ========== Register definition for CAN0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_CAN0_MR (0xF000C000U) /**< \brief (CAN0) Mode Register */ +#define REG_CAN0_IER (0xF000C004U) /**< \brief (CAN0) Interrupt Enable Register */ +#define REG_CAN0_IDR (0xF000C008U) /**< \brief (CAN0) Interrupt Disable Register */ +#define REG_CAN0_IMR (0xF000C00CU) /**< \brief (CAN0) Interrupt Mask Register */ +#define REG_CAN0_SR (0xF000C010U) /**< \brief (CAN0) Status Register */ +#define REG_CAN0_BR (0xF000C014U) /**< \brief (CAN0) Baudrate Register */ +#define REG_CAN0_TIM (0xF000C018U) /**< \brief (CAN0) Timer Register */ +#define REG_CAN0_TIMESTP (0xF000C01CU) /**< \brief (CAN0) Timestamp Register */ +#define REG_CAN0_ECR (0xF000C020U) /**< \brief (CAN0) Error Counter Register */ +#define REG_CAN0_TCR (0xF000C024U) /**< \brief (CAN0) Transfer Command Register */ +#define REG_CAN0_ACR (0xF000C028U) /**< \brief (CAN0) Abort Command Register */ +#define REG_CAN0_WPMR (0xF000C0E4U) /**< \brief (CAN0) Write Protect Mode Register */ +#define REG_CAN0_WPSR (0xF000C0E8U) /**< \brief (CAN0) Write Protect Status Register */ +#define REG_CAN0_MMR0 (0xF000C200U) /**< \brief (CAN0) Mailbox Mode Register (MB = 0) */ +#define REG_CAN0_MAM0 (0xF000C204U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 0) */ +#define REG_CAN0_MID0 (0xF000C208U) /**< \brief (CAN0) Mailbox ID Register (MB = 0) */ +#define REG_CAN0_MFID0 (0xF000C20CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 0) */ +#define REG_CAN0_MSR0 (0xF000C210U) /**< \brief (CAN0) Mailbox Status Register (MB = 0) */ +#define REG_CAN0_MDL0 (0xF000C214U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 0) */ +#define REG_CAN0_MDH0 (0xF000C218U) /**< \brief (CAN0) Mailbox Data High Register (MB = 0) */ +#define REG_CAN0_MCR0 (0xF000C21CU) /**< \brief (CAN0) Mailbox Control Register (MB = 0) */ +#define REG_CAN0_MMR1 (0xF000C220U) /**< \brief (CAN0) Mailbox Mode Register (MB = 1) */ +#define REG_CAN0_MAM1 (0xF000C224U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 1) */ +#define REG_CAN0_MID1 (0xF000C228U) /**< \brief (CAN0) Mailbox ID Register (MB = 1) */ +#define REG_CAN0_MFID1 (0xF000C22CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 1) */ +#define REG_CAN0_MSR1 (0xF000C230U) /**< \brief (CAN0) Mailbox Status Register (MB = 1) */ +#define REG_CAN0_MDL1 (0xF000C234U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 1) */ +#define REG_CAN0_MDH1 (0xF000C238U) /**< \brief (CAN0) Mailbox Data High Register (MB = 1) */ +#define REG_CAN0_MCR1 (0xF000C23CU) /**< \brief (CAN0) Mailbox Control Register (MB = 1) */ +#define REG_CAN0_MMR2 (0xF000C240U) /**< \brief (CAN0) Mailbox Mode Register (MB = 2) */ +#define REG_CAN0_MAM2 (0xF000C244U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 2) */ +#define REG_CAN0_MID2 (0xF000C248U) /**< \brief (CAN0) Mailbox ID Register (MB = 2) */ +#define REG_CAN0_MFID2 (0xF000C24CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 2) */ +#define REG_CAN0_MSR2 (0xF000C250U) /**< \brief (CAN0) Mailbox Status Register (MB = 2) */ +#define REG_CAN0_MDL2 (0xF000C254U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 2) */ +#define REG_CAN0_MDH2 (0xF000C258U) /**< \brief (CAN0) Mailbox Data High Register (MB = 2) */ +#define REG_CAN0_MCR2 (0xF000C25CU) /**< \brief (CAN0) Mailbox Control Register (MB = 2) */ +#define REG_CAN0_MMR3 (0xF000C260U) /**< \brief (CAN0) Mailbox Mode Register (MB = 3) */ +#define REG_CAN0_MAM3 (0xF000C264U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 3) */ +#define REG_CAN0_MID3 (0xF000C268U) /**< \brief (CAN0) Mailbox ID Register (MB = 3) */ +#define REG_CAN0_MFID3 (0xF000C26CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 3) */ +#define REG_CAN0_MSR3 (0xF000C270U) /**< \brief (CAN0) Mailbox Status Register (MB = 3) */ +#define REG_CAN0_MDL3 (0xF000C274U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 3) */ +#define REG_CAN0_MDH3 (0xF000C278U) /**< \brief (CAN0) Mailbox Data High Register (MB = 3) */ +#define REG_CAN0_MCR3 (0xF000C27CU) /**< \brief (CAN0) Mailbox Control Register (MB = 3) */ +#define REG_CAN0_MMR4 (0xF000C280U) /**< \brief (CAN0) Mailbox Mode Register (MB = 4) */ +#define REG_CAN0_MAM4 (0xF000C284U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 4) */ +#define REG_CAN0_MID4 (0xF000C288U) /**< \brief (CAN0) Mailbox ID Register (MB = 4) */ +#define REG_CAN0_MFID4 (0xF000C28CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 4) */ +#define REG_CAN0_MSR4 (0xF000C290U) /**< \brief (CAN0) Mailbox Status Register (MB = 4) */ +#define REG_CAN0_MDL4 (0xF000C294U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 4) */ +#define REG_CAN0_MDH4 (0xF000C298U) /**< \brief (CAN0) Mailbox Data High Register (MB = 4) */ +#define REG_CAN0_MCR4 (0xF000C29CU) /**< \brief (CAN0) Mailbox Control Register (MB = 4) */ +#define REG_CAN0_MMR5 (0xF000C2A0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 5) */ +#define REG_CAN0_MAM5 (0xF000C2A4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 5) */ +#define REG_CAN0_MID5 (0xF000C2A8U) /**< \brief (CAN0) Mailbox ID Register (MB = 5) */ +#define REG_CAN0_MFID5 (0xF000C2ACU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 5) */ +#define REG_CAN0_MSR5 (0xF000C2B0U) /**< \brief (CAN0) Mailbox Status Register (MB = 5) */ +#define REG_CAN0_MDL5 (0xF000C2B4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 5) */ +#define REG_CAN0_MDH5 (0xF000C2B8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 5) */ +#define REG_CAN0_MCR5 (0xF000C2BCU) /**< \brief (CAN0) Mailbox Control Register (MB = 5) */ +#define REG_CAN0_MMR6 (0xF000C2C0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 6) */ +#define REG_CAN0_MAM6 (0xF000C2C4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 6) */ +#define REG_CAN0_MID6 (0xF000C2C8U) /**< \brief (CAN0) Mailbox ID Register (MB = 6) */ +#define REG_CAN0_MFID6 (0xF000C2CCU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 6) */ +#define REG_CAN0_MSR6 (0xF000C2D0U) /**< \brief (CAN0) Mailbox Status Register (MB = 6) */ +#define REG_CAN0_MDL6 (0xF000C2D4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 6) */ +#define REG_CAN0_MDH6 (0xF000C2D8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 6) */ +#define REG_CAN0_MCR6 (0xF000C2DCU) /**< \brief (CAN0) Mailbox Control Register (MB = 6) */ +#define REG_CAN0_MMR7 (0xF000C2E0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 7) */ +#define REG_CAN0_MAM7 (0xF000C2E4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 7) */ +#define REG_CAN0_MID7 (0xF000C2E8U) /**< \brief (CAN0) Mailbox ID Register (MB = 7) */ +#define REG_CAN0_MFID7 (0xF000C2ECU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 7) */ +#define REG_CAN0_MSR7 (0xF000C2F0U) /**< \brief (CAN0) Mailbox Status Register (MB = 7) */ +#define REG_CAN0_MDL7 (0xF000C2F4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 7) */ +#define REG_CAN0_MDH7 (0xF000C2F8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 7) */ +#define REG_CAN0_MCR7 (0xF000C2FCU) /**< \brief (CAN0) Mailbox Control Register (MB = 7) */ +#else +#define REG_CAN0_MR (*(RwReg*)0xF000C000U) /**< \brief (CAN0) Mode Register */ +#define REG_CAN0_IER (*(WoReg*)0xF000C004U) /**< \brief (CAN0) Interrupt Enable Register */ +#define REG_CAN0_IDR (*(WoReg*)0xF000C008U) /**< \brief (CAN0) Interrupt Disable Register */ +#define REG_CAN0_IMR (*(RoReg*)0xF000C00CU) /**< \brief (CAN0) Interrupt Mask Register */ +#define REG_CAN0_SR (*(RoReg*)0xF000C010U) /**< \brief (CAN0) Status Register */ +#define REG_CAN0_BR (*(RwReg*)0xF000C014U) /**< \brief (CAN0) Baudrate Register */ +#define REG_CAN0_TIM (*(RoReg*)0xF000C018U) /**< \brief (CAN0) Timer Register */ +#define REG_CAN0_TIMESTP (*(RoReg*)0xF000C01CU) /**< \brief (CAN0) Timestamp Register */ +#define REG_CAN0_ECR (*(RoReg*)0xF000C020U) /**< \brief (CAN0) Error Counter Register */ +#define REG_CAN0_TCR (*(WoReg*)0xF000C024U) /**< \brief (CAN0) Transfer Command Register */ +#define REG_CAN0_ACR (*(WoReg*)0xF000C028U) /**< \brief (CAN0) Abort Command Register */ +#define REG_CAN0_WPMR (*(RwReg*)0xF000C0E4U) /**< \brief (CAN0) Write Protect Mode Register */ +#define REG_CAN0_WPSR (*(RoReg*)0xF000C0E8U) /**< \brief (CAN0) Write Protect Status Register */ +#define REG_CAN0_MMR0 (*(RwReg*)0xF000C200U) /**< \brief (CAN0) Mailbox Mode Register (MB = 0) */ +#define REG_CAN0_MAM0 (*(RwReg*)0xF000C204U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 0) */ +#define REG_CAN0_MID0 (*(RwReg*)0xF000C208U) /**< \brief (CAN0) Mailbox ID Register (MB = 0) */ +#define REG_CAN0_MFID0 (*(RoReg*)0xF000C20CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 0) */ +#define REG_CAN0_MSR0 (*(RoReg*)0xF000C210U) /**< \brief (CAN0) Mailbox Status Register (MB = 0) */ +#define REG_CAN0_MDL0 (*(RwReg*)0xF000C214U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 0) */ +#define REG_CAN0_MDH0 (*(RwReg*)0xF000C218U) /**< \brief (CAN0) Mailbox Data High Register (MB = 0) */ +#define REG_CAN0_MCR0 (*(WoReg*)0xF000C21CU) /**< \brief (CAN0) Mailbox Control Register (MB = 0) */ +#define REG_CAN0_MMR1 (*(RwReg*)0xF000C220U) /**< \brief (CAN0) Mailbox Mode Register (MB = 1) */ +#define REG_CAN0_MAM1 (*(RwReg*)0xF000C224U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 1) */ +#define REG_CAN0_MID1 (*(RwReg*)0xF000C228U) /**< \brief (CAN0) Mailbox ID Register (MB = 1) */ +#define REG_CAN0_MFID1 (*(RoReg*)0xF000C22CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 1) */ +#define REG_CAN0_MSR1 (*(RoReg*)0xF000C230U) /**< \brief (CAN0) Mailbox Status Register (MB = 1) */ +#define REG_CAN0_MDL1 (*(RwReg*)0xF000C234U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 1) */ +#define REG_CAN0_MDH1 (*(RwReg*)0xF000C238U) /**< \brief (CAN0) Mailbox Data High Register (MB = 1) */ +#define REG_CAN0_MCR1 (*(WoReg*)0xF000C23CU) /**< \brief (CAN0) Mailbox Control Register (MB = 1) */ +#define REG_CAN0_MMR2 (*(RwReg*)0xF000C240U) /**< \brief (CAN0) Mailbox Mode Register (MB = 2) */ +#define REG_CAN0_MAM2 (*(RwReg*)0xF000C244U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 2) */ +#define REG_CAN0_MID2 (*(RwReg*)0xF000C248U) /**< \brief (CAN0) Mailbox ID Register (MB = 2) */ +#define REG_CAN0_MFID2 (*(RoReg*)0xF000C24CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 2) */ +#define REG_CAN0_MSR2 (*(RoReg*)0xF000C250U) /**< \brief (CAN0) Mailbox Status Register (MB = 2) */ +#define REG_CAN0_MDL2 (*(RwReg*)0xF000C254U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 2) */ +#define REG_CAN0_MDH2 (*(RwReg*)0xF000C258U) /**< \brief (CAN0) Mailbox Data High Register (MB = 2) */ +#define REG_CAN0_MCR2 (*(WoReg*)0xF000C25CU) /**< \brief (CAN0) Mailbox Control Register (MB = 2) */ +#define REG_CAN0_MMR3 (*(RwReg*)0xF000C260U) /**< \brief (CAN0) Mailbox Mode Register (MB = 3) */ +#define REG_CAN0_MAM3 (*(RwReg*)0xF000C264U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 3) */ +#define REG_CAN0_MID3 (*(RwReg*)0xF000C268U) /**< \brief (CAN0) Mailbox ID Register (MB = 3) */ +#define REG_CAN0_MFID3 (*(RoReg*)0xF000C26CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 3) */ +#define REG_CAN0_MSR3 (*(RoReg*)0xF000C270U) /**< \brief (CAN0) Mailbox Status Register (MB = 3) */ +#define REG_CAN0_MDL3 (*(RwReg*)0xF000C274U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 3) */ +#define REG_CAN0_MDH3 (*(RwReg*)0xF000C278U) /**< \brief (CAN0) Mailbox Data High Register (MB = 3) */ +#define REG_CAN0_MCR3 (*(WoReg*)0xF000C27CU) /**< \brief (CAN0) Mailbox Control Register (MB = 3) */ +#define REG_CAN0_MMR4 (*(RwReg*)0xF000C280U) /**< \brief (CAN0) Mailbox Mode Register (MB = 4) */ +#define REG_CAN0_MAM4 (*(RwReg*)0xF000C284U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 4) */ +#define REG_CAN0_MID4 (*(RwReg*)0xF000C288U) /**< \brief (CAN0) Mailbox ID Register (MB = 4) */ +#define REG_CAN0_MFID4 (*(RoReg*)0xF000C28CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 4) */ +#define REG_CAN0_MSR4 (*(RoReg*)0xF000C290U) /**< \brief (CAN0) Mailbox Status Register (MB = 4) */ +#define REG_CAN0_MDL4 (*(RwReg*)0xF000C294U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 4) */ +#define REG_CAN0_MDH4 (*(RwReg*)0xF000C298U) /**< \brief (CAN0) Mailbox Data High Register (MB = 4) */ +#define REG_CAN0_MCR4 (*(WoReg*)0xF000C29CU) /**< \brief (CAN0) Mailbox Control Register (MB = 4) */ +#define REG_CAN0_MMR5 (*(RwReg*)0xF000C2A0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 5) */ +#define REG_CAN0_MAM5 (*(RwReg*)0xF000C2A4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 5) */ +#define REG_CAN0_MID5 (*(RwReg*)0xF000C2A8U) /**< \brief (CAN0) Mailbox ID Register (MB = 5) */ +#define REG_CAN0_MFID5 (*(RoReg*)0xF000C2ACU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 5) */ +#define REG_CAN0_MSR5 (*(RoReg*)0xF000C2B0U) /**< \brief (CAN0) Mailbox Status Register (MB = 5) */ +#define REG_CAN0_MDL5 (*(RwReg*)0xF000C2B4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 5) */ +#define REG_CAN0_MDH5 (*(RwReg*)0xF000C2B8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 5) */ +#define REG_CAN0_MCR5 (*(WoReg*)0xF000C2BCU) /**< \brief (CAN0) Mailbox Control Register (MB = 5) */ +#define REG_CAN0_MMR6 (*(RwReg*)0xF000C2C0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 6) */ +#define REG_CAN0_MAM6 (*(RwReg*)0xF000C2C4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 6) */ +#define REG_CAN0_MID6 (*(RwReg*)0xF000C2C8U) /**< \brief (CAN0) Mailbox ID Register (MB = 6) */ +#define REG_CAN0_MFID6 (*(RoReg*)0xF000C2CCU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 6) */ +#define REG_CAN0_MSR6 (*(RoReg*)0xF000C2D0U) /**< \brief (CAN0) Mailbox Status Register (MB = 6) */ +#define REG_CAN0_MDL6 (*(RwReg*)0xF000C2D4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 6) */ +#define REG_CAN0_MDH6 (*(RwReg*)0xF000C2D8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 6) */ +#define REG_CAN0_MCR6 (*(WoReg*)0xF000C2DCU) /**< \brief (CAN0) Mailbox Control Register (MB = 6) */ +#define REG_CAN0_MMR7 (*(RwReg*)0xF000C2E0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 7) */ +#define REG_CAN0_MAM7 (*(RwReg*)0xF000C2E4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 7) */ +#define REG_CAN0_MID7 (*(RwReg*)0xF000C2E8U) /**< \brief (CAN0) Mailbox ID Register (MB = 7) */ +#define REG_CAN0_MFID7 (*(RoReg*)0xF000C2ECU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 7) */ +#define REG_CAN0_MSR7 (*(RoReg*)0xF000C2F0U) /**< \brief (CAN0) Mailbox Status Register (MB = 7) */ +#define REG_CAN0_MDL7 (*(RwReg*)0xF000C2F4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 7) */ +#define REG_CAN0_MDH7 (*(RwReg*)0xF000C2F8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 7) */ +#define REG_CAN0_MCR7 (*(WoReg*)0xF000C2FCU) /**< \brief (CAN0) Mailbox Control Register (MB = 7) */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_CAN0_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_can1.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_can1.h new file mode 100644 index 0000000..1c6f460 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_can1.h
@@ -0,0 +1,192 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_CAN1_INSTANCE_ +#define _SAMA5_CAN1_INSTANCE_ + +/* ========== Register definition for CAN1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_CAN1_MR (0xF8010000U) /**< \brief (CAN1) Mode Register */ +#define REG_CAN1_IER (0xF8010004U) /**< \brief (CAN1) Interrupt Enable Register */ +#define REG_CAN1_IDR (0xF8010008U) /**< \brief (CAN1) Interrupt Disable Register */ +#define REG_CAN1_IMR (0xF801000CU) /**< \brief (CAN1) Interrupt Mask Register */ +#define REG_CAN1_SR (0xF8010010U) /**< \brief (CAN1) Status Register */ +#define REG_CAN1_BR (0xF8010014U) /**< \brief (CAN1) Baudrate Register */ +#define REG_CAN1_TIM (0xF8010018U) /**< \brief (CAN1) Timer Register */ +#define REG_CAN1_TIMESTP (0xF801001CU) /**< \brief (CAN1) Timestamp Register */ +#define REG_CAN1_ECR (0xF8010020U) /**< \brief (CAN1) Error Counter Register */ +#define REG_CAN1_TCR (0xF8010024U) /**< \brief (CAN1) Transfer Command Register */ +#define REG_CAN1_ACR (0xF8010028U) /**< \brief (CAN1) Abort Command Register */ +#define REG_CAN1_WPMR (0xF80100E4U) /**< \brief (CAN1) Write Protect Mode Register */ +#define REG_CAN1_WPSR (0xF80100E8U) /**< \brief (CAN1) Write Protect Status Register */ +#define REG_CAN1_MMR0 (0xF8010200U) /**< \brief (CAN1) Mailbox Mode Register (MB = 0) */ +#define REG_CAN1_MAM0 (0xF8010204U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 0) */ +#define REG_CAN1_MID0 (0xF8010208U) /**< \brief (CAN1) Mailbox ID Register (MB = 0) */ +#define REG_CAN1_MFID0 (0xF801020CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 0) */ +#define REG_CAN1_MSR0 (0xF8010210U) /**< \brief (CAN1) Mailbox Status Register (MB = 0) */ +#define REG_CAN1_MDL0 (0xF8010214U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 0) */ +#define REG_CAN1_MDH0 (0xF8010218U) /**< \brief (CAN1) Mailbox Data High Register (MB = 0) */ +#define REG_CAN1_MCR0 (0xF801021CU) /**< \brief (CAN1) Mailbox Control Register (MB = 0) */ +#define REG_CAN1_MMR1 (0xF8010220U) /**< \brief (CAN1) Mailbox Mode Register (MB = 1) */ +#define REG_CAN1_MAM1 (0xF8010224U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 1) */ +#define REG_CAN1_MID1 (0xF8010228U) /**< \brief (CAN1) Mailbox ID Register (MB = 1) */ +#define REG_CAN1_MFID1 (0xF801022CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 1) */ +#define REG_CAN1_MSR1 (0xF8010230U) /**< \brief (CAN1) Mailbox Status Register (MB = 1) */ +#define REG_CAN1_MDL1 (0xF8010234U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 1) */ +#define REG_CAN1_MDH1 (0xF8010238U) /**< \brief (CAN1) Mailbox Data High Register (MB = 1) */ +#define REG_CAN1_MCR1 (0xF801023CU) /**< \brief (CAN1) Mailbox Control Register (MB = 1) */ +#define REG_CAN1_MMR2 (0xF8010240U) /**< \brief (CAN1) Mailbox Mode Register (MB = 2) */ +#define REG_CAN1_MAM2 (0xF8010244U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 2) */ +#define REG_CAN1_MID2 (0xF8010248U) /**< \brief (CAN1) Mailbox ID Register (MB = 2) */ +#define REG_CAN1_MFID2 (0xF801024CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 2) */ +#define REG_CAN1_MSR2 (0xF8010250U) /**< \brief (CAN1) Mailbox Status Register (MB = 2) */ +#define REG_CAN1_MDL2 (0xF8010254U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 2) */ +#define REG_CAN1_MDH2 (0xF8010258U) /**< \brief (CAN1) Mailbox Data High Register (MB = 2) */ +#define REG_CAN1_MCR2 (0xF801025CU) /**< \brief (CAN1) Mailbox Control Register (MB = 2) */ +#define REG_CAN1_MMR3 (0xF8010260U) /**< \brief (CAN1) Mailbox Mode Register (MB = 3) */ +#define REG_CAN1_MAM3 (0xF8010264U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 3) */ +#define REG_CAN1_MID3 (0xF8010268U) /**< \brief (CAN1) Mailbox ID Register (MB = 3) */ +#define REG_CAN1_MFID3 (0xF801026CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 3) */ +#define REG_CAN1_MSR3 (0xF8010270U) /**< \brief (CAN1) Mailbox Status Register (MB = 3) */ +#define REG_CAN1_MDL3 (0xF8010274U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 3) */ +#define REG_CAN1_MDH3 (0xF8010278U) /**< \brief (CAN1) Mailbox Data High Register (MB = 3) */ +#define REG_CAN1_MCR3 (0xF801027CU) /**< \brief (CAN1) Mailbox Control Register (MB = 3) */ +#define REG_CAN1_MMR4 (0xF8010280U) /**< \brief (CAN1) Mailbox Mode Register (MB = 4) */ +#define REG_CAN1_MAM4 (0xF8010284U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 4) */ +#define REG_CAN1_MID4 (0xF8010288U) /**< \brief (CAN1) Mailbox ID Register (MB = 4) */ +#define REG_CAN1_MFID4 (0xF801028CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 4) */ +#define REG_CAN1_MSR4 (0xF8010290U) /**< \brief (CAN1) Mailbox Status Register (MB = 4) */ +#define REG_CAN1_MDL4 (0xF8010294U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 4) */ +#define REG_CAN1_MDH4 (0xF8010298U) /**< \brief (CAN1) Mailbox Data High Register (MB = 4) */ +#define REG_CAN1_MCR4 (0xF801029CU) /**< \brief (CAN1) Mailbox Control Register (MB = 4) */ +#define REG_CAN1_MMR5 (0xF80102A0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 5) */ +#define REG_CAN1_MAM5 (0xF80102A4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 5) */ +#define REG_CAN1_MID5 (0xF80102A8U) /**< \brief (CAN1) Mailbox ID Register (MB = 5) */ +#define REG_CAN1_MFID5 (0xF80102ACU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 5) */ +#define REG_CAN1_MSR5 (0xF80102B0U) /**< \brief (CAN1) Mailbox Status Register (MB = 5) */ +#define REG_CAN1_MDL5 (0xF80102B4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 5) */ +#define REG_CAN1_MDH5 (0xF80102B8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 5) */ +#define REG_CAN1_MCR5 (0xF80102BCU) /**< \brief (CAN1) Mailbox Control Register (MB = 5) */ +#define REG_CAN1_MMR6 (0xF80102C0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 6) */ +#define REG_CAN1_MAM6 (0xF80102C4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 6) */ +#define REG_CAN1_MID6 (0xF80102C8U) /**< \brief (CAN1) Mailbox ID Register (MB = 6) */ +#define REG_CAN1_MFID6 (0xF80102CCU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 6) */ +#define REG_CAN1_MSR6 (0xF80102D0U) /**< \brief (CAN1) Mailbox Status Register (MB = 6) */ +#define REG_CAN1_MDL6 (0xF80102D4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 6) */ +#define REG_CAN1_MDH6 (0xF80102D8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 6) */ +#define REG_CAN1_MCR6 (0xF80102DCU) /**< \brief (CAN1) Mailbox Control Register (MB = 6) */ +#define REG_CAN1_MMR7 (0xF80102E0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 7) */ +#define REG_CAN1_MAM7 (0xF80102E4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 7) */ +#define REG_CAN1_MID7 (0xF80102E8U) /**< \brief (CAN1) Mailbox ID Register (MB = 7) */ +#define REG_CAN1_MFID7 (0xF80102ECU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 7) */ +#define REG_CAN1_MSR7 (0xF80102F0U) /**< \brief (CAN1) Mailbox Status Register (MB = 7) */ +#define REG_CAN1_MDL7 (0xF80102F4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 7) */ +#define REG_CAN1_MDH7 (0xF80102F8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 7) */ +#define REG_CAN1_MCR7 (0xF80102FCU) /**< \brief (CAN1) Mailbox Control Register (MB = 7) */ +#else +#define REG_CAN1_MR (*(RwReg*)0xF8010000U) /**< \brief (CAN1) Mode Register */ +#define REG_CAN1_IER (*(WoReg*)0xF8010004U) /**< \brief (CAN1) Interrupt Enable Register */ +#define REG_CAN1_IDR (*(WoReg*)0xF8010008U) /**< \brief (CAN1) Interrupt Disable Register */ +#define REG_CAN1_IMR (*(RoReg*)0xF801000CU) /**< \brief (CAN1) Interrupt Mask Register */ +#define REG_CAN1_SR (*(RoReg*)0xF8010010U) /**< \brief (CAN1) Status Register */ +#define REG_CAN1_BR (*(RwReg*)0xF8010014U) /**< \brief (CAN1) Baudrate Register */ +#define REG_CAN1_TIM (*(RoReg*)0xF8010018U) /**< \brief (CAN1) Timer Register */ +#define REG_CAN1_TIMESTP (*(RoReg*)0xF801001CU) /**< \brief (CAN1) Timestamp Register */ +#define REG_CAN1_ECR (*(RoReg*)0xF8010020U) /**< \brief (CAN1) Error Counter Register */ +#define REG_CAN1_TCR (*(WoReg*)0xF8010024U) /**< \brief (CAN1) Transfer Command Register */ +#define REG_CAN1_ACR (*(WoReg*)0xF8010028U) /**< \brief (CAN1) Abort Command Register */ +#define REG_CAN1_WPMR (*(RwReg*)0xF80100E4U) /**< \brief (CAN1) Write Protect Mode Register */ +#define REG_CAN1_WPSR (*(RoReg*)0xF80100E8U) /**< \brief (CAN1) Write Protect Status Register */ +#define REG_CAN1_MMR0 (*(RwReg*)0xF8010200U) /**< \brief (CAN1) Mailbox Mode Register (MB = 0) */ +#define REG_CAN1_MAM0 (*(RwReg*)0xF8010204U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 0) */ +#define REG_CAN1_MID0 (*(RwReg*)0xF8010208U) /**< \brief (CAN1) Mailbox ID Register (MB = 0) */ +#define REG_CAN1_MFID0 (*(RoReg*)0xF801020CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 0) */ +#define REG_CAN1_MSR0 (*(RoReg*)0xF8010210U) /**< \brief (CAN1) Mailbox Status Register (MB = 0) */ +#define REG_CAN1_MDL0 (*(RwReg*)0xF8010214U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 0) */ +#define REG_CAN1_MDH0 (*(RwReg*)0xF8010218U) /**< \brief (CAN1) Mailbox Data High Register (MB = 0) */ +#define REG_CAN1_MCR0 (*(WoReg*)0xF801021CU) /**< \brief (CAN1) Mailbox Control Register (MB = 0) */ +#define REG_CAN1_MMR1 (*(RwReg*)0xF8010220U) /**< \brief (CAN1) Mailbox Mode Register (MB = 1) */ +#define REG_CAN1_MAM1 (*(RwReg*)0xF8010224U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 1) */ +#define REG_CAN1_MID1 (*(RwReg*)0xF8010228U) /**< \brief (CAN1) Mailbox ID Register (MB = 1) */ +#define REG_CAN1_MFID1 (*(RoReg*)0xF801022CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 1) */ +#define REG_CAN1_MSR1 (*(RoReg*)0xF8010230U) /**< \brief (CAN1) Mailbox Status Register (MB = 1) */ +#define REG_CAN1_MDL1 (*(RwReg*)0xF8010234U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 1) */ +#define REG_CAN1_MDH1 (*(RwReg*)0xF8010238U) /**< \brief (CAN1) Mailbox Data High Register (MB = 1) */ +#define REG_CAN1_MCR1 (*(WoReg*)0xF801023CU) /**< \brief (CAN1) Mailbox Control Register (MB = 1) */ +#define REG_CAN1_MMR2 (*(RwReg*)0xF8010240U) /**< \brief (CAN1) Mailbox Mode Register (MB = 2) */ +#define REG_CAN1_MAM2 (*(RwReg*)0xF8010244U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 2) */ +#define REG_CAN1_MID2 (*(RwReg*)0xF8010248U) /**< \brief (CAN1) Mailbox ID Register (MB = 2) */ +#define REG_CAN1_MFID2 (*(RoReg*)0xF801024CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 2) */ +#define REG_CAN1_MSR2 (*(RoReg*)0xF8010250U) /**< \brief (CAN1) Mailbox Status Register (MB = 2) */ +#define REG_CAN1_MDL2 (*(RwReg*)0xF8010254U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 2) */ +#define REG_CAN1_MDH2 (*(RwReg*)0xF8010258U) /**< \brief (CAN1) Mailbox Data High Register (MB = 2) */ +#define REG_CAN1_MCR2 (*(WoReg*)0xF801025CU) /**< \brief (CAN1) Mailbox Control Register (MB = 2) */ +#define REG_CAN1_MMR3 (*(RwReg*)0xF8010260U) /**< \brief (CAN1) Mailbox Mode Register (MB = 3) */ +#define REG_CAN1_MAM3 (*(RwReg*)0xF8010264U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 3) */ +#define REG_CAN1_MID3 (*(RwReg*)0xF8010268U) /**< \brief (CAN1) Mailbox ID Register (MB = 3) */ +#define REG_CAN1_MFID3 (*(RoReg*)0xF801026CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 3) */ +#define REG_CAN1_MSR3 (*(RoReg*)0xF8010270U) /**< \brief (CAN1) Mailbox Status Register (MB = 3) */ +#define REG_CAN1_MDL3 (*(RwReg*)0xF8010274U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 3) */ +#define REG_CAN1_MDH3 (*(RwReg*)0xF8010278U) /**< \brief (CAN1) Mailbox Data High Register (MB = 3) */ +#define REG_CAN1_MCR3 (*(WoReg*)0xF801027CU) /**< \brief (CAN1) Mailbox Control Register (MB = 3) */ +#define REG_CAN1_MMR4 (*(RwReg*)0xF8010280U) /**< \brief (CAN1) Mailbox Mode Register (MB = 4) */ +#define REG_CAN1_MAM4 (*(RwReg*)0xF8010284U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 4) */ +#define REG_CAN1_MID4 (*(RwReg*)0xF8010288U) /**< \brief (CAN1) Mailbox ID Register (MB = 4) */ +#define REG_CAN1_MFID4 (*(RoReg*)0xF801028CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 4) */ +#define REG_CAN1_MSR4 (*(RoReg*)0xF8010290U) /**< \brief (CAN1) Mailbox Status Register (MB = 4) */ +#define REG_CAN1_MDL4 (*(RwReg*)0xF8010294U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 4) */ +#define REG_CAN1_MDH4 (*(RwReg*)0xF8010298U) /**< \brief (CAN1) Mailbox Data High Register (MB = 4) */ +#define REG_CAN1_MCR4 (*(WoReg*)0xF801029CU) /**< \brief (CAN1) Mailbox Control Register (MB = 4) */ +#define REG_CAN1_MMR5 (*(RwReg*)0xF80102A0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 5) */ +#define REG_CAN1_MAM5 (*(RwReg*)0xF80102A4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 5) */ +#define REG_CAN1_MID5 (*(RwReg*)0xF80102A8U) /**< \brief (CAN1) Mailbox ID Register (MB = 5) */ +#define REG_CAN1_MFID5 (*(RoReg*)0xF80102ACU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 5) */ +#define REG_CAN1_MSR5 (*(RoReg*)0xF80102B0U) /**< \brief (CAN1) Mailbox Status Register (MB = 5) */ +#define REG_CAN1_MDL5 (*(RwReg*)0xF80102B4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 5) */ +#define REG_CAN1_MDH5 (*(RwReg*)0xF80102B8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 5) */ +#define REG_CAN1_MCR5 (*(WoReg*)0xF80102BCU) /**< \brief (CAN1) Mailbox Control Register (MB = 5) */ +#define REG_CAN1_MMR6 (*(RwReg*)0xF80102C0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 6) */ +#define REG_CAN1_MAM6 (*(RwReg*)0xF80102C4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 6) */ +#define REG_CAN1_MID6 (*(RwReg*)0xF80102C8U) /**< \brief (CAN1) Mailbox ID Register (MB = 6) */ +#define REG_CAN1_MFID6 (*(RoReg*)0xF80102CCU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 6) */ +#define REG_CAN1_MSR6 (*(RoReg*)0xF80102D0U) /**< \brief (CAN1) Mailbox Status Register (MB = 6) */ +#define REG_CAN1_MDL6 (*(RwReg*)0xF80102D4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 6) */ +#define REG_CAN1_MDH6 (*(RwReg*)0xF80102D8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 6) */ +#define REG_CAN1_MCR6 (*(WoReg*)0xF80102DCU) /**< \brief (CAN1) Mailbox Control Register (MB = 6) */ +#define REG_CAN1_MMR7 (*(RwReg*)0xF80102E0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 7) */ +#define REG_CAN1_MAM7 (*(RwReg*)0xF80102E4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 7) */ +#define REG_CAN1_MID7 (*(RwReg*)0xF80102E8U) /**< \brief (CAN1) Mailbox ID Register (MB = 7) */ +#define REG_CAN1_MFID7 (*(RoReg*)0xF80102ECU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 7) */ +#define REG_CAN1_MSR7 (*(RoReg*)0xF80102F0U) /**< \brief (CAN1) Mailbox Status Register (MB = 7) */ +#define REG_CAN1_MDL7 (*(RwReg*)0xF80102F4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 7) */ +#define REG_CAN1_MDH7 (*(RwReg*)0xF80102F8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 7) */ +#define REG_CAN1_MCR7 (*(WoReg*)0xF80102FCU) /**< \brief (CAN1) Mailbox Control Register (MB = 7) */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_CAN1_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_dbgu.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_dbgu.h new file mode 100644 index 0000000..475fb24 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_dbgu.h
@@ -0,0 +1,62 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_DBGU_INSTANCE_ +#define _SAMA5_DBGU_INSTANCE_ + +/* ========== Register definition for DBGU peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_DBGU_CR (0xFFFFEE00U) /**< \brief (DBGU) Control Register */ +#define REG_DBGU_MR (0xFFFFEE04U) /**< \brief (DBGU) Mode Register */ +#define REG_DBGU_IER (0xFFFFEE08U) /**< \brief (DBGU) Interrupt Enable Register */ +#define REG_DBGU_IDR (0xFFFFEE0CU) /**< \brief (DBGU) Interrupt Disable Register */ +#define REG_DBGU_IMR (0xFFFFEE10U) /**< \brief (DBGU) Interrupt Mask Register */ +#define REG_DBGU_SR (0xFFFFEE14U) /**< \brief (DBGU) Status Register */ +#define REG_DBGU_RHR (0xFFFFEE18U) /**< \brief (DBGU) Receive Holding Register */ +#define REG_DBGU_THR (0xFFFFEE1CU) /**< \brief (DBGU) Transmit Holding Register */ +#define REG_DBGU_BRGR (0xFFFFEE20U) /**< \brief (DBGU) Baud Rate Generator Register */ +#define REG_DBGU_CIDR (0xFFFFEE40U) /**< \brief (DBGU) Chip ID Register */ +#define REG_DBGU_EXID (0xFFFFEE44U) /**< \brief (DBGU) Chip ID Extension Register */ +#define REG_DBGU_FNR (0xFFFFEE48U) /**< \brief (DBGU) Force NTRST Register */ +#else +#define REG_DBGU_CR (*(WoReg*)0xFFFFEE00U) /**< \brief (DBGU) Control Register */ +#define REG_DBGU_MR (*(RwReg*)0xFFFFEE04U) /**< \brief (DBGU) Mode Register */ +#define REG_DBGU_IER (*(WoReg*)0xFFFFEE08U) /**< \brief (DBGU) Interrupt Enable Register */ +#define REG_DBGU_IDR (*(WoReg*)0xFFFFEE0CU) /**< \brief (DBGU) Interrupt Disable Register */ +#define REG_DBGU_IMR (*(RoReg*)0xFFFFEE10U) /**< \brief (DBGU) Interrupt Mask Register */ +#define REG_DBGU_SR (*(RoReg*)0xFFFFEE14U) /**< \brief (DBGU) Status Register */ +#define REG_DBGU_RHR (*(RoReg*)0xFFFFEE18U) /**< \brief (DBGU) Receive Holding Register */ +#define REG_DBGU_THR (*(WoReg*)0xFFFFEE1CU) /**< \brief (DBGU) Transmit Holding Register */ +#define REG_DBGU_BRGR (*(RwReg*)0xFFFFEE20U) /**< \brief (DBGU) Baud Rate Generator Register */ +#define REG_DBGU_CIDR (*(RoReg*)0xFFFFEE40U) /**< \brief (DBGU) Chip ID Register */ +#define REG_DBGU_EXID (*(RoReg*)0xFFFFEE44U) /**< \brief (DBGU) Chip ID Extension Register */ +#define REG_DBGU_FNR (*(RwReg*)0xFFFFEE48U) /**< \brief (DBGU) Force NTRST Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_DBGU_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_dmac0.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_dmac0.h new file mode 100644 index 0000000..97e9103 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_dmac0.h
@@ -0,0 +1,194 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_DMAC0_INSTANCE_ +#define _SAMA5_DMAC0_INSTANCE_ + +/* ========== Register definition for DMAC0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_DMAC0_GCFG (0xFFFFE600U) /**< \brief (DMAC0) DMAC Global Configuration Register */ +#define REG_DMAC0_EN (0xFFFFE604U) /**< \brief (DMAC0) DMAC Enable Register */ +#define REG_DMAC0_SREQ (0xFFFFE608U) /**< \brief (DMAC0) DMAC Software Single Request Register */ +#define REG_DMAC0_CREQ (0xFFFFE60CU) /**< \brief (DMAC0) DMAC Software Chunk Transfer Request Register */ +#define REG_DMAC0_LAST (0xFFFFE610U) /**< \brief (DMAC0) DMAC Software Last Transfer Flag Register */ +#define REG_DMAC0_EBCIER (0xFFFFE618U) /**< \brief (DMAC0) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */ +#define REG_DMAC0_EBCIDR (0xFFFFE61CU) /**< \brief (DMAC0) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */ +#define REG_DMAC0_EBCIMR (0xFFFFE620U) /**< \brief (DMAC0) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */ +#define REG_DMAC0_EBCISR (0xFFFFE624U) /**< \brief (DMAC0) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */ +#define REG_DMAC0_CHER (0xFFFFE628U) /**< \brief (DMAC0) DMAC Channel Handler Enable Register */ +#define REG_DMAC0_CHDR (0xFFFFE62CU) /**< \brief (DMAC0) DMAC Channel Handler Disable Register */ +#define REG_DMAC0_CHSR (0xFFFFE630U) /**< \brief (DMAC0) DMAC Channel Handler Status Register */ +#define REG_DMAC0_SADDR0 (0xFFFFE63CU) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 0) */ +#define REG_DMAC0_DADDR0 (0xFFFFE640U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 0) */ +#define REG_DMAC0_DSCR0 (0xFFFFE644U) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 0) */ +#define REG_DMAC0_CTRLA0 (0xFFFFE648U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 0) */ +#define REG_DMAC0_CTRLB0 (0xFFFFE64CU) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 0) */ +#define REG_DMAC0_CFG0 (0xFFFFE650U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 0) */ +#define REG_DMAC0_SPIP0 (0xFFFFE654U) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 0) */ +#define REG_DMAC0_DPIP0 (0xFFFFE658U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 0) */ +#define REG_DMAC0_SADDR1 (0xFFFFE664U) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 1) */ +#define REG_DMAC0_DADDR1 (0xFFFFE668U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 1) */ +#define REG_DMAC0_DSCR1 (0xFFFFE66CU) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 1) */ +#define REG_DMAC0_CTRLA1 (0xFFFFE670U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 1) */ +#define REG_DMAC0_CTRLB1 (0xFFFFE674U) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 1) */ +#define REG_DMAC0_CFG1 (0xFFFFE678U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 1) */ +#define REG_DMAC0_SPIP1 (0xFFFFE67CU) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 1) */ +#define REG_DMAC0_DPIP1 (0xFFFFE680U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 1) */ +#define REG_DMAC0_SADDR2 (0xFFFFE68CU) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 2) */ +#define REG_DMAC0_DADDR2 (0xFFFFE690U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 2) */ +#define REG_DMAC0_DSCR2 (0xFFFFE694U) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 2) */ +#define REG_DMAC0_CTRLA2 (0xFFFFE698U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 2) */ +#define REG_DMAC0_CTRLB2 (0xFFFFE69CU) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 2) */ +#define REG_DMAC0_CFG2 (0xFFFFE6A0U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 2) */ +#define REG_DMAC0_SPIP2 (0xFFFFE6A4U) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 2) */ +#define REG_DMAC0_DPIP2 (0xFFFFE6A8U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 2) */ +#define REG_DMAC0_SADDR3 (0xFFFFE6B4U) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 3) */ +#define REG_DMAC0_DADDR3 (0xFFFFE6B8U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 3) */ +#define REG_DMAC0_DSCR3 (0xFFFFE6BCU) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 3) */ +#define REG_DMAC0_CTRLA3 (0xFFFFE6C0U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 3) */ +#define REG_DMAC0_CTRLB3 (0xFFFFE6C4U) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 3) */ +#define REG_DMAC0_CFG3 (0xFFFFE6C8U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 3) */ +#define REG_DMAC0_SPIP3 (0xFFFFE6CCU) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 3) */ +#define REG_DMAC0_DPIP3 (0xFFFFE6D0U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 3) */ +#define REG_DMAC0_SADDR4 (0xFFFFE6DCU) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 4) */ +#define REG_DMAC0_DADDR4 (0xFFFFE6E0U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 4) */ +#define REG_DMAC0_DSCR4 (0xFFFFE6E4U) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 4) */ +#define REG_DMAC0_CTRLA4 (0xFFFFE6E8U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 4) */ +#define REG_DMAC0_CTRLB4 (0xFFFFE6ECU) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 4) */ +#define REG_DMAC0_CFG4 (0xFFFFE6F0U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 4) */ +#define REG_DMAC0_SPIP4 (0xFFFFE6F4U) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 4) */ +#define REG_DMAC0_DPIP4 (0xFFFFE6F8U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 4) */ +#define REG_DMAC0_SADDR5 (0xFFFFE704U) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 5) */ +#define REG_DMAC0_DADDR5 (0xFFFFE708U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 5) */ +#define REG_DMAC0_DSCR5 (0xFFFFE70CU) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 5) */ +#define REG_DMAC0_CTRLA5 (0xFFFFE710U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 5) */ +#define REG_DMAC0_CTRLB5 (0xFFFFE714U) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 5) */ +#define REG_DMAC0_CFG5 (0xFFFFE718U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 5) */ +#define REG_DMAC0_SPIP5 (0xFFFFE71CU) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 5) */ +#define REG_DMAC0_DPIP5 (0xFFFFE720U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 5) */ +#define REG_DMAC0_SADDR6 (0xFFFFE72CU) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 6) */ +#define REG_DMAC0_DADDR6 (0xFFFFE730U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 6) */ +#define REG_DMAC0_DSCR6 (0xFFFFE734U) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 6) */ +#define REG_DMAC0_CTRLA6 (0xFFFFE738U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 6) */ +#define REG_DMAC0_CTRLB6 (0xFFFFE73CU) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 6) */ +#define REG_DMAC0_CFG6 (0xFFFFE740U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 6) */ +#define REG_DMAC0_SPIP6 (0xFFFFE744U) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 6) */ +#define REG_DMAC0_DPIP6 (0xFFFFE748U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 6) */ +#define REG_DMAC0_SADDR7 (0xFFFFE754U) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 7) */ +#define REG_DMAC0_DADDR7 (0xFFFFE758U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 7) */ +#define REG_DMAC0_DSCR7 (0xFFFFE75CU) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 7) */ +#define REG_DMAC0_CTRLA7 (0xFFFFE760U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 7) */ +#define REG_DMAC0_CTRLB7 (0xFFFFE764U) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 7) */ +#define REG_DMAC0_CFG7 (0xFFFFE768U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 7) */ +#define REG_DMAC0_SPIP7 (0xFFFFE76CU) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 7) */ +#define REG_DMAC0_DPIP7 (0xFFFFE770U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 7) */ +#define REG_DMAC0_WPMR (0xFFFFE7E4U) /**< \brief (DMAC0) DMAC Write Protect Mode Register */ +#define REG_DMAC0_WPSR (0xFFFFE7E8U) /**< \brief (DMAC0) DMAC Write Protect Status Register */ +#else +#define REG_DMAC0_GCFG (*(RwReg*)0xFFFFE600U) /**< \brief (DMAC0) DMAC Global Configuration Register */ +#define REG_DMAC0_EN (*(RwReg*)0xFFFFE604U) /**< \brief (DMAC0) DMAC Enable Register */ +#define REG_DMAC0_SREQ (*(RwReg*)0xFFFFE608U) /**< \brief (DMAC0) DMAC Software Single Request Register */ +#define REG_DMAC0_CREQ (*(RwReg*)0xFFFFE60CU) /**< \brief (DMAC0) DMAC Software Chunk Transfer Request Register */ +#define REG_DMAC0_LAST (*(RwReg*)0xFFFFE610U) /**< \brief (DMAC0) DMAC Software Last Transfer Flag Register */ +#define REG_DMAC0_EBCIER (*(WoReg*)0xFFFFE618U) /**< \brief (DMAC0) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */ +#define REG_DMAC0_EBCIDR (*(WoReg*)0xFFFFE61CU) /**< \brief (DMAC0) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */ +#define REG_DMAC0_EBCIMR (*(RoReg*)0xFFFFE620U) /**< \brief (DMAC0) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */ +#define REG_DMAC0_EBCISR (*(RoReg*)0xFFFFE624U) /**< \brief (DMAC0) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */ +#define REG_DMAC0_CHER (*(WoReg*)0xFFFFE628U) /**< \brief (DMAC0) DMAC Channel Handler Enable Register */ +#define REG_DMAC0_CHDR (*(WoReg*)0xFFFFE62CU) /**< \brief (DMAC0) DMAC Channel Handler Disable Register */ +#define REG_DMAC0_CHSR (*(RoReg*)0xFFFFE630U) /**< \brief (DMAC0) DMAC Channel Handler Status Register */ +#define REG_DMAC0_SADDR0 (*(RwReg*)0xFFFFE63CU) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 0) */ +#define REG_DMAC0_DADDR0 (*(RwReg*)0xFFFFE640U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 0) */ +#define REG_DMAC0_DSCR0 (*(RwReg*)0xFFFFE644U) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 0) */ +#define REG_DMAC0_CTRLA0 (*(RwReg*)0xFFFFE648U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 0) */ +#define REG_DMAC0_CTRLB0 (*(RwReg*)0xFFFFE64CU) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 0) */ +#define REG_DMAC0_CFG0 (*(RwReg*)0xFFFFE650U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 0) */ +#define REG_DMAC0_SPIP0 (*(RwReg*)0xFFFFE654U) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 0) */ +#define REG_DMAC0_DPIP0 (*(RwReg*)0xFFFFE658U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 0) */ +#define REG_DMAC0_SADDR1 (*(RwReg*)0xFFFFE664U) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 1) */ +#define REG_DMAC0_DADDR1 (*(RwReg*)0xFFFFE668U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 1) */ +#define REG_DMAC0_DSCR1 (*(RwReg*)0xFFFFE66CU) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 1) */ +#define REG_DMAC0_CTRLA1 (*(RwReg*)0xFFFFE670U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 1) */ +#define REG_DMAC0_CTRLB1 (*(RwReg*)0xFFFFE674U) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 1) */ +#define REG_DMAC0_CFG1 (*(RwReg*)0xFFFFE678U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 1) */ +#define REG_DMAC0_SPIP1 (*(RwReg*)0xFFFFE67CU) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 1) */ +#define REG_DMAC0_DPIP1 (*(RwReg*)0xFFFFE680U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 1) */ +#define REG_DMAC0_SADDR2 (*(RwReg*)0xFFFFE68CU) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 2) */ +#define REG_DMAC0_DADDR2 (*(RwReg*)0xFFFFE690U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 2) */ +#define REG_DMAC0_DSCR2 (*(RwReg*)0xFFFFE694U) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 2) */ +#define REG_DMAC0_CTRLA2 (*(RwReg*)0xFFFFE698U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 2) */ +#define REG_DMAC0_CTRLB2 (*(RwReg*)0xFFFFE69CU) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 2) */ +#define REG_DMAC0_CFG2 (*(RwReg*)0xFFFFE6A0U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 2) */ +#define REG_DMAC0_SPIP2 (*(RwReg*)0xFFFFE6A4U) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 2) */ +#define REG_DMAC0_DPIP2 (*(RwReg*)0xFFFFE6A8U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 2) */ +#define REG_DMAC0_SADDR3 (*(RwReg*)0xFFFFE6B4U) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 3) */ +#define REG_DMAC0_DADDR3 (*(RwReg*)0xFFFFE6B8U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 3) */ +#define REG_DMAC0_DSCR3 (*(RwReg*)0xFFFFE6BCU) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 3) */ +#define REG_DMAC0_CTRLA3 (*(RwReg*)0xFFFFE6C0U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 3) */ +#define REG_DMAC0_CTRLB3 (*(RwReg*)0xFFFFE6C4U) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 3) */ +#define REG_DMAC0_CFG3 (*(RwReg*)0xFFFFE6C8U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 3) */ +#define REG_DMAC0_SPIP3 (*(RwReg*)0xFFFFE6CCU) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 3) */ +#define REG_DMAC0_DPIP3 (*(RwReg*)0xFFFFE6D0U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 3) */ +#define REG_DMAC0_SADDR4 (*(RwReg*)0xFFFFE6DCU) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 4) */ +#define REG_DMAC0_DADDR4 (*(RwReg*)0xFFFFE6E0U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 4) */ +#define REG_DMAC0_DSCR4 (*(RwReg*)0xFFFFE6E4U) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 4) */ +#define REG_DMAC0_CTRLA4 (*(RwReg*)0xFFFFE6E8U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 4) */ +#define REG_DMAC0_CTRLB4 (*(RwReg*)0xFFFFE6ECU) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 4) */ +#define REG_DMAC0_CFG4 (*(RwReg*)0xFFFFE6F0U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 4) */ +#define REG_DMAC0_SPIP4 (*(RwReg*)0xFFFFE6F4U) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 4) */ +#define REG_DMAC0_DPIP4 (*(RwReg*)0xFFFFE6F8U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 4) */ +#define REG_DMAC0_SADDR5 (*(RwReg*)0xFFFFE704U) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 5) */ +#define REG_DMAC0_DADDR5 (*(RwReg*)0xFFFFE708U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 5) */ +#define REG_DMAC0_DSCR5 (*(RwReg*)0xFFFFE70CU) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 5) */ +#define REG_DMAC0_CTRLA5 (*(RwReg*)0xFFFFE710U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 5) */ +#define REG_DMAC0_CTRLB5 (*(RwReg*)0xFFFFE714U) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 5) */ +#define REG_DMAC0_CFG5 (*(RwReg*)0xFFFFE718U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 5) */ +#define REG_DMAC0_SPIP5 (*(RwReg*)0xFFFFE71CU) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 5) */ +#define REG_DMAC0_DPIP5 (*(RwReg*)0xFFFFE720U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 5) */ +#define REG_DMAC0_SADDR6 (*(RwReg*)0xFFFFE72CU) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 6) */ +#define REG_DMAC0_DADDR6 (*(RwReg*)0xFFFFE730U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 6) */ +#define REG_DMAC0_DSCR6 (*(RwReg*)0xFFFFE734U) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 6) */ +#define REG_DMAC0_CTRLA6 (*(RwReg*)0xFFFFE738U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 6) */ +#define REG_DMAC0_CTRLB6 (*(RwReg*)0xFFFFE73CU) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 6) */ +#define REG_DMAC0_CFG6 (*(RwReg*)0xFFFFE740U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 6) */ +#define REG_DMAC0_SPIP6 (*(RwReg*)0xFFFFE744U) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 6) */ +#define REG_DMAC0_DPIP6 (*(RwReg*)0xFFFFE748U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 6) */ +#define REG_DMAC0_SADDR7 (*(RwReg*)0xFFFFE754U) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 7) */ +#define REG_DMAC0_DADDR7 (*(RwReg*)0xFFFFE758U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 7) */ +#define REG_DMAC0_DSCR7 (*(RwReg*)0xFFFFE75CU) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 7) */ +#define REG_DMAC0_CTRLA7 (*(RwReg*)0xFFFFE760U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 7) */ +#define REG_DMAC0_CTRLB7 (*(RwReg*)0xFFFFE764U) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 7) */ +#define REG_DMAC0_CFG7 (*(RwReg*)0xFFFFE768U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 7) */ +#define REG_DMAC0_SPIP7 (*(RwReg*)0xFFFFE76CU) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 7) */ +#define REG_DMAC0_DPIP7 (*(RwReg*)0xFFFFE770U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 7) */ +#define REG_DMAC0_WPMR (*(RwReg*)0xFFFFE7E4U) /**< \brief (DMAC0) DMAC Write Protect Mode Register */ +#define REG_DMAC0_WPSR (*(RoReg*)0xFFFFE7E8U) /**< \brief (DMAC0) DMAC Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_DMAC0_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_dmac1.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_dmac1.h new file mode 100644 index 0000000..881dd56 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_dmac1.h
@@ -0,0 +1,194 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_DMAC1_INSTANCE_ +#define _SAMA5_DMAC1_INSTANCE_ + +/* ========== Register definition for DMAC1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_DMAC1_GCFG (0xFFFFE800U) /**< \brief (DMAC1) DMAC Global Configuration Register */ +#define REG_DMAC1_EN (0xFFFFE804U) /**< \brief (DMAC1) DMAC Enable Register */ +#define REG_DMAC1_SREQ (0xFFFFE808U) /**< \brief (DMAC1) DMAC Software Single Request Register */ +#define REG_DMAC1_CREQ (0xFFFFE80CU) /**< \brief (DMAC1) DMAC Software Chunk Transfer Request Register */ +#define REG_DMAC1_LAST (0xFFFFE810U) /**< \brief (DMAC1) DMAC Software Last Transfer Flag Register */ +#define REG_DMAC1_EBCIER (0xFFFFE818U) /**< \brief (DMAC1) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */ +#define REG_DMAC1_EBCIDR (0xFFFFE81CU) /**< \brief (DMAC1) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */ +#define REG_DMAC1_EBCIMR (0xFFFFE820U) /**< \brief (DMAC1) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */ +#define REG_DMAC1_EBCISR (0xFFFFE824U) /**< \brief (DMAC1) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */ +#define REG_DMAC1_CHER (0xFFFFE828U) /**< \brief (DMAC1) DMAC Channel Handler Enable Register */ +#define REG_DMAC1_CHDR (0xFFFFE82CU) /**< \brief (DMAC1) DMAC Channel Handler Disable Register */ +#define REG_DMAC1_CHSR (0xFFFFE830U) /**< \brief (DMAC1) DMAC Channel Handler Status Register */ +#define REG_DMAC1_SADDR0 (0xFFFFE83CU) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 0) */ +#define REG_DMAC1_DADDR0 (0xFFFFE840U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 0) */ +#define REG_DMAC1_DSCR0 (0xFFFFE844U) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 0) */ +#define REG_DMAC1_CTRLA0 (0xFFFFE848U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 0) */ +#define REG_DMAC1_CTRLB0 (0xFFFFE84CU) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 0) */ +#define REG_DMAC1_CFG0 (0xFFFFE850U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 0) */ +#define REG_DMAC1_SPIP0 (0xFFFFE854U) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 0) */ +#define REG_DMAC1_DPIP0 (0xFFFFE858U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 0) */ +#define REG_DMAC1_SADDR1 (0xFFFFE864U) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 1) */ +#define REG_DMAC1_DADDR1 (0xFFFFE868U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 1) */ +#define REG_DMAC1_DSCR1 (0xFFFFE86CU) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 1) */ +#define REG_DMAC1_CTRLA1 (0xFFFFE870U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 1) */ +#define REG_DMAC1_CTRLB1 (0xFFFFE874U) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 1) */ +#define REG_DMAC1_CFG1 (0xFFFFE878U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 1) */ +#define REG_DMAC1_SPIP1 (0xFFFFE87CU) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 1) */ +#define REG_DMAC1_DPIP1 (0xFFFFE880U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 1) */ +#define REG_DMAC1_SADDR2 (0xFFFFE88CU) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 2) */ +#define REG_DMAC1_DADDR2 (0xFFFFE890U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 2) */ +#define REG_DMAC1_DSCR2 (0xFFFFE894U) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 2) */ +#define REG_DMAC1_CTRLA2 (0xFFFFE898U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 2) */ +#define REG_DMAC1_CTRLB2 (0xFFFFE89CU) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 2) */ +#define REG_DMAC1_CFG2 (0xFFFFE8A0U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 2) */ +#define REG_DMAC1_SPIP2 (0xFFFFE8A4U) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 2) */ +#define REG_DMAC1_DPIP2 (0xFFFFE8A8U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 2) */ +#define REG_DMAC1_SADDR3 (0xFFFFE8B4U) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 3) */ +#define REG_DMAC1_DADDR3 (0xFFFFE8B8U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 3) */ +#define REG_DMAC1_DSCR3 (0xFFFFE8BCU) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 3) */ +#define REG_DMAC1_CTRLA3 (0xFFFFE8C0U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 3) */ +#define REG_DMAC1_CTRLB3 (0xFFFFE8C4U) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 3) */ +#define REG_DMAC1_CFG3 (0xFFFFE8C8U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 3) */ +#define REG_DMAC1_SPIP3 (0xFFFFE8CCU) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 3) */ +#define REG_DMAC1_DPIP3 (0xFFFFE8D0U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 3) */ +#define REG_DMAC1_SADDR4 (0xFFFFE8DCU) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 4) */ +#define REG_DMAC1_DADDR4 (0xFFFFE8E0U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 4) */ +#define REG_DMAC1_DSCR4 (0xFFFFE8E4U) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 4) */ +#define REG_DMAC1_CTRLA4 (0xFFFFE8E8U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 4) */ +#define REG_DMAC1_CTRLB4 (0xFFFFE8ECU) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 4) */ +#define REG_DMAC1_CFG4 (0xFFFFE8F0U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 4) */ +#define REG_DMAC1_SPIP4 (0xFFFFE8F4U) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 4) */ +#define REG_DMAC1_DPIP4 (0xFFFFE8F8U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 4) */ +#define REG_DMAC1_SADDR5 (0xFFFFE904U) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 5) */ +#define REG_DMAC1_DADDR5 (0xFFFFE908U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 5) */ +#define REG_DMAC1_DSCR5 (0xFFFFE90CU) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 5) */ +#define REG_DMAC1_CTRLA5 (0xFFFFE910U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 5) */ +#define REG_DMAC1_CTRLB5 (0xFFFFE914U) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 5) */ +#define REG_DMAC1_CFG5 (0xFFFFE918U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 5) */ +#define REG_DMAC1_SPIP5 (0xFFFFE91CU) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 5) */ +#define REG_DMAC1_DPIP5 (0xFFFFE920U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 5) */ +#define REG_DMAC1_SADDR6 (0xFFFFE92CU) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 6) */ +#define REG_DMAC1_DADDR6 (0xFFFFE930U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 6) */ +#define REG_DMAC1_DSCR6 (0xFFFFE934U) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 6) */ +#define REG_DMAC1_CTRLA6 (0xFFFFE938U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 6) */ +#define REG_DMAC1_CTRLB6 (0xFFFFE93CU) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 6) */ +#define REG_DMAC1_CFG6 (0xFFFFE940U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 6) */ +#define REG_DMAC1_SPIP6 (0xFFFFE944U) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 6) */ +#define REG_DMAC1_DPIP6 (0xFFFFE948U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 6) */ +#define REG_DMAC1_SADDR7 (0xFFFFE954U) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 7) */ +#define REG_DMAC1_DADDR7 (0xFFFFE958U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 7) */ +#define REG_DMAC1_DSCR7 (0xFFFFE95CU) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 7) */ +#define REG_DMAC1_CTRLA7 (0xFFFFE960U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 7) */ +#define REG_DMAC1_CTRLB7 (0xFFFFE964U) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 7) */ +#define REG_DMAC1_CFG7 (0xFFFFE968U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 7) */ +#define REG_DMAC1_SPIP7 (0xFFFFE96CU) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 7) */ +#define REG_DMAC1_DPIP7 (0xFFFFE970U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 7) */ +#define REG_DMAC1_WPMR (0xFFFFE9E4U) /**< \brief (DMAC1) DMAC Write Protect Mode Register */ +#define REG_DMAC1_WPSR (0xFFFFE9E8U) /**< \brief (DMAC1) DMAC Write Protect Status Register */ +#else +#define REG_DMAC1_GCFG (*(RwReg*)0xFFFFE800U) /**< \brief (DMAC1) DMAC Global Configuration Register */ +#define REG_DMAC1_EN (*(RwReg*)0xFFFFE804U) /**< \brief (DMAC1) DMAC Enable Register */ +#define REG_DMAC1_SREQ (*(RwReg*)0xFFFFE808U) /**< \brief (DMAC1) DMAC Software Single Request Register */ +#define REG_DMAC1_CREQ (*(RwReg*)0xFFFFE80CU) /**< \brief (DMAC1) DMAC Software Chunk Transfer Request Register */ +#define REG_DMAC1_LAST (*(RwReg*)0xFFFFE810U) /**< \brief (DMAC1) DMAC Software Last Transfer Flag Register */ +#define REG_DMAC1_EBCIER (*(WoReg*)0xFFFFE818U) /**< \brief (DMAC1) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */ +#define REG_DMAC1_EBCIDR (*(WoReg*)0xFFFFE81CU) /**< \brief (DMAC1) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */ +#define REG_DMAC1_EBCIMR (*(RoReg*)0xFFFFE820U) /**< \brief (DMAC1) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */ +#define REG_DMAC1_EBCISR (*(RoReg*)0xFFFFE824U) /**< \brief (DMAC1) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */ +#define REG_DMAC1_CHER (*(WoReg*)0xFFFFE828U) /**< \brief (DMAC1) DMAC Channel Handler Enable Register */ +#define REG_DMAC1_CHDR (*(WoReg*)0xFFFFE82CU) /**< \brief (DMAC1) DMAC Channel Handler Disable Register */ +#define REG_DMAC1_CHSR (*(RoReg*)0xFFFFE830U) /**< \brief (DMAC1) DMAC Channel Handler Status Register */ +#define REG_DMAC1_SADDR0 (*(RwReg*)0xFFFFE83CU) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 0) */ +#define REG_DMAC1_DADDR0 (*(RwReg*)0xFFFFE840U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 0) */ +#define REG_DMAC1_DSCR0 (*(RwReg*)0xFFFFE844U) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 0) */ +#define REG_DMAC1_CTRLA0 (*(RwReg*)0xFFFFE848U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 0) */ +#define REG_DMAC1_CTRLB0 (*(RwReg*)0xFFFFE84CU) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 0) */ +#define REG_DMAC1_CFG0 (*(RwReg*)0xFFFFE850U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 0) */ +#define REG_DMAC1_SPIP0 (*(RwReg*)0xFFFFE854U) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 0) */ +#define REG_DMAC1_DPIP0 (*(RwReg*)0xFFFFE858U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 0) */ +#define REG_DMAC1_SADDR1 (*(RwReg*)0xFFFFE864U) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 1) */ +#define REG_DMAC1_DADDR1 (*(RwReg*)0xFFFFE868U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 1) */ +#define REG_DMAC1_DSCR1 (*(RwReg*)0xFFFFE86CU) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 1) */ +#define REG_DMAC1_CTRLA1 (*(RwReg*)0xFFFFE870U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 1) */ +#define REG_DMAC1_CTRLB1 (*(RwReg*)0xFFFFE874U) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 1) */ +#define REG_DMAC1_CFG1 (*(RwReg*)0xFFFFE878U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 1) */ +#define REG_DMAC1_SPIP1 (*(RwReg*)0xFFFFE87CU) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 1) */ +#define REG_DMAC1_DPIP1 (*(RwReg*)0xFFFFE880U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 1) */ +#define REG_DMAC1_SADDR2 (*(RwReg*)0xFFFFE88CU) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 2) */ +#define REG_DMAC1_DADDR2 (*(RwReg*)0xFFFFE890U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 2) */ +#define REG_DMAC1_DSCR2 (*(RwReg*)0xFFFFE894U) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 2) */ +#define REG_DMAC1_CTRLA2 (*(RwReg*)0xFFFFE898U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 2) */ +#define REG_DMAC1_CTRLB2 (*(RwReg*)0xFFFFE89CU) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 2) */ +#define REG_DMAC1_CFG2 (*(RwReg*)0xFFFFE8A0U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 2) */ +#define REG_DMAC1_SPIP2 (*(RwReg*)0xFFFFE8A4U) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 2) */ +#define REG_DMAC1_DPIP2 (*(RwReg*)0xFFFFE8A8U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 2) */ +#define REG_DMAC1_SADDR3 (*(RwReg*)0xFFFFE8B4U) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 3) */ +#define REG_DMAC1_DADDR3 (*(RwReg*)0xFFFFE8B8U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 3) */ +#define REG_DMAC1_DSCR3 (*(RwReg*)0xFFFFE8BCU) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 3) */ +#define REG_DMAC1_CTRLA3 (*(RwReg*)0xFFFFE8C0U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 3) */ +#define REG_DMAC1_CTRLB3 (*(RwReg*)0xFFFFE8C4U) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 3) */ +#define REG_DMAC1_CFG3 (*(RwReg*)0xFFFFE8C8U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 3) */ +#define REG_DMAC1_SPIP3 (*(RwReg*)0xFFFFE8CCU) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 3) */ +#define REG_DMAC1_DPIP3 (*(RwReg*)0xFFFFE8D0U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 3) */ +#define REG_DMAC1_SADDR4 (*(RwReg*)0xFFFFE8DCU) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 4) */ +#define REG_DMAC1_DADDR4 (*(RwReg*)0xFFFFE8E0U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 4) */ +#define REG_DMAC1_DSCR4 (*(RwReg*)0xFFFFE8E4U) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 4) */ +#define REG_DMAC1_CTRLA4 (*(RwReg*)0xFFFFE8E8U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 4) */ +#define REG_DMAC1_CTRLB4 (*(RwReg*)0xFFFFE8ECU) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 4) */ +#define REG_DMAC1_CFG4 (*(RwReg*)0xFFFFE8F0U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 4) */ +#define REG_DMAC1_SPIP4 (*(RwReg*)0xFFFFE8F4U) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 4) */ +#define REG_DMAC1_DPIP4 (*(RwReg*)0xFFFFE8F8U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 4) */ +#define REG_DMAC1_SADDR5 (*(RwReg*)0xFFFFE904U) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 5) */ +#define REG_DMAC1_DADDR5 (*(RwReg*)0xFFFFE908U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 5) */ +#define REG_DMAC1_DSCR5 (*(RwReg*)0xFFFFE90CU) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 5) */ +#define REG_DMAC1_CTRLA5 (*(RwReg*)0xFFFFE910U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 5) */ +#define REG_DMAC1_CTRLB5 (*(RwReg*)0xFFFFE914U) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 5) */ +#define REG_DMAC1_CFG5 (*(RwReg*)0xFFFFE918U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 5) */ +#define REG_DMAC1_SPIP5 (*(RwReg*)0xFFFFE91CU) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 5) */ +#define REG_DMAC1_DPIP5 (*(RwReg*)0xFFFFE920U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 5) */ +#define REG_DMAC1_SADDR6 (*(RwReg*)0xFFFFE92CU) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 6) */ +#define REG_DMAC1_DADDR6 (*(RwReg*)0xFFFFE930U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 6) */ +#define REG_DMAC1_DSCR6 (*(RwReg*)0xFFFFE934U) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 6) */ +#define REG_DMAC1_CTRLA6 (*(RwReg*)0xFFFFE938U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 6) */ +#define REG_DMAC1_CTRLB6 (*(RwReg*)0xFFFFE93CU) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 6) */ +#define REG_DMAC1_CFG6 (*(RwReg*)0xFFFFE940U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 6) */ +#define REG_DMAC1_SPIP6 (*(RwReg*)0xFFFFE944U) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 6) */ +#define REG_DMAC1_DPIP6 (*(RwReg*)0xFFFFE948U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 6) */ +#define REG_DMAC1_SADDR7 (*(RwReg*)0xFFFFE954U) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 7) */ +#define REG_DMAC1_DADDR7 (*(RwReg*)0xFFFFE958U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 7) */ +#define REG_DMAC1_DSCR7 (*(RwReg*)0xFFFFE95CU) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 7) */ +#define REG_DMAC1_CTRLA7 (*(RwReg*)0xFFFFE960U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 7) */ +#define REG_DMAC1_CTRLB7 (*(RwReg*)0xFFFFE964U) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 7) */ +#define REG_DMAC1_CFG7 (*(RwReg*)0xFFFFE968U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 7) */ +#define REG_DMAC1_SPIP7 (*(RwReg*)0xFFFFE96CU) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 7) */ +#define REG_DMAC1_DPIP7 (*(RwReg*)0xFFFFE970U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 7) */ +#define REG_DMAC1_WPMR (*(RwReg*)0xFFFFE9E4U) /**< \brief (DMAC1) DMAC Write Protect Mode Register */ +#define REG_DMAC1_WPSR (*(RoReg*)0xFFFFE9E8U) /**< \brief (DMAC1) DMAC Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_DMAC1_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_emac.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_emac.h new file mode 100644 index 0000000..7520b4a --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_emac.h
@@ -0,0 +1,130 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_EMAC_INSTANCE_ +#define _SAMA5_EMAC_INSTANCE_ + +/* ========== Register definition for EMAC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_EMAC_NCR (0xF802C000U) /**< \brief (EMAC) Network Control Register */ +#define REG_EMAC_NCFGR (0xF802C004U) /**< \brief (EMAC) Network Configuration Register */ +#define REG_EMAC_NSR (0xF802C008U) /**< \brief (EMAC) Network Status Register */ +#define REG_EMAC_TSR (0xF802C014U) /**< \brief (EMAC) Transmit Status Register */ +#define REG_EMAC_RBQP (0xF802C018U) /**< \brief (EMAC) Receive Buffer Queue Pointer Register */ +#define REG_EMAC_TBQP (0xF802C01CU) /**< \brief (EMAC) Transmit Buffer Queue Pointer Register */ +#define REG_EMAC_RSR (0xF802C020U) /**< \brief (EMAC) Receive Status Register */ +#define REG_EMAC_ISR (0xF802C024U) /**< \brief (EMAC) Interrupt Status Register */ +#define REG_EMAC_IER (0xF802C028U) /**< \brief (EMAC) Interrupt Enable Register */ +#define REG_EMAC_IDR (0xF802C02CU) /**< \brief (EMAC) Interrupt Disable Register */ +#define REG_EMAC_IMR (0xF802C030U) /**< \brief (EMAC) Interrupt Mask Register */ +#define REG_EMAC_MAN (0xF802C034U) /**< \brief (EMAC) Phy Maintenance Register */ +#define REG_EMAC_PTR (0xF802C038U) /**< \brief (EMAC) Pause Time Register */ +#define REG_EMAC_PFR (0xF802C03CU) /**< \brief (EMAC) Pause Frames Received Register */ +#define REG_EMAC_FTO (0xF802C040U) /**< \brief (EMAC) Frames Transmitted Ok Register */ +#define REG_EMAC_SCF (0xF802C044U) /**< \brief (EMAC) Single Collision Frames Register */ +#define REG_EMAC_MCF (0xF802C048U) /**< \brief (EMAC) Multiple Collision Frames Register */ +#define REG_EMAC_FRO (0xF802C04CU) /**< \brief (EMAC) Frames Received Ok Register */ +#define REG_EMAC_FCSE (0xF802C050U) /**< \brief (EMAC) Frame Check Sequence Errors Register */ +#define REG_EMAC_ALE (0xF802C054U) /**< \brief (EMAC) Alignment Errors Register */ +#define REG_EMAC_DTF (0xF802C058U) /**< \brief (EMAC) Deferred Transmission Frames Register */ +#define REG_EMAC_LCOL (0xF802C05CU) /**< \brief (EMAC) Late Collisions Register */ +#define REG_EMAC_ECOL (0xF802C060U) /**< \brief (EMAC) Excessive Collisions Register */ +#define REG_EMAC_TUND (0xF802C064U) /**< \brief (EMAC) Transmit Underrun Errors Register */ +#define REG_EMAC_CSE (0xF802C068U) /**< \brief (EMAC) Carrier Sense Errors Register */ +#define REG_EMAC_RRE (0xF802C06CU) /**< \brief (EMAC) Receive Resource Errors Register */ +#define REG_EMAC_ROV (0xF802C070U) /**< \brief (EMAC) Receive Overrun Errors Register */ +#define REG_EMAC_RSE (0xF802C074U) /**< \brief (EMAC) Receive Symbol Errors Register */ +#define REG_EMAC_ELE (0xF802C078U) /**< \brief (EMAC) Excessive Length Errors Register */ +#define REG_EMAC_RJA (0xF802C07CU) /**< \brief (EMAC) Receive Jabbers Register */ +#define REG_EMAC_USF (0xF802C080U) /**< \brief (EMAC) Undersize Frames Register */ +#define REG_EMAC_STE (0xF802C084U) /**< \brief (EMAC) SQE Test Errors Register */ +#define REG_EMAC_RLE (0xF802C088U) /**< \brief (EMAC) Received Length Field Mismatch Register */ +#define REG_EMAC_HRB (0xF802C090U) /**< \brief (EMAC) Hash Register Bottom [31:0] Register */ +#define REG_EMAC_HRT (0xF802C094U) /**< \brief (EMAC) Hash Register Top [63:32] Register */ +#define REG_EMAC_SA1B (0xF802C098U) /**< \brief (EMAC) Specific Address 1 Bottom Register */ +#define REG_EMAC_SA1T (0xF802C09CU) /**< \brief (EMAC) Specific Address 1 Top Register */ +#define REG_EMAC_SA2B (0xF802C0A0U) /**< \brief (EMAC) Specific Address 2 Bottom Register */ +#define REG_EMAC_SA2T (0xF802C0A4U) /**< \brief (EMAC) Specific Address 2 Top Register */ +#define REG_EMAC_SA3B (0xF802C0A8U) /**< \brief (EMAC) Specific Address 3 Bottom Register */ +#define REG_EMAC_SA3T (0xF802C0ACU) /**< \brief (EMAC) Specific Address 3 Top Register */ +#define REG_EMAC_SA4B (0xF802C0B0U) /**< \brief (EMAC) Specific Address 4 Bottom Register */ +#define REG_EMAC_SA4T (0xF802C0B4U) /**< \brief (EMAC) Specific Address 4 Top Register */ +#define REG_EMAC_TID (0xF802C0B8U) /**< \brief (EMAC) Type ID Checking Register */ +#define REG_EMAC_USRIO (0xF802C0C0U) /**< \brief (EMAC) User Input/Output Register */ +#define REG_EMAC_WOL (0xF802C0C4U) /**< \brief (EMAC) Wake on LAN Register */ +#else +#define REG_EMAC_NCR (*(RwReg*)0xF802C000U) /**< \brief (EMAC) Network Control Register */ +#define REG_EMAC_NCFGR (*(RwReg*)0xF802C004U) /**< \brief (EMAC) Network Configuration Register */ +#define REG_EMAC_NSR (*(RoReg*)0xF802C008U) /**< \brief (EMAC) Network Status Register */ +#define REG_EMAC_TSR (*(RwReg*)0xF802C014U) /**< \brief (EMAC) Transmit Status Register */ +#define REG_EMAC_RBQP (*(RwReg*)0xF802C018U) /**< \brief (EMAC) Receive Buffer Queue Pointer Register */ +#define REG_EMAC_TBQP (*(RwReg*)0xF802C01CU) /**< \brief (EMAC) Transmit Buffer Queue Pointer Register */ +#define REG_EMAC_RSR (*(RwReg*)0xF802C020U) /**< \brief (EMAC) Receive Status Register */ +#define REG_EMAC_ISR (*(RwReg*)0xF802C024U) /**< \brief (EMAC) Interrupt Status Register */ +#define REG_EMAC_IER (*(WoReg*)0xF802C028U) /**< \brief (EMAC) Interrupt Enable Register */ +#define REG_EMAC_IDR (*(WoReg*)0xF802C02CU) /**< \brief (EMAC) Interrupt Disable Register */ +#define REG_EMAC_IMR (*(RoReg*)0xF802C030U) /**< \brief (EMAC) Interrupt Mask Register */ +#define REG_EMAC_MAN (*(RwReg*)0xF802C034U) /**< \brief (EMAC) Phy Maintenance Register */ +#define REG_EMAC_PTR (*(RwReg*)0xF802C038U) /**< \brief (EMAC) Pause Time Register */ +#define REG_EMAC_PFR (*(RwReg*)0xF802C03CU) /**< \brief (EMAC) Pause Frames Received Register */ +#define REG_EMAC_FTO (*(RwReg*)0xF802C040U) /**< \brief (EMAC) Frames Transmitted Ok Register */ +#define REG_EMAC_SCF (*(RwReg*)0xF802C044U) /**< \brief (EMAC) Single Collision Frames Register */ +#define REG_EMAC_MCF (*(RwReg*)0xF802C048U) /**< \brief (EMAC) Multiple Collision Frames Register */ +#define REG_EMAC_FRO (*(RwReg*)0xF802C04CU) /**< \brief (EMAC) Frames Received Ok Register */ +#define REG_EMAC_FCSE (*(RwReg*)0xF802C050U) /**< \brief (EMAC) Frame Check Sequence Errors Register */ +#define REG_EMAC_ALE (*(RwReg*)0xF802C054U) /**< \brief (EMAC) Alignment Errors Register */ +#define REG_EMAC_DTF (*(RwReg*)0xF802C058U) /**< \brief (EMAC) Deferred Transmission Frames Register */ +#define REG_EMAC_LCOL (*(RwReg*)0xF802C05CU) /**< \brief (EMAC) Late Collisions Register */ +#define REG_EMAC_ECOL (*(RwReg*)0xF802C060U) /**< \brief (EMAC) Excessive Collisions Register */ +#define REG_EMAC_TUND (*(RwReg*)0xF802C064U) /**< \brief (EMAC) Transmit Underrun Errors Register */ +#define REG_EMAC_CSE (*(RwReg*)0xF802C068U) /**< \brief (EMAC) Carrier Sense Errors Register */ +#define REG_EMAC_RRE (*(RwReg*)0xF802C06CU) /**< \brief (EMAC) Receive Resource Errors Register */ +#define REG_EMAC_ROV (*(RwReg*)0xF802C070U) /**< \brief (EMAC) Receive Overrun Errors Register */ +#define REG_EMAC_RSE (*(RwReg*)0xF802C074U) /**< \brief (EMAC) Receive Symbol Errors Register */ +#define REG_EMAC_ELE (*(RwReg*)0xF802C078U) /**< \brief (EMAC) Excessive Length Errors Register */ +#define REG_EMAC_RJA (*(RwReg*)0xF802C07CU) /**< \brief (EMAC) Receive Jabbers Register */ +#define REG_EMAC_USF (*(RwReg*)0xF802C080U) /**< \brief (EMAC) Undersize Frames Register */ +#define REG_EMAC_STE (*(RwReg*)0xF802C084U) /**< \brief (EMAC) SQE Test Errors Register */ +#define REG_EMAC_RLE (*(RwReg*)0xF802C088U) /**< \brief (EMAC) Received Length Field Mismatch Register */ +#define REG_EMAC_HRB (*(RwReg*)0xF802C090U) /**< \brief (EMAC) Hash Register Bottom [31:0] Register */ +#define REG_EMAC_HRT (*(RwReg*)0xF802C094U) /**< \brief (EMAC) Hash Register Top [63:32] Register */ +#define REG_EMAC_SA1B (*(RwReg*)0xF802C098U) /**< \brief (EMAC) Specific Address 1 Bottom Register */ +#define REG_EMAC_SA1T (*(RwReg*)0xF802C09CU) /**< \brief (EMAC) Specific Address 1 Top Register */ +#define REG_EMAC_SA2B (*(RwReg*)0xF802C0A0U) /**< \brief (EMAC) Specific Address 2 Bottom Register */ +#define REG_EMAC_SA2T (*(RwReg*)0xF802C0A4U) /**< \brief (EMAC) Specific Address 2 Top Register */ +#define REG_EMAC_SA3B (*(RwReg*)0xF802C0A8U) /**< \brief (EMAC) Specific Address 3 Bottom Register */ +#define REG_EMAC_SA3T (*(RwReg*)0xF802C0ACU) /**< \brief (EMAC) Specific Address 3 Top Register */ +#define REG_EMAC_SA4B (*(RwReg*)0xF802C0B0U) /**< \brief (EMAC) Specific Address 4 Bottom Register */ +#define REG_EMAC_SA4T (*(RwReg*)0xF802C0B4U) /**< \brief (EMAC) Specific Address 4 Top Register */ +#define REG_EMAC_TID (*(RwReg*)0xF802C0B8U) /**< \brief (EMAC) Type ID Checking Register */ +#define REG_EMAC_USRIO (*(RwReg*)0xF802C0C0U) /**< \brief (EMAC) User Input/Output Register */ +#define REG_EMAC_WOL (*(RwReg*)0xF802C0C4U) /**< \brief (EMAC) Wake on LAN Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_EMAC_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_fuse.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_fuse.h new file mode 100644 index 0000000..3d556ef --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_fuse.h
@@ -0,0 +1,48 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_FUSE_INSTANCE_ +#define _SAMA5_FUSE_INSTANCE_ + +/* ========== Register definition for FUSE peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_FUSE_CR (0xFFFFE400U) /**< \brief (FUSE) Fuse Control Register */ +#define REG_FUSE_MR (0xFFFFE404U) /**< \brief (FUSE) Fuse Mode Register */ +#define REG_FUSE_IR (0xFFFFE408U) /**< \brief (FUSE) Fuse Index Register */ +#define REG_FUSE_DR (0xFFFFE40CU) /**< \brief (FUSE) Fuse Data Register */ +#define REG_FUSE_SR (0xFFFFE410U) /**< \brief (FUSE) Fuse Status Register */ +#else +#define REG_FUSE_CR (*(WoReg*)0xFFFFE400U) /**< \brief (FUSE) Fuse Control Register */ +#define REG_FUSE_MR (*(WoReg*)0xFFFFE404U) /**< \brief (FUSE) Fuse Mode Register */ +#define REG_FUSE_IR (*(RwReg*)0xFFFFE408U) /**< \brief (FUSE) Fuse Index Register */ +#define REG_FUSE_DR (*(RwReg*)0xFFFFE40CU) /**< \brief (FUSE) Fuse Data Register */ +#define REG_FUSE_SR (*(RoReg*)0xFFFFE410U) /**< \brief (FUSE) Fuse Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_FUSE_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_gmac.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_gmac.h new file mode 100644 index 0000000..77852b1 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_gmac.h
@@ -0,0 +1,244 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_GMAC_INSTANCE_ +#define _SAMA5_GMAC_INSTANCE_ + +/* ========== Register definition for GMAC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_GMAC_NCR (0xF0028000U) /**< \brief (GMAC) Network Control Register */ +#define REG_GMAC_NCFGR (0xF0028004U) /**< \brief (GMAC) Network Configuration Register */ +#define REG_GMAC_NSR (0xF0028008U) /**< \brief (GMAC) Network Status Register */ +#define REG_GMAC_UR (0xF002800CU) /**< \brief (GMAC) User Register */ +#define REG_GMAC_DCFGR (0xF0028010U) /**< \brief (GMAC) DMA Configuration Register */ +#define REG_GMAC_TSR (0xF0028014U) /**< \brief (GMAC) Transmit Status Register */ +#define REG_GMAC_RBQB (0xF0028018U) /**< \brief (GMAC) Receive Buffer Queue Base Address */ +#define REG_GMAC_TBQB (0xF002801CU) /**< \brief (GMAC) Transmit Buffer Queue Base Address */ +#define REG_GMAC_RSR (0xF0028020U) /**< \brief (GMAC) Receive Status Register */ +#define REG_GMAC_ISR (0xF0028024U) /**< \brief (GMAC) Interrupt Status Register */ +#define REG_GMAC_IER (0xF0028028U) /**< \brief (GMAC) Interrupt Enable Register */ +#define REG_GMAC_IDR (0xF002802CU) /**< \brief (GMAC) Interrupt Disable Register */ +#define REG_GMAC_IMR (0xF0028030U) /**< \brief (GMAC) Interrupt Mask Register */ +#define REG_GMAC_MAN (0xF0028034U) /**< \brief (GMAC) PHY Maintenance Register */ +#define REG_GMAC_RPQ (0xF0028038U) /**< \brief (GMAC) Received Pause Quantum Register */ +#define REG_GMAC_TPQ (0xF002803CU) /**< \brief (GMAC) Transmit Pause Quantum Register */ +#define REG_GMAC_TPSF (0xF0028040U) /**< \brief (GMAC) TX Partial Store and Forward Register */ +#define REG_GMAC_RPSF (0xF0028044U) /**< \brief (GMAC) RX Partial Store and Forward Register */ +#define REG_GMAC_HRB (0xF0028080U) /**< \brief (GMAC) Hash Register Bottom [31:0] */ +#define REG_GMAC_HRT (0xF0028084U) /**< \brief (GMAC) Hash Register Top [63:32] */ +#define REG_GMAC_SAB1 (0xF0028088U) /**< \brief (GMAC) Specific Address 1 Bottom [31:0] Register */ +#define REG_GMAC_SAT1 (0xF002808CU) /**< \brief (GMAC) Specific Address 1 Top [47:32] Register */ +#define REG_GMAC_SAB2 (0xF0028090U) /**< \brief (GMAC) Specific Address 2 Bottom [31:0] Register */ +#define REG_GMAC_SAT2 (0xF0028094U) /**< \brief (GMAC) Specific Address 2 Top [47:32] Register */ +#define REG_GMAC_SAB3 (0xF0028098U) /**< \brief (GMAC) Specific Address 3 Bottom [31:0] Register */ +#define REG_GMAC_SAT3 (0xF002809CU) /**< \brief (GMAC) Specific Address 3 Top [47:32] Register */ +#define REG_GMAC_SAB4 (0xF00280A0U) /**< \brief (GMAC) Specific Address 4 Bottom [31:0] Register */ +#define REG_GMAC_SAT4 (0xF00280A4U) /**< \brief (GMAC) Specific Address 4 Top [47:32] Register */ +#define REG_GMAC_TIDM (0xF00280A8U) /**< \brief (GMAC) Type ID Match 1 Register */ +#define REG_GMAC_WOL (0xF00280B8U) /**< \brief (GMAC) Wake on LAN Register */ +#define REG_GMAC_IPGS (0xF00280BCU) /**< \brief (GMAC) IPG Stretch Register */ +#define REG_GMAC_SVLAN (0xF00280C0U) /**< \brief (GMAC) Stacked VLAN Register */ +#define REG_GMAC_TPFCP (0xF00280C4U) /**< \brief (GMAC) Transmit PFC Pause Register */ +#define REG_GMAC_SAMB1 (0xF00280C8U) /**< \brief (GMAC) Specific Address 1 Mask Bottom [31:0] Register */ +#define REG_GMAC_SAMT1 (0xF00280CCU) /**< \brief (GMAC) Specific Address 1 Mask Top [47:32] Register */ +#define REG_GMAC_OTLO (0xF0028100U) /**< \brief (GMAC) Octets Transmitted [31:0] Register */ +#define REG_GMAC_OTHI (0xF0028104U) /**< \brief (GMAC) Octets Transmitted [47:32] Register */ +#define REG_GMAC_FT (0xF0028108U) /**< \brief (GMAC) Frames Transmitted Register */ +#define REG_GMAC_BCFT (0xF002810CU) /**< \brief (GMAC) Broadcast Frames Transmitted Register */ +#define REG_GMAC_MFT (0xF0028110U) /**< \brief (GMAC) Multicast Frames Transmitted Register */ +#define REG_GMAC_PFT (0xF0028114U) /**< \brief (GMAC) Pause Frames Transmitted Register */ +#define REG_GMAC_BFT64 (0xF0028118U) /**< \brief (GMAC) 64 Byte Frames Transmitted Register */ +#define REG_GMAC_TBFT127 (0xF002811CU) /**< \brief (GMAC) 65 to 127 Byte Frames Transmitted Register */ +#define REG_GMAC_TBFT255 (0xF0028120U) /**< \brief (GMAC) 128 to 255 Byte Frames Transmitted Register */ +#define REG_GMAC_TBFT511 (0xF0028124U) /**< \brief (GMAC) 256 to 511 Byte Frames Transmitted Register */ +#define REG_GMAC_TBFT1023 (0xF0028128U) /**< \brief (GMAC) 512 to 1023 Byte Frames Transmitted Register */ +#define REG_GMAC_TBFT1518 (0xF002812CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Transmitted Register */ +#define REG_GMAC_GTBFT1518 (0xF0028130U) /**< \brief (GMAC) Greater Than 1518 Byte Frames Transmitted Register */ +#define REG_GMAC_TUR (0xF0028134U) /**< \brief (GMAC) Transmit Under Runs Register */ +#define REG_GMAC_SCF (0xF0028138U) /**< \brief (GMAC) Single Collision Frames Register */ +#define REG_GMAC_MCF (0xF002813CU) /**< \brief (GMAC) Multiple Collision Frames Register */ +#define REG_GMAC_EC (0xF0028140U) /**< \brief (GMAC) Excessive Collisions Register */ +#define REG_GMAC_LC (0xF0028144U) /**< \brief (GMAC) Late Collisions Register */ +#define REG_GMAC_DTF (0xF0028148U) /**< \brief (GMAC) Deferred Transmission Frames Register */ +#define REG_GMAC_CSE (0xF002814CU) /**< \brief (GMAC) Carrier Sense Errors Register */ +#define REG_GMAC_ORLO (0xF0028150U) /**< \brief (GMAC) Octets Received [31:0] Received */ +#define REG_GMAC_ORHI (0xF0028154U) /**< \brief (GMAC) Octets Received [47:32] Received */ +#define REG_GMAC_FR (0xF0028158U) /**< \brief (GMAC) Frames Received Register */ +#define REG_GMAC_BCFR (0xF002815CU) /**< \brief (GMAC) Broadcast Frames Received Register */ +#define REG_GMAC_MFR (0xF0028160U) /**< \brief (GMAC) Multicast Frames Received Register */ +#define REG_GMAC_PFR (0xF0028164U) /**< \brief (GMAC) Pause Frames Received Register */ +#define REG_GMAC_BFR64 (0xF0028168U) /**< \brief (GMAC) 64 Byte Frames Received Register */ +#define REG_GMAC_TBFR127 (0xF002816CU) /**< \brief (GMAC) 65 to 127 Byte Frames Received Register */ +#define REG_GMAC_TBFR255 (0xF0028170U) /**< \brief (GMAC) 128 to 255 Byte Frames Received Register */ +#define REG_GMAC_TBFR511 (0xF0028174U) /**< \brief (GMAC) 256 to 511Byte Frames Received Register */ +#define REG_GMAC_TBFR1023 (0xF0028178U) /**< \brief (GMAC) 512 to 1023 Byte Frames Received Register */ +#define REG_GMAC_TBFR1518 (0xF002817CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Received Register */ +#define REG_GMAC_TMXBFR (0xF0028180U) /**< \brief (GMAC) 1519 to Maximum Byte Frames Received Register */ +#define REG_GMAC_UFR (0xF0028184U) /**< \brief (GMAC) Undersize Frames Received Register */ +#define REG_GMAC_OFR (0xF0028188U) /**< \brief (GMAC) Oversize Frames Received Register */ +#define REG_GMAC_JR (0xF002818CU) /**< \brief (GMAC) Jabbers Received Register */ +#define REG_GMAC_FCSE (0xF0028190U) /**< \brief (GMAC) Frame Check Sequence Errors Register */ +#define REG_GMAC_LFFE (0xF0028194U) /**< \brief (GMAC) Length Field Frame Errors Register */ +#define REG_GMAC_RSE (0xF0028198U) /**< \brief (GMAC) Receive Symbol Errors Register */ +#define REG_GMAC_AE (0xF002819CU) /**< \brief (GMAC) Alignment Errors Register */ +#define REG_GMAC_RRE (0xF00281A0U) /**< \brief (GMAC) Receive Resource Errors Register */ +#define REG_GMAC_ROE (0xF00281A4U) /**< \brief (GMAC) Receive Overrun Register */ +#define REG_GMAC_IHCE (0xF00281A8U) /**< \brief (GMAC) IP Header Checksum Errors Register */ +#define REG_GMAC_TCE (0xF00281ACU) /**< \brief (GMAC) TCP Checksum Errors Register */ +#define REG_GMAC_UCE (0xF00281B0U) /**< \brief (GMAC) UDP Checksum Errors Register */ +#define REG_GMAC_TSSS (0xF00281C8U) /**< \brief (GMAC) 1588 Timer Sync Strobe Seconds Register */ +#define REG_GMAC_TSSN (0xF00281CCU) /**< \brief (GMAC) 1588 Timer Sync Strobe Nanoseconds Register */ +#define REG_GMAC_TS (0xF00281D0U) /**< \brief (GMAC) 1588 Timer Seconds Register */ +#define REG_GMAC_TN (0xF00281D4U) /**< \brief (GMAC) 1588 Timer Nanoseconds Register */ +#define REG_GMAC_TA (0xF00281D8U) /**< \brief (GMAC) 1588 Timer Adjust Register */ +#define REG_GMAC_TI (0xF00281DCU) /**< \brief (GMAC) 1588 Timer Increment Register */ +#define REG_GMAC_EFTS (0xF00281E0U) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds */ +#define REG_GMAC_EFTN (0xF00281E4U) /**< \brief (GMAC) PTP Event Frame Transmitted Nanoseconds */ +#define REG_GMAC_EFRS (0xF00281E8U) /**< \brief (GMAC) PTP Event Frame Received Seconds */ +#define REG_GMAC_EFRN (0xF00281ECU) /**< \brief (GMAC) PTP Event Frame Received Nanoseconds */ +#define REG_GMAC_PEFTS (0xF00281F0U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds */ +#define REG_GMAC_PEFTN (0xF00281F4U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Nanoseconds */ +#define REG_GMAC_PEFRS (0xF00281F8U) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds */ +#define REG_GMAC_PEFRN (0xF00281FCU) /**< \brief (GMAC) PTP Peer Event Frame Received Nanoseconds */ +#define REG_GMAC_ISRPQ (0xF0028400U) /**< \brief (GMAC) Interrupt Status Register Priority Queue */ +#define REG_GMAC_TBQBAPQ (0xF0028440U) /**< \brief (GMAC) Transmit Buffer Queue Base Address Priority Queue */ +#define REG_GMAC_RBQBAPQ (0xF0028480U) /**< \brief (GMAC) Receive Buffer Queue Base Address Priority Queue */ +#define REG_GMAC_RBSRPQ (0xF00284A0U) /**< \brief (GMAC) Receive Buffer Size Register Priority Queue */ +#define REG_GMAC_ST1RPQ (0xF0028500U) /**< \brief (GMAC) Screening Type1 Register Priority Queue */ +#define REG_GMAC_ST2RPQ (0xF0028540U) /**< \brief (GMAC) Screening Type2 Register Priority Queue */ +#define REG_GMAC_IERPQ (0xF0028600U) /**< \brief (GMAC) Interrupt Enable Register Priority Queue */ +#define REG_GMAC_IDRPQ (0xF0028620U) /**< \brief (GMAC) Interrupt Disable Register Priority Queue */ +#define REG_GMAC_IMRPQ (0xF0028640U) /**< \brief (GMAC) Interrupt Mask Register Priority Queue */ +#else +#define REG_GMAC_NCR (*(RwReg*)0xF0028000U) /**< \brief (GMAC) Network Control Register */ +#define REG_GMAC_NCFGR (*(RwReg*)0xF0028004U) /**< \brief (GMAC) Network Configuration Register */ +#define REG_GMAC_NSR (*(RoReg*)0xF0028008U) /**< \brief (GMAC) Network Status Register */ +#define REG_GMAC_UR (*(RwReg*)0xF002800CU) /**< \brief (GMAC) User Register */ +#define REG_GMAC_DCFGR (*(RwReg*)0xF0028010U) /**< \brief (GMAC) DMA Configuration Register */ +#define REG_GMAC_TSR (*(RwReg*)0xF0028014U) /**< \brief (GMAC) Transmit Status Register */ +#define REG_GMAC_RBQB (*(RwReg*)0xF0028018U) /**< \brief (GMAC) Receive Buffer Queue Base Address */ +#define REG_GMAC_TBQB (*(RwReg*)0xF002801CU) /**< \brief (GMAC) Transmit Buffer Queue Base Address */ +#define REG_GMAC_RSR (*(RwReg*)0xF0028020U) /**< \brief (GMAC) Receive Status Register */ +#define REG_GMAC_ISR (*(RoReg*)0xF0028024U) /**< \brief (GMAC) Interrupt Status Register */ +#define REG_GMAC_IER (*(WoReg*)0xF0028028U) /**< \brief (GMAC) Interrupt Enable Register */ +#define REG_GMAC_IDR (*(WoReg*)0xF002802CU) /**< \brief (GMAC) Interrupt Disable Register */ +#define REG_GMAC_IMR (*(RoReg*)0xF0028030U) /**< \brief (GMAC) Interrupt Mask Register */ +#define REG_GMAC_MAN (*(RwReg*)0xF0028034U) /**< \brief (GMAC) PHY Maintenance Register */ +#define REG_GMAC_RPQ (*(RoReg*)0xF0028038U) /**< \brief (GMAC) Received Pause Quantum Register */ +#define REG_GMAC_TPQ (*(RwReg*)0xF002803CU) /**< \brief (GMAC) Transmit Pause Quantum Register */ +#define REG_GMAC_TPSF (*(RwReg*)0xF0028040U) /**< \brief (GMAC) TX Partial Store and Forward Register */ +#define REG_GMAC_RPSF (*(RwReg*)0xF0028044U) /**< \brief (GMAC) RX Partial Store and Forward Register */ +#define REG_GMAC_HRB (*(RwReg*)0xF0028080U) /**< \brief (GMAC) Hash Register Bottom [31:0] */ +#define REG_GMAC_HRT (*(RwReg*)0xF0028084U) /**< \brief (GMAC) Hash Register Top [63:32] */ +#define REG_GMAC_SAB1 (*(RwReg*)0xF0028088U) /**< \brief (GMAC) Specific Address 1 Bottom [31:0] Register */ +#define REG_GMAC_SAT1 (*(RwReg*)0xF002808CU) /**< \brief (GMAC) Specific Address 1 Top [47:32] Register */ +#define REG_GMAC_SAB2 (*(RwReg*)0xF0028090U) /**< \brief (GMAC) Specific Address 2 Bottom [31:0] Register */ +#define REG_GMAC_SAT2 (*(RwReg*)0xF0028094U) /**< \brief (GMAC) Specific Address 2 Top [47:32] Register */ +#define REG_GMAC_SAB3 (*(RwReg*)0xF0028098U) /**< \brief (GMAC) Specific Address 3 Bottom [31:0] Register */ +#define REG_GMAC_SAT3 (*(RwReg*)0xF002809CU) /**< \brief (GMAC) Specific Address 3 Top [47:32] Register */ +#define REG_GMAC_SAB4 (*(RwReg*)0xF00280A0U) /**< \brief (GMAC) Specific Address 4 Bottom [31:0] Register */ +#define REG_GMAC_SAT4 (*(RwReg*)0xF00280A4U) /**< \brief (GMAC) Specific Address 4 Top [47:32] Register */ +#define REG_GMAC_TIDM (*(RwReg*)0xF00280A8U) /**< \brief (GMAC) Type ID Match 1 Register */ +#define REG_GMAC_WOL (*(RwReg*)0xF00280B8U) /**< \brief (GMAC) Wake on LAN Register */ +#define REG_GMAC_IPGS (*(RwReg*)0xF00280BCU) /**< \brief (GMAC) IPG Stretch Register */ +#define REG_GMAC_SVLAN (*(RwReg*)0xF00280C0U) /**< \brief (GMAC) Stacked VLAN Register */ +#define REG_GMAC_TPFCP (*(RwReg*)0xF00280C4U) /**< \brief (GMAC) Transmit PFC Pause Register */ +#define REG_GMAC_SAMB1 (*(RwReg*)0xF00280C8U) /**< \brief (GMAC) Specific Address 1 Mask Bottom [31:0] Register */ +#define REG_GMAC_SAMT1 (*(RwReg*)0xF00280CCU) /**< \brief (GMAC) Specific Address 1 Mask Top [47:32] Register */ +#define REG_GMAC_OTLO (*(RoReg*)0xF0028100U) /**< \brief (GMAC) Octets Transmitted [31:0] Register */ +#define REG_GMAC_OTHI (*(RoReg*)0xF0028104U) /**< \brief (GMAC) Octets Transmitted [47:32] Register */ +#define REG_GMAC_FT (*(RoReg*)0xF0028108U) /**< \brief (GMAC) Frames Transmitted Register */ +#define REG_GMAC_BCFT (*(RoReg*)0xF002810CU) /**< \brief (GMAC) Broadcast Frames Transmitted Register */ +#define REG_GMAC_MFT (*(RoReg*)0xF0028110U) /**< \brief (GMAC) Multicast Frames Transmitted Register */ +#define REG_GMAC_PFT (*(RoReg*)0xF0028114U) /**< \brief (GMAC) Pause Frames Transmitted Register */ +#define REG_GMAC_BFT64 (*(RoReg*)0xF0028118U) /**< \brief (GMAC) 64 Byte Frames Transmitted Register */ +#define REG_GMAC_TBFT127 (*(RoReg*)0xF002811CU) /**< \brief (GMAC) 65 to 127 Byte Frames Transmitted Register */ +#define REG_GMAC_TBFT255 (*(RoReg*)0xF0028120U) /**< \brief (GMAC) 128 to 255 Byte Frames Transmitted Register */ +#define REG_GMAC_TBFT511 (*(RoReg*)0xF0028124U) /**< \brief (GMAC) 256 to 511 Byte Frames Transmitted Register */ +#define REG_GMAC_TBFT1023 (*(RoReg*)0xF0028128U) /**< \brief (GMAC) 512 to 1023 Byte Frames Transmitted Register */ +#define REG_GMAC_TBFT1518 (*(RoReg*)0xF002812CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Transmitted Register */ +#define REG_GMAC_GTBFT1518 (*(RoReg*)0xF0028130U) /**< \brief (GMAC) Greater Than 1518 Byte Frames Transmitted Register */ +#define REG_GMAC_TUR (*(RoReg*)0xF0028134U) /**< \brief (GMAC) Transmit Under Runs Register */ +#define REG_GMAC_SCF (*(RoReg*)0xF0028138U) /**< \brief (GMAC) Single Collision Frames Register */ +#define REG_GMAC_MCF (*(RoReg*)0xF002813CU) /**< \brief (GMAC) Multiple Collision Frames Register */ +#define REG_GMAC_EC (*(RoReg*)0xF0028140U) /**< \brief (GMAC) Excessive Collisions Register */ +#define REG_GMAC_LC (*(RoReg*)0xF0028144U) /**< \brief (GMAC) Late Collisions Register */ +#define REG_GMAC_DTF (*(RoReg*)0xF0028148U) /**< \brief (GMAC) Deferred Transmission Frames Register */ +#define REG_GMAC_CSE (*(RoReg*)0xF002814CU) /**< \brief (GMAC) Carrier Sense Errors Register */ +#define REG_GMAC_ORLO (*(RoReg*)0xF0028150U) /**< \brief (GMAC) Octets Received [31:0] Received */ +#define REG_GMAC_ORHI (*(RoReg*)0xF0028154U) /**< \brief (GMAC) Octets Received [47:32] Received */ +#define REG_GMAC_FR (*(RoReg*)0xF0028158U) /**< \brief (GMAC) Frames Received Register */ +#define REG_GMAC_BCFR (*(RoReg*)0xF002815CU) /**< \brief (GMAC) Broadcast Frames Received Register */ +#define REG_GMAC_MFR (*(RoReg*)0xF0028160U) /**< \brief (GMAC) Multicast Frames Received Register */ +#define REG_GMAC_PFR (*(RoReg*)0xF0028164U) /**< \brief (GMAC) Pause Frames Received Register */ +#define REG_GMAC_BFR64 (*(RoReg*)0xF0028168U) /**< \brief (GMAC) 64 Byte Frames Received Register */ +#define REG_GMAC_TBFR127 (*(RoReg*)0xF002816CU) /**< \brief (GMAC) 65 to 127 Byte Frames Received Register */ +#define REG_GMAC_TBFR255 (*(RoReg*)0xF0028170U) /**< \brief (GMAC) 128 to 255 Byte Frames Received Register */ +#define REG_GMAC_TBFR511 (*(RoReg*)0xF0028174U) /**< \brief (GMAC) 256 to 511Byte Frames Received Register */ +#define REG_GMAC_TBFR1023 (*(RoReg*)0xF0028178U) /**< \brief (GMAC) 512 to 1023 Byte Frames Received Register */ +#define REG_GMAC_TBFR1518 (*(RoReg*)0xF002817CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Received Register */ +#define REG_GMAC_TMXBFR (*(RoReg*)0xF0028180U) /**< \brief (GMAC) 1519 to Maximum Byte Frames Received Register */ +#define REG_GMAC_UFR (*(RoReg*)0xF0028184U) /**< \brief (GMAC) Undersize Frames Received Register */ +#define REG_GMAC_OFR (*(RoReg*)0xF0028188U) /**< \brief (GMAC) Oversize Frames Received Register */ +#define REG_GMAC_JR (*(RoReg*)0xF002818CU) /**< \brief (GMAC) Jabbers Received Register */ +#define REG_GMAC_FCSE (*(RoReg*)0xF0028190U) /**< \brief (GMAC) Frame Check Sequence Errors Register */ +#define REG_GMAC_LFFE (*(RoReg*)0xF0028194U) /**< \brief (GMAC) Length Field Frame Errors Register */ +#define REG_GMAC_RSE (*(RoReg*)0xF0028198U) /**< \brief (GMAC) Receive Symbol Errors Register */ +#define REG_GMAC_AE (*(RoReg*)0xF002819CU) /**< \brief (GMAC) Alignment Errors Register */ +#define REG_GMAC_RRE (*(RoReg*)0xF00281A0U) /**< \brief (GMAC) Receive Resource Errors Register */ +#define REG_GMAC_ROE (*(RoReg*)0xF00281A4U) /**< \brief (GMAC) Receive Overrun Register */ +#define REG_GMAC_IHCE (*(RoReg*)0xF00281A8U) /**< \brief (GMAC) IP Header Checksum Errors Register */ +#define REG_GMAC_TCE (*(RoReg*)0xF00281ACU) /**< \brief (GMAC) TCP Checksum Errors Register */ +#define REG_GMAC_UCE (*(RoReg*)0xF00281B0U) /**< \brief (GMAC) UDP Checksum Errors Register */ +#define REG_GMAC_TSSS (*(RwReg*)0xF00281C8U) /**< \brief (GMAC) 1588 Timer Sync Strobe Seconds Register */ +#define REG_GMAC_TSSN (*(RwReg*)0xF00281CCU) /**< \brief (GMAC) 1588 Timer Sync Strobe Nanoseconds Register */ +#define REG_GMAC_TS (*(RwReg*)0xF00281D0U) /**< \brief (GMAC) 1588 Timer Seconds Register */ +#define REG_GMAC_TN (*(RwReg*)0xF00281D4U) /**< \brief (GMAC) 1588 Timer Nanoseconds Register */ +#define REG_GMAC_TA (*(WoReg*)0xF00281D8U) /**< \brief (GMAC) 1588 Timer Adjust Register */ +#define REG_GMAC_TI (*(RwReg*)0xF00281DCU) /**< \brief (GMAC) 1588 Timer Increment Register */ +#define REG_GMAC_EFTS (*(RoReg*)0xF00281E0U) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds */ +#define REG_GMAC_EFTN (*(RoReg*)0xF00281E4U) /**< \brief (GMAC) PTP Event Frame Transmitted Nanoseconds */ +#define REG_GMAC_EFRS (*(RoReg*)0xF00281E8U) /**< \brief (GMAC) PTP Event Frame Received Seconds */ +#define REG_GMAC_EFRN (*(RoReg*)0xF00281ECU) /**< \brief (GMAC) PTP Event Frame Received Nanoseconds */ +#define REG_GMAC_PEFTS (*(RoReg*)0xF00281F0U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds */ +#define REG_GMAC_PEFTN (*(RoReg*)0xF00281F4U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Nanoseconds */ +#define REG_GMAC_PEFRS (*(RoReg*)0xF00281F8U) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds */ +#define REG_GMAC_PEFRN (*(RoReg*)0xF00281FCU) /**< \brief (GMAC) PTP Peer Event Frame Received Nanoseconds */ +#define REG_GMAC_ISRPQ (*(RoReg*)0xF0028400U) /**< \brief (GMAC) Interrupt Status Register Priority Queue */ +#define REG_GMAC_TBQBAPQ (*(RwReg*)0xF0028440U) /**< \brief (GMAC) Transmit Buffer Queue Base Address Priority Queue */ +#define REG_GMAC_RBQBAPQ (*(RwReg*)0xF0028480U) /**< \brief (GMAC) Receive Buffer Queue Base Address Priority Queue */ +#define REG_GMAC_RBSRPQ (*(RwReg*)0xF00284A0U) /**< \brief (GMAC) Receive Buffer Size Register Priority Queue */ +#define REG_GMAC_ST1RPQ (*(RwReg*)0xF0028500U) /**< \brief (GMAC) Screening Type1 Register Priority Queue */ +#define REG_GMAC_ST2RPQ (*(RwReg*)0xF0028540U) /**< \brief (GMAC) Screening Type2 Register Priority Queue */ +#define REG_GMAC_IERPQ (*(WoReg*)0xF0028600U) /**< \brief (GMAC) Interrupt Enable Register Priority Queue */ +#define REG_GMAC_IDRPQ (*(WoReg*)0xF0028620U) /**< \brief (GMAC) Interrupt Disable Register Priority Queue */ +#define REG_GMAC_IMRPQ (*(RwReg*)0xF0028640U) /**< \brief (GMAC) Interrupt Mask Register Priority Queue */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_GMAC_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_gpbr.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_gpbr.h new file mode 100644 index 0000000..7ca1237 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_gpbr.h
@@ -0,0 +1,40 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_GPBR_INSTANCE_ +#define _SAMA5_GPBR_INSTANCE_ + +/* ========== Register definition for GPBR peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_GPBR_GPBR (0xFFFFFE60U) /**< \brief (GPBR) General Purpose Backup Register */ +#else +#define REG_GPBR_GPBR (*(RwReg*)0xFFFFFE60U) /**< \brief (GPBR) General Purpose Backup Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_GPBR_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_hsmci0.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_hsmci0.h new file mode 100644 index 0000000..ac66fad --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_hsmci0.h
@@ -0,0 +1,78 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_HSMCI0_INSTANCE_ +#define _SAMA5_HSMCI0_INSTANCE_ + +/* ========== Register definition for HSMCI0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_HSMCI0_CR (0xF0000000U) /**< \brief (HSMCI0) Control Register */ +#define REG_HSMCI0_MR (0xF0000004U) /**< \brief (HSMCI0) Mode Register */ +#define REG_HSMCI0_DTOR (0xF0000008U) /**< \brief (HSMCI0) Data Timeout Register */ +#define REG_HSMCI0_SDCR (0xF000000CU) /**< \brief (HSMCI0) SD/SDIO Card Register */ +#define REG_HSMCI0_ARGR (0xF0000010U) /**< \brief (HSMCI0) Argument Register */ +#define REG_HSMCI0_CMDR (0xF0000014U) /**< \brief (HSMCI0) Command Register */ +#define REG_HSMCI0_BLKR (0xF0000018U) /**< \brief (HSMCI0) Block Register */ +#define REG_HSMCI0_CSTOR (0xF000001CU) /**< \brief (HSMCI0) Completion Signal Timeout Register */ +#define REG_HSMCI0_RSPR (0xF0000020U) /**< \brief (HSMCI0) Response Register */ +#define REG_HSMCI0_RDR (0xF0000030U) /**< \brief (HSMCI0) Receive Data Register */ +#define REG_HSMCI0_TDR (0xF0000034U) /**< \brief (HSMCI0) Transmit Data Register */ +#define REG_HSMCI0_SR (0xF0000040U) /**< \brief (HSMCI0) Status Register */ +#define REG_HSMCI0_IER (0xF0000044U) /**< \brief (HSMCI0) Interrupt Enable Register */ +#define REG_HSMCI0_IDR (0xF0000048U) /**< \brief (HSMCI0) Interrupt Disable Register */ +#define REG_HSMCI0_IMR (0xF000004CU) /**< \brief (HSMCI0) Interrupt Mask Register */ +#define REG_HSMCI0_DMA (0xF0000050U) /**< \brief (HSMCI0) DMA Configuration Register */ +#define REG_HSMCI0_CFG (0xF0000054U) /**< \brief (HSMCI0) Configuration Register */ +#define REG_HSMCI0_WPMR (0xF00000E4U) /**< \brief (HSMCI0) Write Protection Mode Register */ +#define REG_HSMCI0_WPSR (0xF00000E8U) /**< \brief (HSMCI0) Write Protection Status Register */ +#define REG_HSMCI0_FIFO (0xF0000200U) /**< \brief (HSMCI0) FIFO Memory Aperture0 */ +#else +#define REG_HSMCI0_CR (*(WoReg*)0xF0000000U) /**< \brief (HSMCI0) Control Register */ +#define REG_HSMCI0_MR (*(RwReg*)0xF0000004U) /**< \brief (HSMCI0) Mode Register */ +#define REG_HSMCI0_DTOR (*(RwReg*)0xF0000008U) /**< \brief (HSMCI0) Data Timeout Register */ +#define REG_HSMCI0_SDCR (*(RwReg*)0xF000000CU) /**< \brief (HSMCI0) SD/SDIO Card Register */ +#define REG_HSMCI0_ARGR (*(RwReg*)0xF0000010U) /**< \brief (HSMCI0) Argument Register */ +#define REG_HSMCI0_CMDR (*(WoReg*)0xF0000014U) /**< \brief (HSMCI0) Command Register */ +#define REG_HSMCI0_BLKR (*(RwReg*)0xF0000018U) /**< \brief (HSMCI0) Block Register */ +#define REG_HSMCI0_CSTOR (*(RwReg*)0xF000001CU) /**< \brief (HSMCI0) Completion Signal Timeout Register */ +#define REG_HSMCI0_RSPR (*(RoReg*)0xF0000020U) /**< \brief (HSMCI0) Response Register */ +#define REG_HSMCI0_RDR (*(RoReg*)0xF0000030U) /**< \brief (HSMCI0) Receive Data Register */ +#define REG_HSMCI0_TDR (*(WoReg*)0xF0000034U) /**< \brief (HSMCI0) Transmit Data Register */ +#define REG_HSMCI0_SR (*(RoReg*)0xF0000040U) /**< \brief (HSMCI0) Status Register */ +#define REG_HSMCI0_IER (*(WoReg*)0xF0000044U) /**< \brief (HSMCI0) Interrupt Enable Register */ +#define REG_HSMCI0_IDR (*(WoReg*)0xF0000048U) /**< \brief (HSMCI0) Interrupt Disable Register */ +#define REG_HSMCI0_IMR (*(RoReg*)0xF000004CU) /**< \brief (HSMCI0) Interrupt Mask Register */ +#define REG_HSMCI0_DMA (*(RwReg*)0xF0000050U) /**< \brief (HSMCI0) DMA Configuration Register */ +#define REG_HSMCI0_CFG (*(RwReg*)0xF0000054U) /**< \brief (HSMCI0) Configuration Register */ +#define REG_HSMCI0_WPMR (*(RwReg*)0xF00000E4U) /**< \brief (HSMCI0) Write Protection Mode Register */ +#define REG_HSMCI0_WPSR (*(RoReg*)0xF00000E8U) /**< \brief (HSMCI0) Write Protection Status Register */ +#define REG_HSMCI0_FIFO (*(RwReg*)0xF0000200U) /**< \brief (HSMCI0) FIFO Memory Aperture0 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_HSMCI0_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_hsmci1.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_hsmci1.h new file mode 100644 index 0000000..133832d --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_hsmci1.h
@@ -0,0 +1,78 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_HSMCI1_INSTANCE_ +#define _SAMA5_HSMCI1_INSTANCE_ + +/* ========== Register definition for HSMCI1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_HSMCI1_CR (0xF8000000U) /**< \brief (HSMCI1) Control Register */ +#define REG_HSMCI1_MR (0xF8000004U) /**< \brief (HSMCI1) Mode Register */ +#define REG_HSMCI1_DTOR (0xF8000008U) /**< \brief (HSMCI1) Data Timeout Register */ +#define REG_HSMCI1_SDCR (0xF800000CU) /**< \brief (HSMCI1) SD/SDIO Card Register */ +#define REG_HSMCI1_ARGR (0xF8000010U) /**< \brief (HSMCI1) Argument Register */ +#define REG_HSMCI1_CMDR (0xF8000014U) /**< \brief (HSMCI1) Command Register */ +#define REG_HSMCI1_BLKR (0xF8000018U) /**< \brief (HSMCI1) Block Register */ +#define REG_HSMCI1_CSTOR (0xF800001CU) /**< \brief (HSMCI1) Completion Signal Timeout Register */ +#define REG_HSMCI1_RSPR (0xF8000020U) /**< \brief (HSMCI1) Response Register */ +#define REG_HSMCI1_RDR (0xF8000030U) /**< \brief (HSMCI1) Receive Data Register */ +#define REG_HSMCI1_TDR (0xF8000034U) /**< \brief (HSMCI1) Transmit Data Register */ +#define REG_HSMCI1_SR (0xF8000040U) /**< \brief (HSMCI1) Status Register */ +#define REG_HSMCI1_IER (0xF8000044U) /**< \brief (HSMCI1) Interrupt Enable Register */ +#define REG_HSMCI1_IDR (0xF8000048U) /**< \brief (HSMCI1) Interrupt Disable Register */ +#define REG_HSMCI1_IMR (0xF800004CU) /**< \brief (HSMCI1) Interrupt Mask Register */ +#define REG_HSMCI1_DMA (0xF8000050U) /**< \brief (HSMCI1) DMA Configuration Register */ +#define REG_HSMCI1_CFG (0xF8000054U) /**< \brief (HSMCI1) Configuration Register */ +#define REG_HSMCI1_WPMR (0xF80000E4U) /**< \brief (HSMCI1) Write Protection Mode Register */ +#define REG_HSMCI1_WPSR (0xF80000E8U) /**< \brief (HSMCI1) Write Protection Status Register */ +#define REG_HSMCI1_FIFO (0xF8000200U) /**< \brief (HSMCI1) FIFO Memory Aperture0 */ +#else +#define REG_HSMCI1_CR (*(WoReg*)0xF8000000U) /**< \brief (HSMCI1) Control Register */ +#define REG_HSMCI1_MR (*(RwReg*)0xF8000004U) /**< \brief (HSMCI1) Mode Register */ +#define REG_HSMCI1_DTOR (*(RwReg*)0xF8000008U) /**< \brief (HSMCI1) Data Timeout Register */ +#define REG_HSMCI1_SDCR (*(RwReg*)0xF800000CU) /**< \brief (HSMCI1) SD/SDIO Card Register */ +#define REG_HSMCI1_ARGR (*(RwReg*)0xF8000010U) /**< \brief (HSMCI1) Argument Register */ +#define REG_HSMCI1_CMDR (*(WoReg*)0xF8000014U) /**< \brief (HSMCI1) Command Register */ +#define REG_HSMCI1_BLKR (*(RwReg*)0xF8000018U) /**< \brief (HSMCI1) Block Register */ +#define REG_HSMCI1_CSTOR (*(RwReg*)0xF800001CU) /**< \brief (HSMCI1) Completion Signal Timeout Register */ +#define REG_HSMCI1_RSPR (*(RoReg*)0xF8000020U) /**< \brief (HSMCI1) Response Register */ +#define REG_HSMCI1_RDR (*(RoReg*)0xF8000030U) /**< \brief (HSMCI1) Receive Data Register */ +#define REG_HSMCI1_TDR (*(WoReg*)0xF8000034U) /**< \brief (HSMCI1) Transmit Data Register */ +#define REG_HSMCI1_SR (*(RoReg*)0xF8000040U) /**< \brief (HSMCI1) Status Register */ +#define REG_HSMCI1_IER (*(WoReg*)0xF8000044U) /**< \brief (HSMCI1) Interrupt Enable Register */ +#define REG_HSMCI1_IDR (*(WoReg*)0xF8000048U) /**< \brief (HSMCI1) Interrupt Disable Register */ +#define REG_HSMCI1_IMR (*(RoReg*)0xF800004CU) /**< \brief (HSMCI1) Interrupt Mask Register */ +#define REG_HSMCI1_DMA (*(RwReg*)0xF8000050U) /**< \brief (HSMCI1) DMA Configuration Register */ +#define REG_HSMCI1_CFG (*(RwReg*)0xF8000054U) /**< \brief (HSMCI1) Configuration Register */ +#define REG_HSMCI1_WPMR (*(RwReg*)0xF80000E4U) /**< \brief (HSMCI1) Write Protection Mode Register */ +#define REG_HSMCI1_WPSR (*(RoReg*)0xF80000E8U) /**< \brief (HSMCI1) Write Protection Status Register */ +#define REG_HSMCI1_FIFO (*(RwReg*)0xF8000200U) /**< \brief (HSMCI1) FIFO Memory Aperture0 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_HSMCI1_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_hsmci2.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_hsmci2.h new file mode 100644 index 0000000..0e9d957 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_hsmci2.h
@@ -0,0 +1,78 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_HSMCI2_INSTANCE_ +#define _SAMA5_HSMCI2_INSTANCE_ + +/* ========== Register definition for HSMCI2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_HSMCI2_CR (0xF8004000U) /**< \brief (HSMCI2) Control Register */ +#define REG_HSMCI2_MR (0xF8004004U) /**< \brief (HSMCI2) Mode Register */ +#define REG_HSMCI2_DTOR (0xF8004008U) /**< \brief (HSMCI2) Data Timeout Register */ +#define REG_HSMCI2_SDCR (0xF800400CU) /**< \brief (HSMCI2) SD/SDIO Card Register */ +#define REG_HSMCI2_ARGR (0xF8004010U) /**< \brief (HSMCI2) Argument Register */ +#define REG_HSMCI2_CMDR (0xF8004014U) /**< \brief (HSMCI2) Command Register */ +#define REG_HSMCI2_BLKR (0xF8004018U) /**< \brief (HSMCI2) Block Register */ +#define REG_HSMCI2_CSTOR (0xF800401CU) /**< \brief (HSMCI2) Completion Signal Timeout Register */ +#define REG_HSMCI2_RSPR (0xF8004020U) /**< \brief (HSMCI2) Response Register */ +#define REG_HSMCI2_RDR (0xF8004030U) /**< \brief (HSMCI2) Receive Data Register */ +#define REG_HSMCI2_TDR (0xF8004034U) /**< \brief (HSMCI2) Transmit Data Register */ +#define REG_HSMCI2_SR (0xF8004040U) /**< \brief (HSMCI2) Status Register */ +#define REG_HSMCI2_IER (0xF8004044U) /**< \brief (HSMCI2) Interrupt Enable Register */ +#define REG_HSMCI2_IDR (0xF8004048U) /**< \brief (HSMCI2) Interrupt Disable Register */ +#define REG_HSMCI2_IMR (0xF800404CU) /**< \brief (HSMCI2) Interrupt Mask Register */ +#define REG_HSMCI2_DMA (0xF8004050U) /**< \brief (HSMCI2) DMA Configuration Register */ +#define REG_HSMCI2_CFG (0xF8004054U) /**< \brief (HSMCI2) Configuration Register */ +#define REG_HSMCI2_WPMR (0xF80040E4U) /**< \brief (HSMCI2) Write Protection Mode Register */ +#define REG_HSMCI2_WPSR (0xF80040E8U) /**< \brief (HSMCI2) Write Protection Status Register */ +#define REG_HSMCI2_FIFO (0xF8004200U) /**< \brief (HSMCI2) FIFO Memory Aperture0 */ +#else +#define REG_HSMCI2_CR (*(WoReg*)0xF8004000U) /**< \brief (HSMCI2) Control Register */ +#define REG_HSMCI2_MR (*(RwReg*)0xF8004004U) /**< \brief (HSMCI2) Mode Register */ +#define REG_HSMCI2_DTOR (*(RwReg*)0xF8004008U) /**< \brief (HSMCI2) Data Timeout Register */ +#define REG_HSMCI2_SDCR (*(RwReg*)0xF800400CU) /**< \brief (HSMCI2) SD/SDIO Card Register */ +#define REG_HSMCI2_ARGR (*(RwReg*)0xF8004010U) /**< \brief (HSMCI2) Argument Register */ +#define REG_HSMCI2_CMDR (*(WoReg*)0xF8004014U) /**< \brief (HSMCI2) Command Register */ +#define REG_HSMCI2_BLKR (*(RwReg*)0xF8004018U) /**< \brief (HSMCI2) Block Register */ +#define REG_HSMCI2_CSTOR (*(RwReg*)0xF800401CU) /**< \brief (HSMCI2) Completion Signal Timeout Register */ +#define REG_HSMCI2_RSPR (*(RoReg*)0xF8004020U) /**< \brief (HSMCI2) Response Register */ +#define REG_HSMCI2_RDR (*(RoReg*)0xF8004030U) /**< \brief (HSMCI2) Receive Data Register */ +#define REG_HSMCI2_TDR (*(WoReg*)0xF8004034U) /**< \brief (HSMCI2) Transmit Data Register */ +#define REG_HSMCI2_SR (*(RoReg*)0xF8004040U) /**< \brief (HSMCI2) Status Register */ +#define REG_HSMCI2_IER (*(WoReg*)0xF8004044U) /**< \brief (HSMCI2) Interrupt Enable Register */ +#define REG_HSMCI2_IDR (*(WoReg*)0xF8004048U) /**< \brief (HSMCI2) Interrupt Disable Register */ +#define REG_HSMCI2_IMR (*(RoReg*)0xF800404CU) /**< \brief (HSMCI2) Interrupt Mask Register */ +#define REG_HSMCI2_DMA (*(RwReg*)0xF8004050U) /**< \brief (HSMCI2) DMA Configuration Register */ +#define REG_HSMCI2_CFG (*(RwReg*)0xF8004054U) /**< \brief (HSMCI2) Configuration Register */ +#define REG_HSMCI2_WPMR (*(RwReg*)0xF80040E4U) /**< \brief (HSMCI2) Write Protection Mode Register */ +#define REG_HSMCI2_WPSR (*(RoReg*)0xF80040E8U) /**< \brief (HSMCI2) Write Protection Status Register */ +#define REG_HSMCI2_FIFO (*(RwReg*)0xF8004200U) /**< \brief (HSMCI2) FIFO Memory Aperture0 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_HSMCI2_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_isi.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_isi.h new file mode 100644 index 0000000..14c6671 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_isi.h
@@ -0,0 +1,88 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_ISI_INSTANCE_ +#define _SAMA5_ISI_INSTANCE_ + +/* ========== Register definition for ISI peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_ISI_CFG1 (0xF0034000U) /**< \brief (ISI) ISI Configuration 1 Register */ +#define REG_ISI_CFG2 (0xF0034004U) /**< \brief (ISI) ISI Configuration 2 Register */ +#define REG_ISI_PSIZE (0xF0034008U) /**< \brief (ISI) ISI Preview Size Register */ +#define REG_ISI_PDECF (0xF003400CU) /**< \brief (ISI) ISI Preview Decimation Factor Register */ +#define REG_ISI_Y2R_SET0 (0xF0034010U) /**< \brief (ISI) ISI CSC YCrCb To RGB Set 0 Register */ +#define REG_ISI_Y2R_SET1 (0xF0034014U) /**< \brief (ISI) ISI CSC YCrCb To RGB Set 1 Register */ +#define REG_ISI_R2Y_SET0 (0xF0034018U) /**< \brief (ISI) ISI CSC RGB To YCrCb Set 0 Register */ +#define REG_ISI_R2Y_SET1 (0xF003401CU) /**< \brief (ISI) ISI CSC RGB To YCrCb Set 1 Register */ +#define REG_ISI_R2Y_SET2 (0xF0034020U) /**< \brief (ISI) ISI CSC RGB To YCrCb Set 2 Register */ +#define REG_ISI_CR (0xF0034024U) /**< \brief (ISI) ISI Control Register */ +#define REG_ISI_SR (0xF0034028U) /**< \brief (ISI) ISI Status Register */ +#define REG_ISI_IER (0xF003402CU) /**< \brief (ISI) ISI Interrupt Enable Register */ +#define REG_ISI_IDR (0xF0034030U) /**< \brief (ISI) ISI Interrupt Disable Register */ +#define REG_ISI_IMR (0xF0034034U) /**< \brief (ISI) ISI Interrupt Mask Register */ +#define REG_ISI_DMA_CHER (0xF0034038U) /**< \brief (ISI) DMA Channel Enable Register */ +#define REG_ISI_DMA_CHDR (0xF003403CU) /**< \brief (ISI) DMA Channel Disable Register */ +#define REG_ISI_DMA_CHSR (0xF0034040U) /**< \brief (ISI) DMA Channel Status Register */ +#define REG_ISI_DMA_P_ADDR (0xF0034044U) /**< \brief (ISI) DMA Preview Base Address Register */ +#define REG_ISI_DMA_P_CTRL (0xF0034048U) /**< \brief (ISI) DMA Preview Control Register */ +#define REG_ISI_DMA_P_DSCR (0xF003404CU) /**< \brief (ISI) DMA Preview Descriptor Address Register */ +#define REG_ISI_DMA_C_ADDR (0xF0034050U) /**< \brief (ISI) DMA Codec Base Address Register */ +#define REG_ISI_DMA_C_CTRL (0xF0034054U) /**< \brief (ISI) DMA Codec Control Register */ +#define REG_ISI_DMA_C_DSCR (0xF0034058U) /**< \brief (ISI) DMA Codec Descriptor Address Register */ +#define REG_ISI_WPCR (0xF00340E4U) /**< \brief (ISI) Write Protection Control Register */ +#define REG_ISI_WPSR (0xF00340E8U) /**< \brief (ISI) Write Protection Status Register */ +#else +#define REG_ISI_CFG1 (*(RwReg*)0xF0034000U) /**< \brief (ISI) ISI Configuration 1 Register */ +#define REG_ISI_CFG2 (*(RwReg*)0xF0034004U) /**< \brief (ISI) ISI Configuration 2 Register */ +#define REG_ISI_PSIZE (*(RwReg*)0xF0034008U) /**< \brief (ISI) ISI Preview Size Register */ +#define REG_ISI_PDECF (*(RwReg*)0xF003400CU) /**< \brief (ISI) ISI Preview Decimation Factor Register */ +#define REG_ISI_Y2R_SET0 (*(RwReg*)0xF0034010U) /**< \brief (ISI) ISI CSC YCrCb To RGB Set 0 Register */ +#define REG_ISI_Y2R_SET1 (*(RwReg*)0xF0034014U) /**< \brief (ISI) ISI CSC YCrCb To RGB Set 1 Register */ +#define REG_ISI_R2Y_SET0 (*(RwReg*)0xF0034018U) /**< \brief (ISI) ISI CSC RGB To YCrCb Set 0 Register */ +#define REG_ISI_R2Y_SET1 (*(RwReg*)0xF003401CU) /**< \brief (ISI) ISI CSC RGB To YCrCb Set 1 Register */ +#define REG_ISI_R2Y_SET2 (*(RwReg*)0xF0034020U) /**< \brief (ISI) ISI CSC RGB To YCrCb Set 2 Register */ +#define REG_ISI_CR (*(WoReg*)0xF0034024U) /**< \brief (ISI) ISI Control Register */ +#define REG_ISI_SR (*(RoReg*)0xF0034028U) /**< \brief (ISI) ISI Status Register */ +#define REG_ISI_IER (*(WoReg*)0xF003402CU) /**< \brief (ISI) ISI Interrupt Enable Register */ +#define REG_ISI_IDR (*(WoReg*)0xF0034030U) /**< \brief (ISI) ISI Interrupt Disable Register */ +#define REG_ISI_IMR (*(RoReg*)0xF0034034U) /**< \brief (ISI) ISI Interrupt Mask Register */ +#define REG_ISI_DMA_CHER (*(WoReg*)0xF0034038U) /**< \brief (ISI) DMA Channel Enable Register */ +#define REG_ISI_DMA_CHDR (*(WoReg*)0xF003403CU) /**< \brief (ISI) DMA Channel Disable Register */ +#define REG_ISI_DMA_CHSR (*(RoReg*)0xF0034040U) /**< \brief (ISI) DMA Channel Status Register */ +#define REG_ISI_DMA_P_ADDR (*(RwReg*)0xF0034044U) /**< \brief (ISI) DMA Preview Base Address Register */ +#define REG_ISI_DMA_P_CTRL (*(RwReg*)0xF0034048U) /**< \brief (ISI) DMA Preview Control Register */ +#define REG_ISI_DMA_P_DSCR (*(RwReg*)0xF003404CU) /**< \brief (ISI) DMA Preview Descriptor Address Register */ +#define REG_ISI_DMA_C_ADDR (*(RwReg*)0xF0034050U) /**< \brief (ISI) DMA Codec Base Address Register */ +#define REG_ISI_DMA_C_CTRL (*(RwReg*)0xF0034054U) /**< \brief (ISI) DMA Codec Control Register */ +#define REG_ISI_DMA_C_DSCR (*(RwReg*)0xF0034058U) /**< \brief (ISI) DMA Codec Descriptor Address Register */ +#define REG_ISI_WPCR (*(RwReg*)0xF00340E4U) /**< \brief (ISI) Write Protection Control Register */ +#define REG_ISI_WPSR (*(RoReg*)0xF00340E8U) /**< \brief (ISI) Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_ISI_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_lcdc.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_lcdc.h new file mode 100644 index 0000000..85a5999 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_lcdc.h
@@ -0,0 +1,392 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_LCDC_INSTANCE_ +#define _SAMA5_LCDC_INSTANCE_ + +/* ========== Register definition for LCDC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_LCDC_LCDCFG0 (0xF0030000U) /**< \brief (LCDC) LCD Controller Configuration Register 0 */ +#define REG_LCDC_LCDCFG1 (0xF0030004U) /**< \brief (LCDC) LCD Controller Configuration Register 1 */ +#define REG_LCDC_LCDCFG2 (0xF0030008U) /**< \brief (LCDC) LCD Controller Configuration Register 2 */ +#define REG_LCDC_LCDCFG3 (0xF003000CU) /**< \brief (LCDC) LCD Controller Configuration Register 3 */ +#define REG_LCDC_LCDCFG4 (0xF0030010U) /**< \brief (LCDC) LCD Controller Configuration Register 4 */ +#define REG_LCDC_LCDCFG5 (0xF0030014U) /**< \brief (LCDC) LCD Controller Configuration Register 5 */ +#define REG_LCDC_LCDCFG6 (0xF0030018U) /**< \brief (LCDC) LCD Controller Configuration Register 6 */ +#define REG_LCDC_LCDEN (0xF0030020U) /**< \brief (LCDC) LCD Controller Enable Register */ +#define REG_LCDC_LCDDIS (0xF0030024U) /**< \brief (LCDC) LCD Controller Disable Register */ +#define REG_LCDC_LCDSR (0xF0030028U) /**< \brief (LCDC) LCD Controller Status Register */ +#define REG_LCDC_LCDIER (0xF003002CU) /**< \brief (LCDC) LCD Controller Interrupt Enable Register */ +#define REG_LCDC_LCDIDR (0xF0030030U) /**< \brief (LCDC) LCD Controller Interrupt Disable Register */ +#define REG_LCDC_LCDIMR (0xF0030034U) /**< \brief (LCDC) LCD Controller Interrupt Mask Register */ +#define REG_LCDC_LCDISR (0xF0030038U) /**< \brief (LCDC) LCD Controller Interrupt Status Register */ +#define REG_LCDC_BASECHER (0xF0030040U) /**< \brief (LCDC) Base Layer Channel Enable Register */ +#define REG_LCDC_BASECHDR (0xF0030044U) /**< \brief (LCDC) Base Layer Channel Disable Register */ +#define REG_LCDC_BASECHSR (0xF0030048U) /**< \brief (LCDC) Base Layer Channel Status Register */ +#define REG_LCDC_BASEIER (0xF003004CU) /**< \brief (LCDC) Base Layer Interrupt Enable Register */ +#define REG_LCDC_BASEIDR (0xF0030050U) /**< \brief (LCDC) Base Layer Interrupt Disabled Register */ +#define REG_LCDC_BASEIMR (0xF0030054U) /**< \brief (LCDC) Base Layer Interrupt Mask Register */ +#define REG_LCDC_BASEISR (0xF0030058U) /**< \brief (LCDC) Base Layer Interrupt status Register */ +#define REG_LCDC_BASEHEAD (0xF003005CU) /**< \brief (LCDC) Base DMA Head Register */ +#define REG_LCDC_BASEADDR (0xF0030060U) /**< \brief (LCDC) Base DMA Address Register */ +#define REG_LCDC_BASECTRL (0xF0030064U) /**< \brief (LCDC) Base DMA Control Register */ +#define REG_LCDC_BASENEXT (0xF0030068U) /**< \brief (LCDC) Base DMA Next Register */ +#define REG_LCDC_BASECFG0 (0xF003006CU) /**< \brief (LCDC) Base Configuration register 0 */ +#define REG_LCDC_BASECFG1 (0xF0030070U) /**< \brief (LCDC) Base Configuration register 1 */ +#define REG_LCDC_BASECFG2 (0xF0030074U) /**< \brief (LCDC) Base Configuration register 2 */ +#define REG_LCDC_BASECFG3 (0xF0030078U) /**< \brief (LCDC) Base Configuration register 3 */ +#define REG_LCDC_BASECFG4 (0xF003007CU) /**< \brief (LCDC) Base Configuration register 4 */ +#define REG_LCDC_BASECFG5 (0xF0030080U) /**< \brief (LCDC) Base Configuration register 5 */ +#define REG_LCDC_BASECFG6 (0xF0030084U) /**< \brief (LCDC) Base Configuration register 6 */ +#define REG_LCDC_OVR1CHER (0xF0030140U) /**< \brief (LCDC) Overlay 1 Channel Enable Register */ +#define REG_LCDC_OVR1CHDR (0xF0030144U) /**< \brief (LCDC) Overlay 1 Channel Disable Register */ +#define REG_LCDC_OVR1CHSR (0xF0030148U) /**< \brief (LCDC) Overlay 1 Channel Status Register */ +#define REG_LCDC_OVR1IER (0xF003014CU) /**< \brief (LCDC) Overlay 1 Interrupt Enable Register */ +#define REG_LCDC_OVR1IDR (0xF0030150U) /**< \brief (LCDC) Overlay 1 Interrupt Disable Register */ +#define REG_LCDC_OVR1IMR (0xF0030154U) /**< \brief (LCDC) Overlay 1 Interrupt Mask Register */ +#define REG_LCDC_OVR1ISR (0xF0030158U) /**< \brief (LCDC) Overlay 1 Interrupt Status Register */ +#define REG_LCDC_OVR1HEAD (0xF003015CU) /**< \brief (LCDC) Overlay 1 DMA Head Register */ +#define REG_LCDC_OVR1ADDR (0xF0030160U) /**< \brief (LCDC) Overlay 1 DMA Address Register */ +#define REG_LCDC_OVR1CTRL (0xF0030164U) /**< \brief (LCDC) Overlay1 DMA Control Register */ +#define REG_LCDC_OVR1NEXT (0xF0030168U) /**< \brief (LCDC) Overlay1 DMA Next Register */ +#define REG_LCDC_OVR1CFG0 (0xF003016CU) /**< \brief (LCDC) Overlay 1 Configuration 0 Register */ +#define REG_LCDC_OVR1CFG1 (0xF0030170U) /**< \brief (LCDC) Overlay 1 Configuration 1 Register */ +#define REG_LCDC_OVR1CFG2 (0xF0030174U) /**< \brief (LCDC) Overlay 1 Configuration 2 Register */ +#define REG_LCDC_OVR1CFG3 (0xF0030178U) /**< \brief (LCDC) Overlay 1 Configuration 3 Register */ +#define REG_LCDC_OVR1CFG4 (0xF003017CU) /**< \brief (LCDC) Overlay 1 Configuration 4 Register */ +#define REG_LCDC_OVR1CFG5 (0xF0030180U) /**< \brief (LCDC) Overlay 1 Configuration 5 Register */ +#define REG_LCDC_OVR1CFG6 (0xF0030184U) /**< \brief (LCDC) Overlay 1 Configuration 6 Register */ +#define REG_LCDC_OVR1CFG7 (0xF0030188U) /**< \brief (LCDC) Overlay 1 Configuration 7 Register */ +#define REG_LCDC_OVR1CFG8 (0xF003018CU) /**< \brief (LCDC) Overlay 1 Configuration 8Register */ +#define REG_LCDC_OVR1CFG9 (0xF0030190U) /**< \brief (LCDC) Overlay 1 Configuration 9 Register */ +#define REG_LCDC_OVR2CHER (0xF0030240U) /**< \brief (LCDC) Overlay 2 Channel Enable Register */ +#define REG_LCDC_OVR2CHDR (0xF0030244U) /**< \brief (LCDC) Overlay 2 Channel Disable Register */ +#define REG_LCDC_OVR2CHSR (0xF0030248U) /**< \brief (LCDC) Overlay 2 Channel Status Register */ +#define REG_LCDC_OVR2IER (0xF003024CU) /**< \brief (LCDC) Overlay 2 Interrupt Enable Register */ +#define REG_LCDC_OVR2IDR (0xF0030250U) /**< \brief (LCDC) Overlay 2 Interrupt Disable Register */ +#define REG_LCDC_OVR2IMR (0xF0030254U) /**< \brief (LCDC) Overlay 2 Interrupt Mask Register */ +#define REG_LCDC_OVR2ISR (0xF0030258U) /**< \brief (LCDC) Overlay 2 Interrupt status Register */ +#define REG_LCDC_OVR2HEAD (0xF003025CU) /**< \brief (LCDC) Overlay 2 DMA Head Register */ +#define REG_LCDC_OVR2ADDR (0xF0030260U) /**< \brief (LCDC) Overlay 2 DMA Address Register */ +#define REG_LCDC_OVR2CTRL (0xF0030264U) /**< \brief (LCDC) Overlay 2 DMA Control Register */ +#define REG_LCDC_OVR2NEXT (0xF0030268U) /**< \brief (LCDC) Overlay 2 DMA Next Register */ +#define REG_LCDC_OVR2CFG0 (0xF003026CU) /**< \brief (LCDC) Overlay 2 Configuration 0 Register */ +#define REG_LCDC_OVR2CFG1 (0xF0030270U) /**< \brief (LCDC) Overlay 2 Configuration 1 Register */ +#define REG_LCDC_OVR2CFG2 (0xF0030274U) /**< \brief (LCDC) Overlay 2 Configuration 2 Register */ +#define REG_LCDC_OVR2CFG3 (0xF0030278U) /**< \brief (LCDC) Overlay 2 Configuration 3 Register */ +#define REG_LCDC_OVR2CFG4 (0xF003027CU) /**< \brief (LCDC) Overlay 2 Configuration 4 Register */ +#define REG_LCDC_OVR2CFG5 (0xF0030280U) /**< \brief (LCDC) Overlay 2 Configuration 5 Register */ +#define REG_LCDC_OVR2CFG6 (0xF0030284U) /**< \brief (LCDC) Overlay 2 Configuration 6 Register */ +#define REG_LCDC_OVR2CFG7 (0xF0030288U) /**< \brief (LCDC) Overlay 2 Configuration 7 Register */ +#define REG_LCDC_OVR2CFG8 (0xF003028CU) /**< \brief (LCDC) Overlay 2 Configuration 8 Register */ +#define REG_LCDC_OVR2CFG9 (0xF0030290U) /**< \brief (LCDC) Overlay 2 Configuration 9 Register */ +#define REG_LCDC_HEOCHER (0xF0030340U) /**< \brief (LCDC) High-End Overlay Channel Enable Register */ +#define REG_LCDC_HEOCHDR (0xF0030344U) /**< \brief (LCDC) High-End Overlay Channel Disable Register */ +#define REG_LCDC_HEOCHSR (0xF0030348U) /**< \brief (LCDC) High-End Overlay Channel Status Register */ +#define REG_LCDC_HEOIER (0xF003034CU) /**< \brief (LCDC) High-End Overlay Interrupt Enable Register */ +#define REG_LCDC_HEOIDR (0xF0030350U) /**< \brief (LCDC) High-End Overlay Interrupt Disable Register */ +#define REG_LCDC_HEOIMR (0xF0030354U) /**< \brief (LCDC) High-End Overlay Interrupt Mask Register */ +#define REG_LCDC_HEOISR (0xF0030358U) /**< \brief (LCDC) High-End Overlay Interrupt Status Register */ +#define REG_LCDC_HEOHEAD (0xF003035CU) /**< \brief (LCDC) High-End Overlay DMA Head Register */ +#define REG_LCDC_HEOADDR (0xF0030360U) /**< \brief (LCDC) High-End Overlay DMA Address Register */ +#define REG_LCDC_HEOCTRL (0xF0030364U) /**< \brief (LCDC) High-End Overlay DMA Control Register */ +#define REG_LCDC_HEONEXT (0xF0030368U) /**< \brief (LCDC) High-End Overlay DMA Next Register */ +#define REG_LCDC_HEOUHEAD (0xF003036CU) /**< \brief (LCDC) High-End Overlay U DMA Head Register */ +#define REG_LCDC_HEOUADDR (0xF0030370U) /**< \brief (LCDC) High-End Overlay U DMA Address Register */ +#define REG_LCDC_HEOUCTRL (0xF0030374U) /**< \brief (LCDC) High-End Overlay U DMA control Register */ +#define REG_LCDC_HEOUNEXT (0xF0030378U) /**< \brief (LCDC) High-End Overlay U DMA Next Register */ +#define REG_LCDC_HEOVHEAD (0xF003037CU) /**< \brief (LCDC) High-End Overlay V DMA Head Register */ +#define REG_LCDC_HEOVADDR (0xF0030380U) /**< \brief (LCDC) High-End Overlay V DMA Address Register */ +#define REG_LCDC_HEOVCTRL (0xF0030384U) /**< \brief (LCDC) High-End Overlay V DMA control Register */ +#define REG_LCDC_HEOVNEXT (0xF0030388U) /**< \brief (LCDC) High-End Overlay VDMA Next Register */ +#define REG_LCDC_HEOCFG0 (0xF003038CU) /**< \brief (LCDC) High-End Overlay Configuration Register 0 */ +#define REG_LCDC_HEOCFG1 (0xF0030390U) /**< \brief (LCDC) High-End Overlay Configuration Register 1 */ +#define REG_LCDC_HEOCFG2 (0xF0030394U) /**< \brief (LCDC) High-End Overlay Configuration Register 2 */ +#define REG_LCDC_HEOCFG3 (0xF0030398U) /**< \brief (LCDC) High-End Overlay Configuration Register 3 */ +#define REG_LCDC_HEOCFG4 (0xF003039CU) /**< \brief (LCDC) High-End Overlay Configuration Register 4 */ +#define REG_LCDC_HEOCFG5 (0xF00303A0U) /**< \brief (LCDC) High-End Overlay Configuration Register 5 */ +#define REG_LCDC_HEOCFG6 (0xF00303A4U) /**< \brief (LCDC) High-End Overlay Configuration Register 6 */ +#define REG_LCDC_HEOCFG7 (0xF00303A8U) /**< \brief (LCDC) High-End Overlay Configuration Register 7 */ +#define REG_LCDC_HEOCFG8 (0xF00303ACU) /**< \brief (LCDC) High-End Overlay Configuration Register 8 */ +#define REG_LCDC_HEOCFG9 (0xF00303B0U) /**< \brief (LCDC) High-End Overlay Configuration Register 9 */ +#define REG_LCDC_HEOCFG10 (0xF00303B4U) /**< \brief (LCDC) High-End Overlay Configuration Register 10 */ +#define REG_LCDC_HEOCFG11 (0xF00303B8U) /**< \brief (LCDC) High-End Overlay Configuration Register 11 */ +#define REG_LCDC_HEOCFG12 (0xF00303BCU) /**< \brief (LCDC) High-End Overlay Configuration Register 12 */ +#define REG_LCDC_HEOCFG13 (0xF00303C0U) /**< \brief (LCDC) High-End Overlay Configuration Register 13 */ +#define REG_LCDC_HEOCFG14 (0xF00303C4U) /**< \brief (LCDC) High-End Overlay Configuration Register 14 */ +#define REG_LCDC_HEOCFG15 (0xF00303C8U) /**< \brief (LCDC) High-End Overlay Configuration Register 15 */ +#define REG_LCDC_HEOCFG16 (0xF00303CCU) /**< \brief (LCDC) High-End Overlay Configuration Register 16 */ +#define REG_LCDC_HEOCFG17 (0xF00303D0U) /**< \brief (LCDC) High-End Overlay Configuration Register 17 */ +#define REG_LCDC_HEOCFG18 (0xF00303D4U) /**< \brief (LCDC) High-End Overlay Configuration Register 18 */ +#define REG_LCDC_HEOCFG19 (0xF00303D8U) /**< \brief (LCDC) High-End Overlay Configuration Register 19 */ +#define REG_LCDC_HEOCFG20 (0xF00303DCU) /**< \brief (LCDC) High-End Overlay Configuration Register 20 */ +#define REG_LCDC_HEOCFG21 (0xF00303E0U) /**< \brief (LCDC) High-End Overlay Configuration Register 21 */ +#define REG_LCDC_HEOCFG22 (0xF00303E4U) /**< \brief (LCDC) High-End Overlay Configuration Register 22 */ +#define REG_LCDC_HEOCFG23 (0xF00303E8U) /**< \brief (LCDC) High-End Overlay Configuration Register 23 */ +#define REG_LCDC_HEOCFG24 (0xF00303ECU) /**< \brief (LCDC) High-End Overlay Configuration Register 24 */ +#define REG_LCDC_HEOCFG25 (0xF00303F0U) /**< \brief (LCDC) High-End Overlay Configuration Register 25 */ +#define REG_LCDC_HEOCFG26 (0xF00303F4U) /**< \brief (LCDC) High-End Overlay Configuration Register 26 */ +#define REG_LCDC_HEOCFG27 (0xF00303F8U) /**< \brief (LCDC) High-End Overlay Configuration Register 27 */ +#define REG_LCDC_HEOCFG28 (0xF00303FCU) /**< \brief (LCDC) High-End Overlay Configuration Register 28 */ +#define REG_LCDC_HEOCFG29 (0xF0030400U) /**< \brief (LCDC) High-End Overlay Configuration Register 29 */ +#define REG_LCDC_HEOCFG30 (0xF0030404U) /**< \brief (LCDC) High-End Overlay Configuration Register 30 */ +#define REG_LCDC_HEOCFG31 (0xF0030408U) /**< \brief (LCDC) High-End Overlay Configuration Register 31 */ +#define REG_LCDC_HEOCFG32 (0xF003040CU) /**< \brief (LCDC) High-End Overlay Configuration Register 32 */ +#define REG_LCDC_HEOCFG33 (0xF0030410U) /**< \brief (LCDC) High-End Overlay Configuration Register 33 */ +#define REG_LCDC_HEOCFG34 (0xF0030414U) /**< \brief (LCDC) High-End Overlay Configuration Register 34 */ +#define REG_LCDC_HEOCFG35 (0xF0030418U) /**< \brief (LCDC) High-End Overlay Configuration Register 35 */ +#define REG_LCDC_HEOCFG36 (0xF003041CU) /**< \brief (LCDC) High-End Overlay Configuration Register 36 */ +#define REG_LCDC_HEOCFG37 (0xF0030420U) /**< \brief (LCDC) High-End Overlay Configuration Register 37 */ +#define REG_LCDC_HEOCFG38 (0xF0030424U) /**< \brief (LCDC) High-End Overlay Configuration Register 38 */ +#define REG_LCDC_HEOCFG39 (0xF0030428U) /**< \brief (LCDC) High-End Overlay Configuration Register 39 */ +#define REG_LCDC_HEOCFG40 (0xF003042CU) /**< \brief (LCDC) High-End Overlay Configuration Register 40 */ +#define REG_LCDC_HEOCFG41 (0xF0030430U) /**< \brief (LCDC) High-End Overlay Configuration Register 41 */ +#define REG_LCDC_HCRCHER (0xF0030440U) /**< \brief (LCDC) Hardware Cursor Channel Enable Register */ +#define REG_LCDC_HCRCHDR (0xF0030444U) /**< \brief (LCDC) Hardware Cursor Channel disable Register */ +#define REG_LCDC_HCRCHSR (0xF0030448U) /**< \brief (LCDC) Hardware Cursor Channel Status Register */ +#define REG_LCDC_HCRIER (0xF003044CU) /**< \brief (LCDC) Hardware Cursor Interrupt Enable Register */ +#define REG_LCDC_HCRIDR (0xF0030450U) /**< \brief (LCDC) Hardware Cursor Interrupt Disable Register */ +#define REG_LCDC_HCRIMR (0xF0030454U) /**< \brief (LCDC) Hardware Cursor Interrupt Mask Register */ +#define REG_LCDC_HCRISR (0xF0030458U) /**< \brief (LCDC) Hardware Cursor Interrupt Status Register */ +#define REG_LCDC_HCRHEAD (0xF003045CU) /**< \brief (LCDC) Hardware Cursor DMA Head Register */ +#define REG_LCDC_HCRADDR (0xF0030460U) /**< \brief (LCDC) Hardware cursor DMA Address Register */ +#define REG_LCDC_HCRCTRL (0xF0030464U) /**< \brief (LCDC) Hardware Cursor DMA Control Register */ +#define REG_LCDC_HCRNEXT (0xF0030468U) /**< \brief (LCDC) Hardware Cursor DMA NExt Register */ +#define REG_LCDC_HCRCFG0 (0xF003046CU) /**< \brief (LCDC) Hardware Cursor Configuration 0 Register */ +#define REG_LCDC_HCRCFG1 (0xF0030470U) /**< \brief (LCDC) Hardware Cursor Configuration 1 Register */ +#define REG_LCDC_HCRCFG2 (0xF0030474U) /**< \brief (LCDC) Hardware Cursor Configuration 2 Register */ +#define REG_LCDC_HCRCFG3 (0xF0030478U) /**< \brief (LCDC) Hardware Cursor Configuration 3 Register */ +#define REG_LCDC_HCRCFG4 (0xF003047CU) /**< \brief (LCDC) Hardware Cursor Configuration 4 Register */ +#define REG_LCDC_HCRCFG6 (0xF0030484U) /**< \brief (LCDC) Hardware Cursor Configuration 6 Register */ +#define REG_LCDC_HCRCFG7 (0xF0030488U) /**< \brief (LCDC) Hardware Cursor Configuration 7 Register */ +#define REG_LCDC_HCRCFG8 (0xF003048CU) /**< \brief (LCDC) Hardware Cursor Configuration 8 Register */ +#define REG_LCDC_HCRCFG9 (0xF0030490U) /**< \brief (LCDC) Hardware Cursor Configuration 9 Register */ +#define REG_LCDC_PPCHER (0xF0030540U) /**< \brief (LCDC) Post Processing Channel Enable Register */ +#define REG_LCDC_PPCHDR (0xF0030544U) /**< \brief (LCDC) Post Processing Channel Disable Register */ +#define REG_LCDC_PPCHSR (0xF0030548U) /**< \brief (LCDC) Post Processing Channel Status Register */ +#define REG_LCDC_PPIER (0xF003054CU) /**< \brief (LCDC) Post Processing Interrupt Enable Register */ +#define REG_LCDC_PPIDR (0xF0030550U) /**< \brief (LCDC) Post Processing Interrupt Disable Register */ +#define REG_LCDC_PPIMR (0xF0030554U) /**< \brief (LCDC) Post Processing Interrupt Mask Register */ +#define REG_LCDC_PPISR (0xF0030558U) /**< \brief (LCDC) Post Processing Interrupt Status Register */ +#define REG_LCDC_PPHEAD (0xF003055CU) /**< \brief (LCDC) Post Processing Head Register */ +#define REG_LCDC_PPADDR (0xF0030560U) /**< \brief (LCDC) Post Processing Address Register */ +#define REG_LCDC_PPCTRL (0xF0030564U) /**< \brief (LCDC) Post Processing Control Register */ +#define REG_LCDC_PPNEXT (0xF0030568U) /**< \brief (LCDC) Post Processing Next Register */ +#define REG_LCDC_PPCFG0 (0xF003056CU) /**< \brief (LCDC) Post Processing Configuration Register 0 */ +#define REG_LCDC_PPCFG1 (0xF0030570U) /**< \brief (LCDC) Post Processing Configuration Register 1 */ +#define REG_LCDC_PPCFG2 (0xF0030574U) /**< \brief (LCDC) Post Processing Configuration Register 2 */ +#define REG_LCDC_PPCFG3 (0xF0030578U) /**< \brief (LCDC) Post Processing Configuration Register 3 */ +#define REG_LCDC_PPCFG4 (0xF003057CU) /**< \brief (LCDC) Post Processing Configuration Register 4 */ +#define REG_LCDC_PPCFG5 (0xF0030580U) /**< \brief (LCDC) Post Processing Configuration Register 5 */ +#define REG_LCDC_BASECLUT (0xF0030600U) /**< \brief (LCDC) Base CLUT Register */ +#define REG_LCDC_OVR1CLUT (0xF0030A00U) /**< \brief (LCDC) Overlay 1 CLUT Register */ +#define REG_LCDC_OVR2CLUT (0xF0030E00U) /**< \brief (LCDC) Overlay 2 CLUT Register */ +#define REG_LCDC_HEOCLUT (0xF0031200U) /**< \brief (LCDC) High End Overlay CLUT Register */ +#define REG_LCDC_HCRCLUT (0xF0031600U) /**< \brief (LCDC) Hardware Cursor CLUT Register */ +#else +#define REG_LCDC_LCDCFG0 (*(RwReg*)0xF0030000U) /**< \brief (LCDC) LCD Controller Configuration Register 0 */ +#define REG_LCDC_LCDCFG1 (*(RwReg*)0xF0030004U) /**< \brief (LCDC) LCD Controller Configuration Register 1 */ +#define REG_LCDC_LCDCFG2 (*(RwReg*)0xF0030008U) /**< \brief (LCDC) LCD Controller Configuration Register 2 */ +#define REG_LCDC_LCDCFG3 (*(RwReg*)0xF003000CU) /**< \brief (LCDC) LCD Controller Configuration Register 3 */ +#define REG_LCDC_LCDCFG4 (*(RwReg*)0xF0030010U) /**< \brief (LCDC) LCD Controller Configuration Register 4 */ +#define REG_LCDC_LCDCFG5 (*(RwReg*)0xF0030014U) /**< \brief (LCDC) LCD Controller Configuration Register 5 */ +#define REG_LCDC_LCDCFG6 (*(RwReg*)0xF0030018U) /**< \brief (LCDC) LCD Controller Configuration Register 6 */ +#define REG_LCDC_LCDEN (*(WoReg*)0xF0030020U) /**< \brief (LCDC) LCD Controller Enable Register */ +#define REG_LCDC_LCDDIS (*(WoReg*)0xF0030024U) /**< \brief (LCDC) LCD Controller Disable Register */ +#define REG_LCDC_LCDSR (*(RoReg*)0xF0030028U) /**< \brief (LCDC) LCD Controller Status Register */ +#define REG_LCDC_LCDIER (*(WoReg*)0xF003002CU) /**< \brief (LCDC) LCD Controller Interrupt Enable Register */ +#define REG_LCDC_LCDIDR (*(WoReg*)0xF0030030U) /**< \brief (LCDC) LCD Controller Interrupt Disable Register */ +#define REG_LCDC_LCDIMR (*(RoReg*)0xF0030034U) /**< \brief (LCDC) LCD Controller Interrupt Mask Register */ +#define REG_LCDC_LCDISR (*(RoReg*)0xF0030038U) /**< \brief (LCDC) LCD Controller Interrupt Status Register */ +#define REG_LCDC_BASECHER (*(WoReg*)0xF0030040U) /**< \brief (LCDC) Base Layer Channel Enable Register */ +#define REG_LCDC_BASECHDR (*(WoReg*)0xF0030044U) /**< \brief (LCDC) Base Layer Channel Disable Register */ +#define REG_LCDC_BASECHSR (*(RoReg*)0xF0030048U) /**< \brief (LCDC) Base Layer Channel Status Register */ +#define REG_LCDC_BASEIER (*(WoReg*)0xF003004CU) /**< \brief (LCDC) Base Layer Interrupt Enable Register */ +#define REG_LCDC_BASEIDR (*(WoReg*)0xF0030050U) /**< \brief (LCDC) Base Layer Interrupt Disabled Register */ +#define REG_LCDC_BASEIMR (*(RoReg*)0xF0030054U) /**< \brief (LCDC) Base Layer Interrupt Mask Register */ +#define REG_LCDC_BASEISR (*(RoReg*)0xF0030058U) /**< \brief (LCDC) Base Layer Interrupt status Register */ +#define REG_LCDC_BASEHEAD (*(RwReg*)0xF003005CU) /**< \brief (LCDC) Base DMA Head Register */ +#define REG_LCDC_BASEADDR (*(RwReg*)0xF0030060U) /**< \brief (LCDC) Base DMA Address Register */ +#define REG_LCDC_BASECTRL (*(RwReg*)0xF0030064U) /**< \brief (LCDC) Base DMA Control Register */ +#define REG_LCDC_BASENEXT (*(RwReg*)0xF0030068U) /**< \brief (LCDC) Base DMA Next Register */ +#define REG_LCDC_BASECFG0 (*(RwReg*)0xF003006CU) /**< \brief (LCDC) Base Configuration register 0 */ +#define REG_LCDC_BASECFG1 (*(RwReg*)0xF0030070U) /**< \brief (LCDC) Base Configuration register 1 */ +#define REG_LCDC_BASECFG2 (*(RwReg*)0xF0030074U) /**< \brief (LCDC) Base Configuration register 2 */ +#define REG_LCDC_BASECFG3 (*(RwReg*)0xF0030078U) /**< \brief (LCDC) Base Configuration register 3 */ +#define REG_LCDC_BASECFG4 (*(RwReg*)0xF003007CU) /**< \brief (LCDC) Base Configuration register 4 */ +#define REG_LCDC_BASECFG5 (*(RwReg*)0xF0030080U) /**< \brief (LCDC) Base Configuration register 5 */ +#define REG_LCDC_BASECFG6 (*(RwReg*)0xF0030084U) /**< \brief (LCDC) Base Configuration register 6 */ +#define REG_LCDC_OVR1CHER (*(WoReg*)0xF0030140U) /**< \brief (LCDC) Overlay 1 Channel Enable Register */ +#define REG_LCDC_OVR1CHDR (*(WoReg*)0xF0030144U) /**< \brief (LCDC) Overlay 1 Channel Disable Register */ +#define REG_LCDC_OVR1CHSR (*(RoReg*)0xF0030148U) /**< \brief (LCDC) Overlay 1 Channel Status Register */ +#define REG_LCDC_OVR1IER (*(WoReg*)0xF003014CU) /**< \brief (LCDC) Overlay 1 Interrupt Enable Register */ +#define REG_LCDC_OVR1IDR (*(WoReg*)0xF0030150U) /**< \brief (LCDC) Overlay 1 Interrupt Disable Register */ +#define REG_LCDC_OVR1IMR (*(RoReg*)0xF0030154U) /**< \brief (LCDC) Overlay 1 Interrupt Mask Register */ +#define REG_LCDC_OVR1ISR (*(RoReg*)0xF0030158U) /**< \brief (LCDC) Overlay 1 Interrupt Status Register */ +#define REG_LCDC_OVR1HEAD (*(RwReg*)0xF003015CU) /**< \brief (LCDC) Overlay 1 DMA Head Register */ +#define REG_LCDC_OVR1ADDR (*(RwReg*)0xF0030160U) /**< \brief (LCDC) Overlay 1 DMA Address Register */ +#define REG_LCDC_OVR1CTRL (*(RwReg*)0xF0030164U) /**< \brief (LCDC) Overlay1 DMA Control Register */ +#define REG_LCDC_OVR1NEXT (*(RwReg*)0xF0030168U) /**< \brief (LCDC) Overlay1 DMA Next Register */ +#define REG_LCDC_OVR1CFG0 (*(RwReg*)0xF003016CU) /**< \brief (LCDC) Overlay 1 Configuration 0 Register */ +#define REG_LCDC_OVR1CFG1 (*(RwReg*)0xF0030170U) /**< \brief (LCDC) Overlay 1 Configuration 1 Register */ +#define REG_LCDC_OVR1CFG2 (*(RwReg*)0xF0030174U) /**< \brief (LCDC) Overlay 1 Configuration 2 Register */ +#define REG_LCDC_OVR1CFG3 (*(RwReg*)0xF0030178U) /**< \brief (LCDC) Overlay 1 Configuration 3 Register */ +#define REG_LCDC_OVR1CFG4 (*(RwReg*)0xF003017CU) /**< \brief (LCDC) Overlay 1 Configuration 4 Register */ +#define REG_LCDC_OVR1CFG5 (*(RwReg*)0xF0030180U) /**< \brief (LCDC) Overlay 1 Configuration 5 Register */ +#define REG_LCDC_OVR1CFG6 (*(RwReg*)0xF0030184U) /**< \brief (LCDC) Overlay 1 Configuration 6 Register */ +#define REG_LCDC_OVR1CFG7 (*(RwReg*)0xF0030188U) /**< \brief (LCDC) Overlay 1 Configuration 7 Register */ +#define REG_LCDC_OVR1CFG8 (*(RwReg*)0xF003018CU) /**< \brief (LCDC) Overlay 1 Configuration 8Register */ +#define REG_LCDC_OVR1CFG9 (*(RwReg*)0xF0030190U) /**< \brief (LCDC) Overlay 1 Configuration 9 Register */ +#define REG_LCDC_OVR2CHER (*(WoReg*)0xF0030240U) /**< \brief (LCDC) Overlay 2 Channel Enable Register */ +#define REG_LCDC_OVR2CHDR (*(WoReg*)0xF0030244U) /**< \brief (LCDC) Overlay 2 Channel Disable Register */ +#define REG_LCDC_OVR2CHSR (*(RoReg*)0xF0030248U) /**< \brief (LCDC) Overlay 2 Channel Status Register */ +#define REG_LCDC_OVR2IER (*(WoReg*)0xF003024CU) /**< \brief (LCDC) Overlay 2 Interrupt Enable Register */ +#define REG_LCDC_OVR2IDR (*(WoReg*)0xF0030250U) /**< \brief (LCDC) Overlay 2 Interrupt Disable Register */ +#define REG_LCDC_OVR2IMR (*(RoReg*)0xF0030254U) /**< \brief (LCDC) Overlay 2 Interrupt Mask Register */ +#define REG_LCDC_OVR2ISR (*(RoReg*)0xF0030258U) /**< \brief (LCDC) Overlay 2 Interrupt status Register */ +#define REG_LCDC_OVR2HEAD (*(RwReg*)0xF003025CU) /**< \brief (LCDC) Overlay 2 DMA Head Register */ +#define REG_LCDC_OVR2ADDR (*(RwReg*)0xF0030260U) /**< \brief (LCDC) Overlay 2 DMA Address Register */ +#define REG_LCDC_OVR2CTRL (*(RwReg*)0xF0030264U) /**< \brief (LCDC) Overlay 2 DMA Control Register */ +#define REG_LCDC_OVR2NEXT (*(RwReg*)0xF0030268U) /**< \brief (LCDC) Overlay 2 DMA Next Register */ +#define REG_LCDC_OVR2CFG0 (*(RwReg*)0xF003026CU) /**< \brief (LCDC) Overlay 2 Configuration 0 Register */ +#define REG_LCDC_OVR2CFG1 (*(RwReg*)0xF0030270U) /**< \brief (LCDC) Overlay 2 Configuration 1 Register */ +#define REG_LCDC_OVR2CFG2 (*(RwReg*)0xF0030274U) /**< \brief (LCDC) Overlay 2 Configuration 2 Register */ +#define REG_LCDC_OVR2CFG3 (*(RwReg*)0xF0030278U) /**< \brief (LCDC) Overlay 2 Configuration 3 Register */ +#define REG_LCDC_OVR2CFG4 (*(RwReg*)0xF003027CU) /**< \brief (LCDC) Overlay 2 Configuration 4 Register */ +#define REG_LCDC_OVR2CFG5 (*(RwReg*)0xF0030280U) /**< \brief (LCDC) Overlay 2 Configuration 5 Register */ +#define REG_LCDC_OVR2CFG6 (*(RwReg*)0xF0030284U) /**< \brief (LCDC) Overlay 2 Configuration 6 Register */ +#define REG_LCDC_OVR2CFG7 (*(RwReg*)0xF0030288U) /**< \brief (LCDC) Overlay 2 Configuration 7 Register */ +#define REG_LCDC_OVR2CFG8 (*(RwReg*)0xF003028CU) /**< \brief (LCDC) Overlay 2 Configuration 8 Register */ +#define REG_LCDC_OVR2CFG9 (*(RwReg*)0xF0030290U) /**< \brief (LCDC) Overlay 2 Configuration 9 Register */ +#define REG_LCDC_HEOCHER (*(WoReg*)0xF0030340U) /**< \brief (LCDC) High-End Overlay Channel Enable Register */ +#define REG_LCDC_HEOCHDR (*(WoReg*)0xF0030344U) /**< \brief (LCDC) High-End Overlay Channel Disable Register */ +#define REG_LCDC_HEOCHSR (*(RoReg*)0xF0030348U) /**< \brief (LCDC) High-End Overlay Channel Status Register */ +#define REG_LCDC_HEOIER (*(WoReg*)0xF003034CU) /**< \brief (LCDC) High-End Overlay Interrupt Enable Register */ +#define REG_LCDC_HEOIDR (*(WoReg*)0xF0030350U) /**< \brief (LCDC) High-End Overlay Interrupt Disable Register */ +#define REG_LCDC_HEOIMR (*(RoReg*)0xF0030354U) /**< \brief (LCDC) High-End Overlay Interrupt Mask Register */ +#define REG_LCDC_HEOISR (*(RoReg*)0xF0030358U) /**< \brief (LCDC) High-End Overlay Interrupt Status Register */ +#define REG_LCDC_HEOHEAD (*(RwReg*)0xF003035CU) /**< \brief (LCDC) High-End Overlay DMA Head Register */ +#define REG_LCDC_HEOADDR (*(RwReg*)0xF0030360U) /**< \brief (LCDC) High-End Overlay DMA Address Register */ +#define REG_LCDC_HEOCTRL (*(RwReg*)0xF0030364U) /**< \brief (LCDC) High-End Overlay DMA Control Register */ +#define REG_LCDC_HEONEXT (*(RwReg*)0xF0030368U) /**< \brief (LCDC) High-End Overlay DMA Next Register */ +#define REG_LCDC_HEOUHEAD (*(RwReg*)0xF003036CU) /**< \brief (LCDC) High-End Overlay U DMA Head Register */ +#define REG_LCDC_HEOUADDR (*(RwReg*)0xF0030370U) /**< \brief (LCDC) High-End Overlay U DMA Address Register */ +#define REG_LCDC_HEOUCTRL (*(RwReg*)0xF0030374U) /**< \brief (LCDC) High-End Overlay U DMA control Register */ +#define REG_LCDC_HEOUNEXT (*(RwReg*)0xF0030378U) /**< \brief (LCDC) High-End Overlay U DMA Next Register */ +#define REG_LCDC_HEOVHEAD (*(RwReg*)0xF003037CU) /**< \brief (LCDC) High-End Overlay V DMA Head Register */ +#define REG_LCDC_HEOVADDR (*(RwReg*)0xF0030380U) /**< \brief (LCDC) High-End Overlay V DMA Address Register */ +#define REG_LCDC_HEOVCTRL (*(RwReg*)0xF0030384U) /**< \brief (LCDC) High-End Overlay V DMA control Register */ +#define REG_LCDC_HEOVNEXT (*(RwReg*)0xF0030388U) /**< \brief (LCDC) High-End Overlay VDMA Next Register */ +#define REG_LCDC_HEOCFG0 (*(RwReg*)0xF003038CU) /**< \brief (LCDC) High-End Overlay Configuration Register 0 */ +#define REG_LCDC_HEOCFG1 (*(RwReg*)0xF0030390U) /**< \brief (LCDC) High-End Overlay Configuration Register 1 */ +#define REG_LCDC_HEOCFG2 (*(RwReg*)0xF0030394U) /**< \brief (LCDC) High-End Overlay Configuration Register 2 */ +#define REG_LCDC_HEOCFG3 (*(RwReg*)0xF0030398U) /**< \brief (LCDC) High-End Overlay Configuration Register 3 */ +#define REG_LCDC_HEOCFG4 (*(RwReg*)0xF003039CU) /**< \brief (LCDC) High-End Overlay Configuration Register 4 */ +#define REG_LCDC_HEOCFG5 (*(RwReg*)0xF00303A0U) /**< \brief (LCDC) High-End Overlay Configuration Register 5 */ +#define REG_LCDC_HEOCFG6 (*(RwReg*)0xF00303A4U) /**< \brief (LCDC) High-End Overlay Configuration Register 6 */ +#define REG_LCDC_HEOCFG7 (*(RwReg*)0xF00303A8U) /**< \brief (LCDC) High-End Overlay Configuration Register 7 */ +#define REG_LCDC_HEOCFG8 (*(RwReg*)0xF00303ACU) /**< \brief (LCDC) High-End Overlay Configuration Register 8 */ +#define REG_LCDC_HEOCFG9 (*(RwReg*)0xF00303B0U) /**< \brief (LCDC) High-End Overlay Configuration Register 9 */ +#define REG_LCDC_HEOCFG10 (*(RwReg*)0xF00303B4U) /**< \brief (LCDC) High-End Overlay Configuration Register 10 */ +#define REG_LCDC_HEOCFG11 (*(RwReg*)0xF00303B8U) /**< \brief (LCDC) High-End Overlay Configuration Register 11 */ +#define REG_LCDC_HEOCFG12 (*(RwReg*)0xF00303BCU) /**< \brief (LCDC) High-End Overlay Configuration Register 12 */ +#define REG_LCDC_HEOCFG13 (*(RwReg*)0xF00303C0U) /**< \brief (LCDC) High-End Overlay Configuration Register 13 */ +#define REG_LCDC_HEOCFG14 (*(RwReg*)0xF00303C4U) /**< \brief (LCDC) High-End Overlay Configuration Register 14 */ +#define REG_LCDC_HEOCFG15 (*(RwReg*)0xF00303C8U) /**< \brief (LCDC) High-End Overlay Configuration Register 15 */ +#define REG_LCDC_HEOCFG16 (*(RwReg*)0xF00303CCU) /**< \brief (LCDC) High-End Overlay Configuration Register 16 */ +#define REG_LCDC_HEOCFG17 (*(RwReg*)0xF00303D0U) /**< \brief (LCDC) High-End Overlay Configuration Register 17 */ +#define REG_LCDC_HEOCFG18 (*(RwReg*)0xF00303D4U) /**< \brief (LCDC) High-End Overlay Configuration Register 18 */ +#define REG_LCDC_HEOCFG19 (*(RwReg*)0xF00303D8U) /**< \brief (LCDC) High-End Overlay Configuration Register 19 */ +#define REG_LCDC_HEOCFG20 (*(RwReg*)0xF00303DCU) /**< \brief (LCDC) High-End Overlay Configuration Register 20 */ +#define REG_LCDC_HEOCFG21 (*(RwReg*)0xF00303E0U) /**< \brief (LCDC) High-End Overlay Configuration Register 21 */ +#define REG_LCDC_HEOCFG22 (*(RwReg*)0xF00303E4U) /**< \brief (LCDC) High-End Overlay Configuration Register 22 */ +#define REG_LCDC_HEOCFG23 (*(RwReg*)0xF00303E8U) /**< \brief (LCDC) High-End Overlay Configuration Register 23 */ +#define REG_LCDC_HEOCFG24 (*(RwReg*)0xF00303ECU) /**< \brief (LCDC) High-End Overlay Configuration Register 24 */ +#define REG_LCDC_HEOCFG25 (*(RwReg*)0xF00303F0U) /**< \brief (LCDC) High-End Overlay Configuration Register 25 */ +#define REG_LCDC_HEOCFG26 (*(RwReg*)0xF00303F4U) /**< \brief (LCDC) High-End Overlay Configuration Register 26 */ +#define REG_LCDC_HEOCFG27 (*(RwReg*)0xF00303F8U) /**< \brief (LCDC) High-End Overlay Configuration Register 27 */ +#define REG_LCDC_HEOCFG28 (*(RwReg*)0xF00303FCU) /**< \brief (LCDC) High-End Overlay Configuration Register 28 */ +#define REG_LCDC_HEOCFG29 (*(RwReg*)0xF0030400U) /**< \brief (LCDC) High-End Overlay Configuration Register 29 */ +#define REG_LCDC_HEOCFG30 (*(RwReg*)0xF0030404U) /**< \brief (LCDC) High-End Overlay Configuration Register 30 */ +#define REG_LCDC_HEOCFG31 (*(RwReg*)0xF0030408U) /**< \brief (LCDC) High-End Overlay Configuration Register 31 */ +#define REG_LCDC_HEOCFG32 (*(RwReg*)0xF003040CU) /**< \brief (LCDC) High-End Overlay Configuration Register 32 */ +#define REG_LCDC_HEOCFG33 (*(RwReg*)0xF0030410U) /**< \brief (LCDC) High-End Overlay Configuration Register 33 */ +#define REG_LCDC_HEOCFG34 (*(RwReg*)0xF0030414U) /**< \brief (LCDC) High-End Overlay Configuration Register 34 */ +#define REG_LCDC_HEOCFG35 (*(RwReg*)0xF0030418U) /**< \brief (LCDC) High-End Overlay Configuration Register 35 */ +#define REG_LCDC_HEOCFG36 (*(RwReg*)0xF003041CU) /**< \brief (LCDC) High-End Overlay Configuration Register 36 */ +#define REG_LCDC_HEOCFG37 (*(RwReg*)0xF0030420U) /**< \brief (LCDC) High-End Overlay Configuration Register 37 */ +#define REG_LCDC_HEOCFG38 (*(RwReg*)0xF0030424U) /**< \brief (LCDC) High-End Overlay Configuration Register 38 */ +#define REG_LCDC_HEOCFG39 (*(RwReg*)0xF0030428U) /**< \brief (LCDC) High-End Overlay Configuration Register 39 */ +#define REG_LCDC_HEOCFG40 (*(RwReg*)0xF003042CU) /**< \brief (LCDC) High-End Overlay Configuration Register 40 */ +#define REG_LCDC_HEOCFG41 (*(RwReg*)0xF0030430U) /**< \brief (LCDC) High-End Overlay Configuration Register 41 */ +#define REG_LCDC_HCRCHER (*(WoReg*)0xF0030440U) /**< \brief (LCDC) Hardware Cursor Channel Enable Register */ +#define REG_LCDC_HCRCHDR (*(WoReg*)0xF0030444U) /**< \brief (LCDC) Hardware Cursor Channel disable Register */ +#define REG_LCDC_HCRCHSR (*(RoReg*)0xF0030448U) /**< \brief (LCDC) Hardware Cursor Channel Status Register */ +#define REG_LCDC_HCRIER (*(WoReg*)0xF003044CU) /**< \brief (LCDC) Hardware Cursor Interrupt Enable Register */ +#define REG_LCDC_HCRIDR (*(WoReg*)0xF0030450U) /**< \brief (LCDC) Hardware Cursor Interrupt Disable Register */ +#define REG_LCDC_HCRIMR (*(RoReg*)0xF0030454U) /**< \brief (LCDC) Hardware Cursor Interrupt Mask Register */ +#define REG_LCDC_HCRISR (*(RoReg*)0xF0030458U) /**< \brief (LCDC) Hardware Cursor Interrupt Status Register */ +#define REG_LCDC_HCRHEAD (*(RwReg*)0xF003045CU) /**< \brief (LCDC) Hardware Cursor DMA Head Register */ +#define REG_LCDC_HCRADDR (*(RwReg*)0xF0030460U) /**< \brief (LCDC) Hardware cursor DMA Address Register */ +#define REG_LCDC_HCRCTRL (*(RwReg*)0xF0030464U) /**< \brief (LCDC) Hardware Cursor DMA Control Register */ +#define REG_LCDC_HCRNEXT (*(RwReg*)0xF0030468U) /**< \brief (LCDC) Hardware Cursor DMA NExt Register */ +#define REG_LCDC_HCRCFG0 (*(RwReg*)0xF003046CU) /**< \brief (LCDC) Hardware Cursor Configuration 0 Register */ +#define REG_LCDC_HCRCFG1 (*(RwReg*)0xF0030470U) /**< \brief (LCDC) Hardware Cursor Configuration 1 Register */ +#define REG_LCDC_HCRCFG2 (*(RwReg*)0xF0030474U) /**< \brief (LCDC) Hardware Cursor Configuration 2 Register */ +#define REG_LCDC_HCRCFG3 (*(RwReg*)0xF0030478U) /**< \brief (LCDC) Hardware Cursor Configuration 3 Register */ +#define REG_LCDC_HCRCFG4 (*(RwReg*)0xF003047CU) /**< \brief (LCDC) Hardware Cursor Configuration 4 Register */ +#define REG_LCDC_HCRCFG6 (*(RwReg*)0xF0030484U) /**< \brief (LCDC) Hardware Cursor Configuration 6 Register */ +#define REG_LCDC_HCRCFG7 (*(RwReg*)0xF0030488U) /**< \brief (LCDC) Hardware Cursor Configuration 7 Register */ +#define REG_LCDC_HCRCFG8 (*(RwReg*)0xF003048CU) /**< \brief (LCDC) Hardware Cursor Configuration 8 Register */ +#define REG_LCDC_HCRCFG9 (*(RwReg*)0xF0030490U) /**< \brief (LCDC) Hardware Cursor Configuration 9 Register */ +#define REG_LCDC_PPCHER (*(WoReg*)0xF0030540U) /**< \brief (LCDC) Post Processing Channel Enable Register */ +#define REG_LCDC_PPCHDR (*(WoReg*)0xF0030544U) /**< \brief (LCDC) Post Processing Channel Disable Register */ +#define REG_LCDC_PPCHSR (*(RoReg*)0xF0030548U) /**< \brief (LCDC) Post Processing Channel Status Register */ +#define REG_LCDC_PPIER (*(WoReg*)0xF003054CU) /**< \brief (LCDC) Post Processing Interrupt Enable Register */ +#define REG_LCDC_PPIDR (*(WoReg*)0xF0030550U) /**< \brief (LCDC) Post Processing Interrupt Disable Register */ +#define REG_LCDC_PPIMR (*(RoReg*)0xF0030554U) /**< \brief (LCDC) Post Processing Interrupt Mask Register */ +#define REG_LCDC_PPISR (*(RoReg*)0xF0030558U) /**< \brief (LCDC) Post Processing Interrupt Status Register */ +#define REG_LCDC_PPHEAD (*(RwReg*)0xF003055CU) /**< \brief (LCDC) Post Processing Head Register */ +#define REG_LCDC_PPADDR (*(RwReg*)0xF0030560U) /**< \brief (LCDC) Post Processing Address Register */ +#define REG_LCDC_PPCTRL (*(RwReg*)0xF0030564U) /**< \brief (LCDC) Post Processing Control Register */ +#define REG_LCDC_PPNEXT (*(RwReg*)0xF0030568U) /**< \brief (LCDC) Post Processing Next Register */ +#define REG_LCDC_PPCFG0 (*(RwReg*)0xF003056CU) /**< \brief (LCDC) Post Processing Configuration Register 0 */ +#define REG_LCDC_PPCFG1 (*(RwReg*)0xF0030570U) /**< \brief (LCDC) Post Processing Configuration Register 1 */ +#define REG_LCDC_PPCFG2 (*(RwReg*)0xF0030574U) /**< \brief (LCDC) Post Processing Configuration Register 2 */ +#define REG_LCDC_PPCFG3 (*(RwReg*)0xF0030578U) /**< \brief (LCDC) Post Processing Configuration Register 3 */ +#define REG_LCDC_PPCFG4 (*(RwReg*)0xF003057CU) /**< \brief (LCDC) Post Processing Configuration Register 4 */ +#define REG_LCDC_PPCFG5 (*(RwReg*)0xF0030580U) /**< \brief (LCDC) Post Processing Configuration Register 5 */ +#define REG_LCDC_BASECLUT (*(RwReg*)0xF0030600U) /**< \brief (LCDC) Base CLUT Register */ +#define REG_LCDC_OVR1CLUT (*(RwReg*)0xF0030A00U) /**< \brief (LCDC) Overlay 1 CLUT Register */ +#define REG_LCDC_OVR2CLUT (*(RwReg*)0xF0030E00U) /**< \brief (LCDC) Overlay 2 CLUT Register */ +#define REG_LCDC_HEOCLUT (*(RwReg*)0xF0031200U) /**< \brief (LCDC) High End Overlay CLUT Register */ +#define REG_LCDC_HCRCLUT (*(RwReg*)0xF0031600U) /**< \brief (LCDC) Hardware Cursor CLUT Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_LCDC_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_matrix.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_matrix.h new file mode 100644 index 0000000..cb7c610 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_matrix.h
@@ -0,0 +1,114 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_MATRIX_INSTANCE_ +#define _SAMA5_MATRIX_INSTANCE_ + +/* ========== Register definition for MATRIX peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_MATRIX_MCFG (0xFFFFEC00U) /**< \brief (MATRIX) Master Configuration Register */ +#define REG_MATRIX_SCFG (0xFFFFEC40U) /**< \brief (MATRIX) Slave Configuration Register */ +#define REG_MATRIX_PRAS0 (0xFFFFEC80U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ +#define REG_MATRIX_PRBS0 (0xFFFFEC84U) /**< \brief (MATRIX) Priority Register B for Slave 0 */ +#define REG_MATRIX_PRAS1 (0xFFFFEC88U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ +#define REG_MATRIX_PRBS1 (0xFFFFEC8CU) /**< \brief (MATRIX) Priority Register B for Slave 1 */ +#define REG_MATRIX_PRAS2 (0xFFFFEC90U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ +#define REG_MATRIX_PRBS2 (0xFFFFEC94U) /**< \brief (MATRIX) Priority Register B for Slave 2 */ +#define REG_MATRIX_PRAS3 (0xFFFFEC98U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ +#define REG_MATRIX_PRBS3 (0xFFFFEC9CU) /**< \brief (MATRIX) Priority Register B for Slave 3 */ +#define REG_MATRIX_PRAS4 (0xFFFFECA0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */ +#define REG_MATRIX_PRBS4 (0xFFFFECA4U) /**< \brief (MATRIX) Priority Register B for Slave 4 */ +#define REG_MATRIX_PRAS5 (0xFFFFECA8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */ +#define REG_MATRIX_PRBS5 (0xFFFFECACU) /**< \brief (MATRIX) Priority Register B for Slave 5 */ +#define REG_MATRIX_PRAS6 (0xFFFFECB0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */ +#define REG_MATRIX_PRBS6 (0xFFFFECB4U) /**< \brief (MATRIX) Priority Register B for Slave 6 */ +#define REG_MATRIX_PRAS7 (0xFFFFECB8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */ +#define REG_MATRIX_PRBS7 (0xFFFFECBCU) /**< \brief (MATRIX) Priority Register B for Slave 7 */ +#define REG_MATRIX_PRAS8 (0xFFFFECC0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */ +#define REG_MATRIX_PRBS8 (0xFFFFECC4U) /**< \brief (MATRIX) Priority Register B for Slave 8 */ +#define REG_MATRIX_PRAS9 (0xFFFFECC8U) /**< \brief (MATRIX) Priority Register A for Slave 9 */ +#define REG_MATRIX_PRBS9 (0xFFFFECCCU) /**< \brief (MATRIX) Priority Register B for Slave 9 */ +#define REG_MATRIX_PRAS10 (0xFFFFECD0U) /**< \brief (MATRIX) Priority Register A for Slave 10 */ +#define REG_MATRIX_PRBS10 (0xFFFFECD4U) /**< \brief (MATRIX) Priority Register B for Slave 10 */ +#define REG_MATRIX_PRAS11 (0xFFFFECD8U) /**< \brief (MATRIX) Priority Register A for Slave 11 */ +#define REG_MATRIX_PRBS11 (0xFFFFECDCU) /**< \brief (MATRIX) Priority Register B for Slave 11 */ +#define REG_MATRIX_PRAS12 (0xFFFFECE0U) /**< \brief (MATRIX) Priority Register A for Slave 12 */ +#define REG_MATRIX_PRBS12 (0xFFFFECE4U) /**< \brief (MATRIX) Priority Register B for Slave 12 */ +#define REG_MATRIX_PRAS13 (0xFFFFECE8U) /**< \brief (MATRIX) Priority Register A for Slave 13 */ +#define REG_MATRIX_PRBS13 (0xFFFFECECU) /**< \brief (MATRIX) Priority Register B for Slave 13 */ +#define REG_MATRIX_PRAS14 (0xFFFFECF0U) /**< \brief (MATRIX) Priority Register A for Slave 14 */ +#define REG_MATRIX_PRBS14 (0xFFFFECF4U) /**< \brief (MATRIX) Priority Register B for Slave 14 */ +#define REG_MATRIX_PRAS15 (0xFFFFECF8U) /**< \brief (MATRIX) Priority Register A for Slave 15 */ +#define REG_MATRIX_PRBS15 (0xFFFFECFCU) /**< \brief (MATRIX) Priority Register B for Slave 15 */ +#define REG_MATRIX_MRCR (0xFFFFED00U) /**< \brief (MATRIX) Master Remap Control Register */ +#define REG_MATRIX_SFR (0xFFFFED10U) /**< \brief (MATRIX) Special Function Register */ +#define REG_MATRIX_WPMR (0xFFFFEDE4U) /**< \brief (MATRIX) Write Protect Mode Register */ +#define REG_MATRIX_WPSR (0xFFFFEDE8U) /**< \brief (MATRIX) Write Protect Status Register */ +#else +#define REG_MATRIX_MCFG (*(RwReg*)0xFFFFEC00U) /**< \brief (MATRIX) Master Configuration Register */ +#define REG_MATRIX_SCFG (*(RwReg*)0xFFFFEC40U) /**< \brief (MATRIX) Slave Configuration Register */ +#define REG_MATRIX_PRAS0 (*(RwReg*)0xFFFFEC80U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ +#define REG_MATRIX_PRBS0 (*(RwReg*)0xFFFFEC84U) /**< \brief (MATRIX) Priority Register B for Slave 0 */ +#define REG_MATRIX_PRAS1 (*(RwReg*)0xFFFFEC88U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ +#define REG_MATRIX_PRBS1 (*(RwReg*)0xFFFFEC8CU) /**< \brief (MATRIX) Priority Register B for Slave 1 */ +#define REG_MATRIX_PRAS2 (*(RwReg*)0xFFFFEC90U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ +#define REG_MATRIX_PRBS2 (*(RwReg*)0xFFFFEC94U) /**< \brief (MATRIX) Priority Register B for Slave 2 */ +#define REG_MATRIX_PRAS3 (*(RwReg*)0xFFFFEC98U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ +#define REG_MATRIX_PRBS3 (*(RwReg*)0xFFFFEC9CU) /**< \brief (MATRIX) Priority Register B for Slave 3 */ +#define REG_MATRIX_PRAS4 (*(RwReg*)0xFFFFECA0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */ +#define REG_MATRIX_PRBS4 (*(RwReg*)0xFFFFECA4U) /**< \brief (MATRIX) Priority Register B for Slave 4 */ +#define REG_MATRIX_PRAS5 (*(RwReg*)0xFFFFECA8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */ +#define REG_MATRIX_PRBS5 (*(RwReg*)0xFFFFECACU) /**< \brief (MATRIX) Priority Register B for Slave 5 */ +#define REG_MATRIX_PRAS6 (*(RwReg*)0xFFFFECB0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */ +#define REG_MATRIX_PRBS6 (*(RwReg*)0xFFFFECB4U) /**< \brief (MATRIX) Priority Register B for Slave 6 */ +#define REG_MATRIX_PRAS7 (*(RwReg*)0xFFFFECB8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */ +#define REG_MATRIX_PRBS7 (*(RwReg*)0xFFFFECBCU) /**< \brief (MATRIX) Priority Register B for Slave 7 */ +#define REG_MATRIX_PRAS8 (*(RwReg*)0xFFFFECC0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */ +#define REG_MATRIX_PRBS8 (*(RwReg*)0xFFFFECC4U) /**< \brief (MATRIX) Priority Register B for Slave 8 */ +#define REG_MATRIX_PRAS9 (*(RwReg*)0xFFFFECC8U) /**< \brief (MATRIX) Priority Register A for Slave 9 */ +#define REG_MATRIX_PRBS9 (*(RwReg*)0xFFFFECCCU) /**< \brief (MATRIX) Priority Register B for Slave 9 */ +#define REG_MATRIX_PRAS10 (*(RwReg*)0xFFFFECD0U) /**< \brief (MATRIX) Priority Register A for Slave 10 */ +#define REG_MATRIX_PRBS10 (*(RwReg*)0xFFFFECD4U) /**< \brief (MATRIX) Priority Register B for Slave 10 */ +#define REG_MATRIX_PRAS11 (*(RwReg*)0xFFFFECD8U) /**< \brief (MATRIX) Priority Register A for Slave 11 */ +#define REG_MATRIX_PRBS11 (*(RwReg*)0xFFFFECDCU) /**< \brief (MATRIX) Priority Register B for Slave 11 */ +#define REG_MATRIX_PRAS12 (*(RwReg*)0xFFFFECE0U) /**< \brief (MATRIX) Priority Register A for Slave 12 */ +#define REG_MATRIX_PRBS12 (*(RwReg*)0xFFFFECE4U) /**< \brief (MATRIX) Priority Register B for Slave 12 */ +#define REG_MATRIX_PRAS13 (*(RwReg*)0xFFFFECE8U) /**< \brief (MATRIX) Priority Register A for Slave 13 */ +#define REG_MATRIX_PRBS13 (*(RwReg*)0xFFFFECECU) /**< \brief (MATRIX) Priority Register B for Slave 13 */ +#define REG_MATRIX_PRAS14 (*(RwReg*)0xFFFFECF0U) /**< \brief (MATRIX) Priority Register A for Slave 14 */ +#define REG_MATRIX_PRBS14 (*(RwReg*)0xFFFFECF4U) /**< \brief (MATRIX) Priority Register B for Slave 14 */ +#define REG_MATRIX_PRAS15 (*(RwReg*)0xFFFFECF8U) /**< \brief (MATRIX) Priority Register A for Slave 15 */ +#define REG_MATRIX_PRBS15 (*(RwReg*)0xFFFFECFCU) /**< \brief (MATRIX) Priority Register B for Slave 15 */ +#define REG_MATRIX_MRCR (*(RwReg*)0xFFFFED00U) /**< \brief (MATRIX) Master Remap Control Register */ +#define REG_MATRIX_SFR (*(RwReg*)0xFFFFED10U) /**< \brief (MATRIX) Special Function Register */ +#define REG_MATRIX_WPMR (*(RwReg*)0xFFFFEDE4U) /**< \brief (MATRIX) Write Protect Mode Register */ +#define REG_MATRIX_WPSR (*(RoReg*)0xFFFFEDE8U) /**< \brief (MATRIX) Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_MATRIX_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_mpddrc.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_mpddrc.h new file mode 100644 index 0000000..e44d993 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_mpddrc.h
@@ -0,0 +1,86 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_MPDDRC_INSTANCE_ +#define _SAMA5_MPDDRC_INSTANCE_ + +/* ========== Register definition for MPDDRC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_MPDDRC_MR (0xFFFFEA00U) /**< \brief (MPDDRC) MPDDRC Mode Register */ +#define REG_MPDDRC_RTR (0xFFFFEA04U) /**< \brief (MPDDRC) MPDDRC Refresh Timer Register */ +#define REG_MPDDRC_CR (0xFFFFEA08U) /**< \brief (MPDDRC) MPDDRC Configuration Register */ +#define REG_MPDDRC_TPR0 (0xFFFFEA0CU) /**< \brief (MPDDRC) MPDDRC Timing Parameter 0 Register */ +#define REG_MPDDRC_TPR1 (0xFFFFEA10U) /**< \brief (MPDDRC) MPDDRC Timing Parameter 1 Register */ +#define REG_MPDDRC_TPR2 (0xFFFFEA14U) /**< \brief (MPDDRC) MPDDRC Timing Parameter 2 Register */ +#define REG_MPDDRC_LPR (0xFFFFEA1CU) /**< \brief (MPDDRC) MPDDRC Low-power Register */ +#define REG_MPDDRC_MD (0xFFFFEA20U) /**< \brief (MPDDRC) MPDDRC Memory Device Register */ +#define REG_MPDDRC_LPDDR2_LPR (0xFFFFEA28U) /**< \brief (MPDDRC) MPDDRC LPDDR2 Low-power Register */ +#define REG_MPDDRC_LPDDR2_CAL_MR4 (0xFFFFEA2CU) /**< \brief (MPDDRC) MPDDRC LPDDR2 Calibration and MR4 Register */ +#define REG_MPDDRC_LPDDR2_TIM_CAL (0xFFFFEA30U) /**< \brief (MPDDRC) MPDDRC LPDDR2 Timing Calibration Register */ +#define REG_MPDDRC_IO_CALIBR (0xFFFFEA34U) /**< \brief (MPDDRC) MPDDRC IO Calibration */ +#define REG_MPDDRC_OCMS (0xFFFFEA38U) /**< \brief (MPDDRC) MPDDRC OCMS Register */ +#define REG_MPDDRC_OCMS_KEY1 (0xFFFFEA3CU) /**< \brief (MPDDRC) MPDDRC OCMS KEY1 Register */ +#define REG_MPDDRC_OCMS_KEY2 (0xFFFFEA40U) /**< \brief (MPDDRC) MPDDRC OCMS KEY2 Register */ +#define REG_MPDDRC_DLL_MOR (0xFFFFEA74U) /**< \brief (MPDDRC) MPDDRC DLL Master Offset Register */ +#define REG_MPDDRC_DLL_SOR (0xFFFFEA78U) /**< \brief (MPDDRC) MPDDRC DLL Slave Offset Register */ +#define REG_MPDDRC_DLL_MSR (0xFFFFEA7CU) /**< \brief (MPDDRC) MPDDRC DLL Master Status Register */ +#define REG_MPDDRC_DLL_S0SR (0xFFFFEA80U) /**< \brief (MPDDRC) MPDDRC DLL Slave 0 Status Register */ +#define REG_MPDDRC_DLL_S1SR (0xFFFFEA84U) /**< \brief (MPDDRC) MPDDRC DLL Slave 1 Status Register */ +#define REG_MPDDRC_DLL_S2SR (0xFFFFEA88U) /**< \brief (MPDDRC) MPDDRC DLL Slave 2 Status Register */ +#define REG_MPDDRC_DLL_S3SR (0xFFFFEA8CU) /**< \brief (MPDDRC) MPDDRC DLL Slave 3 Status Register */ +#define REG_MPDDRC_WPCR (0xFFFFEAE4U) /**< \brief (MPDDRC) MPDDRC Write Protect Control Register */ +#define REG_MPDDRC_WPSR (0xFFFFEAE8U) /**< \brief (MPDDRC) MPDDRC Write Protect Status Register */ +#else +#define REG_MPDDRC_MR (*(RwReg*)0xFFFFEA00U) /**< \brief (MPDDRC) MPDDRC Mode Register */ +#define REG_MPDDRC_RTR (*(RwReg*)0xFFFFEA04U) /**< \brief (MPDDRC) MPDDRC Refresh Timer Register */ +#define REG_MPDDRC_CR (*(RwReg*)0xFFFFEA08U) /**< \brief (MPDDRC) MPDDRC Configuration Register */ +#define REG_MPDDRC_TPR0 (*(RwReg*)0xFFFFEA0CU) /**< \brief (MPDDRC) MPDDRC Timing Parameter 0 Register */ +#define REG_MPDDRC_TPR1 (*(RwReg*)0xFFFFEA10U) /**< \brief (MPDDRC) MPDDRC Timing Parameter 1 Register */ +#define REG_MPDDRC_TPR2 (*(RwReg*)0xFFFFEA14U) /**< \brief (MPDDRC) MPDDRC Timing Parameter 2 Register */ +#define REG_MPDDRC_LPR (*(RwReg*)0xFFFFEA1CU) /**< \brief (MPDDRC) MPDDRC Low-power Register */ +#define REG_MPDDRC_MD (*(RwReg*)0xFFFFEA20U) /**< \brief (MPDDRC) MPDDRC Memory Device Register */ +#define REG_MPDDRC_LPDDR2_LPR (*(RwReg*)0xFFFFEA28U) /**< \brief (MPDDRC) MPDDRC LPDDR2 Low-power Register */ +#define REG_MPDDRC_LPDDR2_CAL_MR4 (*(RwReg*)0xFFFFEA2CU) /**< \brief (MPDDRC) MPDDRC LPDDR2 Calibration and MR4 Register */ +#define REG_MPDDRC_LPDDR2_TIM_CAL (*(RwReg*)0xFFFFEA30U) /**< \brief (MPDDRC) MPDDRC LPDDR2 Timing Calibration Register */ +#define REG_MPDDRC_IO_CALIBR (*(RwReg*)0xFFFFEA34U) /**< \brief (MPDDRC) MPDDRC IO Calibration */ +#define REG_MPDDRC_OCMS (*(RwReg*)0xFFFFEA38U) /**< \brief (MPDDRC) MPDDRC OCMS Register */ +#define REG_MPDDRC_OCMS_KEY1 (*(WoReg*)0xFFFFEA3CU) /**< \brief (MPDDRC) MPDDRC OCMS KEY1 Register */ +#define REG_MPDDRC_OCMS_KEY2 (*(WoReg*)0xFFFFEA40U) /**< \brief (MPDDRC) MPDDRC OCMS KEY2 Register */ +#define REG_MPDDRC_DLL_MOR (*(RwReg*)0xFFFFEA74U) /**< \brief (MPDDRC) MPDDRC DLL Master Offset Register */ +#define REG_MPDDRC_DLL_SOR (*(RwReg*)0xFFFFEA78U) /**< \brief (MPDDRC) MPDDRC DLL Slave Offset Register */ +#define REG_MPDDRC_DLL_MSR (*(RoReg*)0xFFFFEA7CU) /**< \brief (MPDDRC) MPDDRC DLL Master Status Register */ +#define REG_MPDDRC_DLL_S0SR (*(RoReg*)0xFFFFEA80U) /**< \brief (MPDDRC) MPDDRC DLL Slave 0 Status Register */ +#define REG_MPDDRC_DLL_S1SR (*(RoReg*)0xFFFFEA84U) /**< \brief (MPDDRC) MPDDRC DLL Slave 1 Status Register */ +#define REG_MPDDRC_DLL_S2SR (*(RoReg*)0xFFFFEA88U) /**< \brief (MPDDRC) MPDDRC DLL Slave 2 Status Register */ +#define REG_MPDDRC_DLL_S3SR (*(RoReg*)0xFFFFEA8CU) /**< \brief (MPDDRC) MPDDRC DLL Slave 3 Status Register */ +#define REG_MPDDRC_WPCR (*(RwReg*)0xFFFFEAE4U) /**< \brief (MPDDRC) MPDDRC Write Protect Control Register */ +#define REG_MPDDRC_WPSR (*(RoReg*)0xFFFFEAE8U) /**< \brief (MPDDRC) MPDDRC Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_MPDDRC_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_pioa.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_pioa.h new file mode 100644 index 0000000..21f3a91 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_pioa.h
@@ -0,0 +1,136 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_PIOA_INSTANCE_ +#define _SAMA5_PIOA_INSTANCE_ + +/* ========== Register definition for PIOA peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PIOA_PER (0xFFFFF200U) /**< \brief (PIOA) PIO Enable Register */ +#define REG_PIOA_PDR (0xFFFFF204U) /**< \brief (PIOA) PIO Disable Register */ +#define REG_PIOA_PSR (0xFFFFF208U) /**< \brief (PIOA) PIO Status Register */ +#define REG_PIOA_OER (0xFFFFF210U) /**< \brief (PIOA) Output Enable Register */ +#define REG_PIOA_ODR (0xFFFFF214U) /**< \brief (PIOA) Output Disable Register */ +#define REG_PIOA_OSR (0xFFFFF218U) /**< \brief (PIOA) Output Status Register */ +#define REG_PIOA_IFER (0xFFFFF220U) /**< \brief (PIOA) Glitch Input Filter Enable Register */ +#define REG_PIOA_IFDR (0xFFFFF224U) /**< \brief (PIOA) Glitch Input Filter Disable Register */ +#define REG_PIOA_IFSR (0xFFFFF228U) /**< \brief (PIOA) Glitch Input Filter Status Register */ +#define REG_PIOA_SODR (0xFFFFF230U) /**< \brief (PIOA) Set Output Data Register */ +#define REG_PIOA_CODR (0xFFFFF234U) /**< \brief (PIOA) Clear Output Data Register */ +#define REG_PIOA_ODSR (0xFFFFF238U) /**< \brief (PIOA) Output Data Status Register */ +#define REG_PIOA_PDSR (0xFFFFF23CU) /**< \brief (PIOA) Pin Data Status Register */ +#define REG_PIOA_IER (0xFFFFF240U) /**< \brief (PIOA) Interrupt Enable Register */ +#define REG_PIOA_IDR (0xFFFFF244U) /**< \brief (PIOA) Interrupt Disable Register */ +#define REG_PIOA_IMR (0xFFFFF248U) /**< \brief (PIOA) Interrupt Mask Register */ +#define REG_PIOA_ISR (0xFFFFF24CU) /**< \brief (PIOA) Interrupt Status Register */ +#define REG_PIOA_MDER (0xFFFFF250U) /**< \brief (PIOA) Multi-driver Enable Register */ +#define REG_PIOA_MDDR (0xFFFFF254U) /**< \brief (PIOA) Multi-driver Disable Register */ +#define REG_PIOA_MDSR (0xFFFFF258U) /**< \brief (PIOA) Multi-driver Status Register */ +#define REG_PIOA_PUDR (0xFFFFF260U) /**< \brief (PIOA) Pull-up Disable Register */ +#define REG_PIOA_PUER (0xFFFFF264U) /**< \brief (PIOA) Pull-up Enable Register */ +#define REG_PIOA_PUSR (0xFFFFF268U) /**< \brief (PIOA) Pad Pull-up Status Register */ +#define REG_PIOA_ABCDSR (0xFFFFF270U) /**< \brief (PIOA) Peripheral Select Register */ +#define REG_PIOA_IFSCDR (0xFFFFF280U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */ +#define REG_PIOA_IFSCER (0xFFFFF284U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */ +#define REG_PIOA_IFSCSR (0xFFFFF288U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */ +#define REG_PIOA_SCDR (0xFFFFF28CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */ +#define REG_PIOA_PPDDR (0xFFFFF290U) /**< \brief (PIOA) Pad Pull-down Disable Register */ +#define REG_PIOA_PPDER (0xFFFFF294U) /**< \brief (PIOA) Pad Pull-down Enable Register */ +#define REG_PIOA_PPDSR (0xFFFFF298U) /**< \brief (PIOA) Pad Pull-down Status Register */ +#define REG_PIOA_OWER (0xFFFFF2A0U) /**< \brief (PIOA) Output Write Enable */ +#define REG_PIOA_OWDR (0xFFFFF2A4U) /**< \brief (PIOA) Output Write Disable */ +#define REG_PIOA_OWSR (0xFFFFF2A8U) /**< \brief (PIOA) Output Write Status Register */ +#define REG_PIOA_AIMER (0xFFFFF2B0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */ +#define REG_PIOA_AIMDR (0xFFFFF2B4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */ +#define REG_PIOA_AIMMR (0xFFFFF2B8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */ +#define REG_PIOA_ESR (0xFFFFF2C0U) /**< \brief (PIOA) Edge Select Register */ +#define REG_PIOA_LSR (0xFFFFF2C4U) /**< \brief (PIOA) Level Select Register */ +#define REG_PIOA_ELSR (0xFFFFF2C8U) /**< \brief (PIOA) Edge/Level Status Register */ +#define REG_PIOA_FELLSR (0xFFFFF2D0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */ +#define REG_PIOA_REHLSR (0xFFFFF2D4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */ +#define REG_PIOA_FRLHSR (0xFFFFF2D8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */ +#define REG_PIOA_LOCKSR (0xFFFFF2E0U) /**< \brief (PIOA) Lock Status */ +#define REG_PIOA_WPMR (0xFFFFF2E4U) /**< \brief (PIOA) Write Protect Mode Register */ +#define REG_PIOA_WPSR (0xFFFFF2E8U) /**< \brief (PIOA) Write Protect Status Register */ +#define REG_PIOA_SCHMITT (0xFFFFF300U) /**< \brief (PIOA) Schmitt Trigger Register */ +#define REG_PIOA_DRIVER1 (0xFFFFF318U) /**< \brief (PIOA) I/O Drive Register 1 */ +#define REG_PIOA_DRIVER2 (0xFFFFF31CU) /**< \brief (PIOA) I/O Drive Register 2 */ +#else +#define REG_PIOA_PER (*(WoReg*)0xFFFFF200U) /**< \brief (PIOA) PIO Enable Register */ +#define REG_PIOA_PDR (*(WoReg*)0xFFFFF204U) /**< \brief (PIOA) PIO Disable Register */ +#define REG_PIOA_PSR (*(RoReg*)0xFFFFF208U) /**< \brief (PIOA) PIO Status Register */ +#define REG_PIOA_OER (*(WoReg*)0xFFFFF210U) /**< \brief (PIOA) Output Enable Register */ +#define REG_PIOA_ODR (*(WoReg*)0xFFFFF214U) /**< \brief (PIOA) Output Disable Register */ +#define REG_PIOA_OSR (*(RoReg*)0xFFFFF218U) /**< \brief (PIOA) Output Status Register */ +#define REG_PIOA_IFER (*(WoReg*)0xFFFFF220U) /**< \brief (PIOA) Glitch Input Filter Enable Register */ +#define REG_PIOA_IFDR (*(WoReg*)0xFFFFF224U) /**< \brief (PIOA) Glitch Input Filter Disable Register */ +#define REG_PIOA_IFSR (*(RoReg*)0xFFFFF228U) /**< \brief (PIOA) Glitch Input Filter Status Register */ +#define REG_PIOA_SODR (*(WoReg*)0xFFFFF230U) /**< \brief (PIOA) Set Output Data Register */ +#define REG_PIOA_CODR (*(WoReg*)0xFFFFF234U) /**< \brief (PIOA) Clear Output Data Register */ +#define REG_PIOA_ODSR (*(RwReg*)0xFFFFF238U) /**< \brief (PIOA) Output Data Status Register */ +#define REG_PIOA_PDSR (*(RoReg*)0xFFFFF23CU) /**< \brief (PIOA) Pin Data Status Register */ +#define REG_PIOA_IER (*(WoReg*)0xFFFFF240U) /**< \brief (PIOA) Interrupt Enable Register */ +#define REG_PIOA_IDR (*(WoReg*)0xFFFFF244U) /**< \brief (PIOA) Interrupt Disable Register */ +#define REG_PIOA_IMR (*(RoReg*)0xFFFFF248U) /**< \brief (PIOA) Interrupt Mask Register */ +#define REG_PIOA_ISR (*(RoReg*)0xFFFFF24CU) /**< \brief (PIOA) Interrupt Status Register */ +#define REG_PIOA_MDER (*(WoReg*)0xFFFFF250U) /**< \brief (PIOA) Multi-driver Enable Register */ +#define REG_PIOA_MDDR (*(WoReg*)0xFFFFF254U) /**< \brief (PIOA) Multi-driver Disable Register */ +#define REG_PIOA_MDSR (*(RoReg*)0xFFFFF258U) /**< \brief (PIOA) Multi-driver Status Register */ +#define REG_PIOA_PUDR (*(WoReg*)0xFFFFF260U) /**< \brief (PIOA) Pull-up Disable Register */ +#define REG_PIOA_PUER (*(WoReg*)0xFFFFF264U) /**< \brief (PIOA) Pull-up Enable Register */ +#define REG_PIOA_PUSR (*(RoReg*)0xFFFFF268U) /**< \brief (PIOA) Pad Pull-up Status Register */ +#define REG_PIOA_ABCDSR (*(RwReg*)0xFFFFF270U) /**< \brief (PIOA) Peripheral Select Register */ +#define REG_PIOA_IFSCDR (*(WoReg*)0xFFFFF280U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */ +#define REG_PIOA_IFSCER (*(WoReg*)0xFFFFF284U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */ +#define REG_PIOA_IFSCSR (*(RoReg*)0xFFFFF288U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */ +#define REG_PIOA_SCDR (*(RwReg*)0xFFFFF28CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */ +#define REG_PIOA_PPDDR (*(WoReg*)0xFFFFF290U) /**< \brief (PIOA) Pad Pull-down Disable Register */ +#define REG_PIOA_PPDER (*(WoReg*)0xFFFFF294U) /**< \brief (PIOA) Pad Pull-down Enable Register */ +#define REG_PIOA_PPDSR (*(RoReg*)0xFFFFF298U) /**< \brief (PIOA) Pad Pull-down Status Register */ +#define REG_PIOA_OWER (*(WoReg*)0xFFFFF2A0U) /**< \brief (PIOA) Output Write Enable */ +#define REG_PIOA_OWDR (*(WoReg*)0xFFFFF2A4U) /**< \brief (PIOA) Output Write Disable */ +#define REG_PIOA_OWSR (*(RoReg*)0xFFFFF2A8U) /**< \brief (PIOA) Output Write Status Register */ +#define REG_PIOA_AIMER (*(WoReg*)0xFFFFF2B0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */ +#define REG_PIOA_AIMDR (*(WoReg*)0xFFFFF2B4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */ +#define REG_PIOA_AIMMR (*(RoReg*)0xFFFFF2B8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */ +#define REG_PIOA_ESR (*(WoReg*)0xFFFFF2C0U) /**< \brief (PIOA) Edge Select Register */ +#define REG_PIOA_LSR (*(WoReg*)0xFFFFF2C4U) /**< \brief (PIOA) Level Select Register */ +#define REG_PIOA_ELSR (*(RoReg*)0xFFFFF2C8U) /**< \brief (PIOA) Edge/Level Status Register */ +#define REG_PIOA_FELLSR (*(WoReg*)0xFFFFF2D0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */ +#define REG_PIOA_REHLSR (*(WoReg*)0xFFFFF2D4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */ +#define REG_PIOA_FRLHSR (*(RoReg*)0xFFFFF2D8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */ +#define REG_PIOA_LOCKSR (*(RoReg*)0xFFFFF2E0U) /**< \brief (PIOA) Lock Status */ +#define REG_PIOA_WPMR (*(RwReg*)0xFFFFF2E4U) /**< \brief (PIOA) Write Protect Mode Register */ +#define REG_PIOA_WPSR (*(RoReg*)0xFFFFF2E8U) /**< \brief (PIOA) Write Protect Status Register */ +#define REG_PIOA_SCHMITT (*(RwReg*)0xFFFFF300U) /**< \brief (PIOA) Schmitt Trigger Register */ +#define REG_PIOA_DRIVER1 (*(RwReg*)0xFFFFF318U) /**< \brief (PIOA) I/O Drive Register 1 */ +#define REG_PIOA_DRIVER2 (*(RwReg*)0xFFFFF31CU) /**< \brief (PIOA) I/O Drive Register 2 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_PIOA_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_piob.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_piob.h new file mode 100644 index 0000000..8c8a7f2 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_piob.h
@@ -0,0 +1,136 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_PIOB_INSTANCE_ +#define _SAMA5_PIOB_INSTANCE_ + +/* ========== Register definition for PIOB peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PIOB_PER (0xFFFFF400U) /**< \brief (PIOB) PIO Enable Register */ +#define REG_PIOB_PDR (0xFFFFF404U) /**< \brief (PIOB) PIO Disable Register */ +#define REG_PIOB_PSR (0xFFFFF408U) /**< \brief (PIOB) PIO Status Register */ +#define REG_PIOB_OER (0xFFFFF410U) /**< \brief (PIOB) Output Enable Register */ +#define REG_PIOB_ODR (0xFFFFF414U) /**< \brief (PIOB) Output Disable Register */ +#define REG_PIOB_OSR (0xFFFFF418U) /**< \brief (PIOB) Output Status Register */ +#define REG_PIOB_IFER (0xFFFFF420U) /**< \brief (PIOB) Glitch Input Filter Enable Register */ +#define REG_PIOB_IFDR (0xFFFFF424U) /**< \brief (PIOB) Glitch Input Filter Disable Register */ +#define REG_PIOB_IFSR (0xFFFFF428U) /**< \brief (PIOB) Glitch Input Filter Status Register */ +#define REG_PIOB_SODR (0xFFFFF430U) /**< \brief (PIOB) Set Output Data Register */ +#define REG_PIOB_CODR (0xFFFFF434U) /**< \brief (PIOB) Clear Output Data Register */ +#define REG_PIOB_ODSR (0xFFFFF438U) /**< \brief (PIOB) Output Data Status Register */ +#define REG_PIOB_PDSR (0xFFFFF43CU) /**< \brief (PIOB) Pin Data Status Register */ +#define REG_PIOB_IER (0xFFFFF440U) /**< \brief (PIOB) Interrupt Enable Register */ +#define REG_PIOB_IDR (0xFFFFF444U) /**< \brief (PIOB) Interrupt Disable Register */ +#define REG_PIOB_IMR (0xFFFFF448U) /**< \brief (PIOB) Interrupt Mask Register */ +#define REG_PIOB_ISR (0xFFFFF44CU) /**< \brief (PIOB) Interrupt Status Register */ +#define REG_PIOB_MDER (0xFFFFF450U) /**< \brief (PIOB) Multi-driver Enable Register */ +#define REG_PIOB_MDDR (0xFFFFF454U) /**< \brief (PIOB) Multi-driver Disable Register */ +#define REG_PIOB_MDSR (0xFFFFF458U) /**< \brief (PIOB) Multi-driver Status Register */ +#define REG_PIOB_PUDR (0xFFFFF460U) /**< \brief (PIOB) Pull-up Disable Register */ +#define REG_PIOB_PUER (0xFFFFF464U) /**< \brief (PIOB) Pull-up Enable Register */ +#define REG_PIOB_PUSR (0xFFFFF468U) /**< \brief (PIOB) Pad Pull-up Status Register */ +#define REG_PIOB_ABCDSR (0xFFFFF470U) /**< \brief (PIOB) Peripheral Select Register */ +#define REG_PIOB_IFSCDR (0xFFFFF480U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */ +#define REG_PIOB_IFSCER (0xFFFFF484U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */ +#define REG_PIOB_IFSCSR (0xFFFFF488U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */ +#define REG_PIOB_SCDR (0xFFFFF48CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */ +#define REG_PIOB_PPDDR (0xFFFFF490U) /**< \brief (PIOB) Pad Pull-down Disable Register */ +#define REG_PIOB_PPDER (0xFFFFF494U) /**< \brief (PIOB) Pad Pull-down Enable Register */ +#define REG_PIOB_PPDSR (0xFFFFF498U) /**< \brief (PIOB) Pad Pull-down Status Register */ +#define REG_PIOB_OWER (0xFFFFF4A0U) /**< \brief (PIOB) Output Write Enable */ +#define REG_PIOB_OWDR (0xFFFFF4A4U) /**< \brief (PIOB) Output Write Disable */ +#define REG_PIOB_OWSR (0xFFFFF4A8U) /**< \brief (PIOB) Output Write Status Register */ +#define REG_PIOB_AIMER (0xFFFFF4B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */ +#define REG_PIOB_AIMDR (0xFFFFF4B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */ +#define REG_PIOB_AIMMR (0xFFFFF4B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */ +#define REG_PIOB_ESR (0xFFFFF4C0U) /**< \brief (PIOB) Edge Select Register */ +#define REG_PIOB_LSR (0xFFFFF4C4U) /**< \brief (PIOB) Level Select Register */ +#define REG_PIOB_ELSR (0xFFFFF4C8U) /**< \brief (PIOB) Edge/Level Status Register */ +#define REG_PIOB_FELLSR (0xFFFFF4D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */ +#define REG_PIOB_REHLSR (0xFFFFF4D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */ +#define REG_PIOB_FRLHSR (0xFFFFF4D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */ +#define REG_PIOB_LOCKSR (0xFFFFF4E0U) /**< \brief (PIOB) Lock Status */ +#define REG_PIOB_WPMR (0xFFFFF4E4U) /**< \brief (PIOB) Write Protect Mode Register */ +#define REG_PIOB_WPSR (0xFFFFF4E8U) /**< \brief (PIOB) Write Protect Status Register */ +#define REG_PIOB_SCHMITT (0xFFFFF500U) /**< \brief (PIOB) Schmitt Trigger Register */ +#define REG_PIOB_DRIVER1 (0xFFFFF518U) /**< \brief (PIOB) I/O Drive Register 1 */ +#define REG_PIOB_DRIVER2 (0xFFFFF51CU) /**< \brief (PIOB) I/O Drive Register 2 */ +#else +#define REG_PIOB_PER (*(WoReg*)0xFFFFF400U) /**< \brief (PIOB) PIO Enable Register */ +#define REG_PIOB_PDR (*(WoReg*)0xFFFFF404U) /**< \brief (PIOB) PIO Disable Register */ +#define REG_PIOB_PSR (*(RoReg*)0xFFFFF408U) /**< \brief (PIOB) PIO Status Register */ +#define REG_PIOB_OER (*(WoReg*)0xFFFFF410U) /**< \brief (PIOB) Output Enable Register */ +#define REG_PIOB_ODR (*(WoReg*)0xFFFFF414U) /**< \brief (PIOB) Output Disable Register */ +#define REG_PIOB_OSR (*(RoReg*)0xFFFFF418U) /**< \brief (PIOB) Output Status Register */ +#define REG_PIOB_IFER (*(WoReg*)0xFFFFF420U) /**< \brief (PIOB) Glitch Input Filter Enable Register */ +#define REG_PIOB_IFDR (*(WoReg*)0xFFFFF424U) /**< \brief (PIOB) Glitch Input Filter Disable Register */ +#define REG_PIOB_IFSR (*(RoReg*)0xFFFFF428U) /**< \brief (PIOB) Glitch Input Filter Status Register */ +#define REG_PIOB_SODR (*(WoReg*)0xFFFFF430U) /**< \brief (PIOB) Set Output Data Register */ +#define REG_PIOB_CODR (*(WoReg*)0xFFFFF434U) /**< \brief (PIOB) Clear Output Data Register */ +#define REG_PIOB_ODSR (*(RwReg*)0xFFFFF438U) /**< \brief (PIOB) Output Data Status Register */ +#define REG_PIOB_PDSR (*(RoReg*)0xFFFFF43CU) /**< \brief (PIOB) Pin Data Status Register */ +#define REG_PIOB_IER (*(WoReg*)0xFFFFF440U) /**< \brief (PIOB) Interrupt Enable Register */ +#define REG_PIOB_IDR (*(WoReg*)0xFFFFF444U) /**< \brief (PIOB) Interrupt Disable Register */ +#define REG_PIOB_IMR (*(RoReg*)0xFFFFF448U) /**< \brief (PIOB) Interrupt Mask Register */ +#define REG_PIOB_ISR (*(RoReg*)0xFFFFF44CU) /**< \brief (PIOB) Interrupt Status Register */ +#define REG_PIOB_MDER (*(WoReg*)0xFFFFF450U) /**< \brief (PIOB) Multi-driver Enable Register */ +#define REG_PIOB_MDDR (*(WoReg*)0xFFFFF454U) /**< \brief (PIOB) Multi-driver Disable Register */ +#define REG_PIOB_MDSR (*(RoReg*)0xFFFFF458U) /**< \brief (PIOB) Multi-driver Status Register */ +#define REG_PIOB_PUDR (*(WoReg*)0xFFFFF460U) /**< \brief (PIOB) Pull-up Disable Register */ +#define REG_PIOB_PUER (*(WoReg*)0xFFFFF464U) /**< \brief (PIOB) Pull-up Enable Register */ +#define REG_PIOB_PUSR (*(RoReg*)0xFFFFF468U) /**< \brief (PIOB) Pad Pull-up Status Register */ +#define REG_PIOB_ABCDSR (*(RwReg*)0xFFFFF470U) /**< \brief (PIOB) Peripheral Select Register */ +#define REG_PIOB_IFSCDR (*(WoReg*)0xFFFFF480U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */ +#define REG_PIOB_IFSCER (*(WoReg*)0xFFFFF484U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */ +#define REG_PIOB_IFSCSR (*(RoReg*)0xFFFFF488U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */ +#define REG_PIOB_SCDR (*(RwReg*)0xFFFFF48CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */ +#define REG_PIOB_PPDDR (*(WoReg*)0xFFFFF490U) /**< \brief (PIOB) Pad Pull-down Disable Register */ +#define REG_PIOB_PPDER (*(WoReg*)0xFFFFF494U) /**< \brief (PIOB) Pad Pull-down Enable Register */ +#define REG_PIOB_PPDSR (*(RoReg*)0xFFFFF498U) /**< \brief (PIOB) Pad Pull-down Status Register */ +#define REG_PIOB_OWER (*(WoReg*)0xFFFFF4A0U) /**< \brief (PIOB) Output Write Enable */ +#define REG_PIOB_OWDR (*(WoReg*)0xFFFFF4A4U) /**< \brief (PIOB) Output Write Disable */ +#define REG_PIOB_OWSR (*(RoReg*)0xFFFFF4A8U) /**< \brief (PIOB) Output Write Status Register */ +#define REG_PIOB_AIMER (*(WoReg*)0xFFFFF4B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */ +#define REG_PIOB_AIMDR (*(WoReg*)0xFFFFF4B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */ +#define REG_PIOB_AIMMR (*(RoReg*)0xFFFFF4B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */ +#define REG_PIOB_ESR (*(WoReg*)0xFFFFF4C0U) /**< \brief (PIOB) Edge Select Register */ +#define REG_PIOB_LSR (*(WoReg*)0xFFFFF4C4U) /**< \brief (PIOB) Level Select Register */ +#define REG_PIOB_ELSR (*(RoReg*)0xFFFFF4C8U) /**< \brief (PIOB) Edge/Level Status Register */ +#define REG_PIOB_FELLSR (*(WoReg*)0xFFFFF4D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */ +#define REG_PIOB_REHLSR (*(WoReg*)0xFFFFF4D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */ +#define REG_PIOB_FRLHSR (*(RoReg*)0xFFFFF4D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */ +#define REG_PIOB_LOCKSR (*(RoReg*)0xFFFFF4E0U) /**< \brief (PIOB) Lock Status */ +#define REG_PIOB_WPMR (*(RwReg*)0xFFFFF4E4U) /**< \brief (PIOB) Write Protect Mode Register */ +#define REG_PIOB_WPSR (*(RoReg*)0xFFFFF4E8U) /**< \brief (PIOB) Write Protect Status Register */ +#define REG_PIOB_SCHMITT (*(RwReg*)0xFFFFF500U) /**< \brief (PIOB) Schmitt Trigger Register */ +#define REG_PIOB_DRIVER1 (*(RwReg*)0xFFFFF518U) /**< \brief (PIOB) I/O Drive Register 1 */ +#define REG_PIOB_DRIVER2 (*(RwReg*)0xFFFFF51CU) /**< \brief (PIOB) I/O Drive Register 2 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_PIOB_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_pioc.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_pioc.h new file mode 100644 index 0000000..98968f0 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_pioc.h
@@ -0,0 +1,136 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_PIOC_INSTANCE_ +#define _SAMA5_PIOC_INSTANCE_ + +/* ========== Register definition for PIOC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PIOC_PER (0xFFFFF600U) /**< \brief (PIOC) PIO Enable Register */ +#define REG_PIOC_PDR (0xFFFFF604U) /**< \brief (PIOC) PIO Disable Register */ +#define REG_PIOC_PSR (0xFFFFF608U) /**< \brief (PIOC) PIO Status Register */ +#define REG_PIOC_OER (0xFFFFF610U) /**< \brief (PIOC) Output Enable Register */ +#define REG_PIOC_ODR (0xFFFFF614U) /**< \brief (PIOC) Output Disable Register */ +#define REG_PIOC_OSR (0xFFFFF618U) /**< \brief (PIOC) Output Status Register */ +#define REG_PIOC_IFER (0xFFFFF620U) /**< \brief (PIOC) Glitch Input Filter Enable Register */ +#define REG_PIOC_IFDR (0xFFFFF624U) /**< \brief (PIOC) Glitch Input Filter Disable Register */ +#define REG_PIOC_IFSR (0xFFFFF628U) /**< \brief (PIOC) Glitch Input Filter Status Register */ +#define REG_PIOC_SODR (0xFFFFF630U) /**< \brief (PIOC) Set Output Data Register */ +#define REG_PIOC_CODR (0xFFFFF634U) /**< \brief (PIOC) Clear Output Data Register */ +#define REG_PIOC_ODSR (0xFFFFF638U) /**< \brief (PIOC) Output Data Status Register */ +#define REG_PIOC_PDSR (0xFFFFF63CU) /**< \brief (PIOC) Pin Data Status Register */ +#define REG_PIOC_IER (0xFFFFF640U) /**< \brief (PIOC) Interrupt Enable Register */ +#define REG_PIOC_IDR (0xFFFFF644U) /**< \brief (PIOC) Interrupt Disable Register */ +#define REG_PIOC_IMR (0xFFFFF648U) /**< \brief (PIOC) Interrupt Mask Register */ +#define REG_PIOC_ISR (0xFFFFF64CU) /**< \brief (PIOC) Interrupt Status Register */ +#define REG_PIOC_MDER (0xFFFFF650U) /**< \brief (PIOC) Multi-driver Enable Register */ +#define REG_PIOC_MDDR (0xFFFFF654U) /**< \brief (PIOC) Multi-driver Disable Register */ +#define REG_PIOC_MDSR (0xFFFFF658U) /**< \brief (PIOC) Multi-driver Status Register */ +#define REG_PIOC_PUDR (0xFFFFF660U) /**< \brief (PIOC) Pull-up Disable Register */ +#define REG_PIOC_PUER (0xFFFFF664U) /**< \brief (PIOC) Pull-up Enable Register */ +#define REG_PIOC_PUSR (0xFFFFF668U) /**< \brief (PIOC) Pad Pull-up Status Register */ +#define REG_PIOC_ABCDSR (0xFFFFF670U) /**< \brief (PIOC) Peripheral Select Register */ +#define REG_PIOC_IFSCDR (0xFFFFF680U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */ +#define REG_PIOC_IFSCER (0xFFFFF684U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */ +#define REG_PIOC_IFSCSR (0xFFFFF688U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */ +#define REG_PIOC_SCDR (0xFFFFF68CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */ +#define REG_PIOC_PPDDR (0xFFFFF690U) /**< \brief (PIOC) Pad Pull-down Disable Register */ +#define REG_PIOC_PPDER (0xFFFFF694U) /**< \brief (PIOC) Pad Pull-down Enable Register */ +#define REG_PIOC_PPDSR (0xFFFFF698U) /**< \brief (PIOC) Pad Pull-down Status Register */ +#define REG_PIOC_OWER (0xFFFFF6A0U) /**< \brief (PIOC) Output Write Enable */ +#define REG_PIOC_OWDR (0xFFFFF6A4U) /**< \brief (PIOC) Output Write Disable */ +#define REG_PIOC_OWSR (0xFFFFF6A8U) /**< \brief (PIOC) Output Write Status Register */ +#define REG_PIOC_AIMER (0xFFFFF6B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */ +#define REG_PIOC_AIMDR (0xFFFFF6B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */ +#define REG_PIOC_AIMMR (0xFFFFF6B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */ +#define REG_PIOC_ESR (0xFFFFF6C0U) /**< \brief (PIOC) Edge Select Register */ +#define REG_PIOC_LSR (0xFFFFF6C4U) /**< \brief (PIOC) Level Select Register */ +#define REG_PIOC_ELSR (0xFFFFF6C8U) /**< \brief (PIOC) Edge/Level Status Register */ +#define REG_PIOC_FELLSR (0xFFFFF6D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */ +#define REG_PIOC_REHLSR (0xFFFFF6D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */ +#define REG_PIOC_FRLHSR (0xFFFFF6D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */ +#define REG_PIOC_LOCKSR (0xFFFFF6E0U) /**< \brief (PIOC) Lock Status */ +#define REG_PIOC_WPMR (0xFFFFF6E4U) /**< \brief (PIOC) Write Protect Mode Register */ +#define REG_PIOC_WPSR (0xFFFFF6E8U) /**< \brief (PIOC) Write Protect Status Register */ +#define REG_PIOC_SCHMITT (0xFFFFF700U) /**< \brief (PIOC) Schmitt Trigger Register */ +#define REG_PIOC_DRIVER1 (0xFFFFF718U) /**< \brief (PIOC) I/O Drive Register 1 */ +#define REG_PIOC_DRIVER2 (0xFFFFF71CU) /**< \brief (PIOC) I/O Drive Register 2 */ +#else +#define REG_PIOC_PER (*(WoReg*)0xFFFFF600U) /**< \brief (PIOC) PIO Enable Register */ +#define REG_PIOC_PDR (*(WoReg*)0xFFFFF604U) /**< \brief (PIOC) PIO Disable Register */ +#define REG_PIOC_PSR (*(RoReg*)0xFFFFF608U) /**< \brief (PIOC) PIO Status Register */ +#define REG_PIOC_OER (*(WoReg*)0xFFFFF610U) /**< \brief (PIOC) Output Enable Register */ +#define REG_PIOC_ODR (*(WoReg*)0xFFFFF614U) /**< \brief (PIOC) Output Disable Register */ +#define REG_PIOC_OSR (*(RoReg*)0xFFFFF618U) /**< \brief (PIOC) Output Status Register */ +#define REG_PIOC_IFER (*(WoReg*)0xFFFFF620U) /**< \brief (PIOC) Glitch Input Filter Enable Register */ +#define REG_PIOC_IFDR (*(WoReg*)0xFFFFF624U) /**< \brief (PIOC) Glitch Input Filter Disable Register */ +#define REG_PIOC_IFSR (*(RoReg*)0xFFFFF628U) /**< \brief (PIOC) Glitch Input Filter Status Register */ +#define REG_PIOC_SODR (*(WoReg*)0xFFFFF630U) /**< \brief (PIOC) Set Output Data Register */ +#define REG_PIOC_CODR (*(WoReg*)0xFFFFF634U) /**< \brief (PIOC) Clear Output Data Register */ +#define REG_PIOC_ODSR (*(RwReg*)0xFFFFF638U) /**< \brief (PIOC) Output Data Status Register */ +#define REG_PIOC_PDSR (*(RoReg*)0xFFFFF63CU) /**< \brief (PIOC) Pin Data Status Register */ +#define REG_PIOC_IER (*(WoReg*)0xFFFFF640U) /**< \brief (PIOC) Interrupt Enable Register */ +#define REG_PIOC_IDR (*(WoReg*)0xFFFFF644U) /**< \brief (PIOC) Interrupt Disable Register */ +#define REG_PIOC_IMR (*(RoReg*)0xFFFFF648U) /**< \brief (PIOC) Interrupt Mask Register */ +#define REG_PIOC_ISR (*(RoReg*)0xFFFFF64CU) /**< \brief (PIOC) Interrupt Status Register */ +#define REG_PIOC_MDER (*(WoReg*)0xFFFFF650U) /**< \brief (PIOC) Multi-driver Enable Register */ +#define REG_PIOC_MDDR (*(WoReg*)0xFFFFF654U) /**< \brief (PIOC) Multi-driver Disable Register */ +#define REG_PIOC_MDSR (*(RoReg*)0xFFFFF658U) /**< \brief (PIOC) Multi-driver Status Register */ +#define REG_PIOC_PUDR (*(WoReg*)0xFFFFF660U) /**< \brief (PIOC) Pull-up Disable Register */ +#define REG_PIOC_PUER (*(WoReg*)0xFFFFF664U) /**< \brief (PIOC) Pull-up Enable Register */ +#define REG_PIOC_PUSR (*(RoReg*)0xFFFFF668U) /**< \brief (PIOC) Pad Pull-up Status Register */ +#define REG_PIOC_ABCDSR (*(RwReg*)0xFFFFF670U) /**< \brief (PIOC) Peripheral Select Register */ +#define REG_PIOC_IFSCDR (*(WoReg*)0xFFFFF680U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */ +#define REG_PIOC_IFSCER (*(WoReg*)0xFFFFF684U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */ +#define REG_PIOC_IFSCSR (*(RoReg*)0xFFFFF688U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */ +#define REG_PIOC_SCDR (*(RwReg*)0xFFFFF68CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */ +#define REG_PIOC_PPDDR (*(WoReg*)0xFFFFF690U) /**< \brief (PIOC) Pad Pull-down Disable Register */ +#define REG_PIOC_PPDER (*(WoReg*)0xFFFFF694U) /**< \brief (PIOC) Pad Pull-down Enable Register */ +#define REG_PIOC_PPDSR (*(RoReg*)0xFFFFF698U) /**< \brief (PIOC) Pad Pull-down Status Register */ +#define REG_PIOC_OWER (*(WoReg*)0xFFFFF6A0U) /**< \brief (PIOC) Output Write Enable */ +#define REG_PIOC_OWDR (*(WoReg*)0xFFFFF6A4U) /**< \brief (PIOC) Output Write Disable */ +#define REG_PIOC_OWSR (*(RoReg*)0xFFFFF6A8U) /**< \brief (PIOC) Output Write Status Register */ +#define REG_PIOC_AIMER (*(WoReg*)0xFFFFF6B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */ +#define REG_PIOC_AIMDR (*(WoReg*)0xFFFFF6B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */ +#define REG_PIOC_AIMMR (*(RoReg*)0xFFFFF6B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */ +#define REG_PIOC_ESR (*(WoReg*)0xFFFFF6C0U) /**< \brief (PIOC) Edge Select Register */ +#define REG_PIOC_LSR (*(WoReg*)0xFFFFF6C4U) /**< \brief (PIOC) Level Select Register */ +#define REG_PIOC_ELSR (*(RoReg*)0xFFFFF6C8U) /**< \brief (PIOC) Edge/Level Status Register */ +#define REG_PIOC_FELLSR (*(WoReg*)0xFFFFF6D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */ +#define REG_PIOC_REHLSR (*(WoReg*)0xFFFFF6D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */ +#define REG_PIOC_FRLHSR (*(RoReg*)0xFFFFF6D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */ +#define REG_PIOC_LOCKSR (*(RoReg*)0xFFFFF6E0U) /**< \brief (PIOC) Lock Status */ +#define REG_PIOC_WPMR (*(RwReg*)0xFFFFF6E4U) /**< \brief (PIOC) Write Protect Mode Register */ +#define REG_PIOC_WPSR (*(RoReg*)0xFFFFF6E8U) /**< \brief (PIOC) Write Protect Status Register */ +#define REG_PIOC_SCHMITT (*(RwReg*)0xFFFFF700U) /**< \brief (PIOC) Schmitt Trigger Register */ +#define REG_PIOC_DRIVER1 (*(RwReg*)0xFFFFF718U) /**< \brief (PIOC) I/O Drive Register 1 */ +#define REG_PIOC_DRIVER2 (*(RwReg*)0xFFFFF71CU) /**< \brief (PIOC) I/O Drive Register 2 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_PIOC_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_piod.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_piod.h new file mode 100644 index 0000000..c8d262d --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_piod.h
@@ -0,0 +1,136 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_PIOD_INSTANCE_ +#define _SAMA5_PIOD_INSTANCE_ + +/* ========== Register definition for PIOD peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PIOD_PER (0xFFFFF800U) /**< \brief (PIOD) PIO Enable Register */ +#define REG_PIOD_PDR (0xFFFFF804U) /**< \brief (PIOD) PIO Disable Register */ +#define REG_PIOD_PSR (0xFFFFF808U) /**< \brief (PIOD) PIO Status Register */ +#define REG_PIOD_OER (0xFFFFF810U) /**< \brief (PIOD) Output Enable Register */ +#define REG_PIOD_ODR (0xFFFFF814U) /**< \brief (PIOD) Output Disable Register */ +#define REG_PIOD_OSR (0xFFFFF818U) /**< \brief (PIOD) Output Status Register */ +#define REG_PIOD_IFER (0xFFFFF820U) /**< \brief (PIOD) Glitch Input Filter Enable Register */ +#define REG_PIOD_IFDR (0xFFFFF824U) /**< \brief (PIOD) Glitch Input Filter Disable Register */ +#define REG_PIOD_IFSR (0xFFFFF828U) /**< \brief (PIOD) Glitch Input Filter Status Register */ +#define REG_PIOD_SODR (0xFFFFF830U) /**< \brief (PIOD) Set Output Data Register */ +#define REG_PIOD_CODR (0xFFFFF834U) /**< \brief (PIOD) Clear Output Data Register */ +#define REG_PIOD_ODSR (0xFFFFF838U) /**< \brief (PIOD) Output Data Status Register */ +#define REG_PIOD_PDSR (0xFFFFF83CU) /**< \brief (PIOD) Pin Data Status Register */ +#define REG_PIOD_IER (0xFFFFF840U) /**< \brief (PIOD) Interrupt Enable Register */ +#define REG_PIOD_IDR (0xFFFFF844U) /**< \brief (PIOD) Interrupt Disable Register */ +#define REG_PIOD_IMR (0xFFFFF848U) /**< \brief (PIOD) Interrupt Mask Register */ +#define REG_PIOD_ISR (0xFFFFF84CU) /**< \brief (PIOD) Interrupt Status Register */ +#define REG_PIOD_MDER (0xFFFFF850U) /**< \brief (PIOD) Multi-driver Enable Register */ +#define REG_PIOD_MDDR (0xFFFFF854U) /**< \brief (PIOD) Multi-driver Disable Register */ +#define REG_PIOD_MDSR (0xFFFFF858U) /**< \brief (PIOD) Multi-driver Status Register */ +#define REG_PIOD_PUDR (0xFFFFF860U) /**< \brief (PIOD) Pull-up Disable Register */ +#define REG_PIOD_PUER (0xFFFFF864U) /**< \brief (PIOD) Pull-up Enable Register */ +#define REG_PIOD_PUSR (0xFFFFF868U) /**< \brief (PIOD) Pad Pull-up Status Register */ +#define REG_PIOD_ABCDSR (0xFFFFF870U) /**< \brief (PIOD) Peripheral Select Register */ +#define REG_PIOD_IFSCDR (0xFFFFF880U) /**< \brief (PIOD) Input Filter Slow Clock Disable Register */ +#define REG_PIOD_IFSCER (0xFFFFF884U) /**< \brief (PIOD) Input Filter Slow Clock Enable Register */ +#define REG_PIOD_IFSCSR (0xFFFFF888U) /**< \brief (PIOD) Input Filter Slow Clock Status Register */ +#define REG_PIOD_SCDR (0xFFFFF88CU) /**< \brief (PIOD) Slow Clock Divider Debouncing Register */ +#define REG_PIOD_PPDDR (0xFFFFF890U) /**< \brief (PIOD) Pad Pull-down Disable Register */ +#define REG_PIOD_PPDER (0xFFFFF894U) /**< \brief (PIOD) Pad Pull-down Enable Register */ +#define REG_PIOD_PPDSR (0xFFFFF898U) /**< \brief (PIOD) Pad Pull-down Status Register */ +#define REG_PIOD_OWER (0xFFFFF8A0U) /**< \brief (PIOD) Output Write Enable */ +#define REG_PIOD_OWDR (0xFFFFF8A4U) /**< \brief (PIOD) Output Write Disable */ +#define REG_PIOD_OWSR (0xFFFFF8A8U) /**< \brief (PIOD) Output Write Status Register */ +#define REG_PIOD_AIMER (0xFFFFF8B0U) /**< \brief (PIOD) Additional Interrupt Modes Enable Register */ +#define REG_PIOD_AIMDR (0xFFFFF8B4U) /**< \brief (PIOD) Additional Interrupt Modes Disables Register */ +#define REG_PIOD_AIMMR (0xFFFFF8B8U) /**< \brief (PIOD) Additional Interrupt Modes Mask Register */ +#define REG_PIOD_ESR (0xFFFFF8C0U) /**< \brief (PIOD) Edge Select Register */ +#define REG_PIOD_LSR (0xFFFFF8C4U) /**< \brief (PIOD) Level Select Register */ +#define REG_PIOD_ELSR (0xFFFFF8C8U) /**< \brief (PIOD) Edge/Level Status Register */ +#define REG_PIOD_FELLSR (0xFFFFF8D0U) /**< \brief (PIOD) Falling Edge/Low Level Select Register */ +#define REG_PIOD_REHLSR (0xFFFFF8D4U) /**< \brief (PIOD) Rising Edge/ High Level Select Register */ +#define REG_PIOD_FRLHSR (0xFFFFF8D8U) /**< \brief (PIOD) Fall/Rise - Low/High Status Register */ +#define REG_PIOD_LOCKSR (0xFFFFF8E0U) /**< \brief (PIOD) Lock Status */ +#define REG_PIOD_WPMR (0xFFFFF8E4U) /**< \brief (PIOD) Write Protect Mode Register */ +#define REG_PIOD_WPSR (0xFFFFF8E8U) /**< \brief (PIOD) Write Protect Status Register */ +#define REG_PIOD_SCHMITT (0xFFFFF900U) /**< \brief (PIOD) Schmitt Trigger Register */ +#define REG_PIOD_DRIVER1 (0xFFFFF918U) /**< \brief (PIOD) I/O Drive Register 1 */ +#define REG_PIOD_DRIVER2 (0xFFFFF91CU) /**< \brief (PIOD) I/O Drive Register 2 */ +#else +#define REG_PIOD_PER (*(WoReg*)0xFFFFF800U) /**< \brief (PIOD) PIO Enable Register */ +#define REG_PIOD_PDR (*(WoReg*)0xFFFFF804U) /**< \brief (PIOD) PIO Disable Register */ +#define REG_PIOD_PSR (*(RoReg*)0xFFFFF808U) /**< \brief (PIOD) PIO Status Register */ +#define REG_PIOD_OER (*(WoReg*)0xFFFFF810U) /**< \brief (PIOD) Output Enable Register */ +#define REG_PIOD_ODR (*(WoReg*)0xFFFFF814U) /**< \brief (PIOD) Output Disable Register */ +#define REG_PIOD_OSR (*(RoReg*)0xFFFFF818U) /**< \brief (PIOD) Output Status Register */ +#define REG_PIOD_IFER (*(WoReg*)0xFFFFF820U) /**< \brief (PIOD) Glitch Input Filter Enable Register */ +#define REG_PIOD_IFDR (*(WoReg*)0xFFFFF824U) /**< \brief (PIOD) Glitch Input Filter Disable Register */ +#define REG_PIOD_IFSR (*(RoReg*)0xFFFFF828U) /**< \brief (PIOD) Glitch Input Filter Status Register */ +#define REG_PIOD_SODR (*(WoReg*)0xFFFFF830U) /**< \brief (PIOD) Set Output Data Register */ +#define REG_PIOD_CODR (*(WoReg*)0xFFFFF834U) /**< \brief (PIOD) Clear Output Data Register */ +#define REG_PIOD_ODSR (*(RwReg*)0xFFFFF838U) /**< \brief (PIOD) Output Data Status Register */ +#define REG_PIOD_PDSR (*(RoReg*)0xFFFFF83CU) /**< \brief (PIOD) Pin Data Status Register */ +#define REG_PIOD_IER (*(WoReg*)0xFFFFF840U) /**< \brief (PIOD) Interrupt Enable Register */ +#define REG_PIOD_IDR (*(WoReg*)0xFFFFF844U) /**< \brief (PIOD) Interrupt Disable Register */ +#define REG_PIOD_IMR (*(RoReg*)0xFFFFF848U) /**< \brief (PIOD) Interrupt Mask Register */ +#define REG_PIOD_ISR (*(RoReg*)0xFFFFF84CU) /**< \brief (PIOD) Interrupt Status Register */ +#define REG_PIOD_MDER (*(WoReg*)0xFFFFF850U) /**< \brief (PIOD) Multi-driver Enable Register */ +#define REG_PIOD_MDDR (*(WoReg*)0xFFFFF854U) /**< \brief (PIOD) Multi-driver Disable Register */ +#define REG_PIOD_MDSR (*(RoReg*)0xFFFFF858U) /**< \brief (PIOD) Multi-driver Status Register */ +#define REG_PIOD_PUDR (*(WoReg*)0xFFFFF860U) /**< \brief (PIOD) Pull-up Disable Register */ +#define REG_PIOD_PUER (*(WoReg*)0xFFFFF864U) /**< \brief (PIOD) Pull-up Enable Register */ +#define REG_PIOD_PUSR (*(RoReg*)0xFFFFF868U) /**< \brief (PIOD) Pad Pull-up Status Register */ +#define REG_PIOD_ABCDSR (*(RwReg*)0xFFFFF870U) /**< \brief (PIOD) Peripheral Select Register */ +#define REG_PIOD_IFSCDR (*(WoReg*)0xFFFFF880U) /**< \brief (PIOD) Input Filter Slow Clock Disable Register */ +#define REG_PIOD_IFSCER (*(WoReg*)0xFFFFF884U) /**< \brief (PIOD) Input Filter Slow Clock Enable Register */ +#define REG_PIOD_IFSCSR (*(RoReg*)0xFFFFF888U) /**< \brief (PIOD) Input Filter Slow Clock Status Register */ +#define REG_PIOD_SCDR (*(RwReg*)0xFFFFF88CU) /**< \brief (PIOD) Slow Clock Divider Debouncing Register */ +#define REG_PIOD_PPDDR (*(WoReg*)0xFFFFF890U) /**< \brief (PIOD) Pad Pull-down Disable Register */ +#define REG_PIOD_PPDER (*(WoReg*)0xFFFFF894U) /**< \brief (PIOD) Pad Pull-down Enable Register */ +#define REG_PIOD_PPDSR (*(RoReg*)0xFFFFF898U) /**< \brief (PIOD) Pad Pull-down Status Register */ +#define REG_PIOD_OWER (*(WoReg*)0xFFFFF8A0U) /**< \brief (PIOD) Output Write Enable */ +#define REG_PIOD_OWDR (*(WoReg*)0xFFFFF8A4U) /**< \brief (PIOD) Output Write Disable */ +#define REG_PIOD_OWSR (*(RoReg*)0xFFFFF8A8U) /**< \brief (PIOD) Output Write Status Register */ +#define REG_PIOD_AIMER (*(WoReg*)0xFFFFF8B0U) /**< \brief (PIOD) Additional Interrupt Modes Enable Register */ +#define REG_PIOD_AIMDR (*(WoReg*)0xFFFFF8B4U) /**< \brief (PIOD) Additional Interrupt Modes Disables Register */ +#define REG_PIOD_AIMMR (*(RoReg*)0xFFFFF8B8U) /**< \brief (PIOD) Additional Interrupt Modes Mask Register */ +#define REG_PIOD_ESR (*(WoReg*)0xFFFFF8C0U) /**< \brief (PIOD) Edge Select Register */ +#define REG_PIOD_LSR (*(WoReg*)0xFFFFF8C4U) /**< \brief (PIOD) Level Select Register */ +#define REG_PIOD_ELSR (*(RoReg*)0xFFFFF8C8U) /**< \brief (PIOD) Edge/Level Status Register */ +#define REG_PIOD_FELLSR (*(WoReg*)0xFFFFF8D0U) /**< \brief (PIOD) Falling Edge/Low Level Select Register */ +#define REG_PIOD_REHLSR (*(WoReg*)0xFFFFF8D4U) /**< \brief (PIOD) Rising Edge/ High Level Select Register */ +#define REG_PIOD_FRLHSR (*(RoReg*)0xFFFFF8D8U) /**< \brief (PIOD) Fall/Rise - Low/High Status Register */ +#define REG_PIOD_LOCKSR (*(RoReg*)0xFFFFF8E0U) /**< \brief (PIOD) Lock Status */ +#define REG_PIOD_WPMR (*(RwReg*)0xFFFFF8E4U) /**< \brief (PIOD) Write Protect Mode Register */ +#define REG_PIOD_WPSR (*(RoReg*)0xFFFFF8E8U) /**< \brief (PIOD) Write Protect Status Register */ +#define REG_PIOD_SCHMITT (*(RwReg*)0xFFFFF900U) /**< \brief (PIOD) Schmitt Trigger Register */ +#define REG_PIOD_DRIVER1 (*(RwReg*)0xFFFFF918U) /**< \brief (PIOD) I/O Drive Register 1 */ +#define REG_PIOD_DRIVER2 (*(RwReg*)0xFFFFF91CU) /**< \brief (PIOD) I/O Drive Register 2 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_PIOD_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_pioe.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_pioe.h new file mode 100644 index 0000000..ea5ff10 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_pioe.h
@@ -0,0 +1,136 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_PIOE_INSTANCE_ +#define _SAMA5_PIOE_INSTANCE_ + +/* ========== Register definition for PIOE peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PIOE_PER (0xFFFFFA00U) /**< \brief (PIOE) PIO Enable Register */ +#define REG_PIOE_PDR (0xFFFFFA04U) /**< \brief (PIOE) PIO Disable Register */ +#define REG_PIOE_PSR (0xFFFFFA08U) /**< \brief (PIOE) PIO Status Register */ +#define REG_PIOE_OER (0xFFFFFA10U) /**< \brief (PIOE) Output Enable Register */ +#define REG_PIOE_ODR (0xFFFFFA14U) /**< \brief (PIOE) Output Disable Register */ +#define REG_PIOE_OSR (0xFFFFFA18U) /**< \brief (PIOE) Output Status Register */ +#define REG_PIOE_IFER (0xFFFFFA20U) /**< \brief (PIOE) Glitch Input Filter Enable Register */ +#define REG_PIOE_IFDR (0xFFFFFA24U) /**< \brief (PIOE) Glitch Input Filter Disable Register */ +#define REG_PIOE_IFSR (0xFFFFFA28U) /**< \brief (PIOE) Glitch Input Filter Status Register */ +#define REG_PIOE_SODR (0xFFFFFA30U) /**< \brief (PIOE) Set Output Data Register */ +#define REG_PIOE_CODR (0xFFFFFA34U) /**< \brief (PIOE) Clear Output Data Register */ +#define REG_PIOE_ODSR (0xFFFFFA38U) /**< \brief (PIOE) Output Data Status Register */ +#define REG_PIOE_PDSR (0xFFFFFA3CU) /**< \brief (PIOE) Pin Data Status Register */ +#define REG_PIOE_IER (0xFFFFFA40U) /**< \brief (PIOE) Interrupt Enable Register */ +#define REG_PIOE_IDR (0xFFFFFA44U) /**< \brief (PIOE) Interrupt Disable Register */ +#define REG_PIOE_IMR (0xFFFFFA48U) /**< \brief (PIOE) Interrupt Mask Register */ +#define REG_PIOE_ISR (0xFFFFFA4CU) /**< \brief (PIOE) Interrupt Status Register */ +#define REG_PIOE_MDER (0xFFFFFA50U) /**< \brief (PIOE) Multi-driver Enable Register */ +#define REG_PIOE_MDDR (0xFFFFFA54U) /**< \brief (PIOE) Multi-driver Disable Register */ +#define REG_PIOE_MDSR (0xFFFFFA58U) /**< \brief (PIOE) Multi-driver Status Register */ +#define REG_PIOE_PUDR (0xFFFFFA60U) /**< \brief (PIOE) Pull-up Disable Register */ +#define REG_PIOE_PUER (0xFFFFFA64U) /**< \brief (PIOE) Pull-up Enable Register */ +#define REG_PIOE_PUSR (0xFFFFFA68U) /**< \brief (PIOE) Pad Pull-up Status Register */ +#define REG_PIOE_ABCDSR (0xFFFFFA70U) /**< \brief (PIOE) Peripheral Select Register */ +#define REG_PIOE_IFSCDR (0xFFFFFA80U) /**< \brief (PIOE) Input Filter Slow Clock Disable Register */ +#define REG_PIOE_IFSCER (0xFFFFFA84U) /**< \brief (PIOE) Input Filter Slow Clock Enable Register */ +#define REG_PIOE_IFSCSR (0xFFFFFA88U) /**< \brief (PIOE) Input Filter Slow Clock Status Register */ +#define REG_PIOE_SCDR (0xFFFFFA8CU) /**< \brief (PIOE) Slow Clock Divider Debouncing Register */ +#define REG_PIOE_PPDDR (0xFFFFFA90U) /**< \brief (PIOE) Pad Pull-down Disable Register */ +#define REG_PIOE_PPDER (0xFFFFFA94U) /**< \brief (PIOE) Pad Pull-down Enable Register */ +#define REG_PIOE_PPDSR (0xFFFFFA98U) /**< \brief (PIOE) Pad Pull-down Status Register */ +#define REG_PIOE_OWER (0xFFFFFAA0U) /**< \brief (PIOE) Output Write Enable */ +#define REG_PIOE_OWDR (0xFFFFFAA4U) /**< \brief (PIOE) Output Write Disable */ +#define REG_PIOE_OWSR (0xFFFFFAA8U) /**< \brief (PIOE) Output Write Status Register */ +#define REG_PIOE_AIMER (0xFFFFFAB0U) /**< \brief (PIOE) Additional Interrupt Modes Enable Register */ +#define REG_PIOE_AIMDR (0xFFFFFAB4U) /**< \brief (PIOE) Additional Interrupt Modes Disables Register */ +#define REG_PIOE_AIMMR (0xFFFFFAB8U) /**< \brief (PIOE) Additional Interrupt Modes Mask Register */ +#define REG_PIOE_ESR (0xFFFFFAC0U) /**< \brief (PIOE) Edge Select Register */ +#define REG_PIOE_LSR (0xFFFFFAC4U) /**< \brief (PIOE) Level Select Register */ +#define REG_PIOE_ELSR (0xFFFFFAC8U) /**< \brief (PIOE) Edge/Level Status Register */ +#define REG_PIOE_FELLSR (0xFFFFFAD0U) /**< \brief (PIOE) Falling Edge/Low Level Select Register */ +#define REG_PIOE_REHLSR (0xFFFFFAD4U) /**< \brief (PIOE) Rising Edge/ High Level Select Register */ +#define REG_PIOE_FRLHSR (0xFFFFFAD8U) /**< \brief (PIOE) Fall/Rise - Low/High Status Register */ +#define REG_PIOE_LOCKSR (0xFFFFFAE0U) /**< \brief (PIOE) Lock Status */ +#define REG_PIOE_WPMR (0xFFFFFAE4U) /**< \brief (PIOE) Write Protect Mode Register */ +#define REG_PIOE_WPSR (0xFFFFFAE8U) /**< \brief (PIOE) Write Protect Status Register */ +#define REG_PIOE_SCHMITT (0xFFFFFB00U) /**< \brief (PIOE) Schmitt Trigger Register */ +#define REG_PIOE_DRIVER1 (0xFFFFFB18U) /**< \brief (PIOE) I/O Drive Register 1 */ +#define REG_PIOE_DRIVER2 (0xFFFFFB1CU) /**< \brief (PIOE) I/O Drive Register 2 */ +#else +#define REG_PIOE_PER (*(WoReg*)0xFFFFFA00U) /**< \brief (PIOE) PIO Enable Register */ +#define REG_PIOE_PDR (*(WoReg*)0xFFFFFA04U) /**< \brief (PIOE) PIO Disable Register */ +#define REG_PIOE_PSR (*(RoReg*)0xFFFFFA08U) /**< \brief (PIOE) PIO Status Register */ +#define REG_PIOE_OER (*(WoReg*)0xFFFFFA10U) /**< \brief (PIOE) Output Enable Register */ +#define REG_PIOE_ODR (*(WoReg*)0xFFFFFA14U) /**< \brief (PIOE) Output Disable Register */ +#define REG_PIOE_OSR (*(RoReg*)0xFFFFFA18U) /**< \brief (PIOE) Output Status Register */ +#define REG_PIOE_IFER (*(WoReg*)0xFFFFFA20U) /**< \brief (PIOE) Glitch Input Filter Enable Register */ +#define REG_PIOE_IFDR (*(WoReg*)0xFFFFFA24U) /**< \brief (PIOE) Glitch Input Filter Disable Register */ +#define REG_PIOE_IFSR (*(RoReg*)0xFFFFFA28U) /**< \brief (PIOE) Glitch Input Filter Status Register */ +#define REG_PIOE_SODR (*(WoReg*)0xFFFFFA30U) /**< \brief (PIOE) Set Output Data Register */ +#define REG_PIOE_CODR (*(WoReg*)0xFFFFFA34U) /**< \brief (PIOE) Clear Output Data Register */ +#define REG_PIOE_ODSR (*(RwReg*)0xFFFFFA38U) /**< \brief (PIOE) Output Data Status Register */ +#define REG_PIOE_PDSR (*(RoReg*)0xFFFFFA3CU) /**< \brief (PIOE) Pin Data Status Register */ +#define REG_PIOE_IER (*(WoReg*)0xFFFFFA40U) /**< \brief (PIOE) Interrupt Enable Register */ +#define REG_PIOE_IDR (*(WoReg*)0xFFFFFA44U) /**< \brief (PIOE) Interrupt Disable Register */ +#define REG_PIOE_IMR (*(RoReg*)0xFFFFFA48U) /**< \brief (PIOE) Interrupt Mask Register */ +#define REG_PIOE_ISR (*(RoReg*)0xFFFFFA4CU) /**< \brief (PIOE) Interrupt Status Register */ +#define REG_PIOE_MDER (*(WoReg*)0xFFFFFA50U) /**< \brief (PIOE) Multi-driver Enable Register */ +#define REG_PIOE_MDDR (*(WoReg*)0xFFFFFA54U) /**< \brief (PIOE) Multi-driver Disable Register */ +#define REG_PIOE_MDSR (*(RoReg*)0xFFFFFA58U) /**< \brief (PIOE) Multi-driver Status Register */ +#define REG_PIOE_PUDR (*(WoReg*)0xFFFFFA60U) /**< \brief (PIOE) Pull-up Disable Register */ +#define REG_PIOE_PUER (*(WoReg*)0xFFFFFA64U) /**< \brief (PIOE) Pull-up Enable Register */ +#define REG_PIOE_PUSR (*(RoReg*)0xFFFFFA68U) /**< \brief (PIOE) Pad Pull-up Status Register */ +#define REG_PIOE_ABCDSR (*(RwReg*)0xFFFFFA70U) /**< \brief (PIOE) Peripheral Select Register */ +#define REG_PIOE_IFSCDR (*(WoReg*)0xFFFFFA80U) /**< \brief (PIOE) Input Filter Slow Clock Disable Register */ +#define REG_PIOE_IFSCER (*(WoReg*)0xFFFFFA84U) /**< \brief (PIOE) Input Filter Slow Clock Enable Register */ +#define REG_PIOE_IFSCSR (*(RoReg*)0xFFFFFA88U) /**< \brief (PIOE) Input Filter Slow Clock Status Register */ +#define REG_PIOE_SCDR (*(RwReg*)0xFFFFFA8CU) /**< \brief (PIOE) Slow Clock Divider Debouncing Register */ +#define REG_PIOE_PPDDR (*(WoReg*)0xFFFFFA90U) /**< \brief (PIOE) Pad Pull-down Disable Register */ +#define REG_PIOE_PPDER (*(WoReg*)0xFFFFFA94U) /**< \brief (PIOE) Pad Pull-down Enable Register */ +#define REG_PIOE_PPDSR (*(RoReg*)0xFFFFFA98U) /**< \brief (PIOE) Pad Pull-down Status Register */ +#define REG_PIOE_OWER (*(WoReg*)0xFFFFFAA0U) /**< \brief (PIOE) Output Write Enable */ +#define REG_PIOE_OWDR (*(WoReg*)0xFFFFFAA4U) /**< \brief (PIOE) Output Write Disable */ +#define REG_PIOE_OWSR (*(RoReg*)0xFFFFFAA8U) /**< \brief (PIOE) Output Write Status Register */ +#define REG_PIOE_AIMER (*(WoReg*)0xFFFFFAB0U) /**< \brief (PIOE) Additional Interrupt Modes Enable Register */ +#define REG_PIOE_AIMDR (*(WoReg*)0xFFFFFAB4U) /**< \brief (PIOE) Additional Interrupt Modes Disables Register */ +#define REG_PIOE_AIMMR (*(RoReg*)0xFFFFFAB8U) /**< \brief (PIOE) Additional Interrupt Modes Mask Register */ +#define REG_PIOE_ESR (*(WoReg*)0xFFFFFAC0U) /**< \brief (PIOE) Edge Select Register */ +#define REG_PIOE_LSR (*(WoReg*)0xFFFFFAC4U) /**< \brief (PIOE) Level Select Register */ +#define REG_PIOE_ELSR (*(RoReg*)0xFFFFFAC8U) /**< \brief (PIOE) Edge/Level Status Register */ +#define REG_PIOE_FELLSR (*(WoReg*)0xFFFFFAD0U) /**< \brief (PIOE) Falling Edge/Low Level Select Register */ +#define REG_PIOE_REHLSR (*(WoReg*)0xFFFFFAD4U) /**< \brief (PIOE) Rising Edge/ High Level Select Register */ +#define REG_PIOE_FRLHSR (*(RoReg*)0xFFFFFAD8U) /**< \brief (PIOE) Fall/Rise - Low/High Status Register */ +#define REG_PIOE_LOCKSR (*(RoReg*)0xFFFFFAE0U) /**< \brief (PIOE) Lock Status */ +#define REG_PIOE_WPMR (*(RwReg*)0xFFFFFAE4U) /**< \brief (PIOE) Write Protect Mode Register */ +#define REG_PIOE_WPSR (*(RoReg*)0xFFFFFAE8U) /**< \brief (PIOE) Write Protect Status Register */ +#define REG_PIOE_SCHMITT (*(RwReg*)0xFFFFFB00U) /**< \brief (PIOE) Schmitt Trigger Register */ +#define REG_PIOE_DRIVER1 (*(RwReg*)0xFFFFFB18U) /**< \brief (PIOE) I/O Drive Register 1 */ +#define REG_PIOE_DRIVER2 (*(RwReg*)0xFFFFFB1CU) /**< \brief (PIOE) I/O Drive Register 2 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_PIOE_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_pit.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_pit.h new file mode 100644 index 0000000..efcd222 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_pit.h
@@ -0,0 +1,46 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_PIT_INSTANCE_ +#define _SAMA5_PIT_INSTANCE_ + +/* ========== Register definition for PIT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PIT_MR (0xFFFFFE30U) /**< \brief (PIT) Mode Register */ +#define REG_PIT_SR (0xFFFFFE34U) /**< \brief (PIT) Status Register */ +#define REG_PIT_PIVR (0xFFFFFE38U) /**< \brief (PIT) Periodic Interval Value Register */ +#define REG_PIT_PIIR (0xFFFFFE3CU) /**< \brief (PIT) Periodic Interval Image Register */ +#else +#define REG_PIT_MR (*(RwReg*)0xFFFFFE30U) /**< \brief (PIT) Mode Register */ +#define REG_PIT_SR (*(RoReg*)0xFFFFFE34U) /**< \brief (PIT) Status Register */ +#define REG_PIT_PIVR (*(RoReg*)0xFFFFFE38U) /**< \brief (PIT) Periodic Interval Value Register */ +#define REG_PIT_PIIR (*(RoReg*)0xFFFFFE3CU) /**< \brief (PIT) Periodic Interval Image Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_PIT_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_pmc.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_pmc.h new file mode 100644 index 0000000..f0d3ed0 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_pmc.h
@@ -0,0 +1,88 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_PMC_INSTANCE_ +#define _SAMA5_PMC_INSTANCE_ + +/* ========== Register definition for PMC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PMC_SCER (0xFFFFFC00U) /**< \brief (PMC) System Clock Enable Register */ +#define REG_PMC_SCDR (0xFFFFFC04U) /**< \brief (PMC) System Clock Disable Register */ +#define REG_PMC_SCSR (0xFFFFFC08U) /**< \brief (PMC) System Clock Status Register */ +#define REG_PMC_PCER0 (0xFFFFFC10U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */ +#define REG_PMC_PCDR0 (0xFFFFFC14U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */ +#define REG_PMC_PCSR0 (0xFFFFFC18U) /**< \brief (PMC) Peripheral Clock Status Register 0 */ +#define REG_CKGR_UCKR (0xFFFFFC1CU) /**< \brief (PMC) UTMI Clock Register */ +#define REG_CKGR_MOR (0xFFFFFC20U) /**< \brief (PMC) Main Oscillator Register */ +#define REG_CKGR_MCFR (0xFFFFFC24U) /**< \brief (PMC) Main Clock Frequency Register */ +#define REG_CKGR_PLLAR (0xFFFFFC28U) /**< \brief (PMC) PLLA Register */ +#define REG_PMC_MCKR (0xFFFFFC30U) /**< \brief (PMC) Master Clock Register */ +#define REG_PMC_USB (0xFFFFFC38U) /**< \brief (PMC) USB Clock Register */ +#define REG_PMC_SMD (0xFFFFFC3CU) /**< \brief (PMC) Soft Modem Clock Register */ +#define REG_PMC_PCK (0xFFFFFC40U) /**< \brief (PMC) Programmable Clock 0 Register */ +#define REG_PMC_IER (0xFFFFFC60U) /**< \brief (PMC) Interrupt Enable Register */ +#define REG_PMC_IDR (0xFFFFFC64U) /**< \brief (PMC) Interrupt Disable Register */ +#define REG_PMC_SR (0xFFFFFC68U) /**< \brief (PMC) Status Register */ +#define REG_PMC_IMR (0xFFFFFC6CU) /**< \brief (PMC) Interrupt Mask Register */ +#define REG_PMC_PLLICPR (0xFFFFFC80U) /**< \brief (PMC) PLL Charge Pump Current Register */ +#define REG_PMC_WPMR (0xFFFFFCE4U) /**< \brief (PMC) Write Protect Mode Register */ +#define REG_PMC_WPSR (0xFFFFFCE8U) /**< \brief (PMC) Write Protect Status Register */ +#define REG_PMC_PCER1 (0xFFFFFD00U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */ +#define REG_PMC_PCDR1 (0xFFFFFD04U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */ +#define REG_PMC_PCSR1 (0xFFFFFD08U) /**< \brief (PMC) Peripheral Clock Status Register 1 */ +#define REG_PMC_PCR (0xFFFFFD0CU) /**< \brief (PMC) Peripheral Control Register */ +#else +#define REG_PMC_SCER (*(WoReg*)0xFFFFFC00U) /**< \brief (PMC) System Clock Enable Register */ +#define REG_PMC_SCDR (*(WoReg*)0xFFFFFC04U) /**< \brief (PMC) System Clock Disable Register */ +#define REG_PMC_SCSR (*(RoReg*)0xFFFFFC08U) /**< \brief (PMC) System Clock Status Register */ +#define REG_PMC_PCER0 (*(WoReg*)0xFFFFFC10U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */ +#define REG_PMC_PCDR0 (*(WoReg*)0xFFFFFC14U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */ +#define REG_PMC_PCSR0 (*(RoReg*)0xFFFFFC18U) /**< \brief (PMC) Peripheral Clock Status Register 0 */ +#define REG_CKGR_UCKR (*(RwReg*)0xFFFFFC1CU) /**< \brief (PMC) UTMI Clock Register */ +#define REG_CKGR_MOR (*(RwReg*)0xFFFFFC20U) /**< \brief (PMC) Main Oscillator Register */ +#define REG_CKGR_MCFR (*(RoReg*)0xFFFFFC24U) /**< \brief (PMC) Main Clock Frequency Register */ +#define REG_CKGR_PLLAR (*(RwReg*)0xFFFFFC28U) /**< \brief (PMC) PLLA Register */ +#define REG_PMC_MCKR (*(RwReg*)0xFFFFFC30U) /**< \brief (PMC) Master Clock Register */ +#define REG_PMC_USB (*(RwReg*)0xFFFFFC38U) /**< \brief (PMC) USB Clock Register */ +#define REG_PMC_SMD (*(RwReg*)0xFFFFFC3CU) /**< \brief (PMC) Soft Modem Clock Register */ +#define REG_PMC_PCK (*(RwReg*)0xFFFFFC40U) /**< \brief (PMC) Programmable Clock 0 Register */ +#define REG_PMC_IER (*(WoReg*)0xFFFFFC60U) /**< \brief (PMC) Interrupt Enable Register */ +#define REG_PMC_IDR (*(WoReg*)0xFFFFFC64U) /**< \brief (PMC) Interrupt Disable Register */ +#define REG_PMC_SR (*(RoReg*)0xFFFFFC68U) /**< \brief (PMC) Status Register */ +#define REG_PMC_IMR (*(RoReg*)0xFFFFFC6CU) /**< \brief (PMC) Interrupt Mask Register */ +#define REG_PMC_PLLICPR (*(WoReg*)0xFFFFFC80U) /**< \brief (PMC) PLL Charge Pump Current Register */ +#define REG_PMC_WPMR (*(RwReg*)0xFFFFFCE4U) /**< \brief (PMC) Write Protect Mode Register */ +#define REG_PMC_WPSR (*(RoReg*)0xFFFFFCE8U) /**< \brief (PMC) Write Protect Status Register */ +#define REG_PMC_PCER1 (*(WoReg*)0xFFFFFD00U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */ +#define REG_PMC_PCDR1 (*(WoReg*)0xFFFFFD04U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */ +#define REG_PMC_PCSR1 (*(RoReg*)0xFFFFFD08U) /**< \brief (PMC) Peripheral Clock Status Register 1 */ +#define REG_PMC_PCR (*(RwReg*)0xFFFFFD0CU) /**< \brief (PMC) Peripheral Control Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_PMC_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_pwm.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_pwm.h new file mode 100644 index 0000000..b251513 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_pwm.h
@@ -0,0 +1,236 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_PWM_INSTANCE_ +#define _SAMA5_PWM_INSTANCE_ + +/* ========== Register definition for PWM peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PWM_CLK (0xF002C000U) /**< \brief (PWM) PWM Clock Register */ +#define REG_PWM_ENA (0xF002C004U) /**< \brief (PWM) PWM Enable Register */ +#define REG_PWM_DIS (0xF002C008U) /**< \brief (PWM) PWM Disable Register */ +#define REG_PWM_SR (0xF002C00CU) /**< \brief (PWM) PWM Status Register */ +#define REG_PWM_IER1 (0xF002C010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */ +#define REG_PWM_IDR1 (0xF002C014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */ +#define REG_PWM_IMR1 (0xF002C018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */ +#define REG_PWM_ISR1 (0xF002C01CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */ +#define REG_PWM_SCM (0xF002C020U) /**< \brief (PWM) PWM Sync Channels Mode Register */ +#define REG_PWM_SCUC (0xF002C028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */ +#define REG_PWM_SCUP (0xF002C02CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */ +#define REG_PWM_SCUPUPD (0xF002C030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */ +#define REG_PWM_IER2 (0xF002C034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */ +#define REG_PWM_IDR2 (0xF002C038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */ +#define REG_PWM_IMR2 (0xF002C03CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */ +#define REG_PWM_ISR2 (0xF002C040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */ +#define REG_PWM_OOV (0xF002C044U) /**< \brief (PWM) PWM Output Override Value Register */ +#define REG_PWM_OS (0xF002C048U) /**< \brief (PWM) PWM Output Selection Register */ +#define REG_PWM_OSS (0xF002C04CU) /**< \brief (PWM) PWM Output Selection Set Register */ +#define REG_PWM_OSC (0xF002C050U) /**< \brief (PWM) PWM Output Selection Clear Register */ +#define REG_PWM_OSSUPD (0xF002C054U) /**< \brief (PWM) PWM Output Selection Set Update Register */ +#define REG_PWM_OSCUPD (0xF002C058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */ +#define REG_PWM_FMR (0xF002C05CU) /**< \brief (PWM) PWM Fault Mode Register */ +#define REG_PWM_FSR (0xF002C060U) /**< \brief (PWM) PWM Fault Status Register */ +#define REG_PWM_FCR (0xF002C064U) /**< \brief (PWM) PWM Fault Clear Register */ +#define REG_PWM_FPV1 (0xF002C068U) /**< \brief (PWM) PWM Fault Protection Value Register 1 */ +#define REG_PWM_FPE (0xF002C06CU) /**< \brief (PWM) PWM Fault Protection Enable Register */ +#define REG_PWM_ELMR (0xF002C07CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */ +#define REG_PWM_FPV2 (0xF002C0C0U) /**< \brief (PWM) PWM Fault Protection Value 2 Register */ +#define REG_PWM_WPCR (0xF002C0E4U) /**< \brief (PWM) PWM Write Protect Control Register */ +#define REG_PWM_WPSR (0xF002C0E8U) /**< \brief (PWM) PWM Write Protect Status Register */ +#define REG_PWM_CMPV0 (0xF002C130U) /**< \brief (PWM) PWM Comparison 0 Value Register */ +#define REG_PWM_CMPVUPD0 (0xF002C134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */ +#define REG_PWM_CMPM0 (0xF002C138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */ +#define REG_PWM_CMPMUPD0 (0xF002C13CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */ +#define REG_PWM_CMPV1 (0xF002C140U) /**< \brief (PWM) PWM Comparison 1 Value Register */ +#define REG_PWM_CMPVUPD1 (0xF002C144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */ +#define REG_PWM_CMPM1 (0xF002C148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */ +#define REG_PWM_CMPMUPD1 (0xF002C14CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */ +#define REG_PWM_CMPV2 (0xF002C150U) /**< \brief (PWM) PWM Comparison 2 Value Register */ +#define REG_PWM_CMPVUPD2 (0xF002C154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */ +#define REG_PWM_CMPM2 (0xF002C158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */ +#define REG_PWM_CMPMUPD2 (0xF002C15CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */ +#define REG_PWM_CMPV3 (0xF002C160U) /**< \brief (PWM) PWM Comparison 3 Value Register */ +#define REG_PWM_CMPVUPD3 (0xF002C164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */ +#define REG_PWM_CMPM3 (0xF002C168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */ +#define REG_PWM_CMPMUPD3 (0xF002C16CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */ +#define REG_PWM_CMPV4 (0xF002C170U) /**< \brief (PWM) PWM Comparison 4 Value Register */ +#define REG_PWM_CMPVUPD4 (0xF002C174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */ +#define REG_PWM_CMPM4 (0xF002C178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */ +#define REG_PWM_CMPMUPD4 (0xF002C17CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */ +#define REG_PWM_CMPV5 (0xF002C180U) /**< \brief (PWM) PWM Comparison 5 Value Register */ +#define REG_PWM_CMPVUPD5 (0xF002C184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */ +#define REG_PWM_CMPM5 (0xF002C188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */ +#define REG_PWM_CMPMUPD5 (0xF002C18CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */ +#define REG_PWM_CMPV6 (0xF002C190U) /**< \brief (PWM) PWM Comparison 6 Value Register */ +#define REG_PWM_CMPVUPD6 (0xF002C194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */ +#define REG_PWM_CMPM6 (0xF002C198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */ +#define REG_PWM_CMPMUPD6 (0xF002C19CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */ +#define REG_PWM_CMPV7 (0xF002C1A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */ +#define REG_PWM_CMPVUPD7 (0xF002C1A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */ +#define REG_PWM_CMPM7 (0xF002C1A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */ +#define REG_PWM_CMPMUPD7 (0xF002C1ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */ +#define REG_PWM_CMR0 (0xF002C200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */ +#define REG_PWM_CDTY0 (0xF002C204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */ +#define REG_PWM_CDTYUPD0 (0xF002C208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */ +#define REG_PWM_CPRD0 (0xF002C20CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */ +#define REG_PWM_CPRDUPD0 (0xF002C210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */ +#define REG_PWM_CCNT0 (0xF002C214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */ +#define REG_PWM_DT0 (0xF002C218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */ +#define REG_PWM_DTUPD0 (0xF002C21CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */ +#define REG_PWM_CMR1 (0xF002C220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */ +#define REG_PWM_CDTY1 (0xF002C224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */ +#define REG_PWM_CDTYUPD1 (0xF002C228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */ +#define REG_PWM_CPRD1 (0xF002C22CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */ +#define REG_PWM_CPRDUPD1 (0xF002C230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */ +#define REG_PWM_CCNT1 (0xF002C234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */ +#define REG_PWM_DT1 (0xF002C238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */ +#define REG_PWM_DTUPD1 (0xF002C23CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */ +#define REG_PWM_CMR2 (0xF002C240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */ +#define REG_PWM_CDTY2 (0xF002C244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */ +#define REG_PWM_CDTYUPD2 (0xF002C248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */ +#define REG_PWM_CPRD2 (0xF002C24CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */ +#define REG_PWM_CPRDUPD2 (0xF002C250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */ +#define REG_PWM_CCNT2 (0xF002C254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */ +#define REG_PWM_DT2 (0xF002C258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */ +#define REG_PWM_DTUPD2 (0xF002C25CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */ +#define REG_PWM_CMR3 (0xF002C260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */ +#define REG_PWM_CDTY3 (0xF002C264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */ +#define REG_PWM_CDTYUPD3 (0xF002C268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */ +#define REG_PWM_CPRD3 (0xF002C26CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */ +#define REG_PWM_CPRDUPD3 (0xF002C270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */ +#define REG_PWM_CCNT3 (0xF002C274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */ +#define REG_PWM_DT3 (0xF002C278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */ +#define REG_PWM_DTUPD3 (0xF002C27CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */ +#define REG_PWM_CMUPD0 (0xF002C400U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 0) */ +#define REG_PWM_CMUPD1 (0xF002C420U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 1) */ +#define REG_PWM_CMUPD2 (0xF002C440U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 2) */ +#define REG_PWM_CMUPD3 (0xF002C460U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 3) */ +#else +#define REG_PWM_CLK (*(RwReg*)0xF002C000U) /**< \brief (PWM) PWM Clock Register */ +#define REG_PWM_ENA (*(WoReg*)0xF002C004U) /**< \brief (PWM) PWM Enable Register */ +#define REG_PWM_DIS (*(WoReg*)0xF002C008U) /**< \brief (PWM) PWM Disable Register */ +#define REG_PWM_SR (*(RoReg*)0xF002C00CU) /**< \brief (PWM) PWM Status Register */ +#define REG_PWM_IER1 (*(WoReg*)0xF002C010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */ +#define REG_PWM_IDR1 (*(WoReg*)0xF002C014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */ +#define REG_PWM_IMR1 (*(RoReg*)0xF002C018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */ +#define REG_PWM_ISR1 (*(RoReg*)0xF002C01CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */ +#define REG_PWM_SCM (*(RwReg*)0xF002C020U) /**< \brief (PWM) PWM Sync Channels Mode Register */ +#define REG_PWM_SCUC (*(RwReg*)0xF002C028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */ +#define REG_PWM_SCUP (*(RwReg*)0xF002C02CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */ +#define REG_PWM_SCUPUPD (*(WoReg*)0xF002C030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */ +#define REG_PWM_IER2 (*(WoReg*)0xF002C034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */ +#define REG_PWM_IDR2 (*(WoReg*)0xF002C038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */ +#define REG_PWM_IMR2 (*(RoReg*)0xF002C03CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */ +#define REG_PWM_ISR2 (*(RoReg*)0xF002C040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */ +#define REG_PWM_OOV (*(RwReg*)0xF002C044U) /**< \brief (PWM) PWM Output Override Value Register */ +#define REG_PWM_OS (*(RwReg*)0xF002C048U) /**< \brief (PWM) PWM Output Selection Register */ +#define REG_PWM_OSS (*(WoReg*)0xF002C04CU) /**< \brief (PWM) PWM Output Selection Set Register */ +#define REG_PWM_OSC (*(WoReg*)0xF002C050U) /**< \brief (PWM) PWM Output Selection Clear Register */ +#define REG_PWM_OSSUPD (*(WoReg*)0xF002C054U) /**< \brief (PWM) PWM Output Selection Set Update Register */ +#define REG_PWM_OSCUPD (*(WoReg*)0xF002C058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */ +#define REG_PWM_FMR (*(RwReg*)0xF002C05CU) /**< \brief (PWM) PWM Fault Mode Register */ +#define REG_PWM_FSR (*(RoReg*)0xF002C060U) /**< \brief (PWM) PWM Fault Status Register */ +#define REG_PWM_FCR (*(WoReg*)0xF002C064U) /**< \brief (PWM) PWM Fault Clear Register */ +#define REG_PWM_FPV1 (*(RwReg*)0xF002C068U) /**< \brief (PWM) PWM Fault Protection Value Register 1 */ +#define REG_PWM_FPE (*(RwReg*)0xF002C06CU) /**< \brief (PWM) PWM Fault Protection Enable Register */ +#define REG_PWM_ELMR (*(RwReg*)0xF002C07CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */ +#define REG_PWM_FPV2 (*(RwReg*)0xF002C0C0U) /**< \brief (PWM) PWM Fault Protection Value 2 Register */ +#define REG_PWM_WPCR (*(WoReg*)0xF002C0E4U) /**< \brief (PWM) PWM Write Protect Control Register */ +#define REG_PWM_WPSR (*(RoReg*)0xF002C0E8U) /**< \brief (PWM) PWM Write Protect Status Register */ +#define REG_PWM_CMPV0 (*(RwReg*)0xF002C130U) /**< \brief (PWM) PWM Comparison 0 Value Register */ +#define REG_PWM_CMPVUPD0 (*(WoReg*)0xF002C134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */ +#define REG_PWM_CMPM0 (*(RwReg*)0xF002C138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */ +#define REG_PWM_CMPMUPD0 (*(WoReg*)0xF002C13CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */ +#define REG_PWM_CMPV1 (*(RwReg*)0xF002C140U) /**< \brief (PWM) PWM Comparison 1 Value Register */ +#define REG_PWM_CMPVUPD1 (*(WoReg*)0xF002C144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */ +#define REG_PWM_CMPM1 (*(RwReg*)0xF002C148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */ +#define REG_PWM_CMPMUPD1 (*(WoReg*)0xF002C14CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */ +#define REG_PWM_CMPV2 (*(RwReg*)0xF002C150U) /**< \brief (PWM) PWM Comparison 2 Value Register */ +#define REG_PWM_CMPVUPD2 (*(WoReg*)0xF002C154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */ +#define REG_PWM_CMPM2 (*(RwReg*)0xF002C158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */ +#define REG_PWM_CMPMUPD2 (*(WoReg*)0xF002C15CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */ +#define REG_PWM_CMPV3 (*(RwReg*)0xF002C160U) /**< \brief (PWM) PWM Comparison 3 Value Register */ +#define REG_PWM_CMPVUPD3 (*(WoReg*)0xF002C164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */ +#define REG_PWM_CMPM3 (*(RwReg*)0xF002C168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */ +#define REG_PWM_CMPMUPD3 (*(WoReg*)0xF002C16CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */ +#define REG_PWM_CMPV4 (*(RwReg*)0xF002C170U) /**< \brief (PWM) PWM Comparison 4 Value Register */ +#define REG_PWM_CMPVUPD4 (*(WoReg*)0xF002C174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */ +#define REG_PWM_CMPM4 (*(RwReg*)0xF002C178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */ +#define REG_PWM_CMPMUPD4 (*(WoReg*)0xF002C17CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */ +#define REG_PWM_CMPV5 (*(RwReg*)0xF002C180U) /**< \brief (PWM) PWM Comparison 5 Value Register */ +#define REG_PWM_CMPVUPD5 (*(WoReg*)0xF002C184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */ +#define REG_PWM_CMPM5 (*(RwReg*)0xF002C188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */ +#define REG_PWM_CMPMUPD5 (*(WoReg*)0xF002C18CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */ +#define REG_PWM_CMPV6 (*(RwReg*)0xF002C190U) /**< \brief (PWM) PWM Comparison 6 Value Register */ +#define REG_PWM_CMPVUPD6 (*(WoReg*)0xF002C194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */ +#define REG_PWM_CMPM6 (*(RwReg*)0xF002C198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */ +#define REG_PWM_CMPMUPD6 (*(WoReg*)0xF002C19CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */ +#define REG_PWM_CMPV7 (*(RwReg*)0xF002C1A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */ +#define REG_PWM_CMPVUPD7 (*(WoReg*)0xF002C1A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */ +#define REG_PWM_CMPM7 (*(RwReg*)0xF002C1A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */ +#define REG_PWM_CMPMUPD7 (*(WoReg*)0xF002C1ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */ +#define REG_PWM_CMR0 (*(RwReg*)0xF002C200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */ +#define REG_PWM_CDTY0 (*(RwReg*)0xF002C204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */ +#define REG_PWM_CDTYUPD0 (*(WoReg*)0xF002C208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */ +#define REG_PWM_CPRD0 (*(RwReg*)0xF002C20CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */ +#define REG_PWM_CPRDUPD0 (*(WoReg*)0xF002C210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */ +#define REG_PWM_CCNT0 (*(RoReg*)0xF002C214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */ +#define REG_PWM_DT0 (*(RwReg*)0xF002C218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */ +#define REG_PWM_DTUPD0 (*(WoReg*)0xF002C21CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */ +#define REG_PWM_CMR1 (*(RwReg*)0xF002C220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */ +#define REG_PWM_CDTY1 (*(RwReg*)0xF002C224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */ +#define REG_PWM_CDTYUPD1 (*(WoReg*)0xF002C228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */ +#define REG_PWM_CPRD1 (*(RwReg*)0xF002C22CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */ +#define REG_PWM_CPRDUPD1 (*(WoReg*)0xF002C230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */ +#define REG_PWM_CCNT1 (*(RoReg*)0xF002C234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */ +#define REG_PWM_DT1 (*(RwReg*)0xF002C238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */ +#define REG_PWM_DTUPD1 (*(WoReg*)0xF002C23CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */ +#define REG_PWM_CMR2 (*(RwReg*)0xF002C240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */ +#define REG_PWM_CDTY2 (*(RwReg*)0xF002C244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */ +#define REG_PWM_CDTYUPD2 (*(WoReg*)0xF002C248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */ +#define REG_PWM_CPRD2 (*(RwReg*)0xF002C24CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */ +#define REG_PWM_CPRDUPD2 (*(WoReg*)0xF002C250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */ +#define REG_PWM_CCNT2 (*(RoReg*)0xF002C254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */ +#define REG_PWM_DT2 (*(RwReg*)0xF002C258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */ +#define REG_PWM_DTUPD2 (*(WoReg*)0xF002C25CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */ +#define REG_PWM_CMR3 (*(RwReg*)0xF002C260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */ +#define REG_PWM_CDTY3 (*(RwReg*)0xF002C264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */ +#define REG_PWM_CDTYUPD3 (*(WoReg*)0xF002C268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */ +#define REG_PWM_CPRD3 (*(RwReg*)0xF002C26CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */ +#define REG_PWM_CPRDUPD3 (*(WoReg*)0xF002C270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */ +#define REG_PWM_CCNT3 (*(RoReg*)0xF002C274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */ +#define REG_PWM_DT3 (*(RwReg*)0xF002C278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */ +#define REG_PWM_DTUPD3 (*(WoReg*)0xF002C27CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */ +#define REG_PWM_CMUPD0 (*(WoReg*)0xF002C400U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 0) */ +#define REG_PWM_CMUPD1 (*(WoReg*)0xF002C420U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 1) */ +#define REG_PWM_CMUPD2 (*(WoReg*)0xF002C440U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 2) */ +#define REG_PWM_CMUPD3 (*(WoReg*)0xF002C460U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 3) */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_PWM_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_rstc.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_rstc.h new file mode 100644 index 0000000..098e424 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_rstc.h
@@ -0,0 +1,44 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_RSTC_INSTANCE_ +#define _SAMA5_RSTC_INSTANCE_ + +/* ========== Register definition for RSTC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_RSTC_CR (0xFFFFFE00U) /**< \brief (RSTC) Control Register */ +#define REG_RSTC_SR (0xFFFFFE04U) /**< \brief (RSTC) Status Register */ +#define REG_RSTC_MR (0xFFFFFE08U) /**< \brief (RSTC) Mode Register */ +#else +#define REG_RSTC_CR (*(WoReg*)0xFFFFFE00U) /**< \brief (RSTC) Control Register */ +#define REG_RSTC_SR (*(RoReg*)0xFFFFFE04U) /**< \brief (RSTC) Status Register */ +#define REG_RSTC_MR (*(RwReg*)0xFFFFFE08U) /**< \brief (RSTC) Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_RSTC_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_rtc.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_rtc.h new file mode 100644 index 0000000..b1507a7 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_rtc.h
@@ -0,0 +1,62 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_RTC_INSTANCE_ +#define _SAMA5_RTC_INSTANCE_ + +/* ========== Register definition for RTC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_RTC_CR (0xFFFFFEB0U) /**< \brief (RTC) Control Register */ +#define REG_RTC_MR (0xFFFFFEB4U) /**< \brief (RTC) Mode Register */ +#define REG_RTC_TIMR (0xFFFFFEB8U) /**< \brief (RTC) Time Register */ +#define REG_RTC_CALR (0xFFFFFEBCU) /**< \brief (RTC) Calendar Register */ +#define REG_RTC_TIMALR (0xFFFFFEC0U) /**< \brief (RTC) Time Alarm Register */ +#define REG_RTC_CALALR (0xFFFFFEC4U) /**< \brief (RTC) Calendar Alarm Register */ +#define REG_RTC_SR (0xFFFFFEC8U) /**< \brief (RTC) Status Register */ +#define REG_RTC_SCCR (0xFFFFFECCU) /**< \brief (RTC) Status Clear Command Register */ +#define REG_RTC_IER (0xFFFFFED0U) /**< \brief (RTC) Interrupt Enable Register */ +#define REG_RTC_IDR (0xFFFFFED4U) /**< \brief (RTC) Interrupt Disable Register */ +#define REG_RTC_IMR (0xFFFFFED8U) /**< \brief (RTC) Interrupt Mask Register */ +#define REG_RTC_VER (0xFFFFFEDCU) /**< \brief (RTC) Valid Entry Register */ +#else +#define REG_RTC_CR (*(RwReg*)0xFFFFFEB0U) /**< \brief (RTC) Control Register */ +#define REG_RTC_MR (*(RwReg*)0xFFFFFEB4U) /**< \brief (RTC) Mode Register */ +#define REG_RTC_TIMR (*(RwReg*)0xFFFFFEB8U) /**< \brief (RTC) Time Register */ +#define REG_RTC_CALR (*(RwReg*)0xFFFFFEBCU) /**< \brief (RTC) Calendar Register */ +#define REG_RTC_TIMALR (*(RwReg*)0xFFFFFEC0U) /**< \brief (RTC) Time Alarm Register */ +#define REG_RTC_CALALR (*(RwReg*)0xFFFFFEC4U) /**< \brief (RTC) Calendar Alarm Register */ +#define REG_RTC_SR (*(RoReg*)0xFFFFFEC8U) /**< \brief (RTC) Status Register */ +#define REG_RTC_SCCR (*(WoReg*)0xFFFFFECCU) /**< \brief (RTC) Status Clear Command Register */ +#define REG_RTC_IER (*(WoReg*)0xFFFFFED0U) /**< \brief (RTC) Interrupt Enable Register */ +#define REG_RTC_IDR (*(WoReg*)0xFFFFFED4U) /**< \brief (RTC) Interrupt Disable Register */ +#define REG_RTC_IMR (*(RoReg*)0xFFFFFED8U) /**< \brief (RTC) Interrupt Mask Register */ +#define REG_RTC_VER (*(RoReg*)0xFFFFFEDCU) /**< \brief (RTC) Valid Entry Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_RTC_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_sckc.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_sckc.h new file mode 100644 index 0000000..6f8b852 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_sckc.h
@@ -0,0 +1,40 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_SCKC_INSTANCE_ +#define _SAMA5_SCKC_INSTANCE_ + +/* ========== Register definition for SCKC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SCKC_CR (0xFFFFFE50U) /**< \brief (SCKC) Slow Clock Configuration Register */ +#else +#define REG_SCKC_CR (*(RwReg*)0xFFFFFE50U) /**< \brief (SCKC) Slow Clock Configuration Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_SCKC_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_sfr.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_sfr.h new file mode 100644 index 0000000..5639ecd --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_sfr.h
@@ -0,0 +1,58 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_SFR_INSTANCE_ +#define _SAMA5_SFR_INSTANCE_ + +/* ========== Register definition for SFR peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SFR_OHCIICR (0xF0038010U) /**< \brief (SFR) OHCI Interrupt Configuration Register */ +#define REG_SFR_OHCIISR (0xF0038014U) /**< \brief (SFR) OHCI Interrupt Status Register */ +#define REG_SFR_AHB (0xF0038020U) /**< \brief (SFR) AHB Configuration Register */ +#define REG_SFR_BRIDGE (0xF0038024U) /**< \brief (SFR) Bridge Configuration Register */ +#define REG_SFR_SECURE (0xF0038028U) /**< \brief (SFR) Security Configuration Register */ +#define REG_SFR_UTMICKTRIM (0xF0038030U) /**< \brief (SFR) UTMI Clock Trimming Register */ +#define REG_SFR_UTMIHSTRIM (0xF0038034U) /**< \brief (SFR) UTMI High Speed Trimming Register */ +#define REG_SFR_UTMIFSTRIM (0xF0038038U) /**< \brief (SFR) UTMI Full Speed Trimming Register */ +#define REG_SFR_UTMISWAP (0xF003803CU) /**< \brief (SFR) UTMI DP/DM Pin Swapping Register */ +#define REG_SFR_EBICFG (0xF0038040U) /**< \brief (SFR) EBI Configuration Register */ +#else +#define REG_SFR_OHCIICR (*(RwReg*)0xF0038010U) /**< \brief (SFR) OHCI Interrupt Configuration Register */ +#define REG_SFR_OHCIISR (*(RoReg*)0xF0038014U) /**< \brief (SFR) OHCI Interrupt Status Register */ +#define REG_SFR_AHB (*(RwReg*)0xF0038020U) /**< \brief (SFR) AHB Configuration Register */ +#define REG_SFR_BRIDGE (*(RwReg*)0xF0038024U) /**< \brief (SFR) Bridge Configuration Register */ +#define REG_SFR_SECURE (*(RwReg*)0xF0038028U) /**< \brief (SFR) Security Configuration Register */ +#define REG_SFR_UTMICKTRIM (*(RwReg*)0xF0038030U) /**< \brief (SFR) UTMI Clock Trimming Register */ +#define REG_SFR_UTMIHSTRIM (*(RwReg*)0xF0038034U) /**< \brief (SFR) UTMI High Speed Trimming Register */ +#define REG_SFR_UTMIFSTRIM (*(RwReg*)0xF0038038U) /**< \brief (SFR) UTMI Full Speed Trimming Register */ +#define REG_SFR_UTMISWAP (*(RwReg*)0xF003803CU) /**< \brief (SFR) UTMI DP/DM Pin Swapping Register */ +#define REG_SFR_EBICFG (*(RwReg*)0xF0038040U) /**< \brief (SFR) EBI Configuration Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_SFR_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_sha.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_sha.h new file mode 100644 index 0000000..15346be --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_sha.h
@@ -0,0 +1,54 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_SHA_INSTANCE_ +#define _SAMA5_SHA_INSTANCE_ + +/* ========== Register definition for SHA peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SHA_CR (0xF8034000U) /**< \brief (SHA) Control Register */ +#define REG_SHA_MR (0xF8034004U) /**< \brief (SHA) Mode Register */ +#define REG_SHA_IER (0xF8034010U) /**< \brief (SHA) Interrupt Enable Register */ +#define REG_SHA_IDR (0xF8034014U) /**< \brief (SHA) Interrupt Disable Register */ +#define REG_SHA_IMR (0xF8034018U) /**< \brief (SHA) Interrupt Mask Register */ +#define REG_SHA_ISR (0xF803401CU) /**< \brief (SHA) Interrupt Status Register */ +#define REG_SHA_IDATAR (0xF8034040U) /**< \brief (SHA) Input Data 0 Register */ +#define REG_SHA_IODATAR (0xF8034080U) /**< \brief (SHA) Input/Output Data 0 Register */ +#else +#define REG_SHA_CR (*(WoReg*)0xF8034000U) /**< \brief (SHA) Control Register */ +#define REG_SHA_MR (*(RwReg*)0xF8034004U) /**< \brief (SHA) Mode Register */ +#define REG_SHA_IER (*(WoReg*)0xF8034010U) /**< \brief (SHA) Interrupt Enable Register */ +#define REG_SHA_IDR (*(WoReg*)0xF8034014U) /**< \brief (SHA) Interrupt Disable Register */ +#define REG_SHA_IMR (*(RoReg*)0xF8034018U) /**< \brief (SHA) Interrupt Mask Register */ +#define REG_SHA_ISR (*(RoReg*)0xF803401CU) /**< \brief (SHA) Interrupt Status Register */ +#define REG_SHA_IDATAR (*(WoReg*)0xF8034040U) /**< \brief (SHA) Input Data 0 Register */ +#define REG_SHA_IODATAR (*(RwReg*)0xF8034080U) /**< \brief (SHA) Input/Output Data 0 Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_SHA_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_shdwc.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_shdwc.h new file mode 100644 index 0000000..001623e --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_shdwc.h
@@ -0,0 +1,44 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_SHDWC_INSTANCE_ +#define _SAMA5_SHDWC_INSTANCE_ + +/* ========== Register definition for SHDWC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SHDWC_CR (0xFFFFFE10U) /**< \brief (SHDWC) Shutdown Control Register */ +#define REG_SHDWC_MR (0xFFFFFE14U) /**< \brief (SHDWC) Shutdown Mode Register */ +#define REG_SHDWC_SR (0xFFFFFE18U) /**< \brief (SHDWC) Shutdown Status Register */ +#else +#define REG_SHDWC_CR (*(WoReg*)0xFFFFFE10U) /**< \brief (SHDWC) Shutdown Control Register */ +#define REG_SHDWC_MR (*(RwReg*)0xFFFFFE14U) /**< \brief (SHDWC) Shutdown Mode Register */ +#define REG_SHDWC_SR (*(RoReg*)0xFFFFFE18U) /**< \brief (SHDWC) Shutdown Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_SHDWC_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_smc.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_smc.h new file mode 100644 index 0000000..3e6a881 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_smc.h
@@ -0,0 +1,602 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_SMC_INSTANCE_ +#define _SAMA5_SMC_INSTANCE_ + +/* ========== Register definition for SMC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SMC_CFG (0xFFFFC000U) /**< \brief (SMC) SMC NFC Configuration Register */ +#define REG_SMC_CTRL (0xFFFFC004U) /**< \brief (SMC) SMC NFC Control Register */ +#define REG_SMC_SR (0xFFFFC008U) /**< \brief (SMC) SMC NFC Status Register */ +#define REG_SMC_IER (0xFFFFC00CU) /**< \brief (SMC) SMC NFC Interrupt Enable Register */ +#define REG_SMC_IDR (0xFFFFC010U) /**< \brief (SMC) SMC NFC Interrupt Disable Register */ +#define REG_SMC_IMR (0xFFFFC014U) /**< \brief (SMC) SMC NFC Interrupt Mask Register */ +#define REG_SMC_ADDR (0xFFFFC018U) /**< \brief (SMC) SMC NFC Address Cycle Zero Register */ +#define REG_SMC_BANK (0xFFFFC01CU) /**< \brief (SMC) SMC Bank Address Register */ +#define REG_SMC_ECC_CTRL (0xFFFFC020U) /**< \brief (SMC) SMC ECC Control Register */ +#define REG_SMC_ECC_MD (0xFFFFC024U) /**< \brief (SMC) SMC ECC Mode Register */ +#define REG_SMC_ECC_SR1 (0xFFFFC028U) /**< \brief (SMC) SMC ECC Status 1 Register */ +#define REG_SMC_ECC_PR0 (0xFFFFC02CU) /**< \brief (SMC) SMC ECC Parity 0 Register */ +#define REG_SMC_ECC_PR1 (0xFFFFC030U) /**< \brief (SMC) SMC ECC parity 1 Register */ +#define REG_SMC_ECC_SR2 (0xFFFFC034U) /**< \brief (SMC) SMC ECC status 2 Register */ +#define REG_SMC_ECC_PR2 (0xFFFFC038U) /**< \brief (SMC) SMC ECC parity 2 Register */ +#define REG_SMC_ECC_PR3 (0xFFFFC03CU) /**< \brief (SMC) SMC ECC parity 3 Register */ +#define REG_SMC_ECC_PR4 (0xFFFFC040U) /**< \brief (SMC) SMC ECC parity 4 Register */ +#define REG_SMC_ECC_PR5 (0xFFFFC044U) /**< \brief (SMC) SMC ECC parity 5 Register */ +#define REG_SMC_ECC_PR6 (0xFFFFC048U) /**< \brief (SMC) SMC ECC parity 6 Register */ +#define REG_SMC_ECC_PR7 (0xFFFFC04CU) /**< \brief (SMC) SMC ECC parity 7 Register */ +#define REG_SMC_ECC_PR8 (0xFFFFC050U) /**< \brief (SMC) SMC ECC parity 8 Register */ +#define REG_SMC_ECC_PR9 (0xFFFFC054U) /**< \brief (SMC) SMC ECC parity 9 Register */ +#define REG_SMC_ECC_PR10 (0xFFFFC058U) /**< \brief (SMC) SMC ECC parity 10 Register */ +#define REG_SMC_ECC_PR11 (0xFFFFC05CU) /**< \brief (SMC) SMC ECC parity 11 Register */ +#define REG_SMC_ECC_PR12 (0xFFFFC060U) /**< \brief (SMC) SMC ECC parity 12 Register */ +#define REG_SMC_ECC_PR13 (0xFFFFC064U) /**< \brief (SMC) SMC ECC parity 13 Register */ +#define REG_SMC_ECC_PR14 (0xFFFFC068U) /**< \brief (SMC) SMC ECC parity 14 Register */ +#define REG_SMC_ECC_PR15 (0xFFFFC06CU) /**< \brief (SMC) SMC ECC parity 15 Register */ +#define REG_SMC_PMECCFG (0xFFFFC070U) /**< \brief (SMC) PMECC Configuration Register */ +#define REG_SMC_PMECCSAREA (0xFFFFC074U) /**< \brief (SMC) PMECC Spare Area Size Register */ +#define REG_SMC_PMECCSADDR (0xFFFFC078U) /**< \brief (SMC) PMECC Start Address Register */ +#define REG_SMC_PMECCEADDR (0xFFFFC07CU) /**< \brief (SMC) PMECC End Address Register */ +#define REG_SMC_PMECCTRL (0xFFFFC084U) /**< \brief (SMC) PMECC Control Register */ +#define REG_SMC_PMECCSR (0xFFFFC088U) /**< \brief (SMC) PMECC Status Register */ +#define REG_SMC_PMECCIER (0xFFFFC08CU) /**< \brief (SMC) PMECC Interrupt Enable register */ +#define REG_SMC_PMECCIDR (0xFFFFC090U) /**< \brief (SMC) PMECC Interrupt Disable Register */ +#define REG_SMC_PMECCIMR (0xFFFFC094U) /**< \brief (SMC) PMECC Interrupt Mask Register */ +#define REG_SMC_PMECCISR (0xFFFFC098U) /**< \brief (SMC) PMECC Interrupt Status Register */ +#define REG_SMC_PMECC0_0 (0xFFFFC0B0U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 0) */ +#define REG_SMC_PMECC1_0 (0xFFFFC0B4U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 0) */ +#define REG_SMC_PMECC2_0 (0xFFFFC0B8U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 0) */ +#define REG_SMC_PMECC3_0 (0xFFFFC0BCU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 0) */ +#define REG_SMC_PMECC4_0 (0xFFFFC0C0U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 0) */ +#define REG_SMC_PMECC5_0 (0xFFFFC0C4U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 0) */ +#define REG_SMC_PMECC6_0 (0xFFFFC0C8U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 0) */ +#define REG_SMC_PMECC7_0 (0xFFFFC0CCU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 0) */ +#define REG_SMC_PMECC8_0 (0xFFFFC0D0U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 0) */ +#define REG_SMC_PMECC9_0 (0xFFFFC0D4U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 0) */ +#define REG_SMC_PMECC10_0 (0xFFFFC0D8U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 0) */ +#define REG_SMC_PMECC0_1 (0xFFFFC0F0U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 1) */ +#define REG_SMC_PMECC1_1 (0xFFFFC0F4U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 1) */ +#define REG_SMC_PMECC2_1 (0xFFFFC0F8U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 1) */ +#define REG_SMC_PMECC3_1 (0xFFFFC0FCU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 1) */ +#define REG_SMC_PMECC4_1 (0xFFFFC100U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 1) */ +#define REG_SMC_PMECC5_1 (0xFFFFC104U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 1) */ +#define REG_SMC_PMECC6_1 (0xFFFFC108U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 1) */ +#define REG_SMC_PMECC7_1 (0xFFFFC10CU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 1) */ +#define REG_SMC_PMECC8_1 (0xFFFFC110U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 1) */ +#define REG_SMC_PMECC9_1 (0xFFFFC114U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 1) */ +#define REG_SMC_PMECC10_1 (0xFFFFC118U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 1) */ +#define REG_SMC_PMECC0_2 (0xFFFFC130U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 2) */ +#define REG_SMC_PMECC1_2 (0xFFFFC134U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 2) */ +#define REG_SMC_PMECC2_2 (0xFFFFC138U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 2) */ +#define REG_SMC_PMECC3_2 (0xFFFFC13CU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 2) */ +#define REG_SMC_PMECC4_2 (0xFFFFC140U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 2) */ +#define REG_SMC_PMECC5_2 (0xFFFFC144U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 2) */ +#define REG_SMC_PMECC6_2 (0xFFFFC148U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 2) */ +#define REG_SMC_PMECC7_2 (0xFFFFC14CU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 2) */ +#define REG_SMC_PMECC8_2 (0xFFFFC150U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 2) */ +#define REG_SMC_PMECC9_2 (0xFFFFC154U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 2) */ +#define REG_SMC_PMECC10_2 (0xFFFFC158U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 2) */ +#define REG_SMC_PMECC0_3 (0xFFFFC170U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 3) */ +#define REG_SMC_PMECC1_3 (0xFFFFC174U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 3) */ +#define REG_SMC_PMECC2_3 (0xFFFFC178U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 3) */ +#define REG_SMC_PMECC3_3 (0xFFFFC17CU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 3) */ +#define REG_SMC_PMECC4_3 (0xFFFFC180U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 3) */ +#define REG_SMC_PMECC5_3 (0xFFFFC184U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 3) */ +#define REG_SMC_PMECC6_3 (0xFFFFC188U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 3) */ +#define REG_SMC_PMECC7_3 (0xFFFFC18CU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 3) */ +#define REG_SMC_PMECC8_3 (0xFFFFC190U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 3) */ +#define REG_SMC_PMECC9_3 (0xFFFFC194U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 3) */ +#define REG_SMC_PMECC10_3 (0xFFFFC198U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 3) */ +#define REG_SMC_PMECC0_4 (0xFFFFC1B0U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 4) */ +#define REG_SMC_PMECC1_4 (0xFFFFC1B4U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 4) */ +#define REG_SMC_PMECC2_4 (0xFFFFC1B8U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 4) */ +#define REG_SMC_PMECC3_4 (0xFFFFC1BCU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 4) */ +#define REG_SMC_PMECC4_4 (0xFFFFC1C0U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 4) */ +#define REG_SMC_PMECC5_4 (0xFFFFC1C4U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 4) */ +#define REG_SMC_PMECC6_4 (0xFFFFC1C8U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 4) */ +#define REG_SMC_PMECC7_4 (0xFFFFC1CCU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 4) */ +#define REG_SMC_PMECC8_4 (0xFFFFC1D0U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 4) */ +#define REG_SMC_PMECC9_4 (0xFFFFC1D4U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 4) */ +#define REG_SMC_PMECC10_4 (0xFFFFC1D8U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 4) */ +#define REG_SMC_PMECC0_5 (0xFFFFC1F0U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 5) */ +#define REG_SMC_PMECC1_5 (0xFFFFC1F4U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 5) */ +#define REG_SMC_PMECC2_5 (0xFFFFC1F8U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 5) */ +#define REG_SMC_PMECC3_5 (0xFFFFC1FCU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 5) */ +#define REG_SMC_PMECC4_5 (0xFFFFC200U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 5) */ +#define REG_SMC_PMECC5_5 (0xFFFFC204U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 5) */ +#define REG_SMC_PMECC6_5 (0xFFFFC208U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 5) */ +#define REG_SMC_PMECC7_5 (0xFFFFC20CU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 5) */ +#define REG_SMC_PMECC8_5 (0xFFFFC210U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 5) */ +#define REG_SMC_PMECC9_5 (0xFFFFC214U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 5) */ +#define REG_SMC_PMECC10_5 (0xFFFFC218U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 5) */ +#define REG_SMC_PMECC0_6 (0xFFFFC230U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 6) */ +#define REG_SMC_PMECC1_6 (0xFFFFC234U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 6) */ +#define REG_SMC_PMECC2_6 (0xFFFFC238U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 6) */ +#define REG_SMC_PMECC3_6 (0xFFFFC23CU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 6) */ +#define REG_SMC_PMECC4_6 (0xFFFFC240U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 6) */ +#define REG_SMC_PMECC5_6 (0xFFFFC244U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 6) */ +#define REG_SMC_PMECC6_6 (0xFFFFC248U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 6) */ +#define REG_SMC_PMECC7_6 (0xFFFFC24CU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 6) */ +#define REG_SMC_PMECC8_6 (0xFFFFC250U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 6) */ +#define REG_SMC_PMECC9_6 (0xFFFFC254U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 6) */ +#define REG_SMC_PMECC10_6 (0xFFFFC258U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 6) */ +#define REG_SMC_PMECC0_7 (0xFFFFC270U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 7) */ +#define REG_SMC_PMECC1_7 (0xFFFFC274U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 7) */ +#define REG_SMC_PMECC2_7 (0xFFFFC278U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 7) */ +#define REG_SMC_PMECC3_7 (0xFFFFC27CU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 7) */ +#define REG_SMC_PMECC4_7 (0xFFFFC280U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 7) */ +#define REG_SMC_PMECC5_7 (0xFFFFC284U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 7) */ +#define REG_SMC_PMECC6_7 (0xFFFFC288U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 7) */ +#define REG_SMC_PMECC7_7 (0xFFFFC28CU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 7) */ +#define REG_SMC_PMECC8_7 (0xFFFFC290U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 7) */ +#define REG_SMC_PMECC9_7 (0xFFFFC294U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 7) */ +#define REG_SMC_PMECC10_7 (0xFFFFC298U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 7) */ +#define REG_SMC_REM0_0 (0xFFFFC2B0U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 0) */ +#define REG_SMC_REM1_0 (0xFFFFC2B4U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 0) */ +#define REG_SMC_REM2_0 (0xFFFFC2B8U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 0) */ +#define REG_SMC_REM3_0 (0xFFFFC2BCU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 0) */ +#define REG_SMC_REM4_0 (0xFFFFC2C0U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 0) */ +#define REG_SMC_REM5_0 (0xFFFFC2C4U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 0) */ +#define REG_SMC_REM6_0 (0xFFFFC2C8U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 0) */ +#define REG_SMC_REM7_0 (0xFFFFC2CCU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 0) */ +#define REG_SMC_REM8_0 (0xFFFFC2D0U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 0) */ +#define REG_SMC_REM9_0 (0xFFFFC2D4U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 0) */ +#define REG_SMC_REM10_0 (0xFFFFC2D8U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 0) */ +#define REG_SMC_REM11_0 (0xFFFFC2DCU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 0) */ +#define REG_SMC_REM0_1 (0xFFFFC2F0U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 1) */ +#define REG_SMC_REM1_1 (0xFFFFC2F4U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 1) */ +#define REG_SMC_REM2_1 (0xFFFFC2F8U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 1) */ +#define REG_SMC_REM3_1 (0xFFFFC2FCU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 1) */ +#define REG_SMC_REM4_1 (0xFFFFC300U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 1) */ +#define REG_SMC_REM5_1 (0xFFFFC304U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 1) */ +#define REG_SMC_REM6_1 (0xFFFFC308U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 1) */ +#define REG_SMC_REM7_1 (0xFFFFC30CU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 1) */ +#define REG_SMC_REM8_1 (0xFFFFC310U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 1) */ +#define REG_SMC_REM9_1 (0xFFFFC314U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 1) */ +#define REG_SMC_REM10_1 (0xFFFFC318U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 1) */ +#define REG_SMC_REM11_1 (0xFFFFC31CU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 1) */ +#define REG_SMC_REM0_2 (0xFFFFC330U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 2) */ +#define REG_SMC_REM1_2 (0xFFFFC334U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 2) */ +#define REG_SMC_REM2_2 (0xFFFFC338U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 2) */ +#define REG_SMC_REM3_2 (0xFFFFC33CU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 2) */ +#define REG_SMC_REM4_2 (0xFFFFC340U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 2) */ +#define REG_SMC_REM5_2 (0xFFFFC344U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 2) */ +#define REG_SMC_REM6_2 (0xFFFFC348U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 2) */ +#define REG_SMC_REM7_2 (0xFFFFC34CU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 2) */ +#define REG_SMC_REM8_2 (0xFFFFC350U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 2) */ +#define REG_SMC_REM9_2 (0xFFFFC354U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 2) */ +#define REG_SMC_REM10_2 (0xFFFFC358U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 2) */ +#define REG_SMC_REM11_2 (0xFFFFC35CU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 2) */ +#define REG_SMC_REM0_3 (0xFFFFC370U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 3) */ +#define REG_SMC_REM1_3 (0xFFFFC374U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 3) */ +#define REG_SMC_REM2_3 (0xFFFFC378U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 3) */ +#define REG_SMC_REM3_3 (0xFFFFC37CU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 3) */ +#define REG_SMC_REM4_3 (0xFFFFC380U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 3) */ +#define REG_SMC_REM5_3 (0xFFFFC384U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 3) */ +#define REG_SMC_REM6_3 (0xFFFFC388U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 3) */ +#define REG_SMC_REM7_3 (0xFFFFC38CU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 3) */ +#define REG_SMC_REM8_3 (0xFFFFC390U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 3) */ +#define REG_SMC_REM9_3 (0xFFFFC394U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 3) */ +#define REG_SMC_REM10_3 (0xFFFFC398U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 3) */ +#define REG_SMC_REM11_3 (0xFFFFC39CU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 3) */ +#define REG_SMC_REM0_4 (0xFFFFC3B0U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 4) */ +#define REG_SMC_REM1_4 (0xFFFFC3B4U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 4) */ +#define REG_SMC_REM2_4 (0xFFFFC3B8U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 4) */ +#define REG_SMC_REM3_4 (0xFFFFC3BCU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 4) */ +#define REG_SMC_REM4_4 (0xFFFFC3C0U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 4) */ +#define REG_SMC_REM5_4 (0xFFFFC3C4U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 4) */ +#define REG_SMC_REM6_4 (0xFFFFC3C8U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 4) */ +#define REG_SMC_REM7_4 (0xFFFFC3CCU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 4) */ +#define REG_SMC_REM8_4 (0xFFFFC3D0U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 4) */ +#define REG_SMC_REM9_4 (0xFFFFC3D4U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 4) */ +#define REG_SMC_REM10_4 (0xFFFFC3D8U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 4) */ +#define REG_SMC_REM11_4 (0xFFFFC3DCU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 4) */ +#define REG_SMC_REM0_5 (0xFFFFC3F0U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 5) */ +#define REG_SMC_REM1_5 (0xFFFFC3F4U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 5) */ +#define REG_SMC_REM2_5 (0xFFFFC3F8U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 5) */ +#define REG_SMC_REM3_5 (0xFFFFC3FCU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 5) */ +#define REG_SMC_REM4_5 (0xFFFFC400U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 5) */ +#define REG_SMC_REM5_5 (0xFFFFC404U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 5) */ +#define REG_SMC_REM6_5 (0xFFFFC408U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 5) */ +#define REG_SMC_REM7_5 (0xFFFFC40CU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 5) */ +#define REG_SMC_REM8_5 (0xFFFFC410U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 5) */ +#define REG_SMC_REM9_5 (0xFFFFC414U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 5) */ +#define REG_SMC_REM10_5 (0xFFFFC418U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 5) */ +#define REG_SMC_REM11_5 (0xFFFFC41CU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 5) */ +#define REG_SMC_REM0_6 (0xFFFFC430U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 6) */ +#define REG_SMC_REM1_6 (0xFFFFC434U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 6) */ +#define REG_SMC_REM2_6 (0xFFFFC438U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 6) */ +#define REG_SMC_REM3_6 (0xFFFFC43CU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 6) */ +#define REG_SMC_REM4_6 (0xFFFFC440U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 6) */ +#define REG_SMC_REM5_6 (0xFFFFC444U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 6) */ +#define REG_SMC_REM6_6 (0xFFFFC448U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 6) */ +#define REG_SMC_REM7_6 (0xFFFFC44CU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 6) */ +#define REG_SMC_REM8_6 (0xFFFFC450U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 6) */ +#define REG_SMC_REM9_6 (0xFFFFC454U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 6) */ +#define REG_SMC_REM10_6 (0xFFFFC458U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 6) */ +#define REG_SMC_REM11_6 (0xFFFFC45CU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 6) */ +#define REG_SMC_REM0_7 (0xFFFFC470U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 7) */ +#define REG_SMC_REM1_7 (0xFFFFC474U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 7) */ +#define REG_SMC_REM2_7 (0xFFFFC478U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 7) */ +#define REG_SMC_REM3_7 (0xFFFFC47CU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 7) */ +#define REG_SMC_REM4_7 (0xFFFFC480U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 7) */ +#define REG_SMC_REM5_7 (0xFFFFC484U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 7) */ +#define REG_SMC_REM6_7 (0xFFFFC488U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 7) */ +#define REG_SMC_REM7_7 (0xFFFFC48CU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 7) */ +#define REG_SMC_REM8_7 (0xFFFFC490U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 7) */ +#define REG_SMC_REM9_7 (0xFFFFC494U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 7) */ +#define REG_SMC_REM10_7 (0xFFFFC498U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 7) */ +#define REG_SMC_REM11_7 (0xFFFFC49CU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 7) */ +#define REG_SMC_ELCFG (0xFFFFC500U) /**< \brief (SMC) PMECC Error Location Configuration Register */ +#define REG_SMC_ELPRIM (0xFFFFC504U) /**< \brief (SMC) PMECC Error Location Primitive Register */ +#define REG_SMC_ELEN (0xFFFFC508U) /**< \brief (SMC) PMECC Error Location Enable Register */ +#define REG_SMC_ELDIS (0xFFFFC50CU) /**< \brief (SMC) PMECC Error Location Disable Register */ +#define REG_SMC_ELSR (0xFFFFC510U) /**< \brief (SMC) PMECC Error Location Status Register */ +#define REG_SMC_ELIER (0xFFFFC514U) /**< \brief (SMC) PMECC Error Location Interrupt Enable register */ +#define REG_SMC_ELIDR (0xFFFFC518U) /**< \brief (SMC) PMECC Error Location Interrupt Disable Register */ +#define REG_SMC_ELIMR (0xFFFFC51CU) /**< \brief (SMC) PMECC Error Location Interrupt Mask Register */ +#define REG_SMC_ELISR (0xFFFFC520U) /**< \brief (SMC) PMECC Error Location Interrupt Status Register */ +#define REG_SMC_SIGMA0 (0xFFFFC528U) /**< \brief (SMC) PMECC Error Location SIGMA 0 Register */ +#define REG_SMC_SIGMA1 (0xFFFFC52CU) /**< \brief (SMC) PMECC Error Location SIGMA 1 Register */ +#define REG_SMC_SIGMA2 (0xFFFFC530U) /**< \brief (SMC) PMECC Error Location SIGMA 2 Register */ +#define REG_SMC_SIGMA3 (0xFFFFC534U) /**< \brief (SMC) PMECC Error Location SIGMA 3 Register */ +#define REG_SMC_SIGMA4 (0xFFFFC538U) /**< \brief (SMC) PMECC Error Location SIGMA 4 Register */ +#define REG_SMC_SIGMA5 (0xFFFFC53CU) /**< \brief (SMC) PMECC Error Location SIGMA 5 Register */ +#define REG_SMC_SIGMA6 (0xFFFFC540U) /**< \brief (SMC) PMECC Error Location SIGMA 6 Register */ +#define REG_SMC_SIGMA7 (0xFFFFC544U) /**< \brief (SMC) PMECC Error Location SIGMA 7 Register */ +#define REG_SMC_SIGMA8 (0xFFFFC548U) /**< \brief (SMC) PMECC Error Location SIGMA 8 Register */ +#define REG_SMC_SIGMA9 (0xFFFFC54CU) /**< \brief (SMC) PMECC Error Location SIGMA 9 Register */ +#define REG_SMC_SIGMA10 (0xFFFFC550U) /**< \brief (SMC) PMECC Error Location SIGMA 10 Register */ +#define REG_SMC_SIGMA11 (0xFFFFC554U) /**< \brief (SMC) PMECC Error Location SIGMA 11 Register */ +#define REG_SMC_SIGMA12 (0xFFFFC558U) /**< \brief (SMC) PMECC Error Location SIGMA 12 Register */ +#define REG_SMC_SIGMA13 (0xFFFFC55CU) /**< \brief (SMC) PMECC Error Location SIGMA 13 Register */ +#define REG_SMC_SIGMA14 (0xFFFFC560U) /**< \brief (SMC) PMECC Error Location SIGMA 14 Register */ +#define REG_SMC_SIGMA15 (0xFFFFC564U) /**< \brief (SMC) PMECC Error Location SIGMA 15 Register */ +#define REG_SMC_SIGMA16 (0xFFFFC568U) /**< \brief (SMC) PMECC Error Location SIGMA 16 Register */ +#define REG_SMC_SIGMA17 (0xFFFFC56CU) /**< \brief (SMC) PMECC Error Location SIGMA 17 Register */ +#define REG_SMC_SIGMA18 (0xFFFFC570U) /**< \brief (SMC) PMECC Error Location SIGMA 18 Register */ +#define REG_SMC_SIGMA19 (0xFFFFC574U) /**< \brief (SMC) PMECC Error Location SIGMA 19 Register */ +#define REG_SMC_SIGMA20 (0xFFFFC578U) /**< \brief (SMC) PMECC Error Location SIGMA 20 Register */ +#define REG_SMC_SIGMA21 (0xFFFFC57CU) /**< \brief (SMC) PMECC Error Location SIGMA 21 Register */ +#define REG_SMC_SIGMA22 (0xFFFFC580U) /**< \brief (SMC) PMECC Error Location SIGMA 22 Register */ +#define REG_SMC_SIGMA23 (0xFFFFC584U) /**< \brief (SMC) PMECC Error Location SIGMA 23 Register */ +#define REG_SMC_SIGMA24 (0xFFFFC588U) /**< \brief (SMC) PMECC Error Location SIGMA 24 Register */ +#define REG_SMC_ERRLOC (0xFFFFC58CU) /**< \brief (SMC) PMECC Error Location 0 Register */ +#define REG_SMC_SETUP0 (0xFFFFC600U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */ +#define REG_SMC_PULSE0 (0xFFFFC604U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */ +#define REG_SMC_CYCLE0 (0xFFFFC608U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */ +#define REG_SMC_TIMINGS0 (0xFFFFC60CU) /**< \brief (SMC) SMC Timings Register (CS_number = 0) */ +#define REG_SMC_MODE0 (0xFFFFC610U) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */ +#define REG_SMC_SETUP1 (0xFFFFC614U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */ +#define REG_SMC_PULSE1 (0xFFFFC618U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */ +#define REG_SMC_CYCLE1 (0xFFFFC61CU) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */ +#define REG_SMC_TIMINGS1 (0xFFFFC620U) /**< \brief (SMC) SMC Timings Register (CS_number = 1) */ +#define REG_SMC_MODE1 (0xFFFFC624U) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */ +#define REG_SMC_SETUP2 (0xFFFFC628U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */ +#define REG_SMC_PULSE2 (0xFFFFC62CU) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */ +#define REG_SMC_CYCLE2 (0xFFFFC630U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */ +#define REG_SMC_TIMINGS2 (0xFFFFC634U) /**< \brief (SMC) SMC Timings Register (CS_number = 2) */ +#define REG_SMC_MODE2 (0xFFFFC638U) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */ +#define REG_SMC_SETUP3 (0xFFFFC63CU) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */ +#define REG_SMC_PULSE3 (0xFFFFC640U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */ +#define REG_SMC_CYCLE3 (0xFFFFC644U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */ +#define REG_SMC_TIMINGS3 (0xFFFFC648U) /**< \brief (SMC) SMC Timings Register (CS_number = 3) */ +#define REG_SMC_MODE3 (0xFFFFC64CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */ +#define REG_SMC_OCMS (0xFFFFC6A0U) /**< \brief (SMC) SMC OCMS Register */ +#define REG_SMC_KEY1 (0xFFFFC6A4U) /**< \brief (SMC) SMC OCMS KEY1 Register */ +#define REG_SMC_KEY2 (0xFFFFC6A8U) /**< \brief (SMC) SMC OCMS KEY2 Register */ +#define REG_SMC_WPCR (0xFFFFC6E4U) /**< \brief (SMC) SMC Write Protection Control Register */ +#define REG_SMC_WPSR (0xFFFFC6E8U) /**< \brief (SMC) SMC Write Protection Status Register */ +#else +#define REG_SMC_CFG (*(RwReg*)0xFFFFC000U) /**< \brief (SMC) SMC NFC Configuration Register */ +#define REG_SMC_CTRL (*(WoReg*)0xFFFFC004U) /**< \brief (SMC) SMC NFC Control Register */ +#define REG_SMC_SR (*(RoReg*)0xFFFFC008U) /**< \brief (SMC) SMC NFC Status Register */ +#define REG_SMC_IER (*(WoReg*)0xFFFFC00CU) /**< \brief (SMC) SMC NFC Interrupt Enable Register */ +#define REG_SMC_IDR (*(WoReg*)0xFFFFC010U) /**< \brief (SMC) SMC NFC Interrupt Disable Register */ +#define REG_SMC_IMR (*(RoReg*)0xFFFFC014U) /**< \brief (SMC) SMC NFC Interrupt Mask Register */ +#define REG_SMC_ADDR (*(RwReg*)0xFFFFC018U) /**< \brief (SMC) SMC NFC Address Cycle Zero Register */ +#define REG_SMC_BANK (*(RwReg*)0xFFFFC01CU) /**< \brief (SMC) SMC Bank Address Register */ +#define REG_SMC_ECC_CTRL (*(WoReg*)0xFFFFC020U) /**< \brief (SMC) SMC ECC Control Register */ +#define REG_SMC_ECC_MD (*(RwReg*)0xFFFFC024U) /**< \brief (SMC) SMC ECC Mode Register */ +#define REG_SMC_ECC_SR1 (*(RoReg*)0xFFFFC028U) /**< \brief (SMC) SMC ECC Status 1 Register */ +#define REG_SMC_ECC_PR0 (*(RoReg*)0xFFFFC02CU) /**< \brief (SMC) SMC ECC Parity 0 Register */ +#define REG_SMC_ECC_PR1 (*(RoReg*)0xFFFFC030U) /**< \brief (SMC) SMC ECC parity 1 Register */ +#define REG_SMC_ECC_SR2 (*(RoReg*)0xFFFFC034U) /**< \brief (SMC) SMC ECC status 2 Register */ +#define REG_SMC_ECC_PR2 (*(RoReg*)0xFFFFC038U) /**< \brief (SMC) SMC ECC parity 2 Register */ +#define REG_SMC_ECC_PR3 (*(RoReg*)0xFFFFC03CU) /**< \brief (SMC) SMC ECC parity 3 Register */ +#define REG_SMC_ECC_PR4 (*(RoReg*)0xFFFFC040U) /**< \brief (SMC) SMC ECC parity 4 Register */ +#define REG_SMC_ECC_PR5 (*(RoReg*)0xFFFFC044U) /**< \brief (SMC) SMC ECC parity 5 Register */ +#define REG_SMC_ECC_PR6 (*(RoReg*)0xFFFFC048U) /**< \brief (SMC) SMC ECC parity 6 Register */ +#define REG_SMC_ECC_PR7 (*(RoReg*)0xFFFFC04CU) /**< \brief (SMC) SMC ECC parity 7 Register */ +#define REG_SMC_ECC_PR8 (*(RoReg*)0xFFFFC050U) /**< \brief (SMC) SMC ECC parity 8 Register */ +#define REG_SMC_ECC_PR9 (*(RoReg*)0xFFFFC054U) /**< \brief (SMC) SMC ECC parity 9 Register */ +#define REG_SMC_ECC_PR10 (*(RoReg*)0xFFFFC058U) /**< \brief (SMC) SMC ECC parity 10 Register */ +#define REG_SMC_ECC_PR11 (*(RoReg*)0xFFFFC05CU) /**< \brief (SMC) SMC ECC parity 11 Register */ +#define REG_SMC_ECC_PR12 (*(RoReg*)0xFFFFC060U) /**< \brief (SMC) SMC ECC parity 12 Register */ +#define REG_SMC_ECC_PR13 (*(RoReg*)0xFFFFC064U) /**< \brief (SMC) SMC ECC parity 13 Register */ +#define REG_SMC_ECC_PR14 (*(RoReg*)0xFFFFC068U) /**< \brief (SMC) SMC ECC parity 14 Register */ +#define REG_SMC_ECC_PR15 (*(RoReg*)0xFFFFC06CU) /**< \brief (SMC) SMC ECC parity 15 Register */ +#define REG_SMC_PMECCFG (*(RwReg*)0xFFFFC070U) /**< \brief (SMC) PMECC Configuration Register */ +#define REG_SMC_PMECCSAREA (*(RwReg*)0xFFFFC074U) /**< \brief (SMC) PMECC Spare Area Size Register */ +#define REG_SMC_PMECCSADDR (*(RwReg*)0xFFFFC078U) /**< \brief (SMC) PMECC Start Address Register */ +#define REG_SMC_PMECCEADDR (*(RwReg*)0xFFFFC07CU) /**< \brief (SMC) PMECC End Address Register */ +#define REG_SMC_PMECCTRL (*(WoReg*)0xFFFFC084U) /**< \brief (SMC) PMECC Control Register */ +#define REG_SMC_PMECCSR (*(RoReg*)0xFFFFC088U) /**< \brief (SMC) PMECC Status Register */ +#define REG_SMC_PMECCIER (*(WoReg*)0xFFFFC08CU) /**< \brief (SMC) PMECC Interrupt Enable register */ +#define REG_SMC_PMECCIDR (*(WoReg*)0xFFFFC090U) /**< \brief (SMC) PMECC Interrupt Disable Register */ +#define REG_SMC_PMECCIMR (*(RoReg*)0xFFFFC094U) /**< \brief (SMC) PMECC Interrupt Mask Register */ +#define REG_SMC_PMECCISR (*(RoReg*)0xFFFFC098U) /**< \brief (SMC) PMECC Interrupt Status Register */ +#define REG_SMC_PMECC0_0 (*(RoReg*)0xFFFFC0B0U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 0) */ +#define REG_SMC_PMECC1_0 (*(RoReg*)0xFFFFC0B4U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 0) */ +#define REG_SMC_PMECC2_0 (*(RoReg*)0xFFFFC0B8U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 0) */ +#define REG_SMC_PMECC3_0 (*(RoReg*)0xFFFFC0BCU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 0) */ +#define REG_SMC_PMECC4_0 (*(RoReg*)0xFFFFC0C0U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 0) */ +#define REG_SMC_PMECC5_0 (*(RoReg*)0xFFFFC0C4U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 0) */ +#define REG_SMC_PMECC6_0 (*(RoReg*)0xFFFFC0C8U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 0) */ +#define REG_SMC_PMECC7_0 (*(RoReg*)0xFFFFC0CCU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 0) */ +#define REG_SMC_PMECC8_0 (*(RoReg*)0xFFFFC0D0U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 0) */ +#define REG_SMC_PMECC9_0 (*(RoReg*)0xFFFFC0D4U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 0) */ +#define REG_SMC_PMECC10_0 (*(RoReg*)0xFFFFC0D8U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 0) */ +#define REG_SMC_PMECC0_1 (*(RoReg*)0xFFFFC0F0U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 1) */ +#define REG_SMC_PMECC1_1 (*(RoReg*)0xFFFFC0F4U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 1) */ +#define REG_SMC_PMECC2_1 (*(RoReg*)0xFFFFC0F8U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 1) */ +#define REG_SMC_PMECC3_1 (*(RoReg*)0xFFFFC0FCU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 1) */ +#define REG_SMC_PMECC4_1 (*(RoReg*)0xFFFFC100U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 1) */ +#define REG_SMC_PMECC5_1 (*(RoReg*)0xFFFFC104U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 1) */ +#define REG_SMC_PMECC6_1 (*(RoReg*)0xFFFFC108U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 1) */ +#define REG_SMC_PMECC7_1 (*(RoReg*)0xFFFFC10CU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 1) */ +#define REG_SMC_PMECC8_1 (*(RoReg*)0xFFFFC110U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 1) */ +#define REG_SMC_PMECC9_1 (*(RoReg*)0xFFFFC114U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 1) */ +#define REG_SMC_PMECC10_1 (*(RoReg*)0xFFFFC118U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 1) */ +#define REG_SMC_PMECC0_2 (*(RoReg*)0xFFFFC130U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 2) */ +#define REG_SMC_PMECC1_2 (*(RoReg*)0xFFFFC134U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 2) */ +#define REG_SMC_PMECC2_2 (*(RoReg*)0xFFFFC138U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 2) */ +#define REG_SMC_PMECC3_2 (*(RoReg*)0xFFFFC13CU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 2) */ +#define REG_SMC_PMECC4_2 (*(RoReg*)0xFFFFC140U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 2) */ +#define REG_SMC_PMECC5_2 (*(RoReg*)0xFFFFC144U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 2) */ +#define REG_SMC_PMECC6_2 (*(RoReg*)0xFFFFC148U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 2) */ +#define REG_SMC_PMECC7_2 (*(RoReg*)0xFFFFC14CU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 2) */ +#define REG_SMC_PMECC8_2 (*(RoReg*)0xFFFFC150U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 2) */ +#define REG_SMC_PMECC9_2 (*(RoReg*)0xFFFFC154U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 2) */ +#define REG_SMC_PMECC10_2 (*(RoReg*)0xFFFFC158U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 2) */ +#define REG_SMC_PMECC0_3 (*(RoReg*)0xFFFFC170U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 3) */ +#define REG_SMC_PMECC1_3 (*(RoReg*)0xFFFFC174U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 3) */ +#define REG_SMC_PMECC2_3 (*(RoReg*)0xFFFFC178U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 3) */ +#define REG_SMC_PMECC3_3 (*(RoReg*)0xFFFFC17CU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 3) */ +#define REG_SMC_PMECC4_3 (*(RoReg*)0xFFFFC180U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 3) */ +#define REG_SMC_PMECC5_3 (*(RoReg*)0xFFFFC184U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 3) */ +#define REG_SMC_PMECC6_3 (*(RoReg*)0xFFFFC188U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 3) */ +#define REG_SMC_PMECC7_3 (*(RoReg*)0xFFFFC18CU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 3) */ +#define REG_SMC_PMECC8_3 (*(RoReg*)0xFFFFC190U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 3) */ +#define REG_SMC_PMECC9_3 (*(RoReg*)0xFFFFC194U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 3) */ +#define REG_SMC_PMECC10_3 (*(RoReg*)0xFFFFC198U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 3) */ +#define REG_SMC_PMECC0_4 (*(RoReg*)0xFFFFC1B0U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 4) */ +#define REG_SMC_PMECC1_4 (*(RoReg*)0xFFFFC1B4U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 4) */ +#define REG_SMC_PMECC2_4 (*(RoReg*)0xFFFFC1B8U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 4) */ +#define REG_SMC_PMECC3_4 (*(RoReg*)0xFFFFC1BCU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 4) */ +#define REG_SMC_PMECC4_4 (*(RoReg*)0xFFFFC1C0U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 4) */ +#define REG_SMC_PMECC5_4 (*(RoReg*)0xFFFFC1C4U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 4) */ +#define REG_SMC_PMECC6_4 (*(RoReg*)0xFFFFC1C8U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 4) */ +#define REG_SMC_PMECC7_4 (*(RoReg*)0xFFFFC1CCU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 4) */ +#define REG_SMC_PMECC8_4 (*(RoReg*)0xFFFFC1D0U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 4) */ +#define REG_SMC_PMECC9_4 (*(RoReg*)0xFFFFC1D4U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 4) */ +#define REG_SMC_PMECC10_4 (*(RoReg*)0xFFFFC1D8U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 4) */ +#define REG_SMC_PMECC0_5 (*(RoReg*)0xFFFFC1F0U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 5) */ +#define REG_SMC_PMECC1_5 (*(RoReg*)0xFFFFC1F4U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 5) */ +#define REG_SMC_PMECC2_5 (*(RoReg*)0xFFFFC1F8U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 5) */ +#define REG_SMC_PMECC3_5 (*(RoReg*)0xFFFFC1FCU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 5) */ +#define REG_SMC_PMECC4_5 (*(RoReg*)0xFFFFC200U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 5) */ +#define REG_SMC_PMECC5_5 (*(RoReg*)0xFFFFC204U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 5) */ +#define REG_SMC_PMECC6_5 (*(RoReg*)0xFFFFC208U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 5) */ +#define REG_SMC_PMECC7_5 (*(RoReg*)0xFFFFC20CU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 5) */ +#define REG_SMC_PMECC8_5 (*(RoReg*)0xFFFFC210U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 5) */ +#define REG_SMC_PMECC9_5 (*(RoReg*)0xFFFFC214U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 5) */ +#define REG_SMC_PMECC10_5 (*(RoReg*)0xFFFFC218U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 5) */ +#define REG_SMC_PMECC0_6 (*(RoReg*)0xFFFFC230U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 6) */ +#define REG_SMC_PMECC1_6 (*(RoReg*)0xFFFFC234U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 6) */ +#define REG_SMC_PMECC2_6 (*(RoReg*)0xFFFFC238U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 6) */ +#define REG_SMC_PMECC3_6 (*(RoReg*)0xFFFFC23CU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 6) */ +#define REG_SMC_PMECC4_6 (*(RoReg*)0xFFFFC240U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 6) */ +#define REG_SMC_PMECC5_6 (*(RoReg*)0xFFFFC244U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 6) */ +#define REG_SMC_PMECC6_6 (*(RoReg*)0xFFFFC248U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 6) */ +#define REG_SMC_PMECC7_6 (*(RoReg*)0xFFFFC24CU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 6) */ +#define REG_SMC_PMECC8_6 (*(RoReg*)0xFFFFC250U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 6) */ +#define REG_SMC_PMECC9_6 (*(RoReg*)0xFFFFC254U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 6) */ +#define REG_SMC_PMECC10_6 (*(RoReg*)0xFFFFC258U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 6) */ +#define REG_SMC_PMECC0_7 (*(RoReg*)0xFFFFC270U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 7) */ +#define REG_SMC_PMECC1_7 (*(RoReg*)0xFFFFC274U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 7) */ +#define REG_SMC_PMECC2_7 (*(RoReg*)0xFFFFC278U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 7) */ +#define REG_SMC_PMECC3_7 (*(RoReg*)0xFFFFC27CU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 7) */ +#define REG_SMC_PMECC4_7 (*(RoReg*)0xFFFFC280U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 7) */ +#define REG_SMC_PMECC5_7 (*(RoReg*)0xFFFFC284U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 7) */ +#define REG_SMC_PMECC6_7 (*(RoReg*)0xFFFFC288U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 7) */ +#define REG_SMC_PMECC7_7 (*(RoReg*)0xFFFFC28CU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 7) */ +#define REG_SMC_PMECC8_7 (*(RoReg*)0xFFFFC290U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 7) */ +#define REG_SMC_PMECC9_7 (*(RoReg*)0xFFFFC294U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 7) */ +#define REG_SMC_PMECC10_7 (*(RoReg*)0xFFFFC298U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 7) */ +#define REG_SMC_REM0_0 (*(RoReg*)0xFFFFC2B0U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 0) */ +#define REG_SMC_REM1_0 (*(RoReg*)0xFFFFC2B4U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 0) */ +#define REG_SMC_REM2_0 (*(RoReg*)0xFFFFC2B8U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 0) */ +#define REG_SMC_REM3_0 (*(RoReg*)0xFFFFC2BCU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 0) */ +#define REG_SMC_REM4_0 (*(RoReg*)0xFFFFC2C0U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 0) */ +#define REG_SMC_REM5_0 (*(RoReg*)0xFFFFC2C4U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 0) */ +#define REG_SMC_REM6_0 (*(RoReg*)0xFFFFC2C8U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 0) */ +#define REG_SMC_REM7_0 (*(RoReg*)0xFFFFC2CCU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 0) */ +#define REG_SMC_REM8_0 (*(RoReg*)0xFFFFC2D0U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 0) */ +#define REG_SMC_REM9_0 (*(RoReg*)0xFFFFC2D4U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 0) */ +#define REG_SMC_REM10_0 (*(RoReg*)0xFFFFC2D8U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 0) */ +#define REG_SMC_REM11_0 (*(RoReg*)0xFFFFC2DCU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 0) */ +#define REG_SMC_REM0_1 (*(RoReg*)0xFFFFC2F0U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 1) */ +#define REG_SMC_REM1_1 (*(RoReg*)0xFFFFC2F4U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 1) */ +#define REG_SMC_REM2_1 (*(RoReg*)0xFFFFC2F8U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 1) */ +#define REG_SMC_REM3_1 (*(RoReg*)0xFFFFC2FCU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 1) */ +#define REG_SMC_REM4_1 (*(RoReg*)0xFFFFC300U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 1) */ +#define REG_SMC_REM5_1 (*(RoReg*)0xFFFFC304U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 1) */ +#define REG_SMC_REM6_1 (*(RoReg*)0xFFFFC308U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 1) */ +#define REG_SMC_REM7_1 (*(RoReg*)0xFFFFC30CU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 1) */ +#define REG_SMC_REM8_1 (*(RoReg*)0xFFFFC310U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 1) */ +#define REG_SMC_REM9_1 (*(RoReg*)0xFFFFC314U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 1) */ +#define REG_SMC_REM10_1 (*(RoReg*)0xFFFFC318U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 1) */ +#define REG_SMC_REM11_1 (*(RoReg*)0xFFFFC31CU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 1) */ +#define REG_SMC_REM0_2 (*(RoReg*)0xFFFFC330U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 2) */ +#define REG_SMC_REM1_2 (*(RoReg*)0xFFFFC334U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 2) */ +#define REG_SMC_REM2_2 (*(RoReg*)0xFFFFC338U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 2) */ +#define REG_SMC_REM3_2 (*(RoReg*)0xFFFFC33CU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 2) */ +#define REG_SMC_REM4_2 (*(RoReg*)0xFFFFC340U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 2) */ +#define REG_SMC_REM5_2 (*(RoReg*)0xFFFFC344U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 2) */ +#define REG_SMC_REM6_2 (*(RoReg*)0xFFFFC348U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 2) */ +#define REG_SMC_REM7_2 (*(RoReg*)0xFFFFC34CU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 2) */ +#define REG_SMC_REM8_2 (*(RoReg*)0xFFFFC350U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 2) */ +#define REG_SMC_REM9_2 (*(RoReg*)0xFFFFC354U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 2) */ +#define REG_SMC_REM10_2 (*(RoReg*)0xFFFFC358U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 2) */ +#define REG_SMC_REM11_2 (*(RoReg*)0xFFFFC35CU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 2) */ +#define REG_SMC_REM0_3 (*(RoReg*)0xFFFFC370U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 3) */ +#define REG_SMC_REM1_3 (*(RoReg*)0xFFFFC374U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 3) */ +#define REG_SMC_REM2_3 (*(RoReg*)0xFFFFC378U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 3) */ +#define REG_SMC_REM3_3 (*(RoReg*)0xFFFFC37CU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 3) */ +#define REG_SMC_REM4_3 (*(RoReg*)0xFFFFC380U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 3) */ +#define REG_SMC_REM5_3 (*(RoReg*)0xFFFFC384U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 3) */ +#define REG_SMC_REM6_3 (*(RoReg*)0xFFFFC388U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 3) */ +#define REG_SMC_REM7_3 (*(RoReg*)0xFFFFC38CU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 3) */ +#define REG_SMC_REM8_3 (*(RoReg*)0xFFFFC390U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 3) */ +#define REG_SMC_REM9_3 (*(RoReg*)0xFFFFC394U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 3) */ +#define REG_SMC_REM10_3 (*(RoReg*)0xFFFFC398U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 3) */ +#define REG_SMC_REM11_3 (*(RoReg*)0xFFFFC39CU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 3) */ +#define REG_SMC_REM0_4 (*(RoReg*)0xFFFFC3B0U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 4) */ +#define REG_SMC_REM1_4 (*(RoReg*)0xFFFFC3B4U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 4) */ +#define REG_SMC_REM2_4 (*(RoReg*)0xFFFFC3B8U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 4) */ +#define REG_SMC_REM3_4 (*(RoReg*)0xFFFFC3BCU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 4) */ +#define REG_SMC_REM4_4 (*(RoReg*)0xFFFFC3C0U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 4) */ +#define REG_SMC_REM5_4 (*(RoReg*)0xFFFFC3C4U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 4) */ +#define REG_SMC_REM6_4 (*(RoReg*)0xFFFFC3C8U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 4) */ +#define REG_SMC_REM7_4 (*(RoReg*)0xFFFFC3CCU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 4) */ +#define REG_SMC_REM8_4 (*(RoReg*)0xFFFFC3D0U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 4) */ +#define REG_SMC_REM9_4 (*(RoReg*)0xFFFFC3D4U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 4) */ +#define REG_SMC_REM10_4 (*(RoReg*)0xFFFFC3D8U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 4) */ +#define REG_SMC_REM11_4 (*(RoReg*)0xFFFFC3DCU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 4) */ +#define REG_SMC_REM0_5 (*(RoReg*)0xFFFFC3F0U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 5) */ +#define REG_SMC_REM1_5 (*(RoReg*)0xFFFFC3F4U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 5) */ +#define REG_SMC_REM2_5 (*(RoReg*)0xFFFFC3F8U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 5) */ +#define REG_SMC_REM3_5 (*(RoReg*)0xFFFFC3FCU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 5) */ +#define REG_SMC_REM4_5 (*(RoReg*)0xFFFFC400U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 5) */ +#define REG_SMC_REM5_5 (*(RoReg*)0xFFFFC404U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 5) */ +#define REG_SMC_REM6_5 (*(RoReg*)0xFFFFC408U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 5) */ +#define REG_SMC_REM7_5 (*(RoReg*)0xFFFFC40CU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 5) */ +#define REG_SMC_REM8_5 (*(RoReg*)0xFFFFC410U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 5) */ +#define REG_SMC_REM9_5 (*(RoReg*)0xFFFFC414U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 5) */ +#define REG_SMC_REM10_5 (*(RoReg*)0xFFFFC418U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 5) */ +#define REG_SMC_REM11_5 (*(RoReg*)0xFFFFC41CU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 5) */ +#define REG_SMC_REM0_6 (*(RoReg*)0xFFFFC430U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 6) */ +#define REG_SMC_REM1_6 (*(RoReg*)0xFFFFC434U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 6) */ +#define REG_SMC_REM2_6 (*(RoReg*)0xFFFFC438U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 6) */ +#define REG_SMC_REM3_6 (*(RoReg*)0xFFFFC43CU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 6) */ +#define REG_SMC_REM4_6 (*(RoReg*)0xFFFFC440U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 6) */ +#define REG_SMC_REM5_6 (*(RoReg*)0xFFFFC444U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 6) */ +#define REG_SMC_REM6_6 (*(RoReg*)0xFFFFC448U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 6) */ +#define REG_SMC_REM7_6 (*(RoReg*)0xFFFFC44CU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 6) */ +#define REG_SMC_REM8_6 (*(RoReg*)0xFFFFC450U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 6) */ +#define REG_SMC_REM9_6 (*(RoReg*)0xFFFFC454U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 6) */ +#define REG_SMC_REM10_6 (*(RoReg*)0xFFFFC458U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 6) */ +#define REG_SMC_REM11_6 (*(RoReg*)0xFFFFC45CU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 6) */ +#define REG_SMC_REM0_7 (*(RoReg*)0xFFFFC470U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 7) */ +#define REG_SMC_REM1_7 (*(RoReg*)0xFFFFC474U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 7) */ +#define REG_SMC_REM2_7 (*(RoReg*)0xFFFFC478U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 7) */ +#define REG_SMC_REM3_7 (*(RoReg*)0xFFFFC47CU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 7) */ +#define REG_SMC_REM4_7 (*(RoReg*)0xFFFFC480U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 7) */ +#define REG_SMC_REM5_7 (*(RoReg*)0xFFFFC484U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 7) */ +#define REG_SMC_REM6_7 (*(RoReg*)0xFFFFC488U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 7) */ +#define REG_SMC_REM7_7 (*(RoReg*)0xFFFFC48CU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 7) */ +#define REG_SMC_REM8_7 (*(RoReg*)0xFFFFC490U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 7) */ +#define REG_SMC_REM9_7 (*(RoReg*)0xFFFFC494U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 7) */ +#define REG_SMC_REM10_7 (*(RoReg*)0xFFFFC498U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 7) */ +#define REG_SMC_REM11_7 (*(RoReg*)0xFFFFC49CU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 7) */ +#define REG_SMC_ELCFG (*(RwReg*)0xFFFFC500U) /**< \brief (SMC) PMECC Error Location Configuration Register */ +#define REG_SMC_ELPRIM (*(RoReg*)0xFFFFC504U) /**< \brief (SMC) PMECC Error Location Primitive Register */ +#define REG_SMC_ELEN (*(WoReg*)0xFFFFC508U) /**< \brief (SMC) PMECC Error Location Enable Register */ +#define REG_SMC_ELDIS (*(WoReg*)0xFFFFC50CU) /**< \brief (SMC) PMECC Error Location Disable Register */ +#define REG_SMC_ELSR (*(RoReg*)0xFFFFC510U) /**< \brief (SMC) PMECC Error Location Status Register */ +#define REG_SMC_ELIER (*(WoReg*)0xFFFFC514U) /**< \brief (SMC) PMECC Error Location Interrupt Enable register */ +#define REG_SMC_ELIDR (*(WoReg*)0xFFFFC518U) /**< \brief (SMC) PMECC Error Location Interrupt Disable Register */ +#define REG_SMC_ELIMR (*(RoReg*)0xFFFFC51CU) /**< \brief (SMC) PMECC Error Location Interrupt Mask Register */ +#define REG_SMC_ELISR (*(RoReg*)0xFFFFC520U) /**< \brief (SMC) PMECC Error Location Interrupt Status Register */ +#define REG_SMC_SIGMA0 (*(RwReg*)0xFFFFC528U) /**< \brief (SMC) PMECC Error Location SIGMA 0 Register */ +#define REG_SMC_SIGMA1 (*(RwReg*)0xFFFFC52CU) /**< \brief (SMC) PMECC Error Location SIGMA 1 Register */ +#define REG_SMC_SIGMA2 (*(RwReg*)0xFFFFC530U) /**< \brief (SMC) PMECC Error Location SIGMA 2 Register */ +#define REG_SMC_SIGMA3 (*(RwReg*)0xFFFFC534U) /**< \brief (SMC) PMECC Error Location SIGMA 3 Register */ +#define REG_SMC_SIGMA4 (*(RwReg*)0xFFFFC538U) /**< \brief (SMC) PMECC Error Location SIGMA 4 Register */ +#define REG_SMC_SIGMA5 (*(RwReg*)0xFFFFC53CU) /**< \brief (SMC) PMECC Error Location SIGMA 5 Register */ +#define REG_SMC_SIGMA6 (*(RwReg*)0xFFFFC540U) /**< \brief (SMC) PMECC Error Location SIGMA 6 Register */ +#define REG_SMC_SIGMA7 (*(RwReg*)0xFFFFC544U) /**< \brief (SMC) PMECC Error Location SIGMA 7 Register */ +#define REG_SMC_SIGMA8 (*(RwReg*)0xFFFFC548U) /**< \brief (SMC) PMECC Error Location SIGMA 8 Register */ +#define REG_SMC_SIGMA9 (*(RwReg*)0xFFFFC54CU) /**< \brief (SMC) PMECC Error Location SIGMA 9 Register */ +#define REG_SMC_SIGMA10 (*(RwReg*)0xFFFFC550U) /**< \brief (SMC) PMECC Error Location SIGMA 10 Register */ +#define REG_SMC_SIGMA11 (*(RwReg*)0xFFFFC554U) /**< \brief (SMC) PMECC Error Location SIGMA 11 Register */ +#define REG_SMC_SIGMA12 (*(RwReg*)0xFFFFC558U) /**< \brief (SMC) PMECC Error Location SIGMA 12 Register */ +#define REG_SMC_SIGMA13 (*(RwReg*)0xFFFFC55CU) /**< \brief (SMC) PMECC Error Location SIGMA 13 Register */ +#define REG_SMC_SIGMA14 (*(RwReg*)0xFFFFC560U) /**< \brief (SMC) PMECC Error Location SIGMA 14 Register */ +#define REG_SMC_SIGMA15 (*(RwReg*)0xFFFFC564U) /**< \brief (SMC) PMECC Error Location SIGMA 15 Register */ +#define REG_SMC_SIGMA16 (*(RwReg*)0xFFFFC568U) /**< \brief (SMC) PMECC Error Location SIGMA 16 Register */ +#define REG_SMC_SIGMA17 (*(RwReg*)0xFFFFC56CU) /**< \brief (SMC) PMECC Error Location SIGMA 17 Register */ +#define REG_SMC_SIGMA18 (*(RwReg*)0xFFFFC570U) /**< \brief (SMC) PMECC Error Location SIGMA 18 Register */ +#define REG_SMC_SIGMA19 (*(RwReg*)0xFFFFC574U) /**< \brief (SMC) PMECC Error Location SIGMA 19 Register */ +#define REG_SMC_SIGMA20 (*(RwReg*)0xFFFFC578U) /**< \brief (SMC) PMECC Error Location SIGMA 20 Register */ +#define REG_SMC_SIGMA21 (*(RwReg*)0xFFFFC57CU) /**< \brief (SMC) PMECC Error Location SIGMA 21 Register */ +#define REG_SMC_SIGMA22 (*(RwReg*)0xFFFFC580U) /**< \brief (SMC) PMECC Error Location SIGMA 22 Register */ +#define REG_SMC_SIGMA23 (*(RwReg*)0xFFFFC584U) /**< \brief (SMC) PMECC Error Location SIGMA 23 Register */ +#define REG_SMC_SIGMA24 (*(RwReg*)0xFFFFC588U) /**< \brief (SMC) PMECC Error Location SIGMA 24 Register */ +#define REG_SMC_ERRLOC (*(RoReg*)0xFFFFC58CU) /**< \brief (SMC) PMECC Error Location 0 Register */ +#define REG_SMC_SETUP0 (*(RwReg*)0xFFFFC600U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */ +#define REG_SMC_PULSE0 (*(RwReg*)0xFFFFC604U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */ +#define REG_SMC_CYCLE0 (*(RwReg*)0xFFFFC608U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */ +#define REG_SMC_TIMINGS0 (*(RwReg*)0xFFFFC60CU) /**< \brief (SMC) SMC Timings Register (CS_number = 0) */ +#define REG_SMC_MODE0 (*(RwReg*)0xFFFFC610U) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */ +#define REG_SMC_SETUP1 (*(RwReg*)0xFFFFC614U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */ +#define REG_SMC_PULSE1 (*(RwReg*)0xFFFFC618U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */ +#define REG_SMC_CYCLE1 (*(RwReg*)0xFFFFC61CU) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */ +#define REG_SMC_TIMINGS1 (*(RwReg*)0xFFFFC620U) /**< \brief (SMC) SMC Timings Register (CS_number = 1) */ +#define REG_SMC_MODE1 (*(RwReg*)0xFFFFC624U) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */ +#define REG_SMC_SETUP2 (*(RwReg*)0xFFFFC628U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */ +#define REG_SMC_PULSE2 (*(RwReg*)0xFFFFC62CU) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */ +#define REG_SMC_CYCLE2 (*(RwReg*)0xFFFFC630U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */ +#define REG_SMC_TIMINGS2 (*(RwReg*)0xFFFFC634U) /**< \brief (SMC) SMC Timings Register (CS_number = 2) */ +#define REG_SMC_MODE2 (*(RwReg*)0xFFFFC638U) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */ +#define REG_SMC_SETUP3 (*(RwReg*)0xFFFFC63CU) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */ +#define REG_SMC_PULSE3 (*(RwReg*)0xFFFFC640U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */ +#define REG_SMC_CYCLE3 (*(RwReg*)0xFFFFC644U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */ +#define REG_SMC_TIMINGS3 (*(RwReg*)0xFFFFC648U) /**< \brief (SMC) SMC Timings Register (CS_number = 3) */ +#define REG_SMC_MODE3 (*(RwReg*)0xFFFFC64CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */ +#define REG_SMC_OCMS (*(RwReg*)0xFFFFC6A0U) /**< \brief (SMC) SMC OCMS Register */ +#define REG_SMC_KEY1 (*(WoReg*)0xFFFFC6A4U) /**< \brief (SMC) SMC OCMS KEY1 Register */ +#define REG_SMC_KEY2 (*(WoReg*)0xFFFFC6A8U) /**< \brief (SMC) SMC OCMS KEY2 Register */ +#define REG_SMC_WPCR (*(WoReg*)0xFFFFC6E4U) /**< \brief (SMC) SMC Write Protection Control Register */ +#define REG_SMC_WPSR (*(RoReg*)0xFFFFC6E8U) /**< \brief (SMC) SMC Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_SMC_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_smd.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_smd.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_smd.h
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_spi0.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_spi0.h new file mode 100644 index 0000000..e917fb5 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_spi0.h
@@ -0,0 +1,60 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_SPI0_INSTANCE_ +#define _SAMA5_SPI0_INSTANCE_ + +/* ========== Register definition for SPI0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SPI0_CR (0xF0004000U) /**< \brief (SPI0) Control Register */ +#define REG_SPI0_MR (0xF0004004U) /**< \brief (SPI0) Mode Register */ +#define REG_SPI0_RDR (0xF0004008U) /**< \brief (SPI0) Receive Data Register */ +#define REG_SPI0_TDR (0xF000400CU) /**< \brief (SPI0) Transmit Data Register */ +#define REG_SPI0_SR (0xF0004010U) /**< \brief (SPI0) Status Register */ +#define REG_SPI0_IER (0xF0004014U) /**< \brief (SPI0) Interrupt Enable Register */ +#define REG_SPI0_IDR (0xF0004018U) /**< \brief (SPI0) Interrupt Disable Register */ +#define REG_SPI0_IMR (0xF000401CU) /**< \brief (SPI0) Interrupt Mask Register */ +#define REG_SPI0_CSR (0xF0004030U) /**< \brief (SPI0) Chip Select Register */ +#define REG_SPI0_WPMR (0xF00040E4U) /**< \brief (SPI0) Write Protection Control Register */ +#define REG_SPI0_WPSR (0xF00040E8U) /**< \brief (SPI0) Write Protection Status Register */ +#else +#define REG_SPI0_CR (*(WoReg*)0xF0004000U) /**< \brief (SPI0) Control Register */ +#define REG_SPI0_MR (*(RwReg*)0xF0004004U) /**< \brief (SPI0) Mode Register */ +#define REG_SPI0_RDR (*(RoReg*)0xF0004008U) /**< \brief (SPI0) Receive Data Register */ +#define REG_SPI0_TDR (*(WoReg*)0xF000400CU) /**< \brief (SPI0) Transmit Data Register */ +#define REG_SPI0_SR (*(RoReg*)0xF0004010U) /**< \brief (SPI0) Status Register */ +#define REG_SPI0_IER (*(WoReg*)0xF0004014U) /**< \brief (SPI0) Interrupt Enable Register */ +#define REG_SPI0_IDR (*(WoReg*)0xF0004018U) /**< \brief (SPI0) Interrupt Disable Register */ +#define REG_SPI0_IMR (*(RoReg*)0xF000401CU) /**< \brief (SPI0) Interrupt Mask Register */ +#define REG_SPI0_CSR (*(RwReg*)0xF0004030U) /**< \brief (SPI0) Chip Select Register */ +#define REG_SPI0_WPMR (*(RwReg*)0xF00040E4U) /**< \brief (SPI0) Write Protection Control Register */ +#define REG_SPI0_WPSR (*(RoReg*)0xF00040E8U) /**< \brief (SPI0) Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_SPI0_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_spi1.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_spi1.h new file mode 100644 index 0000000..cce19b6 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_spi1.h
@@ -0,0 +1,60 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_SPI1_INSTANCE_ +#define _SAMA5_SPI1_INSTANCE_ + +/* ========== Register definition for SPI1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SPI1_CR (0xF8008000U) /**< \brief (SPI1) Control Register */ +#define REG_SPI1_MR (0xF8008004U) /**< \brief (SPI1) Mode Register */ +#define REG_SPI1_RDR (0xF8008008U) /**< \brief (SPI1) Receive Data Register */ +#define REG_SPI1_TDR (0xF800800CU) /**< \brief (SPI1) Transmit Data Register */ +#define REG_SPI1_SR (0xF8008010U) /**< \brief (SPI1) Status Register */ +#define REG_SPI1_IER (0xF8008014U) /**< \brief (SPI1) Interrupt Enable Register */ +#define REG_SPI1_IDR (0xF8008018U) /**< \brief (SPI1) Interrupt Disable Register */ +#define REG_SPI1_IMR (0xF800801CU) /**< \brief (SPI1) Interrupt Mask Register */ +#define REG_SPI1_CSR (0xF8008030U) /**< \brief (SPI1) Chip Select Register */ +#define REG_SPI1_WPMR (0xF80080E4U) /**< \brief (SPI1) Write Protection Control Register */ +#define REG_SPI1_WPSR (0xF80080E8U) /**< \brief (SPI1) Write Protection Status Register */ +#else +#define REG_SPI1_CR (*(WoReg*)0xF8008000U) /**< \brief (SPI1) Control Register */ +#define REG_SPI1_MR (*(RwReg*)0xF8008004U) /**< \brief (SPI1) Mode Register */ +#define REG_SPI1_RDR (*(RoReg*)0xF8008008U) /**< \brief (SPI1) Receive Data Register */ +#define REG_SPI1_TDR (*(WoReg*)0xF800800CU) /**< \brief (SPI1) Transmit Data Register */ +#define REG_SPI1_SR (*(RoReg*)0xF8008010U) /**< \brief (SPI1) Status Register */ +#define REG_SPI1_IER (*(WoReg*)0xF8008014U) /**< \brief (SPI1) Interrupt Enable Register */ +#define REG_SPI1_IDR (*(WoReg*)0xF8008018U) /**< \brief (SPI1) Interrupt Disable Register */ +#define REG_SPI1_IMR (*(RoReg*)0xF800801CU) /**< \brief (SPI1) Interrupt Mask Register */ +#define REG_SPI1_CSR (*(RwReg*)0xF8008030U) /**< \brief (SPI1) Chip Select Register */ +#define REG_SPI1_WPMR (*(RwReg*)0xF80080E4U) /**< \brief (SPI1) Write Protection Control Register */ +#define REG_SPI1_WPSR (*(RoReg*)0xF80080E8U) /**< \brief (SPI1) Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_SPI1_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_ssc0.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_ssc0.h new file mode 100644 index 0000000..9e721e2 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_ssc0.h
@@ -0,0 +1,74 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_SSC0_INSTANCE_ +#define _SAMA5_SSC0_INSTANCE_ + +/* ========== Register definition for SSC0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SSC0_CR (0xF0008000U) /**< \brief (SSC0) Control Register */ +#define REG_SSC0_CMR (0xF0008004U) /**< \brief (SSC0) Clock Mode Register */ +#define REG_SSC0_RCMR (0xF0008010U) /**< \brief (SSC0) Receive Clock Mode Register */ +#define REG_SSC0_RFMR (0xF0008014U) /**< \brief (SSC0) Receive Frame Mode Register */ +#define REG_SSC0_TCMR (0xF0008018U) /**< \brief (SSC0) Transmit Clock Mode Register */ +#define REG_SSC0_TFMR (0xF000801CU) /**< \brief (SSC0) Transmit Frame Mode Register */ +#define REG_SSC0_RHR (0xF0008020U) /**< \brief (SSC0) Receive Holding Register */ +#define REG_SSC0_THR (0xF0008024U) /**< \brief (SSC0) Transmit Holding Register */ +#define REG_SSC0_RSHR (0xF0008030U) /**< \brief (SSC0) Receive Sync. Holding Register */ +#define REG_SSC0_TSHR (0xF0008034U) /**< \brief (SSC0) Transmit Sync. Holding Register */ +#define REG_SSC0_RC0R (0xF0008038U) /**< \brief (SSC0) Receive Compare 0 Register */ +#define REG_SSC0_RC1R (0xF000803CU) /**< \brief (SSC0) Receive Compare 1 Register */ +#define REG_SSC0_SR (0xF0008040U) /**< \brief (SSC0) Status Register */ +#define REG_SSC0_IER (0xF0008044U) /**< \brief (SSC0) Interrupt Enable Register */ +#define REG_SSC0_IDR (0xF0008048U) /**< \brief (SSC0) Interrupt Disable Register */ +#define REG_SSC0_IMR (0xF000804CU) /**< \brief (SSC0) Interrupt Mask Register */ +#define REG_SSC0_WPMR (0xF00080E4U) /**< \brief (SSC0) Write Protect Mode Register */ +#define REG_SSC0_WPSR (0xF00080E8U) /**< \brief (SSC0) Write Protect Status Register */ +#else +#define REG_SSC0_CR (*(WoReg*)0xF0008000U) /**< \brief (SSC0) Control Register */ +#define REG_SSC0_CMR (*(RwReg*)0xF0008004U) /**< \brief (SSC0) Clock Mode Register */ +#define REG_SSC0_RCMR (*(RwReg*)0xF0008010U) /**< \brief (SSC0) Receive Clock Mode Register */ +#define REG_SSC0_RFMR (*(RwReg*)0xF0008014U) /**< \brief (SSC0) Receive Frame Mode Register */ +#define REG_SSC0_TCMR (*(RwReg*)0xF0008018U) /**< \brief (SSC0) Transmit Clock Mode Register */ +#define REG_SSC0_TFMR (*(RwReg*)0xF000801CU) /**< \brief (SSC0) Transmit Frame Mode Register */ +#define REG_SSC0_RHR (*(RoReg*)0xF0008020U) /**< \brief (SSC0) Receive Holding Register */ +#define REG_SSC0_THR (*(WoReg*)0xF0008024U) /**< \brief (SSC0) Transmit Holding Register */ +#define REG_SSC0_RSHR (*(RoReg*)0xF0008030U) /**< \brief (SSC0) Receive Sync. Holding Register */ +#define REG_SSC0_TSHR (*(RwReg*)0xF0008034U) /**< \brief (SSC0) Transmit Sync. Holding Register */ +#define REG_SSC0_RC0R (*(RwReg*)0xF0008038U) /**< \brief (SSC0) Receive Compare 0 Register */ +#define REG_SSC0_RC1R (*(RwReg*)0xF000803CU) /**< \brief (SSC0) Receive Compare 1 Register */ +#define REG_SSC0_SR (*(RoReg*)0xF0008040U) /**< \brief (SSC0) Status Register */ +#define REG_SSC0_IER (*(WoReg*)0xF0008044U) /**< \brief (SSC0) Interrupt Enable Register */ +#define REG_SSC0_IDR (*(WoReg*)0xF0008048U) /**< \brief (SSC0) Interrupt Disable Register */ +#define REG_SSC0_IMR (*(RoReg*)0xF000804CU) /**< \brief (SSC0) Interrupt Mask Register */ +#define REG_SSC0_WPMR (*(RwReg*)0xF00080E4U) /**< \brief (SSC0) Write Protect Mode Register */ +#define REG_SSC0_WPSR (*(RoReg*)0xF00080E8U) /**< \brief (SSC0) Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_SSC0_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_ssc1.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_ssc1.h new file mode 100644 index 0000000..7046fa4 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_ssc1.h
@@ -0,0 +1,74 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_SSC1_INSTANCE_ +#define _SAMA5_SSC1_INSTANCE_ + +/* ========== Register definition for SSC1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SSC1_CR (0xF800C000U) /**< \brief (SSC1) Control Register */ +#define REG_SSC1_CMR (0xF800C004U) /**< \brief (SSC1) Clock Mode Register */ +#define REG_SSC1_RCMR (0xF800C010U) /**< \brief (SSC1) Receive Clock Mode Register */ +#define REG_SSC1_RFMR (0xF800C014U) /**< \brief (SSC1) Receive Frame Mode Register */ +#define REG_SSC1_TCMR (0xF800C018U) /**< \brief (SSC1) Transmit Clock Mode Register */ +#define REG_SSC1_TFMR (0xF800C01CU) /**< \brief (SSC1) Transmit Frame Mode Register */ +#define REG_SSC1_RHR (0xF800C020U) /**< \brief (SSC1) Receive Holding Register */ +#define REG_SSC1_THR (0xF800C024U) /**< \brief (SSC1) Transmit Holding Register */ +#define REG_SSC1_RSHR (0xF800C030U) /**< \brief (SSC1) Receive Sync. Holding Register */ +#define REG_SSC1_TSHR (0xF800C034U) /**< \brief (SSC1) Transmit Sync. Holding Register */ +#define REG_SSC1_RC0R (0xF800C038U) /**< \brief (SSC1) Receive Compare 0 Register */ +#define REG_SSC1_RC1R (0xF800C03CU) /**< \brief (SSC1) Receive Compare 1 Register */ +#define REG_SSC1_SR (0xF800C040U) /**< \brief (SSC1) Status Register */ +#define REG_SSC1_IER (0xF800C044U) /**< \brief (SSC1) Interrupt Enable Register */ +#define REG_SSC1_IDR (0xF800C048U) /**< \brief (SSC1) Interrupt Disable Register */ +#define REG_SSC1_IMR (0xF800C04CU) /**< \brief (SSC1) Interrupt Mask Register */ +#define REG_SSC1_WPMR (0xF800C0E4U) /**< \brief (SSC1) Write Protect Mode Register */ +#define REG_SSC1_WPSR (0xF800C0E8U) /**< \brief (SSC1) Write Protect Status Register */ +#else +#define REG_SSC1_CR (*(WoReg*)0xF800C000U) /**< \brief (SSC1) Control Register */ +#define REG_SSC1_CMR (*(RwReg*)0xF800C004U) /**< \brief (SSC1) Clock Mode Register */ +#define REG_SSC1_RCMR (*(RwReg*)0xF800C010U) /**< \brief (SSC1) Receive Clock Mode Register */ +#define REG_SSC1_RFMR (*(RwReg*)0xF800C014U) /**< \brief (SSC1) Receive Frame Mode Register */ +#define REG_SSC1_TCMR (*(RwReg*)0xF800C018U) /**< \brief (SSC1) Transmit Clock Mode Register */ +#define REG_SSC1_TFMR (*(RwReg*)0xF800C01CU) /**< \brief (SSC1) Transmit Frame Mode Register */ +#define REG_SSC1_RHR (*(RoReg*)0xF800C020U) /**< \brief (SSC1) Receive Holding Register */ +#define REG_SSC1_THR (*(WoReg*)0xF800C024U) /**< \brief (SSC1) Transmit Holding Register */ +#define REG_SSC1_RSHR (*(RoReg*)0xF800C030U) /**< \brief (SSC1) Receive Sync. Holding Register */ +#define REG_SSC1_TSHR (*(RwReg*)0xF800C034U) /**< \brief (SSC1) Transmit Sync. Holding Register */ +#define REG_SSC1_RC0R (*(RwReg*)0xF800C038U) /**< \brief (SSC1) Receive Compare 0 Register */ +#define REG_SSC1_RC1R (*(RwReg*)0xF800C03CU) /**< \brief (SSC1) Receive Compare 1 Register */ +#define REG_SSC1_SR (*(RoReg*)0xF800C040U) /**< \brief (SSC1) Status Register */ +#define REG_SSC1_IER (*(WoReg*)0xF800C044U) /**< \brief (SSC1) Interrupt Enable Register */ +#define REG_SSC1_IDR (*(WoReg*)0xF800C048U) /**< \brief (SSC1) Interrupt Disable Register */ +#define REG_SSC1_IMR (*(RoReg*)0xF800C04CU) /**< \brief (SSC1) Interrupt Mask Register */ +#define REG_SSC1_WPMR (*(RwReg*)0xF800C0E4U) /**< \brief (SSC1) Write Protect Mode Register */ +#define REG_SSC1_WPSR (*(RoReg*)0xF800C0E8U) /**< \brief (SSC1) Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_SSC1_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_tc0.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_tc0.h new file mode 100644 index 0000000..8b926fe --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_tc0.h
@@ -0,0 +1,108 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_TC0_INSTANCE_ +#define _SAMA5_TC0_INSTANCE_ + +/* ========== Register definition for TC0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC0_CCR0 (0xF0010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */ +#define REG_TC0_CMR0 (0xF0010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */ +#define REG_TC0_RAB0 (0xF001000CU) /**< \brief (TC0) Register AB (channel = 0) */ +#define REG_TC0_CV0 (0xF0010010U) /**< \brief (TC0) Counter Value (channel = 0) */ +#define REG_TC0_RA0 (0xF0010014U) /**< \brief (TC0) Register A (channel = 0) */ +#define REG_TC0_RB0 (0xF0010018U) /**< \brief (TC0) Register B (channel = 0) */ +#define REG_TC0_RC0 (0xF001001CU) /**< \brief (TC0) Register C (channel = 0) */ +#define REG_TC0_SR0 (0xF0010020U) /**< \brief (TC0) Status Register (channel = 0) */ +#define REG_TC0_IER0 (0xF0010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */ +#define REG_TC0_IDR0 (0xF0010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */ +#define REG_TC0_IMR0 (0xF001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */ +#define REG_TC0_CCR1 (0xF0010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */ +#define REG_TC0_CMR1 (0xF0010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */ +#define REG_TC0_RAB1 (0xF001004CU) /**< \brief (TC0) Register AB (channel = 1) */ +#define REG_TC0_CV1 (0xF0010050U) /**< \brief (TC0) Counter Value (channel = 1) */ +#define REG_TC0_RA1 (0xF0010054U) /**< \brief (TC0) Register A (channel = 1) */ +#define REG_TC0_RB1 (0xF0010058U) /**< \brief (TC0) Register B (channel = 1) */ +#define REG_TC0_RC1 (0xF001005CU) /**< \brief (TC0) Register C (channel = 1) */ +#define REG_TC0_SR1 (0xF0010060U) /**< \brief (TC0) Status Register (channel = 1) */ +#define REG_TC0_IER1 (0xF0010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */ +#define REG_TC0_IDR1 (0xF0010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */ +#define REG_TC0_IMR1 (0xF001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */ +#define REG_TC0_CCR2 (0xF0010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */ +#define REG_TC0_CMR2 (0xF0010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */ +#define REG_TC0_RAB2 (0xF001008CU) /**< \brief (TC0) Register AB (channel = 2) */ +#define REG_TC0_CV2 (0xF0010090U) /**< \brief (TC0) Counter Value (channel = 2) */ +#define REG_TC0_RA2 (0xF0010094U) /**< \brief (TC0) Register A (channel = 2) */ +#define REG_TC0_RB2 (0xF0010098U) /**< \brief (TC0) Register B (channel = 2) */ +#define REG_TC0_RC2 (0xF001009CU) /**< \brief (TC0) Register C (channel = 2) */ +#define REG_TC0_SR2 (0xF00100A0U) /**< \brief (TC0) Status Register (channel = 2) */ +#define REG_TC0_IER2 (0xF00100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */ +#define REG_TC0_IDR2 (0xF00100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */ +#define REG_TC0_IMR2 (0xF00100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */ +#define REG_TC0_BCR (0xF00100C0U) /**< \brief (TC0) Block Control Register */ +#define REG_TC0_BMR (0xF00100C4U) /**< \brief (TC0) Block Mode Register */ +#else +#define REG_TC0_CCR0 (*(WoReg*)0xF0010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */ +#define REG_TC0_CMR0 (*(RwReg*)0xF0010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */ +#define REG_TC0_RAB0 (*(RoReg*)0xF001000CU) /**< \brief (TC0) Register AB (channel = 0) */ +#define REG_TC0_CV0 (*(RoReg*)0xF0010010U) /**< \brief (TC0) Counter Value (channel = 0) */ +#define REG_TC0_RA0 (*(RwReg*)0xF0010014U) /**< \brief (TC0) Register A (channel = 0) */ +#define REG_TC0_RB0 (*(RwReg*)0xF0010018U) /**< \brief (TC0) Register B (channel = 0) */ +#define REG_TC0_RC0 (*(RwReg*)0xF001001CU) /**< \brief (TC0) Register C (channel = 0) */ +#define REG_TC0_SR0 (*(RoReg*)0xF0010020U) /**< \brief (TC0) Status Register (channel = 0) */ +#define REG_TC0_IER0 (*(WoReg*)0xF0010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */ +#define REG_TC0_IDR0 (*(WoReg*)0xF0010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */ +#define REG_TC0_IMR0 (*(RoReg*)0xF001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */ +#define REG_TC0_CCR1 (*(WoReg*)0xF0010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */ +#define REG_TC0_CMR1 (*(RwReg*)0xF0010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */ +#define REG_TC0_RAB1 (*(RoReg*)0xF001004CU) /**< \brief (TC0) Register AB (channel = 1) */ +#define REG_TC0_CV1 (*(RoReg*)0xF0010050U) /**< \brief (TC0) Counter Value (channel = 1) */ +#define REG_TC0_RA1 (*(RwReg*)0xF0010054U) /**< \brief (TC0) Register A (channel = 1) */ +#define REG_TC0_RB1 (*(RwReg*)0xF0010058U) /**< \brief (TC0) Register B (channel = 1) */ +#define REG_TC0_RC1 (*(RwReg*)0xF001005CU) /**< \brief (TC0) Register C (channel = 1) */ +#define REG_TC0_SR1 (*(RoReg*)0xF0010060U) /**< \brief (TC0) Status Register (channel = 1) */ +#define REG_TC0_IER1 (*(WoReg*)0xF0010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */ +#define REG_TC0_IDR1 (*(WoReg*)0xF0010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */ +#define REG_TC0_IMR1 (*(RoReg*)0xF001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */ +#define REG_TC0_CCR2 (*(WoReg*)0xF0010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */ +#define REG_TC0_CMR2 (*(RwReg*)0xF0010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */ +#define REG_TC0_RAB2 (*(RoReg*)0xF001008CU) /**< \brief (TC0) Register AB (channel = 2) */ +#define REG_TC0_CV2 (*(RoReg*)0xF0010090U) /**< \brief (TC0) Counter Value (channel = 2) */ +#define REG_TC0_RA2 (*(RwReg*)0xF0010094U) /**< \brief (TC0) Register A (channel = 2) */ +#define REG_TC0_RB2 (*(RwReg*)0xF0010098U) /**< \brief (TC0) Register B (channel = 2) */ +#define REG_TC0_RC2 (*(RwReg*)0xF001009CU) /**< \brief (TC0) Register C (channel = 2) */ +#define REG_TC0_SR2 (*(RoReg*)0xF00100A0U) /**< \brief (TC0) Status Register (channel = 2) */ +#define REG_TC0_IER2 (*(WoReg*)0xF00100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */ +#define REG_TC0_IDR2 (*(WoReg*)0xF00100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */ +#define REG_TC0_IMR2 (*(RoReg*)0xF00100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */ +#define REG_TC0_BCR (*(WoReg*)0xF00100C0U) /**< \brief (TC0) Block Control Register */ +#define REG_TC0_BMR (*(RwReg*)0xF00100C4U) /**< \brief (TC0) Block Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_TC0_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_tc1.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_tc1.h new file mode 100644 index 0000000..ef00b12 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_tc1.h
@@ -0,0 +1,108 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_TC1_INSTANCE_ +#define _SAMA5_TC1_INSTANCE_ + +/* ========== Register definition for TC1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC1_CCR0 (0xF8014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */ +#define REG_TC1_CMR0 (0xF8014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */ +#define REG_TC1_RAB0 (0xF801400CU) /**< \brief (TC1) Register AB (channel = 0) */ +#define REG_TC1_CV0 (0xF8014010U) /**< \brief (TC1) Counter Value (channel = 0) */ +#define REG_TC1_RA0 (0xF8014014U) /**< \brief (TC1) Register A (channel = 0) */ +#define REG_TC1_RB0 (0xF8014018U) /**< \brief (TC1) Register B (channel = 0) */ +#define REG_TC1_RC0 (0xF801401CU) /**< \brief (TC1) Register C (channel = 0) */ +#define REG_TC1_SR0 (0xF8014020U) /**< \brief (TC1) Status Register (channel = 0) */ +#define REG_TC1_IER0 (0xF8014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */ +#define REG_TC1_IDR0 (0xF8014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */ +#define REG_TC1_IMR0 (0xF801402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */ +#define REG_TC1_CCR1 (0xF8014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */ +#define REG_TC1_CMR1 (0xF8014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */ +#define REG_TC1_RAB1 (0xF801404CU) /**< \brief (TC1) Register AB (channel = 1) */ +#define REG_TC1_CV1 (0xF8014050U) /**< \brief (TC1) Counter Value (channel = 1) */ +#define REG_TC1_RA1 (0xF8014054U) /**< \brief (TC1) Register A (channel = 1) */ +#define REG_TC1_RB1 (0xF8014058U) /**< \brief (TC1) Register B (channel = 1) */ +#define REG_TC1_RC1 (0xF801405CU) /**< \brief (TC1) Register C (channel = 1) */ +#define REG_TC1_SR1 (0xF8014060U) /**< \brief (TC1) Status Register (channel = 1) */ +#define REG_TC1_IER1 (0xF8014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */ +#define REG_TC1_IDR1 (0xF8014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */ +#define REG_TC1_IMR1 (0xF801406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */ +#define REG_TC1_CCR2 (0xF8014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */ +#define REG_TC1_CMR2 (0xF8014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */ +#define REG_TC1_RAB2 (0xF801408CU) /**< \brief (TC1) Register AB (channel = 2) */ +#define REG_TC1_CV2 (0xF8014090U) /**< \brief (TC1) Counter Value (channel = 2) */ +#define REG_TC1_RA2 (0xF8014094U) /**< \brief (TC1) Register A (channel = 2) */ +#define REG_TC1_RB2 (0xF8014098U) /**< \brief (TC1) Register B (channel = 2) */ +#define REG_TC1_RC2 (0xF801409CU) /**< \brief (TC1) Register C (channel = 2) */ +#define REG_TC1_SR2 (0xF80140A0U) /**< \brief (TC1) Status Register (channel = 2) */ +#define REG_TC1_IER2 (0xF80140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */ +#define REG_TC1_IDR2 (0xF80140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */ +#define REG_TC1_IMR2 (0xF80140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */ +#define REG_TC1_BCR (0xF80140C0U) /**< \brief (TC1) Block Control Register */ +#define REG_TC1_BMR (0xF80140C4U) /**< \brief (TC1) Block Mode Register */ +#else +#define REG_TC1_CCR0 (*(WoReg*)0xF8014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */ +#define REG_TC1_CMR0 (*(RwReg*)0xF8014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */ +#define REG_TC1_RAB0 (*(RoReg*)0xF801400CU) /**< \brief (TC1) Register AB (channel = 0) */ +#define REG_TC1_CV0 (*(RoReg*)0xF8014010U) /**< \brief (TC1) Counter Value (channel = 0) */ +#define REG_TC1_RA0 (*(RwReg*)0xF8014014U) /**< \brief (TC1) Register A (channel = 0) */ +#define REG_TC1_RB0 (*(RwReg*)0xF8014018U) /**< \brief (TC1) Register B (channel = 0) */ +#define REG_TC1_RC0 (*(RwReg*)0xF801401CU) /**< \brief (TC1) Register C (channel = 0) */ +#define REG_TC1_SR0 (*(RoReg*)0xF8014020U) /**< \brief (TC1) Status Register (channel = 0) */ +#define REG_TC1_IER0 (*(WoReg*)0xF8014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */ +#define REG_TC1_IDR0 (*(WoReg*)0xF8014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */ +#define REG_TC1_IMR0 (*(RoReg*)0xF801402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */ +#define REG_TC1_CCR1 (*(WoReg*)0xF8014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */ +#define REG_TC1_CMR1 (*(RwReg*)0xF8014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */ +#define REG_TC1_RAB1 (*(RoReg*)0xF801404CU) /**< \brief (TC1) Register AB (channel = 1) */ +#define REG_TC1_CV1 (*(RoReg*)0xF8014050U) /**< \brief (TC1) Counter Value (channel = 1) */ +#define REG_TC1_RA1 (*(RwReg*)0xF8014054U) /**< \brief (TC1) Register A (channel = 1) */ +#define REG_TC1_RB1 (*(RwReg*)0xF8014058U) /**< \brief (TC1) Register B (channel = 1) */ +#define REG_TC1_RC1 (*(RwReg*)0xF801405CU) /**< \brief (TC1) Register C (channel = 1) */ +#define REG_TC1_SR1 (*(RoReg*)0xF8014060U) /**< \brief (TC1) Status Register (channel = 1) */ +#define REG_TC1_IER1 (*(WoReg*)0xF8014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */ +#define REG_TC1_IDR1 (*(WoReg*)0xF8014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */ +#define REG_TC1_IMR1 (*(RoReg*)0xF801406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */ +#define REG_TC1_CCR2 (*(WoReg*)0xF8014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */ +#define REG_TC1_CMR2 (*(RwReg*)0xF8014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */ +#define REG_TC1_RAB2 (*(RoReg*)0xF801408CU) /**< \brief (TC1) Register AB (channel = 2) */ +#define REG_TC1_CV2 (*(RoReg*)0xF8014090U) /**< \brief (TC1) Counter Value (channel = 2) */ +#define REG_TC1_RA2 (*(RwReg*)0xF8014094U) /**< \brief (TC1) Register A (channel = 2) */ +#define REG_TC1_RB2 (*(RwReg*)0xF8014098U) /**< \brief (TC1) Register B (channel = 2) */ +#define REG_TC1_RC2 (*(RwReg*)0xF801409CU) /**< \brief (TC1) Register C (channel = 2) */ +#define REG_TC1_SR2 (*(RoReg*)0xF80140A0U) /**< \brief (TC1) Status Register (channel = 2) */ +#define REG_TC1_IER2 (*(WoReg*)0xF80140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */ +#define REG_TC1_IDR2 (*(WoReg*)0xF80140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */ +#define REG_TC1_IMR2 (*(RoReg*)0xF80140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */ +#define REG_TC1_BCR (*(WoReg*)0xF80140C0U) /**< \brief (TC1) Block Control Register */ +#define REG_TC1_BMR (*(RwReg*)0xF80140C4U) /**< \brief (TC1) Block Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_TC1_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_tdes.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_tdes.h new file mode 100644 index 0000000..c3add8c --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_tdes.h
@@ -0,0 +1,64 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_TDES_INSTANCE_ +#define _SAMA5_TDES_INSTANCE_ + +/* ========== Register definition for TDES peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TDES_CR (0xF803C000U) /**< \brief (TDES) Control Register */ +#define REG_TDES_MR (0xF803C004U) /**< \brief (TDES) Mode Register */ +#define REG_TDES_IER (0xF803C010U) /**< \brief (TDES) Interrupt Enable Register */ +#define REG_TDES_IDR (0xF803C014U) /**< \brief (TDES) Interrupt Disable Register */ +#define REG_TDES_IMR (0xF803C018U) /**< \brief (TDES) Interrupt Mask Register */ +#define REG_TDES_ISR (0xF803C01CU) /**< \brief (TDES) Interrupt Status Register */ +#define REG_TDES_KEY1WR (0xF803C020U) /**< \brief (TDES) Key 1 Word Register */ +#define REG_TDES_KEY2WR (0xF803C028U) /**< \brief (TDES) Key 2 Word Register */ +#define REG_TDES_KEY3WR (0xF803C030U) /**< \brief (TDES) Key 3 Word Register */ +#define REG_TDES_IDATAR (0xF803C040U) /**< \brief (TDES) Input Data Register */ +#define REG_TDES_ODATAR (0xF803C050U) /**< \brief (TDES) Output Data Register */ +#define REG_TDES_IVR (0xF803C060U) /**< \brief (TDES) Initialization Vector Register */ +#define REG_TDES_XTEARNDR (0xF803C070U) /**< \brief (TDES) XTEA Rounds Register */ +#else +#define REG_TDES_CR (*(WoReg*)0xF803C000U) /**< \brief (TDES) Control Register */ +#define REG_TDES_MR (*(RwReg*)0xF803C004U) /**< \brief (TDES) Mode Register */ +#define REG_TDES_IER (*(WoReg*)0xF803C010U) /**< \brief (TDES) Interrupt Enable Register */ +#define REG_TDES_IDR (*(WoReg*)0xF803C014U) /**< \brief (TDES) Interrupt Disable Register */ +#define REG_TDES_IMR (*(RoReg*)0xF803C018U) /**< \brief (TDES) Interrupt Mask Register */ +#define REG_TDES_ISR (*(RoReg*)0xF803C01CU) /**< \brief (TDES) Interrupt Status Register */ +#define REG_TDES_KEY1WR (*(WoReg*)0xF803C020U) /**< \brief (TDES) Key 1 Word Register */ +#define REG_TDES_KEY2WR (*(WoReg*)0xF803C028U) /**< \brief (TDES) Key 2 Word Register */ +#define REG_TDES_KEY3WR (*(WoReg*)0xF803C030U) /**< \brief (TDES) Key 3 Word Register */ +#define REG_TDES_IDATAR (*(WoReg*)0xF803C040U) /**< \brief (TDES) Input Data Register */ +#define REG_TDES_ODATAR (*(RoReg*)0xF803C050U) /**< \brief (TDES) Output Data Register */ +#define REG_TDES_IVR (*(WoReg*)0xF803C060U) /**< \brief (TDES) Initialization Vector Register */ +#define REG_TDES_XTEARNDR (*(RwReg*)0xF803C070U) /**< \brief (TDES) XTEA Rounds Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_TDES_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_trng.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_trng.h new file mode 100644 index 0000000..8730a0a --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_trng.h
@@ -0,0 +1,50 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_TRNG_INSTANCE_ +#define _SAMA5_TRNG_INSTANCE_ + +/* ========== Register definition for TRNG peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TRNG_CR (0xF8040000U) /**< \brief (TRNG) Control Register */ +#define REG_TRNG_IER (0xF8040010U) /**< \brief (TRNG) Interrupt Enable Register */ +#define REG_TRNG_IDR (0xF8040014U) /**< \brief (TRNG) Interrupt Disable Register */ +#define REG_TRNG_IMR (0xF8040018U) /**< \brief (TRNG) Interrupt Mask Register */ +#define REG_TRNG_ISR (0xF804001CU) /**< \brief (TRNG) Interrupt Status Register */ +#define REG_TRNG_ODATA (0xF8040050U) /**< \brief (TRNG) Output Data Register */ +#else +#define REG_TRNG_CR (*(WoReg*)0xF8040000U) /**< \brief (TRNG) Control Register */ +#define REG_TRNG_IER (*(WoReg*)0xF8040010U) /**< \brief (TRNG) Interrupt Enable Register */ +#define REG_TRNG_IDR (*(WoReg*)0xF8040014U) /**< \brief (TRNG) Interrupt Disable Register */ +#define REG_TRNG_IMR (*(RoReg*)0xF8040018U) /**< \brief (TRNG) Interrupt Mask Register */ +#define REG_TRNG_ISR (*(RoReg*)0xF804001CU) /**< \brief (TRNG) Interrupt Status Register */ +#define REG_TRNG_ODATA (*(RoReg*)0xF8040050U) /**< \brief (TRNG) Output Data Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_TRNG_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_twi0.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_twi0.h new file mode 100644 index 0000000..652561e --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_twi0.h
@@ -0,0 +1,64 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_TWI0_INSTANCE_ +#define _SAMA5_TWI0_INSTANCE_ + +/* ========== Register definition for TWI0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TWI0_CR (0xF0014000U) /**< \brief (TWI0) Control Register */ +#define REG_TWI0_MMR (0xF0014004U) /**< \brief (TWI0) Master Mode Register */ +#define REG_TWI0_SMR (0xF0014008U) /**< \brief (TWI0) Slave Mode Register */ +#define REG_TWI0_IADR (0xF001400CU) /**< \brief (TWI0) Internal Address Register */ +#define REG_TWI0_CWGR (0xF0014010U) /**< \brief (TWI0) Clock Waveform Generator Register */ +#define REG_TWI0_SR (0xF0014020U) /**< \brief (TWI0) Status Register */ +#define REG_TWI0_IER (0xF0014024U) /**< \brief (TWI0) Interrupt Enable Register */ +#define REG_TWI0_IDR (0xF0014028U) /**< \brief (TWI0) Interrupt Disable Register */ +#define REG_TWI0_IMR (0xF001402CU) /**< \brief (TWI0) Interrupt Mask Register */ +#define REG_TWI0_RHR (0xF0014030U) /**< \brief (TWI0) Receive Holding Register */ +#define REG_TWI0_THR (0xF0014034U) /**< \brief (TWI0) Transmit Holding Register */ +#define REG_TWI0_WPROT_MODE (0xF00140E4U) /**< \brief (TWI0) Protection Mode Register */ +#define REG_TWI0_WPROT_STATUS (0xF00140E8U) /**< \brief (TWI0) Protection Status Register */ +#else +#define REG_TWI0_CR (*(WoReg*)0xF0014000U) /**< \brief (TWI0) Control Register */ +#define REG_TWI0_MMR (*(RwReg*)0xF0014004U) /**< \brief (TWI0) Master Mode Register */ +#define REG_TWI0_SMR (*(RwReg*)0xF0014008U) /**< \brief (TWI0) Slave Mode Register */ +#define REG_TWI0_IADR (*(RwReg*)0xF001400CU) /**< \brief (TWI0) Internal Address Register */ +#define REG_TWI0_CWGR (*(RwReg*)0xF0014010U) /**< \brief (TWI0) Clock Waveform Generator Register */ +#define REG_TWI0_SR (*(RoReg*)0xF0014020U) /**< \brief (TWI0) Status Register */ +#define REG_TWI0_IER (*(WoReg*)0xF0014024U) /**< \brief (TWI0) Interrupt Enable Register */ +#define REG_TWI0_IDR (*(WoReg*)0xF0014028U) /**< \brief (TWI0) Interrupt Disable Register */ +#define REG_TWI0_IMR (*(RoReg*)0xF001402CU) /**< \brief (TWI0) Interrupt Mask Register */ +#define REG_TWI0_RHR (*(RoReg*)0xF0014030U) /**< \brief (TWI0) Receive Holding Register */ +#define REG_TWI0_THR (*(WoReg*)0xF0014034U) /**< \brief (TWI0) Transmit Holding Register */ +#define REG_TWI0_WPROT_MODE (*(RwReg*)0xF00140E4U) /**< \brief (TWI0) Protection Mode Register */ +#define REG_TWI0_WPROT_STATUS (*(RoReg*)0xF00140E8U) /**< \brief (TWI0) Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_TWI0_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_twi1.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_twi1.h new file mode 100644 index 0000000..2aca8af --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_twi1.h
@@ -0,0 +1,64 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_TWI1_INSTANCE_ +#define _SAMA5_TWI1_INSTANCE_ + +/* ========== Register definition for TWI1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TWI1_CR (0xF0018000U) /**< \brief (TWI1) Control Register */ +#define REG_TWI1_MMR (0xF0018004U) /**< \brief (TWI1) Master Mode Register */ +#define REG_TWI1_SMR (0xF0018008U) /**< \brief (TWI1) Slave Mode Register */ +#define REG_TWI1_IADR (0xF001800CU) /**< \brief (TWI1) Internal Address Register */ +#define REG_TWI1_CWGR (0xF0018010U) /**< \brief (TWI1) Clock Waveform Generator Register */ +#define REG_TWI1_SR (0xF0018020U) /**< \brief (TWI1) Status Register */ +#define REG_TWI1_IER (0xF0018024U) /**< \brief (TWI1) Interrupt Enable Register */ +#define REG_TWI1_IDR (0xF0018028U) /**< \brief (TWI1) Interrupt Disable Register */ +#define REG_TWI1_IMR (0xF001802CU) /**< \brief (TWI1) Interrupt Mask Register */ +#define REG_TWI1_RHR (0xF0018030U) /**< \brief (TWI1) Receive Holding Register */ +#define REG_TWI1_THR (0xF0018034U) /**< \brief (TWI1) Transmit Holding Register */ +#define REG_TWI1_WPROT_MODE (0xF00180E4U) /**< \brief (TWI1) Protection Mode Register */ +#define REG_TWI1_WPROT_STATUS (0xF00180E8U) /**< \brief (TWI1) Protection Status Register */ +#else +#define REG_TWI1_CR (*(WoReg*)0xF0018000U) /**< \brief (TWI1) Control Register */ +#define REG_TWI1_MMR (*(RwReg*)0xF0018004U) /**< \brief (TWI1) Master Mode Register */ +#define REG_TWI1_SMR (*(RwReg*)0xF0018008U) /**< \brief (TWI1) Slave Mode Register */ +#define REG_TWI1_IADR (*(RwReg*)0xF001800CU) /**< \brief (TWI1) Internal Address Register */ +#define REG_TWI1_CWGR (*(RwReg*)0xF0018010U) /**< \brief (TWI1) Clock Waveform Generator Register */ +#define REG_TWI1_SR (*(RoReg*)0xF0018020U) /**< \brief (TWI1) Status Register */ +#define REG_TWI1_IER (*(WoReg*)0xF0018024U) /**< \brief (TWI1) Interrupt Enable Register */ +#define REG_TWI1_IDR (*(WoReg*)0xF0018028U) /**< \brief (TWI1) Interrupt Disable Register */ +#define REG_TWI1_IMR (*(RoReg*)0xF001802CU) /**< \brief (TWI1) Interrupt Mask Register */ +#define REG_TWI1_RHR (*(RoReg*)0xF0018030U) /**< \brief (TWI1) Receive Holding Register */ +#define REG_TWI1_THR (*(WoReg*)0xF0018034U) /**< \brief (TWI1) Transmit Holding Register */ +#define REG_TWI1_WPROT_MODE (*(RwReg*)0xF00180E4U) /**< \brief (TWI1) Protection Mode Register */ +#define REG_TWI1_WPROT_STATUS (*(RoReg*)0xF00180E8U) /**< \brief (TWI1) Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_TWI1_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_twi2.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_twi2.h new file mode 100644 index 0000000..5fccf83 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_twi2.h
@@ -0,0 +1,64 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_TWI2_INSTANCE_ +#define _SAMA5_TWI2_INSTANCE_ + +/* ========== Register definition for TWI2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TWI2_CR (0xF801C000U) /**< \brief (TWI2) Control Register */ +#define REG_TWI2_MMR (0xF801C004U) /**< \brief (TWI2) Master Mode Register */ +#define REG_TWI2_SMR (0xF801C008U) /**< \brief (TWI2) Slave Mode Register */ +#define REG_TWI2_IADR (0xF801C00CU) /**< \brief (TWI2) Internal Address Register */ +#define REG_TWI2_CWGR (0xF801C010U) /**< \brief (TWI2) Clock Waveform Generator Register */ +#define REG_TWI2_SR (0xF801C020U) /**< \brief (TWI2) Status Register */ +#define REG_TWI2_IER (0xF801C024U) /**< \brief (TWI2) Interrupt Enable Register */ +#define REG_TWI2_IDR (0xF801C028U) /**< \brief (TWI2) Interrupt Disable Register */ +#define REG_TWI2_IMR (0xF801C02CU) /**< \brief (TWI2) Interrupt Mask Register */ +#define REG_TWI2_RHR (0xF801C030U) /**< \brief (TWI2) Receive Holding Register */ +#define REG_TWI2_THR (0xF801C034U) /**< \brief (TWI2) Transmit Holding Register */ +#define REG_TWI2_WPROT_MODE (0xF801C0E4U) /**< \brief (TWI2) Protection Mode Register */ +#define REG_TWI2_WPROT_STATUS (0xF801C0E8U) /**< \brief (TWI2) Protection Status Register */ +#else +#define REG_TWI2_CR (*(WoReg*)0xF801C000U) /**< \brief (TWI2) Control Register */ +#define REG_TWI2_MMR (*(RwReg*)0xF801C004U) /**< \brief (TWI2) Master Mode Register */ +#define REG_TWI2_SMR (*(RwReg*)0xF801C008U) /**< \brief (TWI2) Slave Mode Register */ +#define REG_TWI2_IADR (*(RwReg*)0xF801C00CU) /**< \brief (TWI2) Internal Address Register */ +#define REG_TWI2_CWGR (*(RwReg*)0xF801C010U) /**< \brief (TWI2) Clock Waveform Generator Register */ +#define REG_TWI2_SR (*(RoReg*)0xF801C020U) /**< \brief (TWI2) Status Register */ +#define REG_TWI2_IER (*(WoReg*)0xF801C024U) /**< \brief (TWI2) Interrupt Enable Register */ +#define REG_TWI2_IDR (*(WoReg*)0xF801C028U) /**< \brief (TWI2) Interrupt Disable Register */ +#define REG_TWI2_IMR (*(RoReg*)0xF801C02CU) /**< \brief (TWI2) Interrupt Mask Register */ +#define REG_TWI2_RHR (*(RoReg*)0xF801C030U) /**< \brief (TWI2) Receive Holding Register */ +#define REG_TWI2_THR (*(WoReg*)0xF801C034U) /**< \brief (TWI2) Transmit Holding Register */ +#define REG_TWI2_WPROT_MODE (*(RwReg*)0xF801C0E4U) /**< \brief (TWI2) Protection Mode Register */ +#define REG_TWI2_WPROT_STATUS (*(RoReg*)0xF801C0E8U) /**< \brief (TWI2) Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_TWI2_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_uart0.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_uart0.h new file mode 100644 index 0000000..4df6164 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_uart0.h
@@ -0,0 +1,56 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_UART0_INSTANCE_ +#define _SAMA5_UART0_INSTANCE_ + +/* ========== Register definition for UART0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_UART0_CR (0xF0024000U) /**< \brief (UART0) Control Register */ +#define REG_UART0_MR (0xF0024004U) /**< \brief (UART0) Mode Register */ +#define REG_UART0_IER (0xF0024008U) /**< \brief (UART0) Interrupt Enable Register */ +#define REG_UART0_IDR (0xF002400CU) /**< \brief (UART0) Interrupt Disable Register */ +#define REG_UART0_IMR (0xF0024010U) /**< \brief (UART0) Interrupt Mask Register */ +#define REG_UART0_SR (0xF0024014U) /**< \brief (UART0) Status Register */ +#define REG_UART0_RHR (0xF0024018U) /**< \brief (UART0) Receive Holding Register */ +#define REG_UART0_THR (0xF002401CU) /**< \brief (UART0) Transmit Holding Register */ +#define REG_UART0_BRGR (0xF0024020U) /**< \brief (UART0) Baud Rate Generator Register */ +#else +#define REG_UART0_CR (*(WoReg*)0xF0024000U) /**< \brief (UART0) Control Register */ +#define REG_UART0_MR (*(RwReg*)0xF0024004U) /**< \brief (UART0) Mode Register */ +#define REG_UART0_IER (*(WoReg*)0xF0024008U) /**< \brief (UART0) Interrupt Enable Register */ +#define REG_UART0_IDR (*(WoReg*)0xF002400CU) /**< \brief (UART0) Interrupt Disable Register */ +#define REG_UART0_IMR (*(RoReg*)0xF0024010U) /**< \brief (UART0) Interrupt Mask Register */ +#define REG_UART0_SR (*(RoReg*)0xF0024014U) /**< \brief (UART0) Status Register */ +#define REG_UART0_RHR (*(RoReg*)0xF0024018U) /**< \brief (UART0) Receive Holding Register */ +#define REG_UART0_THR (*(WoReg*)0xF002401CU) /**< \brief (UART0) Transmit Holding Register */ +#define REG_UART0_BRGR (*(RwReg*)0xF0024020U) /**< \brief (UART0) Baud Rate Generator Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_UART0_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_uart1.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_uart1.h new file mode 100644 index 0000000..84a188f --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_uart1.h
@@ -0,0 +1,56 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_UART1_INSTANCE_ +#define _SAMA5_UART1_INSTANCE_ + +/* ========== Register definition for UART1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_UART1_CR (0xF8028000U) /**< \brief (UART1) Control Register */ +#define REG_UART1_MR (0xF8028004U) /**< \brief (UART1) Mode Register */ +#define REG_UART1_IER (0xF8028008U) /**< \brief (UART1) Interrupt Enable Register */ +#define REG_UART1_IDR (0xF802800CU) /**< \brief (UART1) Interrupt Disable Register */ +#define REG_UART1_IMR (0xF8028010U) /**< \brief (UART1) Interrupt Mask Register */ +#define REG_UART1_SR (0xF8028014U) /**< \brief (UART1) Status Register */ +#define REG_UART1_RHR (0xF8028018U) /**< \brief (UART1) Receive Holding Register */ +#define REG_UART1_THR (0xF802801CU) /**< \brief (UART1) Transmit Holding Register */ +#define REG_UART1_BRGR (0xF8028020U) /**< \brief (UART1) Baud Rate Generator Register */ +#else +#define REG_UART1_CR (*(WoReg*)0xF8028000U) /**< \brief (UART1) Control Register */ +#define REG_UART1_MR (*(RwReg*)0xF8028004U) /**< \brief (UART1) Mode Register */ +#define REG_UART1_IER (*(WoReg*)0xF8028008U) /**< \brief (UART1) Interrupt Enable Register */ +#define REG_UART1_IDR (*(WoReg*)0xF802800CU) /**< \brief (UART1) Interrupt Disable Register */ +#define REG_UART1_IMR (*(RoReg*)0xF8028010U) /**< \brief (UART1) Interrupt Mask Register */ +#define REG_UART1_SR (*(RoReg*)0xF8028014U) /**< \brief (UART1) Status Register */ +#define REG_UART1_RHR (*(RoReg*)0xF8028018U) /**< \brief (UART1) Receive Holding Register */ +#define REG_UART1_THR (*(WoReg*)0xF802801CU) /**< \brief (UART1) Transmit Holding Register */ +#define REG_UART1_BRGR (*(RwReg*)0xF8028020U) /**< \brief (UART1) Baud Rate Generator Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_UART1_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_udphs.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_udphs.h new file mode 100644 index 0000000..7d72b16 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_udphs.h
@@ -0,0 +1,338 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_UDPHS_INSTANCE_ +#define _SAMA5_UDPHS_INSTANCE_ + +/* ========== Register definition for UDPHS peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_UDPHS_CTRL (0xF8030000U) /**< \brief (UDPHS) UDPHS Control Register */ +#define REG_UDPHS_FNUM (0xF8030004U) /**< \brief (UDPHS) UDPHS Frame Number Register */ +#define REG_UDPHS_IEN (0xF8030010U) /**< \brief (UDPHS) UDPHS Interrupt Enable Register */ +#define REG_UDPHS_INTSTA (0xF8030014U) /**< \brief (UDPHS) UDPHS Interrupt Status Register */ +#define REG_UDPHS_CLRINT (0xF8030018U) /**< \brief (UDPHS) UDPHS Clear Interrupt Register */ +#define REG_UDPHS_EPTRST (0xF803001CU) /**< \brief (UDPHS) UDPHS Endpoints Reset Register */ +#define REG_UDPHS_TST (0xF80300E0U) /**< \brief (UDPHS) UDPHS Test Register */ +#define REG_UDPHS_IPNAME1 (0xF80300F0U) /**< \brief (UDPHS) UDPHS Name1 Register */ +#define REG_UDPHS_IPNAME2 (0xF80300F4U) /**< \brief (UDPHS) UDPHS Name2 Register */ +#define REG_UDPHS_IPFEATURES (0xF80300F8U) /**< \brief (UDPHS) UDPHS Features Register */ +#define REG_UDPHS_EPTCFG0 (0xF8030100U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 0) */ +#define REG_UDPHS_EPTCTLENB0 (0xF8030104U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 0) */ +#define REG_UDPHS_EPTCTLDIS0 (0xF8030108U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 0) */ +#define REG_UDPHS_EPTCTL0 (0xF803010CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 0) */ +#define REG_UDPHS_EPTSETSTA0 (0xF8030114U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 0) */ +#define REG_UDPHS_EPTCLRSTA0 (0xF8030118U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 0) */ +#define REG_UDPHS_EPTSTA0 (0xF803011CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 0) */ +#define REG_UDPHS_EPTCFG1 (0xF8030120U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 1) */ +#define REG_UDPHS_EPTCTLENB1 (0xF8030124U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 1) */ +#define REG_UDPHS_EPTCTLDIS1 (0xF8030128U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 1) */ +#define REG_UDPHS_EPTCTL1 (0xF803012CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 1) */ +#define REG_UDPHS_EPTSETSTA1 (0xF8030134U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 1) */ +#define REG_UDPHS_EPTCLRSTA1 (0xF8030138U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 1) */ +#define REG_UDPHS_EPTSTA1 (0xF803013CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 1) */ +#define REG_UDPHS_EPTCFG2 (0xF8030140U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 2) */ +#define REG_UDPHS_EPTCTLENB2 (0xF8030144U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 2) */ +#define REG_UDPHS_EPTCTLDIS2 (0xF8030148U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 2) */ +#define REG_UDPHS_EPTCTL2 (0xF803014CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 2) */ +#define REG_UDPHS_EPTSETSTA2 (0xF8030154U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 2) */ +#define REG_UDPHS_EPTCLRSTA2 (0xF8030158U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 2) */ +#define REG_UDPHS_EPTSTA2 (0xF803015CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 2) */ +#define REG_UDPHS_EPTCFG3 (0xF8030160U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 3) */ +#define REG_UDPHS_EPTCTLENB3 (0xF8030164U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 3) */ +#define REG_UDPHS_EPTCTLDIS3 (0xF8030168U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 3) */ +#define REG_UDPHS_EPTCTL3 (0xF803016CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 3) */ +#define REG_UDPHS_EPTSETSTA3 (0xF8030174U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 3) */ +#define REG_UDPHS_EPTCLRSTA3 (0xF8030178U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 3) */ +#define REG_UDPHS_EPTSTA3 (0xF803017CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 3) */ +#define REG_UDPHS_EPTCFG4 (0xF8030180U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 4) */ +#define REG_UDPHS_EPTCTLENB4 (0xF8030184U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 4) */ +#define REG_UDPHS_EPTCTLDIS4 (0xF8030188U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 4) */ +#define REG_UDPHS_EPTCTL4 (0xF803018CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 4) */ +#define REG_UDPHS_EPTSETSTA4 (0xF8030194U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 4) */ +#define REG_UDPHS_EPTCLRSTA4 (0xF8030198U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 4) */ +#define REG_UDPHS_EPTSTA4 (0xF803019CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 4) */ +#define REG_UDPHS_EPTCFG5 (0xF80301A0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 5) */ +#define REG_UDPHS_EPTCTLENB5 (0xF80301A4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 5) */ +#define REG_UDPHS_EPTCTLDIS5 (0xF80301A8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 5) */ +#define REG_UDPHS_EPTCTL5 (0xF80301ACU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 5) */ +#define REG_UDPHS_EPTSETSTA5 (0xF80301B4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 5) */ +#define REG_UDPHS_EPTCLRSTA5 (0xF80301B8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 5) */ +#define REG_UDPHS_EPTSTA5 (0xF80301BCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 5) */ +#define REG_UDPHS_EPTCFG6 (0xF80301C0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 6) */ +#define REG_UDPHS_EPTCTLENB6 (0xF80301C4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 6) */ +#define REG_UDPHS_EPTCTLDIS6 (0xF80301C8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 6) */ +#define REG_UDPHS_EPTCTL6 (0xF80301CCU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 6) */ +#define REG_UDPHS_EPTSETSTA6 (0xF80301D4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 6) */ +#define REG_UDPHS_EPTCLRSTA6 (0xF80301D8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 6) */ +#define REG_UDPHS_EPTSTA6 (0xF80301DCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 6) */ +#define REG_UDPHS_EPTCFG7 (0xF80301E0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 7) */ +#define REG_UDPHS_EPTCTLENB7 (0xF80301E4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 7) */ +#define REG_UDPHS_EPTCTLDIS7 (0xF80301E8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 7) */ +#define REG_UDPHS_EPTCTL7 (0xF80301ECU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 7) */ +#define REG_UDPHS_EPTSETSTA7 (0xF80301F4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 7) */ +#define REG_UDPHS_EPTCLRSTA7 (0xF80301F8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 7) */ +#define REG_UDPHS_EPTSTA7 (0xF80301FCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 7) */ +#define REG_UDPHS_EPTCFG8 (0xF8030200U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 8) */ +#define REG_UDPHS_EPTCTLENB8 (0xF8030204U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 8) */ +#define REG_UDPHS_EPTCTLDIS8 (0xF8030208U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 8) */ +#define REG_UDPHS_EPTCTL8 (0xF803020CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 8) */ +#define REG_UDPHS_EPTSETSTA8 (0xF8030214U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 8) */ +#define REG_UDPHS_EPTCLRSTA8 (0xF8030218U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 8) */ +#define REG_UDPHS_EPTSTA8 (0xF803021CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 8) */ +#define REG_UDPHS_EPTCFG9 (0xF8030220U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 9) */ +#define REG_UDPHS_EPTCTLENB9 (0xF8030224U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 9) */ +#define REG_UDPHS_EPTCTLDIS9 (0xF8030228U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 9) */ +#define REG_UDPHS_EPTCTL9 (0xF803022CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 9) */ +#define REG_UDPHS_EPTSETSTA9 (0xF8030234U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 9) */ +#define REG_UDPHS_EPTCLRSTA9 (0xF8030238U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 9) */ +#define REG_UDPHS_EPTSTA9 (0xF803023CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 9) */ +#define REG_UDPHS_EPTCFG10 (0xF8030240U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 10) */ +#define REG_UDPHS_EPTCTLENB10 (0xF8030244U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 10) */ +#define REG_UDPHS_EPTCTLDIS10 (0xF8030248U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 10) */ +#define REG_UDPHS_EPTCTL10 (0xF803024CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 10) */ +#define REG_UDPHS_EPTSETSTA10 (0xF8030254U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 10) */ +#define REG_UDPHS_EPTCLRSTA10 (0xF8030258U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 10) */ +#define REG_UDPHS_EPTSTA10 (0xF803025CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 10) */ +#define REG_UDPHS_EPTCFG11 (0xF8030260U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 11) */ +#define REG_UDPHS_EPTCTLENB11 (0xF8030264U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 11) */ +#define REG_UDPHS_EPTCTLDIS11 (0xF8030268U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 11) */ +#define REG_UDPHS_EPTCTL11 (0xF803026CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 11) */ +#define REG_UDPHS_EPTSETSTA11 (0xF8030274U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 11) */ +#define REG_UDPHS_EPTCLRSTA11 (0xF8030278U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 11) */ +#define REG_UDPHS_EPTSTA11 (0xF803027CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 11) */ +#define REG_UDPHS_EPTCFG12 (0xF8030280U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 12) */ +#define REG_UDPHS_EPTCTLENB12 (0xF8030284U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 12) */ +#define REG_UDPHS_EPTCTLDIS12 (0xF8030288U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 12) */ +#define REG_UDPHS_EPTCTL12 (0xF803028CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 12) */ +#define REG_UDPHS_EPTSETSTA12 (0xF8030294U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 12) */ +#define REG_UDPHS_EPTCLRSTA12 (0xF8030298U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 12) */ +#define REG_UDPHS_EPTSTA12 (0xF803029CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 12) */ +#define REG_UDPHS_EPTCFG13 (0xF80302A0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 13) */ +#define REG_UDPHS_EPTCTLENB13 (0xF80302A4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 13) */ +#define REG_UDPHS_EPTCTLDIS13 (0xF80302A8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 13) */ +#define REG_UDPHS_EPTCTL13 (0xF80302ACU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 13) */ +#define REG_UDPHS_EPTSETSTA13 (0xF80302B4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 13) */ +#define REG_UDPHS_EPTCLRSTA13 (0xF80302B8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 13) */ +#define REG_UDPHS_EPTSTA13 (0xF80302BCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 13) */ +#define REG_UDPHS_EPTCFG14 (0xF80302C0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 14) */ +#define REG_UDPHS_EPTCTLENB14 (0xF80302C4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 14) */ +#define REG_UDPHS_EPTCTLDIS14 (0xF80302C8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 14) */ +#define REG_UDPHS_EPTCTL14 (0xF80302CCU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 14) */ +#define REG_UDPHS_EPTSETSTA14 (0xF80302D4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 14) */ +#define REG_UDPHS_EPTCLRSTA14 (0xF80302D8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 14) */ +#define REG_UDPHS_EPTSTA14 (0xF80302DCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 14) */ +#define REG_UDPHS_EPTCFG15 (0xF80302E0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 15) */ +#define REG_UDPHS_EPTCTLENB15 (0xF80302E4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 15) */ +#define REG_UDPHS_EPTCTLDIS15 (0xF80302E8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 15) */ +#define REG_UDPHS_EPTCTL15 (0xF80302ECU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 15) */ +#define REG_UDPHS_EPTSETSTA15 (0xF80302F4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 15) */ +#define REG_UDPHS_EPTCLRSTA15 (0xF80302F8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 15) */ +#define REG_UDPHS_EPTSTA15 (0xF80302FCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 15) */ +#define REG_UDPHS_DMANXTDSC0 (0xF8030300U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 0) */ +#define REG_UDPHS_DMAADDRESS0 (0xF8030304U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 0) */ +#define REG_UDPHS_DMACONTROL0 (0xF8030308U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 0) */ +#define REG_UDPHS_DMASTATUS0 (0xF803030CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 0) */ +#define REG_UDPHS_DMANXTDSC1 (0xF8030310U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 1) */ +#define REG_UDPHS_DMAADDRESS1 (0xF8030314U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 1) */ +#define REG_UDPHS_DMACONTROL1 (0xF8030318U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 1) */ +#define REG_UDPHS_DMASTATUS1 (0xF803031CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 1) */ +#define REG_UDPHS_DMANXTDSC2 (0xF8030320U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 2) */ +#define REG_UDPHS_DMAADDRESS2 (0xF8030324U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 2) */ +#define REG_UDPHS_DMACONTROL2 (0xF8030328U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 2) */ +#define REG_UDPHS_DMASTATUS2 (0xF803032CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 2) */ +#define REG_UDPHS_DMANXTDSC3 (0xF8030330U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 3) */ +#define REG_UDPHS_DMAADDRESS3 (0xF8030334U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 3) */ +#define REG_UDPHS_DMACONTROL3 (0xF8030338U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 3) */ +#define REG_UDPHS_DMASTATUS3 (0xF803033CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 3) */ +#define REG_UDPHS_DMANXTDSC4 (0xF8030340U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 4) */ +#define REG_UDPHS_DMAADDRESS4 (0xF8030344U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 4) */ +#define REG_UDPHS_DMACONTROL4 (0xF8030348U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 4) */ +#define REG_UDPHS_DMASTATUS4 (0xF803034CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 4) */ +#define REG_UDPHS_DMANXTDSC5 (0xF8030350U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 5) */ +#define REG_UDPHS_DMAADDRESS5 (0xF8030354U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 5) */ +#define REG_UDPHS_DMACONTROL5 (0xF8030358U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 5) */ +#define REG_UDPHS_DMASTATUS5 (0xF803035CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 5) */ +#define REG_UDPHS_DMANXTDSC6 (0xF8030360U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 6) */ +#define REG_UDPHS_DMAADDRESS6 (0xF8030364U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 6) */ +#define REG_UDPHS_DMACONTROL6 (0xF8030368U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 6) */ +#define REG_UDPHS_DMASTATUS6 (0xF803036CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 6) */ +#else +#define REG_UDPHS_CTRL (*(RwReg*)0xF8030000U) /**< \brief (UDPHS) UDPHS Control Register */ +#define REG_UDPHS_FNUM (*(RoReg*)0xF8030004U) /**< \brief (UDPHS) UDPHS Frame Number Register */ +#define REG_UDPHS_IEN (*(RwReg*)0xF8030010U) /**< \brief (UDPHS) UDPHS Interrupt Enable Register */ +#define REG_UDPHS_INTSTA (*(RoReg*)0xF8030014U) /**< \brief (UDPHS) UDPHS Interrupt Status Register */ +#define REG_UDPHS_CLRINT (*(WoReg*)0xF8030018U) /**< \brief (UDPHS) UDPHS Clear Interrupt Register */ +#define REG_UDPHS_EPTRST (*(WoReg*)0xF803001CU) /**< \brief (UDPHS) UDPHS Endpoints Reset Register */ +#define REG_UDPHS_TST (*(RwReg*)0xF80300E0U) /**< \brief (UDPHS) UDPHS Test Register */ +#define REG_UDPHS_IPNAME1 (*(RoReg*)0xF80300F0U) /**< \brief (UDPHS) UDPHS Name1 Register */ +#define REG_UDPHS_IPNAME2 (*(RoReg*)0xF80300F4U) /**< \brief (UDPHS) UDPHS Name2 Register */ +#define REG_UDPHS_IPFEATURES (*(RoReg*)0xF80300F8U) /**< \brief (UDPHS) UDPHS Features Register */ +#define REG_UDPHS_EPTCFG0 (*(RwReg*)0xF8030100U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 0) */ +#define REG_UDPHS_EPTCTLENB0 (*(WoReg*)0xF8030104U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 0) */ +#define REG_UDPHS_EPTCTLDIS0 (*(WoReg*)0xF8030108U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 0) */ +#define REG_UDPHS_EPTCTL0 (*(RoReg*)0xF803010CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 0) */ +#define REG_UDPHS_EPTSETSTA0 (*(WoReg*)0xF8030114U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 0) */ +#define REG_UDPHS_EPTCLRSTA0 (*(WoReg*)0xF8030118U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 0) */ +#define REG_UDPHS_EPTSTA0 (*(RoReg*)0xF803011CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 0) */ +#define REG_UDPHS_EPTCFG1 (*(RwReg*)0xF8030120U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 1) */ +#define REG_UDPHS_EPTCTLENB1 (*(WoReg*)0xF8030124U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 1) */ +#define REG_UDPHS_EPTCTLDIS1 (*(WoReg*)0xF8030128U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 1) */ +#define REG_UDPHS_EPTCTL1 (*(RoReg*)0xF803012CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 1) */ +#define REG_UDPHS_EPTSETSTA1 (*(WoReg*)0xF8030134U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 1) */ +#define REG_UDPHS_EPTCLRSTA1 (*(WoReg*)0xF8030138U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 1) */ +#define REG_UDPHS_EPTSTA1 (*(RoReg*)0xF803013CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 1) */ +#define REG_UDPHS_EPTCFG2 (*(RwReg*)0xF8030140U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 2) */ +#define REG_UDPHS_EPTCTLENB2 (*(WoReg*)0xF8030144U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 2) */ +#define REG_UDPHS_EPTCTLDIS2 (*(WoReg*)0xF8030148U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 2) */ +#define REG_UDPHS_EPTCTL2 (*(RoReg*)0xF803014CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 2) */ +#define REG_UDPHS_EPTSETSTA2 (*(WoReg*)0xF8030154U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 2) */ +#define REG_UDPHS_EPTCLRSTA2 (*(WoReg*)0xF8030158U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 2) */ +#define REG_UDPHS_EPTSTA2 (*(RoReg*)0xF803015CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 2) */ +#define REG_UDPHS_EPTCFG3 (*(RwReg*)0xF8030160U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 3) */ +#define REG_UDPHS_EPTCTLENB3 (*(WoReg*)0xF8030164U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 3) */ +#define REG_UDPHS_EPTCTLDIS3 (*(WoReg*)0xF8030168U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 3) */ +#define REG_UDPHS_EPTCTL3 (*(RoReg*)0xF803016CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 3) */ +#define REG_UDPHS_EPTSETSTA3 (*(WoReg*)0xF8030174U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 3) */ +#define REG_UDPHS_EPTCLRSTA3 (*(WoReg*)0xF8030178U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 3) */ +#define REG_UDPHS_EPTSTA3 (*(RoReg*)0xF803017CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 3) */ +#define REG_UDPHS_EPTCFG4 (*(RwReg*)0xF8030180U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 4) */ +#define REG_UDPHS_EPTCTLENB4 (*(WoReg*)0xF8030184U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 4) */ +#define REG_UDPHS_EPTCTLDIS4 (*(WoReg*)0xF8030188U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 4) */ +#define REG_UDPHS_EPTCTL4 (*(RoReg*)0xF803018CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 4) */ +#define REG_UDPHS_EPTSETSTA4 (*(WoReg*)0xF8030194U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 4) */ +#define REG_UDPHS_EPTCLRSTA4 (*(WoReg*)0xF8030198U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 4) */ +#define REG_UDPHS_EPTSTA4 (*(RoReg*)0xF803019CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 4) */ +#define REG_UDPHS_EPTCFG5 (*(RwReg*)0xF80301A0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 5) */ +#define REG_UDPHS_EPTCTLENB5 (*(WoReg*)0xF80301A4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 5) */ +#define REG_UDPHS_EPTCTLDIS5 (*(WoReg*)0xF80301A8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 5) */ +#define REG_UDPHS_EPTCTL5 (*(RoReg*)0xF80301ACU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 5) */ +#define REG_UDPHS_EPTSETSTA5 (*(WoReg*)0xF80301B4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 5) */ +#define REG_UDPHS_EPTCLRSTA5 (*(WoReg*)0xF80301B8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 5) */ +#define REG_UDPHS_EPTSTA5 (*(RoReg*)0xF80301BCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 5) */ +#define REG_UDPHS_EPTCFG6 (*(RwReg*)0xF80301C0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 6) */ +#define REG_UDPHS_EPTCTLENB6 (*(WoReg*)0xF80301C4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 6) */ +#define REG_UDPHS_EPTCTLDIS6 (*(WoReg*)0xF80301C8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 6) */ +#define REG_UDPHS_EPTCTL6 (*(RoReg*)0xF80301CCU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 6) */ +#define REG_UDPHS_EPTSETSTA6 (*(WoReg*)0xF80301D4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 6) */ +#define REG_UDPHS_EPTCLRSTA6 (*(WoReg*)0xF80301D8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 6) */ +#define REG_UDPHS_EPTSTA6 (*(RoReg*)0xF80301DCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 6) */ +#define REG_UDPHS_EPTCFG7 (*(RwReg*)0xF80301E0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 7) */ +#define REG_UDPHS_EPTCTLENB7 (*(WoReg*)0xF80301E4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 7) */ +#define REG_UDPHS_EPTCTLDIS7 (*(WoReg*)0xF80301E8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 7) */ +#define REG_UDPHS_EPTCTL7 (*(RoReg*)0xF80301ECU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 7) */ +#define REG_UDPHS_EPTSETSTA7 (*(WoReg*)0xF80301F4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 7) */ +#define REG_UDPHS_EPTCLRSTA7 (*(WoReg*)0xF80301F8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 7) */ +#define REG_UDPHS_EPTSTA7 (*(RoReg*)0xF80301FCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 7) */ +#define REG_UDPHS_EPTCFG8 (*(RwReg*)0xF8030200U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 8) */ +#define REG_UDPHS_EPTCTLENB8 (*(WoReg*)0xF8030204U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 8) */ +#define REG_UDPHS_EPTCTLDIS8 (*(WoReg*)0xF8030208U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 8) */ +#define REG_UDPHS_EPTCTL8 (*(RoReg*)0xF803020CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 8) */ +#define REG_UDPHS_EPTSETSTA8 (*(WoReg*)0xF8030214U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 8) */ +#define REG_UDPHS_EPTCLRSTA8 (*(WoReg*)0xF8030218U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 8) */ +#define REG_UDPHS_EPTSTA8 (*(RoReg*)0xF803021CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 8) */ +#define REG_UDPHS_EPTCFG9 (*(RwReg*)0xF8030220U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 9) */ +#define REG_UDPHS_EPTCTLENB9 (*(WoReg*)0xF8030224U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 9) */ +#define REG_UDPHS_EPTCTLDIS9 (*(WoReg*)0xF8030228U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 9) */ +#define REG_UDPHS_EPTCTL9 (*(RoReg*)0xF803022CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 9) */ +#define REG_UDPHS_EPTSETSTA9 (*(WoReg*)0xF8030234U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 9) */ +#define REG_UDPHS_EPTCLRSTA9 (*(WoReg*)0xF8030238U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 9) */ +#define REG_UDPHS_EPTSTA9 (*(RoReg*)0xF803023CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 9) */ +#define REG_UDPHS_EPTCFG10 (*(RwReg*)0xF8030240U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 10) */ +#define REG_UDPHS_EPTCTLENB10 (*(WoReg*)0xF8030244U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 10) */ +#define REG_UDPHS_EPTCTLDIS10 (*(WoReg*)0xF8030248U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 10) */ +#define REG_UDPHS_EPTCTL10 (*(RoReg*)0xF803024CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 10) */ +#define REG_UDPHS_EPTSETSTA10 (*(WoReg*)0xF8030254U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 10) */ +#define REG_UDPHS_EPTCLRSTA10 (*(WoReg*)0xF8030258U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 10) */ +#define REG_UDPHS_EPTSTA10 (*(RoReg*)0xF803025CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 10) */ +#define REG_UDPHS_EPTCFG11 (*(RwReg*)0xF8030260U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 11) */ +#define REG_UDPHS_EPTCTLENB11 (*(WoReg*)0xF8030264U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 11) */ +#define REG_UDPHS_EPTCTLDIS11 (*(WoReg*)0xF8030268U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 11) */ +#define REG_UDPHS_EPTCTL11 (*(RoReg*)0xF803026CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 11) */ +#define REG_UDPHS_EPTSETSTA11 (*(WoReg*)0xF8030274U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 11) */ +#define REG_UDPHS_EPTCLRSTA11 (*(WoReg*)0xF8030278U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 11) */ +#define REG_UDPHS_EPTSTA11 (*(RoReg*)0xF803027CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 11) */ +#define REG_UDPHS_EPTCFG12 (*(RwReg*)0xF8030280U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 12) */ +#define REG_UDPHS_EPTCTLENB12 (*(WoReg*)0xF8030284U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 12) */ +#define REG_UDPHS_EPTCTLDIS12 (*(WoReg*)0xF8030288U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 12) */ +#define REG_UDPHS_EPTCTL12 (*(RoReg*)0xF803028CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 12) */ +#define REG_UDPHS_EPTSETSTA12 (*(WoReg*)0xF8030294U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 12) */ +#define REG_UDPHS_EPTCLRSTA12 (*(WoReg*)0xF8030298U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 12) */ +#define REG_UDPHS_EPTSTA12 (*(RoReg*)0xF803029CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 12) */ +#define REG_UDPHS_EPTCFG13 (*(RwReg*)0xF80302A0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 13) */ +#define REG_UDPHS_EPTCTLENB13 (*(WoReg*)0xF80302A4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 13) */ +#define REG_UDPHS_EPTCTLDIS13 (*(WoReg*)0xF80302A8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 13) */ +#define REG_UDPHS_EPTCTL13 (*(RoReg*)0xF80302ACU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 13) */ +#define REG_UDPHS_EPTSETSTA13 (*(WoReg*)0xF80302B4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 13) */ +#define REG_UDPHS_EPTCLRSTA13 (*(WoReg*)0xF80302B8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 13) */ +#define REG_UDPHS_EPTSTA13 (*(RoReg*)0xF80302BCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 13) */ +#define REG_UDPHS_EPTCFG14 (*(RwReg*)0xF80302C0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 14) */ +#define REG_UDPHS_EPTCTLENB14 (*(WoReg*)0xF80302C4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 14) */ +#define REG_UDPHS_EPTCTLDIS14 (*(WoReg*)0xF80302C8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 14) */ +#define REG_UDPHS_EPTCTL14 (*(RoReg*)0xF80302CCU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 14) */ +#define REG_UDPHS_EPTSETSTA14 (*(WoReg*)0xF80302D4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 14) */ +#define REG_UDPHS_EPTCLRSTA14 (*(WoReg*)0xF80302D8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 14) */ +#define REG_UDPHS_EPTSTA14 (*(RoReg*)0xF80302DCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 14) */ +#define REG_UDPHS_EPTCFG15 (*(RwReg*)0xF80302E0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 15) */ +#define REG_UDPHS_EPTCTLENB15 (*(WoReg*)0xF80302E4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 15) */ +#define REG_UDPHS_EPTCTLDIS15 (*(WoReg*)0xF80302E8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 15) */ +#define REG_UDPHS_EPTCTL15 (*(RoReg*)0xF80302ECU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 15) */ +#define REG_UDPHS_EPTSETSTA15 (*(WoReg*)0xF80302F4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 15) */ +#define REG_UDPHS_EPTCLRSTA15 (*(WoReg*)0xF80302F8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 15) */ +#define REG_UDPHS_EPTSTA15 (*(RoReg*)0xF80302FCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 15) */ +#define REG_UDPHS_DMANXTDSC0 (*(RwReg*)0xF8030300U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 0) */ +#define REG_UDPHS_DMAADDRESS0 (*(RwReg*)0xF8030304U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 0) */ +#define REG_UDPHS_DMACONTROL0 (*(RwReg*)0xF8030308U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 0) */ +#define REG_UDPHS_DMASTATUS0 (*(RwReg*)0xF803030CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 0) */ +#define REG_UDPHS_DMANXTDSC1 (*(RwReg*)0xF8030310U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 1) */ +#define REG_UDPHS_DMAADDRESS1 (*(RwReg*)0xF8030314U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 1) */ +#define REG_UDPHS_DMACONTROL1 (*(RwReg*)0xF8030318U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 1) */ +#define REG_UDPHS_DMASTATUS1 (*(RwReg*)0xF803031CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 1) */ +#define REG_UDPHS_DMANXTDSC2 (*(RwReg*)0xF8030320U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 2) */ +#define REG_UDPHS_DMAADDRESS2 (*(RwReg*)0xF8030324U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 2) */ +#define REG_UDPHS_DMACONTROL2 (*(RwReg*)0xF8030328U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 2) */ +#define REG_UDPHS_DMASTATUS2 (*(RwReg*)0xF803032CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 2) */ +#define REG_UDPHS_DMANXTDSC3 (*(RwReg*)0xF8030330U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 3) */ +#define REG_UDPHS_DMAADDRESS3 (*(RwReg*)0xF8030334U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 3) */ +#define REG_UDPHS_DMACONTROL3 (*(RwReg*)0xF8030338U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 3) */ +#define REG_UDPHS_DMASTATUS3 (*(RwReg*)0xF803033CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 3) */ +#define REG_UDPHS_DMANXTDSC4 (*(RwReg*)0xF8030340U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 4) */ +#define REG_UDPHS_DMAADDRESS4 (*(RwReg*)0xF8030344U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 4) */ +#define REG_UDPHS_DMACONTROL4 (*(RwReg*)0xF8030348U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 4) */ +#define REG_UDPHS_DMASTATUS4 (*(RwReg*)0xF803034CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 4) */ +#define REG_UDPHS_DMANXTDSC5 (*(RwReg*)0xF8030350U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 5) */ +#define REG_UDPHS_DMAADDRESS5 (*(RwReg*)0xF8030354U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 5) */ +#define REG_UDPHS_DMACONTROL5 (*(RwReg*)0xF8030358U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 5) */ +#define REG_UDPHS_DMASTATUS5 (*(RwReg*)0xF803035CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 5) */ +#define REG_UDPHS_DMANXTDSC6 (*(RwReg*)0xF8030360U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 6) */ +#define REG_UDPHS_DMAADDRESS6 (*(RwReg*)0xF8030364U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 6) */ +#define REG_UDPHS_DMACONTROL6 (*(RwReg*)0xF8030368U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 6) */ +#define REG_UDPHS_DMASTATUS6 (*(RwReg*)0xF803036CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 6) */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_UDPHS_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_usart0.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_usart0.h new file mode 100644 index 0000000..1fcb2fd --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_usart0.h
@@ -0,0 +1,72 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_USART0_INSTANCE_ +#define _SAMA5_USART0_INSTANCE_ + +/* ========== Register definition for USART0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_USART0_CR (0xF001C000U) /**< \brief (USART0) Control Register */ +#define REG_USART0_MR (0xF001C004U) /**< \brief (USART0) Mode Register */ +#define REG_USART0_IER (0xF001C008U) /**< \brief (USART0) Interrupt Enable Register */ +#define REG_USART0_IDR (0xF001C00CU) /**< \brief (USART0) Interrupt Disable Register */ +#define REG_USART0_IMR (0xF001C010U) /**< \brief (USART0) Interrupt Mask Register */ +#define REG_USART0_CSR (0xF001C014U) /**< \brief (USART0) Channel Status Register */ +#define REG_USART0_RHR (0xF001C018U) /**< \brief (USART0) Receiver Holding Register */ +#define REG_USART0_THR (0xF001C01CU) /**< \brief (USART0) Transmitter Holding Register */ +#define REG_USART0_BRGR (0xF001C020U) /**< \brief (USART0) Baud Rate Generator Register */ +#define REG_USART0_RTOR (0xF001C024U) /**< \brief (USART0) Receiver Time-out Register */ +#define REG_USART0_TTGR (0xF001C028U) /**< \brief (USART0) Transmitter Timeguard Register */ +#define REG_USART0_FIDI (0xF001C040U) /**< \brief (USART0) FI DI Ratio Register */ +#define REG_USART0_NER (0xF001C044U) /**< \brief (USART0) Number of Errors Register */ +#define REG_USART0_IF (0xF001C04CU) /**< \brief (USART0) IrDA Filter Register */ +#define REG_USART0_MAN (0xF001C050U) /**< \brief (USART0) Manchester Encoder Decoder Register */ +#define REG_USART0_WPMR (0xF001C0E4U) /**< \brief (USART0) Write Protect Mode Register */ +#define REG_USART0_WPSR (0xF001C0E8U) /**< \brief (USART0) Write Protect Status Register */ +#else +#define REG_USART0_CR (*(WoReg*)0xF001C000U) /**< \brief (USART0) Control Register */ +#define REG_USART0_MR (*(RwReg*)0xF001C004U) /**< \brief (USART0) Mode Register */ +#define REG_USART0_IER (*(WoReg*)0xF001C008U) /**< \brief (USART0) Interrupt Enable Register */ +#define REG_USART0_IDR (*(WoReg*)0xF001C00CU) /**< \brief (USART0) Interrupt Disable Register */ +#define REG_USART0_IMR (*(RoReg*)0xF001C010U) /**< \brief (USART0) Interrupt Mask Register */ +#define REG_USART0_CSR (*(RoReg*)0xF001C014U) /**< \brief (USART0) Channel Status Register */ +#define REG_USART0_RHR (*(RoReg*)0xF001C018U) /**< \brief (USART0) Receiver Holding Register */ +#define REG_USART0_THR (*(WoReg*)0xF001C01CU) /**< \brief (USART0) Transmitter Holding Register */ +#define REG_USART0_BRGR (*(RwReg*)0xF001C020U) /**< \brief (USART0) Baud Rate Generator Register */ +#define REG_USART0_RTOR (*(RwReg*)0xF001C024U) /**< \brief (USART0) Receiver Time-out Register */ +#define REG_USART0_TTGR (*(RwReg*)0xF001C028U) /**< \brief (USART0) Transmitter Timeguard Register */ +#define REG_USART0_FIDI (*(RwReg*)0xF001C040U) /**< \brief (USART0) FI DI Ratio Register */ +#define REG_USART0_NER (*(RoReg*)0xF001C044U) /**< \brief (USART0) Number of Errors Register */ +#define REG_USART0_IF (*(RwReg*)0xF001C04CU) /**< \brief (USART0) IrDA Filter Register */ +#define REG_USART0_MAN (*(RwReg*)0xF001C050U) /**< \brief (USART0) Manchester Encoder Decoder Register */ +#define REG_USART0_WPMR (*(RwReg*)0xF001C0E4U) /**< \brief (USART0) Write Protect Mode Register */ +#define REG_USART0_WPSR (*(RoReg*)0xF001C0E8U) /**< \brief (USART0) Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_USART0_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_usart1.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_usart1.h new file mode 100644 index 0000000..fb1172a --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_usart1.h
@@ -0,0 +1,72 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_USART1_INSTANCE_ +#define _SAMA5_USART1_INSTANCE_ + +/* ========== Register definition for USART1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_USART1_CR (0xF0020000U) /**< \brief (USART1) Control Register */ +#define REG_USART1_MR (0xF0020004U) /**< \brief (USART1) Mode Register */ +#define REG_USART1_IER (0xF0020008U) /**< \brief (USART1) Interrupt Enable Register */ +#define REG_USART1_IDR (0xF002000CU) /**< \brief (USART1) Interrupt Disable Register */ +#define REG_USART1_IMR (0xF0020010U) /**< \brief (USART1) Interrupt Mask Register */ +#define REG_USART1_CSR (0xF0020014U) /**< \brief (USART1) Channel Status Register */ +#define REG_USART1_RHR (0xF0020018U) /**< \brief (USART1) Receiver Holding Register */ +#define REG_USART1_THR (0xF002001CU) /**< \brief (USART1) Transmitter Holding Register */ +#define REG_USART1_BRGR (0xF0020020U) /**< \brief (USART1) Baud Rate Generator Register */ +#define REG_USART1_RTOR (0xF0020024U) /**< \brief (USART1) Receiver Time-out Register */ +#define REG_USART1_TTGR (0xF0020028U) /**< \brief (USART1) Transmitter Timeguard Register */ +#define REG_USART1_FIDI (0xF0020040U) /**< \brief (USART1) FI DI Ratio Register */ +#define REG_USART1_NER (0xF0020044U) /**< \brief (USART1) Number of Errors Register */ +#define REG_USART1_IF (0xF002004CU) /**< \brief (USART1) IrDA Filter Register */ +#define REG_USART1_MAN (0xF0020050U) /**< \brief (USART1) Manchester Encoder Decoder Register */ +#define REG_USART1_WPMR (0xF00200E4U) /**< \brief (USART1) Write Protect Mode Register */ +#define REG_USART1_WPSR (0xF00200E8U) /**< \brief (USART1) Write Protect Status Register */ +#else +#define REG_USART1_CR (*(WoReg*)0xF0020000U) /**< \brief (USART1) Control Register */ +#define REG_USART1_MR (*(RwReg*)0xF0020004U) /**< \brief (USART1) Mode Register */ +#define REG_USART1_IER (*(WoReg*)0xF0020008U) /**< \brief (USART1) Interrupt Enable Register */ +#define REG_USART1_IDR (*(WoReg*)0xF002000CU) /**< \brief (USART1) Interrupt Disable Register */ +#define REG_USART1_IMR (*(RoReg*)0xF0020010U) /**< \brief (USART1) Interrupt Mask Register */ +#define REG_USART1_CSR (*(RoReg*)0xF0020014U) /**< \brief (USART1) Channel Status Register */ +#define REG_USART1_RHR (*(RoReg*)0xF0020018U) /**< \brief (USART1) Receiver Holding Register */ +#define REG_USART1_THR (*(WoReg*)0xF002001CU) /**< \brief (USART1) Transmitter Holding Register */ +#define REG_USART1_BRGR (*(RwReg*)0xF0020020U) /**< \brief (USART1) Baud Rate Generator Register */ +#define REG_USART1_RTOR (*(RwReg*)0xF0020024U) /**< \brief (USART1) Receiver Time-out Register */ +#define REG_USART1_TTGR (*(RwReg*)0xF0020028U) /**< \brief (USART1) Transmitter Timeguard Register */ +#define REG_USART1_FIDI (*(RwReg*)0xF0020040U) /**< \brief (USART1) FI DI Ratio Register */ +#define REG_USART1_NER (*(RoReg*)0xF0020044U) /**< \brief (USART1) Number of Errors Register */ +#define REG_USART1_IF (*(RwReg*)0xF002004CU) /**< \brief (USART1) IrDA Filter Register */ +#define REG_USART1_MAN (*(RwReg*)0xF0020050U) /**< \brief (USART1) Manchester Encoder Decoder Register */ +#define REG_USART1_WPMR (*(RwReg*)0xF00200E4U) /**< \brief (USART1) Write Protect Mode Register */ +#define REG_USART1_WPSR (*(RoReg*)0xF00200E8U) /**< \brief (USART1) Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_USART1_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_usart2.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_usart2.h new file mode 100644 index 0000000..d8fed01 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_usart2.h
@@ -0,0 +1,72 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_USART2_INSTANCE_ +#define _SAMA5_USART2_INSTANCE_ + +/* ========== Register definition for USART2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_USART2_CR (0xF8020000U) /**< \brief (USART2) Control Register */ +#define REG_USART2_MR (0xF8020004U) /**< \brief (USART2) Mode Register */ +#define REG_USART2_IER (0xF8020008U) /**< \brief (USART2) Interrupt Enable Register */ +#define REG_USART2_IDR (0xF802000CU) /**< \brief (USART2) Interrupt Disable Register */ +#define REG_USART2_IMR (0xF8020010U) /**< \brief (USART2) Interrupt Mask Register */ +#define REG_USART2_CSR (0xF8020014U) /**< \brief (USART2) Channel Status Register */ +#define REG_USART2_RHR (0xF8020018U) /**< \brief (USART2) Receiver Holding Register */ +#define REG_USART2_THR (0xF802001CU) /**< \brief (USART2) Transmitter Holding Register */ +#define REG_USART2_BRGR (0xF8020020U) /**< \brief (USART2) Baud Rate Generator Register */ +#define REG_USART2_RTOR (0xF8020024U) /**< \brief (USART2) Receiver Time-out Register */ +#define REG_USART2_TTGR (0xF8020028U) /**< \brief (USART2) Transmitter Timeguard Register */ +#define REG_USART2_FIDI (0xF8020040U) /**< \brief (USART2) FI DI Ratio Register */ +#define REG_USART2_NER (0xF8020044U) /**< \brief (USART2) Number of Errors Register */ +#define REG_USART2_IF (0xF802004CU) /**< \brief (USART2) IrDA Filter Register */ +#define REG_USART2_MAN (0xF8020050U) /**< \brief (USART2) Manchester Encoder Decoder Register */ +#define REG_USART2_WPMR (0xF80200E4U) /**< \brief (USART2) Write Protect Mode Register */ +#define REG_USART2_WPSR (0xF80200E8U) /**< \brief (USART2) Write Protect Status Register */ +#else +#define REG_USART2_CR (*(WoReg*)0xF8020000U) /**< \brief (USART2) Control Register */ +#define REG_USART2_MR (*(RwReg*)0xF8020004U) /**< \brief (USART2) Mode Register */ +#define REG_USART2_IER (*(WoReg*)0xF8020008U) /**< \brief (USART2) Interrupt Enable Register */ +#define REG_USART2_IDR (*(WoReg*)0xF802000CU) /**< \brief (USART2) Interrupt Disable Register */ +#define REG_USART2_IMR (*(RoReg*)0xF8020010U) /**< \brief (USART2) Interrupt Mask Register */ +#define REG_USART2_CSR (*(RoReg*)0xF8020014U) /**< \brief (USART2) Channel Status Register */ +#define REG_USART2_RHR (*(RoReg*)0xF8020018U) /**< \brief (USART2) Receiver Holding Register */ +#define REG_USART2_THR (*(WoReg*)0xF802001CU) /**< \brief (USART2) Transmitter Holding Register */ +#define REG_USART2_BRGR (*(RwReg*)0xF8020020U) /**< \brief (USART2) Baud Rate Generator Register */ +#define REG_USART2_RTOR (*(RwReg*)0xF8020024U) /**< \brief (USART2) Receiver Time-out Register */ +#define REG_USART2_TTGR (*(RwReg*)0xF8020028U) /**< \brief (USART2) Transmitter Timeguard Register */ +#define REG_USART2_FIDI (*(RwReg*)0xF8020040U) /**< \brief (USART2) FI DI Ratio Register */ +#define REG_USART2_NER (*(RoReg*)0xF8020044U) /**< \brief (USART2) Number of Errors Register */ +#define REG_USART2_IF (*(RwReg*)0xF802004CU) /**< \brief (USART2) IrDA Filter Register */ +#define REG_USART2_MAN (*(RwReg*)0xF8020050U) /**< \brief (USART2) Manchester Encoder Decoder Register */ +#define REG_USART2_WPMR (*(RwReg*)0xF80200E4U) /**< \brief (USART2) Write Protect Mode Register */ +#define REG_USART2_WPSR (*(RoReg*)0xF80200E8U) /**< \brief (USART2) Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_USART2_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_usart3.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_usart3.h new file mode 100644 index 0000000..845b76b --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_usart3.h
@@ -0,0 +1,72 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_USART3_INSTANCE_ +#define _SAMA5_USART3_INSTANCE_ + +/* ========== Register definition for USART3 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_USART3_CR (0xF8024000U) /**< \brief (USART3) Control Register */ +#define REG_USART3_MR (0xF8024004U) /**< \brief (USART3) Mode Register */ +#define REG_USART3_IER (0xF8024008U) /**< \brief (USART3) Interrupt Enable Register */ +#define REG_USART3_IDR (0xF802400CU) /**< \brief (USART3) Interrupt Disable Register */ +#define REG_USART3_IMR (0xF8024010U) /**< \brief (USART3) Interrupt Mask Register */ +#define REG_USART3_CSR (0xF8024014U) /**< \brief (USART3) Channel Status Register */ +#define REG_USART3_RHR (0xF8024018U) /**< \brief (USART3) Receiver Holding Register */ +#define REG_USART3_THR (0xF802401CU) /**< \brief (USART3) Transmitter Holding Register */ +#define REG_USART3_BRGR (0xF8024020U) /**< \brief (USART3) Baud Rate Generator Register */ +#define REG_USART3_RTOR (0xF8024024U) /**< \brief (USART3) Receiver Time-out Register */ +#define REG_USART3_TTGR (0xF8024028U) /**< \brief (USART3) Transmitter Timeguard Register */ +#define REG_USART3_FIDI (0xF8024040U) /**< \brief (USART3) FI DI Ratio Register */ +#define REG_USART3_NER (0xF8024044U) /**< \brief (USART3) Number of Errors Register */ +#define REG_USART3_IF (0xF802404CU) /**< \brief (USART3) IrDA Filter Register */ +#define REG_USART3_MAN (0xF8024050U) /**< \brief (USART3) Manchester Encoder Decoder Register */ +#define REG_USART3_WPMR (0xF80240E4U) /**< \brief (USART3) Write Protect Mode Register */ +#define REG_USART3_WPSR (0xF80240E8U) /**< \brief (USART3) Write Protect Status Register */ +#else +#define REG_USART3_CR (*(WoReg*)0xF8024000U) /**< \brief (USART3) Control Register */ +#define REG_USART3_MR (*(RwReg*)0xF8024004U) /**< \brief (USART3) Mode Register */ +#define REG_USART3_IER (*(WoReg*)0xF8024008U) /**< \brief (USART3) Interrupt Enable Register */ +#define REG_USART3_IDR (*(WoReg*)0xF802400CU) /**< \brief (USART3) Interrupt Disable Register */ +#define REG_USART3_IMR (*(RoReg*)0xF8024010U) /**< \brief (USART3) Interrupt Mask Register */ +#define REG_USART3_CSR (*(RoReg*)0xF8024014U) /**< \brief (USART3) Channel Status Register */ +#define REG_USART3_RHR (*(RoReg*)0xF8024018U) /**< \brief (USART3) Receiver Holding Register */ +#define REG_USART3_THR (*(WoReg*)0xF802401CU) /**< \brief (USART3) Transmitter Holding Register */ +#define REG_USART3_BRGR (*(RwReg*)0xF8024020U) /**< \brief (USART3) Baud Rate Generator Register */ +#define REG_USART3_RTOR (*(RwReg*)0xF8024024U) /**< \brief (USART3) Receiver Time-out Register */ +#define REG_USART3_TTGR (*(RwReg*)0xF8024028U) /**< \brief (USART3) Transmitter Timeguard Register */ +#define REG_USART3_FIDI (*(RwReg*)0xF8024040U) /**< \brief (USART3) FI DI Ratio Register */ +#define REG_USART3_NER (*(RoReg*)0xF8024044U) /**< \brief (USART3) Number of Errors Register */ +#define REG_USART3_IF (*(RwReg*)0xF802404CU) /**< \brief (USART3) IrDA Filter Register */ +#define REG_USART3_MAN (*(RwReg*)0xF8024050U) /**< \brief (USART3) Manchester Encoder Decoder Register */ +#define REG_USART3_WPMR (*(RwReg*)0xF80240E4U) /**< \brief (USART3) Write Protect Mode Register */ +#define REG_USART3_WPSR (*(RoReg*)0xF80240E8U) /**< \brief (USART3) Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_USART3_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_wdt.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_wdt.h new file mode 100644 index 0000000..48af56a --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_wdt.h
@@ -0,0 +1,44 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_WDT_INSTANCE_ +#define _SAMA5_WDT_INSTANCE_ + +/* ========== Register definition for WDT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_WDT_CR (0xFFFFFE40U) /**< \brief (WDT) Control Register */ +#define REG_WDT_MR (0xFFFFFE44U) /**< \brief (WDT) Mode Register */ +#define REG_WDT_SR (0xFFFFFE48U) /**< \brief (WDT) Status Register */ +#else +#define REG_WDT_CR (*(WoReg*)0xFFFFFE40U) /**< \brief (WDT) Control Register */ +#define REG_WDT_MR (*(RwReg*)0xFFFFFE44U) /**< \brief (WDT) Mode Register */ +#define REG_WDT_SR (*(RoReg*)0xFFFFFE48U) /**< \brief (WDT) Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_WDT_INSTANCE_ */