diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_adc.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_adc.h new file mode 100644 index 0000000..c6bc4f7 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_adc.h
@@ -0,0 +1,104 @@ +/** + * \file + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM3XA_ADC_INSTANCE_ +#define _SAM3XA_ADC_INSTANCE_ + +/* ========== Register definition for ADC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_ADC_CR (0x400C0000U) /**< \brief (ADC) Control Register */ +#define REG_ADC_MR (0x400C0004U) /**< \brief (ADC) Mode Register */ +#define REG_ADC_SEQR1 (0x400C0008U) /**< \brief (ADC) Channel Sequence Register 1 */ +#define REG_ADC_SEQR2 (0x400C000CU) /**< \brief (ADC) Channel Sequence Register 2 */ +#define REG_ADC_CHER (0x400C0010U) /**< \brief (ADC) Channel Enable Register */ +#define REG_ADC_CHDR (0x400C0014U) /**< \brief (ADC) Channel Disable Register */ +#define REG_ADC_CHSR (0x400C0018U) /**< \brief (ADC) Channel Status Register */ +#define REG_ADC_LCDR (0x400C0020U) /**< \brief (ADC) Last Converted Data Register */ +#define REG_ADC_IER (0x400C0024U) /**< \brief (ADC) Interrupt Enable Register */ +#define REG_ADC_IDR (0x400C0028U) /**< \brief (ADC) Interrupt Disable Register */ +#define REG_ADC_IMR (0x400C002CU) /**< \brief (ADC) Interrupt Mask Register */ +#define REG_ADC_ISR (0x400C0030U) /**< \brief (ADC) Interrupt Status Register */ +#define REG_ADC_OVER (0x400C003CU) /**< \brief (ADC) Overrun Status Register */ +#define REG_ADC_EMR (0x400C0040U) /**< \brief (ADC) Extended Mode Register */ +#define REG_ADC_CWR (0x400C0044U) /**< \brief (ADC) Compare Window Register */ +#define REG_ADC_CGR (0x400C0048U) /**< \brief (ADC) Channel Gain Register */ +#define REG_ADC_COR (0x400C004CU) /**< \brief (ADC) Channel Offset Register */ +#define REG_ADC_CDR (0x400C0050U) /**< \brief (ADC) Channel Data Register */ +#define REG_ADC_ACR (0x400C0094U) /**< \brief (ADC) Analog Control Register */ +#define REG_ADC_WPMR (0x400C00E4U) /**< \brief (ADC) Write Protect Mode Register */ +#define REG_ADC_WPSR (0x400C00E8U) /**< \brief (ADC) Write Protect Status Register */ +#define REG_ADC_RPR (0x400C0100U) /**< \brief (ADC) Receive Pointer Register */ +#define REG_ADC_RCR (0x400C0104U) /**< \brief (ADC) Receive Counter Register */ +#define REG_ADC_RNPR (0x400C0110U) /**< \brief (ADC) Receive Next Pointer Register */ +#define REG_ADC_RNCR (0x400C0114U) /**< \brief (ADC) Receive Next Counter Register */ +#define REG_ADC_PTCR (0x400C0120U) /**< \brief (ADC) Transfer Control Register */ +#define REG_ADC_PTSR (0x400C0124U) /**< \brief (ADC) Transfer Status Register */ +#else +#define REG_ADC_CR (*(WoReg*)0x400C0000U) /**< \brief (ADC) Control Register */ +#define REG_ADC_MR (*(RwReg*)0x400C0004U) /**< \brief (ADC) Mode Register */ +#define REG_ADC_SEQR1 (*(RwReg*)0x400C0008U) /**< \brief (ADC) Channel Sequence Register 1 */ +#define REG_ADC_SEQR2 (*(RwReg*)0x400C000CU) /**< \brief (ADC) Channel Sequence Register 2 */ +#define REG_ADC_CHER (*(WoReg*)0x400C0010U) /**< \brief (ADC) Channel Enable Register */ +#define REG_ADC_CHDR (*(WoReg*)0x400C0014U) /**< \brief (ADC) Channel Disable Register */ +#define REG_ADC_CHSR (*(RoReg*)0x400C0018U) /**< \brief (ADC) Channel Status Register */ +#define REG_ADC_LCDR (*(RoReg*)0x400C0020U) /**< \brief (ADC) Last Converted Data Register */ +#define REG_ADC_IER (*(WoReg*)0x400C0024U) /**< \brief (ADC) Interrupt Enable Register */ +#define REG_ADC_IDR (*(WoReg*)0x400C0028U) /**< \brief (ADC) Interrupt Disable Register */ +#define REG_ADC_IMR (*(RoReg*)0x400C002CU) /**< \brief (ADC) Interrupt Mask Register */ +#define REG_ADC_ISR (*(RoReg*)0x400C0030U) /**< \brief (ADC) Interrupt Status Register */ +#define REG_ADC_OVER (*(RoReg*)0x400C003CU) /**< \brief (ADC) Overrun Status Register */ +#define REG_ADC_EMR (*(RwReg*)0x400C0040U) /**< \brief (ADC) Extended Mode Register */ +#define REG_ADC_CWR (*(RwReg*)0x400C0044U) /**< \brief (ADC) Compare Window Register */ +#define REG_ADC_CGR (*(RwReg*)0x400C0048U) /**< \brief (ADC) Channel Gain Register */ +#define REG_ADC_COR (*(RwReg*)0x400C004CU) /**< \brief (ADC) Channel Offset Register */ +#define REG_ADC_CDR (*(RoReg*)0x400C0050U) /**< \brief (ADC) Channel Data Register */ +#define REG_ADC_ACR (*(RwReg*)0x400C0094U) /**< \brief (ADC) Analog Control Register */ +#define REG_ADC_WPMR (*(RwReg*)0x400C00E4U) /**< \brief (ADC) Write Protect Mode Register */ +#define REG_ADC_WPSR (*(RoReg*)0x400C00E8U) /**< \brief (ADC) Write Protect Status Register */ +#define REG_ADC_RPR (*(RwReg*)0x400C0100U) /**< \brief (ADC) Receive Pointer Register */ +#define REG_ADC_RCR (*(RwReg*)0x400C0104U) /**< \brief (ADC) Receive Counter Register */ +#define REG_ADC_RNPR (*(RwReg*)0x400C0110U) /**< \brief (ADC) Receive Next Pointer Register */ +#define REG_ADC_RNCR (*(RwReg*)0x400C0114U) /**< \brief (ADC) Receive Next Counter Register */ +#define REG_ADC_PTCR (*(WoReg*)0x400C0120U) /**< \brief (ADC) Transfer Control Register */ +#define REG_ADC_PTSR (*(RoReg*)0x400C0124U) /**< \brief (ADC) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_ADC_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_can0.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_can0.h new file mode 100644 index 0000000..85a1e21 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_can0.h
@@ -0,0 +1,204 @@ +/** + * \file + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM3XA_CAN0_INSTANCE_ +#define _SAM3XA_CAN0_INSTANCE_ + +/* ========== Register definition for CAN0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_CAN0_MR (0x400B4000U) /**< \brief (CAN0) Mode Register */ +#define REG_CAN0_IER (0x400B4004U) /**< \brief (CAN0) Interrupt Enable Register */ +#define REG_CAN0_IDR (0x400B4008U) /**< \brief (CAN0) Interrupt Disable Register */ +#define REG_CAN0_IMR (0x400B400CU) /**< \brief (CAN0) Interrupt Mask Register */ +#define REG_CAN0_SR (0x400B4010U) /**< \brief (CAN0) Status Register */ +#define REG_CAN0_BR (0x400B4014U) /**< \brief (CAN0) Baudrate Register */ +#define REG_CAN0_TIM (0x400B4018U) /**< \brief (CAN0) Timer Register */ +#define REG_CAN0_TIMESTP (0x400B401CU) /**< \brief (CAN0) Timestamp Register */ +#define REG_CAN0_ECR (0x400B4020U) /**< \brief (CAN0) Error Counter Register */ +#define REG_CAN0_TCR (0x400B4024U) /**< \brief (CAN0) Transfer Command Register */ +#define REG_CAN0_ACR (0x400B4028U) /**< \brief (CAN0) Abort Command Register */ +#define REG_CAN0_WPMR (0x400B40E4U) /**< \brief (CAN0) Write Protect Mode Register */ +#define REG_CAN0_WPSR (0x400B40E8U) /**< \brief (CAN0) Write Protect Status Register */ +#define REG_CAN0_MMR0 (0x400B4200U) /**< \brief (CAN0) Mailbox Mode Register (MB = 0) */ +#define REG_CAN0_MAM0 (0x400B4204U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 0) */ +#define REG_CAN0_MID0 (0x400B4208U) /**< \brief (CAN0) Mailbox ID Register (MB = 0) */ +#define REG_CAN0_MFID0 (0x400B420CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 0) */ +#define REG_CAN0_MSR0 (0x400B4210U) /**< \brief (CAN0) Mailbox Status Register (MB = 0) */ +#define REG_CAN0_MDL0 (0x400B4214U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 0) */ +#define REG_CAN0_MDH0 (0x400B4218U) /**< \brief (CAN0) Mailbox Data High Register (MB = 0) */ +#define REG_CAN0_MCR0 (0x400B421CU) /**< \brief (CAN0) Mailbox Control Register (MB = 0) */ +#define REG_CAN0_MMR1 (0x400B4220U) /**< \brief (CAN0) Mailbox Mode Register (MB = 1) */ +#define REG_CAN0_MAM1 (0x400B4224U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 1) */ +#define REG_CAN0_MID1 (0x400B4228U) /**< \brief (CAN0) Mailbox ID Register (MB = 1) */ +#define REG_CAN0_MFID1 (0x400B422CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 1) */ +#define REG_CAN0_MSR1 (0x400B4230U) /**< \brief (CAN0) Mailbox Status Register (MB = 1) */ +#define REG_CAN0_MDL1 (0x400B4234U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 1) */ +#define REG_CAN0_MDH1 (0x400B4238U) /**< \brief (CAN0) Mailbox Data High Register (MB = 1) */ +#define REG_CAN0_MCR1 (0x400B423CU) /**< \brief (CAN0) Mailbox Control Register (MB = 1) */ +#define REG_CAN0_MMR2 (0x400B4240U) /**< \brief (CAN0) Mailbox Mode Register (MB = 2) */ +#define REG_CAN0_MAM2 (0x400B4244U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 2) */ +#define REG_CAN0_MID2 (0x400B4248U) /**< \brief (CAN0) Mailbox ID Register (MB = 2) */ +#define REG_CAN0_MFID2 (0x400B424CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 2) */ +#define REG_CAN0_MSR2 (0x400B4250U) /**< \brief (CAN0) Mailbox Status Register (MB = 2) */ +#define REG_CAN0_MDL2 (0x400B4254U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 2) */ +#define REG_CAN0_MDH2 (0x400B4258U) /**< \brief (CAN0) Mailbox Data High Register (MB = 2) */ +#define REG_CAN0_MCR2 (0x400B425CU) /**< \brief (CAN0) Mailbox Control Register (MB = 2) */ +#define REG_CAN0_MMR3 (0x400B4260U) /**< \brief (CAN0) Mailbox Mode Register (MB = 3) */ +#define REG_CAN0_MAM3 (0x400B4264U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 3) */ +#define REG_CAN0_MID3 (0x400B4268U) /**< \brief (CAN0) Mailbox ID Register (MB = 3) */ +#define REG_CAN0_MFID3 (0x400B426CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 3) */ +#define REG_CAN0_MSR3 (0x400B4270U) /**< \brief (CAN0) Mailbox Status Register (MB = 3) */ +#define REG_CAN0_MDL3 (0x400B4274U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 3) */ +#define REG_CAN0_MDH3 (0x400B4278U) /**< \brief (CAN0) Mailbox Data High Register (MB = 3) */ +#define REG_CAN0_MCR3 (0x400B427CU) /**< \brief (CAN0) Mailbox Control Register (MB = 3) */ +#define REG_CAN0_MMR4 (0x400B4280U) /**< \brief (CAN0) Mailbox Mode Register (MB = 4) */ +#define REG_CAN0_MAM4 (0x400B4284U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 4) */ +#define REG_CAN0_MID4 (0x400B4288U) /**< \brief (CAN0) Mailbox ID Register (MB = 4) */ +#define REG_CAN0_MFID4 (0x400B428CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 4) */ +#define REG_CAN0_MSR4 (0x400B4290U) /**< \brief (CAN0) Mailbox Status Register (MB = 4) */ +#define REG_CAN0_MDL4 (0x400B4294U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 4) */ +#define REG_CAN0_MDH4 (0x400B4298U) /**< \brief (CAN0) Mailbox Data High Register (MB = 4) */ +#define REG_CAN0_MCR4 (0x400B429CU) /**< \brief (CAN0) Mailbox Control Register (MB = 4) */ +#define REG_CAN0_MMR5 (0x400B42A0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 5) */ +#define REG_CAN0_MAM5 (0x400B42A4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 5) */ +#define REG_CAN0_MID5 (0x400B42A8U) /**< \brief (CAN0) Mailbox ID Register (MB = 5) */ +#define REG_CAN0_MFID5 (0x400B42ACU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 5) */ +#define REG_CAN0_MSR5 (0x400B42B0U) /**< \brief (CAN0) Mailbox Status Register (MB = 5) */ +#define REG_CAN0_MDL5 (0x400B42B4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 5) */ +#define REG_CAN0_MDH5 (0x400B42B8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 5) */ +#define REG_CAN0_MCR5 (0x400B42BCU) /**< \brief (CAN0) Mailbox Control Register (MB = 5) */ +#define REG_CAN0_MMR6 (0x400B42C0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 6) */ +#define REG_CAN0_MAM6 (0x400B42C4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 6) */ +#define REG_CAN0_MID6 (0x400B42C8U) /**< \brief (CAN0) Mailbox ID Register (MB = 6) */ +#define REG_CAN0_MFID6 (0x400B42CCU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 6) */ +#define REG_CAN0_MSR6 (0x400B42D0U) /**< \brief (CAN0) Mailbox Status Register (MB = 6) */ +#define REG_CAN0_MDL6 (0x400B42D4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 6) */ +#define REG_CAN0_MDH6 (0x400B42D8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 6) */ +#define REG_CAN0_MCR6 (0x400B42DCU) /**< \brief (CAN0) Mailbox Control Register (MB = 6) */ +#define REG_CAN0_MMR7 (0x400B42E0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 7) */ +#define REG_CAN0_MAM7 (0x400B42E4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 7) */ +#define REG_CAN0_MID7 (0x400B42E8U) /**< \brief (CAN0) Mailbox ID Register (MB = 7) */ +#define REG_CAN0_MFID7 (0x400B42ECU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 7) */ +#define REG_CAN0_MSR7 (0x400B42F0U) /**< \brief (CAN0) Mailbox Status Register (MB = 7) */ +#define REG_CAN0_MDL7 (0x400B42F4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 7) */ +#define REG_CAN0_MDH7 (0x400B42F8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 7) */ +#define REG_CAN0_MCR7 (0x400B42FCU) /**< \brief (CAN0) Mailbox Control Register (MB = 7) */ +#else +#define REG_CAN0_MR (*(RwReg*)0x400B4000U) /**< \brief (CAN0) Mode Register */ +#define REG_CAN0_IER (*(WoReg*)0x400B4004U) /**< \brief (CAN0) Interrupt Enable Register */ +#define REG_CAN0_IDR (*(WoReg*)0x400B4008U) /**< \brief (CAN0) Interrupt Disable Register */ +#define REG_CAN0_IMR (*(RoReg*)0x400B400CU) /**< \brief (CAN0) Interrupt Mask Register */ +#define REG_CAN0_SR (*(RoReg*)0x400B4010U) /**< \brief (CAN0) Status Register */ +#define REG_CAN0_BR (*(RwReg*)0x400B4014U) /**< \brief (CAN0) Baudrate Register */ +#define REG_CAN0_TIM (*(RoReg*)0x400B4018U) /**< \brief (CAN0) Timer Register */ +#define REG_CAN0_TIMESTP (*(RoReg*)0x400B401CU) /**< \brief (CAN0) Timestamp Register */ +#define REG_CAN0_ECR (*(RoReg*)0x400B4020U) /**< \brief (CAN0) Error Counter Register */ +#define REG_CAN0_TCR (*(WoReg*)0x400B4024U) /**< \brief (CAN0) Transfer Command Register */ +#define REG_CAN0_ACR (*(WoReg*)0x400B4028U) /**< \brief (CAN0) Abort Command Register */ +#define REG_CAN0_WPMR (*(RwReg*)0x400B40E4U) /**< \brief (CAN0) Write Protect Mode Register */ +#define REG_CAN0_WPSR (*(RoReg*)0x400B40E8U) /**< \brief (CAN0) Write Protect Status Register */ +#define REG_CAN0_MMR0 (*(RwReg*)0x400B4200U) /**< \brief (CAN0) Mailbox Mode Register (MB = 0) */ +#define REG_CAN0_MAM0 (*(RwReg*)0x400B4204U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 0) */ +#define REG_CAN0_MID0 (*(RwReg*)0x400B4208U) /**< \brief (CAN0) Mailbox ID Register (MB = 0) */ +#define REG_CAN0_MFID0 (*(RoReg*)0x400B420CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 0) */ +#define REG_CAN0_MSR0 (*(RoReg*)0x400B4210U) /**< \brief (CAN0) Mailbox Status Register (MB = 0) */ +#define REG_CAN0_MDL0 (*(RwReg*)0x400B4214U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 0) */ +#define REG_CAN0_MDH0 (*(RwReg*)0x400B4218U) /**< \brief (CAN0) Mailbox Data High Register (MB = 0) */ +#define REG_CAN0_MCR0 (*(WoReg*)0x400B421CU) /**< \brief (CAN0) Mailbox Control Register (MB = 0) */ +#define REG_CAN0_MMR1 (*(RwReg*)0x400B4220U) /**< \brief (CAN0) Mailbox Mode Register (MB = 1) */ +#define REG_CAN0_MAM1 (*(RwReg*)0x400B4224U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 1) */ +#define REG_CAN0_MID1 (*(RwReg*)0x400B4228U) /**< \brief (CAN0) Mailbox ID Register (MB = 1) */ +#define REG_CAN0_MFID1 (*(RoReg*)0x400B422CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 1) */ +#define REG_CAN0_MSR1 (*(RoReg*)0x400B4230U) /**< \brief (CAN0) Mailbox Status Register (MB = 1) */ +#define REG_CAN0_MDL1 (*(RwReg*)0x400B4234U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 1) */ +#define REG_CAN0_MDH1 (*(RwReg*)0x400B4238U) /**< \brief (CAN0) Mailbox Data High Register (MB = 1) */ +#define REG_CAN0_MCR1 (*(WoReg*)0x400B423CU) /**< \brief (CAN0) Mailbox Control Register (MB = 1) */ +#define REG_CAN0_MMR2 (*(RwReg*)0x400B4240U) /**< \brief (CAN0) Mailbox Mode Register (MB = 2) */ +#define REG_CAN0_MAM2 (*(RwReg*)0x400B4244U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 2) */ +#define REG_CAN0_MID2 (*(RwReg*)0x400B4248U) /**< \brief (CAN0) Mailbox ID Register (MB = 2) */ +#define REG_CAN0_MFID2 (*(RoReg*)0x400B424CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 2) */ +#define REG_CAN0_MSR2 (*(RoReg*)0x400B4250U) /**< \brief (CAN0) Mailbox Status Register (MB = 2) */ +#define REG_CAN0_MDL2 (*(RwReg*)0x400B4254U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 2) */ +#define REG_CAN0_MDH2 (*(RwReg*)0x400B4258U) /**< \brief (CAN0) Mailbox Data High Register (MB = 2) */ +#define REG_CAN0_MCR2 (*(WoReg*)0x400B425CU) /**< \brief (CAN0) Mailbox Control Register (MB = 2) */ +#define REG_CAN0_MMR3 (*(RwReg*)0x400B4260U) /**< \brief (CAN0) Mailbox Mode Register (MB = 3) */ +#define REG_CAN0_MAM3 (*(RwReg*)0x400B4264U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 3) */ +#define REG_CAN0_MID3 (*(RwReg*)0x400B4268U) /**< \brief (CAN0) Mailbox ID Register (MB = 3) */ +#define REG_CAN0_MFID3 (*(RoReg*)0x400B426CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 3) */ +#define REG_CAN0_MSR3 (*(RoReg*)0x400B4270U) /**< \brief (CAN0) Mailbox Status Register (MB = 3) */ +#define REG_CAN0_MDL3 (*(RwReg*)0x400B4274U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 3) */ +#define REG_CAN0_MDH3 (*(RwReg*)0x400B4278U) /**< \brief (CAN0) Mailbox Data High Register (MB = 3) */ +#define REG_CAN0_MCR3 (*(WoReg*)0x400B427CU) /**< \brief (CAN0) Mailbox Control Register (MB = 3) */ +#define REG_CAN0_MMR4 (*(RwReg*)0x400B4280U) /**< \brief (CAN0) Mailbox Mode Register (MB = 4) */ +#define REG_CAN0_MAM4 (*(RwReg*)0x400B4284U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 4) */ +#define REG_CAN0_MID4 (*(RwReg*)0x400B4288U) /**< \brief (CAN0) Mailbox ID Register (MB = 4) */ +#define REG_CAN0_MFID4 (*(RoReg*)0x400B428CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 4) */ +#define REG_CAN0_MSR4 (*(RoReg*)0x400B4290U) /**< \brief (CAN0) Mailbox Status Register (MB = 4) */ +#define REG_CAN0_MDL4 (*(RwReg*)0x400B4294U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 4) */ +#define REG_CAN0_MDH4 (*(RwReg*)0x400B4298U) /**< \brief (CAN0) Mailbox Data High Register (MB = 4) */ +#define REG_CAN0_MCR4 (*(WoReg*)0x400B429CU) /**< \brief (CAN0) Mailbox Control Register (MB = 4) */ +#define REG_CAN0_MMR5 (*(RwReg*)0x400B42A0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 5) */ +#define REG_CAN0_MAM5 (*(RwReg*)0x400B42A4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 5) */ +#define REG_CAN0_MID5 (*(RwReg*)0x400B42A8U) /**< \brief (CAN0) Mailbox ID Register (MB = 5) */ +#define REG_CAN0_MFID5 (*(RoReg*)0x400B42ACU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 5) */ +#define REG_CAN0_MSR5 (*(RoReg*)0x400B42B0U) /**< \brief (CAN0) Mailbox Status Register (MB = 5) */ +#define REG_CAN0_MDL5 (*(RwReg*)0x400B42B4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 5) */ +#define REG_CAN0_MDH5 (*(RwReg*)0x400B42B8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 5) */ +#define REG_CAN0_MCR5 (*(WoReg*)0x400B42BCU) /**< \brief (CAN0) Mailbox Control Register (MB = 5) */ +#define REG_CAN0_MMR6 (*(RwReg*)0x400B42C0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 6) */ +#define REG_CAN0_MAM6 (*(RwReg*)0x400B42C4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 6) */ +#define REG_CAN0_MID6 (*(RwReg*)0x400B42C8U) /**< \brief (CAN0) Mailbox ID Register (MB = 6) */ +#define REG_CAN0_MFID6 (*(RoReg*)0x400B42CCU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 6) */ +#define REG_CAN0_MSR6 (*(RoReg*)0x400B42D0U) /**< \brief (CAN0) Mailbox Status Register (MB = 6) */ +#define REG_CAN0_MDL6 (*(RwReg*)0x400B42D4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 6) */ +#define REG_CAN0_MDH6 (*(RwReg*)0x400B42D8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 6) */ +#define REG_CAN0_MCR6 (*(WoReg*)0x400B42DCU) /**< \brief (CAN0) Mailbox Control Register (MB = 6) */ +#define REG_CAN0_MMR7 (*(RwReg*)0x400B42E0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 7) */ +#define REG_CAN0_MAM7 (*(RwReg*)0x400B42E4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 7) */ +#define REG_CAN0_MID7 (*(RwReg*)0x400B42E8U) /**< \brief (CAN0) Mailbox ID Register (MB = 7) */ +#define REG_CAN0_MFID7 (*(RoReg*)0x400B42ECU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 7) */ +#define REG_CAN0_MSR7 (*(RoReg*)0x400B42F0U) /**< \brief (CAN0) Mailbox Status Register (MB = 7) */ +#define REG_CAN0_MDL7 (*(RwReg*)0x400B42F4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 7) */ +#define REG_CAN0_MDH7 (*(RwReg*)0x400B42F8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 7) */ +#define REG_CAN0_MCR7 (*(WoReg*)0x400B42FCU) /**< \brief (CAN0) Mailbox Control Register (MB = 7) */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_CAN0_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_can1.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_can1.h new file mode 100644 index 0000000..52c092f --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_can1.h
@@ -0,0 +1,204 @@ +/** + * \file + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM3XA_CAN1_INSTANCE_ +#define _SAM3XA_CAN1_INSTANCE_ + +/* ========== Register definition for CAN1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_CAN1_MR (0x400B8000U) /**< \brief (CAN1) Mode Register */ +#define REG_CAN1_IER (0x400B8004U) /**< \brief (CAN1) Interrupt Enable Register */ +#define REG_CAN1_IDR (0x400B8008U) /**< \brief (CAN1) Interrupt Disable Register */ +#define REG_CAN1_IMR (0x400B800CU) /**< \brief (CAN1) Interrupt Mask Register */ +#define REG_CAN1_SR (0x400B8010U) /**< \brief (CAN1) Status Register */ +#define REG_CAN1_BR (0x400B8014U) /**< \brief (CAN1) Baudrate Register */ +#define REG_CAN1_TIM (0x400B8018U) /**< \brief (CAN1) Timer Register */ +#define REG_CAN1_TIMESTP (0x400B801CU) /**< \brief (CAN1) Timestamp Register */ +#define REG_CAN1_ECR (0x400B8020U) /**< \brief (CAN1) Error Counter Register */ +#define REG_CAN1_TCR (0x400B8024U) /**< \brief (CAN1) Transfer Command Register */ +#define REG_CAN1_ACR (0x400B8028U) /**< \brief (CAN1) Abort Command Register */ +#define REG_CAN1_WPMR (0x400B80E4U) /**< \brief (CAN1) Write Protect Mode Register */ +#define REG_CAN1_WPSR (0x400B80E8U) /**< \brief (CAN1) Write Protect Status Register */ +#define REG_CAN1_MMR0 (0x400B8200U) /**< \brief (CAN1) Mailbox Mode Register (MB = 0) */ +#define REG_CAN1_MAM0 (0x400B8204U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 0) */ +#define REG_CAN1_MID0 (0x400B8208U) /**< \brief (CAN1) Mailbox ID Register (MB = 0) */ +#define REG_CAN1_MFID0 (0x400B820CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 0) */ +#define REG_CAN1_MSR0 (0x400B8210U) /**< \brief (CAN1) Mailbox Status Register (MB = 0) */ +#define REG_CAN1_MDL0 (0x400B8214U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 0) */ +#define REG_CAN1_MDH0 (0x400B8218U) /**< \brief (CAN1) Mailbox Data High Register (MB = 0) */ +#define REG_CAN1_MCR0 (0x400B821CU) /**< \brief (CAN1) Mailbox Control Register (MB = 0) */ +#define REG_CAN1_MMR1 (0x400B8220U) /**< \brief (CAN1) Mailbox Mode Register (MB = 1) */ +#define REG_CAN1_MAM1 (0x400B8224U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 1) */ +#define REG_CAN1_MID1 (0x400B8228U) /**< \brief (CAN1) Mailbox ID Register (MB = 1) */ +#define REG_CAN1_MFID1 (0x400B822CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 1) */ +#define REG_CAN1_MSR1 (0x400B8230U) /**< \brief (CAN1) Mailbox Status Register (MB = 1) */ +#define REG_CAN1_MDL1 (0x400B8234U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 1) */ +#define REG_CAN1_MDH1 (0x400B8238U) /**< \brief (CAN1) Mailbox Data High Register (MB = 1) */ +#define REG_CAN1_MCR1 (0x400B823CU) /**< \brief (CAN1) Mailbox Control Register (MB = 1) */ +#define REG_CAN1_MMR2 (0x400B8240U) /**< \brief (CAN1) Mailbox Mode Register (MB = 2) */ +#define REG_CAN1_MAM2 (0x400B8244U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 2) */ +#define REG_CAN1_MID2 (0x400B8248U) /**< \brief (CAN1) Mailbox ID Register (MB = 2) */ +#define REG_CAN1_MFID2 (0x400B824CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 2) */ +#define REG_CAN1_MSR2 (0x400B8250U) /**< \brief (CAN1) Mailbox Status Register (MB = 2) */ +#define REG_CAN1_MDL2 (0x400B8254U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 2) */ +#define REG_CAN1_MDH2 (0x400B8258U) /**< \brief (CAN1) Mailbox Data High Register (MB = 2) */ +#define REG_CAN1_MCR2 (0x400B825CU) /**< \brief (CAN1) Mailbox Control Register (MB = 2) */ +#define REG_CAN1_MMR3 (0x400B8260U) /**< \brief (CAN1) Mailbox Mode Register (MB = 3) */ +#define REG_CAN1_MAM3 (0x400B8264U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 3) */ +#define REG_CAN1_MID3 (0x400B8268U) /**< \brief (CAN1) Mailbox ID Register (MB = 3) */ +#define REG_CAN1_MFID3 (0x400B826CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 3) */ +#define REG_CAN1_MSR3 (0x400B8270U) /**< \brief (CAN1) Mailbox Status Register (MB = 3) */ +#define REG_CAN1_MDL3 (0x400B8274U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 3) */ +#define REG_CAN1_MDH3 (0x400B8278U) /**< \brief (CAN1) Mailbox Data High Register (MB = 3) */ +#define REG_CAN1_MCR3 (0x400B827CU) /**< \brief (CAN1) Mailbox Control Register (MB = 3) */ +#define REG_CAN1_MMR4 (0x400B8280U) /**< \brief (CAN1) Mailbox Mode Register (MB = 4) */ +#define REG_CAN1_MAM4 (0x400B8284U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 4) */ +#define REG_CAN1_MID4 (0x400B8288U) /**< \brief (CAN1) Mailbox ID Register (MB = 4) */ +#define REG_CAN1_MFID4 (0x400B828CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 4) */ +#define REG_CAN1_MSR4 (0x400B8290U) /**< \brief (CAN1) Mailbox Status Register (MB = 4) */ +#define REG_CAN1_MDL4 (0x400B8294U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 4) */ +#define REG_CAN1_MDH4 (0x400B8298U) /**< \brief (CAN1) Mailbox Data High Register (MB = 4) */ +#define REG_CAN1_MCR4 (0x400B829CU) /**< \brief (CAN1) Mailbox Control Register (MB = 4) */ +#define REG_CAN1_MMR5 (0x400B82A0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 5) */ +#define REG_CAN1_MAM5 (0x400B82A4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 5) */ +#define REG_CAN1_MID5 (0x400B82A8U) /**< \brief (CAN1) Mailbox ID Register (MB = 5) */ +#define REG_CAN1_MFID5 (0x400B82ACU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 5) */ +#define REG_CAN1_MSR5 (0x400B82B0U) /**< \brief (CAN1) Mailbox Status Register (MB = 5) */ +#define REG_CAN1_MDL5 (0x400B82B4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 5) */ +#define REG_CAN1_MDH5 (0x400B82B8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 5) */ +#define REG_CAN1_MCR5 (0x400B82BCU) /**< \brief (CAN1) Mailbox Control Register (MB = 5) */ +#define REG_CAN1_MMR6 (0x400B82C0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 6) */ +#define REG_CAN1_MAM6 (0x400B82C4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 6) */ +#define REG_CAN1_MID6 (0x400B82C8U) /**< \brief (CAN1) Mailbox ID Register (MB = 6) */ +#define REG_CAN1_MFID6 (0x400B82CCU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 6) */ +#define REG_CAN1_MSR6 (0x400B82D0U) /**< \brief (CAN1) Mailbox Status Register (MB = 6) */ +#define REG_CAN1_MDL6 (0x400B82D4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 6) */ +#define REG_CAN1_MDH6 (0x400B82D8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 6) */ +#define REG_CAN1_MCR6 (0x400B82DCU) /**< \brief (CAN1) Mailbox Control Register (MB = 6) */ +#define REG_CAN1_MMR7 (0x400B82E0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 7) */ +#define REG_CAN1_MAM7 (0x400B82E4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 7) */ +#define REG_CAN1_MID7 (0x400B82E8U) /**< \brief (CAN1) Mailbox ID Register (MB = 7) */ +#define REG_CAN1_MFID7 (0x400B82ECU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 7) */ +#define REG_CAN1_MSR7 (0x400B82F0U) /**< \brief (CAN1) Mailbox Status Register (MB = 7) */ +#define REG_CAN1_MDL7 (0x400B82F4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 7) */ +#define REG_CAN1_MDH7 (0x400B82F8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 7) */ +#define REG_CAN1_MCR7 (0x400B82FCU) /**< \brief (CAN1) Mailbox Control Register (MB = 7) */ +#else +#define REG_CAN1_MR (*(RwReg*)0x400B8000U) /**< \brief (CAN1) Mode Register */ +#define REG_CAN1_IER (*(WoReg*)0x400B8004U) /**< \brief (CAN1) Interrupt Enable Register */ +#define REG_CAN1_IDR (*(WoReg*)0x400B8008U) /**< \brief (CAN1) Interrupt Disable Register */ +#define REG_CAN1_IMR (*(RoReg*)0x400B800CU) /**< \brief (CAN1) Interrupt Mask Register */ +#define REG_CAN1_SR (*(RoReg*)0x400B8010U) /**< \brief (CAN1) Status Register */ +#define REG_CAN1_BR (*(RwReg*)0x400B8014U) /**< \brief (CAN1) Baudrate Register */ +#define REG_CAN1_TIM (*(RoReg*)0x400B8018U) /**< \brief (CAN1) Timer Register */ +#define REG_CAN1_TIMESTP (*(RoReg*)0x400B801CU) /**< \brief (CAN1) Timestamp Register */ +#define REG_CAN1_ECR (*(RoReg*)0x400B8020U) /**< \brief (CAN1) Error Counter Register */ +#define REG_CAN1_TCR (*(WoReg*)0x400B8024U) /**< \brief (CAN1) Transfer Command Register */ +#define REG_CAN1_ACR (*(WoReg*)0x400B8028U) /**< \brief (CAN1) Abort Command Register */ +#define REG_CAN1_WPMR (*(RwReg*)0x400B80E4U) /**< \brief (CAN1) Write Protect Mode Register */ +#define REG_CAN1_WPSR (*(RoReg*)0x400B80E8U) /**< \brief (CAN1) Write Protect Status Register */ +#define REG_CAN1_MMR0 (*(RwReg*)0x400B8200U) /**< \brief (CAN1) Mailbox Mode Register (MB = 0) */ +#define REG_CAN1_MAM0 (*(RwReg*)0x400B8204U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 0) */ +#define REG_CAN1_MID0 (*(RwReg*)0x400B8208U) /**< \brief (CAN1) Mailbox ID Register (MB = 0) */ +#define REG_CAN1_MFID0 (*(RoReg*)0x400B820CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 0) */ +#define REG_CAN1_MSR0 (*(RoReg*)0x400B8210U) /**< \brief (CAN1) Mailbox Status Register (MB = 0) */ +#define REG_CAN1_MDL0 (*(RwReg*)0x400B8214U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 0) */ +#define REG_CAN1_MDH0 (*(RwReg*)0x400B8218U) /**< \brief (CAN1) Mailbox Data High Register (MB = 0) */ +#define REG_CAN1_MCR0 (*(WoReg*)0x400B821CU) /**< \brief (CAN1) Mailbox Control Register (MB = 0) */ +#define REG_CAN1_MMR1 (*(RwReg*)0x400B8220U) /**< \brief (CAN1) Mailbox Mode Register (MB = 1) */ +#define REG_CAN1_MAM1 (*(RwReg*)0x400B8224U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 1) */ +#define REG_CAN1_MID1 (*(RwReg*)0x400B8228U) /**< \brief (CAN1) Mailbox ID Register (MB = 1) */ +#define REG_CAN1_MFID1 (*(RoReg*)0x400B822CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 1) */ +#define REG_CAN1_MSR1 (*(RoReg*)0x400B8230U) /**< \brief (CAN1) Mailbox Status Register (MB = 1) */ +#define REG_CAN1_MDL1 (*(RwReg*)0x400B8234U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 1) */ +#define REG_CAN1_MDH1 (*(RwReg*)0x400B8238U) /**< \brief (CAN1) Mailbox Data High Register (MB = 1) */ +#define REG_CAN1_MCR1 (*(WoReg*)0x400B823CU) /**< \brief (CAN1) Mailbox Control Register (MB = 1) */ +#define REG_CAN1_MMR2 (*(RwReg*)0x400B8240U) /**< \brief (CAN1) Mailbox Mode Register (MB = 2) */ +#define REG_CAN1_MAM2 (*(RwReg*)0x400B8244U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 2) */ +#define REG_CAN1_MID2 (*(RwReg*)0x400B8248U) /**< \brief (CAN1) Mailbox ID Register (MB = 2) */ +#define REG_CAN1_MFID2 (*(RoReg*)0x400B824CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 2) */ +#define REG_CAN1_MSR2 (*(RoReg*)0x400B8250U) /**< \brief (CAN1) Mailbox Status Register (MB = 2) */ +#define REG_CAN1_MDL2 (*(RwReg*)0x400B8254U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 2) */ +#define REG_CAN1_MDH2 (*(RwReg*)0x400B8258U) /**< \brief (CAN1) Mailbox Data High Register (MB = 2) */ +#define REG_CAN1_MCR2 (*(WoReg*)0x400B825CU) /**< \brief (CAN1) Mailbox Control Register (MB = 2) */ +#define REG_CAN1_MMR3 (*(RwReg*)0x400B8260U) /**< \brief (CAN1) Mailbox Mode Register (MB = 3) */ +#define REG_CAN1_MAM3 (*(RwReg*)0x400B8264U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 3) */ +#define REG_CAN1_MID3 (*(RwReg*)0x400B8268U) /**< \brief (CAN1) Mailbox ID Register (MB = 3) */ +#define REG_CAN1_MFID3 (*(RoReg*)0x400B826CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 3) */ +#define REG_CAN1_MSR3 (*(RoReg*)0x400B8270U) /**< \brief (CAN1) Mailbox Status Register (MB = 3) */ +#define REG_CAN1_MDL3 (*(RwReg*)0x400B8274U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 3) */ +#define REG_CAN1_MDH3 (*(RwReg*)0x400B8278U) /**< \brief (CAN1) Mailbox Data High Register (MB = 3) */ +#define REG_CAN1_MCR3 (*(WoReg*)0x400B827CU) /**< \brief (CAN1) Mailbox Control Register (MB = 3) */ +#define REG_CAN1_MMR4 (*(RwReg*)0x400B8280U) /**< \brief (CAN1) Mailbox Mode Register (MB = 4) */ +#define REG_CAN1_MAM4 (*(RwReg*)0x400B8284U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 4) */ +#define REG_CAN1_MID4 (*(RwReg*)0x400B8288U) /**< \brief (CAN1) Mailbox ID Register (MB = 4) */ +#define REG_CAN1_MFID4 (*(RoReg*)0x400B828CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 4) */ +#define REG_CAN1_MSR4 (*(RoReg*)0x400B8290U) /**< \brief (CAN1) Mailbox Status Register (MB = 4) */ +#define REG_CAN1_MDL4 (*(RwReg*)0x400B8294U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 4) */ +#define REG_CAN1_MDH4 (*(RwReg*)0x400B8298U) /**< \brief (CAN1) Mailbox Data High Register (MB = 4) */ +#define REG_CAN1_MCR4 (*(WoReg*)0x400B829CU) /**< \brief (CAN1) Mailbox Control Register (MB = 4) */ +#define REG_CAN1_MMR5 (*(RwReg*)0x400B82A0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 5) */ +#define REG_CAN1_MAM5 (*(RwReg*)0x400B82A4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 5) */ +#define REG_CAN1_MID5 (*(RwReg*)0x400B82A8U) /**< \brief (CAN1) Mailbox ID Register (MB = 5) */ +#define REG_CAN1_MFID5 (*(RoReg*)0x400B82ACU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 5) */ +#define REG_CAN1_MSR5 (*(RoReg*)0x400B82B0U) /**< \brief (CAN1) Mailbox Status Register (MB = 5) */ +#define REG_CAN1_MDL5 (*(RwReg*)0x400B82B4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 5) */ +#define REG_CAN1_MDH5 (*(RwReg*)0x400B82B8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 5) */ +#define REG_CAN1_MCR5 (*(WoReg*)0x400B82BCU) /**< \brief (CAN1) Mailbox Control Register (MB = 5) */ +#define REG_CAN1_MMR6 (*(RwReg*)0x400B82C0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 6) */ +#define REG_CAN1_MAM6 (*(RwReg*)0x400B82C4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 6) */ +#define REG_CAN1_MID6 (*(RwReg*)0x400B82C8U) /**< \brief (CAN1) Mailbox ID Register (MB = 6) */ +#define REG_CAN1_MFID6 (*(RoReg*)0x400B82CCU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 6) */ +#define REG_CAN1_MSR6 (*(RoReg*)0x400B82D0U) /**< \brief (CAN1) Mailbox Status Register (MB = 6) */ +#define REG_CAN1_MDL6 (*(RwReg*)0x400B82D4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 6) */ +#define REG_CAN1_MDH6 (*(RwReg*)0x400B82D8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 6) */ +#define REG_CAN1_MCR6 (*(WoReg*)0x400B82DCU) /**< \brief (CAN1) Mailbox Control Register (MB = 6) */ +#define REG_CAN1_MMR7 (*(RwReg*)0x400B82E0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 7) */ +#define REG_CAN1_MAM7 (*(RwReg*)0x400B82E4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 7) */ +#define REG_CAN1_MID7 (*(RwReg*)0x400B82E8U) /**< \brief (CAN1) Mailbox ID Register (MB = 7) */ +#define REG_CAN1_MFID7 (*(RoReg*)0x400B82ECU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 7) */ +#define REG_CAN1_MSR7 (*(RoReg*)0x400B82F0U) /**< \brief (CAN1) Mailbox Status Register (MB = 7) */ +#define REG_CAN1_MDL7 (*(RwReg*)0x400B82F4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 7) */ +#define REG_CAN1_MDH7 (*(RwReg*)0x400B82F8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 7) */ +#define REG_CAN1_MCR7 (*(WoReg*)0x400B82FCU) /**< \brief (CAN1) Mailbox Control Register (MB = 7) */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_CAN1_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h new file mode 100644 index 0000000..cfd5f8d --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h
@@ -0,0 +1,54 @@ +/** + * \file + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM3XA_CHIPID_INSTANCE_ +#define _SAM3XA_CHIPID_INSTANCE_ + +/* ========== Register definition for CHIPID peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_CHIPID_CIDR (0x400E0940U) /**< \brief (CHIPID) Chip ID Register */ +#define REG_CHIPID_EXID (0x400E0944U) /**< \brief (CHIPID) Chip ID Extension Register */ +#else +#define REG_CHIPID_CIDR (*(RoReg*)0x400E0940U) /**< \brief (CHIPID) Chip ID Register */ +#define REG_CHIPID_EXID (*(RoReg*)0x400E0944U) /**< \brief (CHIPID) Chip ID Extension Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_CHIPID_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h new file mode 100644 index 0000000..4822d93 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h
@@ -0,0 +1,88 @@ +/** + * \file + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM3XA_DACC_INSTANCE_ +#define _SAM3XA_DACC_INSTANCE_ + +/* ========== Register definition for DACC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_DACC_CR (0x400C8000U) /**< \brief (DACC) Control Register */ +#define REG_DACC_MR (0x400C8004U) /**< \brief (DACC) Mode Register */ +#define REG_DACC_CHER (0x400C8010U) /**< \brief (DACC) Channel Enable Register */ +#define REG_DACC_CHDR (0x400C8014U) /**< \brief (DACC) Channel Disable Register */ +#define REG_DACC_CHSR (0x400C8018U) /**< \brief (DACC) Channel Status Register */ +#define REG_DACC_CDR (0x400C8020U) /**< \brief (DACC) Conversion Data Register */ +#define REG_DACC_IER (0x400C8024U) /**< \brief (DACC) Interrupt Enable Register */ +#define REG_DACC_IDR (0x400C8028U) /**< \brief (DACC) Interrupt Disable Register */ +#define REG_DACC_IMR (0x400C802CU) /**< \brief (DACC) Interrupt Mask Register */ +#define REG_DACC_ISR (0x400C8030U) /**< \brief (DACC) Interrupt Status Register */ +#define REG_DACC_ACR (0x400C8094U) /**< \brief (DACC) Analog Current Register */ +#define REG_DACC_WPMR (0x400C80E4U) /**< \brief (DACC) Write Protect Mode register */ +#define REG_DACC_WPSR (0x400C80E8U) /**< \brief (DACC) Write Protect Status register */ +#define REG_DACC_TPR (0x400C8108U) /**< \brief (DACC) Transmit Pointer Register */ +#define REG_DACC_TCR (0x400C810CU) /**< \brief (DACC) Transmit Counter Register */ +#define REG_DACC_TNPR (0x400C8118U) /**< \brief (DACC) Transmit Next Pointer Register */ +#define REG_DACC_TNCR (0x400C811CU) /**< \brief (DACC) Transmit Next Counter Register */ +#define REG_DACC_PTCR (0x400C8120U) /**< \brief (DACC) Transfer Control Register */ +#define REG_DACC_PTSR (0x400C8124U) /**< \brief (DACC) Transfer Status Register */ +#else +#define REG_DACC_CR (*(WoReg*)0x400C8000U) /**< \brief (DACC) Control Register */ +#define REG_DACC_MR (*(RwReg*)0x400C8004U) /**< \brief (DACC) Mode Register */ +#define REG_DACC_CHER (*(WoReg*)0x400C8010U) /**< \brief (DACC) Channel Enable Register */ +#define REG_DACC_CHDR (*(WoReg*)0x400C8014U) /**< \brief (DACC) Channel Disable Register */ +#define REG_DACC_CHSR (*(RoReg*)0x400C8018U) /**< \brief (DACC) Channel Status Register */ +#define REG_DACC_CDR (*(WoReg*)0x400C8020U) /**< \brief (DACC) Conversion Data Register */ +#define REG_DACC_IER (*(WoReg*)0x400C8024U) /**< \brief (DACC) Interrupt Enable Register */ +#define REG_DACC_IDR (*(WoReg*)0x400C8028U) /**< \brief (DACC) Interrupt Disable Register */ +#define REG_DACC_IMR (*(RoReg*)0x400C802CU) /**< \brief (DACC) Interrupt Mask Register */ +#define REG_DACC_ISR (*(RoReg*)0x400C8030U) /**< \brief (DACC) Interrupt Status Register */ +#define REG_DACC_ACR (*(RwReg*)0x400C8094U) /**< \brief (DACC) Analog Current Register */ +#define REG_DACC_WPMR (*(RwReg*)0x400C80E4U) /**< \brief (DACC) Write Protect Mode register */ +#define REG_DACC_WPSR (*(RoReg*)0x400C80E8U) /**< \brief (DACC) Write Protect Status register */ +#define REG_DACC_TPR (*(RwReg*)0x400C8108U) /**< \brief (DACC) Transmit Pointer Register */ +#define REG_DACC_TCR (*(RwReg*)0x400C810CU) /**< \brief (DACC) Transmit Counter Register */ +#define REG_DACC_TNPR (*(RwReg*)0x400C8118U) /**< \brief (DACC) Transmit Next Pointer Register */ +#define REG_DACC_TNCR (*(RwReg*)0x400C811CU) /**< \brief (DACC) Transmit Next Counter Register */ +#define REG_DACC_PTCR (*(WoReg*)0x400C8120U) /**< \brief (DACC) Transfer Control Register */ +#define REG_DACC_PTSR (*(RoReg*)0x400C8124U) /**< \brief (DACC) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_DACC_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h new file mode 100644 index 0000000..6de0459 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h
@@ -0,0 +1,150 @@ +/** + * \file + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM3XA_DMAC_INSTANCE_ +#define _SAM3XA_DMAC_INSTANCE_ + +/* ========== Register definition for DMAC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_DMAC_GCFG (0x400C4000U) /**< \brief (DMAC) DMAC Global Configuration Register */ +#define REG_DMAC_EN (0x400C4004U) /**< \brief (DMAC) DMAC Enable Register */ +#define REG_DMAC_SREQ (0x400C4008U) /**< \brief (DMAC) DMAC Software Single Request Register */ +#define REG_DMAC_CREQ (0x400C400CU) /**< \brief (DMAC) DMAC Software Chunk Transfer Request Register */ +#define REG_DMAC_LAST (0x400C4010U) /**< \brief (DMAC) DMAC Software Last Transfer Flag Register */ +#define REG_DMAC_EBCIER (0x400C4018U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */ +#define REG_DMAC_EBCIDR (0x400C401CU) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */ +#define REG_DMAC_EBCIMR (0x400C4020U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */ +#define REG_DMAC_EBCISR (0x400C4024U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */ +#define REG_DMAC_CHER (0x400C4028U) /**< \brief (DMAC) DMAC Channel Handler Enable Register */ +#define REG_DMAC_CHDR (0x400C402CU) /**< \brief (DMAC) DMAC Channel Handler Disable Register */ +#define REG_DMAC_CHSR (0x400C4030U) /**< \brief (DMAC) DMAC Channel Handler Status Register */ +#define REG_DMAC_SADDR0 (0x400C403CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 0) */ +#define REG_DMAC_DADDR0 (0x400C4040U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 0) */ +#define REG_DMAC_DSCR0 (0x400C4044U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 0) */ +#define REG_DMAC_CTRLA0 (0x400C4048U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 0) */ +#define REG_DMAC_CTRLB0 (0x400C404CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 0) */ +#define REG_DMAC_CFG0 (0x400C4050U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 0) */ +#define REG_DMAC_SADDR1 (0x400C4064U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 1) */ +#define REG_DMAC_DADDR1 (0x400C4068U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 1) */ +#define REG_DMAC_DSCR1 (0x400C406CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 1) */ +#define REG_DMAC_CTRLA1 (0x400C4070U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 1) */ +#define REG_DMAC_CTRLB1 (0x400C4074U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 1) */ +#define REG_DMAC_CFG1 (0x400C4078U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 1) */ +#define REG_DMAC_SADDR2 (0x400C408CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 2) */ +#define REG_DMAC_DADDR2 (0x400C4090U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 2) */ +#define REG_DMAC_DSCR2 (0x400C4094U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 2) */ +#define REG_DMAC_CTRLA2 (0x400C4098U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 2) */ +#define REG_DMAC_CTRLB2 (0x400C409CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 2) */ +#define REG_DMAC_CFG2 (0x400C40A0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 2) */ +#define REG_DMAC_SADDR3 (0x400C40B4U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 3) */ +#define REG_DMAC_DADDR3 (0x400C40B8U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 3) */ +#define REG_DMAC_DSCR3 (0x400C40BCU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 3) */ +#define REG_DMAC_CTRLA3 (0x400C40C0U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 3) */ +#define REG_DMAC_CTRLB3 (0x400C40C4U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 3) */ +#define REG_DMAC_CFG3 (0x400C40C8U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 3) */ +#define REG_DMAC_SADDR4 (0x400C40DCU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 4) */ +#define REG_DMAC_DADDR4 (0x400C40E0U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 4) */ +#define REG_DMAC_DSCR4 (0x400C40E4U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 4) */ +#define REG_DMAC_CTRLA4 (0x400C40E8U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 4) */ +#define REG_DMAC_CTRLB4 (0x400C40ECU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 4) */ +#define REG_DMAC_CFG4 (0x400C40F0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 4) */ +#define REG_DMAC_SADDR5 (0x400C4104U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 5) */ +#define REG_DMAC_DADDR5 (0x400C4108U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 5) */ +#define REG_DMAC_DSCR5 (0x400C410CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 5) */ +#define REG_DMAC_CTRLA5 (0x400C4110U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 5) */ +#define REG_DMAC_CTRLB5 (0x400C4114U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 5) */ +#define REG_DMAC_CFG5 (0x400C4118U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 5) */ +#define REG_DMAC_WPMR (0x400C41E4U) /**< \brief (DMAC) DMAC Write Protect Mode Register */ +#define REG_DMAC_WPSR (0x400C41E8U) /**< \brief (DMAC) DMAC Write Protect Status Register */ +#else +#define REG_DMAC_GCFG (*(RwReg*)0x400C4000U) /**< \brief (DMAC) DMAC Global Configuration Register */ +#define REG_DMAC_EN (*(RwReg*)0x400C4004U) /**< \brief (DMAC) DMAC Enable Register */ +#define REG_DMAC_SREQ (*(RwReg*)0x400C4008U) /**< \brief (DMAC) DMAC Software Single Request Register */ +#define REG_DMAC_CREQ (*(RwReg*)0x400C400CU) /**< \brief (DMAC) DMAC Software Chunk Transfer Request Register */ +#define REG_DMAC_LAST (*(RwReg*)0x400C4010U) /**< \brief (DMAC) DMAC Software Last Transfer Flag Register */ +#define REG_DMAC_EBCIER (*(WoReg*)0x400C4018U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */ +#define REG_DMAC_EBCIDR (*(WoReg*)0x400C401CU) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */ +#define REG_DMAC_EBCIMR (*(RoReg*)0x400C4020U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */ +#define REG_DMAC_EBCISR (*(RoReg*)0x400C4024U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */ +#define REG_DMAC_CHER (*(WoReg*)0x400C4028U) /**< \brief (DMAC) DMAC Channel Handler Enable Register */ +#define REG_DMAC_CHDR (*(WoReg*)0x400C402CU) /**< \brief (DMAC) DMAC Channel Handler Disable Register */ +#define REG_DMAC_CHSR (*(RoReg*)0x400C4030U) /**< \brief (DMAC) DMAC Channel Handler Status Register */ +#define REG_DMAC_SADDR0 (*(RwReg*)0x400C403CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 0) */ +#define REG_DMAC_DADDR0 (*(RwReg*)0x400C4040U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 0) */ +#define REG_DMAC_DSCR0 (*(RwReg*)0x400C4044U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 0) */ +#define REG_DMAC_CTRLA0 (*(RwReg*)0x400C4048U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 0) */ +#define REG_DMAC_CTRLB0 (*(RwReg*)0x400C404CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 0) */ +#define REG_DMAC_CFG0 (*(RwReg*)0x400C4050U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 0) */ +#define REG_DMAC_SADDR1 (*(RwReg*)0x400C4064U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 1) */ +#define REG_DMAC_DADDR1 (*(RwReg*)0x400C4068U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 1) */ +#define REG_DMAC_DSCR1 (*(RwReg*)0x400C406CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 1) */ +#define REG_DMAC_CTRLA1 (*(RwReg*)0x400C4070U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 1) */ +#define REG_DMAC_CTRLB1 (*(RwReg*)0x400C4074U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 1) */ +#define REG_DMAC_CFG1 (*(RwReg*)0x400C4078U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 1) */ +#define REG_DMAC_SADDR2 (*(RwReg*)0x400C408CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 2) */ +#define REG_DMAC_DADDR2 (*(RwReg*)0x400C4090U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 2) */ +#define REG_DMAC_DSCR2 (*(RwReg*)0x400C4094U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 2) */ +#define REG_DMAC_CTRLA2 (*(RwReg*)0x400C4098U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 2) */ +#define REG_DMAC_CTRLB2 (*(RwReg*)0x400C409CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 2) */ +#define REG_DMAC_CFG2 (*(RwReg*)0x400C40A0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 2) */ +#define REG_DMAC_SADDR3 (*(RwReg*)0x400C40B4U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 3) */ +#define REG_DMAC_DADDR3 (*(RwReg*)0x400C40B8U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 3) */ +#define REG_DMAC_DSCR3 (*(RwReg*)0x400C40BCU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 3) */ +#define REG_DMAC_CTRLA3 (*(RwReg*)0x400C40C0U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 3) */ +#define REG_DMAC_CTRLB3 (*(RwReg*)0x400C40C4U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 3) */ +#define REG_DMAC_CFG3 (*(RwReg*)0x400C40C8U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 3) */ +#define REG_DMAC_SADDR4 (*(RwReg*)0x400C40DCU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 4) */ +#define REG_DMAC_DADDR4 (*(RwReg*)0x400C40E0U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 4) */ +#define REG_DMAC_DSCR4 (*(RwReg*)0x400C40E4U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 4) */ +#define REG_DMAC_CTRLA4 (*(RwReg*)0x400C40E8U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 4) */ +#define REG_DMAC_CTRLB4 (*(RwReg*)0x400C40ECU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 4) */ +#define REG_DMAC_CFG4 (*(RwReg*)0x400C40F0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 4) */ +#define REG_DMAC_SADDR5 (*(RwReg*)0x400C4104U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 5) */ +#define REG_DMAC_DADDR5 (*(RwReg*)0x400C4108U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 5) */ +#define REG_DMAC_DSCR5 (*(RwReg*)0x400C410CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 5) */ +#define REG_DMAC_CTRLA5 (*(RwReg*)0x400C4110U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 5) */ +#define REG_DMAC_CTRLB5 (*(RwReg*)0x400C4114U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 5) */ +#define REG_DMAC_CFG5 (*(RwReg*)0x400C4118U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 5) */ +#define REG_DMAC_WPMR (*(RwReg*)0x400C41E4U) /**< \brief (DMAC) DMAC Write Protect Mode Register */ +#define REG_DMAC_WPSR (*(RoReg*)0x400C41E8U) /**< \brief (DMAC) DMAC Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_DMAC_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h new file mode 100644 index 0000000..6dc9ea9 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h
@@ -0,0 +1,58 @@ +/** + * \file + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM3XA_EFC0_INSTANCE_ +#define _SAM3XA_EFC0_INSTANCE_ + +/* ========== Register definition for EFC0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_EFC0_FMR (0x400E0A00U) /**< \brief (EFC0) EEFC Flash Mode Register */ +#define REG_EFC0_FCR (0x400E0A04U) /**< \brief (EFC0) EEFC Flash Command Register */ +#define REG_EFC0_FSR (0x400E0A08U) /**< \brief (EFC0) EEFC Flash Status Register */ +#define REG_EFC0_FRR (0x400E0A0CU) /**< \brief (EFC0) EEFC Flash Result Register */ +#else +#define REG_EFC0_FMR (*(RwReg*)0x400E0A00U) /**< \brief (EFC0) EEFC Flash Mode Register */ +#define REG_EFC0_FCR (*(WoReg*)0x400E0A04U) /**< \brief (EFC0) EEFC Flash Command Register */ +#define REG_EFC0_FSR (*(RoReg*)0x400E0A08U) /**< \brief (EFC0) EEFC Flash Status Register */ +#define REG_EFC0_FRR (*(RoReg*)0x400E0A0CU) /**< \brief (EFC0) EEFC Flash Result Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_EFC0_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h new file mode 100644 index 0000000..5e2217f --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h
@@ -0,0 +1,58 @@ +/** + * \file + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM3XA_EFC1_INSTANCE_ +#define _SAM3XA_EFC1_INSTANCE_ + +/* ========== Register definition for EFC1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_EFC1_FMR (0x400E0C00U) /**< \brief (EFC1) EEFC Flash Mode Register */ +#define REG_EFC1_FCR (0x400E0C04U) /**< \brief (EFC1) EEFC Flash Command Register */ +#define REG_EFC1_FSR (0x400E0C08U) /**< \brief (EFC1) EEFC Flash Status Register */ +#define REG_EFC1_FRR (0x400E0C0CU) /**< \brief (EFC1) EEFC Flash Result Register */ +#else +#define REG_EFC1_FMR (*(RwReg*)0x400E0C00U) /**< \brief (EFC1) EEFC Flash Mode Register */ +#define REG_EFC1_FCR (*(WoReg*)0x400E0C04U) /**< \brief (EFC1) EEFC Flash Command Register */ +#define REG_EFC1_FSR (*(RoReg*)0x400E0C08U) /**< \brief (EFC1) EEFC Flash Status Register */ +#define REG_EFC1_FRR (*(RoReg*)0x400E0C0CU) /**< \brief (EFC1) EEFC Flash Result Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_EFC1_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_emac.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_emac.h new file mode 100644 index 0000000..a862e23 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_emac.h
@@ -0,0 +1,140 @@ +/** + * \file + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM3XA_EMAC_INSTANCE_ +#define _SAM3XA_EMAC_INSTANCE_ + +/* ========== Register definition for EMAC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_EMAC_NCR (0x400B0000U) /**< \brief (EMAC) Network Control Register */ +#define REG_EMAC_NCFGR (0x400B0004U) /**< \brief (EMAC) Network Configuration Register */ +#define REG_EMAC_NSR (0x400B0008U) /**< \brief (EMAC) Network Status Register */ +#define REG_EMAC_TSR (0x400B0014U) /**< \brief (EMAC) Transmit Status Register */ +#define REG_EMAC_RBQP (0x400B0018U) /**< \brief (EMAC) Receive Buffer Queue Pointer Register */ +#define REG_EMAC_TBQP (0x400B001CU) /**< \brief (EMAC) Transmit Buffer Queue Pointer Register */ +#define REG_EMAC_RSR (0x400B0020U) /**< \brief (EMAC) Receive Status Register */ +#define REG_EMAC_ISR (0x400B0024U) /**< \brief (EMAC) Interrupt Status Register */ +#define REG_EMAC_IER (0x400B0028U) /**< \brief (EMAC) Interrupt Enable Register */ +#define REG_EMAC_IDR (0x400B002CU) /**< \brief (EMAC) Interrupt Disable Register */ +#define REG_EMAC_IMR (0x400B0030U) /**< \brief (EMAC) Interrupt Mask Register */ +#define REG_EMAC_MAN (0x400B0034U) /**< \brief (EMAC) Phy Maintenance Register */ +#define REG_EMAC_PTR (0x400B0038U) /**< \brief (EMAC) Pause Time Register */ +#define REG_EMAC_PFR (0x400B003CU) /**< \brief (EMAC) Pause Frames Received Register */ +#define REG_EMAC_FTO (0x400B0040U) /**< \brief (EMAC) Frames Transmitted Ok Register */ +#define REG_EMAC_SCF (0x400B0044U) /**< \brief (EMAC) Single Collision Frames Register */ +#define REG_EMAC_MCF (0x400B0048U) /**< \brief (EMAC) Multiple Collision Frames Register */ +#define REG_EMAC_FRO (0x400B004CU) /**< \brief (EMAC) Frames Received Ok Register */ +#define REG_EMAC_FCSE (0x400B0050U) /**< \brief (EMAC) Frame Check Sequence Errors Register */ +#define REG_EMAC_ALE (0x400B0054U) /**< \brief (EMAC) Alignment Errors Register */ +#define REG_EMAC_DTF (0x400B0058U) /**< \brief (EMAC) Deferred Transmission Frames Register */ +#define REG_EMAC_LCOL (0x400B005CU) /**< \brief (EMAC) Late Collisions Register */ +#define REG_EMAC_ECOL (0x400B0060U) /**< \brief (EMAC) Excessive Collisions Register */ +#define REG_EMAC_TUND (0x400B0064U) /**< \brief (EMAC) Transmit Underrun Errors Register */ +#define REG_EMAC_CSE (0x400B0068U) /**< \brief (EMAC) Carrier Sense Errors Register */ +#define REG_EMAC_RRE (0x400B006CU) /**< \brief (EMAC) Receive Resource Errors Register */ +#define REG_EMAC_ROV (0x400B0070U) /**< \brief (EMAC) Receive Overrun Errors Register */ +#define REG_EMAC_RSE (0x400B0074U) /**< \brief (EMAC) Receive Symbol Errors Register */ +#define REG_EMAC_ELE (0x400B0078U) /**< \brief (EMAC) Excessive Length Errors Register */ +#define REG_EMAC_RJA (0x400B007CU) /**< \brief (EMAC) Receive Jabbers Register */ +#define REG_EMAC_USF (0x400B0080U) /**< \brief (EMAC) Undersize Frames Register */ +#define REG_EMAC_STE (0x400B0084U) /**< \brief (EMAC) SQE Test Errors Register */ +#define REG_EMAC_RLE (0x400B0088U) /**< \brief (EMAC) Received Length Field Mismatch Register */ +#define REG_EMAC_HRB (0x400B0090U) /**< \brief (EMAC) Hash Register Bottom [31:0] Register */ +#define REG_EMAC_HRT (0x400B0094U) /**< \brief (EMAC) Hash Register Top [63:32] Register */ +#define REG_EMAC_SA1B (0x400B0098U) /**< \brief (EMAC) Specific Address 1 Bottom Register */ +#define REG_EMAC_SA1T (0x400B009CU) /**< \brief (EMAC) Specific Address 1 Top Register */ +#define REG_EMAC_SA2B (0x400B00A0U) /**< \brief (EMAC) Specific Address 2 Bottom Register */ +#define REG_EMAC_SA2T (0x400B00A4U) /**< \brief (EMAC) Specific Address 2 Top Register */ +#define REG_EMAC_SA3B (0x400B00A8U) /**< \brief (EMAC) Specific Address 3 Bottom Register */ +#define REG_EMAC_SA3T (0x400B00ACU) /**< \brief (EMAC) Specific Address 3 Top Register */ +#define REG_EMAC_SA4B (0x400B00B0U) /**< \brief (EMAC) Specific Address 4 Bottom Register */ +#define REG_EMAC_SA4T (0x400B00B4U) /**< \brief (EMAC) Specific Address 4 Top Register */ +#define REG_EMAC_TID (0x400B00B8U) /**< \brief (EMAC) Type ID Checking Register */ +#define REG_EMAC_USRIO (0x400B00C0U) /**< \brief (EMAC) User Input/Output Register */ +#else +#define REG_EMAC_NCR (*(RwReg*)0x400B0000U) /**< \brief (EMAC) Network Control Register */ +#define REG_EMAC_NCFGR (*(RwReg*)0x400B0004U) /**< \brief (EMAC) Network Configuration Register */ +#define REG_EMAC_NSR (*(RoReg*)0x400B0008U) /**< \brief (EMAC) Network Status Register */ +#define REG_EMAC_TSR (*(RwReg*)0x400B0014U) /**< \brief (EMAC) Transmit Status Register */ +#define REG_EMAC_RBQP (*(RwReg*)0x400B0018U) /**< \brief (EMAC) Receive Buffer Queue Pointer Register */ +#define REG_EMAC_TBQP (*(RwReg*)0x400B001CU) /**< \brief (EMAC) Transmit Buffer Queue Pointer Register */ +#define REG_EMAC_RSR (*(RwReg*)0x400B0020U) /**< \brief (EMAC) Receive Status Register */ +#define REG_EMAC_ISR (*(RwReg*)0x400B0024U) /**< \brief (EMAC) Interrupt Status Register */ +#define REG_EMAC_IER (*(WoReg*)0x400B0028U) /**< \brief (EMAC) Interrupt Enable Register */ +#define REG_EMAC_IDR (*(WoReg*)0x400B002CU) /**< \brief (EMAC) Interrupt Disable Register */ +#define REG_EMAC_IMR (*(RoReg*)0x400B0030U) /**< \brief (EMAC) Interrupt Mask Register */ +#define REG_EMAC_MAN (*(RwReg*)0x400B0034U) /**< \brief (EMAC) Phy Maintenance Register */ +#define REG_EMAC_PTR (*(RwReg*)0x400B0038U) /**< \brief (EMAC) Pause Time Register */ +#define REG_EMAC_PFR (*(RwReg*)0x400B003CU) /**< \brief (EMAC) Pause Frames Received Register */ +#define REG_EMAC_FTO (*(RwReg*)0x400B0040U) /**< \brief (EMAC) Frames Transmitted Ok Register */ +#define REG_EMAC_SCF (*(RwReg*)0x400B0044U) /**< \brief (EMAC) Single Collision Frames Register */ +#define REG_EMAC_MCF (*(RwReg*)0x400B0048U) /**< \brief (EMAC) Multiple Collision Frames Register */ +#define REG_EMAC_FRO (*(RwReg*)0x400B004CU) /**< \brief (EMAC) Frames Received Ok Register */ +#define REG_EMAC_FCSE (*(RwReg*)0x400B0050U) /**< \brief (EMAC) Frame Check Sequence Errors Register */ +#define REG_EMAC_ALE (*(RwReg*)0x400B0054U) /**< \brief (EMAC) Alignment Errors Register */ +#define REG_EMAC_DTF (*(RwReg*)0x400B0058U) /**< \brief (EMAC) Deferred Transmission Frames Register */ +#define REG_EMAC_LCOL (*(RwReg*)0x400B005CU) /**< \brief (EMAC) Late Collisions Register */ +#define REG_EMAC_ECOL (*(RwReg*)0x400B0060U) /**< \brief (EMAC) Excessive Collisions Register */ +#define REG_EMAC_TUND (*(RwReg*)0x400B0064U) /**< \brief (EMAC) Transmit Underrun Errors Register */ +#define REG_EMAC_CSE (*(RwReg*)0x400B0068U) /**< \brief (EMAC) Carrier Sense Errors Register */ +#define REG_EMAC_RRE (*(RwReg*)0x400B006CU) /**< \brief (EMAC) Receive Resource Errors Register */ +#define REG_EMAC_ROV (*(RwReg*)0x400B0070U) /**< \brief (EMAC) Receive Overrun Errors Register */ +#define REG_EMAC_RSE (*(RwReg*)0x400B0074U) /**< \brief (EMAC) Receive Symbol Errors Register */ +#define REG_EMAC_ELE (*(RwReg*)0x400B0078U) /**< \brief (EMAC) Excessive Length Errors Register */ +#define REG_EMAC_RJA (*(RwReg*)0x400B007CU) /**< \brief (EMAC) Receive Jabbers Register */ +#define REG_EMAC_USF (*(RwReg*)0x400B0080U) /**< \brief (EMAC) Undersize Frames Register */ +#define REG_EMAC_STE (*(RwReg*)0x400B0084U) /**< \brief (EMAC) SQE Test Errors Register */ +#define REG_EMAC_RLE (*(RwReg*)0x400B0088U) /**< \brief (EMAC) Received Length Field Mismatch Register */ +#define REG_EMAC_HRB (*(RwReg*)0x400B0090U) /**< \brief (EMAC) Hash Register Bottom [31:0] Register */ +#define REG_EMAC_HRT (*(RwReg*)0x400B0094U) /**< \brief (EMAC) Hash Register Top [63:32] Register */ +#define REG_EMAC_SA1B (*(RwReg*)0x400B0098U) /**< \brief (EMAC) Specific Address 1 Bottom Register */ +#define REG_EMAC_SA1T (*(RwReg*)0x400B009CU) /**< \brief (EMAC) Specific Address 1 Top Register */ +#define REG_EMAC_SA2B (*(RwReg*)0x400B00A0U) /**< \brief (EMAC) Specific Address 2 Bottom Register */ +#define REG_EMAC_SA2T (*(RwReg*)0x400B00A4U) /**< \brief (EMAC) Specific Address 2 Top Register */ +#define REG_EMAC_SA3B (*(RwReg*)0x400B00A8U) /**< \brief (EMAC) Specific Address 3 Bottom Register */ +#define REG_EMAC_SA3T (*(RwReg*)0x400B00ACU) /**< \brief (EMAC) Specific Address 3 Top Register */ +#define REG_EMAC_SA4B (*(RwReg*)0x400B00B0U) /**< \brief (EMAC) Specific Address 4 Bottom Register */ +#define REG_EMAC_SA4T (*(RwReg*)0x400B00B4U) /**< \brief (EMAC) Specific Address 4 Top Register */ +#define REG_EMAC_TID (*(RwReg*)0x400B00B8U) /**< \brief (EMAC) Type ID Checking Register */ +#define REG_EMAC_USRIO (*(RwReg*)0x400B00C0U) /**< \brief (EMAC) User Input/Output Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_EMAC_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h new file mode 100644 index 0000000..0ec6593 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h
@@ -0,0 +1,52 @@ +/** + * \file + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM3XA_GPBR_INSTANCE_ +#define _SAM3XA_GPBR_INSTANCE_ + +/* ========== Register definition for GPBR peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_GPBR_GPBR (0x400E1A90U) /**< \brief (GPBR) General Purpose Backup Register */ +#else +#define REG_GPBR_GPBR (*(RwReg*)0x400E1A90U) /**< \brief (GPBR) General Purpose Backup Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_GPBR_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h new file mode 100644 index 0000000..b459593 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h
@@ -0,0 +1,90 @@ +/** + * \file + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM3XA_HSMCI_INSTANCE_ +#define _SAM3XA_HSMCI_INSTANCE_ + +/* ========== Register definition for HSMCI peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_HSMCI_CR (0x40000000U) /**< \brief (HSMCI) Control Register */ +#define REG_HSMCI_MR (0x40000004U) /**< \brief (HSMCI) Mode Register */ +#define REG_HSMCI_DTOR (0x40000008U) /**< \brief (HSMCI) Data Timeout Register */ +#define REG_HSMCI_SDCR (0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */ +#define REG_HSMCI_ARGR (0x40000010U) /**< \brief (HSMCI) Argument Register */ +#define REG_HSMCI_CMDR (0x40000014U) /**< \brief (HSMCI) Command Register */ +#define REG_HSMCI_BLKR (0x40000018U) /**< \brief (HSMCI) Block Register */ +#define REG_HSMCI_CSTOR (0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */ +#define REG_HSMCI_RSPR (0x40000020U) /**< \brief (HSMCI) Response Register */ +#define REG_HSMCI_RDR (0x40000030U) /**< \brief (HSMCI) Receive Data Register */ +#define REG_HSMCI_TDR (0x40000034U) /**< \brief (HSMCI) Transmit Data Register */ +#define REG_HSMCI_SR (0x40000040U) /**< \brief (HSMCI) Status Register */ +#define REG_HSMCI_IER (0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */ +#define REG_HSMCI_IDR (0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */ +#define REG_HSMCI_IMR (0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */ +#define REG_HSMCI_DMA (0x40000050U) /**< \brief (HSMCI) DMA Configuration Register */ +#define REG_HSMCI_CFG (0x40000054U) /**< \brief (HSMCI) Configuration Register */ +#define REG_HSMCI_WPMR (0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */ +#define REG_HSMCI_WPSR (0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */ +#define REG_HSMCI_FIFO (0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */ +#else +#define REG_HSMCI_CR (*(WoReg*)0x40000000U) /**< \brief (HSMCI) Control Register */ +#define REG_HSMCI_MR (*(RwReg*)0x40000004U) /**< \brief (HSMCI) Mode Register */ +#define REG_HSMCI_DTOR (*(RwReg*)0x40000008U) /**< \brief (HSMCI) Data Timeout Register */ +#define REG_HSMCI_SDCR (*(RwReg*)0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */ +#define REG_HSMCI_ARGR (*(RwReg*)0x40000010U) /**< \brief (HSMCI) Argument Register */ +#define REG_HSMCI_CMDR (*(WoReg*)0x40000014U) /**< \brief (HSMCI) Command Register */ +#define REG_HSMCI_BLKR (*(RwReg*)0x40000018U) /**< \brief (HSMCI) Block Register */ +#define REG_HSMCI_CSTOR (*(RwReg*)0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */ +#define REG_HSMCI_RSPR (*(RoReg*)0x40000020U) /**< \brief (HSMCI) Response Register */ +#define REG_HSMCI_RDR (*(RoReg*)0x40000030U) /**< \brief (HSMCI) Receive Data Register */ +#define REG_HSMCI_TDR (*(WoReg*)0x40000034U) /**< \brief (HSMCI) Transmit Data Register */ +#define REG_HSMCI_SR (*(RoReg*)0x40000040U) /**< \brief (HSMCI) Status Register */ +#define REG_HSMCI_IER (*(WoReg*)0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */ +#define REG_HSMCI_IDR (*(WoReg*)0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */ +#define REG_HSMCI_IMR (*(RoReg*)0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */ +#define REG_HSMCI_DMA (*(RwReg*)0x40000050U) /**< \brief (HSMCI) DMA Configuration Register */ +#define REG_HSMCI_CFG (*(RwReg*)0x40000054U) /**< \brief (HSMCI) Configuration Register */ +#define REG_HSMCI_WPMR (*(RwReg*)0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */ +#define REG_HSMCI_WPSR (*(RoReg*)0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */ +#define REG_HSMCI_FIFO (*(RwReg*)0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_HSMCI_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h new file mode 100644 index 0000000..c04bf93 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h
@@ -0,0 +1,80 @@ +/** + * \file + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM3XA_MATRIX_INSTANCE_ +#define _SAM3XA_MATRIX_INSTANCE_ + +/* ========== Register definition for MATRIX peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_MATRIX_MCFG (0x400E0400U) /**< \brief (MATRIX) Master Configuration Register */ +#define REG_MATRIX_SCFG (0x400E0440U) /**< \brief (MATRIX) Slave Configuration Register */ +#define REG_MATRIX_PRAS0 (0x400E0480U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ +#define REG_MATRIX_PRAS1 (0x400E0488U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ +#define REG_MATRIX_PRAS2 (0x400E0490U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ +#define REG_MATRIX_PRAS3 (0x400E0498U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ +#define REG_MATRIX_PRAS4 (0x400E04A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */ +#define REG_MATRIX_PRAS5 (0x400E04A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */ +#define REG_MATRIX_PRAS6 (0x400E04B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */ +#define REG_MATRIX_PRAS7 (0x400E04B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */ +#define REG_MATRIX_PRAS8 (0x400E04C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */ +#define REG_MATRIX_MRCR (0x400E0500U) /**< \brief (MATRIX) Master Remap Control Register */ +#define REG_CCFG_SYSIO (0x400E0514U) /**< \brief (MATRIX) System I/O Configuration register */ +#define REG_MATRIX_WPMR (0x400E05E4U) /**< \brief (MATRIX) Write Protect Mode Register */ +#define REG_MATRIX_WPSR (0x400E05E8U) /**< \brief (MATRIX) Write Protect Status Register */ +#else +#define REG_MATRIX_MCFG (*(RwReg*)0x400E0400U) /**< \brief (MATRIX) Master Configuration Register */ +#define REG_MATRIX_SCFG (*(RwReg*)0x400E0440U) /**< \brief (MATRIX) Slave Configuration Register */ +#define REG_MATRIX_PRAS0 (*(RwReg*)0x400E0480U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ +#define REG_MATRIX_PRAS1 (*(RwReg*)0x400E0488U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ +#define REG_MATRIX_PRAS2 (*(RwReg*)0x400E0490U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ +#define REG_MATRIX_PRAS3 (*(RwReg*)0x400E0498U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ +#define REG_MATRIX_PRAS4 (*(RwReg*)0x400E04A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */ +#define REG_MATRIX_PRAS5 (*(RwReg*)0x400E04A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */ +#define REG_MATRIX_PRAS6 (*(RwReg*)0x400E04B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */ +#define REG_MATRIX_PRAS7 (*(RwReg*)0x400E04B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */ +#define REG_MATRIX_PRAS8 (*(RwReg*)0x400E04C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */ +#define REG_MATRIX_MRCR (*(RwReg*)0x400E0500U) /**< \brief (MATRIX) Master Remap Control Register */ +#define REG_CCFG_SYSIO (*(RwReg*)0x400E0514U) /**< \brief (MATRIX) System I/O Configuration register */ +#define REG_MATRIX_WPMR (*(RwReg*)0x400E05E4U) /**< \brief (MATRIX) Write Protect Mode Register */ +#define REG_MATRIX_WPSR (*(RoReg*)0x400E05E8U) /**< \brief (MATRIX) Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_MATRIX_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h new file mode 100644 index 0000000..8b17722 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h
@@ -0,0 +1,136 @@ +/** + * \file + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM3XA_PIOA_INSTANCE_ +#define _SAM3XA_PIOA_INSTANCE_ + +/* ========== Register definition for PIOA peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PIOA_PER (0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */ +#define REG_PIOA_PDR (0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */ +#define REG_PIOA_PSR (0x400E0E08U) /**< \brief (PIOA) PIO Status Register */ +#define REG_PIOA_OER (0x400E0E10U) /**< \brief (PIOA) Output Enable Register */ +#define REG_PIOA_ODR (0x400E0E14U) /**< \brief (PIOA) Output Disable Register */ +#define REG_PIOA_OSR (0x400E0E18U) /**< \brief (PIOA) Output Status Register */ +#define REG_PIOA_IFER (0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */ +#define REG_PIOA_IFDR (0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */ +#define REG_PIOA_IFSR (0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */ +#define REG_PIOA_SODR (0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */ +#define REG_PIOA_CODR (0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */ +#define REG_PIOA_ODSR (0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */ +#define REG_PIOA_PDSR (0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */ +#define REG_PIOA_IER (0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */ +#define REG_PIOA_IDR (0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */ +#define REG_PIOA_IMR (0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */ +#define REG_PIOA_ISR (0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */ +#define REG_PIOA_MDER (0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */ +#define REG_PIOA_MDDR (0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */ +#define REG_PIOA_MDSR (0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */ +#define REG_PIOA_PUDR (0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */ +#define REG_PIOA_PUER (0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */ +#define REG_PIOA_PUSR (0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */ +#define REG_PIOA_ABSR (0x400E0E70U) /**< \brief (PIOA) Peripheral AB Select Register */ +#define REG_PIOA_SCIFSR (0x400E0E80U) /**< \brief (PIOA) System Clock Glitch Input Filter Select Register */ +#define REG_PIOA_DIFSR (0x400E0E84U) /**< \brief (PIOA) Debouncing Input Filter Select Register */ +#define REG_PIOA_IFDGSR (0x400E0E88U) /**< \brief (PIOA) Glitch or Debouncing Input Filter Clock Selection Status Register */ +#define REG_PIOA_SCDR (0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */ +#define REG_PIOA_OWER (0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */ +#define REG_PIOA_OWDR (0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */ +#define REG_PIOA_OWSR (0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */ +#define REG_PIOA_AIMER (0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */ +#define REG_PIOA_AIMDR (0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */ +#define REG_PIOA_AIMMR (0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */ +#define REG_PIOA_ESR (0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */ +#define REG_PIOA_LSR (0x400E0EC4U) /**< \brief (PIOA) Level Select Register */ +#define REG_PIOA_ELSR (0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */ +#define REG_PIOA_FELLSR (0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */ +#define REG_PIOA_REHLSR (0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */ +#define REG_PIOA_FRLHSR (0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */ +#define REG_PIOA_LOCKSR (0x400E0EE0U) /**< \brief (PIOA) Lock Status */ +#define REG_PIOA_WPMR (0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */ +#define REG_PIOA_WPSR (0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */ +#else +#define REG_PIOA_PER (*(WoReg*)0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */ +#define REG_PIOA_PDR (*(WoReg*)0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */ +#define REG_PIOA_PSR (*(RoReg*)0x400E0E08U) /**< \brief (PIOA) PIO Status Register */ +#define REG_PIOA_OER (*(WoReg*)0x400E0E10U) /**< \brief (PIOA) Output Enable Register */ +#define REG_PIOA_ODR (*(WoReg*)0x400E0E14U) /**< \brief (PIOA) Output Disable Register */ +#define REG_PIOA_OSR (*(RoReg*)0x400E0E18U) /**< \brief (PIOA) Output Status Register */ +#define REG_PIOA_IFER (*(WoReg*)0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */ +#define REG_PIOA_IFDR (*(WoReg*)0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */ +#define REG_PIOA_IFSR (*(RoReg*)0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */ +#define REG_PIOA_SODR (*(WoReg*)0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */ +#define REG_PIOA_CODR (*(WoReg*)0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */ +#define REG_PIOA_ODSR (*(RwReg*)0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */ +#define REG_PIOA_PDSR (*(RoReg*)0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */ +#define REG_PIOA_IER (*(WoReg*)0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */ +#define REG_PIOA_IDR (*(WoReg*)0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */ +#define REG_PIOA_IMR (*(RoReg*)0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */ +#define REG_PIOA_ISR (*(RoReg*)0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */ +#define REG_PIOA_MDER (*(WoReg*)0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */ +#define REG_PIOA_MDDR (*(WoReg*)0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */ +#define REG_PIOA_MDSR (*(RoReg*)0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */ +#define REG_PIOA_PUDR (*(WoReg*)0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */ +#define REG_PIOA_PUER (*(WoReg*)0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */ +#define REG_PIOA_PUSR (*(RoReg*)0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */ +#define REG_PIOA_ABSR (*(RwReg*)0x400E0E70U) /**< \brief (PIOA) Peripheral AB Select Register */ +#define REG_PIOA_SCIFSR (*(WoReg*)0x400E0E80U) /**< \brief (PIOA) System Clock Glitch Input Filter Select Register */ +#define REG_PIOA_DIFSR (*(WoReg*)0x400E0E84U) /**< \brief (PIOA) Debouncing Input Filter Select Register */ +#define REG_PIOA_IFDGSR (*(RoReg*)0x400E0E88U) /**< \brief (PIOA) Glitch or Debouncing Input Filter Clock Selection Status Register */ +#define REG_PIOA_SCDR (*(RwReg*)0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */ +#define REG_PIOA_OWER (*(WoReg*)0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */ +#define REG_PIOA_OWDR (*(WoReg*)0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */ +#define REG_PIOA_OWSR (*(RoReg*)0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */ +#define REG_PIOA_AIMER (*(WoReg*)0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */ +#define REG_PIOA_AIMDR (*(WoReg*)0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */ +#define REG_PIOA_AIMMR (*(RoReg*)0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */ +#define REG_PIOA_ESR (*(WoReg*)0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */ +#define REG_PIOA_LSR (*(WoReg*)0x400E0EC4U) /**< \brief (PIOA) Level Select Register */ +#define REG_PIOA_ELSR (*(RoReg*)0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */ +#define REG_PIOA_FELLSR (*(WoReg*)0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */ +#define REG_PIOA_REHLSR (*(WoReg*)0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */ +#define REG_PIOA_FRLHSR (*(RoReg*)0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */ +#define REG_PIOA_LOCKSR (*(RoReg*)0x400E0EE0U) /**< \brief (PIOA) Lock Status */ +#define REG_PIOA_WPMR (*(RwReg*)0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */ +#define REG_PIOA_WPSR (*(RoReg*)0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_PIOA_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_piob.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_piob.h new file mode 100644 index 0000000..dc9b890 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_piob.h
@@ -0,0 +1,136 @@ +/** + * \file + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM3XA_PIOB_INSTANCE_ +#define _SAM3XA_PIOB_INSTANCE_ + +/* ========== Register definition for PIOB peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PIOB_PER (0x400E1000U) /**< \brief (PIOB) PIO Enable Register */ +#define REG_PIOB_PDR (0x400E1004U) /**< \brief (PIOB) PIO Disable Register */ +#define REG_PIOB_PSR (0x400E1008U) /**< \brief (PIOB) PIO Status Register */ +#define REG_PIOB_OER (0x400E1010U) /**< \brief (PIOB) Output Enable Register */ +#define REG_PIOB_ODR (0x400E1014U) /**< \brief (PIOB) Output Disable Register */ +#define REG_PIOB_OSR (0x400E1018U) /**< \brief (PIOB) Output Status Register */ +#define REG_PIOB_IFER (0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */ +#define REG_PIOB_IFDR (0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */ +#define REG_PIOB_IFSR (0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */ +#define REG_PIOB_SODR (0x400E1030U) /**< \brief (PIOB) Set Output Data Register */ +#define REG_PIOB_CODR (0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */ +#define REG_PIOB_ODSR (0x400E1038U) /**< \brief (PIOB) Output Data Status Register */ +#define REG_PIOB_PDSR (0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */ +#define REG_PIOB_IER (0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */ +#define REG_PIOB_IDR (0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */ +#define REG_PIOB_IMR (0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */ +#define REG_PIOB_ISR (0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */ +#define REG_PIOB_MDER (0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */ +#define REG_PIOB_MDDR (0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */ +#define REG_PIOB_MDSR (0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */ +#define REG_PIOB_PUDR (0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */ +#define REG_PIOB_PUER (0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */ +#define REG_PIOB_PUSR (0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */ +#define REG_PIOB_ABSR (0x400E1070U) /**< \brief (PIOB) Peripheral AB Select Register */ +#define REG_PIOB_SCIFSR (0x400E1080U) /**< \brief (PIOB) System Clock Glitch Input Filter Select Register */ +#define REG_PIOB_DIFSR (0x400E1084U) /**< \brief (PIOB) Debouncing Input Filter Select Register */ +#define REG_PIOB_IFDGSR (0x400E1088U) /**< \brief (PIOB) Glitch or Debouncing Input Filter Clock Selection Status Register */ +#define REG_PIOB_SCDR (0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */ +#define REG_PIOB_OWER (0x400E10A0U) /**< \brief (PIOB) Output Write Enable */ +#define REG_PIOB_OWDR (0x400E10A4U) /**< \brief (PIOB) Output Write Disable */ +#define REG_PIOB_OWSR (0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */ +#define REG_PIOB_AIMER (0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */ +#define REG_PIOB_AIMDR (0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */ +#define REG_PIOB_AIMMR (0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */ +#define REG_PIOB_ESR (0x400E10C0U) /**< \brief (PIOB) Edge Select Register */ +#define REG_PIOB_LSR (0x400E10C4U) /**< \brief (PIOB) Level Select Register */ +#define REG_PIOB_ELSR (0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */ +#define REG_PIOB_FELLSR (0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */ +#define REG_PIOB_REHLSR (0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */ +#define REG_PIOB_FRLHSR (0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */ +#define REG_PIOB_LOCKSR (0x400E10E0U) /**< \brief (PIOB) Lock Status */ +#define REG_PIOB_WPMR (0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */ +#define REG_PIOB_WPSR (0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */ +#else +#define REG_PIOB_PER (*(WoReg*)0x400E1000U) /**< \brief (PIOB) PIO Enable Register */ +#define REG_PIOB_PDR (*(WoReg*)0x400E1004U) /**< \brief (PIOB) PIO Disable Register */ +#define REG_PIOB_PSR (*(RoReg*)0x400E1008U) /**< \brief (PIOB) PIO Status Register */ +#define REG_PIOB_OER (*(WoReg*)0x400E1010U) /**< \brief (PIOB) Output Enable Register */ +#define REG_PIOB_ODR (*(WoReg*)0x400E1014U) /**< \brief (PIOB) Output Disable Register */ +#define REG_PIOB_OSR (*(RoReg*)0x400E1018U) /**< \brief (PIOB) Output Status Register */ +#define REG_PIOB_IFER (*(WoReg*)0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */ +#define REG_PIOB_IFDR (*(WoReg*)0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */ +#define REG_PIOB_IFSR (*(RoReg*)0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */ +#define REG_PIOB_SODR (*(WoReg*)0x400E1030U) /**< \brief (PIOB) Set Output Data Register */ +#define REG_PIOB_CODR (*(WoReg*)0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */ +#define REG_PIOB_ODSR (*(RwReg*)0x400E1038U) /**< \brief (PIOB) Output Data Status Register */ +#define REG_PIOB_PDSR (*(RoReg*)0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */ +#define REG_PIOB_IER (*(WoReg*)0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */ +#define REG_PIOB_IDR (*(WoReg*)0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */ +#define REG_PIOB_IMR (*(RoReg*)0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */ +#define REG_PIOB_ISR (*(RoReg*)0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */ +#define REG_PIOB_MDER (*(WoReg*)0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */ +#define REG_PIOB_MDDR (*(WoReg*)0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */ +#define REG_PIOB_MDSR (*(RoReg*)0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */ +#define REG_PIOB_PUDR (*(WoReg*)0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */ +#define REG_PIOB_PUER (*(WoReg*)0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */ +#define REG_PIOB_PUSR (*(RoReg*)0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */ +#define REG_PIOB_ABSR (*(RwReg*)0x400E1070U) /**< \brief (PIOB) Peripheral AB Select Register */ +#define REG_PIOB_SCIFSR (*(WoReg*)0x400E1080U) /**< \brief (PIOB) System Clock Glitch Input Filter Select Register */ +#define REG_PIOB_DIFSR (*(WoReg*)0x400E1084U) /**< \brief (PIOB) Debouncing Input Filter Select Register */ +#define REG_PIOB_IFDGSR (*(RoReg*)0x400E1088U) /**< \brief (PIOB) Glitch or Debouncing Input Filter Clock Selection Status Register */ +#define REG_PIOB_SCDR (*(RwReg*)0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */ +#define REG_PIOB_OWER (*(WoReg*)0x400E10A0U) /**< \brief (PIOB) Output Write Enable */ +#define REG_PIOB_OWDR (*(WoReg*)0x400E10A4U) /**< \brief (PIOB) Output Write Disable */ +#define REG_PIOB_OWSR (*(RoReg*)0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */ +#define REG_PIOB_AIMER (*(WoReg*)0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */ +#define REG_PIOB_AIMDR (*(WoReg*)0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */ +#define REG_PIOB_AIMMR (*(RoReg*)0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */ +#define REG_PIOB_ESR (*(WoReg*)0x400E10C0U) /**< \brief (PIOB) Edge Select Register */ +#define REG_PIOB_LSR (*(WoReg*)0x400E10C4U) /**< \brief (PIOB) Level Select Register */ +#define REG_PIOB_ELSR (*(RoReg*)0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */ +#define REG_PIOB_FELLSR (*(WoReg*)0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */ +#define REG_PIOB_REHLSR (*(WoReg*)0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */ +#define REG_PIOB_FRLHSR (*(RoReg*)0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */ +#define REG_PIOB_LOCKSR (*(RoReg*)0x400E10E0U) /**< \brief (PIOB) Lock Status */ +#define REG_PIOB_WPMR (*(RwReg*)0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */ +#define REG_PIOB_WPSR (*(RoReg*)0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_PIOB_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h new file mode 100644 index 0000000..8959a03 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h
@@ -0,0 +1,136 @@ +/** + * \file + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM3XA_PIOC_INSTANCE_ +#define _SAM3XA_PIOC_INSTANCE_ + +/* ========== Register definition for PIOC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PIOC_PER (0x400E1200U) /**< \brief (PIOC) PIO Enable Register */ +#define REG_PIOC_PDR (0x400E1204U) /**< \brief (PIOC) PIO Disable Register */ +#define REG_PIOC_PSR (0x400E1208U) /**< \brief (PIOC) PIO Status Register */ +#define REG_PIOC_OER (0x400E1210U) /**< \brief (PIOC) Output Enable Register */ +#define REG_PIOC_ODR (0x400E1214U) /**< \brief (PIOC) Output Disable Register */ +#define REG_PIOC_OSR (0x400E1218U) /**< \brief (PIOC) Output Status Register */ +#define REG_PIOC_IFER (0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */ +#define REG_PIOC_IFDR (0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */ +#define REG_PIOC_IFSR (0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */ +#define REG_PIOC_SODR (0x400E1230U) /**< \brief (PIOC) Set Output Data Register */ +#define REG_PIOC_CODR (0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */ +#define REG_PIOC_ODSR (0x400E1238U) /**< \brief (PIOC) Output Data Status Register */ +#define REG_PIOC_PDSR (0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */ +#define REG_PIOC_IER (0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */ +#define REG_PIOC_IDR (0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */ +#define REG_PIOC_IMR (0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */ +#define REG_PIOC_ISR (0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */ +#define REG_PIOC_MDER (0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */ +#define REG_PIOC_MDDR (0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */ +#define REG_PIOC_MDSR (0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */ +#define REG_PIOC_PUDR (0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */ +#define REG_PIOC_PUER (0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */ +#define REG_PIOC_PUSR (0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */ +#define REG_PIOC_ABSR (0x400E1270U) /**< \brief (PIOC) Peripheral AB Select Register */ +#define REG_PIOC_SCIFSR (0x400E1280U) /**< \brief (PIOC) System Clock Glitch Input Filter Select Register */ +#define REG_PIOC_DIFSR (0x400E1284U) /**< \brief (PIOC) Debouncing Input Filter Select Register */ +#define REG_PIOC_IFDGSR (0x400E1288U) /**< \brief (PIOC) Glitch or Debouncing Input Filter Clock Selection Status Register */ +#define REG_PIOC_SCDR (0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */ +#define REG_PIOC_OWER (0x400E12A0U) /**< \brief (PIOC) Output Write Enable */ +#define REG_PIOC_OWDR (0x400E12A4U) /**< \brief (PIOC) Output Write Disable */ +#define REG_PIOC_OWSR (0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */ +#define REG_PIOC_AIMER (0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */ +#define REG_PIOC_AIMDR (0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */ +#define REG_PIOC_AIMMR (0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */ +#define REG_PIOC_ESR (0x400E12C0U) /**< \brief (PIOC) Edge Select Register */ +#define REG_PIOC_LSR (0x400E12C4U) /**< \brief (PIOC) Level Select Register */ +#define REG_PIOC_ELSR (0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */ +#define REG_PIOC_FELLSR (0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */ +#define REG_PIOC_REHLSR (0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */ +#define REG_PIOC_FRLHSR (0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */ +#define REG_PIOC_LOCKSR (0x400E12E0U) /**< \brief (PIOC) Lock Status */ +#define REG_PIOC_WPMR (0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */ +#define REG_PIOC_WPSR (0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */ +#else +#define REG_PIOC_PER (*(WoReg*)0x400E1200U) /**< \brief (PIOC) PIO Enable Register */ +#define REG_PIOC_PDR (*(WoReg*)0x400E1204U) /**< \brief (PIOC) PIO Disable Register */ +#define REG_PIOC_PSR (*(RoReg*)0x400E1208U) /**< \brief (PIOC) PIO Status Register */ +#define REG_PIOC_OER (*(WoReg*)0x400E1210U) /**< \brief (PIOC) Output Enable Register */ +#define REG_PIOC_ODR (*(WoReg*)0x400E1214U) /**< \brief (PIOC) Output Disable Register */ +#define REG_PIOC_OSR (*(RoReg*)0x400E1218U) /**< \brief (PIOC) Output Status Register */ +#define REG_PIOC_IFER (*(WoReg*)0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */ +#define REG_PIOC_IFDR (*(WoReg*)0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */ +#define REG_PIOC_IFSR (*(RoReg*)0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */ +#define REG_PIOC_SODR (*(WoReg*)0x400E1230U) /**< \brief (PIOC) Set Output Data Register */ +#define REG_PIOC_CODR (*(WoReg*)0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */ +#define REG_PIOC_ODSR (*(RwReg*)0x400E1238U) /**< \brief (PIOC) Output Data Status Register */ +#define REG_PIOC_PDSR (*(RoReg*)0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */ +#define REG_PIOC_IER (*(WoReg*)0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */ +#define REG_PIOC_IDR (*(WoReg*)0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */ +#define REG_PIOC_IMR (*(RoReg*)0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */ +#define REG_PIOC_ISR (*(RoReg*)0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */ +#define REG_PIOC_MDER (*(WoReg*)0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */ +#define REG_PIOC_MDDR (*(WoReg*)0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */ +#define REG_PIOC_MDSR (*(RoReg*)0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */ +#define REG_PIOC_PUDR (*(WoReg*)0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */ +#define REG_PIOC_PUER (*(WoReg*)0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */ +#define REG_PIOC_PUSR (*(RoReg*)0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */ +#define REG_PIOC_ABSR (*(RwReg*)0x400E1270U) /**< \brief (PIOC) Peripheral AB Select Register */ +#define REG_PIOC_SCIFSR (*(WoReg*)0x400E1280U) /**< \brief (PIOC) System Clock Glitch Input Filter Select Register */ +#define REG_PIOC_DIFSR (*(WoReg*)0x400E1284U) /**< \brief (PIOC) Debouncing Input Filter Select Register */ +#define REG_PIOC_IFDGSR (*(RoReg*)0x400E1288U) /**< \brief (PIOC) Glitch or Debouncing Input Filter Clock Selection Status Register */ +#define REG_PIOC_SCDR (*(RwReg*)0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */ +#define REG_PIOC_OWER (*(WoReg*)0x400E12A0U) /**< \brief (PIOC) Output Write Enable */ +#define REG_PIOC_OWDR (*(WoReg*)0x400E12A4U) /**< \brief (PIOC) Output Write Disable */ +#define REG_PIOC_OWSR (*(RoReg*)0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */ +#define REG_PIOC_AIMER (*(WoReg*)0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */ +#define REG_PIOC_AIMDR (*(WoReg*)0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */ +#define REG_PIOC_AIMMR (*(RoReg*)0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */ +#define REG_PIOC_ESR (*(WoReg*)0x400E12C0U) /**< \brief (PIOC) Edge Select Register */ +#define REG_PIOC_LSR (*(WoReg*)0x400E12C4U) /**< \brief (PIOC) Level Select Register */ +#define REG_PIOC_ELSR (*(RoReg*)0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */ +#define REG_PIOC_FELLSR (*(WoReg*)0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */ +#define REG_PIOC_REHLSR (*(WoReg*)0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */ +#define REG_PIOC_FRLHSR (*(RoReg*)0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */ +#define REG_PIOC_LOCKSR (*(RoReg*)0x400E12E0U) /**< \brief (PIOC) Lock Status */ +#define REG_PIOC_WPMR (*(RwReg*)0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */ +#define REG_PIOC_WPSR (*(RoReg*)0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_PIOC_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_piod.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_piod.h new file mode 100644 index 0000000..927c308 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_piod.h
@@ -0,0 +1,136 @@ +/** + * \file + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM3XA_PIOD_INSTANCE_ +#define _SAM3XA_PIOD_INSTANCE_ + +/* ========== Register definition for PIOD peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PIOD_PER (0x400E1400U) /**< \brief (PIOD) PIO Enable Register */ +#define REG_PIOD_PDR (0x400E1404U) /**< \brief (PIOD) PIO Disable Register */ +#define REG_PIOD_PSR (0x400E1408U) /**< \brief (PIOD) PIO Status Register */ +#define REG_PIOD_OER (0x400E1410U) /**< \brief (PIOD) Output Enable Register */ +#define REG_PIOD_ODR (0x400E1414U) /**< \brief (PIOD) Output Disable Register */ +#define REG_PIOD_OSR (0x400E1418U) /**< \brief (PIOD) Output Status Register */ +#define REG_PIOD_IFER (0x400E1420U) /**< \brief (PIOD) Glitch Input Filter Enable Register */ +#define REG_PIOD_IFDR (0x400E1424U) /**< \brief (PIOD) Glitch Input Filter Disable Register */ +#define REG_PIOD_IFSR (0x400E1428U) /**< \brief (PIOD) Glitch Input Filter Status Register */ +#define REG_PIOD_SODR (0x400E1430U) /**< \brief (PIOD) Set Output Data Register */ +#define REG_PIOD_CODR (0x400E1434U) /**< \brief (PIOD) Clear Output Data Register */ +#define REG_PIOD_ODSR (0x400E1438U) /**< \brief (PIOD) Output Data Status Register */ +#define REG_PIOD_PDSR (0x400E143CU) /**< \brief (PIOD) Pin Data Status Register */ +#define REG_PIOD_IER (0x400E1440U) /**< \brief (PIOD) Interrupt Enable Register */ +#define REG_PIOD_IDR (0x400E1444U) /**< \brief (PIOD) Interrupt Disable Register */ +#define REG_PIOD_IMR (0x400E1448U) /**< \brief (PIOD) Interrupt Mask Register */ +#define REG_PIOD_ISR (0x400E144CU) /**< \brief (PIOD) Interrupt Status Register */ +#define REG_PIOD_MDER (0x400E1450U) /**< \brief (PIOD) Multi-driver Enable Register */ +#define REG_PIOD_MDDR (0x400E1454U) /**< \brief (PIOD) Multi-driver Disable Register */ +#define REG_PIOD_MDSR (0x400E1458U) /**< \brief (PIOD) Multi-driver Status Register */ +#define REG_PIOD_PUDR (0x400E1460U) /**< \brief (PIOD) Pull-up Disable Register */ +#define REG_PIOD_PUER (0x400E1464U) /**< \brief (PIOD) Pull-up Enable Register */ +#define REG_PIOD_PUSR (0x400E1468U) /**< \brief (PIOD) Pad Pull-up Status Register */ +#define REG_PIOD_ABSR (0x400E1470U) /**< \brief (PIOD) Peripheral AB Select Register */ +#define REG_PIOD_SCIFSR (0x400E1480U) /**< \brief (PIOD) System Clock Glitch Input Filter Select Register */ +#define REG_PIOD_DIFSR (0x400E1484U) /**< \brief (PIOD) Debouncing Input Filter Select Register */ +#define REG_PIOD_IFDGSR (0x400E1488U) /**< \brief (PIOD) Glitch or Debouncing Input Filter Clock Selection Status Register */ +#define REG_PIOD_SCDR (0x400E148CU) /**< \brief (PIOD) Slow Clock Divider Debouncing Register */ +#define REG_PIOD_OWER (0x400E14A0U) /**< \brief (PIOD) Output Write Enable */ +#define REG_PIOD_OWDR (0x400E14A4U) /**< \brief (PIOD) Output Write Disable */ +#define REG_PIOD_OWSR (0x400E14A8U) /**< \brief (PIOD) Output Write Status Register */ +#define REG_PIOD_AIMER (0x400E14B0U) /**< \brief (PIOD) Additional Interrupt Modes Enable Register */ +#define REG_PIOD_AIMDR (0x400E14B4U) /**< \brief (PIOD) Additional Interrupt Modes Disables Register */ +#define REG_PIOD_AIMMR (0x400E14B8U) /**< \brief (PIOD) Additional Interrupt Modes Mask Register */ +#define REG_PIOD_ESR (0x400E14C0U) /**< \brief (PIOD) Edge Select Register */ +#define REG_PIOD_LSR (0x400E14C4U) /**< \brief (PIOD) Level Select Register */ +#define REG_PIOD_ELSR (0x400E14C8U) /**< \brief (PIOD) Edge/Level Status Register */ +#define REG_PIOD_FELLSR (0x400E14D0U) /**< \brief (PIOD) Falling Edge/Low Level Select Register */ +#define REG_PIOD_REHLSR (0x400E14D4U) /**< \brief (PIOD) Rising Edge/ High Level Select Register */ +#define REG_PIOD_FRLHSR (0x400E14D8U) /**< \brief (PIOD) Fall/Rise - Low/High Status Register */ +#define REG_PIOD_LOCKSR (0x400E14E0U) /**< \brief (PIOD) Lock Status */ +#define REG_PIOD_WPMR (0x400E14E4U) /**< \brief (PIOD) Write Protect Mode Register */ +#define REG_PIOD_WPSR (0x400E14E8U) /**< \brief (PIOD) Write Protect Status Register */ +#else +#define REG_PIOD_PER (*(WoReg*)0x400E1400U) /**< \brief (PIOD) PIO Enable Register */ +#define REG_PIOD_PDR (*(WoReg*)0x400E1404U) /**< \brief (PIOD) PIO Disable Register */ +#define REG_PIOD_PSR (*(RoReg*)0x400E1408U) /**< \brief (PIOD) PIO Status Register */ +#define REG_PIOD_OER (*(WoReg*)0x400E1410U) /**< \brief (PIOD) Output Enable Register */ +#define REG_PIOD_ODR (*(WoReg*)0x400E1414U) /**< \brief (PIOD) Output Disable Register */ +#define REG_PIOD_OSR (*(RoReg*)0x400E1418U) /**< \brief (PIOD) Output Status Register */ +#define REG_PIOD_IFER (*(WoReg*)0x400E1420U) /**< \brief (PIOD) Glitch Input Filter Enable Register */ +#define REG_PIOD_IFDR (*(WoReg*)0x400E1424U) /**< \brief (PIOD) Glitch Input Filter Disable Register */ +#define REG_PIOD_IFSR (*(RoReg*)0x400E1428U) /**< \brief (PIOD) Glitch Input Filter Status Register */ +#define REG_PIOD_SODR (*(WoReg*)0x400E1430U) /**< \brief (PIOD) Set Output Data Register */ +#define REG_PIOD_CODR (*(WoReg*)0x400E1434U) /**< \brief (PIOD) Clear Output Data Register */ +#define REG_PIOD_ODSR (*(RwReg*)0x400E1438U) /**< \brief (PIOD) Output Data Status Register */ +#define REG_PIOD_PDSR (*(RoReg*)0x400E143CU) /**< \brief (PIOD) Pin Data Status Register */ +#define REG_PIOD_IER (*(WoReg*)0x400E1440U) /**< \brief (PIOD) Interrupt Enable Register */ +#define REG_PIOD_IDR (*(WoReg*)0x400E1444U) /**< \brief (PIOD) Interrupt Disable Register */ +#define REG_PIOD_IMR (*(RoReg*)0x400E1448U) /**< \brief (PIOD) Interrupt Mask Register */ +#define REG_PIOD_ISR (*(RoReg*)0x400E144CU) /**< \brief (PIOD) Interrupt Status Register */ +#define REG_PIOD_MDER (*(WoReg*)0x400E1450U) /**< \brief (PIOD) Multi-driver Enable Register */ +#define REG_PIOD_MDDR (*(WoReg*)0x400E1454U) /**< \brief (PIOD) Multi-driver Disable Register */ +#define REG_PIOD_MDSR (*(RoReg*)0x400E1458U) /**< \brief (PIOD) Multi-driver Status Register */ +#define REG_PIOD_PUDR (*(WoReg*)0x400E1460U) /**< \brief (PIOD) Pull-up Disable Register */ +#define REG_PIOD_PUER (*(WoReg*)0x400E1464U) /**< \brief (PIOD) Pull-up Enable Register */ +#define REG_PIOD_PUSR (*(RoReg*)0x400E1468U) /**< \brief (PIOD) Pad Pull-up Status Register */ +#define REG_PIOD_ABSR (*(RwReg*)0x400E1470U) /**< \brief (PIOD) Peripheral AB Select Register */ +#define REG_PIOD_SCIFSR (*(WoReg*)0x400E1480U) /**< \brief (PIOD) System Clock Glitch Input Filter Select Register */ +#define REG_PIOD_DIFSR (*(WoReg*)0x400E1484U) /**< \brief (PIOD) Debouncing Input Filter Select Register */ +#define REG_PIOD_IFDGSR (*(RoReg*)0x400E1488U) /**< \brief (PIOD) Glitch or Debouncing Input Filter Clock Selection Status Register */ +#define REG_PIOD_SCDR (*(RwReg*)0x400E148CU) /**< \brief (PIOD) Slow Clock Divider Debouncing Register */ +#define REG_PIOD_OWER (*(WoReg*)0x400E14A0U) /**< \brief (PIOD) Output Write Enable */ +#define REG_PIOD_OWDR (*(WoReg*)0x400E14A4U) /**< \brief (PIOD) Output Write Disable */ +#define REG_PIOD_OWSR (*(RoReg*)0x400E14A8U) /**< \brief (PIOD) Output Write Status Register */ +#define REG_PIOD_AIMER (*(WoReg*)0x400E14B0U) /**< \brief (PIOD) Additional Interrupt Modes Enable Register */ +#define REG_PIOD_AIMDR (*(WoReg*)0x400E14B4U) /**< \brief (PIOD) Additional Interrupt Modes Disables Register */ +#define REG_PIOD_AIMMR (*(RoReg*)0x400E14B8U) /**< \brief (PIOD) Additional Interrupt Modes Mask Register */ +#define REG_PIOD_ESR (*(WoReg*)0x400E14C0U) /**< \brief (PIOD) Edge Select Register */ +#define REG_PIOD_LSR (*(WoReg*)0x400E14C4U) /**< \brief (PIOD) Level Select Register */ +#define REG_PIOD_ELSR (*(RoReg*)0x400E14C8U) /**< \brief (PIOD) Edge/Level Status Register */ +#define REG_PIOD_FELLSR (*(WoReg*)0x400E14D0U) /**< \brief (PIOD) Falling Edge/Low Level Select Register */ +#define REG_PIOD_REHLSR (*(WoReg*)0x400E14D4U) /**< \brief (PIOD) Rising Edge/ High Level Select Register */ +#define REG_PIOD_FRLHSR (*(RoReg*)0x400E14D8U) /**< \brief (PIOD) Fall/Rise - Low/High Status Register */ +#define REG_PIOD_LOCKSR (*(RoReg*)0x400E14E0U) /**< \brief (PIOD) Lock Status */ +#define REG_PIOD_WPMR (*(RwReg*)0x400E14E4U) /**< \brief (PIOD) Write Protect Mode Register */ +#define REG_PIOD_WPSR (*(RoReg*)0x400E14E8U) /**< \brief (PIOD) Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_PIOD_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_pioe.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_pioe.h new file mode 100644 index 0000000..2e8979b --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_pioe.h
@@ -0,0 +1,136 @@ +/** + * \file + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM3XA_PIOE_INSTANCE_ +#define _SAM3XA_PIOE_INSTANCE_ + +/* ========== Register definition for PIOE peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PIOE_PER (0x400E1600U) /**< \brief (PIOE) PIO Enable Register */ +#define REG_PIOE_PDR (0x400E1604U) /**< \brief (PIOE) PIO Disable Register */ +#define REG_PIOE_PSR (0x400E1608U) /**< \brief (PIOE) PIO Status Register */ +#define REG_PIOE_OER (0x400E1610U) /**< \brief (PIOE) Output Enable Register */ +#define REG_PIOE_ODR (0x400E1614U) /**< \brief (PIOE) Output Disable Register */ +#define REG_PIOE_OSR (0x400E1618U) /**< \brief (PIOE) Output Status Register */ +#define REG_PIOE_IFER (0x400E1620U) /**< \brief (PIOE) Glitch Input Filter Enable Register */ +#define REG_PIOE_IFDR (0x400E1624U) /**< \brief (PIOE) Glitch Input Filter Disable Register */ +#define REG_PIOE_IFSR (0x400E1628U) /**< \brief (PIOE) Glitch Input Filter Status Register */ +#define REG_PIOE_SODR (0x400E1630U) /**< \brief (PIOE) Set Output Data Register */ +#define REG_PIOE_CODR (0x400E1634U) /**< \brief (PIOE) Clear Output Data Register */ +#define REG_PIOE_ODSR (0x400E1638U) /**< \brief (PIOE) Output Data Status Register */ +#define REG_PIOE_PDSR (0x400E163CU) /**< \brief (PIOE) Pin Data Status Register */ +#define REG_PIOE_IER (0x400E1640U) /**< \brief (PIOE) Interrupt Enable Register */ +#define REG_PIOE_IDR (0x400E1644U) /**< \brief (PIOE) Interrupt Disable Register */ +#define REG_PIOE_IMR (0x400E1648U) /**< \brief (PIOE) Interrupt Mask Register */ +#define REG_PIOE_ISR (0x400E164CU) /**< \brief (PIOE) Interrupt Status Register */ +#define REG_PIOE_MDER (0x400E1650U) /**< \brief (PIOE) Multi-driver Enable Register */ +#define REG_PIOE_MDDR (0x400E1654U) /**< \brief (PIOE) Multi-driver Disable Register */ +#define REG_PIOE_MDSR (0x400E1658U) /**< \brief (PIOE) Multi-driver Status Register */ +#define REG_PIOE_PUDR (0x400E1660U) /**< \brief (PIOE) Pull-up Disable Register */ +#define REG_PIOE_PUER (0x400E1664U) /**< \brief (PIOE) Pull-up Enable Register */ +#define REG_PIOE_PUSR (0x400E1668U) /**< \brief (PIOE) Pad Pull-up Status Register */ +#define REG_PIOE_ABSR (0x400E1670U) /**< \brief (PIOE) Peripheral AB Select Register */ +#define REG_PIOE_SCIFSR (0x400E1680U) /**< \brief (PIOE) System Clock Glitch Input Filter Select Register */ +#define REG_PIOE_DIFSR (0x400E1684U) /**< \brief (PIOE) Debouncing Input Filter Select Register */ +#define REG_PIOE_IFDGSR (0x400E1688U) /**< \brief (PIOE) Glitch or Debouncing Input Filter Clock Selection Status Register */ +#define REG_PIOE_SCDR (0x400E168CU) /**< \brief (PIOE) Slow Clock Divider Debouncing Register */ +#define REG_PIOE_OWER (0x400E16A0U) /**< \brief (PIOE) Output Write Enable */ +#define REG_PIOE_OWDR (0x400E16A4U) /**< \brief (PIOE) Output Write Disable */ +#define REG_PIOE_OWSR (0x400E16A8U) /**< \brief (PIOE) Output Write Status Register */ +#define REG_PIOE_AIMER (0x400E16B0U) /**< \brief (PIOE) Additional Interrupt Modes Enable Register */ +#define REG_PIOE_AIMDR (0x400E16B4U) /**< \brief (PIOE) Additional Interrupt Modes Disables Register */ +#define REG_PIOE_AIMMR (0x400E16B8U) /**< \brief (PIOE) Additional Interrupt Modes Mask Register */ +#define REG_PIOE_ESR (0x400E16C0U) /**< \brief (PIOE) Edge Select Register */ +#define REG_PIOE_LSR (0x400E16C4U) /**< \brief (PIOE) Level Select Register */ +#define REG_PIOE_ELSR (0x400E16C8U) /**< \brief (PIOE) Edge/Level Status Register */ +#define REG_PIOE_FELLSR (0x400E16D0U) /**< \brief (PIOE) Falling Edge/Low Level Select Register */ +#define REG_PIOE_REHLSR (0x400E16D4U) /**< \brief (PIOE) Rising Edge/ High Level Select Register */ +#define REG_PIOE_FRLHSR (0x400E16D8U) /**< \brief (PIOE) Fall/Rise - Low/High Status Register */ +#define REG_PIOE_LOCKSR (0x400E16E0U) /**< \brief (PIOE) Lock Status */ +#define REG_PIOE_WPMR (0x400E16E4U) /**< \brief (PIOE) Write Protect Mode Register */ +#define REG_PIOE_WPSR (0x400E16E8U) /**< \brief (PIOE) Write Protect Status Register */ +#else +#define REG_PIOE_PER (*(WoReg*)0x400E1600U) /**< \brief (PIOE) PIO Enable Register */ +#define REG_PIOE_PDR (*(WoReg*)0x400E1604U) /**< \brief (PIOE) PIO Disable Register */ +#define REG_PIOE_PSR (*(RoReg*)0x400E1608U) /**< \brief (PIOE) PIO Status Register */ +#define REG_PIOE_OER (*(WoReg*)0x400E1610U) /**< \brief (PIOE) Output Enable Register */ +#define REG_PIOE_ODR (*(WoReg*)0x400E1614U) /**< \brief (PIOE) Output Disable Register */ +#define REG_PIOE_OSR (*(RoReg*)0x400E1618U) /**< \brief (PIOE) Output Status Register */ +#define REG_PIOE_IFER (*(WoReg*)0x400E1620U) /**< \brief (PIOE) Glitch Input Filter Enable Register */ +#define REG_PIOE_IFDR (*(WoReg*)0x400E1624U) /**< \brief (PIOE) Glitch Input Filter Disable Register */ +#define REG_PIOE_IFSR (*(RoReg*)0x400E1628U) /**< \brief (PIOE) Glitch Input Filter Status Register */ +#define REG_PIOE_SODR (*(WoReg*)0x400E1630U) /**< \brief (PIOE) Set Output Data Register */ +#define REG_PIOE_CODR (*(WoReg*)0x400E1634U) /**< \brief (PIOE) Clear Output Data Register */ +#define REG_PIOE_ODSR (*(RwReg*)0x400E1638U) /**< \brief (PIOE) Output Data Status Register */ +#define REG_PIOE_PDSR (*(RoReg*)0x400E163CU) /**< \brief (PIOE) Pin Data Status Register */ +#define REG_PIOE_IER (*(WoReg*)0x400E1640U) /**< \brief (PIOE) Interrupt Enable Register */ +#define REG_PIOE_IDR (*(WoReg*)0x400E1644U) /**< \brief (PIOE) Interrupt Disable Register */ +#define REG_PIOE_IMR (*(RoReg*)0x400E1648U) /**< \brief (PIOE) Interrupt Mask Register */ +#define REG_PIOE_ISR (*(RoReg*)0x400E164CU) /**< \brief (PIOE) Interrupt Status Register */ +#define REG_PIOE_MDER (*(WoReg*)0x400E1650U) /**< \brief (PIOE) Multi-driver Enable Register */ +#define REG_PIOE_MDDR (*(WoReg*)0x400E1654U) /**< \brief (PIOE) Multi-driver Disable Register */ +#define REG_PIOE_MDSR (*(RoReg*)0x400E1658U) /**< \brief (PIOE) Multi-driver Status Register */ +#define REG_PIOE_PUDR (*(WoReg*)0x400E1660U) /**< \brief (PIOE) Pull-up Disable Register */ +#define REG_PIOE_PUER (*(WoReg*)0x400E1664U) /**< \brief (PIOE) Pull-up Enable Register */ +#define REG_PIOE_PUSR (*(RoReg*)0x400E1668U) /**< \brief (PIOE) Pad Pull-up Status Register */ +#define REG_PIOE_ABSR (*(RwReg*)0x400E1670U) /**< \brief (PIOE) Peripheral AB Select Register */ +#define REG_PIOE_SCIFSR (*(WoReg*)0x400E1680U) /**< \brief (PIOE) System Clock Glitch Input Filter Select Register */ +#define REG_PIOE_DIFSR (*(WoReg*)0x400E1684U) /**< \brief (PIOE) Debouncing Input Filter Select Register */ +#define REG_PIOE_IFDGSR (*(RoReg*)0x400E1688U) /**< \brief (PIOE) Glitch or Debouncing Input Filter Clock Selection Status Register */ +#define REG_PIOE_SCDR (*(RwReg*)0x400E168CU) /**< \brief (PIOE) Slow Clock Divider Debouncing Register */ +#define REG_PIOE_OWER (*(WoReg*)0x400E16A0U) /**< \brief (PIOE) Output Write Enable */ +#define REG_PIOE_OWDR (*(WoReg*)0x400E16A4U) /**< \brief (PIOE) Output Write Disable */ +#define REG_PIOE_OWSR (*(RoReg*)0x400E16A8U) /**< \brief (PIOE) Output Write Status Register */ +#define REG_PIOE_AIMER (*(WoReg*)0x400E16B0U) /**< \brief (PIOE) Additional Interrupt Modes Enable Register */ +#define REG_PIOE_AIMDR (*(WoReg*)0x400E16B4U) /**< \brief (PIOE) Additional Interrupt Modes Disables Register */ +#define REG_PIOE_AIMMR (*(RoReg*)0x400E16B8U) /**< \brief (PIOE) Additional Interrupt Modes Mask Register */ +#define REG_PIOE_ESR (*(WoReg*)0x400E16C0U) /**< \brief (PIOE) Edge Select Register */ +#define REG_PIOE_LSR (*(WoReg*)0x400E16C4U) /**< \brief (PIOE) Level Select Register */ +#define REG_PIOE_ELSR (*(RoReg*)0x400E16C8U) /**< \brief (PIOE) Edge/Level Status Register */ +#define REG_PIOE_FELLSR (*(WoReg*)0x400E16D0U) /**< \brief (PIOE) Falling Edge/Low Level Select Register */ +#define REG_PIOE_REHLSR (*(WoReg*)0x400E16D4U) /**< \brief (PIOE) Rising Edge/ High Level Select Register */ +#define REG_PIOE_FRLHSR (*(RoReg*)0x400E16D8U) /**< \brief (PIOE) Fall/Rise - Low/High Status Register */ +#define REG_PIOE_LOCKSR (*(RoReg*)0x400E16E0U) /**< \brief (PIOE) Lock Status */ +#define REG_PIOE_WPMR (*(RwReg*)0x400E16E4U) /**< \brief (PIOE) Write Protect Mode Register */ +#define REG_PIOE_WPSR (*(RoReg*)0x400E16E8U) /**< \brief (PIOE) Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_PIOE_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_piof.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_piof.h new file mode 100644 index 0000000..af4a35d --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_piof.h
@@ -0,0 +1,136 @@ +/** + * \file + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM3XA_PIOF_INSTANCE_ +#define _SAM3XA_PIOF_INSTANCE_ + +/* ========== Register definition for PIOF peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PIOF_PER (0x400E1800U) /**< \brief (PIOF) PIO Enable Register */ +#define REG_PIOF_PDR (0x400E1804U) /**< \brief (PIOF) PIO Disable Register */ +#define REG_PIOF_PSR (0x400E1808U) /**< \brief (PIOF) PIO Status Register */ +#define REG_PIOF_OER (0x400E1810U) /**< \brief (PIOF) Output Enable Register */ +#define REG_PIOF_ODR (0x400E1814U) /**< \brief (PIOF) Output Disable Register */ +#define REG_PIOF_OSR (0x400E1818U) /**< \brief (PIOF) Output Status Register */ +#define REG_PIOF_IFER (0x400E1820U) /**< \brief (PIOF) Glitch Input Filter Enable Register */ +#define REG_PIOF_IFDR (0x400E1824U) /**< \brief (PIOF) Glitch Input Filter Disable Register */ +#define REG_PIOF_IFSR (0x400E1828U) /**< \brief (PIOF) Glitch Input Filter Status Register */ +#define REG_PIOF_SODR (0x400E1830U) /**< \brief (PIOF) Set Output Data Register */ +#define REG_PIOF_CODR (0x400E1834U) /**< \brief (PIOF) Clear Output Data Register */ +#define REG_PIOF_ODSR (0x400E1838U) /**< \brief (PIOF) Output Data Status Register */ +#define REG_PIOF_PDSR (0x400E183CU) /**< \brief (PIOF) Pin Data Status Register */ +#define REG_PIOF_IER (0x400E1840U) /**< \brief (PIOF) Interrupt Enable Register */ +#define REG_PIOF_IDR (0x400E1844U) /**< \brief (PIOF) Interrupt Disable Register */ +#define REG_PIOF_IMR (0x400E1848U) /**< \brief (PIOF) Interrupt Mask Register */ +#define REG_PIOF_ISR (0x400E184CU) /**< \brief (PIOF) Interrupt Status Register */ +#define REG_PIOF_MDER (0x400E1850U) /**< \brief (PIOF) Multi-driver Enable Register */ +#define REG_PIOF_MDDR (0x400E1854U) /**< \brief (PIOF) Multi-driver Disable Register */ +#define REG_PIOF_MDSR (0x400E1858U) /**< \brief (PIOF) Multi-driver Status Register */ +#define REG_PIOF_PUDR (0x400E1860U) /**< \brief (PIOF) Pull-up Disable Register */ +#define REG_PIOF_PUER (0x400E1864U) /**< \brief (PIOF) Pull-up Enable Register */ +#define REG_PIOF_PUSR (0x400E1868U) /**< \brief (PIOF) Pad Pull-up Status Register */ +#define REG_PIOF_ABSR (0x400E1870U) /**< \brief (PIOF) Peripheral AB Select Register */ +#define REG_PIOF_SCIFSR (0x400E1880U) /**< \brief (PIOF) System Clock Glitch Input Filter Select Register */ +#define REG_PIOF_DIFSR (0x400E1884U) /**< \brief (PIOF) Debouncing Input Filter Select Register */ +#define REG_PIOF_IFDGSR (0x400E1888U) /**< \brief (PIOF) Glitch or Debouncing Input Filter Clock Selection Status Register */ +#define REG_PIOF_SCDR (0x400E188CU) /**< \brief (PIOF) Slow Clock Divider Debouncing Register */ +#define REG_PIOF_OWER (0x400E18A0U) /**< \brief (PIOF) Output Write Enable */ +#define REG_PIOF_OWDR (0x400E18A4U) /**< \brief (PIOF) Output Write Disable */ +#define REG_PIOF_OWSR (0x400E18A8U) /**< \brief (PIOF) Output Write Status Register */ +#define REG_PIOF_AIMER (0x400E18B0U) /**< \brief (PIOF) Additional Interrupt Modes Enable Register */ +#define REG_PIOF_AIMDR (0x400E18B4U) /**< \brief (PIOF) Additional Interrupt Modes Disables Register */ +#define REG_PIOF_AIMMR (0x400E18B8U) /**< \brief (PIOF) Additional Interrupt Modes Mask Register */ +#define REG_PIOF_ESR (0x400E18C0U) /**< \brief (PIOF) Edge Select Register */ +#define REG_PIOF_LSR (0x400E18C4U) /**< \brief (PIOF) Level Select Register */ +#define REG_PIOF_ELSR (0x400E18C8U) /**< \brief (PIOF) Edge/Level Status Register */ +#define REG_PIOF_FELLSR (0x400E18D0U) /**< \brief (PIOF) Falling Edge/Low Level Select Register */ +#define REG_PIOF_REHLSR (0x400E18D4U) /**< \brief (PIOF) Rising Edge/ High Level Select Register */ +#define REG_PIOF_FRLHSR (0x400E18D8U) /**< \brief (PIOF) Fall/Rise - Low/High Status Register */ +#define REG_PIOF_LOCKSR (0x400E18E0U) /**< \brief (PIOF) Lock Status */ +#define REG_PIOF_WPMR (0x400E18E4U) /**< \brief (PIOF) Write Protect Mode Register */ +#define REG_PIOF_WPSR (0x400E18E8U) /**< \brief (PIOF) Write Protect Status Register */ +#else +#define REG_PIOF_PER (*(WoReg*)0x400E1800U) /**< \brief (PIOF) PIO Enable Register */ +#define REG_PIOF_PDR (*(WoReg*)0x400E1804U) /**< \brief (PIOF) PIO Disable Register */ +#define REG_PIOF_PSR (*(RoReg*)0x400E1808U) /**< \brief (PIOF) PIO Status Register */ +#define REG_PIOF_OER (*(WoReg*)0x400E1810U) /**< \brief (PIOF) Output Enable Register */ +#define REG_PIOF_ODR (*(WoReg*)0x400E1814U) /**< \brief (PIOF) Output Disable Register */ +#define REG_PIOF_OSR (*(RoReg*)0x400E1818U) /**< \brief (PIOF) Output Status Register */ +#define REG_PIOF_IFER (*(WoReg*)0x400E1820U) /**< \brief (PIOF) Glitch Input Filter Enable Register */ +#define REG_PIOF_IFDR (*(WoReg*)0x400E1824U) /**< \brief (PIOF) Glitch Input Filter Disable Register */ +#define REG_PIOF_IFSR (*(RoReg*)0x400E1828U) /**< \brief (PIOF) Glitch Input Filter Status Register */ +#define REG_PIOF_SODR (*(WoReg*)0x400E1830U) /**< \brief (PIOF) Set Output Data Register */ +#define REG_PIOF_CODR (*(WoReg*)0x400E1834U) /**< \brief (PIOF) Clear Output Data Register */ +#define REG_PIOF_ODSR (*(RwReg*)0x400E1838U) /**< \brief (PIOF) Output Data Status Register */ +#define REG_PIOF_PDSR (*(RoReg*)0x400E183CU) /**< \brief (PIOF) Pin Data Status Register */ +#define REG_PIOF_IER (*(WoReg*)0x400E1840U) /**< \brief (PIOF) Interrupt Enable Register */ +#define REG_PIOF_IDR (*(WoReg*)0x400E1844U) /**< \brief (PIOF) Interrupt Disable Register */ +#define REG_PIOF_IMR (*(RoReg*)0x400E1848U) /**< \brief (PIOF) Interrupt Mask Register */ +#define REG_PIOF_ISR (*(RoReg*)0x400E184CU) /**< \brief (PIOF) Interrupt Status Register */ +#define REG_PIOF_MDER (*(WoReg*)0x400E1850U) /**< \brief (PIOF) Multi-driver Enable Register */ +#define REG_PIOF_MDDR (*(WoReg*)0x400E1854U) /**< \brief (PIOF) Multi-driver Disable Register */ +#define REG_PIOF_MDSR (*(RoReg*)0x400E1858U) /**< \brief (PIOF) Multi-driver Status Register */ +#define REG_PIOF_PUDR (*(WoReg*)0x400E1860U) /**< \brief (PIOF) Pull-up Disable Register */ +#define REG_PIOF_PUER (*(WoReg*)0x400E1864U) /**< \brief (PIOF) Pull-up Enable Register */ +#define REG_PIOF_PUSR (*(RoReg*)0x400E1868U) /**< \brief (PIOF) Pad Pull-up Status Register */ +#define REG_PIOF_ABSR (*(RwReg*)0x400E1870U) /**< \brief (PIOF) Peripheral AB Select Register */ +#define REG_PIOF_SCIFSR (*(WoReg*)0x400E1880U) /**< \brief (PIOF) System Clock Glitch Input Filter Select Register */ +#define REG_PIOF_DIFSR (*(WoReg*)0x400E1884U) /**< \brief (PIOF) Debouncing Input Filter Select Register */ +#define REG_PIOF_IFDGSR (*(RoReg*)0x400E1888U) /**< \brief (PIOF) Glitch or Debouncing Input Filter Clock Selection Status Register */ +#define REG_PIOF_SCDR (*(RwReg*)0x400E188CU) /**< \brief (PIOF) Slow Clock Divider Debouncing Register */ +#define REG_PIOF_OWER (*(WoReg*)0x400E18A0U) /**< \brief (PIOF) Output Write Enable */ +#define REG_PIOF_OWDR (*(WoReg*)0x400E18A4U) /**< \brief (PIOF) Output Write Disable */ +#define REG_PIOF_OWSR (*(RoReg*)0x400E18A8U) /**< \brief (PIOF) Output Write Status Register */ +#define REG_PIOF_AIMER (*(WoReg*)0x400E18B0U) /**< \brief (PIOF) Additional Interrupt Modes Enable Register */ +#define REG_PIOF_AIMDR (*(WoReg*)0x400E18B4U) /**< \brief (PIOF) Additional Interrupt Modes Disables Register */ +#define REG_PIOF_AIMMR (*(RoReg*)0x400E18B8U) /**< \brief (PIOF) Additional Interrupt Modes Mask Register */ +#define REG_PIOF_ESR (*(WoReg*)0x400E18C0U) /**< \brief (PIOF) Edge Select Register */ +#define REG_PIOF_LSR (*(WoReg*)0x400E18C4U) /**< \brief (PIOF) Level Select Register */ +#define REG_PIOF_ELSR (*(RoReg*)0x400E18C8U) /**< \brief (PIOF) Edge/Level Status Register */ +#define REG_PIOF_FELLSR (*(WoReg*)0x400E18D0U) /**< \brief (PIOF) Falling Edge/Low Level Select Register */ +#define REG_PIOF_REHLSR (*(WoReg*)0x400E18D4U) /**< \brief (PIOF) Rising Edge/ High Level Select Register */ +#define REG_PIOF_FRLHSR (*(RoReg*)0x400E18D8U) /**< \brief (PIOF) Fall/Rise - Low/High Status Register */ +#define REG_PIOF_LOCKSR (*(RoReg*)0x400E18E0U) /**< \brief (PIOF) Lock Status */ +#define REG_PIOF_WPMR (*(RwReg*)0x400E18E4U) /**< \brief (PIOF) Write Protect Mode Register */ +#define REG_PIOF_WPSR (*(RoReg*)0x400E18E8U) /**< \brief (PIOF) Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_PIOF_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h new file mode 100644 index 0000000..9eb1ff5 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h
@@ -0,0 +1,102 @@ +/** + * \file + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM3XA_PMC_INSTANCE_ +#define _SAM3XA_PMC_INSTANCE_ + +/* ========== Register definition for PMC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PMC_SCER (0x400E0600U) /**< \brief (PMC) System Clock Enable Register */ +#define REG_PMC_SCDR (0x400E0604U) /**< \brief (PMC) System Clock Disable Register */ +#define REG_PMC_SCSR (0x400E0608U) /**< \brief (PMC) System Clock Status Register */ +#define REG_PMC_PCER0 (0x400E0610U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */ +#define REG_PMC_PCDR0 (0x400E0614U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */ +#define REG_PMC_PCSR0 (0x400E0618U) /**< \brief (PMC) Peripheral Clock Status Register 0 */ +#define REG_CKGR_UCKR (0x400E061CU) /**< \brief (PMC) UTMI Clock Register */ +#define REG_CKGR_MOR (0x400E0620U) /**< \brief (PMC) Main Oscillator Register */ +#define REG_CKGR_MCFR (0x400E0624U) /**< \brief (PMC) Main Clock Frequency Register */ +#define REG_CKGR_PLLAR (0x400E0628U) /**< \brief (PMC) PLLA Register */ +#define REG_PMC_MCKR (0x400E0630U) /**< \brief (PMC) Master Clock Register */ +#define REG_PMC_USB (0x400E0638U) /**< \brief (PMC) USB Clock Register */ +#define REG_PMC_PCK (0x400E0640U) /**< \brief (PMC) Programmable Clock 0 Register */ +#define REG_PMC_IER (0x400E0660U) /**< \brief (PMC) Interrupt Enable Register */ +#define REG_PMC_IDR (0x400E0664U) /**< \brief (PMC) Interrupt Disable Register */ +#define REG_PMC_SR (0x400E0668U) /**< \brief (PMC) Status Register */ +#define REG_PMC_IMR (0x400E066CU) /**< \brief (PMC) Interrupt Mask Register */ +#define REG_PMC_FSMR (0x400E0670U) /**< \brief (PMC) Fast Startup Mode Register */ +#define REG_PMC_FSPR (0x400E0674U) /**< \brief (PMC) Fast Startup Polarity Register */ +#define REG_PMC_FOCR (0x400E0678U) /**< \brief (PMC) Fault Output Clear Register */ +#define REG_PMC_WPMR (0x400E06E4U) /**< \brief (PMC) Write Protect Mode Register */ +#define REG_PMC_WPSR (0x400E06E8U) /**< \brief (PMC) Write Protect Status Register */ +#define REG_PMC_PCER1 (0x400E0700U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */ +#define REG_PMC_PCDR1 (0x400E0704U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */ +#define REG_PMC_PCSR1 (0x400E0708U) /**< \brief (PMC) Peripheral Clock Status Register 1 */ +#define REG_PMC_PCR (0x400E070CU) /**< \brief (PMC) Peripheral Control Register */ +#else +#define REG_PMC_SCER (*(WoReg*)0x400E0600U) /**< \brief (PMC) System Clock Enable Register */ +#define REG_PMC_SCDR (*(WoReg*)0x400E0604U) /**< \brief (PMC) System Clock Disable Register */ +#define REG_PMC_SCSR (*(RoReg*)0x400E0608U) /**< \brief (PMC) System Clock Status Register */ +#define REG_PMC_PCER0 (*(WoReg*)0x400E0610U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */ +#define REG_PMC_PCDR0 (*(WoReg*)0x400E0614U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */ +#define REG_PMC_PCSR0 (*(RoReg*)0x400E0618U) /**< \brief (PMC) Peripheral Clock Status Register 0 */ +#define REG_CKGR_UCKR (*(RwReg*)0x400E061CU) /**< \brief (PMC) UTMI Clock Register */ +#define REG_CKGR_MOR (*(RwReg*)0x400E0620U) /**< \brief (PMC) Main Oscillator Register */ +#define REG_CKGR_MCFR (*(RoReg*)0x400E0624U) /**< \brief (PMC) Main Clock Frequency Register */ +#define REG_CKGR_PLLAR (*(RwReg*)0x400E0628U) /**< \brief (PMC) PLLA Register */ +#define REG_PMC_MCKR (*(RwReg*)0x400E0630U) /**< \brief (PMC) Master Clock Register */ +#define REG_PMC_USB (*(RwReg*)0x400E0638U) /**< \brief (PMC) USB Clock Register */ +#define REG_PMC_PCK (*(RwReg*)0x400E0640U) /**< \brief (PMC) Programmable Clock 0 Register */ +#define REG_PMC_IER (*(WoReg*)0x400E0660U) /**< \brief (PMC) Interrupt Enable Register */ +#define REG_PMC_IDR (*(WoReg*)0x400E0664U) /**< \brief (PMC) Interrupt Disable Register */ +#define REG_PMC_SR (*(RoReg*)0x400E0668U) /**< \brief (PMC) Status Register */ +#define REG_PMC_IMR (*(RoReg*)0x400E066CU) /**< \brief (PMC) Interrupt Mask Register */ +#define REG_PMC_FSMR (*(RwReg*)0x400E0670U) /**< \brief (PMC) Fast Startup Mode Register */ +#define REG_PMC_FSPR (*(RwReg*)0x400E0674U) /**< \brief (PMC) Fast Startup Polarity Register */ +#define REG_PMC_FOCR (*(WoReg*)0x400E0678U) /**< \brief (PMC) Fault Output Clear Register */ +#define REG_PMC_WPMR (*(RwReg*)0x400E06E4U) /**< \brief (PMC) Write Protect Mode Register */ +#define REG_PMC_WPSR (*(RoReg*)0x400E06E8U) /**< \brief (PMC) Write Protect Status Register */ +#define REG_PMC_PCER1 (*(WoReg*)0x400E0700U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */ +#define REG_PMC_PCDR1 (*(WoReg*)0x400E0704U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */ +#define REG_PMC_PCSR1 (*(RoReg*)0x400E0708U) /**< \brief (PMC) Peripheral Clock Status Register 1 */ +#define REG_PMC_PCR (*(RwReg*)0x400E070CU) /**< \brief (PMC) Peripheral Control Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_PMC_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h new file mode 100644 index 0000000..cb1d7ec --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h
@@ -0,0 +1,318 @@ +/** + * \file + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM3XA_PWM_INSTANCE_ +#define _SAM3XA_PWM_INSTANCE_ + +/* ========== Register definition for PWM peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PWM_CLK (0x40094000U) /**< \brief (PWM) PWM Clock Register */ +#define REG_PWM_ENA (0x40094004U) /**< \brief (PWM) PWM Enable Register */ +#define REG_PWM_DIS (0x40094008U) /**< \brief (PWM) PWM Disable Register */ +#define REG_PWM_SR (0x4009400CU) /**< \brief (PWM) PWM Status Register */ +#define REG_PWM_IER1 (0x40094010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */ +#define REG_PWM_IDR1 (0x40094014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */ +#define REG_PWM_IMR1 (0x40094018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */ +#define REG_PWM_ISR1 (0x4009401CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */ +#define REG_PWM_SCM (0x40094020U) /**< \brief (PWM) PWM Sync Channels Mode Register */ +#define REG_PWM_SCUC (0x40094028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */ +#define REG_PWM_SCUP (0x4009402CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */ +#define REG_PWM_SCUPUPD (0x40094030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */ +#define REG_PWM_IER2 (0x40094034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */ +#define REG_PWM_IDR2 (0x40094038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */ +#define REG_PWM_IMR2 (0x4009403CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */ +#define REG_PWM_ISR2 (0x40094040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */ +#define REG_PWM_OOV (0x40094044U) /**< \brief (PWM) PWM Output Override Value Register */ +#define REG_PWM_OS (0x40094048U) /**< \brief (PWM) PWM Output Selection Register */ +#define REG_PWM_OSS (0x4009404CU) /**< \brief (PWM) PWM Output Selection Set Register */ +#define REG_PWM_OSC (0x40094050U) /**< \brief (PWM) PWM Output Selection Clear Register */ +#define REG_PWM_OSSUPD (0x40094054U) /**< \brief (PWM) PWM Output Selection Set Update Register */ +#define REG_PWM_OSCUPD (0x40094058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */ +#define REG_PWM_FMR (0x4009405CU) /**< \brief (PWM) PWM Fault Mode Register */ +#define REG_PWM_FSR (0x40094060U) /**< \brief (PWM) PWM Fault Status Register */ +#define REG_PWM_FCR (0x40094064U) /**< \brief (PWM) PWM Fault Clear Register */ +#define REG_PWM_FPV (0x40094068U) /**< \brief (PWM) PWM Fault Protection Value Register */ +#define REG_PWM_FPE1 (0x4009406CU) /**< \brief (PWM) PWM Fault Protection Enable Register 1 */ +#define REG_PWM_FPE2 (0x40094070U) /**< \brief (PWM) PWM Fault Protection Enable Register 2 */ +#define REG_PWM_ELMR (0x4009407CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */ +#define REG_PWM_SMMR (0x400940B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */ +#define REG_PWM_WPCR (0x400940E4U) /**< \brief (PWM) PWM Write Protect Control Register */ +#define REG_PWM_WPSR (0x400940E8U) /**< \brief (PWM) PWM Write Protect Status Register */ +#define REG_PWM_TPR (0x40094108U) /**< \brief (PWM) Transmit Pointer Register */ +#define REG_PWM_TCR (0x4009410CU) /**< \brief (PWM) Transmit Counter Register */ +#define REG_PWM_TNPR (0x40094118U) /**< \brief (PWM) Transmit Next Pointer Register */ +#define REG_PWM_TNCR (0x4009411CU) /**< \brief (PWM) Transmit Next Counter Register */ +#define REG_PWM_PTCR (0x40094120U) /**< \brief (PWM) Transfer Control Register */ +#define REG_PWM_PTSR (0x40094124U) /**< \brief (PWM) Transfer Status Register */ +#define REG_PWM_CMPV0 (0x40094130U) /**< \brief (PWM) PWM Comparison 0 Value Register */ +#define REG_PWM_CMPVUPD0 (0x40094134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */ +#define REG_PWM_CMPM0 (0x40094138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */ +#define REG_PWM_CMPMUPD0 (0x4009413CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */ +#define REG_PWM_CMPV1 (0x40094140U) /**< \brief (PWM) PWM Comparison 1 Value Register */ +#define REG_PWM_CMPVUPD1 (0x40094144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */ +#define REG_PWM_CMPM1 (0x40094148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */ +#define REG_PWM_CMPMUPD1 (0x4009414CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */ +#define REG_PWM_CMPV2 (0x40094150U) /**< \brief (PWM) PWM Comparison 2 Value Register */ +#define REG_PWM_CMPVUPD2 (0x40094154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */ +#define REG_PWM_CMPM2 (0x40094158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */ +#define REG_PWM_CMPMUPD2 (0x4009415CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */ +#define REG_PWM_CMPV3 (0x40094160U) /**< \brief (PWM) PWM Comparison 3 Value Register */ +#define REG_PWM_CMPVUPD3 (0x40094164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */ +#define REG_PWM_CMPM3 (0x40094168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */ +#define REG_PWM_CMPMUPD3 (0x4009416CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */ +#define REG_PWM_CMPV4 (0x40094170U) /**< \brief (PWM) PWM Comparison 4 Value Register */ +#define REG_PWM_CMPVUPD4 (0x40094174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */ +#define REG_PWM_CMPM4 (0x40094178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */ +#define REG_PWM_CMPMUPD4 (0x4009417CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */ +#define REG_PWM_CMPV5 (0x40094180U) /**< \brief (PWM) PWM Comparison 5 Value Register */ +#define REG_PWM_CMPVUPD5 (0x40094184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */ +#define REG_PWM_CMPM5 (0x40094188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */ +#define REG_PWM_CMPMUPD5 (0x4009418CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */ +#define REG_PWM_CMPV6 (0x40094190U) /**< \brief (PWM) PWM Comparison 6 Value Register */ +#define REG_PWM_CMPVUPD6 (0x40094194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */ +#define REG_PWM_CMPM6 (0x40094198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */ +#define REG_PWM_CMPMUPD6 (0x4009419CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */ +#define REG_PWM_CMPV7 (0x400941A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */ +#define REG_PWM_CMPVUPD7 (0x400941A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */ +#define REG_PWM_CMPM7 (0x400941A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */ +#define REG_PWM_CMPMUPD7 (0x400941ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */ +#define REG_PWM_CMR0 (0x40094200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */ +#define REG_PWM_CDTY0 (0x40094204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */ +#define REG_PWM_CDTYUPD0 (0x40094208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */ +#define REG_PWM_CPRD0 (0x4009420CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */ +#define REG_PWM_CPRDUPD0 (0x40094210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */ +#define REG_PWM_CCNT0 (0x40094214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */ +#define REG_PWM_DT0 (0x40094218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */ +#define REG_PWM_DTUPD0 (0x4009421CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */ +#define REG_PWM_CMR1 (0x40094220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */ +#define REG_PWM_CDTY1 (0x40094224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */ +#define REG_PWM_CDTYUPD1 (0x40094228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */ +#define REG_PWM_CPRD1 (0x4009422CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */ +#define REG_PWM_CPRDUPD1 (0x40094230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */ +#define REG_PWM_CCNT1 (0x40094234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */ +#define REG_PWM_DT1 (0x40094238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */ +#define REG_PWM_DTUPD1 (0x4009423CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */ +#define REG_PWM_CMR2 (0x40094240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */ +#define REG_PWM_CDTY2 (0x40094244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */ +#define REG_PWM_CDTYUPD2 (0x40094248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */ +#define REG_PWM_CPRD2 (0x4009424CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */ +#define REG_PWM_CPRDUPD2 (0x40094250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */ +#define REG_PWM_CCNT2 (0x40094254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */ +#define REG_PWM_DT2 (0x40094258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */ +#define REG_PWM_DTUPD2 (0x4009425CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */ +#define REG_PWM_CMR3 (0x40094260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */ +#define REG_PWM_CDTY3 (0x40094264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */ +#define REG_PWM_CDTYUPD3 (0x40094268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */ +#define REG_PWM_CPRD3 (0x4009426CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */ +#define REG_PWM_CPRDUPD3 (0x40094270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */ +#define REG_PWM_CCNT3 (0x40094274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */ +#define REG_PWM_DT3 (0x40094278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */ +#define REG_PWM_DTUPD3 (0x4009427CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */ +#define REG_PWM_CMR4 (0x40094280U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 4) */ +#define REG_PWM_CDTY4 (0x40094284U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 4) */ +#define REG_PWM_CDTYUPD4 (0x40094288U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 4) */ +#define REG_PWM_CPRD4 (0x4009428CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 4) */ +#define REG_PWM_CPRDUPD4 (0x40094290U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 4) */ +#define REG_PWM_CCNT4 (0x40094294U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 4) */ +#define REG_PWM_DT4 (0x40094298U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 4) */ +#define REG_PWM_DTUPD4 (0x4009429CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 4) */ +#define REG_PWM_CMR5 (0x400942A0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 5) */ +#define REG_PWM_CDTY5 (0x400942A4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 5) */ +#define REG_PWM_CDTYUPD5 (0x400942A8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 5) */ +#define REG_PWM_CPRD5 (0x400942ACU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 5) */ +#define REG_PWM_CPRDUPD5 (0x400942B0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 5) */ +#define REG_PWM_CCNT5 (0x400942B4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 5) */ +#define REG_PWM_DT5 (0x400942B8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 5) */ +#define REG_PWM_DTUPD5 (0x400942BCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 5) */ +#define REG_PWM_CMR6 (0x400942C0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 6) */ +#define REG_PWM_CDTY6 (0x400942C4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 6) */ +#define REG_PWM_CDTYUPD6 (0x400942C8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 6) */ +#define REG_PWM_CPRD6 (0x400942CCU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 6) */ +#define REG_PWM_CPRDUPD6 (0x400942D0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 6) */ +#define REG_PWM_CCNT6 (0x400942D4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 6) */ +#define REG_PWM_DT6 (0x400942D8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 6) */ +#define REG_PWM_DTUPD6 (0x400942DCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 6) */ +#define REG_PWM_CMR7 (0x400942E0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 7) */ +#define REG_PWM_CDTY7 (0x400942E4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 7) */ +#define REG_PWM_CDTYUPD7 (0x400942E8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 7) */ +#define REG_PWM_CPRD7 (0x400942ECU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 7) */ +#define REG_PWM_CPRDUPD7 (0x400942F0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 7) */ +#define REG_PWM_CCNT7 (0x400942F4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 7) */ +#define REG_PWM_DT7 (0x400942F8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 7) */ +#define REG_PWM_DTUPD7 (0x400942FCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 7) */ +#else +#define REG_PWM_CLK (*(RwReg*)0x40094000U) /**< \brief (PWM) PWM Clock Register */ +#define REG_PWM_ENA (*(WoReg*)0x40094004U) /**< \brief (PWM) PWM Enable Register */ +#define REG_PWM_DIS (*(WoReg*)0x40094008U) /**< \brief (PWM) PWM Disable Register */ +#define REG_PWM_SR (*(RoReg*)0x4009400CU) /**< \brief (PWM) PWM Status Register */ +#define REG_PWM_IER1 (*(WoReg*)0x40094010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */ +#define REG_PWM_IDR1 (*(WoReg*)0x40094014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */ +#define REG_PWM_IMR1 (*(RoReg*)0x40094018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */ +#define REG_PWM_ISR1 (*(RoReg*)0x4009401CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */ +#define REG_PWM_SCM (*(RwReg*)0x40094020U) /**< \brief (PWM) PWM Sync Channels Mode Register */ +#define REG_PWM_SCUC (*(RwReg*)0x40094028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */ +#define REG_PWM_SCUP (*(RwReg*)0x4009402CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */ +#define REG_PWM_SCUPUPD (*(WoReg*)0x40094030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */ +#define REG_PWM_IER2 (*(WoReg*)0x40094034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */ +#define REG_PWM_IDR2 (*(WoReg*)0x40094038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */ +#define REG_PWM_IMR2 (*(RoReg*)0x4009403CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */ +#define REG_PWM_ISR2 (*(RoReg*)0x40094040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */ +#define REG_PWM_OOV (*(RwReg*)0x40094044U) /**< \brief (PWM) PWM Output Override Value Register */ +#define REG_PWM_OS (*(RwReg*)0x40094048U) /**< \brief (PWM) PWM Output Selection Register */ +#define REG_PWM_OSS (*(WoReg*)0x4009404CU) /**< \brief (PWM) PWM Output Selection Set Register */ +#define REG_PWM_OSC (*(WoReg*)0x40094050U) /**< \brief (PWM) PWM Output Selection Clear Register */ +#define REG_PWM_OSSUPD (*(WoReg*)0x40094054U) /**< \brief (PWM) PWM Output Selection Set Update Register */ +#define REG_PWM_OSCUPD (*(WoReg*)0x40094058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */ +#define REG_PWM_FMR (*(RwReg*)0x4009405CU) /**< \brief (PWM) PWM Fault Mode Register */ +#define REG_PWM_FSR (*(RoReg*)0x40094060U) /**< \brief (PWM) PWM Fault Status Register */ +#define REG_PWM_FCR (*(WoReg*)0x40094064U) /**< \brief (PWM) PWM Fault Clear Register */ +#define REG_PWM_FPV (*(RwReg*)0x40094068U) /**< \brief (PWM) PWM Fault Protection Value Register */ +#define REG_PWM_FPE1 (*(RwReg*)0x4009406CU) /**< \brief (PWM) PWM Fault Protection Enable Register 1 */ +#define REG_PWM_FPE2 (*(RwReg*)0x40094070U) /**< \brief (PWM) PWM Fault Protection Enable Register 2 */ +#define REG_PWM_ELMR (*(RwReg*)0x4009407CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */ +#define REG_PWM_SMMR (*(RwReg*)0x400940B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */ +#define REG_PWM_WPCR (*(WoReg*)0x400940E4U) /**< \brief (PWM) PWM Write Protect Control Register */ +#define REG_PWM_WPSR (*(RoReg*)0x400940E8U) /**< \brief (PWM) PWM Write Protect Status Register */ +#define REG_PWM_TPR (*(RwReg*)0x40094108U) /**< \brief (PWM) Transmit Pointer Register */ +#define REG_PWM_TCR (*(RwReg*)0x4009410CU) /**< \brief (PWM) Transmit Counter Register */ +#define REG_PWM_TNPR (*(RwReg*)0x40094118U) /**< \brief (PWM) Transmit Next Pointer Register */ +#define REG_PWM_TNCR (*(RwReg*)0x4009411CU) /**< \brief (PWM) Transmit Next Counter Register */ +#define REG_PWM_PTCR (*(WoReg*)0x40094120U) /**< \brief (PWM) Transfer Control Register */ +#define REG_PWM_PTSR (*(RoReg*)0x40094124U) /**< \brief (PWM) Transfer Status Register */ +#define REG_PWM_CMPV0 (*(RwReg*)0x40094130U) /**< \brief (PWM) PWM Comparison 0 Value Register */ +#define REG_PWM_CMPVUPD0 (*(WoReg*)0x40094134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */ +#define REG_PWM_CMPM0 (*(RwReg*)0x40094138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */ +#define REG_PWM_CMPMUPD0 (*(WoReg*)0x4009413CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */ +#define REG_PWM_CMPV1 (*(RwReg*)0x40094140U) /**< \brief (PWM) PWM Comparison 1 Value Register */ +#define REG_PWM_CMPVUPD1 (*(WoReg*)0x40094144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */ +#define REG_PWM_CMPM1 (*(RwReg*)0x40094148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */ +#define REG_PWM_CMPMUPD1 (*(WoReg*)0x4009414CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */ +#define REG_PWM_CMPV2 (*(RwReg*)0x40094150U) /**< \brief (PWM) PWM Comparison 2 Value Register */ +#define REG_PWM_CMPVUPD2 (*(WoReg*)0x40094154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */ +#define REG_PWM_CMPM2 (*(RwReg*)0x40094158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */ +#define REG_PWM_CMPMUPD2 (*(WoReg*)0x4009415CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */ +#define REG_PWM_CMPV3 (*(RwReg*)0x40094160U) /**< \brief (PWM) PWM Comparison 3 Value Register */ +#define REG_PWM_CMPVUPD3 (*(WoReg*)0x40094164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */ +#define REG_PWM_CMPM3 (*(RwReg*)0x40094168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */ +#define REG_PWM_CMPMUPD3 (*(WoReg*)0x4009416CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */ +#define REG_PWM_CMPV4 (*(RwReg*)0x40094170U) /**< \brief (PWM) PWM Comparison 4 Value Register */ +#define REG_PWM_CMPVUPD4 (*(WoReg*)0x40094174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */ +#define REG_PWM_CMPM4 (*(RwReg*)0x40094178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */ +#define REG_PWM_CMPMUPD4 (*(WoReg*)0x4009417CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */ +#define REG_PWM_CMPV5 (*(RwReg*)0x40094180U) /**< \brief (PWM) PWM Comparison 5 Value Register */ +#define REG_PWM_CMPVUPD5 (*(WoReg*)0x40094184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */ +#define REG_PWM_CMPM5 (*(RwReg*)0x40094188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */ +#define REG_PWM_CMPMUPD5 (*(WoReg*)0x4009418CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */ +#define REG_PWM_CMPV6 (*(RwReg*)0x40094190U) /**< \brief (PWM) PWM Comparison 6 Value Register */ +#define REG_PWM_CMPVUPD6 (*(WoReg*)0x40094194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */ +#define REG_PWM_CMPM6 (*(RwReg*)0x40094198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */ +#define REG_PWM_CMPMUPD6 (*(WoReg*)0x4009419CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */ +#define REG_PWM_CMPV7 (*(RwReg*)0x400941A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */ +#define REG_PWM_CMPVUPD7 (*(WoReg*)0x400941A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */ +#define REG_PWM_CMPM7 (*(RwReg*)0x400941A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */ +#define REG_PWM_CMPMUPD7 (*(WoReg*)0x400941ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */ +#define REG_PWM_CMR0 (*(RwReg*)0x40094200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */ +#define REG_PWM_CDTY0 (*(RwReg*)0x40094204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */ +#define REG_PWM_CDTYUPD0 (*(WoReg*)0x40094208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */ +#define REG_PWM_CPRD0 (*(RwReg*)0x4009420CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */ +#define REG_PWM_CPRDUPD0 (*(WoReg*)0x40094210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */ +#define REG_PWM_CCNT0 (*(RoReg*)0x40094214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */ +#define REG_PWM_DT0 (*(RwReg*)0x40094218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */ +#define REG_PWM_DTUPD0 (*(WoReg*)0x4009421CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */ +#define REG_PWM_CMR1 (*(RwReg*)0x40094220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */ +#define REG_PWM_CDTY1 (*(RwReg*)0x40094224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */ +#define REG_PWM_CDTYUPD1 (*(WoReg*)0x40094228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */ +#define REG_PWM_CPRD1 (*(RwReg*)0x4009422CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */ +#define REG_PWM_CPRDUPD1 (*(WoReg*)0x40094230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */ +#define REG_PWM_CCNT1 (*(RoReg*)0x40094234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */ +#define REG_PWM_DT1 (*(RwReg*)0x40094238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */ +#define REG_PWM_DTUPD1 (*(WoReg*)0x4009423CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */ +#define REG_PWM_CMR2 (*(RwReg*)0x40094240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */ +#define REG_PWM_CDTY2 (*(RwReg*)0x40094244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */ +#define REG_PWM_CDTYUPD2 (*(WoReg*)0x40094248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */ +#define REG_PWM_CPRD2 (*(RwReg*)0x4009424CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */ +#define REG_PWM_CPRDUPD2 (*(WoReg*)0x40094250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */ +#define REG_PWM_CCNT2 (*(RoReg*)0x40094254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */ +#define REG_PWM_DT2 (*(RwReg*)0x40094258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */ +#define REG_PWM_DTUPD2 (*(WoReg*)0x4009425CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */ +#define REG_PWM_CMR3 (*(RwReg*)0x40094260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */ +#define REG_PWM_CDTY3 (*(RwReg*)0x40094264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */ +#define REG_PWM_CDTYUPD3 (*(WoReg*)0x40094268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */ +#define REG_PWM_CPRD3 (*(RwReg*)0x4009426CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */ +#define REG_PWM_CPRDUPD3 (*(WoReg*)0x40094270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */ +#define REG_PWM_CCNT3 (*(RoReg*)0x40094274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */ +#define REG_PWM_DT3 (*(RwReg*)0x40094278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */ +#define REG_PWM_DTUPD3 (*(WoReg*)0x4009427CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */ +#define REG_PWM_CMR4 (*(RwReg*)0x40094280U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 4) */ +#define REG_PWM_CDTY4 (*(RwReg*)0x40094284U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 4) */ +#define REG_PWM_CDTYUPD4 (*(WoReg*)0x40094288U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 4) */ +#define REG_PWM_CPRD4 (*(RwReg*)0x4009428CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 4) */ +#define REG_PWM_CPRDUPD4 (*(WoReg*)0x40094290U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 4) */ +#define REG_PWM_CCNT4 (*(RoReg*)0x40094294U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 4) */ +#define REG_PWM_DT4 (*(RwReg*)0x40094298U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 4) */ +#define REG_PWM_DTUPD4 (*(WoReg*)0x4009429CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 4) */ +#define REG_PWM_CMR5 (*(RwReg*)0x400942A0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 5) */ +#define REG_PWM_CDTY5 (*(RwReg*)0x400942A4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 5) */ +#define REG_PWM_CDTYUPD5 (*(WoReg*)0x400942A8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 5) */ +#define REG_PWM_CPRD5 (*(RwReg*)0x400942ACU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 5) */ +#define REG_PWM_CPRDUPD5 (*(WoReg*)0x400942B0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 5) */ +#define REG_PWM_CCNT5 (*(RoReg*)0x400942B4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 5) */ +#define REG_PWM_DT5 (*(RwReg*)0x400942B8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 5) */ +#define REG_PWM_DTUPD5 (*(WoReg*)0x400942BCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 5) */ +#define REG_PWM_CMR6 (*(RwReg*)0x400942C0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 6) */ +#define REG_PWM_CDTY6 (*(RwReg*)0x400942C4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 6) */ +#define REG_PWM_CDTYUPD6 (*(WoReg*)0x400942C8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 6) */ +#define REG_PWM_CPRD6 (*(RwReg*)0x400942CCU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 6) */ +#define REG_PWM_CPRDUPD6 (*(WoReg*)0x400942D0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 6) */ +#define REG_PWM_CCNT6 (*(RoReg*)0x400942D4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 6) */ +#define REG_PWM_DT6 (*(RwReg*)0x400942D8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 6) */ +#define REG_PWM_DTUPD6 (*(WoReg*)0x400942DCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 6) */ +#define REG_PWM_CMR7 (*(RwReg*)0x400942E0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 7) */ +#define REG_PWM_CDTY7 (*(RwReg*)0x400942E4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 7) */ +#define REG_PWM_CDTYUPD7 (*(WoReg*)0x400942E8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 7) */ +#define REG_PWM_CPRD7 (*(RwReg*)0x400942ECU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 7) */ +#define REG_PWM_CPRDUPD7 (*(WoReg*)0x400942F0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 7) */ +#define REG_PWM_CCNT7 (*(RoReg*)0x400942F4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 7) */ +#define REG_PWM_DT7 (*(RwReg*)0x400942F8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 7) */ +#define REG_PWM_DTUPD7 (*(WoReg*)0x400942FCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 7) */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_PWM_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h new file mode 100644 index 0000000..2915549 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h
@@ -0,0 +1,56 @@ +/** + * \file + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM3XA_RSTC_INSTANCE_ +#define _SAM3XA_RSTC_INSTANCE_ + +/* ========== Register definition for RSTC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_RSTC_CR (0x400E1A00U) /**< \brief (RSTC) Control Register */ +#define REG_RSTC_SR (0x400E1A04U) /**< \brief (RSTC) Status Register */ +#define REG_RSTC_MR (0x400E1A08U) /**< \brief (RSTC) Mode Register */ +#else +#define REG_RSTC_CR (*(WoReg*)0x400E1A00U) /**< \brief (RSTC) Control Register */ +#define REG_RSTC_SR (*(RoReg*)0x400E1A04U) /**< \brief (RSTC) Status Register */ +#define REG_RSTC_MR (*(RwReg*)0x400E1A08U) /**< \brief (RSTC) Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_RSTC_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h new file mode 100644 index 0000000..b646a5a --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h
@@ -0,0 +1,76 @@ +/** + * \file + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM3XA_RTC_INSTANCE_ +#define _SAM3XA_RTC_INSTANCE_ + +/* ========== Register definition for RTC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_RTC_CR (0x400E1A60U) /**< \brief (RTC) Control Register */ +#define REG_RTC_MR (0x400E1A64U) /**< \brief (RTC) Mode Register */ +#define REG_RTC_TIMR (0x400E1A68U) /**< \brief (RTC) Time Register */ +#define REG_RTC_CALR (0x400E1A6CU) /**< \brief (RTC) Calendar Register */ +#define REG_RTC_TIMALR (0x400E1A70U) /**< \brief (RTC) Time Alarm Register */ +#define REG_RTC_CALALR (0x400E1A74U) /**< \brief (RTC) Calendar Alarm Register */ +#define REG_RTC_SR (0x400E1A78U) /**< \brief (RTC) Status Register */ +#define REG_RTC_SCCR (0x400E1A7CU) /**< \brief (RTC) Status Clear Command Register */ +#define REG_RTC_IER (0x400E1A80U) /**< \brief (RTC) Interrupt Enable Register */ +#define REG_RTC_IDR (0x400E1A84U) /**< \brief (RTC) Interrupt Disable Register */ +#define REG_RTC_IMR (0x400E1A88U) /**< \brief (RTC) Interrupt Mask Register */ +#define REG_RTC_VER (0x400E1A8CU) /**< \brief (RTC) Valid Entry Register */ +#define REG_RTC_WPMR (0x400E1B44U) /**< \brief (RTC) Write Protect Mode Register */ +#else +#define REG_RTC_CR (*(RwReg*)0x400E1A60U) /**< \brief (RTC) Control Register */ +#define REG_RTC_MR (*(RwReg*)0x400E1A64U) /**< \brief (RTC) Mode Register */ +#define REG_RTC_TIMR (*(RwReg*)0x400E1A68U) /**< \brief (RTC) Time Register */ +#define REG_RTC_CALR (*(RwReg*)0x400E1A6CU) /**< \brief (RTC) Calendar Register */ +#define REG_RTC_TIMALR (*(RwReg*)0x400E1A70U) /**< \brief (RTC) Time Alarm Register */ +#define REG_RTC_CALALR (*(RwReg*)0x400E1A74U) /**< \brief (RTC) Calendar Alarm Register */ +#define REG_RTC_SR (*(RoReg*)0x400E1A78U) /**< \brief (RTC) Status Register */ +#define REG_RTC_SCCR (*(WoReg*)0x400E1A7CU) /**< \brief (RTC) Status Clear Command Register */ +#define REG_RTC_IER (*(WoReg*)0x400E1A80U) /**< \brief (RTC) Interrupt Enable Register */ +#define REG_RTC_IDR (*(WoReg*)0x400E1A84U) /**< \brief (RTC) Interrupt Disable Register */ +#define REG_RTC_IMR (*(RoReg*)0x400E1A88U) /**< \brief (RTC) Interrupt Mask Register */ +#define REG_RTC_VER (*(RoReg*)0x400E1A8CU) /**< \brief (RTC) Valid Entry Register */ +#define REG_RTC_WPMR (*(RwReg*)0x400E1B44U) /**< \brief (RTC) Write Protect Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_RTC_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h new file mode 100644 index 0000000..d27a9f5 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h
@@ -0,0 +1,58 @@ +/** + * \file + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM3XA_RTT_INSTANCE_ +#define _SAM3XA_RTT_INSTANCE_ + +/* ========== Register definition for RTT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_RTT_MR (0x400E1A30U) /**< \brief (RTT) Mode Register */ +#define REG_RTT_AR (0x400E1A34U) /**< \brief (RTT) Alarm Register */ +#define REG_RTT_VR (0x400E1A38U) /**< \brief (RTT) Value Register */ +#define REG_RTT_SR (0x400E1A3CU) /**< \brief (RTT) Status Register */ +#else +#define REG_RTT_MR (*(RwReg*)0x400E1A30U) /**< \brief (RTT) Mode Register */ +#define REG_RTT_AR (*(RwReg*)0x400E1A34U) /**< \brief (RTT) Alarm Register */ +#define REG_RTT_VR (*(RoReg*)0x400E1A38U) /**< \brief (RTT) Value Register */ +#define REG_RTT_SR (*(RoReg*)0x400E1A3CU) /**< \brief (RTT) Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_RTT_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_sdramc.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_sdramc.h new file mode 100644 index 0000000..16a1f04 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_sdramc.h
@@ -0,0 +1,72 @@ +/** + * \file + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM3XA_SDRAMC_INSTANCE_ +#define _SAM3XA_SDRAMC_INSTANCE_ + +/* ========== Register definition for SDRAMC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SDRAMC_MR (0x400E0200U) /**< \brief (SDRAMC) SDRAMC Mode Register */ +#define REG_SDRAMC_TR (0x400E0204U) /**< \brief (SDRAMC) SDRAMC Refresh Timer Register */ +#define REG_SDRAMC_CR (0x400E0208U) /**< \brief (SDRAMC) SDRAMC Configuration Register */ +#define REG_SDRAMC_LPR (0x400E0210U) /**< \brief (SDRAMC) SDRAMC Low Power Register */ +#define REG_SDRAMC_IER (0x400E0214U) /**< \brief (SDRAMC) SDRAMC Interrupt Enable Register */ +#define REG_SDRAMC_IDR (0x400E0218U) /**< \brief (SDRAMC) SDRAMC Interrupt Disable Register */ +#define REG_SDRAMC_IMR (0x400E021CU) /**< \brief (SDRAMC) SDRAMC Interrupt Mask Register */ +#define REG_SDRAMC_ISR (0x400E0220U) /**< \brief (SDRAMC) SDRAMC Interrupt Status Register */ +#define REG_SDRAMC_MDR (0x400E0224U) /**< \brief (SDRAMC) SDRAMC Memory Device Register */ +#define REG_SDRAMC_CR1 (0x400E0228U) /**< \brief (SDRAMC) SDRAMC Configuration Register 1 */ +#define REG_SDRAMC_OCMS (0x400E022CU) /**< \brief (SDRAMC) SDRAMC OCMS Register 1 */ +#else +#define REG_SDRAMC_MR (*(RwReg*)0x400E0200U) /**< \brief (SDRAMC) SDRAMC Mode Register */ +#define REG_SDRAMC_TR (*(RwReg*)0x400E0204U) /**< \brief (SDRAMC) SDRAMC Refresh Timer Register */ +#define REG_SDRAMC_CR (*(RwReg*)0x400E0208U) /**< \brief (SDRAMC) SDRAMC Configuration Register */ +#define REG_SDRAMC_LPR (*(RwReg*)0x400E0210U) /**< \brief (SDRAMC) SDRAMC Low Power Register */ +#define REG_SDRAMC_IER (*(WoReg*)0x400E0214U) /**< \brief (SDRAMC) SDRAMC Interrupt Enable Register */ +#define REG_SDRAMC_IDR (*(WoReg*)0x400E0218U) /**< \brief (SDRAMC) SDRAMC Interrupt Disable Register */ +#define REG_SDRAMC_IMR (*(RoReg*)0x400E021CU) /**< \brief (SDRAMC) SDRAMC Interrupt Mask Register */ +#define REG_SDRAMC_ISR (*(RoReg*)0x400E0220U) /**< \brief (SDRAMC) SDRAMC Interrupt Status Register */ +#define REG_SDRAMC_MDR (*(RwReg*)0x400E0224U) /**< \brief (SDRAMC) SDRAMC Memory Device Register */ +#define REG_SDRAMC_CR1 (*(RwReg*)0x400E0228U) /**< \brief (SDRAMC) SDRAMC Configuration Register 1 */ +#define REG_SDRAMC_OCMS (*(RwReg*)0x400E022CU) /**< \brief (SDRAMC) SDRAMC OCMS Register 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_SDRAMC_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_smc.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_smc.h new file mode 100644 index 0000000..7d3c5c1 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_smc.h
@@ -0,0 +1,196 @@ +/** + * \file + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM3XA_SMC_INSTANCE_ +#define _SAM3XA_SMC_INSTANCE_ + +/* ========== Register definition for SMC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SMC_CFG (0x400E0000U) /**< \brief (SMC) SMC NFC Configuration Register */ +#define REG_SMC_CTRL (0x400E0004U) /**< \brief (SMC) SMC NFC Control Register */ +#define REG_SMC_SR (0x400E0008U) /**< \brief (SMC) SMC NFC Status Register */ +#define REG_SMC_IER (0x400E000CU) /**< \brief (SMC) SMC NFC Interrupt Enable Register */ +#define REG_SMC_IDR (0x400E0010U) /**< \brief (SMC) SMC NFC Interrupt Disable Register */ +#define REG_SMC_IMR (0x400E0014U) /**< \brief (SMC) SMC NFC Interrupt Mask Register */ +#define REG_SMC_ADDR (0x400E0018U) /**< \brief (SMC) SMC NFC Address Cycle Zero Register */ +#define REG_SMC_BANK (0x400E001CU) /**< \brief (SMC) SMC Bank Address Register */ +#define REG_SMC_ECC_CTRL (0x400E0020U) /**< \brief (SMC) SMC ECC Control Register */ +#define REG_SMC_ECC_MD (0x400E0024U) /**< \brief (SMC) SMC ECC Mode Register */ +#define REG_SMC_ECC_SR1 (0x400E0028U) /**< \brief (SMC) SMC ECC Status 1 Register */ +#define REG_SMC_ECC_PR0 (0x400E002CU) /**< \brief (SMC) SMC ECC Parity 0 Register */ +#define REG_SMC_ECC_PR1 (0x400E0030U) /**< \brief (SMC) SMC ECC parity 1 Register */ +#define REG_SMC_ECC_SR2 (0x400E0034U) /**< \brief (SMC) SMC ECC status 2 Register */ +#define REG_SMC_ECC_PR2 (0x400E0038U) /**< \brief (SMC) SMC ECC parity 2 Register */ +#define REG_SMC_ECC_PR3 (0x400E003CU) /**< \brief (SMC) SMC ECC parity 3 Register */ +#define REG_SMC_ECC_PR4 (0x400E0040U) /**< \brief (SMC) SMC ECC parity 4 Register */ +#define REG_SMC_ECC_PR5 (0x400E0044U) /**< \brief (SMC) SMC ECC parity 5 Register */ +#define REG_SMC_ECC_PR6 (0x400E0048U) /**< \brief (SMC) SMC ECC parity 6 Register */ +#define REG_SMC_ECC_PR7 (0x400E004CU) /**< \brief (SMC) SMC ECC parity 7 Register */ +#define REG_SMC_ECC_PR8 (0x400E0050U) /**< \brief (SMC) SMC ECC parity 8 Register */ +#define REG_SMC_ECC_PR9 (0x400E0054U) /**< \brief (SMC) SMC ECC parity 9 Register */ +#define REG_SMC_ECC_PR10 (0x400E0058U) /**< \brief (SMC) SMC ECC parity 10 Register */ +#define REG_SMC_ECC_PR11 (0x400E005CU) /**< \brief (SMC) SMC ECC parity 11 Register */ +#define REG_SMC_ECC_PR12 (0x400E0060U) /**< \brief (SMC) SMC ECC parity 12 Register */ +#define REG_SMC_ECC_PR13 (0x400E0064U) /**< \brief (SMC) SMC ECC parity 13 Register */ +#define REG_SMC_ECC_PR14 (0x400E0068U) /**< \brief (SMC) SMC ECC parity 14 Register */ +#define REG_SMC_ECC_PR15 (0x400E006CU) /**< \brief (SMC) SMC ECC parity 15 Register */ +#define REG_SMC_SETUP0 (0x400E0070U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */ +#define REG_SMC_PULSE0 (0x400E0074U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */ +#define REG_SMC_CYCLE0 (0x400E0078U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */ +#define REG_SMC_TIMINGS0 (0x400E007CU) /**< \brief (SMC) SMC Timings Register (CS_number = 0) */ +#define REG_SMC_MODE0 (0x400E0080U) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */ +#define REG_SMC_SETUP1 (0x400E0084U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */ +#define REG_SMC_PULSE1 (0x400E0088U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */ +#define REG_SMC_CYCLE1 (0x400E008CU) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */ +#define REG_SMC_TIMINGS1 (0x400E0090U) /**< \brief (SMC) SMC Timings Register (CS_number = 1) */ +#define REG_SMC_MODE1 (0x400E0094U) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */ +#define REG_SMC_SETUP2 (0x400E0098U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */ +#define REG_SMC_PULSE2 (0x400E009CU) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */ +#define REG_SMC_CYCLE2 (0x400E00A0U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */ +#define REG_SMC_TIMINGS2 (0x400E00A4U) /**< \brief (SMC) SMC Timings Register (CS_number = 2) */ +#define REG_SMC_MODE2 (0x400E00A8U) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */ +#define REG_SMC_SETUP3 (0x400E00ACU) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */ +#define REG_SMC_PULSE3 (0x400E00B0U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */ +#define REG_SMC_CYCLE3 (0x400E00B4U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */ +#define REG_SMC_TIMINGS3 (0x400E00B8U) /**< \brief (SMC) SMC Timings Register (CS_number = 3) */ +#define REG_SMC_MODE3 (0x400E00BCU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */ +#define REG_SMC_SETUP4 (0x400E00C0U) /**< \brief (SMC) SMC Setup Register (CS_number = 4) */ +#define REG_SMC_PULSE4 (0x400E00C4U) /**< \brief (SMC) SMC Pulse Register (CS_number = 4) */ +#define REG_SMC_CYCLE4 (0x400E00C8U) /**< \brief (SMC) SMC Cycle Register (CS_number = 4) */ +#define REG_SMC_TIMINGS4 (0x400E00CCU) /**< \brief (SMC) SMC Timings Register (CS_number = 4) */ +#define REG_SMC_MODE4 (0x400E00D0U) /**< \brief (SMC) SMC Mode Register (CS_number = 4) */ +#define REG_SMC_SETUP5 (0x400E00D4U) /**< \brief (SMC) SMC Setup Register (CS_number = 5) */ +#define REG_SMC_PULSE5 (0x400E00D8U) /**< \brief (SMC) SMC Pulse Register (CS_number = 5) */ +#define REG_SMC_CYCLE5 (0x400E00DCU) /**< \brief (SMC) SMC Cycle Register (CS_number = 5) */ +#define REG_SMC_TIMINGS5 (0x400E00E0U) /**< \brief (SMC) SMC Timings Register (CS_number = 5) */ +#define REG_SMC_MODE5 (0x400E00E4U) /**< \brief (SMC) SMC Mode Register (CS_number = 5) */ +#define REG_SMC_SETUP6 (0x400E00E8U) /**< \brief (SMC) SMC Setup Register (CS_number = 6) */ +#define REG_SMC_PULSE6 (0x400E00ECU) /**< \brief (SMC) SMC Pulse Register (CS_number = 6) */ +#define REG_SMC_CYCLE6 (0x400E00F0U) /**< \brief (SMC) SMC Cycle Register (CS_number = 6) */ +#define REG_SMC_TIMINGS6 (0x400E00F4U) /**< \brief (SMC) SMC Timings Register (CS_number = 6) */ +#define REG_SMC_MODE6 (0x400E00F8U) /**< \brief (SMC) SMC Mode Register (CS_number = 6) */ +#define REG_SMC_SETUP7 (0x400E00FCU) /**< \brief (SMC) SMC Setup Register (CS_number = 7) */ +#define REG_SMC_PULSE7 (0x400E0100U) /**< \brief (SMC) SMC Pulse Register (CS_number = 7) */ +#define REG_SMC_CYCLE7 (0x400E0104U) /**< \brief (SMC) SMC Cycle Register (CS_number = 7) */ +#define REG_SMC_TIMINGS7 (0x400E0108U) /**< \brief (SMC) SMC Timings Register (CS_number = 7) */ +#define REG_SMC_MODE7 (0x400E010CU) /**< \brief (SMC) SMC Mode Register (CS_number = 7) */ +#define REG_SMC_OCMS (0x400E0110U) /**< \brief (SMC) SMC OCMS Register */ +#define REG_SMC_KEY1 (0x400E0114U) /**< \brief (SMC) SMC OCMS KEY1 Register */ +#define REG_SMC_KEY2 (0x400E0118U) /**< \brief (SMC) SMC OCMS KEY2 Register */ +#define REG_SMC_WPCR (0x400E01E4U) /**< \brief (SMC) Write Protection Control Register */ +#define REG_SMC_WPSR (0x400E01E8U) /**< \brief (SMC) Write Protection Status Register */ +#else +#define REG_SMC_CFG (*(RwReg*)0x400E0000U) /**< \brief (SMC) SMC NFC Configuration Register */ +#define REG_SMC_CTRL (*(WoReg*)0x400E0004U) /**< \brief (SMC) SMC NFC Control Register */ +#define REG_SMC_SR (*(RoReg*)0x400E0008U) /**< \brief (SMC) SMC NFC Status Register */ +#define REG_SMC_IER (*(WoReg*)0x400E000CU) /**< \brief (SMC) SMC NFC Interrupt Enable Register */ +#define REG_SMC_IDR (*(WoReg*)0x400E0010U) /**< \brief (SMC) SMC NFC Interrupt Disable Register */ +#define REG_SMC_IMR (*(RoReg*)0x400E0014U) /**< \brief (SMC) SMC NFC Interrupt Mask Register */ +#define REG_SMC_ADDR (*(RwReg*)0x400E0018U) /**< \brief (SMC) SMC NFC Address Cycle Zero Register */ +#define REG_SMC_BANK (*(RwReg*)0x400E001CU) /**< \brief (SMC) SMC Bank Address Register */ +#define REG_SMC_ECC_CTRL (*(WoReg*)0x400E0020U) /**< \brief (SMC) SMC ECC Control Register */ +#define REG_SMC_ECC_MD (*(RwReg*)0x400E0024U) /**< \brief (SMC) SMC ECC Mode Register */ +#define REG_SMC_ECC_SR1 (*(RoReg*)0x400E0028U) /**< \brief (SMC) SMC ECC Status 1 Register */ +#define REG_SMC_ECC_PR0 (*(RoReg*)0x400E002CU) /**< \brief (SMC) SMC ECC Parity 0 Register */ +#define REG_SMC_ECC_PR1 (*(RoReg*)0x400E0030U) /**< \brief (SMC) SMC ECC parity 1 Register */ +#define REG_SMC_ECC_SR2 (*(RoReg*)0x400E0034U) /**< \brief (SMC) SMC ECC status 2 Register */ +#define REG_SMC_ECC_PR2 (*(RoReg*)0x400E0038U) /**< \brief (SMC) SMC ECC parity 2 Register */ +#define REG_SMC_ECC_PR3 (*(RoReg*)0x400E003CU) /**< \brief (SMC) SMC ECC parity 3 Register */ +#define REG_SMC_ECC_PR4 (*(RoReg*)0x400E0040U) /**< \brief (SMC) SMC ECC parity 4 Register */ +#define REG_SMC_ECC_PR5 (*(RoReg*)0x400E0044U) /**< \brief (SMC) SMC ECC parity 5 Register */ +#define REG_SMC_ECC_PR6 (*(RoReg*)0x400E0048U) /**< \brief (SMC) SMC ECC parity 6 Register */ +#define REG_SMC_ECC_PR7 (*(RoReg*)0x400E004CU) /**< \brief (SMC) SMC ECC parity 7 Register */ +#define REG_SMC_ECC_PR8 (*(RoReg*)0x400E0050U) /**< \brief (SMC) SMC ECC parity 8 Register */ +#define REG_SMC_ECC_PR9 (*(RoReg*)0x400E0054U) /**< \brief (SMC) SMC ECC parity 9 Register */ +#define REG_SMC_ECC_PR10 (*(RoReg*)0x400E0058U) /**< \brief (SMC) SMC ECC parity 10 Register */ +#define REG_SMC_ECC_PR11 (*(RoReg*)0x400E005CU) /**< \brief (SMC) SMC ECC parity 11 Register */ +#define REG_SMC_ECC_PR12 (*(RoReg*)0x400E0060U) /**< \brief (SMC) SMC ECC parity 12 Register */ +#define REG_SMC_ECC_PR13 (*(RoReg*)0x400E0064U) /**< \brief (SMC) SMC ECC parity 13 Register */ +#define REG_SMC_ECC_PR14 (*(RoReg*)0x400E0068U) /**< \brief (SMC) SMC ECC parity 14 Register */ +#define REG_SMC_ECC_PR15 (*(RoReg*)0x400E006CU) /**< \brief (SMC) SMC ECC parity 15 Register */ +#define REG_SMC_SETUP0 (*(RwReg*)0x400E0070U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */ +#define REG_SMC_PULSE0 (*(RwReg*)0x400E0074U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */ +#define REG_SMC_CYCLE0 (*(RwReg*)0x400E0078U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */ +#define REG_SMC_TIMINGS0 (*(RwReg*)0x400E007CU) /**< \brief (SMC) SMC Timings Register (CS_number = 0) */ +#define REG_SMC_MODE0 (*(RwReg*)0x400E0080U) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */ +#define REG_SMC_SETUP1 (*(RwReg*)0x400E0084U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */ +#define REG_SMC_PULSE1 (*(RwReg*)0x400E0088U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */ +#define REG_SMC_CYCLE1 (*(RwReg*)0x400E008CU) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */ +#define REG_SMC_TIMINGS1 (*(RwReg*)0x400E0090U) /**< \brief (SMC) SMC Timings Register (CS_number = 1) */ +#define REG_SMC_MODE1 (*(RwReg*)0x400E0094U) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */ +#define REG_SMC_SETUP2 (*(RwReg*)0x400E0098U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */ +#define REG_SMC_PULSE2 (*(RwReg*)0x400E009CU) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */ +#define REG_SMC_CYCLE2 (*(RwReg*)0x400E00A0U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */ +#define REG_SMC_TIMINGS2 (*(RwReg*)0x400E00A4U) /**< \brief (SMC) SMC Timings Register (CS_number = 2) */ +#define REG_SMC_MODE2 (*(RwReg*)0x400E00A8U) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */ +#define REG_SMC_SETUP3 (*(RwReg*)0x400E00ACU) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */ +#define REG_SMC_PULSE3 (*(RwReg*)0x400E00B0U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */ +#define REG_SMC_CYCLE3 (*(RwReg*)0x400E00B4U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */ +#define REG_SMC_TIMINGS3 (*(RwReg*)0x400E00B8U) /**< \brief (SMC) SMC Timings Register (CS_number = 3) */ +#define REG_SMC_MODE3 (*(RwReg*)0x400E00BCU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */ +#define REG_SMC_SETUP4 (*(RwReg*)0x400E00C0U) /**< \brief (SMC) SMC Setup Register (CS_number = 4) */ +#define REG_SMC_PULSE4 (*(RwReg*)0x400E00C4U) /**< \brief (SMC) SMC Pulse Register (CS_number = 4) */ +#define REG_SMC_CYCLE4 (*(RwReg*)0x400E00C8U) /**< \brief (SMC) SMC Cycle Register (CS_number = 4) */ +#define REG_SMC_TIMINGS4 (*(RwReg*)0x400E00CCU) /**< \brief (SMC) SMC Timings Register (CS_number = 4) */ +#define REG_SMC_MODE4 (*(RwReg*)0x400E00D0U) /**< \brief (SMC) SMC Mode Register (CS_number = 4) */ +#define REG_SMC_SETUP5 (*(RwReg*)0x400E00D4U) /**< \brief (SMC) SMC Setup Register (CS_number = 5) */ +#define REG_SMC_PULSE5 (*(RwReg*)0x400E00D8U) /**< \brief (SMC) SMC Pulse Register (CS_number = 5) */ +#define REG_SMC_CYCLE5 (*(RwReg*)0x400E00DCU) /**< \brief (SMC) SMC Cycle Register (CS_number = 5) */ +#define REG_SMC_TIMINGS5 (*(RwReg*)0x400E00E0U) /**< \brief (SMC) SMC Timings Register (CS_number = 5) */ +#define REG_SMC_MODE5 (*(RwReg*)0x400E00E4U) /**< \brief (SMC) SMC Mode Register (CS_number = 5) */ +#define REG_SMC_SETUP6 (*(RwReg*)0x400E00E8U) /**< \brief (SMC) SMC Setup Register (CS_number = 6) */ +#define REG_SMC_PULSE6 (*(RwReg*)0x400E00ECU) /**< \brief (SMC) SMC Pulse Register (CS_number = 6) */ +#define REG_SMC_CYCLE6 (*(RwReg*)0x400E00F0U) /**< \brief (SMC) SMC Cycle Register (CS_number = 6) */ +#define REG_SMC_TIMINGS6 (*(RwReg*)0x400E00F4U) /**< \brief (SMC) SMC Timings Register (CS_number = 6) */ +#define REG_SMC_MODE6 (*(RwReg*)0x400E00F8U) /**< \brief (SMC) SMC Mode Register (CS_number = 6) */ +#define REG_SMC_SETUP7 (*(RwReg*)0x400E00FCU) /**< \brief (SMC) SMC Setup Register (CS_number = 7) */ +#define REG_SMC_PULSE7 (*(RwReg*)0x400E0100U) /**< \brief (SMC) SMC Pulse Register (CS_number = 7) */ +#define REG_SMC_CYCLE7 (*(RwReg*)0x400E0104U) /**< \brief (SMC) SMC Cycle Register (CS_number = 7) */ +#define REG_SMC_TIMINGS7 (*(RwReg*)0x400E0108U) /**< \brief (SMC) SMC Timings Register (CS_number = 7) */ +#define REG_SMC_MODE7 (*(RwReg*)0x400E010CU) /**< \brief (SMC) SMC Mode Register (CS_number = 7) */ +#define REG_SMC_OCMS (*(RwReg*)0x400E0110U) /**< \brief (SMC) SMC OCMS Register */ +#define REG_SMC_KEY1 (*(WoReg*)0x400E0114U) /**< \brief (SMC) SMC OCMS KEY1 Register */ +#define REG_SMC_KEY2 (*(WoReg*)0x400E0118U) /**< \brief (SMC) SMC OCMS KEY2 Register */ +#define REG_SMC_WPCR (*(WoReg*)0x400E01E4U) /**< \brief (SMC) Write Protection Control Register */ +#define REG_SMC_WPSR (*(RoReg*)0x400E01E8U) /**< \brief (SMC) Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_SMC_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h new file mode 100644 index 0000000..353fb72 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h
@@ -0,0 +1,72 @@ +/** + * \file + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM3XA_SPI0_INSTANCE_ +#define _SAM3XA_SPI0_INSTANCE_ + +/* ========== Register definition for SPI0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SPI0_CR (0x40008000U) /**< \brief (SPI0) Control Register */ +#define REG_SPI0_MR (0x40008004U) /**< \brief (SPI0) Mode Register */ +#define REG_SPI0_RDR (0x40008008U) /**< \brief (SPI0) Receive Data Register */ +#define REG_SPI0_TDR (0x4000800CU) /**< \brief (SPI0) Transmit Data Register */ +#define REG_SPI0_SR (0x40008010U) /**< \brief (SPI0) Status Register */ +#define REG_SPI0_IER (0x40008014U) /**< \brief (SPI0) Interrupt Enable Register */ +#define REG_SPI0_IDR (0x40008018U) /**< \brief (SPI0) Interrupt Disable Register */ +#define REG_SPI0_IMR (0x4000801CU) /**< \brief (SPI0) Interrupt Mask Register */ +#define REG_SPI0_CSR (0x40008030U) /**< \brief (SPI0) Chip Select Register */ +#define REG_SPI0_WPMR (0x400080E4U) /**< \brief (SPI0) Write Protection Control Register */ +#define REG_SPI0_WPSR (0x400080E8U) /**< \brief (SPI0) Write Protection Status Register */ +#else +#define REG_SPI0_CR (*(WoReg*)0x40008000U) /**< \brief (SPI0) Control Register */ +#define REG_SPI0_MR (*(RwReg*)0x40008004U) /**< \brief (SPI0) Mode Register */ +#define REG_SPI0_RDR (*(RoReg*)0x40008008U) /**< \brief (SPI0) Receive Data Register */ +#define REG_SPI0_TDR (*(WoReg*)0x4000800CU) /**< \brief (SPI0) Transmit Data Register */ +#define REG_SPI0_SR (*(RoReg*)0x40008010U) /**< \brief (SPI0) Status Register */ +#define REG_SPI0_IER (*(WoReg*)0x40008014U) /**< \brief (SPI0) Interrupt Enable Register */ +#define REG_SPI0_IDR (*(WoReg*)0x40008018U) /**< \brief (SPI0) Interrupt Disable Register */ +#define REG_SPI0_IMR (*(RoReg*)0x4000801CU) /**< \brief (SPI0) Interrupt Mask Register */ +#define REG_SPI0_CSR (*(RwReg*)0x40008030U) /**< \brief (SPI0) Chip Select Register */ +#define REG_SPI0_WPMR (*(RwReg*)0x400080E4U) /**< \brief (SPI0) Write Protection Control Register */ +#define REG_SPI0_WPSR (*(RoReg*)0x400080E8U) /**< \brief (SPI0) Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_SPI0_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_spi1.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_spi1.h new file mode 100644 index 0000000..cf9d0e1 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_spi1.h
@@ -0,0 +1,72 @@ +/** + * \file + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM3XA_SPI1_INSTANCE_ +#define _SAM3XA_SPI1_INSTANCE_ + +/* ========== Register definition for SPI1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SPI1_CR (0x4000C000U) /**< \brief (SPI1) Control Register */ +#define REG_SPI1_MR (0x4000C004U) /**< \brief (SPI1) Mode Register */ +#define REG_SPI1_RDR (0x4000C008U) /**< \brief (SPI1) Receive Data Register */ +#define REG_SPI1_TDR (0x4000C00CU) /**< \brief (SPI1) Transmit Data Register */ +#define REG_SPI1_SR (0x4000C010U) /**< \brief (SPI1) Status Register */ +#define REG_SPI1_IER (0x4000C014U) /**< \brief (SPI1) Interrupt Enable Register */ +#define REG_SPI1_IDR (0x4000C018U) /**< \brief (SPI1) Interrupt Disable Register */ +#define REG_SPI1_IMR (0x4000C01CU) /**< \brief (SPI1) Interrupt Mask Register */ +#define REG_SPI1_CSR (0x4000C030U) /**< \brief (SPI1) Chip Select Register */ +#define REG_SPI1_WPMR (0x4000C0E4U) /**< \brief (SPI1) Write Protection Control Register */ +#define REG_SPI1_WPSR (0x4000C0E8U) /**< \brief (SPI1) Write Protection Status Register */ +#else +#define REG_SPI1_CR (*(WoReg*)0x4000C000U) /**< \brief (SPI1) Control Register */ +#define REG_SPI1_MR (*(RwReg*)0x4000C004U) /**< \brief (SPI1) Mode Register */ +#define REG_SPI1_RDR (*(RoReg*)0x4000C008U) /**< \brief (SPI1) Receive Data Register */ +#define REG_SPI1_TDR (*(WoReg*)0x4000C00CU) /**< \brief (SPI1) Transmit Data Register */ +#define REG_SPI1_SR (*(RoReg*)0x4000C010U) /**< \brief (SPI1) Status Register */ +#define REG_SPI1_IER (*(WoReg*)0x4000C014U) /**< \brief (SPI1) Interrupt Enable Register */ +#define REG_SPI1_IDR (*(WoReg*)0x4000C018U) /**< \brief (SPI1) Interrupt Disable Register */ +#define REG_SPI1_IMR (*(RoReg*)0x4000C01CU) /**< \brief (SPI1) Interrupt Mask Register */ +#define REG_SPI1_CSR (*(RwReg*)0x4000C030U) /**< \brief (SPI1) Chip Select Register */ +#define REG_SPI1_WPMR (*(RwReg*)0x4000C0E4U) /**< \brief (SPI1) Write Protection Control Register */ +#define REG_SPI1_WPSR (*(RoReg*)0x4000C0E8U) /**< \brief (SPI1) Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_SPI1_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h new file mode 100644 index 0000000..fe89992 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h
@@ -0,0 +1,86 @@ +/** + * \file + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM3XA_SSC_INSTANCE_ +#define _SAM3XA_SSC_INSTANCE_ + +/* ========== Register definition for SSC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SSC_CR (0x40004000U) /**< \brief (SSC) Control Register */ +#define REG_SSC_CMR (0x40004004U) /**< \brief (SSC) Clock Mode Register */ +#define REG_SSC_RCMR (0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */ +#define REG_SSC_RFMR (0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */ +#define REG_SSC_TCMR (0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */ +#define REG_SSC_TFMR (0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */ +#define REG_SSC_RHR (0x40004020U) /**< \brief (SSC) Receive Holding Register */ +#define REG_SSC_THR (0x40004024U) /**< \brief (SSC) Transmit Holding Register */ +#define REG_SSC_RSHR (0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */ +#define REG_SSC_TSHR (0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */ +#define REG_SSC_RC0R (0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */ +#define REG_SSC_RC1R (0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */ +#define REG_SSC_SR (0x40004040U) /**< \brief (SSC) Status Register */ +#define REG_SSC_IER (0x40004044U) /**< \brief (SSC) Interrupt Enable Register */ +#define REG_SSC_IDR (0x40004048U) /**< \brief (SSC) Interrupt Disable Register */ +#define REG_SSC_IMR (0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */ +#define REG_SSC_WPMR (0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */ +#define REG_SSC_WPSR (0x400040E8U) /**< \brief (SSC) Write Protect Status Register */ +#else +#define REG_SSC_CR (*(WoReg*)0x40004000U) /**< \brief (SSC) Control Register */ +#define REG_SSC_CMR (*(RwReg*)0x40004004U) /**< \brief (SSC) Clock Mode Register */ +#define REG_SSC_RCMR (*(RwReg*)0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */ +#define REG_SSC_RFMR (*(RwReg*)0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */ +#define REG_SSC_TCMR (*(RwReg*)0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */ +#define REG_SSC_TFMR (*(RwReg*)0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */ +#define REG_SSC_RHR (*(RoReg*)0x40004020U) /**< \brief (SSC) Receive Holding Register */ +#define REG_SSC_THR (*(WoReg*)0x40004024U) /**< \brief (SSC) Transmit Holding Register */ +#define REG_SSC_RSHR (*(RoReg*)0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */ +#define REG_SSC_TSHR (*(RwReg*)0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */ +#define REG_SSC_RC0R (*(RwReg*)0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */ +#define REG_SSC_RC1R (*(RwReg*)0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */ +#define REG_SSC_SR (*(RoReg*)0x40004040U) /**< \brief (SSC) Status Register */ +#define REG_SSC_IER (*(WoReg*)0x40004044U) /**< \brief (SSC) Interrupt Enable Register */ +#define REG_SSC_IDR (*(WoReg*)0x40004048U) /**< \brief (SSC) Interrupt Disable Register */ +#define REG_SSC_IMR (*(RoReg*)0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */ +#define REG_SSC_WPMR (*(RwReg*)0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */ +#define REG_SSC_WPSR (*(RoReg*)0x400040E8U) /**< \brief (SSC) Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_SSC_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_supc.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_supc.h new file mode 100644 index 0000000..d32c681 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_supc.h
@@ -0,0 +1,62 @@ +/** + * \file + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM3XA_SUPC_INSTANCE_ +#define _SAM3XA_SUPC_INSTANCE_ + +/* ========== Register definition for SUPC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SUPC_CR (0x400E1A10U) /**< \brief (SUPC) Supply Controller Control Register */ +#define REG_SUPC_SMMR (0x400E1A14U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */ +#define REG_SUPC_MR (0x400E1A18U) /**< \brief (SUPC) Supply Controller Mode Register */ +#define REG_SUPC_WUMR (0x400E1A1CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */ +#define REG_SUPC_WUIR (0x400E1A20U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */ +#define REG_SUPC_SR (0x400E1A24U) /**< \brief (SUPC) Supply Controller Status Register */ +#else +#define REG_SUPC_CR (*(WoReg*)0x400E1A10U) /**< \brief (SUPC) Supply Controller Control Register */ +#define REG_SUPC_SMMR (*(RwReg*)0x400E1A14U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */ +#define REG_SUPC_MR (*(RwReg*)0x400E1A18U) /**< \brief (SUPC) Supply Controller Mode Register */ +#define REG_SUPC_WUMR (*(RwReg*)0x400E1A1CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */ +#define REG_SUPC_WUIR (*(RwReg*)0x400E1A20U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */ +#define REG_SUPC_SR (*(RoReg*)0x400E1A24U) /**< \brief (SUPC) Supply Controller Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_SUPC_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h new file mode 100644 index 0000000..bf7cdcc --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h
@@ -0,0 +1,132 @@ +/** + * \file + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM3XA_TC0_INSTANCE_ +#define _SAM3XA_TC0_INSTANCE_ + +/* ========== Register definition for TC0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC0_CCR0 (0x40080000U) /**< \brief (TC0) Channel Control Register (channel = 0) */ +#define REG_TC0_CMR0 (0x40080004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */ +#define REG_TC0_SMMR0 (0x40080008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */ +#define REG_TC0_CV0 (0x40080010U) /**< \brief (TC0) Counter Value (channel = 0) */ +#define REG_TC0_RA0 (0x40080014U) /**< \brief (TC0) Register A (channel = 0) */ +#define REG_TC0_RB0 (0x40080018U) /**< \brief (TC0) Register B (channel = 0) */ +#define REG_TC0_RC0 (0x4008001CU) /**< \brief (TC0) Register C (channel = 0) */ +#define REG_TC0_SR0 (0x40080020U) /**< \brief (TC0) Status Register (channel = 0) */ +#define REG_TC0_IER0 (0x40080024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */ +#define REG_TC0_IDR0 (0x40080028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */ +#define REG_TC0_IMR0 (0x4008002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */ +#define REG_TC0_CCR1 (0x40080040U) /**< \brief (TC0) Channel Control Register (channel = 1) */ +#define REG_TC0_CMR1 (0x40080044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */ +#define REG_TC0_SMMR1 (0x40080048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */ +#define REG_TC0_CV1 (0x40080050U) /**< \brief (TC0) Counter Value (channel = 1) */ +#define REG_TC0_RA1 (0x40080054U) /**< \brief (TC0) Register A (channel = 1) */ +#define REG_TC0_RB1 (0x40080058U) /**< \brief (TC0) Register B (channel = 1) */ +#define REG_TC0_RC1 (0x4008005CU) /**< \brief (TC0) Register C (channel = 1) */ +#define REG_TC0_SR1 (0x40080060U) /**< \brief (TC0) Status Register (channel = 1) */ +#define REG_TC0_IER1 (0x40080064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */ +#define REG_TC0_IDR1 (0x40080068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */ +#define REG_TC0_IMR1 (0x4008006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */ +#define REG_TC0_CCR2 (0x40080080U) /**< \brief (TC0) Channel Control Register (channel = 2) */ +#define REG_TC0_CMR2 (0x40080084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */ +#define REG_TC0_SMMR2 (0x40080088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */ +#define REG_TC0_CV2 (0x40080090U) /**< \brief (TC0) Counter Value (channel = 2) */ +#define REG_TC0_RA2 (0x40080094U) /**< \brief (TC0) Register A (channel = 2) */ +#define REG_TC0_RB2 (0x40080098U) /**< \brief (TC0) Register B (channel = 2) */ +#define REG_TC0_RC2 (0x4008009CU) /**< \brief (TC0) Register C (channel = 2) */ +#define REG_TC0_SR2 (0x400800A0U) /**< \brief (TC0) Status Register (channel = 2) */ +#define REG_TC0_IER2 (0x400800A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */ +#define REG_TC0_IDR2 (0x400800A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */ +#define REG_TC0_IMR2 (0x400800ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */ +#define REG_TC0_BCR (0x400800C0U) /**< \brief (TC0) Block Control Register */ +#define REG_TC0_BMR (0x400800C4U) /**< \brief (TC0) Block Mode Register */ +#define REG_TC0_QIER (0x400800C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */ +#define REG_TC0_QIDR (0x400800CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */ +#define REG_TC0_QIMR (0x400800D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */ +#define REG_TC0_QISR (0x400800D4U) /**< \brief (TC0) QDEC Interrupt Status Register */ +#define REG_TC0_FMR (0x400800D8U) /**< \brief (TC0) Fault Mode Register */ +#define REG_TC0_WPMR (0x400800E4U) /**< \brief (TC0) Write Protect Mode Register */ +#else +#define REG_TC0_CCR0 (*(WoReg*)0x40080000U) /**< \brief (TC0) Channel Control Register (channel = 0) */ +#define REG_TC0_CMR0 (*(RwReg*)0x40080004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */ +#define REG_TC0_SMMR0 (*(RwReg*)0x40080008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */ +#define REG_TC0_CV0 (*(RoReg*)0x40080010U) /**< \brief (TC0) Counter Value (channel = 0) */ +#define REG_TC0_RA0 (*(RwReg*)0x40080014U) /**< \brief (TC0) Register A (channel = 0) */ +#define REG_TC0_RB0 (*(RwReg*)0x40080018U) /**< \brief (TC0) Register B (channel = 0) */ +#define REG_TC0_RC0 (*(RwReg*)0x4008001CU) /**< \brief (TC0) Register C (channel = 0) */ +#define REG_TC0_SR0 (*(RoReg*)0x40080020U) /**< \brief (TC0) Status Register (channel = 0) */ +#define REG_TC0_IER0 (*(WoReg*)0x40080024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */ +#define REG_TC0_IDR0 (*(WoReg*)0x40080028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */ +#define REG_TC0_IMR0 (*(RoReg*)0x4008002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */ +#define REG_TC0_CCR1 (*(WoReg*)0x40080040U) /**< \brief (TC0) Channel Control Register (channel = 1) */ +#define REG_TC0_CMR1 (*(RwReg*)0x40080044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */ +#define REG_TC0_SMMR1 (*(RwReg*)0x40080048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */ +#define REG_TC0_CV1 (*(RoReg*)0x40080050U) /**< \brief (TC0) Counter Value (channel = 1) */ +#define REG_TC0_RA1 (*(RwReg*)0x40080054U) /**< \brief (TC0) Register A (channel = 1) */ +#define REG_TC0_RB1 (*(RwReg*)0x40080058U) /**< \brief (TC0) Register B (channel = 1) */ +#define REG_TC0_RC1 (*(RwReg*)0x4008005CU) /**< \brief (TC0) Register C (channel = 1) */ +#define REG_TC0_SR1 (*(RoReg*)0x40080060U) /**< \brief (TC0) Status Register (channel = 1) */ +#define REG_TC0_IER1 (*(WoReg*)0x40080064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */ +#define REG_TC0_IDR1 (*(WoReg*)0x40080068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */ +#define REG_TC0_IMR1 (*(RoReg*)0x4008006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */ +#define REG_TC0_CCR2 (*(WoReg*)0x40080080U) /**< \brief (TC0) Channel Control Register (channel = 2) */ +#define REG_TC0_CMR2 (*(RwReg*)0x40080084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */ +#define REG_TC0_SMMR2 (*(RwReg*)0x40080088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */ +#define REG_TC0_CV2 (*(RoReg*)0x40080090U) /**< \brief (TC0) Counter Value (channel = 2) */ +#define REG_TC0_RA2 (*(RwReg*)0x40080094U) /**< \brief (TC0) Register A (channel = 2) */ +#define REG_TC0_RB2 (*(RwReg*)0x40080098U) /**< \brief (TC0) Register B (channel = 2) */ +#define REG_TC0_RC2 (*(RwReg*)0x4008009CU) /**< \brief (TC0) Register C (channel = 2) */ +#define REG_TC0_SR2 (*(RoReg*)0x400800A0U) /**< \brief (TC0) Status Register (channel = 2) */ +#define REG_TC0_IER2 (*(WoReg*)0x400800A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */ +#define REG_TC0_IDR2 (*(WoReg*)0x400800A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */ +#define REG_TC0_IMR2 (*(RoReg*)0x400800ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */ +#define REG_TC0_BCR (*(WoReg*)0x400800C0U) /**< \brief (TC0) Block Control Register */ +#define REG_TC0_BMR (*(RwReg*)0x400800C4U) /**< \brief (TC0) Block Mode Register */ +#define REG_TC0_QIER (*(WoReg*)0x400800C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */ +#define REG_TC0_QIDR (*(WoReg*)0x400800CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */ +#define REG_TC0_QIMR (*(RoReg*)0x400800D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */ +#define REG_TC0_QISR (*(RoReg*)0x400800D4U) /**< \brief (TC0) QDEC Interrupt Status Register */ +#define REG_TC0_FMR (*(RwReg*)0x400800D8U) /**< \brief (TC0) Fault Mode Register */ +#define REG_TC0_WPMR (*(RwReg*)0x400800E4U) /**< \brief (TC0) Write Protect Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_TC0_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h new file mode 100644 index 0000000..9d27ac7 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h
@@ -0,0 +1,132 @@ +/** + * \file + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM3XA_TC1_INSTANCE_ +#define _SAM3XA_TC1_INSTANCE_ + +/* ========== Register definition for TC1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC1_CCR0 (0x40084000U) /**< \brief (TC1) Channel Control Register (channel = 0) */ +#define REG_TC1_CMR0 (0x40084004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */ +#define REG_TC1_SMMR0 (0x40084008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */ +#define REG_TC1_CV0 (0x40084010U) /**< \brief (TC1) Counter Value (channel = 0) */ +#define REG_TC1_RA0 (0x40084014U) /**< \brief (TC1) Register A (channel = 0) */ +#define REG_TC1_RB0 (0x40084018U) /**< \brief (TC1) Register B (channel = 0) */ +#define REG_TC1_RC0 (0x4008401CU) /**< \brief (TC1) Register C (channel = 0) */ +#define REG_TC1_SR0 (0x40084020U) /**< \brief (TC1) Status Register (channel = 0) */ +#define REG_TC1_IER0 (0x40084024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */ +#define REG_TC1_IDR0 (0x40084028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */ +#define REG_TC1_IMR0 (0x4008402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */ +#define REG_TC1_CCR1 (0x40084040U) /**< \brief (TC1) Channel Control Register (channel = 1) */ +#define REG_TC1_CMR1 (0x40084044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */ +#define REG_TC1_SMMR1 (0x40084048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */ +#define REG_TC1_CV1 (0x40084050U) /**< \brief (TC1) Counter Value (channel = 1) */ +#define REG_TC1_RA1 (0x40084054U) /**< \brief (TC1) Register A (channel = 1) */ +#define REG_TC1_RB1 (0x40084058U) /**< \brief (TC1) Register B (channel = 1) */ +#define REG_TC1_RC1 (0x4008405CU) /**< \brief (TC1) Register C (channel = 1) */ +#define REG_TC1_SR1 (0x40084060U) /**< \brief (TC1) Status Register (channel = 1) */ +#define REG_TC1_IER1 (0x40084064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */ +#define REG_TC1_IDR1 (0x40084068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */ +#define REG_TC1_IMR1 (0x4008406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */ +#define REG_TC1_CCR2 (0x40084080U) /**< \brief (TC1) Channel Control Register (channel = 2) */ +#define REG_TC1_CMR2 (0x40084084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */ +#define REG_TC1_SMMR2 (0x40084088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */ +#define REG_TC1_CV2 (0x40084090U) /**< \brief (TC1) Counter Value (channel = 2) */ +#define REG_TC1_RA2 (0x40084094U) /**< \brief (TC1) Register A (channel = 2) */ +#define REG_TC1_RB2 (0x40084098U) /**< \brief (TC1) Register B (channel = 2) */ +#define REG_TC1_RC2 (0x4008409CU) /**< \brief (TC1) Register C (channel = 2) */ +#define REG_TC1_SR2 (0x400840A0U) /**< \brief (TC1) Status Register (channel = 2) */ +#define REG_TC1_IER2 (0x400840A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */ +#define REG_TC1_IDR2 (0x400840A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */ +#define REG_TC1_IMR2 (0x400840ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */ +#define REG_TC1_BCR (0x400840C0U) /**< \brief (TC1) Block Control Register */ +#define REG_TC1_BMR (0x400840C4U) /**< \brief (TC1) Block Mode Register */ +#define REG_TC1_QIER (0x400840C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */ +#define REG_TC1_QIDR (0x400840CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */ +#define REG_TC1_QIMR (0x400840D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */ +#define REG_TC1_QISR (0x400840D4U) /**< \brief (TC1) QDEC Interrupt Status Register */ +#define REG_TC1_FMR (0x400840D8U) /**< \brief (TC1) Fault Mode Register */ +#define REG_TC1_WPMR (0x400840E4U) /**< \brief (TC1) Write Protect Mode Register */ +#else +#define REG_TC1_CCR0 (*(WoReg*)0x40084000U) /**< \brief (TC1) Channel Control Register (channel = 0) */ +#define REG_TC1_CMR0 (*(RwReg*)0x40084004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */ +#define REG_TC1_SMMR0 (*(RwReg*)0x40084008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */ +#define REG_TC1_CV0 (*(RoReg*)0x40084010U) /**< \brief (TC1) Counter Value (channel = 0) */ +#define REG_TC1_RA0 (*(RwReg*)0x40084014U) /**< \brief (TC1) Register A (channel = 0) */ +#define REG_TC1_RB0 (*(RwReg*)0x40084018U) /**< \brief (TC1) Register B (channel = 0) */ +#define REG_TC1_RC0 (*(RwReg*)0x4008401CU) /**< \brief (TC1) Register C (channel = 0) */ +#define REG_TC1_SR0 (*(RoReg*)0x40084020U) /**< \brief (TC1) Status Register (channel = 0) */ +#define REG_TC1_IER0 (*(WoReg*)0x40084024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */ +#define REG_TC1_IDR0 (*(WoReg*)0x40084028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */ +#define REG_TC1_IMR0 (*(RoReg*)0x4008402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */ +#define REG_TC1_CCR1 (*(WoReg*)0x40084040U) /**< \brief (TC1) Channel Control Register (channel = 1) */ +#define REG_TC1_CMR1 (*(RwReg*)0x40084044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */ +#define REG_TC1_SMMR1 (*(RwReg*)0x40084048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */ +#define REG_TC1_CV1 (*(RoReg*)0x40084050U) /**< \brief (TC1) Counter Value (channel = 1) */ +#define REG_TC1_RA1 (*(RwReg*)0x40084054U) /**< \brief (TC1) Register A (channel = 1) */ +#define REG_TC1_RB1 (*(RwReg*)0x40084058U) /**< \brief (TC1) Register B (channel = 1) */ +#define REG_TC1_RC1 (*(RwReg*)0x4008405CU) /**< \brief (TC1) Register C (channel = 1) */ +#define REG_TC1_SR1 (*(RoReg*)0x40084060U) /**< \brief (TC1) Status Register (channel = 1) */ +#define REG_TC1_IER1 (*(WoReg*)0x40084064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */ +#define REG_TC1_IDR1 (*(WoReg*)0x40084068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */ +#define REG_TC1_IMR1 (*(RoReg*)0x4008406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */ +#define REG_TC1_CCR2 (*(WoReg*)0x40084080U) /**< \brief (TC1) Channel Control Register (channel = 2) */ +#define REG_TC1_CMR2 (*(RwReg*)0x40084084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */ +#define REG_TC1_SMMR2 (*(RwReg*)0x40084088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */ +#define REG_TC1_CV2 (*(RoReg*)0x40084090U) /**< \brief (TC1) Counter Value (channel = 2) */ +#define REG_TC1_RA2 (*(RwReg*)0x40084094U) /**< \brief (TC1) Register A (channel = 2) */ +#define REG_TC1_RB2 (*(RwReg*)0x40084098U) /**< \brief (TC1) Register B (channel = 2) */ +#define REG_TC1_RC2 (*(RwReg*)0x4008409CU) /**< \brief (TC1) Register C (channel = 2) */ +#define REG_TC1_SR2 (*(RoReg*)0x400840A0U) /**< \brief (TC1) Status Register (channel = 2) */ +#define REG_TC1_IER2 (*(WoReg*)0x400840A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */ +#define REG_TC1_IDR2 (*(WoReg*)0x400840A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */ +#define REG_TC1_IMR2 (*(RoReg*)0x400840ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */ +#define REG_TC1_BCR (*(WoReg*)0x400840C0U) /**< \brief (TC1) Block Control Register */ +#define REG_TC1_BMR (*(RwReg*)0x400840C4U) /**< \brief (TC1) Block Mode Register */ +#define REG_TC1_QIER (*(WoReg*)0x400840C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */ +#define REG_TC1_QIDR (*(WoReg*)0x400840CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */ +#define REG_TC1_QIMR (*(RoReg*)0x400840D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */ +#define REG_TC1_QISR (*(RoReg*)0x400840D4U) /**< \brief (TC1) QDEC Interrupt Status Register */ +#define REG_TC1_FMR (*(RwReg*)0x400840D8U) /**< \brief (TC1) Fault Mode Register */ +#define REG_TC1_WPMR (*(RwReg*)0x400840E4U) /**< \brief (TC1) Write Protect Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_TC1_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h new file mode 100644 index 0000000..ba1cc74 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h
@@ -0,0 +1,132 @@ +/** + * \file + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM3XA_TC2_INSTANCE_ +#define _SAM3XA_TC2_INSTANCE_ + +/* ========== Register definition for TC2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC2_CCR0 (0x40088000U) /**< \brief (TC2) Channel Control Register (channel = 0) */ +#define REG_TC2_CMR0 (0x40088004U) /**< \brief (TC2) Channel Mode Register (channel = 0) */ +#define REG_TC2_SMMR0 (0x40088008U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 0) */ +#define REG_TC2_CV0 (0x40088010U) /**< \brief (TC2) Counter Value (channel = 0) */ +#define REG_TC2_RA0 (0x40088014U) /**< \brief (TC2) Register A (channel = 0) */ +#define REG_TC2_RB0 (0x40088018U) /**< \brief (TC2) Register B (channel = 0) */ +#define REG_TC2_RC0 (0x4008801CU) /**< \brief (TC2) Register C (channel = 0) */ +#define REG_TC2_SR0 (0x40088020U) /**< \brief (TC2) Status Register (channel = 0) */ +#define REG_TC2_IER0 (0x40088024U) /**< \brief (TC2) Interrupt Enable Register (channel = 0) */ +#define REG_TC2_IDR0 (0x40088028U) /**< \brief (TC2) Interrupt Disable Register (channel = 0) */ +#define REG_TC2_IMR0 (0x4008802CU) /**< \brief (TC2) Interrupt Mask Register (channel = 0) */ +#define REG_TC2_CCR1 (0x40088040U) /**< \brief (TC2) Channel Control Register (channel = 1) */ +#define REG_TC2_CMR1 (0x40088044U) /**< \brief (TC2) Channel Mode Register (channel = 1) */ +#define REG_TC2_SMMR1 (0x40088048U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 1) */ +#define REG_TC2_CV1 (0x40088050U) /**< \brief (TC2) Counter Value (channel = 1) */ +#define REG_TC2_RA1 (0x40088054U) /**< \brief (TC2) Register A (channel = 1) */ +#define REG_TC2_RB1 (0x40088058U) /**< \brief (TC2) Register B (channel = 1) */ +#define REG_TC2_RC1 (0x4008805CU) /**< \brief (TC2) Register C (channel = 1) */ +#define REG_TC2_SR1 (0x40088060U) /**< \brief (TC2) Status Register (channel = 1) */ +#define REG_TC2_IER1 (0x40088064U) /**< \brief (TC2) Interrupt Enable Register (channel = 1) */ +#define REG_TC2_IDR1 (0x40088068U) /**< \brief (TC2) Interrupt Disable Register (channel = 1) */ +#define REG_TC2_IMR1 (0x4008806CU) /**< \brief (TC2) Interrupt Mask Register (channel = 1) */ +#define REG_TC2_CCR2 (0x40088080U) /**< \brief (TC2) Channel Control Register (channel = 2) */ +#define REG_TC2_CMR2 (0x40088084U) /**< \brief (TC2) Channel Mode Register (channel = 2) */ +#define REG_TC2_SMMR2 (0x40088088U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 2) */ +#define REG_TC2_CV2 (0x40088090U) /**< \brief (TC2) Counter Value (channel = 2) */ +#define REG_TC2_RA2 (0x40088094U) /**< \brief (TC2) Register A (channel = 2) */ +#define REG_TC2_RB2 (0x40088098U) /**< \brief (TC2) Register B (channel = 2) */ +#define REG_TC2_RC2 (0x4008809CU) /**< \brief (TC2) Register C (channel = 2) */ +#define REG_TC2_SR2 (0x400880A0U) /**< \brief (TC2) Status Register (channel = 2) */ +#define REG_TC2_IER2 (0x400880A4U) /**< \brief (TC2) Interrupt Enable Register (channel = 2) */ +#define REG_TC2_IDR2 (0x400880A8U) /**< \brief (TC2) Interrupt Disable Register (channel = 2) */ +#define REG_TC2_IMR2 (0x400880ACU) /**< \brief (TC2) Interrupt Mask Register (channel = 2) */ +#define REG_TC2_BCR (0x400880C0U) /**< \brief (TC2) Block Control Register */ +#define REG_TC2_BMR (0x400880C4U) /**< \brief (TC2) Block Mode Register */ +#define REG_TC2_QIER (0x400880C8U) /**< \brief (TC2) QDEC Interrupt Enable Register */ +#define REG_TC2_QIDR (0x400880CCU) /**< \brief (TC2) QDEC Interrupt Disable Register */ +#define REG_TC2_QIMR (0x400880D0U) /**< \brief (TC2) QDEC Interrupt Mask Register */ +#define REG_TC2_QISR (0x400880D4U) /**< \brief (TC2) QDEC Interrupt Status Register */ +#define REG_TC2_FMR (0x400880D8U) /**< \brief (TC2) Fault Mode Register */ +#define REG_TC2_WPMR (0x400880E4U) /**< \brief (TC2) Write Protect Mode Register */ +#else +#define REG_TC2_CCR0 (*(WoReg*)0x40088000U) /**< \brief (TC2) Channel Control Register (channel = 0) */ +#define REG_TC2_CMR0 (*(RwReg*)0x40088004U) /**< \brief (TC2) Channel Mode Register (channel = 0) */ +#define REG_TC2_SMMR0 (*(RwReg*)0x40088008U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 0) */ +#define REG_TC2_CV0 (*(RoReg*)0x40088010U) /**< \brief (TC2) Counter Value (channel = 0) */ +#define REG_TC2_RA0 (*(RwReg*)0x40088014U) /**< \brief (TC2) Register A (channel = 0) */ +#define REG_TC2_RB0 (*(RwReg*)0x40088018U) /**< \brief (TC2) Register B (channel = 0) */ +#define REG_TC2_RC0 (*(RwReg*)0x4008801CU) /**< \brief (TC2) Register C (channel = 0) */ +#define REG_TC2_SR0 (*(RoReg*)0x40088020U) /**< \brief (TC2) Status Register (channel = 0) */ +#define REG_TC2_IER0 (*(WoReg*)0x40088024U) /**< \brief (TC2) Interrupt Enable Register (channel = 0) */ +#define REG_TC2_IDR0 (*(WoReg*)0x40088028U) /**< \brief (TC2) Interrupt Disable Register (channel = 0) */ +#define REG_TC2_IMR0 (*(RoReg*)0x4008802CU) /**< \brief (TC2) Interrupt Mask Register (channel = 0) */ +#define REG_TC2_CCR1 (*(WoReg*)0x40088040U) /**< \brief (TC2) Channel Control Register (channel = 1) */ +#define REG_TC2_CMR1 (*(RwReg*)0x40088044U) /**< \brief (TC2) Channel Mode Register (channel = 1) */ +#define REG_TC2_SMMR1 (*(RwReg*)0x40088048U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 1) */ +#define REG_TC2_CV1 (*(RoReg*)0x40088050U) /**< \brief (TC2) Counter Value (channel = 1) */ +#define REG_TC2_RA1 (*(RwReg*)0x40088054U) /**< \brief (TC2) Register A (channel = 1) */ +#define REG_TC2_RB1 (*(RwReg*)0x40088058U) /**< \brief (TC2) Register B (channel = 1) */ +#define REG_TC2_RC1 (*(RwReg*)0x4008805CU) /**< \brief (TC2) Register C (channel = 1) */ +#define REG_TC2_SR1 (*(RoReg*)0x40088060U) /**< \brief (TC2) Status Register (channel = 1) */ +#define REG_TC2_IER1 (*(WoReg*)0x40088064U) /**< \brief (TC2) Interrupt Enable Register (channel = 1) */ +#define REG_TC2_IDR1 (*(WoReg*)0x40088068U) /**< \brief (TC2) Interrupt Disable Register (channel = 1) */ +#define REG_TC2_IMR1 (*(RoReg*)0x4008806CU) /**< \brief (TC2) Interrupt Mask Register (channel = 1) */ +#define REG_TC2_CCR2 (*(WoReg*)0x40088080U) /**< \brief (TC2) Channel Control Register (channel = 2) */ +#define REG_TC2_CMR2 (*(RwReg*)0x40088084U) /**< \brief (TC2) Channel Mode Register (channel = 2) */ +#define REG_TC2_SMMR2 (*(RwReg*)0x40088088U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 2) */ +#define REG_TC2_CV2 (*(RoReg*)0x40088090U) /**< \brief (TC2) Counter Value (channel = 2) */ +#define REG_TC2_RA2 (*(RwReg*)0x40088094U) /**< \brief (TC2) Register A (channel = 2) */ +#define REG_TC2_RB2 (*(RwReg*)0x40088098U) /**< \brief (TC2) Register B (channel = 2) */ +#define REG_TC2_RC2 (*(RwReg*)0x4008809CU) /**< \brief (TC2) Register C (channel = 2) */ +#define REG_TC2_SR2 (*(RoReg*)0x400880A0U) /**< \brief (TC2) Status Register (channel = 2) */ +#define REG_TC2_IER2 (*(WoReg*)0x400880A4U) /**< \brief (TC2) Interrupt Enable Register (channel = 2) */ +#define REG_TC2_IDR2 (*(WoReg*)0x400880A8U) /**< \brief (TC2) Interrupt Disable Register (channel = 2) */ +#define REG_TC2_IMR2 (*(RoReg*)0x400880ACU) /**< \brief (TC2) Interrupt Mask Register (channel = 2) */ +#define REG_TC2_BCR (*(WoReg*)0x400880C0U) /**< \brief (TC2) Block Control Register */ +#define REG_TC2_BMR (*(RwReg*)0x400880C4U) /**< \brief (TC2) Block Mode Register */ +#define REG_TC2_QIER (*(WoReg*)0x400880C8U) /**< \brief (TC2) QDEC Interrupt Enable Register */ +#define REG_TC2_QIDR (*(WoReg*)0x400880CCU) /**< \brief (TC2) QDEC Interrupt Disable Register */ +#define REG_TC2_QIMR (*(RoReg*)0x400880D0U) /**< \brief (TC2) QDEC Interrupt Mask Register */ +#define REG_TC2_QISR (*(RoReg*)0x400880D4U) /**< \brief (TC2) QDEC Interrupt Status Register */ +#define REG_TC2_FMR (*(RwReg*)0x400880D8U) /**< \brief (TC2) Fault Mode Register */ +#define REG_TC2_WPMR (*(RwReg*)0x400880E4U) /**< \brief (TC2) Write Protect Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_TC2_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_trng.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_trng.h new file mode 100644 index 0000000..e417669 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_trng.h
@@ -0,0 +1,62 @@ +/** + * \file + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM3XA_TRNG_INSTANCE_ +#define _SAM3XA_TRNG_INSTANCE_ + +/* ========== Register definition for TRNG peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TRNG_CR (0x400BC000U) /**< \brief (TRNG) Control Register */ +#define REG_TRNG_IER (0x400BC010U) /**< \brief (TRNG) Interrupt Enable Register */ +#define REG_TRNG_IDR (0x400BC014U) /**< \brief (TRNG) Interrupt Disable Register */ +#define REG_TRNG_IMR (0x400BC018U) /**< \brief (TRNG) Interrupt Mask Register */ +#define REG_TRNG_ISR (0x400BC01CU) /**< \brief (TRNG) Interrupt Status Register */ +#define REG_TRNG_ODATA (0x400BC050U) /**< \brief (TRNG) Output Data Register */ +#else +#define REG_TRNG_CR (*(WoReg*)0x400BC000U) /**< \brief (TRNG) Control Register */ +#define REG_TRNG_IER (*(WoReg*)0x400BC010U) /**< \brief (TRNG) Interrupt Enable Register */ +#define REG_TRNG_IDR (*(WoReg*)0x400BC014U) /**< \brief (TRNG) Interrupt Disable Register */ +#define REG_TRNG_IMR (*(RoReg*)0x400BC018U) /**< \brief (TRNG) Interrupt Mask Register */ +#define REG_TRNG_ISR (*(RoReg*)0x400BC01CU) /**< \brief (TRNG) Interrupt Status Register */ +#define REG_TRNG_ODATA (*(RoReg*)0x400BC050U) /**< \brief (TRNG) Output Data Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_TRNG_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h new file mode 100644 index 0000000..0f763ad --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h
@@ -0,0 +1,92 @@ +/** + * \file + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM3XA_TWI0_INSTANCE_ +#define _SAM3XA_TWI0_INSTANCE_ + +/* ========== Register definition for TWI0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TWI0_CR (0x4008C000U) /**< \brief (TWI0) Control Register */ +#define REG_TWI0_MMR (0x4008C004U) /**< \brief (TWI0) Master Mode Register */ +#define REG_TWI0_SMR (0x4008C008U) /**< \brief (TWI0) Slave Mode Register */ +#define REG_TWI0_IADR (0x4008C00CU) /**< \brief (TWI0) Internal Address Register */ +#define REG_TWI0_CWGR (0x4008C010U) /**< \brief (TWI0) Clock Waveform Generator Register */ +#define REG_TWI0_SR (0x4008C020U) /**< \brief (TWI0) Status Register */ +#define REG_TWI0_IER (0x4008C024U) /**< \brief (TWI0) Interrupt Enable Register */ +#define REG_TWI0_IDR (0x4008C028U) /**< \brief (TWI0) Interrupt Disable Register */ +#define REG_TWI0_IMR (0x4008C02CU) /**< \brief (TWI0) Interrupt Mask Register */ +#define REG_TWI0_RHR (0x4008C030U) /**< \brief (TWI0) Receive Holding Register */ +#define REG_TWI0_THR (0x4008C034U) /**< \brief (TWI0) Transmit Holding Register */ +#define REG_TWI0_RPR (0x4008C100U) /**< \brief (TWI0) Receive Pointer Register */ +#define REG_TWI0_RCR (0x4008C104U) /**< \brief (TWI0) Receive Counter Register */ +#define REG_TWI0_TPR (0x4008C108U) /**< \brief (TWI0) Transmit Pointer Register */ +#define REG_TWI0_TCR (0x4008C10CU) /**< \brief (TWI0) Transmit Counter Register */ +#define REG_TWI0_RNPR (0x4008C110U) /**< \brief (TWI0) Receive Next Pointer Register */ +#define REG_TWI0_RNCR (0x4008C114U) /**< \brief (TWI0) Receive Next Counter Register */ +#define REG_TWI0_TNPR (0x4008C118U) /**< \brief (TWI0) Transmit Next Pointer Register */ +#define REG_TWI0_TNCR (0x4008C11CU) /**< \brief (TWI0) Transmit Next Counter Register */ +#define REG_TWI0_PTCR (0x4008C120U) /**< \brief (TWI0) Transfer Control Register */ +#define REG_TWI0_PTSR (0x4008C124U) /**< \brief (TWI0) Transfer Status Register */ +#else +#define REG_TWI0_CR (*(WoReg*)0x4008C000U) /**< \brief (TWI0) Control Register */ +#define REG_TWI0_MMR (*(RwReg*)0x4008C004U) /**< \brief (TWI0) Master Mode Register */ +#define REG_TWI0_SMR (*(RwReg*)0x4008C008U) /**< \brief (TWI0) Slave Mode Register */ +#define REG_TWI0_IADR (*(RwReg*)0x4008C00CU) /**< \brief (TWI0) Internal Address Register */ +#define REG_TWI0_CWGR (*(RwReg*)0x4008C010U) /**< \brief (TWI0) Clock Waveform Generator Register */ +#define REG_TWI0_SR (*(RoReg*)0x4008C020U) /**< \brief (TWI0) Status Register */ +#define REG_TWI0_IER (*(WoReg*)0x4008C024U) /**< \brief (TWI0) Interrupt Enable Register */ +#define REG_TWI0_IDR (*(WoReg*)0x4008C028U) /**< \brief (TWI0) Interrupt Disable Register */ +#define REG_TWI0_IMR (*(RoReg*)0x4008C02CU) /**< \brief (TWI0) Interrupt Mask Register */ +#define REG_TWI0_RHR (*(RoReg*)0x4008C030U) /**< \brief (TWI0) Receive Holding Register */ +#define REG_TWI0_THR (*(WoReg*)0x4008C034U) /**< \brief (TWI0) Transmit Holding Register */ +#define REG_TWI0_RPR (*(RwReg*)0x4008C100U) /**< \brief (TWI0) Receive Pointer Register */ +#define REG_TWI0_RCR (*(RwReg*)0x4008C104U) /**< \brief (TWI0) Receive Counter Register */ +#define REG_TWI0_TPR (*(RwReg*)0x4008C108U) /**< \brief (TWI0) Transmit Pointer Register */ +#define REG_TWI0_TCR (*(RwReg*)0x4008C10CU) /**< \brief (TWI0) Transmit Counter Register */ +#define REG_TWI0_RNPR (*(RwReg*)0x4008C110U) /**< \brief (TWI0) Receive Next Pointer Register */ +#define REG_TWI0_RNCR (*(RwReg*)0x4008C114U) /**< \brief (TWI0) Receive Next Counter Register */ +#define REG_TWI0_TNPR (*(RwReg*)0x4008C118U) /**< \brief (TWI0) Transmit Next Pointer Register */ +#define REG_TWI0_TNCR (*(RwReg*)0x4008C11CU) /**< \brief (TWI0) Transmit Next Counter Register */ +#define REG_TWI0_PTCR (*(WoReg*)0x4008C120U) /**< \brief (TWI0) Transfer Control Register */ +#define REG_TWI0_PTSR (*(RoReg*)0x4008C124U) /**< \brief (TWI0) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_TWI0_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h new file mode 100644 index 0000000..328514f --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h
@@ -0,0 +1,92 @@ +/** + * \file + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM3XA_TWI1_INSTANCE_ +#define _SAM3XA_TWI1_INSTANCE_ + +/* ========== Register definition for TWI1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TWI1_CR (0x40090000U) /**< \brief (TWI1) Control Register */ +#define REG_TWI1_MMR (0x40090004U) /**< \brief (TWI1) Master Mode Register */ +#define REG_TWI1_SMR (0x40090008U) /**< \brief (TWI1) Slave Mode Register */ +#define REG_TWI1_IADR (0x4009000CU) /**< \brief (TWI1) Internal Address Register */ +#define REG_TWI1_CWGR (0x40090010U) /**< \brief (TWI1) Clock Waveform Generator Register */ +#define REG_TWI1_SR (0x40090020U) /**< \brief (TWI1) Status Register */ +#define REG_TWI1_IER (0x40090024U) /**< \brief (TWI1) Interrupt Enable Register */ +#define REG_TWI1_IDR (0x40090028U) /**< \brief (TWI1) Interrupt Disable Register */ +#define REG_TWI1_IMR (0x4009002CU) /**< \brief (TWI1) Interrupt Mask Register */ +#define REG_TWI1_RHR (0x40090030U) /**< \brief (TWI1) Receive Holding Register */ +#define REG_TWI1_THR (0x40090034U) /**< \brief (TWI1) Transmit Holding Register */ +#define REG_TWI1_RPR (0x40090100U) /**< \brief (TWI1) Receive Pointer Register */ +#define REG_TWI1_RCR (0x40090104U) /**< \brief (TWI1) Receive Counter Register */ +#define REG_TWI1_TPR (0x40090108U) /**< \brief (TWI1) Transmit Pointer Register */ +#define REG_TWI1_TCR (0x4009010CU) /**< \brief (TWI1) Transmit Counter Register */ +#define REG_TWI1_RNPR (0x40090110U) /**< \brief (TWI1) Receive Next Pointer Register */ +#define REG_TWI1_RNCR (0x40090114U) /**< \brief (TWI1) Receive Next Counter Register */ +#define REG_TWI1_TNPR (0x40090118U) /**< \brief (TWI1) Transmit Next Pointer Register */ +#define REG_TWI1_TNCR (0x4009011CU) /**< \brief (TWI1) Transmit Next Counter Register */ +#define REG_TWI1_PTCR (0x40090120U) /**< \brief (TWI1) Transfer Control Register */ +#define REG_TWI1_PTSR (0x40090124U) /**< \brief (TWI1) Transfer Status Register */ +#else +#define REG_TWI1_CR (*(WoReg*)0x40090000U) /**< \brief (TWI1) Control Register */ +#define REG_TWI1_MMR (*(RwReg*)0x40090004U) /**< \brief (TWI1) Master Mode Register */ +#define REG_TWI1_SMR (*(RwReg*)0x40090008U) /**< \brief (TWI1) Slave Mode Register */ +#define REG_TWI1_IADR (*(RwReg*)0x4009000CU) /**< \brief (TWI1) Internal Address Register */ +#define REG_TWI1_CWGR (*(RwReg*)0x40090010U) /**< \brief (TWI1) Clock Waveform Generator Register */ +#define REG_TWI1_SR (*(RoReg*)0x40090020U) /**< \brief (TWI1) Status Register */ +#define REG_TWI1_IER (*(WoReg*)0x40090024U) /**< \brief (TWI1) Interrupt Enable Register */ +#define REG_TWI1_IDR (*(WoReg*)0x40090028U) /**< \brief (TWI1) Interrupt Disable Register */ +#define REG_TWI1_IMR (*(RoReg*)0x4009002CU) /**< \brief (TWI1) Interrupt Mask Register */ +#define REG_TWI1_RHR (*(RoReg*)0x40090030U) /**< \brief (TWI1) Receive Holding Register */ +#define REG_TWI1_THR (*(WoReg*)0x40090034U) /**< \brief (TWI1) Transmit Holding Register */ +#define REG_TWI1_RPR (*(RwReg*)0x40090100U) /**< \brief (TWI1) Receive Pointer Register */ +#define REG_TWI1_RCR (*(RwReg*)0x40090104U) /**< \brief (TWI1) Receive Counter Register */ +#define REG_TWI1_TPR (*(RwReg*)0x40090108U) /**< \brief (TWI1) Transmit Pointer Register */ +#define REG_TWI1_TCR (*(RwReg*)0x4009010CU) /**< \brief (TWI1) Transmit Counter Register */ +#define REG_TWI1_RNPR (*(RwReg*)0x40090110U) /**< \brief (TWI1) Receive Next Pointer Register */ +#define REG_TWI1_RNCR (*(RwReg*)0x40090114U) /**< \brief (TWI1) Receive Next Counter Register */ +#define REG_TWI1_TNPR (*(RwReg*)0x40090118U) /**< \brief (TWI1) Transmit Next Pointer Register */ +#define REG_TWI1_TNCR (*(RwReg*)0x4009011CU) /**< \brief (TWI1) Transmit Next Counter Register */ +#define REG_TWI1_PTCR (*(WoReg*)0x40090120U) /**< \brief (TWI1) Transfer Control Register */ +#define REG_TWI1_PTSR (*(RoReg*)0x40090124U) /**< \brief (TWI1) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_TWI1_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_uart.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_uart.h new file mode 100644 index 0000000..c0d3b5e --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_uart.h
@@ -0,0 +1,88 @@ +/** + * \file + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM3XA_UART_INSTANCE_ +#define _SAM3XA_UART_INSTANCE_ + +/* ========== Register definition for UART peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_UART_CR (0x400E0800U) /**< \brief (UART) Control Register */ +#define REG_UART_MR (0x400E0804U) /**< \brief (UART) Mode Register */ +#define REG_UART_IER (0x400E0808U) /**< \brief (UART) Interrupt Enable Register */ +#define REG_UART_IDR (0x400E080CU) /**< \brief (UART) Interrupt Disable Register */ +#define REG_UART_IMR (0x400E0810U) /**< \brief (UART) Interrupt Mask Register */ +#define REG_UART_SR (0x400E0814U) /**< \brief (UART) Status Register */ +#define REG_UART_RHR (0x400E0818U) /**< \brief (UART) Receive Holding Register */ +#define REG_UART_THR (0x400E081CU) /**< \brief (UART) Transmit Holding Register */ +#define REG_UART_BRGR (0x400E0820U) /**< \brief (UART) Baud Rate Generator Register */ +#define REG_UART_RPR (0x400E0900U) /**< \brief (UART) Receive Pointer Register */ +#define REG_UART_RCR (0x400E0904U) /**< \brief (UART) Receive Counter Register */ +#define REG_UART_TPR (0x400E0908U) /**< \brief (UART) Transmit Pointer Register */ +#define REG_UART_TCR (0x400E090CU) /**< \brief (UART) Transmit Counter Register */ +#define REG_UART_RNPR (0x400E0910U) /**< \brief (UART) Receive Next Pointer Register */ +#define REG_UART_RNCR (0x400E0914U) /**< \brief (UART) Receive Next Counter Register */ +#define REG_UART_TNPR (0x400E0918U) /**< \brief (UART) Transmit Next Pointer Register */ +#define REG_UART_TNCR (0x400E091CU) /**< \brief (UART) Transmit Next Counter Register */ +#define REG_UART_PTCR (0x400E0920U) /**< \brief (UART) Transfer Control Register */ +#define REG_UART_PTSR (0x400E0924U) /**< \brief (UART) Transfer Status Register */ +#else +#define REG_UART_CR (*(WoReg*)0x400E0800U) /**< \brief (UART) Control Register */ +#define REG_UART_MR (*(RwReg*)0x400E0804U) /**< \brief (UART) Mode Register */ +#define REG_UART_IER (*(WoReg*)0x400E0808U) /**< \brief (UART) Interrupt Enable Register */ +#define REG_UART_IDR (*(WoReg*)0x400E080CU) /**< \brief (UART) Interrupt Disable Register */ +#define REG_UART_IMR (*(RoReg*)0x400E0810U) /**< \brief (UART) Interrupt Mask Register */ +#define REG_UART_SR (*(RoReg*)0x400E0814U) /**< \brief (UART) Status Register */ +#define REG_UART_RHR (*(RoReg*)0x400E0818U) /**< \brief (UART) Receive Holding Register */ +#define REG_UART_THR (*(WoReg*)0x400E081CU) /**< \brief (UART) Transmit Holding Register */ +#define REG_UART_BRGR (*(RwReg*)0x400E0820U) /**< \brief (UART) Baud Rate Generator Register */ +#define REG_UART_RPR (*(RwReg*)0x400E0900U) /**< \brief (UART) Receive Pointer Register */ +#define REG_UART_RCR (*(RwReg*)0x400E0904U) /**< \brief (UART) Receive Counter Register */ +#define REG_UART_TPR (*(RwReg*)0x400E0908U) /**< \brief (UART) Transmit Pointer Register */ +#define REG_UART_TCR (*(RwReg*)0x400E090CU) /**< \brief (UART) Transmit Counter Register */ +#define REG_UART_RNPR (*(RwReg*)0x400E0910U) /**< \brief (UART) Receive Next Pointer Register */ +#define REG_UART_RNCR (*(RwReg*)0x400E0914U) /**< \brief (UART) Receive Next Counter Register */ +#define REG_UART_TNPR (*(RwReg*)0x400E0918U) /**< \brief (UART) Transmit Next Pointer Register */ +#define REG_UART_TNCR (*(RwReg*)0x400E091CU) /**< \brief (UART) Transmit Next Counter Register */ +#define REG_UART_PTCR (*(WoReg*)0x400E0920U) /**< \brief (UART) Transfer Control Register */ +#define REG_UART_PTSR (*(RoReg*)0x400E0924U) /**< \brief (UART) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_UART_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h new file mode 100644 index 0000000..de5ebb4 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h
@@ -0,0 +1,246 @@ +/** + * \file + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM3XA_UOTGHS_INSTANCE_ +#define _SAM3XA_UOTGHS_INSTANCE_ + +/* ========== Register definition for UOTGHS peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_UOTGHS_DEVCTRL (0x400AC000U) /**< \brief (UOTGHS) Device General Control Register */ +#define REG_UOTGHS_DEVISR (0x400AC004U) /**< \brief (UOTGHS) Device Global Interrupt Status Register */ +#define REG_UOTGHS_DEVICR (0x400AC008U) /**< \brief (UOTGHS) Device Global Interrupt Clear Register */ +#define REG_UOTGHS_DEVIFR (0x400AC00CU) /**< \brief (UOTGHS) Device Global Interrupt Set Register */ +#define REG_UOTGHS_DEVIMR (0x400AC010U) /**< \brief (UOTGHS) Device Global Interrupt Mask Register */ +#define REG_UOTGHS_DEVIDR (0x400AC014U) /**< \brief (UOTGHS) Device Global Interrupt Disable Register */ +#define REG_UOTGHS_DEVIER (0x400AC018U) /**< \brief (UOTGHS) Device Global Interrupt Enable Register */ +#define REG_UOTGHS_DEVEPT (0x400AC01CU) /**< \brief (UOTGHS) Device Endpoint Register */ +#define REG_UOTGHS_DEVFNUM (0x400AC020U) /**< \brief (UOTGHS) Device Frame Number Register */ +#define REG_UOTGHS_DEVEPTCFG (0x400AC100U) /**< \brief (UOTGHS) Device Endpoint Configuration Register (n = 0) */ +#define REG_UOTGHS_DEVEPTISR (0x400AC130U) /**< \brief (UOTGHS) Device Endpoint Status Register (n = 0) */ +#define REG_UOTGHS_DEVEPTICR (0x400AC160U) /**< \brief (UOTGHS) Device Endpoint Clear Register (n = 0) */ +#define REG_UOTGHS_DEVEPTIFR (0x400AC190U) /**< \brief (UOTGHS) Device Endpoint Set Register (n = 0) */ +#define REG_UOTGHS_DEVEPTIMR (0x400AC1C0U) /**< \brief (UOTGHS) Device Endpoint Mask Register (n = 0) */ +#define REG_UOTGHS_DEVEPTIER (0x400AC1F0U) /**< \brief (UOTGHS) Device Endpoint Enable Register (n = 0) */ +#define REG_UOTGHS_DEVEPTIDR (0x400AC220U) /**< \brief (UOTGHS) Device Endpoint Disable Register (n = 0) */ +#define REG_UOTGHS_DEVDMANXTDSC1 (0x400AC310U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 1) */ +#define REG_UOTGHS_DEVDMAADDRESS1 (0x400AC314U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 1) */ +#define REG_UOTGHS_DEVDMACONTROL1 (0x400AC318U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 1) */ +#define REG_UOTGHS_DEVDMASTATUS1 (0x400AC31CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 1) */ +#define REG_UOTGHS_DEVDMANXTDSC2 (0x400AC320U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 2) */ +#define REG_UOTGHS_DEVDMAADDRESS2 (0x400AC324U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 2) */ +#define REG_UOTGHS_DEVDMACONTROL2 (0x400AC328U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 2) */ +#define REG_UOTGHS_DEVDMASTATUS2 (0x400AC32CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 2) */ +#define REG_UOTGHS_DEVDMANXTDSC3 (0x400AC330U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 3) */ +#define REG_UOTGHS_DEVDMAADDRESS3 (0x400AC334U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 3) */ +#define REG_UOTGHS_DEVDMACONTROL3 (0x400AC338U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 3) */ +#define REG_UOTGHS_DEVDMASTATUS3 (0x400AC33CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 3) */ +#define REG_UOTGHS_DEVDMANXTDSC4 (0x400AC340U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 4) */ +#define REG_UOTGHS_DEVDMAADDRESS4 (0x400AC344U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 4) */ +#define REG_UOTGHS_DEVDMACONTROL4 (0x400AC348U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 4) */ +#define REG_UOTGHS_DEVDMASTATUS4 (0x400AC34CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 4) */ +#define REG_UOTGHS_DEVDMANXTDSC5 (0x400AC350U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 5) */ +#define REG_UOTGHS_DEVDMAADDRESS5 (0x400AC354U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 5) */ +#define REG_UOTGHS_DEVDMACONTROL5 (0x400AC358U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 5) */ +#define REG_UOTGHS_DEVDMASTATUS5 (0x400AC35CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 5) */ +#define REG_UOTGHS_DEVDMANXTDSC6 (0x400AC360U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 6) */ +#define REG_UOTGHS_DEVDMAADDRESS6 (0x400AC364U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 6) */ +#define REG_UOTGHS_DEVDMACONTROL6 (0x400AC368U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 6) */ +#define REG_UOTGHS_DEVDMASTATUS6 (0x400AC36CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 6) */ +#define REG_UOTGHS_DEVDMANXTDSC7 (0x400AC370U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 7) */ +#define REG_UOTGHS_DEVDMAADDRESS7 (0x400AC374U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 7) */ +#define REG_UOTGHS_DEVDMACONTROL7 (0x400AC378U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 7) */ +#define REG_UOTGHS_DEVDMASTATUS7 (0x400AC37CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 7) */ +#define REG_UOTGHS_HSTCTRL (0x400AC400U) /**< \brief (UOTGHS) Host General Control Register */ +#define REG_UOTGHS_HSTISR (0x400AC404U) /**< \brief (UOTGHS) Host Global Interrupt Status Register */ +#define REG_UOTGHS_HSTICR (0x400AC408U) /**< \brief (UOTGHS) Host Global Interrupt Clear Register */ +#define REG_UOTGHS_HSTIFR (0x400AC40CU) /**< \brief (UOTGHS) Host Global Interrupt Set Register */ +#define REG_UOTGHS_HSTIMR (0x400AC410U) /**< \brief (UOTGHS) Host Global Interrupt Mask Register */ +#define REG_UOTGHS_HSTIDR (0x400AC414U) /**< \brief (UOTGHS) Host Global Interrupt Disable Register */ +#define REG_UOTGHS_HSTIER (0x400AC418U) /**< \brief (UOTGHS) Host Global Interrupt Enable Register */ +#define REG_UOTGHS_HSTPIP (0x400AC41CU) /**< \brief (UOTGHS) Host Pipe Register */ +#define REG_UOTGHS_HSTFNUM (0x400AC420U) /**< \brief (UOTGHS) Host Frame Number Register */ +#define REG_UOTGHS_HSTADDR1 (0x400AC424U) /**< \brief (UOTGHS) Host Address 1 Register */ +#define REG_UOTGHS_HSTADDR2 (0x400AC428U) /**< \brief (UOTGHS) Host Address 2 Register */ +#define REG_UOTGHS_HSTADDR3 (0x400AC42CU) /**< \brief (UOTGHS) Host Address 3 Register */ +#define REG_UOTGHS_HSTPIPCFG (0x400AC500U) /**< \brief (UOTGHS) Host Pipe Configuration Register (n = 0) */ +#define REG_UOTGHS_HSTPIPISR (0x400AC530U) /**< \brief (UOTGHS) Host Pipe Status Register (n = 0) */ +#define REG_UOTGHS_HSTPIPICR (0x400AC560U) /**< \brief (UOTGHS) Host Pipe Clear Register (n = 0) */ +#define REG_UOTGHS_HSTPIPIFR (0x400AC590U) /**< \brief (UOTGHS) Host Pipe Set Register (n = 0) */ +#define REG_UOTGHS_HSTPIPIMR (0x400AC5C0U) /**< \brief (UOTGHS) Host Pipe Mask Register (n = 0) */ +#define REG_UOTGHS_HSTPIPIER (0x400AC5F0U) /**< \brief (UOTGHS) Host Pipe Enable Register (n = 0) */ +#define REG_UOTGHS_HSTPIPIDR (0x400AC620U) /**< \brief (UOTGHS) Host Pipe Disable Register (n = 0) */ +#define REG_UOTGHS_HSTPIPINRQ (0x400AC650U) /**< \brief (UOTGHS) Host Pipe IN Request Register (n = 0) */ +#define REG_UOTGHS_HSTPIPERR (0x400AC680U) /**< \brief (UOTGHS) Host Pipe Error Register (n = 0) */ +#define REG_UOTGHS_HSTDMANXTDSC1 (0x400AC710U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 1) */ +#define REG_UOTGHS_HSTDMAADDRESS1 (0x400AC714U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 1) */ +#define REG_UOTGHS_HSTDMACONTROL1 (0x400AC718U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 1) */ +#define REG_UOTGHS_HSTDMASTATUS1 (0x400AC71CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 1) */ +#define REG_UOTGHS_HSTDMANXTDSC2 (0x400AC720U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 2) */ +#define REG_UOTGHS_HSTDMAADDRESS2 (0x400AC724U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 2) */ +#define REG_UOTGHS_HSTDMACONTROL2 (0x400AC728U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 2) */ +#define REG_UOTGHS_HSTDMASTATUS2 (0x400AC72CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 2) */ +#define REG_UOTGHS_HSTDMANXTDSC3 (0x400AC730U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 3) */ +#define REG_UOTGHS_HSTDMAADDRESS3 (0x400AC734U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 3) */ +#define REG_UOTGHS_HSTDMACONTROL3 (0x400AC738U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 3) */ +#define REG_UOTGHS_HSTDMASTATUS3 (0x400AC73CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 3) */ +#define REG_UOTGHS_HSTDMANXTDSC4 (0x400AC740U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 4) */ +#define REG_UOTGHS_HSTDMAADDRESS4 (0x400AC744U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 4) */ +#define REG_UOTGHS_HSTDMACONTROL4 (0x400AC748U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 4) */ +#define REG_UOTGHS_HSTDMASTATUS4 (0x400AC74CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 4) */ +#define REG_UOTGHS_HSTDMANXTDSC5 (0x400AC750U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 5) */ +#define REG_UOTGHS_HSTDMAADDRESS5 (0x400AC754U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 5) */ +#define REG_UOTGHS_HSTDMACONTROL5 (0x400AC758U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 5) */ +#define REG_UOTGHS_HSTDMASTATUS5 (0x400AC75CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 5) */ +#define REG_UOTGHS_HSTDMANXTDSC6 (0x400AC760U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 6) */ +#define REG_UOTGHS_HSTDMAADDRESS6 (0x400AC764U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 6) */ +#define REG_UOTGHS_HSTDMACONTROL6 (0x400AC768U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 6) */ +#define REG_UOTGHS_HSTDMASTATUS6 (0x400AC76CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 6) */ +#define REG_UOTGHS_HSTDMANXTDSC7 (0x400AC770U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 7) */ +#define REG_UOTGHS_HSTDMAADDRESS7 (0x400AC774U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 7) */ +#define REG_UOTGHS_HSTDMACONTROL7 (0x400AC778U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 7) */ +#define REG_UOTGHS_HSTDMASTATUS7 (0x400AC77CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 7) */ +#define REG_UOTGHS_CTRL (0x400AC800U) /**< \brief (UOTGHS) General Control Register */ +#define REG_UOTGHS_SR (0x400AC804U) /**< \brief (UOTGHS) General Status Register */ +#define REG_UOTGHS_SCR (0x400AC808U) /**< \brief (UOTGHS) General Status Clear Register */ +#define REG_UOTGHS_SFR (0x400AC80CU) /**< \brief (UOTGHS) General Status Set Register */ +#define REG_UOTGHS_FSM (0x400AC82CU) /**< \brief (UOTGHS) General Finite State Machine Register */ +#else +#define REG_UOTGHS_DEVCTRL (*(RwReg*)0x400AC000U) /**< \brief (UOTGHS) Device General Control Register */ +#define REG_UOTGHS_DEVISR (*(RoReg*)0x400AC004U) /**< \brief (UOTGHS) Device Global Interrupt Status Register */ +#define REG_UOTGHS_DEVICR (*(WoReg*)0x400AC008U) /**< \brief (UOTGHS) Device Global Interrupt Clear Register */ +#define REG_UOTGHS_DEVIFR (*(WoReg*)0x400AC00CU) /**< \brief (UOTGHS) Device Global Interrupt Set Register */ +#define REG_UOTGHS_DEVIMR (*(RoReg*)0x400AC010U) /**< \brief (UOTGHS) Device Global Interrupt Mask Register */ +#define REG_UOTGHS_DEVIDR (*(WoReg*)0x400AC014U) /**< \brief (UOTGHS) Device Global Interrupt Disable Register */ +#define REG_UOTGHS_DEVIER (*(WoReg*)0x400AC018U) /**< \brief (UOTGHS) Device Global Interrupt Enable Register */ +#define REG_UOTGHS_DEVEPT (*(RwReg*)0x400AC01CU) /**< \brief (UOTGHS) Device Endpoint Register */ +#define REG_UOTGHS_DEVFNUM (*(RoReg*)0x400AC020U) /**< \brief (UOTGHS) Device Frame Number Register */ +#define REG_UOTGHS_DEVEPTCFG (*(RwReg*)0x400AC100U) /**< \brief (UOTGHS) Device Endpoint Configuration Register (n = 0) */ +#define REG_UOTGHS_DEVEPTISR (*(RoReg*)0x400AC130U) /**< \brief (UOTGHS) Device Endpoint Status Register (n = 0) */ +#define REG_UOTGHS_DEVEPTICR (*(WoReg*)0x400AC160U) /**< \brief (UOTGHS) Device Endpoint Clear Register (n = 0) */ +#define REG_UOTGHS_DEVEPTIFR (*(WoReg*)0x400AC190U) /**< \brief (UOTGHS) Device Endpoint Set Register (n = 0) */ +#define REG_UOTGHS_DEVEPTIMR (*(RoReg*)0x400AC1C0U) /**< \brief (UOTGHS) Device Endpoint Mask Register (n = 0) */ +#define REG_UOTGHS_DEVEPTIER (*(WoReg*)0x400AC1F0U) /**< \brief (UOTGHS) Device Endpoint Enable Register (n = 0) */ +#define REG_UOTGHS_DEVEPTIDR (*(WoReg*)0x400AC220U) /**< \brief (UOTGHS) Device Endpoint Disable Register (n = 0) */ +#define REG_UOTGHS_DEVDMANXTDSC1 (*(RwReg*)0x400AC310U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 1) */ +#define REG_UOTGHS_DEVDMAADDRESS1 (*(RwReg*)0x400AC314U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 1) */ +#define REG_UOTGHS_DEVDMACONTROL1 (*(RwReg*)0x400AC318U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 1) */ +#define REG_UOTGHS_DEVDMASTATUS1 (*(RwReg*)0x400AC31CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 1) */ +#define REG_UOTGHS_DEVDMANXTDSC2 (*(RwReg*)0x400AC320U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 2) */ +#define REG_UOTGHS_DEVDMAADDRESS2 (*(RwReg*)0x400AC324U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 2) */ +#define REG_UOTGHS_DEVDMACONTROL2 (*(RwReg*)0x400AC328U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 2) */ +#define REG_UOTGHS_DEVDMASTATUS2 (*(RwReg*)0x400AC32CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 2) */ +#define REG_UOTGHS_DEVDMANXTDSC3 (*(RwReg*)0x400AC330U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 3) */ +#define REG_UOTGHS_DEVDMAADDRESS3 (*(RwReg*)0x400AC334U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 3) */ +#define REG_UOTGHS_DEVDMACONTROL3 (*(RwReg*)0x400AC338U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 3) */ +#define REG_UOTGHS_DEVDMASTATUS3 (*(RwReg*)0x400AC33CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 3) */ +#define REG_UOTGHS_DEVDMANXTDSC4 (*(RwReg*)0x400AC340U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 4) */ +#define REG_UOTGHS_DEVDMAADDRESS4 (*(RwReg*)0x400AC344U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 4) */ +#define REG_UOTGHS_DEVDMACONTROL4 (*(RwReg*)0x400AC348U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 4) */ +#define REG_UOTGHS_DEVDMASTATUS4 (*(RwReg*)0x400AC34CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 4) */ +#define REG_UOTGHS_DEVDMANXTDSC5 (*(RwReg*)0x400AC350U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 5) */ +#define REG_UOTGHS_DEVDMAADDRESS5 (*(RwReg*)0x400AC354U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 5) */ +#define REG_UOTGHS_DEVDMACONTROL5 (*(RwReg*)0x400AC358U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 5) */ +#define REG_UOTGHS_DEVDMASTATUS5 (*(RwReg*)0x400AC35CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 5) */ +#define REG_UOTGHS_DEVDMANXTDSC6 (*(RwReg*)0x400AC360U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 6) */ +#define REG_UOTGHS_DEVDMAADDRESS6 (*(RwReg*)0x400AC364U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 6) */ +#define REG_UOTGHS_DEVDMACONTROL6 (*(RwReg*)0x400AC368U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 6) */ +#define REG_UOTGHS_DEVDMASTATUS6 (*(RwReg*)0x400AC36CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 6) */ +#define REG_UOTGHS_DEVDMANXTDSC7 (*(RwReg*)0x400AC370U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 7) */ +#define REG_UOTGHS_DEVDMAADDRESS7 (*(RwReg*)0x400AC374U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 7) */ +#define REG_UOTGHS_DEVDMACONTROL7 (*(RwReg*)0x400AC378U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 7) */ +#define REG_UOTGHS_DEVDMASTATUS7 (*(RwReg*)0x400AC37CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 7) */ +#define REG_UOTGHS_HSTCTRL (*(RwReg*)0x400AC400U) /**< \brief (UOTGHS) Host General Control Register */ +#define REG_UOTGHS_HSTISR (*(RoReg*)0x400AC404U) /**< \brief (UOTGHS) Host Global Interrupt Status Register */ +#define REG_UOTGHS_HSTICR (*(WoReg*)0x400AC408U) /**< \brief (UOTGHS) Host Global Interrupt Clear Register */ +#define REG_UOTGHS_HSTIFR (*(WoReg*)0x400AC40CU) /**< \brief (UOTGHS) Host Global Interrupt Set Register */ +#define REG_UOTGHS_HSTIMR (*(RoReg*)0x400AC410U) /**< \brief (UOTGHS) Host Global Interrupt Mask Register */ +#define REG_UOTGHS_HSTIDR (*(WoReg*)0x400AC414U) /**< \brief (UOTGHS) Host Global Interrupt Disable Register */ +#define REG_UOTGHS_HSTIER (*(WoReg*)0x400AC418U) /**< \brief (UOTGHS) Host Global Interrupt Enable Register */ +#define REG_UOTGHS_HSTPIP (*(RwReg*)0x400AC41CU) /**< \brief (UOTGHS) Host Pipe Register */ +#define REG_UOTGHS_HSTFNUM (*(RwReg*)0x400AC420U) /**< \brief (UOTGHS) Host Frame Number Register */ +#define REG_UOTGHS_HSTADDR1 (*(RwReg*)0x400AC424U) /**< \brief (UOTGHS) Host Address 1 Register */ +#define REG_UOTGHS_HSTADDR2 (*(RwReg*)0x400AC428U) /**< \brief (UOTGHS) Host Address 2 Register */ +#define REG_UOTGHS_HSTADDR3 (*(RwReg*)0x400AC42CU) /**< \brief (UOTGHS) Host Address 3 Register */ +#define REG_UOTGHS_HSTPIPCFG (*(RwReg*)0x400AC500U) /**< \brief (UOTGHS) Host Pipe Configuration Register (n = 0) */ +#define REG_UOTGHS_HSTPIPISR (*(RoReg*)0x400AC530U) /**< \brief (UOTGHS) Host Pipe Status Register (n = 0) */ +#define REG_UOTGHS_HSTPIPICR (*(WoReg*)0x400AC560U) /**< \brief (UOTGHS) Host Pipe Clear Register (n = 0) */ +#define REG_UOTGHS_HSTPIPIFR (*(WoReg*)0x400AC590U) /**< \brief (UOTGHS) Host Pipe Set Register (n = 0) */ +#define REG_UOTGHS_HSTPIPIMR (*(RoReg*)0x400AC5C0U) /**< \brief (UOTGHS) Host Pipe Mask Register (n = 0) */ +#define REG_UOTGHS_HSTPIPIER (*(WoReg*)0x400AC5F0U) /**< \brief (UOTGHS) Host Pipe Enable Register (n = 0) */ +#define REG_UOTGHS_HSTPIPIDR (*(WoReg*)0x400AC620U) /**< \brief (UOTGHS) Host Pipe Disable Register (n = 0) */ +#define REG_UOTGHS_HSTPIPINRQ (*(RwReg*)0x400AC650U) /**< \brief (UOTGHS) Host Pipe IN Request Register (n = 0) */ +#define REG_UOTGHS_HSTPIPERR (*(RwReg*)0x400AC680U) /**< \brief (UOTGHS) Host Pipe Error Register (n = 0) */ +#define REG_UOTGHS_HSTDMANXTDSC1 (*(RwReg*)0x400AC710U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 1) */ +#define REG_UOTGHS_HSTDMAADDRESS1 (*(RwReg*)0x400AC714U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 1) */ +#define REG_UOTGHS_HSTDMACONTROL1 (*(RwReg*)0x400AC718U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 1) */ +#define REG_UOTGHS_HSTDMASTATUS1 (*(RwReg*)0x400AC71CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 1) */ +#define REG_UOTGHS_HSTDMANXTDSC2 (*(RwReg*)0x400AC720U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 2) */ +#define REG_UOTGHS_HSTDMAADDRESS2 (*(RwReg*)0x400AC724U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 2) */ +#define REG_UOTGHS_HSTDMACONTROL2 (*(RwReg*)0x400AC728U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 2) */ +#define REG_UOTGHS_HSTDMASTATUS2 (*(RwReg*)0x400AC72CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 2) */ +#define REG_UOTGHS_HSTDMANXTDSC3 (*(RwReg*)0x400AC730U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 3) */ +#define REG_UOTGHS_HSTDMAADDRESS3 (*(RwReg*)0x400AC734U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 3) */ +#define REG_UOTGHS_HSTDMACONTROL3 (*(RwReg*)0x400AC738U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 3) */ +#define REG_UOTGHS_HSTDMASTATUS3 (*(RwReg*)0x400AC73CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 3) */ +#define REG_UOTGHS_HSTDMANXTDSC4 (*(RwReg*)0x400AC740U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 4) */ +#define REG_UOTGHS_HSTDMAADDRESS4 (*(RwReg*)0x400AC744U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 4) */ +#define REG_UOTGHS_HSTDMACONTROL4 (*(RwReg*)0x400AC748U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 4) */ +#define REG_UOTGHS_HSTDMASTATUS4 (*(RwReg*)0x400AC74CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 4) */ +#define REG_UOTGHS_HSTDMANXTDSC5 (*(RwReg*)0x400AC750U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 5) */ +#define REG_UOTGHS_HSTDMAADDRESS5 (*(RwReg*)0x400AC754U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 5) */ +#define REG_UOTGHS_HSTDMACONTROL5 (*(RwReg*)0x400AC758U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 5) */ +#define REG_UOTGHS_HSTDMASTATUS5 (*(RwReg*)0x400AC75CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 5) */ +#define REG_UOTGHS_HSTDMANXTDSC6 (*(RwReg*)0x400AC760U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 6) */ +#define REG_UOTGHS_HSTDMAADDRESS6 (*(RwReg*)0x400AC764U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 6) */ +#define REG_UOTGHS_HSTDMACONTROL6 (*(RwReg*)0x400AC768U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 6) */ +#define REG_UOTGHS_HSTDMASTATUS6 (*(RwReg*)0x400AC76CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 6) */ +#define REG_UOTGHS_HSTDMANXTDSC7 (*(RwReg*)0x400AC770U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 7) */ +#define REG_UOTGHS_HSTDMAADDRESS7 (*(RwReg*)0x400AC774U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 7) */ +#define REG_UOTGHS_HSTDMACONTROL7 (*(RwReg*)0x400AC778U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 7) */ +#define REG_UOTGHS_HSTDMASTATUS7 (*(RwReg*)0x400AC77CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 7) */ +#define REG_UOTGHS_CTRL (*(RwReg*)0x400AC800U) /**< \brief (UOTGHS) General Control Register */ +#define REG_UOTGHS_SR (*(RoReg*)0x400AC804U) /**< \brief (UOTGHS) General Status Register */ +#define REG_UOTGHS_SCR (*(WoReg*)0x400AC808U) /**< \brief (UOTGHS) General Status Clear Register */ +#define REG_UOTGHS_SFR (*(WoReg*)0x400AC80CU) /**< \brief (UOTGHS) General Status Set Register */ +#define REG_UOTGHS_FSM (*(RoReg*)0x400AC82CU) /**< \brief (UOTGHS) General Finite State Machine Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_UOTGHS_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h new file mode 100644 index 0000000..2d5f277 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h
@@ -0,0 +1,108 @@ +/** + * \file + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM3XA_USART0_INSTANCE_ +#define _SAM3XA_USART0_INSTANCE_ + +/* ========== Register definition for USART0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_USART0_CR (0x40098000U) /**< \brief (USART0) Control Register */ +#define REG_USART0_MR (0x40098004U) /**< \brief (USART0) Mode Register */ +#define REG_USART0_IER (0x40098008U) /**< \brief (USART0) Interrupt Enable Register */ +#define REG_USART0_IDR (0x4009800CU) /**< \brief (USART0) Interrupt Disable Register */ +#define REG_USART0_IMR (0x40098010U) /**< \brief (USART0) Interrupt Mask Register */ +#define REG_USART0_CSR (0x40098014U) /**< \brief (USART0) Channel Status Register */ +#define REG_USART0_RHR (0x40098018U) /**< \brief (USART0) Receiver Holding Register */ +#define REG_USART0_THR (0x4009801CU) /**< \brief (USART0) Transmitter Holding Register */ +#define REG_USART0_BRGR (0x40098020U) /**< \brief (USART0) Baud Rate Generator Register */ +#define REG_USART0_RTOR (0x40098024U) /**< \brief (USART0) Receiver Time-out Register */ +#define REG_USART0_TTGR (0x40098028U) /**< \brief (USART0) Transmitter Timeguard Register */ +#define REG_USART0_FIDI (0x40098040U) /**< \brief (USART0) FI DI Ratio Register */ +#define REG_USART0_NER (0x40098044U) /**< \brief (USART0) Number of Errors Register */ +#define REG_USART0_IF (0x4009804CU) /**< \brief (USART0) IrDA Filter Register */ +#define REG_USART0_MAN (0x40098050U) /**< \brief (USART0) Manchester Encoder Decoder Register */ +#define REG_USART0_LINMR (0x40098054U) /**< \brief (USART0) LIN Mode Register */ +#define REG_USART0_LINIR (0x40098058U) /**< \brief (USART0) LIN Identifier Register */ +#define REG_USART0_WPMR (0x400980E4U) /**< \brief (USART0) Write Protect Mode Register */ +#define REG_USART0_WPSR (0x400980E8U) /**< \brief (USART0) Write Protect Status Register */ +#define REG_USART0_RPR (0x40098100U) /**< \brief (USART0) Receive Pointer Register */ +#define REG_USART0_RCR (0x40098104U) /**< \brief (USART0) Receive Counter Register */ +#define REG_USART0_TPR (0x40098108U) /**< \brief (USART0) Transmit Pointer Register */ +#define REG_USART0_TCR (0x4009810CU) /**< \brief (USART0) Transmit Counter Register */ +#define REG_USART0_RNPR (0x40098110U) /**< \brief (USART0) Receive Next Pointer Register */ +#define REG_USART0_RNCR (0x40098114U) /**< \brief (USART0) Receive Next Counter Register */ +#define REG_USART0_TNPR (0x40098118U) /**< \brief (USART0) Transmit Next Pointer Register */ +#define REG_USART0_TNCR (0x4009811CU) /**< \brief (USART0) Transmit Next Counter Register */ +#define REG_USART0_PTCR (0x40098120U) /**< \brief (USART0) Transfer Control Register */ +#define REG_USART0_PTSR (0x40098124U) /**< \brief (USART0) Transfer Status Register */ +#else +#define REG_USART0_CR (*(WoReg*)0x40098000U) /**< \brief (USART0) Control Register */ +#define REG_USART0_MR (*(RwReg*)0x40098004U) /**< \brief (USART0) Mode Register */ +#define REG_USART0_IER (*(WoReg*)0x40098008U) /**< \brief (USART0) Interrupt Enable Register */ +#define REG_USART0_IDR (*(WoReg*)0x4009800CU) /**< \brief (USART0) Interrupt Disable Register */ +#define REG_USART0_IMR (*(RoReg*)0x40098010U) /**< \brief (USART0) Interrupt Mask Register */ +#define REG_USART0_CSR (*(RoReg*)0x40098014U) /**< \brief (USART0) Channel Status Register */ +#define REG_USART0_RHR (*(RoReg*)0x40098018U) /**< \brief (USART0) Receiver Holding Register */ +#define REG_USART0_THR (*(WoReg*)0x4009801CU) /**< \brief (USART0) Transmitter Holding Register */ +#define REG_USART0_BRGR (*(RwReg*)0x40098020U) /**< \brief (USART0) Baud Rate Generator Register */ +#define REG_USART0_RTOR (*(RwReg*)0x40098024U) /**< \brief (USART0) Receiver Time-out Register */ +#define REG_USART0_TTGR (*(RwReg*)0x40098028U) /**< \brief (USART0) Transmitter Timeguard Register */ +#define REG_USART0_FIDI (*(RwReg*)0x40098040U) /**< \brief (USART0) FI DI Ratio Register */ +#define REG_USART0_NER (*(RoReg*)0x40098044U) /**< \brief (USART0) Number of Errors Register */ +#define REG_USART0_IF (*(RwReg*)0x4009804CU) /**< \brief (USART0) IrDA Filter Register */ +#define REG_USART0_MAN (*(RwReg*)0x40098050U) /**< \brief (USART0) Manchester Encoder Decoder Register */ +#define REG_USART0_LINMR (*(RwReg*)0x40098054U) /**< \brief (USART0) LIN Mode Register */ +#define REG_USART0_LINIR (*(RwReg*)0x40098058U) /**< \brief (USART0) LIN Identifier Register */ +#define REG_USART0_WPMR (*(RwReg*)0x400980E4U) /**< \brief (USART0) Write Protect Mode Register */ +#define REG_USART0_WPSR (*(RoReg*)0x400980E8U) /**< \brief (USART0) Write Protect Status Register */ +#define REG_USART0_RPR (*(RwReg*)0x40098100U) /**< \brief (USART0) Receive Pointer Register */ +#define REG_USART0_RCR (*(RwReg*)0x40098104U) /**< \brief (USART0) Receive Counter Register */ +#define REG_USART0_TPR (*(RwReg*)0x40098108U) /**< \brief (USART0) Transmit Pointer Register */ +#define REG_USART0_TCR (*(RwReg*)0x4009810CU) /**< \brief (USART0) Transmit Counter Register */ +#define REG_USART0_RNPR (*(RwReg*)0x40098110U) /**< \brief (USART0) Receive Next Pointer Register */ +#define REG_USART0_RNCR (*(RwReg*)0x40098114U) /**< \brief (USART0) Receive Next Counter Register */ +#define REG_USART0_TNPR (*(RwReg*)0x40098118U) /**< \brief (USART0) Transmit Next Pointer Register */ +#define REG_USART0_TNCR (*(RwReg*)0x4009811CU) /**< \brief (USART0) Transmit Next Counter Register */ +#define REG_USART0_PTCR (*(WoReg*)0x40098120U) /**< \brief (USART0) Transfer Control Register */ +#define REG_USART0_PTSR (*(RoReg*)0x40098124U) /**< \brief (USART0) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_USART0_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h new file mode 100644 index 0000000..e0fa053 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h
@@ -0,0 +1,108 @@ +/** + * \file + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM3XA_USART1_INSTANCE_ +#define _SAM3XA_USART1_INSTANCE_ + +/* ========== Register definition for USART1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_USART1_CR (0x4009C000U) /**< \brief (USART1) Control Register */ +#define REG_USART1_MR (0x4009C004U) /**< \brief (USART1) Mode Register */ +#define REG_USART1_IER (0x4009C008U) /**< \brief (USART1) Interrupt Enable Register */ +#define REG_USART1_IDR (0x4009C00CU) /**< \brief (USART1) Interrupt Disable Register */ +#define REG_USART1_IMR (0x4009C010U) /**< \brief (USART1) Interrupt Mask Register */ +#define REG_USART1_CSR (0x4009C014U) /**< \brief (USART1) Channel Status Register */ +#define REG_USART1_RHR (0x4009C018U) /**< \brief (USART1) Receiver Holding Register */ +#define REG_USART1_THR (0x4009C01CU) /**< \brief (USART1) Transmitter Holding Register */ +#define REG_USART1_BRGR (0x4009C020U) /**< \brief (USART1) Baud Rate Generator Register */ +#define REG_USART1_RTOR (0x4009C024U) /**< \brief (USART1) Receiver Time-out Register */ +#define REG_USART1_TTGR (0x4009C028U) /**< \brief (USART1) Transmitter Timeguard Register */ +#define REG_USART1_FIDI (0x4009C040U) /**< \brief (USART1) FI DI Ratio Register */ +#define REG_USART1_NER (0x4009C044U) /**< \brief (USART1) Number of Errors Register */ +#define REG_USART1_IF (0x4009C04CU) /**< \brief (USART1) IrDA Filter Register */ +#define REG_USART1_MAN (0x4009C050U) /**< \brief (USART1) Manchester Encoder Decoder Register */ +#define REG_USART1_LINMR (0x4009C054U) /**< \brief (USART1) LIN Mode Register */ +#define REG_USART1_LINIR (0x4009C058U) /**< \brief (USART1) LIN Identifier Register */ +#define REG_USART1_WPMR (0x4009C0E4U) /**< \brief (USART1) Write Protect Mode Register */ +#define REG_USART1_WPSR (0x4009C0E8U) /**< \brief (USART1) Write Protect Status Register */ +#define REG_USART1_RPR (0x4009C100U) /**< \brief (USART1) Receive Pointer Register */ +#define REG_USART1_RCR (0x4009C104U) /**< \brief (USART1) Receive Counter Register */ +#define REG_USART1_TPR (0x4009C108U) /**< \brief (USART1) Transmit Pointer Register */ +#define REG_USART1_TCR (0x4009C10CU) /**< \brief (USART1) Transmit Counter Register */ +#define REG_USART1_RNPR (0x4009C110U) /**< \brief (USART1) Receive Next Pointer Register */ +#define REG_USART1_RNCR (0x4009C114U) /**< \brief (USART1) Receive Next Counter Register */ +#define REG_USART1_TNPR (0x4009C118U) /**< \brief (USART1) Transmit Next Pointer Register */ +#define REG_USART1_TNCR (0x4009C11CU) /**< \brief (USART1) Transmit Next Counter Register */ +#define REG_USART1_PTCR (0x4009C120U) /**< \brief (USART1) Transfer Control Register */ +#define REG_USART1_PTSR (0x4009C124U) /**< \brief (USART1) Transfer Status Register */ +#else +#define REG_USART1_CR (*(WoReg*)0x4009C000U) /**< \brief (USART1) Control Register */ +#define REG_USART1_MR (*(RwReg*)0x4009C004U) /**< \brief (USART1) Mode Register */ +#define REG_USART1_IER (*(WoReg*)0x4009C008U) /**< \brief (USART1) Interrupt Enable Register */ +#define REG_USART1_IDR (*(WoReg*)0x4009C00CU) /**< \brief (USART1) Interrupt Disable Register */ +#define REG_USART1_IMR (*(RoReg*)0x4009C010U) /**< \brief (USART1) Interrupt Mask Register */ +#define REG_USART1_CSR (*(RoReg*)0x4009C014U) /**< \brief (USART1) Channel Status Register */ +#define REG_USART1_RHR (*(RoReg*)0x4009C018U) /**< \brief (USART1) Receiver Holding Register */ +#define REG_USART1_THR (*(WoReg*)0x4009C01CU) /**< \brief (USART1) Transmitter Holding Register */ +#define REG_USART1_BRGR (*(RwReg*)0x4009C020U) /**< \brief (USART1) Baud Rate Generator Register */ +#define REG_USART1_RTOR (*(RwReg*)0x4009C024U) /**< \brief (USART1) Receiver Time-out Register */ +#define REG_USART1_TTGR (*(RwReg*)0x4009C028U) /**< \brief (USART1) Transmitter Timeguard Register */ +#define REG_USART1_FIDI (*(RwReg*)0x4009C040U) /**< \brief (USART1) FI DI Ratio Register */ +#define REG_USART1_NER (*(RoReg*)0x4009C044U) /**< \brief (USART1) Number of Errors Register */ +#define REG_USART1_IF (*(RwReg*)0x4009C04CU) /**< \brief (USART1) IrDA Filter Register */ +#define REG_USART1_MAN (*(RwReg*)0x4009C050U) /**< \brief (USART1) Manchester Encoder Decoder Register */ +#define REG_USART1_LINMR (*(RwReg*)0x4009C054U) /**< \brief (USART1) LIN Mode Register */ +#define REG_USART1_LINIR (*(RwReg*)0x4009C058U) /**< \brief (USART1) LIN Identifier Register */ +#define REG_USART1_WPMR (*(RwReg*)0x4009C0E4U) /**< \brief (USART1) Write Protect Mode Register */ +#define REG_USART1_WPSR (*(RoReg*)0x4009C0E8U) /**< \brief (USART1) Write Protect Status Register */ +#define REG_USART1_RPR (*(RwReg*)0x4009C100U) /**< \brief (USART1) Receive Pointer Register */ +#define REG_USART1_RCR (*(RwReg*)0x4009C104U) /**< \brief (USART1) Receive Counter Register */ +#define REG_USART1_TPR (*(RwReg*)0x4009C108U) /**< \brief (USART1) Transmit Pointer Register */ +#define REG_USART1_TCR (*(RwReg*)0x4009C10CU) /**< \brief (USART1) Transmit Counter Register */ +#define REG_USART1_RNPR (*(RwReg*)0x4009C110U) /**< \brief (USART1) Receive Next Pointer Register */ +#define REG_USART1_RNCR (*(RwReg*)0x4009C114U) /**< \brief (USART1) Receive Next Counter Register */ +#define REG_USART1_TNPR (*(RwReg*)0x4009C118U) /**< \brief (USART1) Transmit Next Pointer Register */ +#define REG_USART1_TNCR (*(RwReg*)0x4009C11CU) /**< \brief (USART1) Transmit Next Counter Register */ +#define REG_USART1_PTCR (*(WoReg*)0x4009C120U) /**< \brief (USART1) Transfer Control Register */ +#define REG_USART1_PTSR (*(RoReg*)0x4009C124U) /**< \brief (USART1) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_USART1_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h new file mode 100644 index 0000000..e1600af --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h
@@ -0,0 +1,108 @@ +/** + * \file + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM3XA_USART2_INSTANCE_ +#define _SAM3XA_USART2_INSTANCE_ + +/* ========== Register definition for USART2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_USART2_CR (0x400A0000U) /**< \brief (USART2) Control Register */ +#define REG_USART2_MR (0x400A0004U) /**< \brief (USART2) Mode Register */ +#define REG_USART2_IER (0x400A0008U) /**< \brief (USART2) Interrupt Enable Register */ +#define REG_USART2_IDR (0x400A000CU) /**< \brief (USART2) Interrupt Disable Register */ +#define REG_USART2_IMR (0x400A0010U) /**< \brief (USART2) Interrupt Mask Register */ +#define REG_USART2_CSR (0x400A0014U) /**< \brief (USART2) Channel Status Register */ +#define REG_USART2_RHR (0x400A0018U) /**< \brief (USART2) Receiver Holding Register */ +#define REG_USART2_THR (0x400A001CU) /**< \brief (USART2) Transmitter Holding Register */ +#define REG_USART2_BRGR (0x400A0020U) /**< \brief (USART2) Baud Rate Generator Register */ +#define REG_USART2_RTOR (0x400A0024U) /**< \brief (USART2) Receiver Time-out Register */ +#define REG_USART2_TTGR (0x400A0028U) /**< \brief (USART2) Transmitter Timeguard Register */ +#define REG_USART2_FIDI (0x400A0040U) /**< \brief (USART2) FI DI Ratio Register */ +#define REG_USART2_NER (0x400A0044U) /**< \brief (USART2) Number of Errors Register */ +#define REG_USART2_IF (0x400A004CU) /**< \brief (USART2) IrDA Filter Register */ +#define REG_USART2_MAN (0x400A0050U) /**< \brief (USART2) Manchester Encoder Decoder Register */ +#define REG_USART2_LINMR (0x400A0054U) /**< \brief (USART2) LIN Mode Register */ +#define REG_USART2_LINIR (0x400A0058U) /**< \brief (USART2) LIN Identifier Register */ +#define REG_USART2_WPMR (0x400A00E4U) /**< \brief (USART2) Write Protect Mode Register */ +#define REG_USART2_WPSR (0x400A00E8U) /**< \brief (USART2) Write Protect Status Register */ +#define REG_USART2_RPR (0x400A0100U) /**< \brief (USART2) Receive Pointer Register */ +#define REG_USART2_RCR (0x400A0104U) /**< \brief (USART2) Receive Counter Register */ +#define REG_USART2_TPR (0x400A0108U) /**< \brief (USART2) Transmit Pointer Register */ +#define REG_USART2_TCR (0x400A010CU) /**< \brief (USART2) Transmit Counter Register */ +#define REG_USART2_RNPR (0x400A0110U) /**< \brief (USART2) Receive Next Pointer Register */ +#define REG_USART2_RNCR (0x400A0114U) /**< \brief (USART2) Receive Next Counter Register */ +#define REG_USART2_TNPR (0x400A0118U) /**< \brief (USART2) Transmit Next Pointer Register */ +#define REG_USART2_TNCR (0x400A011CU) /**< \brief (USART2) Transmit Next Counter Register */ +#define REG_USART2_PTCR (0x400A0120U) /**< \brief (USART2) Transfer Control Register */ +#define REG_USART2_PTSR (0x400A0124U) /**< \brief (USART2) Transfer Status Register */ +#else +#define REG_USART2_CR (*(WoReg*)0x400A0000U) /**< \brief (USART2) Control Register */ +#define REG_USART2_MR (*(RwReg*)0x400A0004U) /**< \brief (USART2) Mode Register */ +#define REG_USART2_IER (*(WoReg*)0x400A0008U) /**< \brief (USART2) Interrupt Enable Register */ +#define REG_USART2_IDR (*(WoReg*)0x400A000CU) /**< \brief (USART2) Interrupt Disable Register */ +#define REG_USART2_IMR (*(RoReg*)0x400A0010U) /**< \brief (USART2) Interrupt Mask Register */ +#define REG_USART2_CSR (*(RoReg*)0x400A0014U) /**< \brief (USART2) Channel Status Register */ +#define REG_USART2_RHR (*(RoReg*)0x400A0018U) /**< \brief (USART2) Receiver Holding Register */ +#define REG_USART2_THR (*(WoReg*)0x400A001CU) /**< \brief (USART2) Transmitter Holding Register */ +#define REG_USART2_BRGR (*(RwReg*)0x400A0020U) /**< \brief (USART2) Baud Rate Generator Register */ +#define REG_USART2_RTOR (*(RwReg*)0x400A0024U) /**< \brief (USART2) Receiver Time-out Register */ +#define REG_USART2_TTGR (*(RwReg*)0x400A0028U) /**< \brief (USART2) Transmitter Timeguard Register */ +#define REG_USART2_FIDI (*(RwReg*)0x400A0040U) /**< \brief (USART2) FI DI Ratio Register */ +#define REG_USART2_NER (*(RoReg*)0x400A0044U) /**< \brief (USART2) Number of Errors Register */ +#define REG_USART2_IF (*(RwReg*)0x400A004CU) /**< \brief (USART2) IrDA Filter Register */ +#define REG_USART2_MAN (*(RwReg*)0x400A0050U) /**< \brief (USART2) Manchester Encoder Decoder Register */ +#define REG_USART2_LINMR (*(RwReg*)0x400A0054U) /**< \brief (USART2) LIN Mode Register */ +#define REG_USART2_LINIR (*(RwReg*)0x400A0058U) /**< \brief (USART2) LIN Identifier Register */ +#define REG_USART2_WPMR (*(RwReg*)0x400A00E4U) /**< \brief (USART2) Write Protect Mode Register */ +#define REG_USART2_WPSR (*(RoReg*)0x400A00E8U) /**< \brief (USART2) Write Protect Status Register */ +#define REG_USART2_RPR (*(RwReg*)0x400A0100U) /**< \brief (USART2) Receive Pointer Register */ +#define REG_USART2_RCR (*(RwReg*)0x400A0104U) /**< \brief (USART2) Receive Counter Register */ +#define REG_USART2_TPR (*(RwReg*)0x400A0108U) /**< \brief (USART2) Transmit Pointer Register */ +#define REG_USART2_TCR (*(RwReg*)0x400A010CU) /**< \brief (USART2) Transmit Counter Register */ +#define REG_USART2_RNPR (*(RwReg*)0x400A0110U) /**< \brief (USART2) Receive Next Pointer Register */ +#define REG_USART2_RNCR (*(RwReg*)0x400A0114U) /**< \brief (USART2) Receive Next Counter Register */ +#define REG_USART2_TNPR (*(RwReg*)0x400A0118U) /**< \brief (USART2) Transmit Next Pointer Register */ +#define REG_USART2_TNCR (*(RwReg*)0x400A011CU) /**< \brief (USART2) Transmit Next Counter Register */ +#define REG_USART2_PTCR (*(WoReg*)0x400A0120U) /**< \brief (USART2) Transfer Control Register */ +#define REG_USART2_PTSR (*(RoReg*)0x400A0124U) /**< \brief (USART2) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_USART2_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h new file mode 100644 index 0000000..7d76a67 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h
@@ -0,0 +1,108 @@ +/** + * \file + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM3XA_USART3_INSTANCE_ +#define _SAM3XA_USART3_INSTANCE_ + +/* ========== Register definition for USART3 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_USART3_CR (0x400A4000U) /**< \brief (USART3) Control Register */ +#define REG_USART3_MR (0x400A4004U) /**< \brief (USART3) Mode Register */ +#define REG_USART3_IER (0x400A4008U) /**< \brief (USART3) Interrupt Enable Register */ +#define REG_USART3_IDR (0x400A400CU) /**< \brief (USART3) Interrupt Disable Register */ +#define REG_USART3_IMR (0x400A4010U) /**< \brief (USART3) Interrupt Mask Register */ +#define REG_USART3_CSR (0x400A4014U) /**< \brief (USART3) Channel Status Register */ +#define REG_USART3_RHR (0x400A4018U) /**< \brief (USART3) Receiver Holding Register */ +#define REG_USART3_THR (0x400A401CU) /**< \brief (USART3) Transmitter Holding Register */ +#define REG_USART3_BRGR (0x400A4020U) /**< \brief (USART3) Baud Rate Generator Register */ +#define REG_USART3_RTOR (0x400A4024U) /**< \brief (USART3) Receiver Time-out Register */ +#define REG_USART3_TTGR (0x400A4028U) /**< \brief (USART3) Transmitter Timeguard Register */ +#define REG_USART3_FIDI (0x400A4040U) /**< \brief (USART3) FI DI Ratio Register */ +#define REG_USART3_NER (0x400A4044U) /**< \brief (USART3) Number of Errors Register */ +#define REG_USART3_IF (0x400A404CU) /**< \brief (USART3) IrDA Filter Register */ +#define REG_USART3_MAN (0x400A4050U) /**< \brief (USART3) Manchester Encoder Decoder Register */ +#define REG_USART3_LINMR (0x400A4054U) /**< \brief (USART3) LIN Mode Register */ +#define REG_USART3_LINIR (0x400A4058U) /**< \brief (USART3) LIN Identifier Register */ +#define REG_USART3_WPMR (0x400A40E4U) /**< \brief (USART3) Write Protect Mode Register */ +#define REG_USART3_WPSR (0x400A40E8U) /**< \brief (USART3) Write Protect Status Register */ +#define REG_USART3_RPR (0x400A4100U) /**< \brief (USART3) Receive Pointer Register */ +#define REG_USART3_RCR (0x400A4104U) /**< \brief (USART3) Receive Counter Register */ +#define REG_USART3_TPR (0x400A4108U) /**< \brief (USART3) Transmit Pointer Register */ +#define REG_USART3_TCR (0x400A410CU) /**< \brief (USART3) Transmit Counter Register */ +#define REG_USART3_RNPR (0x400A4110U) /**< \brief (USART3) Receive Next Pointer Register */ +#define REG_USART3_RNCR (0x400A4114U) /**< \brief (USART3) Receive Next Counter Register */ +#define REG_USART3_TNPR (0x400A4118U) /**< \brief (USART3) Transmit Next Pointer Register */ +#define REG_USART3_TNCR (0x400A411CU) /**< \brief (USART3) Transmit Next Counter Register */ +#define REG_USART3_PTCR (0x400A4120U) /**< \brief (USART3) Transfer Control Register */ +#define REG_USART3_PTSR (0x400A4124U) /**< \brief (USART3) Transfer Status Register */ +#else +#define REG_USART3_CR (*(WoReg*)0x400A4000U) /**< \brief (USART3) Control Register */ +#define REG_USART3_MR (*(RwReg*)0x400A4004U) /**< \brief (USART3) Mode Register */ +#define REG_USART3_IER (*(WoReg*)0x400A4008U) /**< \brief (USART3) Interrupt Enable Register */ +#define REG_USART3_IDR (*(WoReg*)0x400A400CU) /**< \brief (USART3) Interrupt Disable Register */ +#define REG_USART3_IMR (*(RoReg*)0x400A4010U) /**< \brief (USART3) Interrupt Mask Register */ +#define REG_USART3_CSR (*(RoReg*)0x400A4014U) /**< \brief (USART3) Channel Status Register */ +#define REG_USART3_RHR (*(RoReg*)0x400A4018U) /**< \brief (USART3) Receiver Holding Register */ +#define REG_USART3_THR (*(WoReg*)0x400A401CU) /**< \brief (USART3) Transmitter Holding Register */ +#define REG_USART3_BRGR (*(RwReg*)0x400A4020U) /**< \brief (USART3) Baud Rate Generator Register */ +#define REG_USART3_RTOR (*(RwReg*)0x400A4024U) /**< \brief (USART3) Receiver Time-out Register */ +#define REG_USART3_TTGR (*(RwReg*)0x400A4028U) /**< \brief (USART3) Transmitter Timeguard Register */ +#define REG_USART3_FIDI (*(RwReg*)0x400A4040U) /**< \brief (USART3) FI DI Ratio Register */ +#define REG_USART3_NER (*(RoReg*)0x400A4044U) /**< \brief (USART3) Number of Errors Register */ +#define REG_USART3_IF (*(RwReg*)0x400A404CU) /**< \brief (USART3) IrDA Filter Register */ +#define REG_USART3_MAN (*(RwReg*)0x400A4050U) /**< \brief (USART3) Manchester Encoder Decoder Register */ +#define REG_USART3_LINMR (*(RwReg*)0x400A4054U) /**< \brief (USART3) LIN Mode Register */ +#define REG_USART3_LINIR (*(RwReg*)0x400A4058U) /**< \brief (USART3) LIN Identifier Register */ +#define REG_USART3_WPMR (*(RwReg*)0x400A40E4U) /**< \brief (USART3) Write Protect Mode Register */ +#define REG_USART3_WPSR (*(RoReg*)0x400A40E8U) /**< \brief (USART3) Write Protect Status Register */ +#define REG_USART3_RPR (*(RwReg*)0x400A4100U) /**< \brief (USART3) Receive Pointer Register */ +#define REG_USART3_RCR (*(RwReg*)0x400A4104U) /**< \brief (USART3) Receive Counter Register */ +#define REG_USART3_TPR (*(RwReg*)0x400A4108U) /**< \brief (USART3) Transmit Pointer Register */ +#define REG_USART3_TCR (*(RwReg*)0x400A410CU) /**< \brief (USART3) Transmit Counter Register */ +#define REG_USART3_RNPR (*(RwReg*)0x400A4110U) /**< \brief (USART3) Receive Next Pointer Register */ +#define REG_USART3_RNCR (*(RwReg*)0x400A4114U) /**< \brief (USART3) Receive Next Counter Register */ +#define REG_USART3_TNPR (*(RwReg*)0x400A4118U) /**< \brief (USART3) Transmit Next Pointer Register */ +#define REG_USART3_TNCR (*(RwReg*)0x400A411CU) /**< \brief (USART3) Transmit Next Counter Register */ +#define REG_USART3_PTCR (*(WoReg*)0x400A4120U) /**< \brief (USART3) Transfer Control Register */ +#define REG_USART3_PTSR (*(RoReg*)0x400A4124U) /**< \brief (USART3) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_USART3_INSTANCE_ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h new file mode 100644 index 0000000..4ab94ca --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h
@@ -0,0 +1,56 @@ +/** + * \file + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM3XA_WDT_INSTANCE_ +#define _SAM3XA_WDT_INSTANCE_ + +/* ========== Register definition for WDT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_WDT_CR (0x400E1A50U) /**< \brief (WDT) Control Register */ +#define REG_WDT_MR (0x400E1A54U) /**< \brief (WDT) Mode Register */ +#define REG_WDT_SR (0x400E1A58U) /**< \brief (WDT) Status Register */ +#else +#define REG_WDT_CR (*(WoReg*)0x400E1A50U) /**< \brief (WDT) Control Register */ +#define REG_WDT_MR (*(RwReg*)0x400E1A54U) /**< \brief (WDT) Mode Register */ +#define REG_WDT_SR (*(RoReg*)0x400E1A58U) /**< \brief (WDT) Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_WDT_INSTANCE_ */